Commit | Line | Data |
---|---|---|
a66098da | 1 | /* |
ce9e2e1b LB |
2 | * drivers/net/wireless/mwl8k.c |
3 | * Driver for Marvell TOPDOG 802.11 Wireless cards | |
a66098da | 4 | * |
a145d575 | 5 | * Copyright (C) 2008-2009 Marvell Semiconductor Inc. |
a66098da LB |
6 | * |
7 | * This file is licensed under the terms of the GNU General Public | |
8 | * License version 2. This program is licensed "as is" without any | |
9 | * warranty of any kind, whether express or implied. | |
10 | */ | |
11 | ||
12 | #include <linux/init.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/kernel.h> | |
3d76e82c | 15 | #include <linux/sched.h> |
a66098da LB |
16 | #include <linux/spinlock.h> |
17 | #include <linux/list.h> | |
18 | #include <linux/pci.h> | |
19 | #include <linux/delay.h> | |
20 | #include <linux/completion.h> | |
21 | #include <linux/etherdevice.h> | |
22 | #include <net/mac80211.h> | |
23 | #include <linux/moduleparam.h> | |
24 | #include <linux/firmware.h> | |
25 | #include <linux/workqueue.h> | |
26 | ||
27 | #define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver" | |
28 | #define MWL8K_NAME KBUILD_MODNAME | |
6976b665 | 29 | #define MWL8K_VERSION "0.11" |
a66098da | 30 | |
a66098da LB |
31 | /* Register definitions */ |
32 | #define MWL8K_HIU_GEN_PTR 0x00000c10 | |
ce9e2e1b LB |
33 | #define MWL8K_MODE_STA 0x0000005a |
34 | #define MWL8K_MODE_AP 0x000000a5 | |
a66098da | 35 | #define MWL8K_HIU_INT_CODE 0x00000c14 |
ce9e2e1b LB |
36 | #define MWL8K_FWSTA_READY 0xf0f1f2f4 |
37 | #define MWL8K_FWAP_READY 0xf1f2f4a5 | |
38 | #define MWL8K_INT_CODE_CMD_FINISHED 0x00000005 | |
a66098da LB |
39 | #define MWL8K_HIU_SCRATCH 0x00000c40 |
40 | ||
41 | /* Host->device communications */ | |
42 | #define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18 | |
43 | #define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c | |
44 | #define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20 | |
45 | #define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24 | |
46 | #define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28 | |
ce9e2e1b LB |
47 | #define MWL8K_H2A_INT_DUMMY (1 << 20) |
48 | #define MWL8K_H2A_INT_RESET (1 << 15) | |
49 | #define MWL8K_H2A_INT_DOORBELL (1 << 1) | |
50 | #define MWL8K_H2A_INT_PPA_READY (1 << 0) | |
a66098da LB |
51 | |
52 | /* Device->host communications */ | |
53 | #define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c | |
54 | #define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30 | |
55 | #define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34 | |
56 | #define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38 | |
57 | #define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c | |
ce9e2e1b LB |
58 | #define MWL8K_A2H_INT_DUMMY (1 << 20) |
59 | #define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11) | |
60 | #define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10) | |
61 | #define MWL8K_A2H_INT_RADAR_DETECT (1 << 7) | |
62 | #define MWL8K_A2H_INT_RADIO_ON (1 << 6) | |
63 | #define MWL8K_A2H_INT_RADIO_OFF (1 << 5) | |
64 | #define MWL8K_A2H_INT_MAC_EVENT (1 << 3) | |
65 | #define MWL8K_A2H_INT_OPC_DONE (1 << 2) | |
66 | #define MWL8K_A2H_INT_RX_READY (1 << 1) | |
67 | #define MWL8K_A2H_INT_TX_DONE (1 << 0) | |
a66098da LB |
68 | |
69 | #define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \ | |
70 | MWL8K_A2H_INT_CHNL_SWITCHED | \ | |
71 | MWL8K_A2H_INT_QUEUE_EMPTY | \ | |
72 | MWL8K_A2H_INT_RADAR_DETECT | \ | |
73 | MWL8K_A2H_INT_RADIO_ON | \ | |
74 | MWL8K_A2H_INT_RADIO_OFF | \ | |
75 | MWL8K_A2H_INT_MAC_EVENT | \ | |
76 | MWL8K_A2H_INT_OPC_DONE | \ | |
77 | MWL8K_A2H_INT_RX_READY | \ | |
78 | MWL8K_A2H_INT_TX_DONE) | |
79 | ||
a66098da LB |
80 | #define MWL8K_RX_QUEUES 1 |
81 | #define MWL8K_TX_QUEUES 4 | |
82 | ||
54bc3a0d LB |
83 | struct rxd_ops { |
84 | int rxd_size; | |
85 | void (*rxd_init)(void *rxd, dma_addr_t next_dma_addr); | |
86 | void (*rxd_refill)(void *rxd, dma_addr_t addr, int len); | |
20f09c3d LB |
87 | int (*rxd_process)(void *rxd, struct ieee80211_rx_status *status, |
88 | __le16 *qos); | |
54bc3a0d LB |
89 | }; |
90 | ||
45a390dd | 91 | struct mwl8k_device_info { |
a74b295e LB |
92 | char *part_name; |
93 | char *helper_image; | |
94 | char *fw_image; | |
89a91f4f | 95 | struct rxd_ops *ap_rxd_ops; |
45a390dd LB |
96 | }; |
97 | ||
a66098da | 98 | struct mwl8k_rx_queue { |
45eb400d | 99 | int rxd_count; |
a66098da LB |
100 | |
101 | /* hw receives here */ | |
45eb400d | 102 | int head; |
a66098da LB |
103 | |
104 | /* refill descs here */ | |
45eb400d | 105 | int tail; |
a66098da | 106 | |
54bc3a0d | 107 | void *rxd; |
45eb400d | 108 | dma_addr_t rxd_dma; |
788838eb LB |
109 | struct { |
110 | struct sk_buff *skb; | |
111 | DECLARE_PCI_UNMAP_ADDR(dma) | |
112 | } *buf; | |
a66098da LB |
113 | }; |
114 | ||
a66098da LB |
115 | struct mwl8k_tx_queue { |
116 | /* hw transmits here */ | |
45eb400d | 117 | int head; |
a66098da LB |
118 | |
119 | /* sw appends here */ | |
45eb400d | 120 | int tail; |
a66098da | 121 | |
45eb400d LB |
122 | struct ieee80211_tx_queue_stats stats; |
123 | struct mwl8k_tx_desc *txd; | |
124 | dma_addr_t txd_dma; | |
125 | struct sk_buff **skb; | |
a66098da LB |
126 | }; |
127 | ||
a66098da | 128 | struct mwl8k_priv { |
a66098da | 129 | struct ieee80211_hw *hw; |
a66098da | 130 | struct pci_dev *pdev; |
a66098da | 131 | |
45a390dd LB |
132 | struct mwl8k_device_info *device_info; |
133 | ||
be695fc4 LB |
134 | void __iomem *sram; |
135 | void __iomem *regs; | |
136 | ||
137 | /* firmware */ | |
22be40d9 LB |
138 | struct firmware *fw_helper; |
139 | struct firmware *fw_ucode; | |
a66098da | 140 | |
be695fc4 LB |
141 | /* hardware/firmware parameters */ |
142 | bool ap_fw; | |
143 | struct rxd_ops *rxd_ops; | |
144 | ||
618952a7 LB |
145 | /* firmware access */ |
146 | struct mutex fw_mutex; | |
147 | struct task_struct *fw_mutex_owner; | |
148 | int fw_mutex_depth; | |
618952a7 LB |
149 | struct completion *hostcmd_wait; |
150 | ||
a66098da LB |
151 | /* lock held over TX and TX reap */ |
152 | spinlock_t tx_lock; | |
a66098da | 153 | |
88de754a LB |
154 | /* TX quiesce completion, protected by fw_mutex and tx_lock */ |
155 | struct completion *tx_wait; | |
156 | ||
a66098da | 157 | struct ieee80211_vif *vif; |
a66098da LB |
158 | |
159 | struct ieee80211_channel *current_channel; | |
160 | ||
161 | /* power management status cookie from firmware */ | |
162 | u32 *cookie; | |
163 | dma_addr_t cookie_dma; | |
164 | ||
165 | u16 num_mcaddrs; | |
a66098da | 166 | u8 hw_rev; |
2aa7b01f | 167 | u32 fw_rev; |
a66098da LB |
168 | |
169 | /* | |
170 | * Running count of TX packets in flight, to avoid | |
171 | * iterating over the transmit rings each time. | |
172 | */ | |
173 | int pending_tx_pkts; | |
174 | ||
175 | struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES]; | |
176 | struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES]; | |
177 | ||
178 | /* PHY parameters */ | |
179 | struct ieee80211_supported_band band; | |
180 | struct ieee80211_channel channels[14]; | |
140eb5e2 | 181 | struct ieee80211_rate rates[14]; |
a66098da | 182 | |
c46563b7 | 183 | bool radio_on; |
68ce3884 | 184 | bool radio_short_preamble; |
a43c49a8 | 185 | bool sniffer_enabled; |
0439b1f5 | 186 | bool wmm_enabled; |
a66098da | 187 | |
a66098da LB |
188 | /* XXX need to convert this to handle multiple interfaces */ |
189 | bool capture_beacon; | |
d89173f2 | 190 | u8 capture_bssid[ETH_ALEN]; |
a66098da LB |
191 | struct sk_buff *beacon_skb; |
192 | ||
193 | /* | |
194 | * This FJ worker has to be global as it is scheduled from the | |
195 | * RX handler. At this point we don't know which interface it | |
196 | * belongs to until the list of bssids waiting to complete join | |
197 | * is checked. | |
198 | */ | |
199 | struct work_struct finalize_join_worker; | |
200 | ||
201 | /* Tasklet to reclaim TX descriptors and buffers after tx */ | |
202 | struct tasklet_struct tx_reclaim_task; | |
a66098da LB |
203 | }; |
204 | ||
205 | /* Per interface specific private data */ | |
206 | struct mwl8k_vif { | |
7dc6a7a7 LB |
207 | /* Local MAC address. */ |
208 | u8 mac_addr[ETH_ALEN]; | |
a66098da | 209 | |
7dc6a7a7 LB |
210 | /* BSSID of AP. */ |
211 | u8 bssid[ETH_ALEN]; | |
a66098da | 212 | |
55489b6e | 213 | /* Index into station database. Returned by UPDATE_STADB. */ |
a66098da LB |
214 | u8 peer_id; |
215 | ||
216 | /* Non AMPDU sequence number assigned by driver */ | |
217 | u16 seqno; | |
a66098da LB |
218 | }; |
219 | ||
a94cc97e | 220 | #define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv)) |
a66098da LB |
221 | |
222 | static const struct ieee80211_channel mwl8k_channels[] = { | |
223 | { .center_freq = 2412, .hw_value = 1, }, | |
224 | { .center_freq = 2417, .hw_value = 2, }, | |
225 | { .center_freq = 2422, .hw_value = 3, }, | |
226 | { .center_freq = 2427, .hw_value = 4, }, | |
227 | { .center_freq = 2432, .hw_value = 5, }, | |
228 | { .center_freq = 2437, .hw_value = 6, }, | |
229 | { .center_freq = 2442, .hw_value = 7, }, | |
230 | { .center_freq = 2447, .hw_value = 8, }, | |
231 | { .center_freq = 2452, .hw_value = 9, }, | |
232 | { .center_freq = 2457, .hw_value = 10, }, | |
233 | { .center_freq = 2462, .hw_value = 11, }, | |
647ca6b0 LB |
234 | { .center_freq = 2467, .hw_value = 12, }, |
235 | { .center_freq = 2472, .hw_value = 13, }, | |
236 | { .center_freq = 2484, .hw_value = 14, }, | |
a66098da LB |
237 | }; |
238 | ||
239 | static const struct ieee80211_rate mwl8k_rates[] = { | |
240 | { .bitrate = 10, .hw_value = 2, }, | |
241 | { .bitrate = 20, .hw_value = 4, }, | |
242 | { .bitrate = 55, .hw_value = 11, }, | |
5dfd3e2c LB |
243 | { .bitrate = 110, .hw_value = 22, }, |
244 | { .bitrate = 220, .hw_value = 44, }, | |
a66098da LB |
245 | { .bitrate = 60, .hw_value = 12, }, |
246 | { .bitrate = 90, .hw_value = 18, }, | |
a66098da LB |
247 | { .bitrate = 120, .hw_value = 24, }, |
248 | { .bitrate = 180, .hw_value = 36, }, | |
249 | { .bitrate = 240, .hw_value = 48, }, | |
250 | { .bitrate = 360, .hw_value = 72, }, | |
251 | { .bitrate = 480, .hw_value = 96, }, | |
252 | { .bitrate = 540, .hw_value = 108, }, | |
140eb5e2 LB |
253 | { .bitrate = 720, .hw_value = 144, }, |
254 | }; | |
255 | ||
256 | static const u8 mwl8k_rateids[12] = { | |
257 | 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108, | |
a66098da LB |
258 | }; |
259 | ||
a66098da LB |
260 | /* Set or get info from Firmware */ |
261 | #define MWL8K_CMD_SET 0x0001 | |
262 | #define MWL8K_CMD_GET 0x0000 | |
263 | ||
264 | /* Firmware command codes */ | |
265 | #define MWL8K_CMD_CODE_DNLD 0x0001 | |
266 | #define MWL8K_CMD_GET_HW_SPEC 0x0003 | |
42fba21d | 267 | #define MWL8K_CMD_SET_HW_SPEC 0x0004 |
a66098da LB |
268 | #define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010 |
269 | #define MWL8K_CMD_GET_STAT 0x0014 | |
ff45fc60 LB |
270 | #define MWL8K_CMD_RADIO_CONTROL 0x001c |
271 | #define MWL8K_CMD_RF_TX_POWER 0x001e | |
08b06347 | 272 | #define MWL8K_CMD_RF_ANTENNA 0x0020 |
a66098da LB |
273 | #define MWL8K_CMD_SET_PRE_SCAN 0x0107 |
274 | #define MWL8K_CMD_SET_POST_SCAN 0x0108 | |
ff45fc60 LB |
275 | #define MWL8K_CMD_SET_RF_CHANNEL 0x010a |
276 | #define MWL8K_CMD_SET_AID 0x010d | |
277 | #define MWL8K_CMD_SET_RATE 0x0110 | |
278 | #define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111 | |
279 | #define MWL8K_CMD_RTS_THRESHOLD 0x0113 | |
a66098da | 280 | #define MWL8K_CMD_SET_SLOT 0x0114 |
ff45fc60 LB |
281 | #define MWL8K_CMD_SET_EDCA_PARAMS 0x0115 |
282 | #define MWL8K_CMD_SET_WMM_MODE 0x0123 | |
a66098da | 283 | #define MWL8K_CMD_MIMO_CONFIG 0x0125 |
ff45fc60 | 284 | #define MWL8K_CMD_USE_FIXED_RATE 0x0126 |
a66098da | 285 | #define MWL8K_CMD_ENABLE_SNIFFER 0x0150 |
32060e1b | 286 | #define MWL8K_CMD_SET_MAC_ADDR 0x0202 |
a66098da | 287 | #define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203 |
ff45fc60 | 288 | #define MWL8K_CMD_UPDATE_STADB 0x1123 |
a66098da LB |
289 | |
290 | static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize) | |
291 | { | |
292 | #define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\ | |
293 | snprintf(buf, bufsize, "%s", #x);\ | |
294 | return buf;\ | |
295 | } while (0) | |
ce9e2e1b | 296 | switch (cmd & ~0x8000) { |
a66098da LB |
297 | MWL8K_CMDNAME(CODE_DNLD); |
298 | MWL8K_CMDNAME(GET_HW_SPEC); | |
42fba21d | 299 | MWL8K_CMDNAME(SET_HW_SPEC); |
a66098da LB |
300 | MWL8K_CMDNAME(MAC_MULTICAST_ADR); |
301 | MWL8K_CMDNAME(GET_STAT); | |
302 | MWL8K_CMDNAME(RADIO_CONTROL); | |
303 | MWL8K_CMDNAME(RF_TX_POWER); | |
08b06347 | 304 | MWL8K_CMDNAME(RF_ANTENNA); |
a66098da LB |
305 | MWL8K_CMDNAME(SET_PRE_SCAN); |
306 | MWL8K_CMDNAME(SET_POST_SCAN); | |
307 | MWL8K_CMDNAME(SET_RF_CHANNEL); | |
ff45fc60 LB |
308 | MWL8K_CMDNAME(SET_AID); |
309 | MWL8K_CMDNAME(SET_RATE); | |
310 | MWL8K_CMDNAME(SET_FINALIZE_JOIN); | |
311 | MWL8K_CMDNAME(RTS_THRESHOLD); | |
a66098da | 312 | MWL8K_CMDNAME(SET_SLOT); |
ff45fc60 LB |
313 | MWL8K_CMDNAME(SET_EDCA_PARAMS); |
314 | MWL8K_CMDNAME(SET_WMM_MODE); | |
a66098da | 315 | MWL8K_CMDNAME(MIMO_CONFIG); |
ff45fc60 | 316 | MWL8K_CMDNAME(USE_FIXED_RATE); |
a66098da | 317 | MWL8K_CMDNAME(ENABLE_SNIFFER); |
32060e1b | 318 | MWL8K_CMDNAME(SET_MAC_ADDR); |
a66098da | 319 | MWL8K_CMDNAME(SET_RATEADAPT_MODE); |
ff45fc60 | 320 | MWL8K_CMDNAME(UPDATE_STADB); |
a66098da LB |
321 | default: |
322 | snprintf(buf, bufsize, "0x%x", cmd); | |
323 | } | |
324 | #undef MWL8K_CMDNAME | |
325 | ||
326 | return buf; | |
327 | } | |
328 | ||
329 | /* Hardware and firmware reset */ | |
330 | static void mwl8k_hw_reset(struct mwl8k_priv *priv) | |
331 | { | |
332 | iowrite32(MWL8K_H2A_INT_RESET, | |
333 | priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); | |
334 | iowrite32(MWL8K_H2A_INT_RESET, | |
335 | priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); | |
336 | msleep(20); | |
337 | } | |
338 | ||
339 | /* Release fw image */ | |
340 | static void mwl8k_release_fw(struct firmware **fw) | |
341 | { | |
342 | if (*fw == NULL) | |
343 | return; | |
344 | release_firmware(*fw); | |
345 | *fw = NULL; | |
346 | } | |
347 | ||
348 | static void mwl8k_release_firmware(struct mwl8k_priv *priv) | |
349 | { | |
22be40d9 LB |
350 | mwl8k_release_fw(&priv->fw_ucode); |
351 | mwl8k_release_fw(&priv->fw_helper); | |
a66098da LB |
352 | } |
353 | ||
354 | /* Request fw image */ | |
355 | static int mwl8k_request_fw(struct mwl8k_priv *priv, | |
c2c357ce | 356 | const char *fname, struct firmware **fw) |
a66098da LB |
357 | { |
358 | /* release current image */ | |
359 | if (*fw != NULL) | |
360 | mwl8k_release_fw(fw); | |
361 | ||
362 | return request_firmware((const struct firmware **)fw, | |
c2c357ce | 363 | fname, &priv->pdev->dev); |
a66098da LB |
364 | } |
365 | ||
45a390dd | 366 | static int mwl8k_request_firmware(struct mwl8k_priv *priv) |
a66098da | 367 | { |
a74b295e | 368 | struct mwl8k_device_info *di = priv->device_info; |
a66098da LB |
369 | int rc; |
370 | ||
a74b295e | 371 | if (di->helper_image != NULL) { |
22be40d9 | 372 | rc = mwl8k_request_fw(priv, di->helper_image, &priv->fw_helper); |
a74b295e LB |
373 | if (rc) { |
374 | printk(KERN_ERR "%s: Error requesting helper " | |
375 | "firmware file %s\n", pci_name(priv->pdev), | |
376 | di->helper_image); | |
377 | return rc; | |
378 | } | |
a66098da LB |
379 | } |
380 | ||
22be40d9 | 381 | rc = mwl8k_request_fw(priv, di->fw_image, &priv->fw_ucode); |
a66098da | 382 | if (rc) { |
c2c357ce | 383 | printk(KERN_ERR "%s: Error requesting firmware file %s\n", |
a74b295e | 384 | pci_name(priv->pdev), di->fw_image); |
22be40d9 | 385 | mwl8k_release_fw(&priv->fw_helper); |
a66098da LB |
386 | return rc; |
387 | } | |
388 | ||
389 | return 0; | |
390 | } | |
391 | ||
7e75b942 BH |
392 | MODULE_FIRMWARE("mwl8k/helper_8687.fw"); |
393 | MODULE_FIRMWARE("mwl8k/fmimage_8687.fw"); | |
394 | ||
a66098da LB |
395 | struct mwl8k_cmd_pkt { |
396 | __le16 code; | |
397 | __le16 length; | |
398 | __le16 seq_num; | |
399 | __le16 result; | |
400 | char payload[0]; | |
401 | } __attribute__((packed)); | |
402 | ||
403 | /* | |
404 | * Firmware loading. | |
405 | */ | |
406 | static int | |
407 | mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length) | |
408 | { | |
409 | void __iomem *regs = priv->regs; | |
410 | dma_addr_t dma_addr; | |
a66098da LB |
411 | int loops; |
412 | ||
413 | dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE); | |
414 | if (pci_dma_mapping_error(priv->pdev, dma_addr)) | |
415 | return -ENOMEM; | |
416 | ||
417 | iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR); | |
418 | iowrite32(0, regs + MWL8K_HIU_INT_CODE); | |
419 | iowrite32(MWL8K_H2A_INT_DOORBELL, | |
420 | regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); | |
421 | iowrite32(MWL8K_H2A_INT_DUMMY, | |
422 | regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); | |
423 | ||
a66098da LB |
424 | loops = 1000; |
425 | do { | |
426 | u32 int_code; | |
427 | ||
428 | int_code = ioread32(regs + MWL8K_HIU_INT_CODE); | |
429 | if (int_code == MWL8K_INT_CODE_CMD_FINISHED) { | |
430 | iowrite32(0, regs + MWL8K_HIU_INT_CODE); | |
a66098da LB |
431 | break; |
432 | } | |
433 | ||
3d76e82c | 434 | cond_resched(); |
a66098da LB |
435 | udelay(1); |
436 | } while (--loops); | |
437 | ||
438 | pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE); | |
439 | ||
d4b70570 | 440 | return loops ? 0 : -ETIMEDOUT; |
a66098da LB |
441 | } |
442 | ||
443 | static int mwl8k_load_fw_image(struct mwl8k_priv *priv, | |
444 | const u8 *data, size_t length) | |
445 | { | |
446 | struct mwl8k_cmd_pkt *cmd; | |
447 | int done; | |
448 | int rc = 0; | |
449 | ||
450 | cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL); | |
451 | if (cmd == NULL) | |
452 | return -ENOMEM; | |
453 | ||
454 | cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD); | |
455 | cmd->seq_num = 0; | |
456 | cmd->result = 0; | |
457 | ||
458 | done = 0; | |
459 | while (length) { | |
460 | int block_size = length > 256 ? 256 : length; | |
461 | ||
462 | memcpy(cmd->payload, data + done, block_size); | |
463 | cmd->length = cpu_to_le16(block_size); | |
464 | ||
465 | rc = mwl8k_send_fw_load_cmd(priv, cmd, | |
466 | sizeof(*cmd) + block_size); | |
467 | if (rc) | |
468 | break; | |
469 | ||
470 | done += block_size; | |
471 | length -= block_size; | |
472 | } | |
473 | ||
474 | if (!rc) { | |
475 | cmd->length = 0; | |
476 | rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd)); | |
477 | } | |
478 | ||
479 | kfree(cmd); | |
480 | ||
481 | return rc; | |
482 | } | |
483 | ||
484 | static int mwl8k_feed_fw_image(struct mwl8k_priv *priv, | |
485 | const u8 *data, size_t length) | |
486 | { | |
487 | unsigned char *buffer; | |
488 | int may_continue, rc = 0; | |
489 | u32 done, prev_block_size; | |
490 | ||
491 | buffer = kmalloc(1024, GFP_KERNEL); | |
492 | if (buffer == NULL) | |
493 | return -ENOMEM; | |
494 | ||
495 | done = 0; | |
496 | prev_block_size = 0; | |
497 | may_continue = 1000; | |
498 | while (may_continue > 0) { | |
499 | u32 block_size; | |
500 | ||
501 | block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH); | |
502 | if (block_size & 1) { | |
503 | block_size &= ~1; | |
504 | may_continue--; | |
505 | } else { | |
506 | done += prev_block_size; | |
507 | length -= prev_block_size; | |
508 | } | |
509 | ||
510 | if (block_size > 1024 || block_size > length) { | |
511 | rc = -EOVERFLOW; | |
512 | break; | |
513 | } | |
514 | ||
515 | if (length == 0) { | |
516 | rc = 0; | |
517 | break; | |
518 | } | |
519 | ||
520 | if (block_size == 0) { | |
521 | rc = -EPROTO; | |
522 | may_continue--; | |
523 | udelay(1); | |
524 | continue; | |
525 | } | |
526 | ||
527 | prev_block_size = block_size; | |
528 | memcpy(buffer, data + done, block_size); | |
529 | ||
530 | rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size); | |
531 | if (rc) | |
532 | break; | |
533 | } | |
534 | ||
535 | if (!rc && length != 0) | |
536 | rc = -EREMOTEIO; | |
537 | ||
538 | kfree(buffer); | |
539 | ||
540 | return rc; | |
541 | } | |
542 | ||
c2c357ce | 543 | static int mwl8k_load_firmware(struct ieee80211_hw *hw) |
a66098da | 544 | { |
c2c357ce | 545 | struct mwl8k_priv *priv = hw->priv; |
22be40d9 | 546 | struct firmware *fw = priv->fw_ucode; |
c2c357ce LB |
547 | int rc; |
548 | int loops; | |
549 | ||
550 | if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) { | |
22be40d9 | 551 | struct firmware *helper = priv->fw_helper; |
a66098da | 552 | |
c2c357ce LB |
553 | if (helper == NULL) { |
554 | printk(KERN_ERR "%s: helper image needed but none " | |
555 | "given\n", pci_name(priv->pdev)); | |
556 | return -EINVAL; | |
557 | } | |
a66098da | 558 | |
c2c357ce | 559 | rc = mwl8k_load_fw_image(priv, helper->data, helper->size); |
a66098da LB |
560 | if (rc) { |
561 | printk(KERN_ERR "%s: unable to load firmware " | |
c2c357ce | 562 | "helper image\n", pci_name(priv->pdev)); |
a66098da LB |
563 | return rc; |
564 | } | |
89b872e2 | 565 | msleep(5); |
a66098da | 566 | |
c2c357ce | 567 | rc = mwl8k_feed_fw_image(priv, fw->data, fw->size); |
a66098da | 568 | } else { |
c2c357ce | 569 | rc = mwl8k_load_fw_image(priv, fw->data, fw->size); |
a66098da LB |
570 | } |
571 | ||
572 | if (rc) { | |
c2c357ce LB |
573 | printk(KERN_ERR "%s: unable to load firmware image\n", |
574 | pci_name(priv->pdev)); | |
a66098da LB |
575 | return rc; |
576 | } | |
577 | ||
89a91f4f | 578 | iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR); |
a66098da | 579 | |
89b872e2 | 580 | loops = 500000; |
a66098da | 581 | do { |
eae74e65 LB |
582 | u32 ready_code; |
583 | ||
584 | ready_code = ioread32(priv->regs + MWL8K_HIU_INT_CODE); | |
585 | if (ready_code == MWL8K_FWAP_READY) { | |
586 | priv->ap_fw = 1; | |
587 | break; | |
588 | } else if (ready_code == MWL8K_FWSTA_READY) { | |
589 | priv->ap_fw = 0; | |
a66098da | 590 | break; |
eae74e65 LB |
591 | } |
592 | ||
593 | cond_resched(); | |
a66098da LB |
594 | udelay(1); |
595 | } while (--loops); | |
596 | ||
597 | return loops ? 0 : -ETIMEDOUT; | |
598 | } | |
599 | ||
600 | ||
601 | /* | |
602 | * Defines shared between transmission and reception. | |
603 | */ | |
604 | /* HT control fields for firmware */ | |
605 | struct ewc_ht_info { | |
606 | __le16 control1; | |
607 | __le16 control2; | |
608 | __le16 control3; | |
609 | } __attribute__((packed)); | |
610 | ||
611 | /* Firmware Station database operations */ | |
612 | #define MWL8K_STA_DB_ADD_ENTRY 0 | |
613 | #define MWL8K_STA_DB_MODIFY_ENTRY 1 | |
614 | #define MWL8K_STA_DB_DEL_ENTRY 2 | |
615 | #define MWL8K_STA_DB_FLUSH 3 | |
616 | ||
617 | /* Peer Entry flags - used to define the type of the peer node */ | |
618 | #define MWL8K_PEER_TYPE_ACCESSPOINT 2 | |
a66098da | 619 | |
a66098da LB |
620 | struct peer_capability_info { |
621 | /* Peer type - AP vs. STA. */ | |
622 | __u8 peer_type; | |
623 | ||
624 | /* Basic 802.11 capabilities from assoc resp. */ | |
625 | __le16 basic_caps; | |
626 | ||
627 | /* Set if peer supports 802.11n high throughput (HT). */ | |
628 | __u8 ht_support; | |
629 | ||
630 | /* Valid if HT is supported. */ | |
631 | __le16 ht_caps; | |
632 | __u8 extended_ht_caps; | |
633 | struct ewc_ht_info ewc_info; | |
634 | ||
635 | /* Legacy rate table. Intersection of our rates and peer rates. */ | |
140eb5e2 | 636 | __u8 legacy_rates[12]; |
a66098da LB |
637 | |
638 | /* HT rate table. Intersection of our rates and peer rates. */ | |
0b5351a8 | 639 | __u8 ht_rates[16]; |
c23b5a69 | 640 | __u8 pad[16]; |
a66098da LB |
641 | |
642 | /* If set, interoperability mode, no proprietary extensions. */ | |
643 | __u8 interop; | |
644 | __u8 pad2; | |
645 | __u8 station_id; | |
646 | __le16 amsdu_enabled; | |
647 | } __attribute__((packed)); | |
648 | ||
a66098da LB |
649 | /* DMA header used by firmware and hardware. */ |
650 | struct mwl8k_dma_data { | |
651 | __le16 fwlen; | |
652 | struct ieee80211_hdr wh; | |
20f09c3d | 653 | char data[0]; |
a66098da LB |
654 | } __attribute__((packed)); |
655 | ||
656 | /* Routines to add/remove DMA header from skb. */ | |
20f09c3d | 657 | static inline void mwl8k_remove_dma_header(struct sk_buff *skb, __le16 qos) |
a66098da | 658 | { |
20f09c3d LB |
659 | struct mwl8k_dma_data *tr; |
660 | int hdrlen; | |
661 | ||
662 | tr = (struct mwl8k_dma_data *)skb->data; | |
663 | hdrlen = ieee80211_hdrlen(tr->wh.frame_control); | |
664 | ||
665 | if (hdrlen != sizeof(tr->wh)) { | |
666 | if (ieee80211_is_data_qos(tr->wh.frame_control)) { | |
667 | memmove(tr->data - hdrlen, &tr->wh, hdrlen - 2); | |
668 | *((__le16 *)(tr->data - 2)) = qos; | |
669 | } else { | |
670 | memmove(tr->data - hdrlen, &tr->wh, hdrlen); | |
671 | } | |
a66098da | 672 | } |
20f09c3d LB |
673 | |
674 | if (hdrlen != sizeof(*tr)) | |
675 | skb_pull(skb, sizeof(*tr) - hdrlen); | |
a66098da LB |
676 | } |
677 | ||
76266b2a | 678 | static inline void mwl8k_add_dma_header(struct sk_buff *skb) |
a66098da LB |
679 | { |
680 | struct ieee80211_hdr *wh; | |
ca009301 | 681 | int hdrlen; |
a66098da LB |
682 | struct mwl8k_dma_data *tr; |
683 | ||
ca009301 LB |
684 | /* |
685 | * Add a firmware DMA header; the firmware requires that we | |
686 | * present a 2-byte payload length followed by a 4-address | |
687 | * header (without QoS field), followed (optionally) by any | |
688 | * WEP/ExtIV header (but only filled in for CCMP). | |
689 | */ | |
a66098da | 690 | wh = (struct ieee80211_hdr *)skb->data; |
ca009301 | 691 | |
a66098da | 692 | hdrlen = ieee80211_hdrlen(wh->frame_control); |
ca009301 LB |
693 | if (hdrlen != sizeof(*tr)) |
694 | skb_push(skb, sizeof(*tr) - hdrlen); | |
a66098da | 695 | |
ca009301 LB |
696 | if (ieee80211_is_data_qos(wh->frame_control)) |
697 | hdrlen -= 2; | |
a66098da LB |
698 | |
699 | tr = (struct mwl8k_dma_data *)skb->data; | |
700 | if (wh != &tr->wh) | |
701 | memmove(&tr->wh, wh, hdrlen); | |
ca009301 LB |
702 | if (hdrlen != sizeof(tr->wh)) |
703 | memset(((void *)&tr->wh) + hdrlen, 0, sizeof(tr->wh) - hdrlen); | |
a66098da LB |
704 | |
705 | /* | |
706 | * Firmware length is the length of the fully formed "802.11 | |
707 | * payload". That is, everything except for the 802.11 header. | |
708 | * This includes all crypto material including the MIC. | |
709 | */ | |
ca009301 | 710 | tr->fwlen = cpu_to_le16(skb->len - sizeof(*tr)); |
a66098da LB |
711 | } |
712 | ||
713 | ||
714 | /* | |
89a91f4f | 715 | * Packet reception for 88w8366 AP firmware. |
6f6d1e9a | 716 | */ |
89a91f4f | 717 | struct mwl8k_rxd_8366_ap { |
6f6d1e9a LB |
718 | __le16 pkt_len; |
719 | __u8 sq2; | |
720 | __u8 rate; | |
721 | __le32 pkt_phys_addr; | |
722 | __le32 next_rxd_phys_addr; | |
723 | __le16 qos_control; | |
724 | __le16 htsig2; | |
725 | __le32 hw_rssi_info; | |
726 | __le32 hw_noise_floor_info; | |
727 | __u8 noise_floor; | |
728 | __u8 pad0[3]; | |
729 | __u8 rssi; | |
730 | __u8 rx_status; | |
731 | __u8 channel; | |
732 | __u8 rx_ctrl; | |
733 | } __attribute__((packed)); | |
734 | ||
89a91f4f LB |
735 | #define MWL8K_8366_AP_RATE_INFO_MCS_FORMAT 0x80 |
736 | #define MWL8K_8366_AP_RATE_INFO_40MHZ 0x40 | |
737 | #define MWL8K_8366_AP_RATE_INFO_RATEID(x) ((x) & 0x3f) | |
8e9f33f0 | 738 | |
89a91f4f | 739 | #define MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST 0x80 |
6f6d1e9a | 740 | |
89a91f4f | 741 | static void mwl8k_rxd_8366_ap_init(void *_rxd, dma_addr_t next_dma_addr) |
6f6d1e9a | 742 | { |
89a91f4f | 743 | struct mwl8k_rxd_8366_ap *rxd = _rxd; |
6f6d1e9a LB |
744 | |
745 | rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr); | |
89a91f4f | 746 | rxd->rx_ctrl = MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST; |
6f6d1e9a LB |
747 | } |
748 | ||
89a91f4f | 749 | static void mwl8k_rxd_8366_ap_refill(void *_rxd, dma_addr_t addr, int len) |
6f6d1e9a | 750 | { |
89a91f4f | 751 | struct mwl8k_rxd_8366_ap *rxd = _rxd; |
6f6d1e9a LB |
752 | |
753 | rxd->pkt_len = cpu_to_le16(len); | |
754 | rxd->pkt_phys_addr = cpu_to_le32(addr); | |
755 | wmb(); | |
756 | rxd->rx_ctrl = 0; | |
757 | } | |
758 | ||
759 | static int | |
89a91f4f LB |
760 | mwl8k_rxd_8366_ap_process(void *_rxd, struct ieee80211_rx_status *status, |
761 | __le16 *qos) | |
6f6d1e9a | 762 | { |
89a91f4f | 763 | struct mwl8k_rxd_8366_ap *rxd = _rxd; |
6f6d1e9a | 764 | |
89a91f4f | 765 | if (!(rxd->rx_ctrl & MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST)) |
6f6d1e9a LB |
766 | return -1; |
767 | rmb(); | |
768 | ||
769 | memset(status, 0, sizeof(*status)); | |
770 | ||
771 | status->signal = -rxd->rssi; | |
772 | status->noise = -rxd->noise_floor; | |
773 | ||
89a91f4f | 774 | if (rxd->rate & MWL8K_8366_AP_RATE_INFO_MCS_FORMAT) { |
6f6d1e9a | 775 | status->flag |= RX_FLAG_HT; |
89a91f4f | 776 | if (rxd->rate & MWL8K_8366_AP_RATE_INFO_40MHZ) |
8e9f33f0 | 777 | status->flag |= RX_FLAG_40MHZ; |
89a91f4f | 778 | status->rate_idx = MWL8K_8366_AP_RATE_INFO_RATEID(rxd->rate); |
6f6d1e9a LB |
779 | } else { |
780 | int i; | |
781 | ||
782 | for (i = 0; i < ARRAY_SIZE(mwl8k_rates); i++) { | |
783 | if (mwl8k_rates[i].hw_value == rxd->rate) { | |
784 | status->rate_idx = i; | |
785 | break; | |
786 | } | |
787 | } | |
788 | } | |
789 | ||
790 | status->band = IEEE80211_BAND_2GHZ; | |
791 | status->freq = ieee80211_channel_to_frequency(rxd->channel); | |
792 | ||
20f09c3d LB |
793 | *qos = rxd->qos_control; |
794 | ||
6f6d1e9a LB |
795 | return le16_to_cpu(rxd->pkt_len); |
796 | } | |
797 | ||
89a91f4f LB |
798 | static struct rxd_ops rxd_8366_ap_ops = { |
799 | .rxd_size = sizeof(struct mwl8k_rxd_8366_ap), | |
800 | .rxd_init = mwl8k_rxd_8366_ap_init, | |
801 | .rxd_refill = mwl8k_rxd_8366_ap_refill, | |
802 | .rxd_process = mwl8k_rxd_8366_ap_process, | |
6f6d1e9a LB |
803 | }; |
804 | ||
805 | /* | |
89a91f4f | 806 | * Packet reception for STA firmware. |
a66098da | 807 | */ |
89a91f4f | 808 | struct mwl8k_rxd_sta { |
a66098da LB |
809 | __le16 pkt_len; |
810 | __u8 link_quality; | |
811 | __u8 noise_level; | |
812 | __le32 pkt_phys_addr; | |
45eb400d | 813 | __le32 next_rxd_phys_addr; |
a66098da LB |
814 | __le16 qos_control; |
815 | __le16 rate_info; | |
816 | __le32 pad0[4]; | |
817 | __u8 rssi; | |
818 | __u8 channel; | |
819 | __le16 pad1; | |
820 | __u8 rx_ctrl; | |
821 | __u8 rx_status; | |
822 | __u8 pad2[2]; | |
823 | } __attribute__((packed)); | |
824 | ||
89a91f4f LB |
825 | #define MWL8K_STA_RATE_INFO_SHORTPRE 0x8000 |
826 | #define MWL8K_STA_RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3) | |
827 | #define MWL8K_STA_RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f) | |
828 | #define MWL8K_STA_RATE_INFO_40MHZ 0x0004 | |
829 | #define MWL8K_STA_RATE_INFO_SHORTGI 0x0002 | |
830 | #define MWL8K_STA_RATE_INFO_MCS_FORMAT 0x0001 | |
54bc3a0d | 831 | |
89a91f4f | 832 | #define MWL8K_STA_RX_CTRL_OWNED_BY_HOST 0x02 |
54bc3a0d | 833 | |
89a91f4f | 834 | static void mwl8k_rxd_sta_init(void *_rxd, dma_addr_t next_dma_addr) |
54bc3a0d | 835 | { |
89a91f4f | 836 | struct mwl8k_rxd_sta *rxd = _rxd; |
54bc3a0d LB |
837 | |
838 | rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr); | |
89a91f4f | 839 | rxd->rx_ctrl = MWL8K_STA_RX_CTRL_OWNED_BY_HOST; |
54bc3a0d LB |
840 | } |
841 | ||
89a91f4f | 842 | static void mwl8k_rxd_sta_refill(void *_rxd, dma_addr_t addr, int len) |
54bc3a0d | 843 | { |
89a91f4f | 844 | struct mwl8k_rxd_sta *rxd = _rxd; |
54bc3a0d LB |
845 | |
846 | rxd->pkt_len = cpu_to_le16(len); | |
847 | rxd->pkt_phys_addr = cpu_to_le32(addr); | |
848 | wmb(); | |
849 | rxd->rx_ctrl = 0; | |
850 | } | |
851 | ||
852 | static int | |
89a91f4f | 853 | mwl8k_rxd_sta_process(void *_rxd, struct ieee80211_rx_status *status, |
20f09c3d | 854 | __le16 *qos) |
54bc3a0d | 855 | { |
89a91f4f | 856 | struct mwl8k_rxd_sta *rxd = _rxd; |
54bc3a0d LB |
857 | u16 rate_info; |
858 | ||
89a91f4f | 859 | if (!(rxd->rx_ctrl & MWL8K_STA_RX_CTRL_OWNED_BY_HOST)) |
54bc3a0d LB |
860 | return -1; |
861 | rmb(); | |
862 | ||
863 | rate_info = le16_to_cpu(rxd->rate_info); | |
864 | ||
865 | memset(status, 0, sizeof(*status)); | |
866 | ||
867 | status->signal = -rxd->rssi; | |
868 | status->noise = -rxd->noise_level; | |
89a91f4f LB |
869 | status->antenna = MWL8K_STA_RATE_INFO_ANTSELECT(rate_info); |
870 | status->rate_idx = MWL8K_STA_RATE_INFO_RATEID(rate_info); | |
54bc3a0d | 871 | |
89a91f4f | 872 | if (rate_info & MWL8K_STA_RATE_INFO_SHORTPRE) |
54bc3a0d | 873 | status->flag |= RX_FLAG_SHORTPRE; |
89a91f4f | 874 | if (rate_info & MWL8K_STA_RATE_INFO_40MHZ) |
54bc3a0d | 875 | status->flag |= RX_FLAG_40MHZ; |
89a91f4f | 876 | if (rate_info & MWL8K_STA_RATE_INFO_SHORTGI) |
54bc3a0d | 877 | status->flag |= RX_FLAG_SHORT_GI; |
89a91f4f | 878 | if (rate_info & MWL8K_STA_RATE_INFO_MCS_FORMAT) |
54bc3a0d LB |
879 | status->flag |= RX_FLAG_HT; |
880 | ||
881 | status->band = IEEE80211_BAND_2GHZ; | |
882 | status->freq = ieee80211_channel_to_frequency(rxd->channel); | |
883 | ||
20f09c3d LB |
884 | *qos = rxd->qos_control; |
885 | ||
54bc3a0d LB |
886 | return le16_to_cpu(rxd->pkt_len); |
887 | } | |
888 | ||
89a91f4f LB |
889 | static struct rxd_ops rxd_sta_ops = { |
890 | .rxd_size = sizeof(struct mwl8k_rxd_sta), | |
891 | .rxd_init = mwl8k_rxd_sta_init, | |
892 | .rxd_refill = mwl8k_rxd_sta_refill, | |
893 | .rxd_process = mwl8k_rxd_sta_process, | |
54bc3a0d LB |
894 | }; |
895 | ||
896 | ||
a66098da LB |
897 | #define MWL8K_RX_DESCS 256 |
898 | #define MWL8K_RX_MAXSZ 3800 | |
899 | ||
900 | static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index) | |
901 | { | |
902 | struct mwl8k_priv *priv = hw->priv; | |
903 | struct mwl8k_rx_queue *rxq = priv->rxq + index; | |
904 | int size; | |
905 | int i; | |
906 | ||
45eb400d LB |
907 | rxq->rxd_count = 0; |
908 | rxq->head = 0; | |
909 | rxq->tail = 0; | |
a66098da | 910 | |
54bc3a0d | 911 | size = MWL8K_RX_DESCS * priv->rxd_ops->rxd_size; |
a66098da | 912 | |
45eb400d LB |
913 | rxq->rxd = pci_alloc_consistent(priv->pdev, size, &rxq->rxd_dma); |
914 | if (rxq->rxd == NULL) { | |
a66098da | 915 | printk(KERN_ERR "%s: failed to alloc RX descriptors\n", |
c2c357ce | 916 | wiphy_name(hw->wiphy)); |
a66098da LB |
917 | return -ENOMEM; |
918 | } | |
45eb400d | 919 | memset(rxq->rxd, 0, size); |
a66098da | 920 | |
788838eb LB |
921 | rxq->buf = kmalloc(MWL8K_RX_DESCS * sizeof(*rxq->buf), GFP_KERNEL); |
922 | if (rxq->buf == NULL) { | |
a66098da | 923 | printk(KERN_ERR "%s: failed to alloc RX skbuff list\n", |
c2c357ce | 924 | wiphy_name(hw->wiphy)); |
45eb400d | 925 | pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma); |
a66098da LB |
926 | return -ENOMEM; |
927 | } | |
788838eb | 928 | memset(rxq->buf, 0, MWL8K_RX_DESCS * sizeof(*rxq->buf)); |
a66098da LB |
929 | |
930 | for (i = 0; i < MWL8K_RX_DESCS; i++) { | |
54bc3a0d LB |
931 | int desc_size; |
932 | void *rxd; | |
a66098da | 933 | int nexti; |
54bc3a0d LB |
934 | dma_addr_t next_dma_addr; |
935 | ||
936 | desc_size = priv->rxd_ops->rxd_size; | |
937 | rxd = rxq->rxd + (i * priv->rxd_ops->rxd_size); | |
a66098da | 938 | |
54bc3a0d LB |
939 | nexti = i + 1; |
940 | if (nexti == MWL8K_RX_DESCS) | |
941 | nexti = 0; | |
942 | next_dma_addr = rxq->rxd_dma + (nexti * desc_size); | |
a66098da | 943 | |
54bc3a0d | 944 | priv->rxd_ops->rxd_init(rxd, next_dma_addr); |
a66098da LB |
945 | } |
946 | ||
947 | return 0; | |
948 | } | |
949 | ||
950 | static int rxq_refill(struct ieee80211_hw *hw, int index, int limit) | |
951 | { | |
952 | struct mwl8k_priv *priv = hw->priv; | |
953 | struct mwl8k_rx_queue *rxq = priv->rxq + index; | |
954 | int refilled; | |
955 | ||
956 | refilled = 0; | |
45eb400d | 957 | while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) { |
a66098da | 958 | struct sk_buff *skb; |
788838eb | 959 | dma_addr_t addr; |
a66098da | 960 | int rx; |
54bc3a0d | 961 | void *rxd; |
a66098da LB |
962 | |
963 | skb = dev_alloc_skb(MWL8K_RX_MAXSZ); | |
964 | if (skb == NULL) | |
965 | break; | |
966 | ||
788838eb LB |
967 | addr = pci_map_single(priv->pdev, skb->data, |
968 | MWL8K_RX_MAXSZ, DMA_FROM_DEVICE); | |
a66098da | 969 | |
54bc3a0d LB |
970 | rxq->rxd_count++; |
971 | rx = rxq->tail++; | |
972 | if (rxq->tail == MWL8K_RX_DESCS) | |
973 | rxq->tail = 0; | |
788838eb LB |
974 | rxq->buf[rx].skb = skb; |
975 | pci_unmap_addr_set(&rxq->buf[rx], dma, addr); | |
54bc3a0d LB |
976 | |
977 | rxd = rxq->rxd + (rx * priv->rxd_ops->rxd_size); | |
978 | priv->rxd_ops->rxd_refill(rxd, addr, MWL8K_RX_MAXSZ); | |
a66098da LB |
979 | |
980 | refilled++; | |
981 | } | |
982 | ||
983 | return refilled; | |
984 | } | |
985 | ||
986 | /* Must be called only when the card's reception is completely halted */ | |
987 | static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index) | |
988 | { | |
989 | struct mwl8k_priv *priv = hw->priv; | |
990 | struct mwl8k_rx_queue *rxq = priv->rxq + index; | |
991 | int i; | |
992 | ||
993 | for (i = 0; i < MWL8K_RX_DESCS; i++) { | |
788838eb LB |
994 | if (rxq->buf[i].skb != NULL) { |
995 | pci_unmap_single(priv->pdev, | |
996 | pci_unmap_addr(&rxq->buf[i], dma), | |
997 | MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE); | |
998 | pci_unmap_addr_set(&rxq->buf[i], dma, 0); | |
999 | ||
1000 | kfree_skb(rxq->buf[i].skb); | |
1001 | rxq->buf[i].skb = NULL; | |
a66098da LB |
1002 | } |
1003 | } | |
1004 | ||
788838eb LB |
1005 | kfree(rxq->buf); |
1006 | rxq->buf = NULL; | |
a66098da LB |
1007 | |
1008 | pci_free_consistent(priv->pdev, | |
54bc3a0d | 1009 | MWL8K_RX_DESCS * priv->rxd_ops->rxd_size, |
45eb400d LB |
1010 | rxq->rxd, rxq->rxd_dma); |
1011 | rxq->rxd = NULL; | |
a66098da LB |
1012 | } |
1013 | ||
1014 | ||
1015 | /* | |
1016 | * Scan a list of BSSIDs to process for finalize join. | |
1017 | * Allows for extension to process multiple BSSIDs. | |
1018 | */ | |
1019 | static inline int | |
1020 | mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh) | |
1021 | { | |
1022 | return priv->capture_beacon && | |
1023 | ieee80211_is_beacon(wh->frame_control) && | |
1024 | !compare_ether_addr(wh->addr3, priv->capture_bssid); | |
1025 | } | |
1026 | ||
3779752d LB |
1027 | static inline void mwl8k_save_beacon(struct ieee80211_hw *hw, |
1028 | struct sk_buff *skb) | |
a66098da | 1029 | { |
3779752d LB |
1030 | struct mwl8k_priv *priv = hw->priv; |
1031 | ||
a66098da | 1032 | priv->capture_beacon = false; |
d89173f2 | 1033 | memset(priv->capture_bssid, 0, ETH_ALEN); |
a66098da LB |
1034 | |
1035 | /* | |
1036 | * Use GFP_ATOMIC as rxq_process is called from | |
1037 | * the primary interrupt handler, memory allocation call | |
1038 | * must not sleep. | |
1039 | */ | |
1040 | priv->beacon_skb = skb_copy(skb, GFP_ATOMIC); | |
1041 | if (priv->beacon_skb != NULL) | |
3779752d | 1042 | ieee80211_queue_work(hw, &priv->finalize_join_worker); |
a66098da LB |
1043 | } |
1044 | ||
1045 | static int rxq_process(struct ieee80211_hw *hw, int index, int limit) | |
1046 | { | |
1047 | struct mwl8k_priv *priv = hw->priv; | |
1048 | struct mwl8k_rx_queue *rxq = priv->rxq + index; | |
1049 | int processed; | |
1050 | ||
1051 | processed = 0; | |
45eb400d | 1052 | while (rxq->rxd_count && limit--) { |
a66098da | 1053 | struct sk_buff *skb; |
54bc3a0d LB |
1054 | void *rxd; |
1055 | int pkt_len; | |
a66098da | 1056 | struct ieee80211_rx_status status; |
20f09c3d | 1057 | __le16 qos; |
a66098da | 1058 | |
788838eb | 1059 | skb = rxq->buf[rxq->head].skb; |
d25f9f13 LB |
1060 | if (skb == NULL) |
1061 | break; | |
54bc3a0d LB |
1062 | |
1063 | rxd = rxq->rxd + (rxq->head * priv->rxd_ops->rxd_size); | |
1064 | ||
20f09c3d | 1065 | pkt_len = priv->rxd_ops->rxd_process(rxd, &status, &qos); |
54bc3a0d LB |
1066 | if (pkt_len < 0) |
1067 | break; | |
1068 | ||
788838eb LB |
1069 | rxq->buf[rxq->head].skb = NULL; |
1070 | ||
1071 | pci_unmap_single(priv->pdev, | |
1072 | pci_unmap_addr(&rxq->buf[rxq->head], dma), | |
1073 | MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE); | |
1074 | pci_unmap_addr_set(&rxq->buf[rxq->head], dma, 0); | |
a66098da | 1075 | |
54bc3a0d LB |
1076 | rxq->head++; |
1077 | if (rxq->head == MWL8K_RX_DESCS) | |
1078 | rxq->head = 0; | |
1079 | ||
45eb400d | 1080 | rxq->rxd_count--; |
a66098da | 1081 | |
54bc3a0d | 1082 | skb_put(skb, pkt_len); |
20f09c3d | 1083 | mwl8k_remove_dma_header(skb, qos); |
a66098da | 1084 | |
a66098da | 1085 | /* |
c2c357ce LB |
1086 | * Check for a pending join operation. Save a |
1087 | * copy of the beacon and schedule a tasklet to | |
1088 | * send a FINALIZE_JOIN command to the firmware. | |
a66098da | 1089 | */ |
54bc3a0d | 1090 | if (mwl8k_capture_bssid(priv, (void *)skb->data)) |
3779752d | 1091 | mwl8k_save_beacon(hw, skb); |
a66098da | 1092 | |
f1d58c25 JB |
1093 | memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status)); |
1094 | ieee80211_rx_irqsafe(hw, skb); | |
a66098da LB |
1095 | |
1096 | processed++; | |
1097 | } | |
1098 | ||
1099 | return processed; | |
1100 | } | |
1101 | ||
1102 | ||
1103 | /* | |
1104 | * Packet transmission. | |
1105 | */ | |
1106 | ||
a66098da LB |
1107 | #define MWL8K_TXD_STATUS_OK 0x00000001 |
1108 | #define MWL8K_TXD_STATUS_OK_RETRY 0x00000002 | |
1109 | #define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004 | |
1110 | #define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008 | |
a66098da | 1111 | #define MWL8K_TXD_STATUS_FW_OWNED 0x80000000 |
a66098da | 1112 | |
e0493a8d LB |
1113 | #define MWL8K_QOS_QLEN_UNSPEC 0xff00 |
1114 | #define MWL8K_QOS_ACK_POLICY_MASK 0x0060 | |
1115 | #define MWL8K_QOS_ACK_POLICY_NORMAL 0x0000 | |
1116 | #define MWL8K_QOS_ACK_POLICY_BLOCKACK 0x0060 | |
1117 | #define MWL8K_QOS_EOSP 0x0010 | |
1118 | ||
a66098da LB |
1119 | struct mwl8k_tx_desc { |
1120 | __le32 status; | |
1121 | __u8 data_rate; | |
1122 | __u8 tx_priority; | |
1123 | __le16 qos_control; | |
1124 | __le32 pkt_phys_addr; | |
1125 | __le16 pkt_len; | |
d89173f2 | 1126 | __u8 dest_MAC_addr[ETH_ALEN]; |
45eb400d | 1127 | __le32 next_txd_phys_addr; |
a66098da LB |
1128 | __le32 reserved; |
1129 | __le16 rate_info; | |
1130 | __u8 peer_id; | |
1131 | __u8 tx_frag_cnt; | |
1132 | } __attribute__((packed)); | |
1133 | ||
1134 | #define MWL8K_TX_DESCS 128 | |
1135 | ||
1136 | static int mwl8k_txq_init(struct ieee80211_hw *hw, int index) | |
1137 | { | |
1138 | struct mwl8k_priv *priv = hw->priv; | |
1139 | struct mwl8k_tx_queue *txq = priv->txq + index; | |
1140 | int size; | |
1141 | int i; | |
1142 | ||
45eb400d LB |
1143 | memset(&txq->stats, 0, sizeof(struct ieee80211_tx_queue_stats)); |
1144 | txq->stats.limit = MWL8K_TX_DESCS; | |
1145 | txq->head = 0; | |
1146 | txq->tail = 0; | |
a66098da LB |
1147 | |
1148 | size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc); | |
1149 | ||
45eb400d LB |
1150 | txq->txd = pci_alloc_consistent(priv->pdev, size, &txq->txd_dma); |
1151 | if (txq->txd == NULL) { | |
a66098da | 1152 | printk(KERN_ERR "%s: failed to alloc TX descriptors\n", |
c2c357ce | 1153 | wiphy_name(hw->wiphy)); |
a66098da LB |
1154 | return -ENOMEM; |
1155 | } | |
45eb400d | 1156 | memset(txq->txd, 0, size); |
a66098da | 1157 | |
45eb400d LB |
1158 | txq->skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->skb), GFP_KERNEL); |
1159 | if (txq->skb == NULL) { | |
a66098da | 1160 | printk(KERN_ERR "%s: failed to alloc TX skbuff list\n", |
c2c357ce | 1161 | wiphy_name(hw->wiphy)); |
45eb400d | 1162 | pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma); |
a66098da LB |
1163 | return -ENOMEM; |
1164 | } | |
45eb400d | 1165 | memset(txq->skb, 0, MWL8K_TX_DESCS * sizeof(*txq->skb)); |
a66098da LB |
1166 | |
1167 | for (i = 0; i < MWL8K_TX_DESCS; i++) { | |
1168 | struct mwl8k_tx_desc *tx_desc; | |
1169 | int nexti; | |
1170 | ||
45eb400d | 1171 | tx_desc = txq->txd + i; |
a66098da LB |
1172 | nexti = (i + 1) % MWL8K_TX_DESCS; |
1173 | ||
1174 | tx_desc->status = 0; | |
45eb400d LB |
1175 | tx_desc->next_txd_phys_addr = |
1176 | cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc)); | |
a66098da LB |
1177 | } |
1178 | ||
1179 | return 0; | |
1180 | } | |
1181 | ||
1182 | static inline void mwl8k_tx_start(struct mwl8k_priv *priv) | |
1183 | { | |
1184 | iowrite32(MWL8K_H2A_INT_PPA_READY, | |
1185 | priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); | |
1186 | iowrite32(MWL8K_H2A_INT_DUMMY, | |
1187 | priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); | |
1188 | ioread32(priv->regs + MWL8K_HIU_INT_CODE); | |
1189 | } | |
1190 | ||
7e1112d3 | 1191 | static void mwl8k_dump_tx_rings(struct ieee80211_hw *hw) |
a66098da | 1192 | { |
7e1112d3 LB |
1193 | struct mwl8k_priv *priv = hw->priv; |
1194 | int i; | |
1195 | ||
1196 | for (i = 0; i < MWL8K_TX_QUEUES; i++) { | |
1197 | struct mwl8k_tx_queue *txq = priv->txq + i; | |
1198 | int fw_owned = 0; | |
1199 | int drv_owned = 0; | |
1200 | int unused = 0; | |
1201 | int desc; | |
1202 | ||
a66098da | 1203 | for (desc = 0; desc < MWL8K_TX_DESCS; desc++) { |
7e1112d3 LB |
1204 | struct mwl8k_tx_desc *tx_desc = txq->txd + desc; |
1205 | u32 status; | |
a66098da | 1206 | |
7e1112d3 | 1207 | status = le32_to_cpu(tx_desc->status); |
a66098da | 1208 | if (status & MWL8K_TXD_STATUS_FW_OWNED) |
7e1112d3 | 1209 | fw_owned++; |
a66098da | 1210 | else |
7e1112d3 | 1211 | drv_owned++; |
a66098da LB |
1212 | |
1213 | if (tx_desc->pkt_len == 0) | |
7e1112d3 | 1214 | unused++; |
a66098da | 1215 | } |
a66098da | 1216 | |
7e1112d3 LB |
1217 | printk(KERN_ERR "%s: txq[%d] len=%d head=%d tail=%d " |
1218 | "fw_owned=%d drv_owned=%d unused=%d\n", | |
1219 | wiphy_name(hw->wiphy), i, | |
1220 | txq->stats.len, txq->head, txq->tail, | |
1221 | fw_owned, drv_owned, unused); | |
1222 | } | |
a66098da LB |
1223 | } |
1224 | ||
618952a7 | 1225 | /* |
88de754a | 1226 | * Must be called with priv->fw_mutex held and tx queues stopped. |
618952a7 | 1227 | */ |
7e1112d3 LB |
1228 | #define MWL8K_TX_WAIT_TIMEOUT_MS 1000 |
1229 | ||
950d5b01 | 1230 | static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw) |
a66098da | 1231 | { |
a66098da | 1232 | struct mwl8k_priv *priv = hw->priv; |
88de754a | 1233 | DECLARE_COMPLETION_ONSTACK(tx_wait); |
7e1112d3 LB |
1234 | int retry; |
1235 | int rc; | |
a66098da LB |
1236 | |
1237 | might_sleep(); | |
1238 | ||
7e1112d3 LB |
1239 | /* |
1240 | * The TX queues are stopped at this point, so this test | |
1241 | * doesn't need to take ->tx_lock. | |
1242 | */ | |
1243 | if (!priv->pending_tx_pkts) | |
1244 | return 0; | |
1245 | ||
1246 | retry = 0; | |
1247 | rc = 0; | |
1248 | ||
a66098da | 1249 | spin_lock_bh(&priv->tx_lock); |
7e1112d3 LB |
1250 | priv->tx_wait = &tx_wait; |
1251 | while (!rc) { | |
1252 | int oldcount; | |
1253 | unsigned long timeout; | |
a66098da | 1254 | |
7e1112d3 | 1255 | oldcount = priv->pending_tx_pkts; |
a66098da | 1256 | |
7e1112d3 | 1257 | spin_unlock_bh(&priv->tx_lock); |
88de754a | 1258 | timeout = wait_for_completion_timeout(&tx_wait, |
7e1112d3 | 1259 | msecs_to_jiffies(MWL8K_TX_WAIT_TIMEOUT_MS)); |
a66098da | 1260 | spin_lock_bh(&priv->tx_lock); |
7e1112d3 LB |
1261 | |
1262 | if (timeout) { | |
1263 | WARN_ON(priv->pending_tx_pkts); | |
1264 | if (retry) { | |
1265 | printk(KERN_NOTICE "%s: tx rings drained\n", | |
1266 | wiphy_name(hw->wiphy)); | |
1267 | } | |
1268 | break; | |
1269 | } | |
1270 | ||
1271 | if (priv->pending_tx_pkts < oldcount) { | |
9a2303b9 LB |
1272 | printk(KERN_NOTICE "%s: waiting for tx rings " |
1273 | "to drain (%d -> %d pkts)\n", | |
7e1112d3 LB |
1274 | wiphy_name(hw->wiphy), oldcount, |
1275 | priv->pending_tx_pkts); | |
1276 | retry = 1; | |
1277 | continue; | |
1278 | } | |
1279 | ||
a66098da | 1280 | priv->tx_wait = NULL; |
a66098da | 1281 | |
7e1112d3 LB |
1282 | printk(KERN_ERR "%s: tx rings stuck for %d ms\n", |
1283 | wiphy_name(hw->wiphy), MWL8K_TX_WAIT_TIMEOUT_MS); | |
1284 | mwl8k_dump_tx_rings(hw); | |
1285 | ||
1286 | rc = -ETIMEDOUT; | |
a66098da | 1287 | } |
7e1112d3 | 1288 | spin_unlock_bh(&priv->tx_lock); |
a66098da | 1289 | |
7e1112d3 | 1290 | return rc; |
a66098da LB |
1291 | } |
1292 | ||
c23b5a69 LB |
1293 | #define MWL8K_TXD_SUCCESS(status) \ |
1294 | ((status) & (MWL8K_TXD_STATUS_OK | \ | |
1295 | MWL8K_TXD_STATUS_OK_RETRY | \ | |
1296 | MWL8K_TXD_STATUS_OK_MORE_RETRY)) | |
a66098da LB |
1297 | |
1298 | static void mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int force) | |
1299 | { | |
1300 | struct mwl8k_priv *priv = hw->priv; | |
1301 | struct mwl8k_tx_queue *txq = priv->txq + index; | |
1302 | int wake = 0; | |
1303 | ||
45eb400d | 1304 | while (txq->stats.len > 0) { |
a66098da | 1305 | int tx; |
a66098da LB |
1306 | struct mwl8k_tx_desc *tx_desc; |
1307 | unsigned long addr; | |
ce9e2e1b | 1308 | int size; |
a66098da LB |
1309 | struct sk_buff *skb; |
1310 | struct ieee80211_tx_info *info; | |
1311 | u32 status; | |
1312 | ||
45eb400d LB |
1313 | tx = txq->head; |
1314 | tx_desc = txq->txd + tx; | |
a66098da LB |
1315 | |
1316 | status = le32_to_cpu(tx_desc->status); | |
1317 | ||
1318 | if (status & MWL8K_TXD_STATUS_FW_OWNED) { | |
1319 | if (!force) | |
1320 | break; | |
1321 | tx_desc->status &= | |
1322 | ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED); | |
1323 | } | |
1324 | ||
45eb400d LB |
1325 | txq->head = (tx + 1) % MWL8K_TX_DESCS; |
1326 | BUG_ON(txq->stats.len == 0); | |
1327 | txq->stats.len--; | |
a66098da LB |
1328 | priv->pending_tx_pkts--; |
1329 | ||
1330 | addr = le32_to_cpu(tx_desc->pkt_phys_addr); | |
ce9e2e1b | 1331 | size = le16_to_cpu(tx_desc->pkt_len); |
45eb400d LB |
1332 | skb = txq->skb[tx]; |
1333 | txq->skb[tx] = NULL; | |
a66098da LB |
1334 | |
1335 | BUG_ON(skb == NULL); | |
1336 | pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE); | |
1337 | ||
20f09c3d | 1338 | mwl8k_remove_dma_header(skb, tx_desc->qos_control); |
a66098da LB |
1339 | |
1340 | /* Mark descriptor as unused */ | |
1341 | tx_desc->pkt_phys_addr = 0; | |
1342 | tx_desc->pkt_len = 0; | |
1343 | ||
a66098da LB |
1344 | info = IEEE80211_SKB_CB(skb); |
1345 | ieee80211_tx_info_clear_status(info); | |
ce9e2e1b | 1346 | if (MWL8K_TXD_SUCCESS(status)) |
a66098da | 1347 | info->flags |= IEEE80211_TX_STAT_ACK; |
a66098da LB |
1348 | |
1349 | ieee80211_tx_status_irqsafe(hw, skb); | |
1350 | ||
618952a7 | 1351 | wake = 1; |
a66098da LB |
1352 | } |
1353 | ||
618952a7 | 1354 | if (wake && priv->radio_on && !mutex_is_locked(&priv->fw_mutex)) |
a66098da LB |
1355 | ieee80211_wake_queue(hw, index); |
1356 | } | |
1357 | ||
1358 | /* must be called only when the card's transmit is completely halted */ | |
1359 | static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index) | |
1360 | { | |
1361 | struct mwl8k_priv *priv = hw->priv; | |
1362 | struct mwl8k_tx_queue *txq = priv->txq + index; | |
1363 | ||
1364 | mwl8k_txq_reclaim(hw, index, 1); | |
1365 | ||
45eb400d LB |
1366 | kfree(txq->skb); |
1367 | txq->skb = NULL; | |
a66098da LB |
1368 | |
1369 | pci_free_consistent(priv->pdev, | |
1370 | MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc), | |
45eb400d LB |
1371 | txq->txd, txq->txd_dma); |
1372 | txq->txd = NULL; | |
a66098da LB |
1373 | } |
1374 | ||
1375 | static int | |
1376 | mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb) | |
1377 | { | |
1378 | struct mwl8k_priv *priv = hw->priv; | |
1379 | struct ieee80211_tx_info *tx_info; | |
23b33906 | 1380 | struct mwl8k_vif *mwl8k_vif; |
a66098da LB |
1381 | struct ieee80211_hdr *wh; |
1382 | struct mwl8k_tx_queue *txq; | |
1383 | struct mwl8k_tx_desc *tx; | |
a66098da | 1384 | dma_addr_t dma; |
23b33906 LB |
1385 | u32 txstatus; |
1386 | u8 txdatarate; | |
1387 | u16 qos; | |
a66098da | 1388 | |
23b33906 LB |
1389 | wh = (struct ieee80211_hdr *)skb->data; |
1390 | if (ieee80211_is_data_qos(wh->frame_control)) | |
1391 | qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh))); | |
1392 | else | |
1393 | qos = 0; | |
a66098da | 1394 | |
76266b2a | 1395 | mwl8k_add_dma_header(skb); |
23b33906 | 1396 | wh = &((struct mwl8k_dma_data *)skb->data)->wh; |
a66098da LB |
1397 | |
1398 | tx_info = IEEE80211_SKB_CB(skb); | |
1399 | mwl8k_vif = MWL8K_VIF(tx_info->control.vif); | |
a66098da LB |
1400 | |
1401 | if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { | |
1402 | u16 seqno = mwl8k_vif->seqno; | |
23b33906 | 1403 | |
a66098da LB |
1404 | wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); |
1405 | wh->seq_ctrl |= cpu_to_le16(seqno << 4); | |
1406 | mwl8k_vif->seqno = seqno++ % 4096; | |
1407 | } | |
1408 | ||
23b33906 LB |
1409 | /* Setup firmware control bit fields for each frame type. */ |
1410 | txstatus = 0; | |
1411 | txdatarate = 0; | |
1412 | if (ieee80211_is_mgmt(wh->frame_control) || | |
1413 | ieee80211_is_ctl(wh->frame_control)) { | |
1414 | txdatarate = 0; | |
e0493a8d | 1415 | qos |= MWL8K_QOS_QLEN_UNSPEC | MWL8K_QOS_EOSP; |
23b33906 LB |
1416 | } else if (ieee80211_is_data(wh->frame_control)) { |
1417 | txdatarate = 1; | |
1418 | if (is_multicast_ether_addr(wh->addr1)) | |
1419 | txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX; | |
1420 | ||
e0493a8d | 1421 | qos &= ~MWL8K_QOS_ACK_POLICY_MASK; |
23b33906 | 1422 | if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) |
e0493a8d | 1423 | qos |= MWL8K_QOS_ACK_POLICY_BLOCKACK; |
23b33906 | 1424 | else |
e0493a8d | 1425 | qos |= MWL8K_QOS_ACK_POLICY_NORMAL; |
23b33906 | 1426 | } |
a66098da LB |
1427 | |
1428 | dma = pci_map_single(priv->pdev, skb->data, | |
1429 | skb->len, PCI_DMA_TODEVICE); | |
1430 | ||
1431 | if (pci_dma_mapping_error(priv->pdev, dma)) { | |
1432 | printk(KERN_DEBUG "%s: failed to dma map skb, " | |
c2c357ce | 1433 | "dropping TX frame.\n", wiphy_name(hw->wiphy)); |
23b33906 | 1434 | dev_kfree_skb(skb); |
a66098da LB |
1435 | return NETDEV_TX_OK; |
1436 | } | |
1437 | ||
23b33906 | 1438 | spin_lock_bh(&priv->tx_lock); |
a66098da | 1439 | |
23b33906 | 1440 | txq = priv->txq + index; |
a66098da | 1441 | |
45eb400d LB |
1442 | BUG_ON(txq->skb[txq->tail] != NULL); |
1443 | txq->skb[txq->tail] = skb; | |
a66098da | 1444 | |
45eb400d | 1445 | tx = txq->txd + txq->tail; |
23b33906 LB |
1446 | tx->data_rate = txdatarate; |
1447 | tx->tx_priority = index; | |
a66098da | 1448 | tx->qos_control = cpu_to_le16(qos); |
a66098da LB |
1449 | tx->pkt_phys_addr = cpu_to_le32(dma); |
1450 | tx->pkt_len = cpu_to_le16(skb->len); | |
23b33906 LB |
1451 | tx->rate_info = 0; |
1452 | tx->peer_id = mwl8k_vif->peer_id; | |
a66098da | 1453 | wmb(); |
23b33906 LB |
1454 | tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus); |
1455 | ||
45eb400d LB |
1456 | txq->stats.count++; |
1457 | txq->stats.len++; | |
a66098da | 1458 | priv->pending_tx_pkts++; |
a66098da | 1459 | |
45eb400d LB |
1460 | txq->tail++; |
1461 | if (txq->tail == MWL8K_TX_DESCS) | |
1462 | txq->tail = 0; | |
23b33906 | 1463 | |
45eb400d | 1464 | if (txq->head == txq->tail) |
a66098da LB |
1465 | ieee80211_stop_queue(hw, index); |
1466 | ||
23b33906 | 1467 | mwl8k_tx_start(priv); |
a66098da LB |
1468 | |
1469 | spin_unlock_bh(&priv->tx_lock); | |
1470 | ||
1471 | return NETDEV_TX_OK; | |
1472 | } | |
1473 | ||
1474 | ||
618952a7 LB |
1475 | /* |
1476 | * Firmware access. | |
1477 | * | |
1478 | * We have the following requirements for issuing firmware commands: | |
1479 | * - Some commands require that the packet transmit path is idle when | |
1480 | * the command is issued. (For simplicity, we'll just quiesce the | |
1481 | * transmit path for every command.) | |
1482 | * - There are certain sequences of commands that need to be issued to | |
1483 | * the hardware sequentially, with no other intervening commands. | |
1484 | * | |
1485 | * This leads to an implementation of a "firmware lock" as a mutex that | |
1486 | * can be taken recursively, and which is taken by both the low-level | |
1487 | * command submission function (mwl8k_post_cmd) as well as any users of | |
1488 | * that function that require issuing of an atomic sequence of commands, | |
1489 | * and quiesces the transmit path whenever it's taken. | |
1490 | */ | |
1491 | static int mwl8k_fw_lock(struct ieee80211_hw *hw) | |
1492 | { | |
1493 | struct mwl8k_priv *priv = hw->priv; | |
1494 | ||
1495 | if (priv->fw_mutex_owner != current) { | |
1496 | int rc; | |
1497 | ||
1498 | mutex_lock(&priv->fw_mutex); | |
1499 | ieee80211_stop_queues(hw); | |
1500 | ||
1501 | rc = mwl8k_tx_wait_empty(hw); | |
1502 | if (rc) { | |
1503 | ieee80211_wake_queues(hw); | |
1504 | mutex_unlock(&priv->fw_mutex); | |
1505 | ||
1506 | return rc; | |
1507 | } | |
1508 | ||
1509 | priv->fw_mutex_owner = current; | |
1510 | } | |
1511 | ||
1512 | priv->fw_mutex_depth++; | |
1513 | ||
1514 | return 0; | |
1515 | } | |
1516 | ||
1517 | static void mwl8k_fw_unlock(struct ieee80211_hw *hw) | |
1518 | { | |
1519 | struct mwl8k_priv *priv = hw->priv; | |
1520 | ||
1521 | if (!--priv->fw_mutex_depth) { | |
1522 | ieee80211_wake_queues(hw); | |
1523 | priv->fw_mutex_owner = NULL; | |
1524 | mutex_unlock(&priv->fw_mutex); | |
1525 | } | |
1526 | } | |
1527 | ||
1528 | ||
a66098da LB |
1529 | /* |
1530 | * Command processing. | |
1531 | */ | |
1532 | ||
0c9cc640 LB |
1533 | /* Timeout firmware commands after 10s */ |
1534 | #define MWL8K_CMD_TIMEOUT_MS 10000 | |
a66098da LB |
1535 | |
1536 | static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd) | |
1537 | { | |
1538 | DECLARE_COMPLETION_ONSTACK(cmd_wait); | |
1539 | struct mwl8k_priv *priv = hw->priv; | |
1540 | void __iomem *regs = priv->regs; | |
1541 | dma_addr_t dma_addr; | |
1542 | unsigned int dma_size; | |
1543 | int rc; | |
a66098da LB |
1544 | unsigned long timeout = 0; |
1545 | u8 buf[32]; | |
1546 | ||
c2c357ce | 1547 | cmd->result = 0xffff; |
a66098da LB |
1548 | dma_size = le16_to_cpu(cmd->length); |
1549 | dma_addr = pci_map_single(priv->pdev, cmd, dma_size, | |
1550 | PCI_DMA_BIDIRECTIONAL); | |
1551 | if (pci_dma_mapping_error(priv->pdev, dma_addr)) | |
1552 | return -ENOMEM; | |
1553 | ||
618952a7 | 1554 | rc = mwl8k_fw_lock(hw); |
39a1e42e LB |
1555 | if (rc) { |
1556 | pci_unmap_single(priv->pdev, dma_addr, dma_size, | |
1557 | PCI_DMA_BIDIRECTIONAL); | |
618952a7 | 1558 | return rc; |
39a1e42e | 1559 | } |
a66098da | 1560 | |
a66098da LB |
1561 | priv->hostcmd_wait = &cmd_wait; |
1562 | iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR); | |
1563 | iowrite32(MWL8K_H2A_INT_DOORBELL, | |
1564 | regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); | |
1565 | iowrite32(MWL8K_H2A_INT_DUMMY, | |
1566 | regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); | |
a66098da LB |
1567 | |
1568 | timeout = wait_for_completion_timeout(&cmd_wait, | |
1569 | msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS)); | |
1570 | ||
618952a7 LB |
1571 | priv->hostcmd_wait = NULL; |
1572 | ||
1573 | mwl8k_fw_unlock(hw); | |
1574 | ||
37055bd4 LB |
1575 | pci_unmap_single(priv->pdev, dma_addr, dma_size, |
1576 | PCI_DMA_BIDIRECTIONAL); | |
1577 | ||
a66098da | 1578 | if (!timeout) { |
a66098da | 1579 | printk(KERN_ERR "%s: Command %s timeout after %u ms\n", |
c2c357ce | 1580 | wiphy_name(hw->wiphy), |
a66098da LB |
1581 | mwl8k_cmd_name(cmd->code, buf, sizeof(buf)), |
1582 | MWL8K_CMD_TIMEOUT_MS); | |
1583 | rc = -ETIMEDOUT; | |
1584 | } else { | |
0c9cc640 LB |
1585 | int ms; |
1586 | ||
1587 | ms = MWL8K_CMD_TIMEOUT_MS - jiffies_to_msecs(timeout); | |
1588 | ||
ce9e2e1b | 1589 | rc = cmd->result ? -EINVAL : 0; |
a66098da LB |
1590 | if (rc) |
1591 | printk(KERN_ERR "%s: Command %s error 0x%x\n", | |
c2c357ce | 1592 | wiphy_name(hw->wiphy), |
a66098da | 1593 | mwl8k_cmd_name(cmd->code, buf, sizeof(buf)), |
76c962a2 | 1594 | le16_to_cpu(cmd->result)); |
0c9cc640 LB |
1595 | else if (ms > 2000) |
1596 | printk(KERN_NOTICE "%s: Command %s took %d ms\n", | |
1597 | wiphy_name(hw->wiphy), | |
1598 | mwl8k_cmd_name(cmd->code, buf, sizeof(buf)), | |
1599 | ms); | |
a66098da LB |
1600 | } |
1601 | ||
a66098da LB |
1602 | return rc; |
1603 | } | |
1604 | ||
1605 | /* | |
04b147b1 | 1606 | * CMD_GET_HW_SPEC (STA version). |
a66098da | 1607 | */ |
04b147b1 | 1608 | struct mwl8k_cmd_get_hw_spec_sta { |
a66098da LB |
1609 | struct mwl8k_cmd_pkt header; |
1610 | __u8 hw_rev; | |
1611 | __u8 host_interface; | |
1612 | __le16 num_mcaddrs; | |
d89173f2 | 1613 | __u8 perm_addr[ETH_ALEN]; |
a66098da LB |
1614 | __le16 region_code; |
1615 | __le32 fw_rev; | |
1616 | __le32 ps_cookie; | |
1617 | __le32 caps; | |
1618 | __u8 mcs_bitmap[16]; | |
1619 | __le32 rx_queue_ptr; | |
1620 | __le32 num_tx_queues; | |
1621 | __le32 tx_queue_ptrs[MWL8K_TX_QUEUES]; | |
1622 | __le32 caps2; | |
1623 | __le32 num_tx_desc_per_queue; | |
45eb400d | 1624 | __le32 total_rxd; |
a66098da LB |
1625 | } __attribute__((packed)); |
1626 | ||
04b147b1 | 1627 | static int mwl8k_cmd_get_hw_spec_sta(struct ieee80211_hw *hw) |
a66098da LB |
1628 | { |
1629 | struct mwl8k_priv *priv = hw->priv; | |
04b147b1 | 1630 | struct mwl8k_cmd_get_hw_spec_sta *cmd; |
a66098da LB |
1631 | int rc; |
1632 | int i; | |
1633 | ||
1634 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
1635 | if (cmd == NULL) | |
1636 | return -ENOMEM; | |
1637 | ||
1638 | cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC); | |
1639 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
1640 | ||
1641 | memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr)); | |
1642 | cmd->ps_cookie = cpu_to_le32(priv->cookie_dma); | |
45eb400d | 1643 | cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma); |
4ff6432e | 1644 | cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES); |
a66098da | 1645 | for (i = 0; i < MWL8K_TX_QUEUES; i++) |
45eb400d | 1646 | cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma); |
4ff6432e | 1647 | cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS); |
45eb400d | 1648 | cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS); |
a66098da LB |
1649 | |
1650 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
1651 | ||
1652 | if (!rc) { | |
1653 | SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr); | |
1654 | priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs); | |
4ff6432e | 1655 | priv->fw_rev = le32_to_cpu(cmd->fw_rev); |
a66098da | 1656 | priv->hw_rev = cmd->hw_rev; |
a66098da LB |
1657 | } |
1658 | ||
1659 | kfree(cmd); | |
1660 | return rc; | |
1661 | } | |
1662 | ||
42fba21d LB |
1663 | /* |
1664 | * CMD_GET_HW_SPEC (AP version). | |
1665 | */ | |
1666 | struct mwl8k_cmd_get_hw_spec_ap { | |
1667 | struct mwl8k_cmd_pkt header; | |
1668 | __u8 hw_rev; | |
1669 | __u8 host_interface; | |
1670 | __le16 num_wcb; | |
1671 | __le16 num_mcaddrs; | |
1672 | __u8 perm_addr[ETH_ALEN]; | |
1673 | __le16 region_code; | |
1674 | __le16 num_antenna; | |
1675 | __le32 fw_rev; | |
1676 | __le32 wcbbase0; | |
1677 | __le32 rxwrptr; | |
1678 | __le32 rxrdptr; | |
1679 | __le32 ps_cookie; | |
1680 | __le32 wcbbase1; | |
1681 | __le32 wcbbase2; | |
1682 | __le32 wcbbase3; | |
1683 | } __attribute__((packed)); | |
1684 | ||
1685 | static int mwl8k_cmd_get_hw_spec_ap(struct ieee80211_hw *hw) | |
1686 | { | |
1687 | struct mwl8k_priv *priv = hw->priv; | |
1688 | struct mwl8k_cmd_get_hw_spec_ap *cmd; | |
1689 | int rc; | |
1690 | ||
1691 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
1692 | if (cmd == NULL) | |
1693 | return -ENOMEM; | |
1694 | ||
1695 | cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC); | |
1696 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
1697 | ||
1698 | memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr)); | |
1699 | cmd->ps_cookie = cpu_to_le32(priv->cookie_dma); | |
1700 | ||
1701 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
1702 | ||
1703 | if (!rc) { | |
1704 | int off; | |
1705 | ||
1706 | SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr); | |
1707 | priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs); | |
1708 | priv->fw_rev = le32_to_cpu(cmd->fw_rev); | |
1709 | priv->hw_rev = cmd->hw_rev; | |
1710 | ||
1711 | off = le32_to_cpu(cmd->wcbbase0) & 0xffff; | |
1712 | iowrite32(cpu_to_le32(priv->txq[0].txd_dma), priv->sram + off); | |
1713 | ||
1714 | off = le32_to_cpu(cmd->rxwrptr) & 0xffff; | |
1715 | iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off); | |
1716 | ||
1717 | off = le32_to_cpu(cmd->rxrdptr) & 0xffff; | |
1718 | iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off); | |
1719 | ||
1720 | off = le32_to_cpu(cmd->wcbbase1) & 0xffff; | |
1721 | iowrite32(cpu_to_le32(priv->txq[1].txd_dma), priv->sram + off); | |
1722 | ||
1723 | off = le32_to_cpu(cmd->wcbbase2) & 0xffff; | |
1724 | iowrite32(cpu_to_le32(priv->txq[2].txd_dma), priv->sram + off); | |
1725 | ||
1726 | off = le32_to_cpu(cmd->wcbbase3) & 0xffff; | |
1727 | iowrite32(cpu_to_le32(priv->txq[3].txd_dma), priv->sram + off); | |
1728 | } | |
1729 | ||
1730 | kfree(cmd); | |
1731 | return rc; | |
1732 | } | |
1733 | ||
1734 | /* | |
1735 | * CMD_SET_HW_SPEC. | |
1736 | */ | |
1737 | struct mwl8k_cmd_set_hw_spec { | |
1738 | struct mwl8k_cmd_pkt header; | |
1739 | __u8 hw_rev; | |
1740 | __u8 host_interface; | |
1741 | __le16 num_mcaddrs; | |
1742 | __u8 perm_addr[ETH_ALEN]; | |
1743 | __le16 region_code; | |
1744 | __le32 fw_rev; | |
1745 | __le32 ps_cookie; | |
1746 | __le32 caps; | |
1747 | __le32 rx_queue_ptr; | |
1748 | __le32 num_tx_queues; | |
1749 | __le32 tx_queue_ptrs[MWL8K_TX_QUEUES]; | |
1750 | __le32 flags; | |
1751 | __le32 num_tx_desc_per_queue; | |
1752 | __le32 total_rxd; | |
1753 | } __attribute__((packed)); | |
1754 | ||
1755 | #define MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT 0x00000080 | |
1756 | ||
1757 | static int mwl8k_cmd_set_hw_spec(struct ieee80211_hw *hw) | |
1758 | { | |
1759 | struct mwl8k_priv *priv = hw->priv; | |
1760 | struct mwl8k_cmd_set_hw_spec *cmd; | |
1761 | int rc; | |
1762 | int i; | |
1763 | ||
1764 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
1765 | if (cmd == NULL) | |
1766 | return -ENOMEM; | |
1767 | ||
1768 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_HW_SPEC); | |
1769 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
1770 | ||
1771 | cmd->ps_cookie = cpu_to_le32(priv->cookie_dma); | |
1772 | cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma); | |
1773 | cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES); | |
1774 | for (i = 0; i < MWL8K_TX_QUEUES; i++) | |
1775 | cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma); | |
1776 | cmd->flags = cpu_to_le32(MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT); | |
1777 | cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS); | |
1778 | cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS); | |
1779 | ||
1780 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
1781 | kfree(cmd); | |
1782 | ||
1783 | return rc; | |
1784 | } | |
1785 | ||
a66098da LB |
1786 | /* |
1787 | * CMD_MAC_MULTICAST_ADR. | |
1788 | */ | |
1789 | struct mwl8k_cmd_mac_multicast_adr { | |
1790 | struct mwl8k_cmd_pkt header; | |
1791 | __le16 action; | |
1792 | __le16 numaddr; | |
ce9e2e1b | 1793 | __u8 addr[0][ETH_ALEN]; |
a66098da LB |
1794 | }; |
1795 | ||
d5e30845 LB |
1796 | #define MWL8K_ENABLE_RX_DIRECTED 0x0001 |
1797 | #define MWL8K_ENABLE_RX_MULTICAST 0x0002 | |
1798 | #define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004 | |
1799 | #define MWL8K_ENABLE_RX_BROADCAST 0x0008 | |
ce9e2e1b | 1800 | |
e81cd2d6 | 1801 | static struct mwl8k_cmd_pkt * |
447ced07 | 1802 | __mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti, |
e81cd2d6 | 1803 | int mc_count, struct dev_addr_list *mclist) |
a66098da | 1804 | { |
e81cd2d6 | 1805 | struct mwl8k_priv *priv = hw->priv; |
a66098da | 1806 | struct mwl8k_cmd_mac_multicast_adr *cmd; |
e81cd2d6 | 1807 | int size; |
e81cd2d6 | 1808 | |
447ced07 | 1809 | if (allmulti || mc_count > priv->num_mcaddrs) { |
d5e30845 LB |
1810 | allmulti = 1; |
1811 | mc_count = 0; | |
1812 | } | |
e81cd2d6 LB |
1813 | |
1814 | size = sizeof(*cmd) + mc_count * ETH_ALEN; | |
ce9e2e1b | 1815 | |
e81cd2d6 | 1816 | cmd = kzalloc(size, GFP_ATOMIC); |
a66098da | 1817 | if (cmd == NULL) |
e81cd2d6 | 1818 | return NULL; |
a66098da LB |
1819 | |
1820 | cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR); | |
1821 | cmd->header.length = cpu_to_le16(size); | |
d5e30845 LB |
1822 | cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED | |
1823 | MWL8K_ENABLE_RX_BROADCAST); | |
1824 | ||
1825 | if (allmulti) { | |
1826 | cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST); | |
1827 | } else if (mc_count) { | |
1828 | int i; | |
1829 | ||
1830 | cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST); | |
1831 | cmd->numaddr = cpu_to_le16(mc_count); | |
1832 | for (i = 0; i < mc_count && mclist; i++) { | |
1833 | if (mclist->da_addrlen != ETH_ALEN) { | |
1834 | kfree(cmd); | |
1835 | return NULL; | |
1836 | } | |
1837 | memcpy(cmd->addr[i], mclist->da_addr, ETH_ALEN); | |
1838 | mclist = mclist->next; | |
a66098da | 1839 | } |
a66098da LB |
1840 | } |
1841 | ||
e81cd2d6 | 1842 | return &cmd->header; |
a66098da LB |
1843 | } |
1844 | ||
1845 | /* | |
55489b6e | 1846 | * CMD_GET_STAT. |
a66098da | 1847 | */ |
55489b6e | 1848 | struct mwl8k_cmd_get_stat { |
a66098da | 1849 | struct mwl8k_cmd_pkt header; |
a66098da LB |
1850 | __le32 stats[64]; |
1851 | } __attribute__((packed)); | |
1852 | ||
1853 | #define MWL8K_STAT_ACK_FAILURE 9 | |
1854 | #define MWL8K_STAT_RTS_FAILURE 12 | |
1855 | #define MWL8K_STAT_FCS_ERROR 24 | |
1856 | #define MWL8K_STAT_RTS_SUCCESS 11 | |
1857 | ||
55489b6e LB |
1858 | static int mwl8k_cmd_get_stat(struct ieee80211_hw *hw, |
1859 | struct ieee80211_low_level_stats *stats) | |
a66098da | 1860 | { |
55489b6e | 1861 | struct mwl8k_cmd_get_stat *cmd; |
a66098da LB |
1862 | int rc; |
1863 | ||
1864 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
1865 | if (cmd == NULL) | |
1866 | return -ENOMEM; | |
1867 | ||
1868 | cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT); | |
1869 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
a66098da LB |
1870 | |
1871 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
1872 | if (!rc) { | |
1873 | stats->dot11ACKFailureCount = | |
1874 | le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]); | |
1875 | stats->dot11RTSFailureCount = | |
1876 | le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]); | |
1877 | stats->dot11FCSErrorCount = | |
1878 | le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]); | |
1879 | stats->dot11RTSSuccessCount = | |
1880 | le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]); | |
1881 | } | |
1882 | kfree(cmd); | |
1883 | ||
1884 | return rc; | |
1885 | } | |
1886 | ||
1887 | /* | |
55489b6e | 1888 | * CMD_RADIO_CONTROL. |
a66098da | 1889 | */ |
55489b6e | 1890 | struct mwl8k_cmd_radio_control { |
a66098da LB |
1891 | struct mwl8k_cmd_pkt header; |
1892 | __le16 action; | |
1893 | __le16 control; | |
1894 | __le16 radio_on; | |
1895 | } __attribute__((packed)); | |
1896 | ||
c46563b7 | 1897 | static int |
55489b6e | 1898 | mwl8k_cmd_radio_control(struct ieee80211_hw *hw, bool enable, bool force) |
a66098da LB |
1899 | { |
1900 | struct mwl8k_priv *priv = hw->priv; | |
55489b6e | 1901 | struct mwl8k_cmd_radio_control *cmd; |
a66098da LB |
1902 | int rc; |
1903 | ||
c46563b7 | 1904 | if (enable == priv->radio_on && !force) |
a66098da LB |
1905 | return 0; |
1906 | ||
a66098da LB |
1907 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); |
1908 | if (cmd == NULL) | |
1909 | return -ENOMEM; | |
1910 | ||
1911 | cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL); | |
1912 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
1913 | cmd->action = cpu_to_le16(MWL8K_CMD_SET); | |
68ce3884 | 1914 | cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1); |
a66098da LB |
1915 | cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000); |
1916 | ||
1917 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
1918 | kfree(cmd); | |
1919 | ||
1920 | if (!rc) | |
c46563b7 | 1921 | priv->radio_on = enable; |
a66098da LB |
1922 | |
1923 | return rc; | |
1924 | } | |
1925 | ||
55489b6e | 1926 | static int mwl8k_cmd_radio_disable(struct ieee80211_hw *hw) |
c46563b7 | 1927 | { |
55489b6e | 1928 | return mwl8k_cmd_radio_control(hw, 0, 0); |
c46563b7 LB |
1929 | } |
1930 | ||
55489b6e | 1931 | static int mwl8k_cmd_radio_enable(struct ieee80211_hw *hw) |
c46563b7 | 1932 | { |
55489b6e | 1933 | return mwl8k_cmd_radio_control(hw, 1, 0); |
c46563b7 LB |
1934 | } |
1935 | ||
a66098da LB |
1936 | static int |
1937 | mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble) | |
1938 | { | |
99200a99 | 1939 | struct mwl8k_priv *priv = hw->priv; |
a66098da | 1940 | |
68ce3884 | 1941 | priv->radio_short_preamble = short_preamble; |
a66098da | 1942 | |
55489b6e | 1943 | return mwl8k_cmd_radio_control(hw, 1, 1); |
a66098da LB |
1944 | } |
1945 | ||
1946 | /* | |
55489b6e | 1947 | * CMD_RF_TX_POWER. |
a66098da LB |
1948 | */ |
1949 | #define MWL8K_TX_POWER_LEVEL_TOTAL 8 | |
1950 | ||
55489b6e | 1951 | struct mwl8k_cmd_rf_tx_power { |
a66098da LB |
1952 | struct mwl8k_cmd_pkt header; |
1953 | __le16 action; | |
1954 | __le16 support_level; | |
1955 | __le16 current_level; | |
1956 | __le16 reserved; | |
1957 | __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL]; | |
1958 | } __attribute__((packed)); | |
1959 | ||
55489b6e | 1960 | static int mwl8k_cmd_rf_tx_power(struct ieee80211_hw *hw, int dBm) |
a66098da | 1961 | { |
55489b6e | 1962 | struct mwl8k_cmd_rf_tx_power *cmd; |
a66098da LB |
1963 | int rc; |
1964 | ||
1965 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
1966 | if (cmd == NULL) | |
1967 | return -ENOMEM; | |
1968 | ||
1969 | cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER); | |
1970 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
1971 | cmd->action = cpu_to_le16(MWL8K_CMD_SET); | |
1972 | cmd->support_level = cpu_to_le16(dBm); | |
1973 | ||
1974 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
1975 | kfree(cmd); | |
1976 | ||
1977 | return rc; | |
1978 | } | |
1979 | ||
08b06347 LB |
1980 | /* |
1981 | * CMD_RF_ANTENNA. | |
1982 | */ | |
1983 | struct mwl8k_cmd_rf_antenna { | |
1984 | struct mwl8k_cmd_pkt header; | |
1985 | __le16 antenna; | |
1986 | __le16 mode; | |
1987 | } __attribute__((packed)); | |
1988 | ||
1989 | #define MWL8K_RF_ANTENNA_RX 1 | |
1990 | #define MWL8K_RF_ANTENNA_TX 2 | |
1991 | ||
1992 | static int | |
1993 | mwl8k_cmd_rf_antenna(struct ieee80211_hw *hw, int antenna, int mask) | |
1994 | { | |
1995 | struct mwl8k_cmd_rf_antenna *cmd; | |
1996 | int rc; | |
1997 | ||
1998 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
1999 | if (cmd == NULL) | |
2000 | return -ENOMEM; | |
2001 | ||
2002 | cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_ANTENNA); | |
2003 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2004 | cmd->antenna = cpu_to_le16(antenna); | |
2005 | cmd->mode = cpu_to_le16(mask); | |
2006 | ||
2007 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2008 | kfree(cmd); | |
2009 | ||
2010 | return rc; | |
2011 | } | |
2012 | ||
a66098da LB |
2013 | /* |
2014 | * CMD_SET_PRE_SCAN. | |
2015 | */ | |
2016 | struct mwl8k_cmd_set_pre_scan { | |
2017 | struct mwl8k_cmd_pkt header; | |
2018 | } __attribute__((packed)); | |
2019 | ||
2020 | static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw) | |
2021 | { | |
2022 | struct mwl8k_cmd_set_pre_scan *cmd; | |
2023 | int rc; | |
2024 | ||
2025 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2026 | if (cmd == NULL) | |
2027 | return -ENOMEM; | |
2028 | ||
2029 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN); | |
2030 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2031 | ||
2032 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2033 | kfree(cmd); | |
2034 | ||
2035 | return rc; | |
2036 | } | |
2037 | ||
2038 | /* | |
2039 | * CMD_SET_POST_SCAN. | |
2040 | */ | |
2041 | struct mwl8k_cmd_set_post_scan { | |
2042 | struct mwl8k_cmd_pkt header; | |
2043 | __le32 isibss; | |
d89173f2 | 2044 | __u8 bssid[ETH_ALEN]; |
a66098da LB |
2045 | } __attribute__((packed)); |
2046 | ||
2047 | static int | |
ce9e2e1b | 2048 | mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, __u8 *mac) |
a66098da LB |
2049 | { |
2050 | struct mwl8k_cmd_set_post_scan *cmd; | |
2051 | int rc; | |
2052 | ||
2053 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2054 | if (cmd == NULL) | |
2055 | return -ENOMEM; | |
2056 | ||
2057 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN); | |
2058 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2059 | cmd->isibss = 0; | |
d89173f2 | 2060 | memcpy(cmd->bssid, mac, ETH_ALEN); |
a66098da LB |
2061 | |
2062 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2063 | kfree(cmd); | |
2064 | ||
2065 | return rc; | |
2066 | } | |
2067 | ||
2068 | /* | |
2069 | * CMD_SET_RF_CHANNEL. | |
2070 | */ | |
2071 | struct mwl8k_cmd_set_rf_channel { | |
2072 | struct mwl8k_cmd_pkt header; | |
2073 | __le16 action; | |
2074 | __u8 current_channel; | |
2075 | __le32 channel_flags; | |
2076 | } __attribute__((packed)); | |
2077 | ||
2078 | static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw, | |
2079 | struct ieee80211_channel *channel) | |
2080 | { | |
2081 | struct mwl8k_cmd_set_rf_channel *cmd; | |
2082 | int rc; | |
2083 | ||
2084 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2085 | if (cmd == NULL) | |
2086 | return -ENOMEM; | |
2087 | ||
2088 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL); | |
2089 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2090 | cmd->action = cpu_to_le16(MWL8K_CMD_SET); | |
2091 | cmd->current_channel = channel->hw_value; | |
2092 | if (channel->band == IEEE80211_BAND_2GHZ) | |
2093 | cmd->channel_flags = cpu_to_le32(0x00000081); | |
2094 | else | |
2095 | cmd->channel_flags = cpu_to_le32(0x00000000); | |
2096 | ||
2097 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2098 | kfree(cmd); | |
2099 | ||
2100 | return rc; | |
2101 | } | |
2102 | ||
2103 | /* | |
55489b6e | 2104 | * CMD_SET_AID. |
a66098da | 2105 | */ |
55489b6e LB |
2106 | #define MWL8K_FRAME_PROT_DISABLED 0x00 |
2107 | #define MWL8K_FRAME_PROT_11G 0x07 | |
2108 | #define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02 | |
2109 | #define MWL8K_FRAME_PROT_11N_HT_ALL 0x06 | |
a66098da | 2110 | |
55489b6e LB |
2111 | struct mwl8k_cmd_update_set_aid { |
2112 | struct mwl8k_cmd_pkt header; | |
2113 | __le16 aid; | |
a66098da | 2114 | |
55489b6e LB |
2115 | /* AP's MAC address (BSSID) */ |
2116 | __u8 bssid[ETH_ALEN]; | |
2117 | __le16 protection_mode; | |
2118 | __u8 supp_rates[14]; | |
a66098da LB |
2119 | } __attribute__((packed)); |
2120 | ||
55489b6e LB |
2121 | static int |
2122 | mwl8k_cmd_set_aid(struct ieee80211_hw *hw, struct ieee80211_vif *vif) | |
a66098da | 2123 | { |
55489b6e | 2124 | struct mwl8k_vif *mv_vif = MWL8K_VIF(vif); |
55489b6e LB |
2125 | struct mwl8k_cmd_update_set_aid *cmd; |
2126 | u16 prot_mode; | |
a66098da LB |
2127 | int rc; |
2128 | ||
2129 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2130 | if (cmd == NULL) | |
2131 | return -ENOMEM; | |
2132 | ||
55489b6e | 2133 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID); |
a66098da | 2134 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); |
7dc6a7a7 | 2135 | cmd->aid = cpu_to_le16(vif->bss_conf.aid); |
a66098da | 2136 | |
55489b6e | 2137 | memcpy(cmd->bssid, mv_vif->bssid, ETH_ALEN); |
a66098da | 2138 | |
7dc6a7a7 | 2139 | if (vif->bss_conf.use_cts_prot) { |
55489b6e LB |
2140 | prot_mode = MWL8K_FRAME_PROT_11G; |
2141 | } else { | |
7dc6a7a7 | 2142 | switch (vif->bss_conf.ht_operation_mode & |
55489b6e LB |
2143 | IEEE80211_HT_OP_MODE_PROTECTION) { |
2144 | case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ: | |
2145 | prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY; | |
2146 | break; | |
2147 | case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED: | |
2148 | prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL; | |
2149 | break; | |
2150 | default: | |
2151 | prot_mode = MWL8K_FRAME_PROT_DISABLED; | |
2152 | break; | |
2153 | } | |
2154 | } | |
2155 | cmd->protection_mode = cpu_to_le16(prot_mode); | |
a66098da | 2156 | |
55489b6e | 2157 | memcpy(cmd->supp_rates, mwl8k_rateids, sizeof(mwl8k_rateids)); |
a66098da LB |
2158 | |
2159 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2160 | kfree(cmd); | |
2161 | ||
2162 | return rc; | |
2163 | } | |
2164 | ||
32060e1b | 2165 | /* |
55489b6e | 2166 | * CMD_SET_RATE. |
32060e1b | 2167 | */ |
55489b6e LB |
2168 | struct mwl8k_cmd_set_rate { |
2169 | struct mwl8k_cmd_pkt header; | |
2170 | __u8 legacy_rates[14]; | |
2171 | ||
2172 | /* Bitmap for supported MCS codes. */ | |
2173 | __u8 mcs_set[16]; | |
2174 | __u8 reserved[16]; | |
32060e1b LB |
2175 | } __attribute__((packed)); |
2176 | ||
55489b6e LB |
2177 | static int |
2178 | mwl8k_cmd_set_rate(struct ieee80211_hw *hw, struct ieee80211_vif *vif) | |
32060e1b | 2179 | { |
55489b6e | 2180 | struct mwl8k_cmd_set_rate *cmd; |
32060e1b LB |
2181 | int rc; |
2182 | ||
2183 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2184 | if (cmd == NULL) | |
2185 | return -ENOMEM; | |
2186 | ||
55489b6e | 2187 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE); |
32060e1b | 2188 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); |
55489b6e | 2189 | memcpy(cmd->legacy_rates, mwl8k_rateids, sizeof(mwl8k_rateids)); |
32060e1b LB |
2190 | |
2191 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2192 | kfree(cmd); | |
2193 | ||
2194 | return rc; | |
2195 | } | |
2196 | ||
a66098da | 2197 | /* |
55489b6e | 2198 | * CMD_FINALIZE_JOIN. |
a66098da | 2199 | */ |
55489b6e LB |
2200 | #define MWL8K_FJ_BEACON_MAXLEN 128 |
2201 | ||
2202 | struct mwl8k_cmd_finalize_join { | |
a66098da | 2203 | struct mwl8k_cmd_pkt header; |
55489b6e LB |
2204 | __le32 sleep_interval; /* Number of beacon periods to sleep */ |
2205 | __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN]; | |
a66098da LB |
2206 | } __attribute__((packed)); |
2207 | ||
55489b6e LB |
2208 | static int mwl8k_cmd_finalize_join(struct ieee80211_hw *hw, void *frame, |
2209 | int framelen, int dtim) | |
a66098da | 2210 | { |
55489b6e LB |
2211 | struct mwl8k_cmd_finalize_join *cmd; |
2212 | struct ieee80211_mgmt *payload = frame; | |
2213 | int payload_len; | |
a66098da LB |
2214 | int rc; |
2215 | ||
2216 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2217 | if (cmd == NULL) | |
2218 | return -ENOMEM; | |
2219 | ||
55489b6e | 2220 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN); |
a66098da | 2221 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); |
55489b6e LB |
2222 | cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1); |
2223 | ||
2224 | payload_len = framelen - ieee80211_hdrlen(payload->frame_control); | |
2225 | if (payload_len < 0) | |
2226 | payload_len = 0; | |
2227 | else if (payload_len > MWL8K_FJ_BEACON_MAXLEN) | |
2228 | payload_len = MWL8K_FJ_BEACON_MAXLEN; | |
2229 | ||
2230 | memcpy(cmd->beacon_data, &payload->u.beacon, payload_len); | |
a66098da LB |
2231 | |
2232 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2233 | kfree(cmd); | |
2234 | ||
2235 | return rc; | |
2236 | } | |
2237 | ||
2238 | /* | |
55489b6e | 2239 | * CMD_SET_RTS_THRESHOLD. |
a66098da | 2240 | */ |
55489b6e | 2241 | struct mwl8k_cmd_set_rts_threshold { |
a66098da LB |
2242 | struct mwl8k_cmd_pkt header; |
2243 | __le16 action; | |
55489b6e | 2244 | __le16 threshold; |
a66098da LB |
2245 | } __attribute__((packed)); |
2246 | ||
55489b6e LB |
2247 | static int mwl8k_cmd_set_rts_threshold(struct ieee80211_hw *hw, |
2248 | u16 action, u16 threshold) | |
a66098da | 2249 | { |
55489b6e | 2250 | struct mwl8k_cmd_set_rts_threshold *cmd; |
a66098da LB |
2251 | int rc; |
2252 | ||
2253 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2254 | if (cmd == NULL) | |
2255 | return -ENOMEM; | |
2256 | ||
55489b6e | 2257 | cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD); |
a66098da | 2258 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); |
55489b6e LB |
2259 | cmd->action = cpu_to_le16(action); |
2260 | cmd->threshold = cpu_to_le16(threshold); | |
a66098da LB |
2261 | |
2262 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2263 | kfree(cmd); | |
2264 | ||
a66098da LB |
2265 | return rc; |
2266 | } | |
2267 | ||
2268 | /* | |
55489b6e | 2269 | * CMD_SET_SLOT. |
a66098da | 2270 | */ |
55489b6e | 2271 | struct mwl8k_cmd_set_slot { |
a66098da LB |
2272 | struct mwl8k_cmd_pkt header; |
2273 | __le16 action; | |
55489b6e | 2274 | __u8 short_slot; |
a66098da LB |
2275 | } __attribute__((packed)); |
2276 | ||
55489b6e | 2277 | static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time) |
a66098da | 2278 | { |
55489b6e | 2279 | struct mwl8k_cmd_set_slot *cmd; |
a66098da LB |
2280 | int rc; |
2281 | ||
2282 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2283 | if (cmd == NULL) | |
2284 | return -ENOMEM; | |
2285 | ||
55489b6e | 2286 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT); |
a66098da | 2287 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); |
55489b6e LB |
2288 | cmd->action = cpu_to_le16(MWL8K_CMD_SET); |
2289 | cmd->short_slot = short_slot_time; | |
a66098da LB |
2290 | |
2291 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2292 | kfree(cmd); | |
2293 | ||
2294 | return rc; | |
2295 | } | |
2296 | ||
2297 | /* | |
2298 | * CMD_SET_EDCA_PARAMS. | |
2299 | */ | |
2300 | struct mwl8k_cmd_set_edca_params { | |
2301 | struct mwl8k_cmd_pkt header; | |
2302 | ||
2303 | /* See MWL8K_SET_EDCA_XXX below */ | |
2304 | __le16 action; | |
2305 | ||
2306 | /* TX opportunity in units of 32 us */ | |
2307 | __le16 txop; | |
2308 | ||
2e484c89 LB |
2309 | union { |
2310 | struct { | |
2311 | /* Log exponent of max contention period: 0...15 */ | |
2312 | __le32 log_cw_max; | |
2313 | ||
2314 | /* Log exponent of min contention period: 0...15 */ | |
2315 | __le32 log_cw_min; | |
2316 | ||
2317 | /* Adaptive interframe spacing in units of 32us */ | |
2318 | __u8 aifs; | |
2319 | ||
2320 | /* TX queue to configure */ | |
2321 | __u8 txq; | |
2322 | } ap; | |
2323 | struct { | |
2324 | /* Log exponent of max contention period: 0...15 */ | |
2325 | __u8 log_cw_max; | |
a66098da | 2326 | |
2e484c89 LB |
2327 | /* Log exponent of min contention period: 0...15 */ |
2328 | __u8 log_cw_min; | |
a66098da | 2329 | |
2e484c89 LB |
2330 | /* Adaptive interframe spacing in units of 32us */ |
2331 | __u8 aifs; | |
a66098da | 2332 | |
2e484c89 LB |
2333 | /* TX queue to configure */ |
2334 | __u8 txq; | |
2335 | } sta; | |
2336 | }; | |
a66098da LB |
2337 | } __attribute__((packed)); |
2338 | ||
a66098da LB |
2339 | #define MWL8K_SET_EDCA_CW 0x01 |
2340 | #define MWL8K_SET_EDCA_TXOP 0x02 | |
2341 | #define MWL8K_SET_EDCA_AIFS 0x04 | |
2342 | ||
2343 | #define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \ | |
2344 | MWL8K_SET_EDCA_TXOP | \ | |
2345 | MWL8K_SET_EDCA_AIFS) | |
2346 | ||
2347 | static int | |
55489b6e LB |
2348 | mwl8k_cmd_set_edca_params(struct ieee80211_hw *hw, __u8 qnum, |
2349 | __u16 cw_min, __u16 cw_max, | |
2350 | __u8 aifs, __u16 txop) | |
a66098da | 2351 | { |
2e484c89 | 2352 | struct mwl8k_priv *priv = hw->priv; |
a66098da | 2353 | struct mwl8k_cmd_set_edca_params *cmd; |
a66098da LB |
2354 | int rc; |
2355 | ||
2356 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2357 | if (cmd == NULL) | |
2358 | return -ENOMEM; | |
2359 | ||
22995b24 LB |
2360 | /* |
2361 | * Queues 0 (BE) and 1 (BK) are swapped in hardware for | |
2362 | * this call. | |
2363 | */ | |
2364 | qnum ^= !(qnum >> 1); | |
2365 | ||
a66098da LB |
2366 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS); |
2367 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
a66098da LB |
2368 | cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL); |
2369 | cmd->txop = cpu_to_le16(txop); | |
2e484c89 LB |
2370 | if (priv->ap_fw) { |
2371 | cmd->ap.log_cw_max = cpu_to_le32(ilog2(cw_max + 1)); | |
2372 | cmd->ap.log_cw_min = cpu_to_le32(ilog2(cw_min + 1)); | |
2373 | cmd->ap.aifs = aifs; | |
2374 | cmd->ap.txq = qnum; | |
2375 | } else { | |
2376 | cmd->sta.log_cw_max = (u8)ilog2(cw_max + 1); | |
2377 | cmd->sta.log_cw_min = (u8)ilog2(cw_min + 1); | |
2378 | cmd->sta.aifs = aifs; | |
2379 | cmd->sta.txq = qnum; | |
2380 | } | |
a66098da LB |
2381 | |
2382 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2383 | kfree(cmd); | |
2384 | ||
2385 | return rc; | |
2386 | } | |
2387 | ||
2388 | /* | |
55489b6e | 2389 | * CMD_SET_WMM_MODE. |
a66098da | 2390 | */ |
55489b6e | 2391 | struct mwl8k_cmd_set_wmm_mode { |
a66098da | 2392 | struct mwl8k_cmd_pkt header; |
55489b6e | 2393 | __le16 action; |
a66098da LB |
2394 | } __attribute__((packed)); |
2395 | ||
55489b6e | 2396 | static int mwl8k_cmd_set_wmm_mode(struct ieee80211_hw *hw, bool enable) |
a66098da | 2397 | { |
55489b6e LB |
2398 | struct mwl8k_priv *priv = hw->priv; |
2399 | struct mwl8k_cmd_set_wmm_mode *cmd; | |
a66098da LB |
2400 | int rc; |
2401 | ||
a66098da LB |
2402 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); |
2403 | if (cmd == NULL) | |
2404 | return -ENOMEM; | |
2405 | ||
55489b6e | 2406 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE); |
a66098da | 2407 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); |
55489b6e | 2408 | cmd->action = cpu_to_le16(!!enable); |
a66098da LB |
2409 | |
2410 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2411 | kfree(cmd); | |
16cec43d | 2412 | |
55489b6e LB |
2413 | if (!rc) |
2414 | priv->wmm_enabled = enable; | |
a66098da LB |
2415 | |
2416 | return rc; | |
2417 | } | |
2418 | ||
2419 | /* | |
55489b6e | 2420 | * CMD_MIMO_CONFIG. |
a66098da | 2421 | */ |
55489b6e LB |
2422 | struct mwl8k_cmd_mimo_config { |
2423 | struct mwl8k_cmd_pkt header; | |
2424 | __le32 action; | |
2425 | __u8 rx_antenna_map; | |
2426 | __u8 tx_antenna_map; | |
a66098da LB |
2427 | } __attribute__((packed)); |
2428 | ||
55489b6e | 2429 | static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx) |
a66098da | 2430 | { |
55489b6e | 2431 | struct mwl8k_cmd_mimo_config *cmd; |
a66098da LB |
2432 | int rc; |
2433 | ||
2434 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2435 | if (cmd == NULL) | |
2436 | return -ENOMEM; | |
2437 | ||
55489b6e | 2438 | cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG); |
a66098da | 2439 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); |
55489b6e LB |
2440 | cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET); |
2441 | cmd->rx_antenna_map = rx; | |
2442 | cmd->tx_antenna_map = tx; | |
a66098da LB |
2443 | |
2444 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2445 | kfree(cmd); | |
2446 | ||
2447 | return rc; | |
2448 | } | |
2449 | ||
2450 | /* | |
2451 | * CMD_USE_FIXED_RATE. | |
2452 | */ | |
2453 | #define MWL8K_RATE_TABLE_SIZE 8 | |
2454 | #define MWL8K_UCAST_RATE 0 | |
a66098da LB |
2455 | #define MWL8K_USE_AUTO_RATE 0x0002 |
2456 | ||
2457 | struct mwl8k_rate_entry { | |
2458 | /* Set to 1 if HT rate, 0 if legacy. */ | |
2459 | __le32 is_ht_rate; | |
2460 | ||
2461 | /* Set to 1 to use retry_count field. */ | |
2462 | __le32 enable_retry; | |
2463 | ||
2464 | /* Specified legacy rate or MCS. */ | |
2465 | __le32 rate; | |
2466 | ||
2467 | /* Number of allowed retries. */ | |
2468 | __le32 retry_count; | |
2469 | } __attribute__((packed)); | |
2470 | ||
2471 | struct mwl8k_rate_table { | |
2472 | /* 1 to allow specified rate and below */ | |
2473 | __le32 allow_rate_drop; | |
2474 | __le32 num_rates; | |
2475 | struct mwl8k_rate_entry rate_entry[MWL8K_RATE_TABLE_SIZE]; | |
2476 | } __attribute__((packed)); | |
2477 | ||
2478 | struct mwl8k_cmd_use_fixed_rate { | |
2479 | struct mwl8k_cmd_pkt header; | |
2480 | __le32 action; | |
2481 | struct mwl8k_rate_table rate_table; | |
2482 | ||
2483 | /* Unicast, Broadcast or Multicast */ | |
2484 | __le32 rate_type; | |
2485 | __le32 reserved1; | |
2486 | __le32 reserved2; | |
2487 | } __attribute__((packed)); | |
2488 | ||
2489 | static int mwl8k_cmd_use_fixed_rate(struct ieee80211_hw *hw, | |
2490 | u32 action, u32 rate_type, struct mwl8k_rate_table *rate_table) | |
2491 | { | |
2492 | struct mwl8k_cmd_use_fixed_rate *cmd; | |
2493 | int count; | |
2494 | int rc; | |
2495 | ||
2496 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2497 | if (cmd == NULL) | |
2498 | return -ENOMEM; | |
2499 | ||
2500 | cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE); | |
2501 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2502 | ||
2503 | cmd->action = cpu_to_le32(action); | |
2504 | cmd->rate_type = cpu_to_le32(rate_type); | |
2505 | ||
2506 | if (rate_table != NULL) { | |
c2c357ce LB |
2507 | /* |
2508 | * Copy over each field manually so that endian | |
2509 | * conversion can be done. | |
2510 | */ | |
a66098da LB |
2511 | cmd->rate_table.allow_rate_drop = |
2512 | cpu_to_le32(rate_table->allow_rate_drop); | |
2513 | cmd->rate_table.num_rates = | |
2514 | cpu_to_le32(rate_table->num_rates); | |
2515 | ||
2516 | for (count = 0; count < rate_table->num_rates; count++) { | |
2517 | struct mwl8k_rate_entry *dst = | |
2518 | &cmd->rate_table.rate_entry[count]; | |
2519 | struct mwl8k_rate_entry *src = | |
2520 | &rate_table->rate_entry[count]; | |
2521 | ||
2522 | dst->is_ht_rate = cpu_to_le32(src->is_ht_rate); | |
2523 | dst->enable_retry = cpu_to_le32(src->enable_retry); | |
2524 | dst->rate = cpu_to_le32(src->rate); | |
2525 | dst->retry_count = cpu_to_le32(src->retry_count); | |
2526 | } | |
2527 | } | |
2528 | ||
2529 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2530 | kfree(cmd); | |
2531 | ||
2532 | return rc; | |
2533 | } | |
2534 | ||
55489b6e LB |
2535 | /* |
2536 | * CMD_ENABLE_SNIFFER. | |
2537 | */ | |
2538 | struct mwl8k_cmd_enable_sniffer { | |
2539 | struct mwl8k_cmd_pkt header; | |
2540 | __le32 action; | |
2541 | } __attribute__((packed)); | |
2542 | ||
2543 | static int mwl8k_cmd_enable_sniffer(struct ieee80211_hw *hw, bool enable) | |
2544 | { | |
2545 | struct mwl8k_cmd_enable_sniffer *cmd; | |
2546 | int rc; | |
2547 | ||
2548 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2549 | if (cmd == NULL) | |
2550 | return -ENOMEM; | |
2551 | ||
2552 | cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER); | |
2553 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2554 | cmd->action = cpu_to_le32(!!enable); | |
2555 | ||
2556 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2557 | kfree(cmd); | |
2558 | ||
2559 | return rc; | |
2560 | } | |
2561 | ||
2562 | /* | |
2563 | * CMD_SET_MAC_ADDR. | |
2564 | */ | |
2565 | struct mwl8k_cmd_set_mac_addr { | |
2566 | struct mwl8k_cmd_pkt header; | |
2567 | union { | |
2568 | struct { | |
2569 | __le16 mac_type; | |
2570 | __u8 mac_addr[ETH_ALEN]; | |
2571 | } mbss; | |
2572 | __u8 mac_addr[ETH_ALEN]; | |
2573 | }; | |
2574 | } __attribute__((packed)); | |
2575 | ||
2576 | static int mwl8k_cmd_set_mac_addr(struct ieee80211_hw *hw, u8 *mac) | |
2577 | { | |
2578 | struct mwl8k_priv *priv = hw->priv; | |
2579 | struct mwl8k_cmd_set_mac_addr *cmd; | |
2580 | int rc; | |
2581 | ||
2582 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2583 | if (cmd == NULL) | |
2584 | return -ENOMEM; | |
2585 | ||
2586 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR); | |
2587 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2588 | if (priv->ap_fw) { | |
2589 | cmd->mbss.mac_type = 0; | |
2590 | memcpy(cmd->mbss.mac_addr, mac, ETH_ALEN); | |
2591 | } else { | |
2592 | memcpy(cmd->mac_addr, mac, ETH_ALEN); | |
2593 | } | |
2594 | ||
2595 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2596 | kfree(cmd); | |
2597 | ||
2598 | return rc; | |
2599 | } | |
2600 | ||
2601 | /* | |
2602 | * CMD_SET_RATEADAPT_MODE. | |
2603 | */ | |
2604 | struct mwl8k_cmd_set_rate_adapt_mode { | |
2605 | struct mwl8k_cmd_pkt header; | |
2606 | __le16 action; | |
2607 | __le16 mode; | |
2608 | } __attribute__((packed)); | |
2609 | ||
2610 | static int mwl8k_cmd_set_rateadapt_mode(struct ieee80211_hw *hw, __u16 mode) | |
2611 | { | |
2612 | struct mwl8k_cmd_set_rate_adapt_mode *cmd; | |
2613 | int rc; | |
2614 | ||
2615 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2616 | if (cmd == NULL) | |
2617 | return -ENOMEM; | |
2618 | ||
2619 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE); | |
2620 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2621 | cmd->action = cpu_to_le16(MWL8K_CMD_SET); | |
2622 | cmd->mode = cpu_to_le16(mode); | |
2623 | ||
2624 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2625 | kfree(cmd); | |
2626 | ||
2627 | return rc; | |
2628 | } | |
2629 | ||
2630 | /* | |
2631 | * CMD_UPDATE_STADB. | |
2632 | */ | |
2633 | struct mwl8k_cmd_update_stadb { | |
2634 | struct mwl8k_cmd_pkt header; | |
2635 | ||
2636 | /* See STADB_ACTION_TYPE */ | |
2637 | __le32 action; | |
2638 | ||
2639 | /* Peer MAC address */ | |
2640 | __u8 peer_addr[ETH_ALEN]; | |
2641 | ||
2642 | __le32 reserved; | |
2643 | ||
2644 | /* Peer info - valid during add/update. */ | |
2645 | struct peer_capability_info peer_info; | |
2646 | } __attribute__((packed)); | |
2647 | ||
2648 | static int mwl8k_cmd_update_stadb(struct ieee80211_hw *hw, | |
2649 | struct ieee80211_vif *vif, __u32 action) | |
2650 | { | |
2651 | struct mwl8k_vif *mv_vif = MWL8K_VIF(vif); | |
55489b6e LB |
2652 | struct mwl8k_cmd_update_stadb *cmd; |
2653 | struct peer_capability_info *peer_info; | |
2654 | int rc; | |
2655 | ||
2656 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2657 | if (cmd == NULL) | |
2658 | return -ENOMEM; | |
2659 | ||
2660 | cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB); | |
2661 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2662 | ||
2663 | cmd->action = cpu_to_le32(action); | |
2664 | peer_info = &cmd->peer_info; | |
2665 | memcpy(cmd->peer_addr, mv_vif->bssid, ETH_ALEN); | |
2666 | ||
2667 | switch (action) { | |
2668 | case MWL8K_STA_DB_ADD_ENTRY: | |
2669 | case MWL8K_STA_DB_MODIFY_ENTRY: | |
2670 | /* Build peer_info block */ | |
2671 | peer_info->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT; | |
7dc6a7a7 LB |
2672 | peer_info->basic_caps = |
2673 | cpu_to_le16(vif->bss_conf.assoc_capability); | |
55489b6e LB |
2674 | memcpy(peer_info->legacy_rates, mwl8k_rateids, |
2675 | sizeof(mwl8k_rateids)); | |
2676 | peer_info->interop = 1; | |
2677 | peer_info->amsdu_enabled = 0; | |
2678 | ||
2679 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2680 | if (rc == 0) | |
2681 | mv_vif->peer_id = peer_info->station_id; | |
2682 | ||
2683 | break; | |
2684 | ||
2685 | case MWL8K_STA_DB_DEL_ENTRY: | |
2686 | case MWL8K_STA_DB_FLUSH: | |
2687 | default: | |
2688 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2689 | if (rc == 0) | |
2690 | mv_vif->peer_id = 0; | |
2691 | break; | |
2692 | } | |
2693 | kfree(cmd); | |
2694 | ||
2695 | return rc; | |
2696 | } | |
2697 | ||
a66098da LB |
2698 | |
2699 | /* | |
2700 | * Interrupt handling. | |
2701 | */ | |
2702 | static irqreturn_t mwl8k_interrupt(int irq, void *dev_id) | |
2703 | { | |
2704 | struct ieee80211_hw *hw = dev_id; | |
2705 | struct mwl8k_priv *priv = hw->priv; | |
2706 | u32 status; | |
2707 | ||
2708 | status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS); | |
2709 | iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS); | |
2710 | ||
a66098da LB |
2711 | if (!status) |
2712 | return IRQ_NONE; | |
2713 | ||
2714 | if (status & MWL8K_A2H_INT_TX_DONE) | |
2715 | tasklet_schedule(&priv->tx_reclaim_task); | |
2716 | ||
2717 | if (status & MWL8K_A2H_INT_RX_READY) { | |
2718 | while (rxq_process(hw, 0, 1)) | |
2719 | rxq_refill(hw, 0, 1); | |
2720 | } | |
2721 | ||
2722 | if (status & MWL8K_A2H_INT_OPC_DONE) { | |
618952a7 | 2723 | if (priv->hostcmd_wait != NULL) |
a66098da | 2724 | complete(priv->hostcmd_wait); |
a66098da LB |
2725 | } |
2726 | ||
2727 | if (status & MWL8K_A2H_INT_QUEUE_EMPTY) { | |
618952a7 | 2728 | if (!mutex_is_locked(&priv->fw_mutex) && |
88de754a | 2729 | priv->radio_on && priv->pending_tx_pkts) |
618952a7 | 2730 | mwl8k_tx_start(priv); |
a66098da LB |
2731 | } |
2732 | ||
2733 | return IRQ_HANDLED; | |
2734 | } | |
2735 | ||
2736 | ||
2737 | /* | |
2738 | * Core driver operations. | |
2739 | */ | |
2740 | static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb) | |
2741 | { | |
2742 | struct mwl8k_priv *priv = hw->priv; | |
2743 | int index = skb_get_queue_mapping(skb); | |
2744 | int rc; | |
2745 | ||
2746 | if (priv->current_channel == NULL) { | |
2747 | printk(KERN_DEBUG "%s: dropped TX frame since radio " | |
c2c357ce | 2748 | "disabled\n", wiphy_name(hw->wiphy)); |
a66098da LB |
2749 | dev_kfree_skb(skb); |
2750 | return NETDEV_TX_OK; | |
2751 | } | |
2752 | ||
2753 | rc = mwl8k_txq_xmit(hw, index, skb); | |
2754 | ||
2755 | return rc; | |
2756 | } | |
2757 | ||
a66098da LB |
2758 | static int mwl8k_start(struct ieee80211_hw *hw) |
2759 | { | |
a66098da LB |
2760 | struct mwl8k_priv *priv = hw->priv; |
2761 | int rc; | |
2762 | ||
a0607fd3 | 2763 | rc = request_irq(priv->pdev->irq, mwl8k_interrupt, |
a66098da LB |
2764 | IRQF_SHARED, MWL8K_NAME, hw); |
2765 | if (rc) { | |
2766 | printk(KERN_ERR "%s: failed to register IRQ handler\n", | |
c2c357ce | 2767 | wiphy_name(hw->wiphy)); |
2ec610cb | 2768 | return -EIO; |
a66098da LB |
2769 | } |
2770 | ||
2ec610cb LB |
2771 | /* Enable tx reclaim tasklet */ |
2772 | tasklet_enable(&priv->tx_reclaim_task); | |
2773 | ||
a66098da | 2774 | /* Enable interrupts */ |
c23b5a69 | 2775 | iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); |
a66098da | 2776 | |
2ec610cb LB |
2777 | rc = mwl8k_fw_lock(hw); |
2778 | if (!rc) { | |
55489b6e | 2779 | rc = mwl8k_cmd_radio_enable(hw); |
a66098da | 2780 | |
5e4cf166 LB |
2781 | if (!priv->ap_fw) { |
2782 | if (!rc) | |
55489b6e | 2783 | rc = mwl8k_cmd_enable_sniffer(hw, 0); |
a66098da | 2784 | |
5e4cf166 LB |
2785 | if (!rc) |
2786 | rc = mwl8k_cmd_set_pre_scan(hw); | |
2787 | ||
2788 | if (!rc) | |
2789 | rc = mwl8k_cmd_set_post_scan(hw, | |
2790 | "\x00\x00\x00\x00\x00\x00"); | |
2791 | } | |
2ec610cb LB |
2792 | |
2793 | if (!rc) | |
55489b6e | 2794 | rc = mwl8k_cmd_set_rateadapt_mode(hw, 0); |
a66098da | 2795 | |
2ec610cb | 2796 | if (!rc) |
55489b6e | 2797 | rc = mwl8k_cmd_set_wmm_mode(hw, 0); |
a66098da | 2798 | |
2ec610cb LB |
2799 | mwl8k_fw_unlock(hw); |
2800 | } | |
2801 | ||
2802 | if (rc) { | |
2803 | iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); | |
2804 | free_irq(priv->pdev->irq, hw); | |
2805 | tasklet_disable(&priv->tx_reclaim_task); | |
2806 | } | |
a66098da LB |
2807 | |
2808 | return rc; | |
2809 | } | |
2810 | ||
a66098da LB |
2811 | static void mwl8k_stop(struct ieee80211_hw *hw) |
2812 | { | |
a66098da LB |
2813 | struct mwl8k_priv *priv = hw->priv; |
2814 | int i; | |
2815 | ||
55489b6e | 2816 | mwl8k_cmd_radio_disable(hw); |
a66098da LB |
2817 | |
2818 | ieee80211_stop_queues(hw); | |
2819 | ||
a66098da | 2820 | /* Disable interrupts */ |
a66098da | 2821 | iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); |
a66098da LB |
2822 | free_irq(priv->pdev->irq, hw); |
2823 | ||
2824 | /* Stop finalize join worker */ | |
2825 | cancel_work_sync(&priv->finalize_join_worker); | |
2826 | if (priv->beacon_skb != NULL) | |
2827 | dev_kfree_skb(priv->beacon_skb); | |
2828 | ||
2829 | /* Stop tx reclaim tasklet */ | |
2830 | tasklet_disable(&priv->tx_reclaim_task); | |
2831 | ||
a66098da LB |
2832 | /* Return all skbs to mac80211 */ |
2833 | for (i = 0; i < MWL8K_TX_QUEUES; i++) | |
2834 | mwl8k_txq_reclaim(hw, i, 1); | |
2835 | } | |
2836 | ||
2837 | static int mwl8k_add_interface(struct ieee80211_hw *hw, | |
1ed32e4f | 2838 | struct ieee80211_vif *vif) |
a66098da LB |
2839 | { |
2840 | struct mwl8k_priv *priv = hw->priv; | |
2841 | struct mwl8k_vif *mwl8k_vif; | |
2842 | ||
2843 | /* | |
2844 | * We only support one active interface at a time. | |
2845 | */ | |
2846 | if (priv->vif != NULL) | |
2847 | return -EBUSY; | |
2848 | ||
2849 | /* | |
2850 | * We only support managed interfaces for now. | |
2851 | */ | |
1ed32e4f | 2852 | if (vif->type != NL80211_IFTYPE_STATION) |
a66098da LB |
2853 | return -EINVAL; |
2854 | ||
a43c49a8 LB |
2855 | /* |
2856 | * Reject interface creation if sniffer mode is active, as | |
2857 | * STA operation is mutually exclusive with hardware sniffer | |
2858 | * mode. | |
2859 | */ | |
2860 | if (priv->sniffer_enabled) { | |
2861 | printk(KERN_INFO "%s: unable to create STA " | |
2862 | "interface due to sniffer mode being enabled\n", | |
2863 | wiphy_name(hw->wiphy)); | |
2864 | return -EINVAL; | |
2865 | } | |
2866 | ||
a66098da | 2867 | /* Clean out driver private area */ |
1ed32e4f | 2868 | mwl8k_vif = MWL8K_VIF(vif); |
a66098da LB |
2869 | memset(mwl8k_vif, 0, sizeof(*mwl8k_vif)); |
2870 | ||
32060e1b | 2871 | /* Set and save the mac address */ |
1ed32e4f JB |
2872 | mwl8k_cmd_set_mac_addr(hw, vif->addr); |
2873 | memcpy(mwl8k_vif->mac_addr, vif->addr, ETH_ALEN); | |
a66098da | 2874 | |
a66098da LB |
2875 | /* Set Initial sequence number to zero */ |
2876 | mwl8k_vif->seqno = 0; | |
2877 | ||
1ed32e4f | 2878 | priv->vif = vif; |
a66098da LB |
2879 | priv->current_channel = NULL; |
2880 | ||
2881 | return 0; | |
2882 | } | |
2883 | ||
2884 | static void mwl8k_remove_interface(struct ieee80211_hw *hw, | |
1ed32e4f | 2885 | struct ieee80211_vif *vif) |
a66098da LB |
2886 | { |
2887 | struct mwl8k_priv *priv = hw->priv; | |
2888 | ||
2889 | if (priv->vif == NULL) | |
2890 | return; | |
2891 | ||
55489b6e | 2892 | mwl8k_cmd_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00"); |
32060e1b | 2893 | |
a66098da LB |
2894 | priv->vif = NULL; |
2895 | } | |
2896 | ||
ee03a932 | 2897 | static int mwl8k_config(struct ieee80211_hw *hw, u32 changed) |
a66098da | 2898 | { |
a66098da LB |
2899 | struct ieee80211_conf *conf = &hw->conf; |
2900 | struct mwl8k_priv *priv = hw->priv; | |
ee03a932 | 2901 | int rc; |
a66098da | 2902 | |
7595d67a | 2903 | if (conf->flags & IEEE80211_CONF_IDLE) { |
55489b6e | 2904 | mwl8k_cmd_radio_disable(hw); |
7595d67a | 2905 | priv->current_channel = NULL; |
ee03a932 | 2906 | return 0; |
7595d67a LB |
2907 | } |
2908 | ||
ee03a932 LB |
2909 | rc = mwl8k_fw_lock(hw); |
2910 | if (rc) | |
2911 | return rc; | |
a66098da | 2912 | |
55489b6e | 2913 | rc = mwl8k_cmd_radio_enable(hw); |
ee03a932 LB |
2914 | if (rc) |
2915 | goto out; | |
a66098da | 2916 | |
ee03a932 LB |
2917 | rc = mwl8k_cmd_set_rf_channel(hw, conf->channel); |
2918 | if (rc) | |
2919 | goto out; | |
2920 | ||
2921 | priv->current_channel = conf->channel; | |
a66098da LB |
2922 | |
2923 | if (conf->power_level > 18) | |
2924 | conf->power_level = 18; | |
55489b6e | 2925 | rc = mwl8k_cmd_rf_tx_power(hw, conf->power_level); |
ee03a932 LB |
2926 | if (rc) |
2927 | goto out; | |
a66098da | 2928 | |
08b06347 LB |
2929 | if (priv->ap_fw) { |
2930 | rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_RX, 0x7); | |
2931 | if (!rc) | |
2932 | rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_TX, 0x7); | |
2933 | } else { | |
2934 | rc = mwl8k_cmd_mimo_config(hw, 0x7, 0x7); | |
2935 | } | |
a66098da | 2936 | |
ee03a932 LB |
2937 | out: |
2938 | mwl8k_fw_unlock(hw); | |
a66098da | 2939 | |
ee03a932 | 2940 | return rc; |
a66098da LB |
2941 | } |
2942 | ||
3a980d0a LB |
2943 | static void mwl8k_bss_info_changed(struct ieee80211_hw *hw, |
2944 | struct ieee80211_vif *vif, | |
2945 | struct ieee80211_bss_conf *info, | |
2946 | u32 changed) | |
a66098da | 2947 | { |
a66098da LB |
2948 | struct mwl8k_priv *priv = hw->priv; |
2949 | struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif); | |
3a980d0a LB |
2950 | int rc; |
2951 | ||
3a980d0a LB |
2952 | if ((changed & BSS_CHANGED_ASSOC) == 0) |
2953 | return; | |
a66098da | 2954 | |
a66098da LB |
2955 | priv->capture_beacon = false; |
2956 | ||
3a980d0a | 2957 | rc = mwl8k_fw_lock(hw); |
942457d6 | 2958 | if (rc) |
3a980d0a LB |
2959 | return; |
2960 | ||
7dc6a7a7 LB |
2961 | if (vif->bss_conf.assoc) { |
2962 | memcpy(mwl8k_vif->bssid, vif->bss_conf.bssid, ETH_ALEN); | |
d1844d77 | 2963 | |
a66098da | 2964 | /* Install rates */ |
55489b6e | 2965 | rc = mwl8k_cmd_set_rate(hw, vif); |
3a980d0a LB |
2966 | if (rc) |
2967 | goto out; | |
a66098da LB |
2968 | |
2969 | /* Turn on rate adaptation */ | |
3a980d0a LB |
2970 | rc = mwl8k_cmd_use_fixed_rate(hw, MWL8K_USE_AUTO_RATE, |
2971 | MWL8K_UCAST_RATE, NULL); | |
2972 | if (rc) | |
2973 | goto out; | |
a66098da LB |
2974 | |
2975 | /* Set radio preamble */ | |
7dc6a7a7 LB |
2976 | rc = mwl8k_set_radio_preamble(hw, |
2977 | vif->bss_conf.use_short_preamble); | |
3a980d0a LB |
2978 | if (rc) |
2979 | goto out; | |
a66098da LB |
2980 | |
2981 | /* Set slot time */ | |
7dc6a7a7 | 2982 | rc = mwl8k_cmd_set_slot(hw, vif->bss_conf.use_short_slot); |
3a980d0a LB |
2983 | if (rc) |
2984 | goto out; | |
a66098da LB |
2985 | |
2986 | /* Update peer rate info */ | |
55489b6e | 2987 | rc = mwl8k_cmd_update_stadb(hw, vif, |
3a980d0a LB |
2988 | MWL8K_STA_DB_MODIFY_ENTRY); |
2989 | if (rc) | |
2990 | goto out; | |
a66098da LB |
2991 | |
2992 | /* Set AID */ | |
3a980d0a LB |
2993 | rc = mwl8k_cmd_set_aid(hw, vif); |
2994 | if (rc) | |
2995 | goto out; | |
a66098da LB |
2996 | |
2997 | /* | |
2998 | * Finalize the join. Tell rx handler to process | |
2999 | * next beacon from our BSSID. | |
3000 | */ | |
d89173f2 | 3001 | memcpy(priv->capture_bssid, mwl8k_vif->bssid, ETH_ALEN); |
a66098da LB |
3002 | priv->capture_beacon = true; |
3003 | } else { | |
55489b6e | 3004 | rc = mwl8k_cmd_update_stadb(hw, vif, MWL8K_STA_DB_DEL_ENTRY); |
d89173f2 | 3005 | memset(mwl8k_vif->bssid, 0, ETH_ALEN); |
a66098da LB |
3006 | } |
3007 | ||
3a980d0a LB |
3008 | out: |
3009 | mwl8k_fw_unlock(hw); | |
a66098da LB |
3010 | } |
3011 | ||
e81cd2d6 LB |
3012 | static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw, |
3013 | int mc_count, struct dev_addr_list *mclist) | |
3014 | { | |
3015 | struct mwl8k_cmd_pkt *cmd; | |
3016 | ||
447ced07 LB |
3017 | /* |
3018 | * Synthesize and return a command packet that programs the | |
3019 | * hardware multicast address filter. At this point we don't | |
3020 | * know whether FIF_ALLMULTI is being requested, but if it is, | |
3021 | * we'll end up throwing this packet away and creating a new | |
3022 | * one in mwl8k_configure_filter(). | |
3023 | */ | |
3024 | cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_count, mclist); | |
e81cd2d6 LB |
3025 | |
3026 | return (unsigned long)cmd; | |
3027 | } | |
3028 | ||
a43c49a8 LB |
3029 | static int |
3030 | mwl8k_configure_filter_sniffer(struct ieee80211_hw *hw, | |
3031 | unsigned int changed_flags, | |
3032 | unsigned int *total_flags) | |
3033 | { | |
3034 | struct mwl8k_priv *priv = hw->priv; | |
3035 | ||
3036 | /* | |
3037 | * Hardware sniffer mode is mutually exclusive with STA | |
3038 | * operation, so refuse to enable sniffer mode if a STA | |
3039 | * interface is active. | |
3040 | */ | |
3041 | if (priv->vif != NULL) { | |
3042 | if (net_ratelimit()) | |
3043 | printk(KERN_INFO "%s: not enabling sniffer " | |
3044 | "mode because STA interface is active\n", | |
3045 | wiphy_name(hw->wiphy)); | |
3046 | return 0; | |
3047 | } | |
3048 | ||
3049 | if (!priv->sniffer_enabled) { | |
55489b6e | 3050 | if (mwl8k_cmd_enable_sniffer(hw, 1)) |
a43c49a8 LB |
3051 | return 0; |
3052 | priv->sniffer_enabled = true; | |
3053 | } | |
3054 | ||
3055 | *total_flags &= FIF_PROMISC_IN_BSS | FIF_ALLMULTI | | |
3056 | FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL | | |
3057 | FIF_OTHER_BSS; | |
3058 | ||
3059 | return 1; | |
3060 | } | |
3061 | ||
e6935ea1 LB |
3062 | static void mwl8k_configure_filter(struct ieee80211_hw *hw, |
3063 | unsigned int changed_flags, | |
3064 | unsigned int *total_flags, | |
3065 | u64 multicast) | |
3066 | { | |
3067 | struct mwl8k_priv *priv = hw->priv; | |
a43c49a8 LB |
3068 | struct mwl8k_cmd_pkt *cmd = (void *)(unsigned long)multicast; |
3069 | ||
c0adae2c LB |
3070 | /* |
3071 | * AP firmware doesn't allow fine-grained control over | |
3072 | * the receive filter. | |
3073 | */ | |
3074 | if (priv->ap_fw) { | |
3075 | *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC; | |
3076 | kfree(cmd); | |
3077 | return; | |
3078 | } | |
3079 | ||
a43c49a8 LB |
3080 | /* |
3081 | * Enable hardware sniffer mode if FIF_CONTROL or | |
3082 | * FIF_OTHER_BSS is requested. | |
3083 | */ | |
3084 | if (*total_flags & (FIF_CONTROL | FIF_OTHER_BSS) && | |
3085 | mwl8k_configure_filter_sniffer(hw, changed_flags, total_flags)) { | |
3086 | kfree(cmd); | |
3087 | return; | |
3088 | } | |
a66098da | 3089 | |
e6935ea1 | 3090 | /* Clear unsupported feature flags */ |
447ced07 | 3091 | *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC; |
a66098da | 3092 | |
e6935ea1 LB |
3093 | if (mwl8k_fw_lock(hw)) |
3094 | return; | |
a66098da | 3095 | |
a43c49a8 | 3096 | if (priv->sniffer_enabled) { |
55489b6e | 3097 | mwl8k_cmd_enable_sniffer(hw, 0); |
a43c49a8 LB |
3098 | priv->sniffer_enabled = false; |
3099 | } | |
3100 | ||
e6935ea1 | 3101 | if (changed_flags & FIF_BCN_PRBRESP_PROMISC) { |
77165d88 LB |
3102 | if (*total_flags & FIF_BCN_PRBRESP_PROMISC) { |
3103 | /* | |
3104 | * Disable the BSS filter. | |
3105 | */ | |
e6935ea1 | 3106 | mwl8k_cmd_set_pre_scan(hw); |
77165d88 | 3107 | } else { |
a94cc97e LB |
3108 | u8 *bssid; |
3109 | ||
77165d88 LB |
3110 | /* |
3111 | * Enable the BSS filter. | |
3112 | * | |
3113 | * If there is an active STA interface, use that | |
3114 | * interface's BSSID, otherwise use a dummy one | |
3115 | * (where the OUI part needs to be nonzero for | |
3116 | * the BSSID to be accepted by POST_SCAN). | |
3117 | */ | |
3118 | bssid = "\x01\x00\x00\x00\x00\x00"; | |
a94cc97e LB |
3119 | if (priv->vif != NULL) |
3120 | bssid = MWL8K_VIF(priv->vif)->bssid; | |
3121 | ||
e6935ea1 | 3122 | mwl8k_cmd_set_post_scan(hw, bssid); |
a66098da LB |
3123 | } |
3124 | } | |
3125 | ||
447ced07 LB |
3126 | /* |
3127 | * If FIF_ALLMULTI is being requested, throw away the command | |
3128 | * packet that ->prepare_multicast() built and replace it with | |
3129 | * a command packet that enables reception of all multicast | |
3130 | * packets. | |
3131 | */ | |
3132 | if (*total_flags & FIF_ALLMULTI) { | |
3133 | kfree(cmd); | |
3134 | cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, 0, NULL); | |
3135 | } | |
3136 | ||
3137 | if (cmd != NULL) { | |
3138 | mwl8k_post_cmd(hw, cmd); | |
3139 | kfree(cmd); | |
e6935ea1 | 3140 | } |
a66098da | 3141 | |
e6935ea1 | 3142 | mwl8k_fw_unlock(hw); |
a66098da LB |
3143 | } |
3144 | ||
a66098da LB |
3145 | static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value) |
3146 | { | |
55489b6e | 3147 | return mwl8k_cmd_set_rts_threshold(hw, MWL8K_CMD_SET, value); |
a66098da LB |
3148 | } |
3149 | ||
a66098da LB |
3150 | static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue, |
3151 | const struct ieee80211_tx_queue_params *params) | |
3152 | { | |
3e4f542c | 3153 | struct mwl8k_priv *priv = hw->priv; |
a66098da | 3154 | int rc; |
a66098da | 3155 | |
3e4f542c LB |
3156 | rc = mwl8k_fw_lock(hw); |
3157 | if (!rc) { | |
3158 | if (!priv->wmm_enabled) | |
55489b6e | 3159 | rc = mwl8k_cmd_set_wmm_mode(hw, 1); |
a66098da | 3160 | |
3e4f542c | 3161 | if (!rc) |
55489b6e LB |
3162 | rc = mwl8k_cmd_set_edca_params(hw, queue, |
3163 | params->cw_min, | |
3164 | params->cw_max, | |
3165 | params->aifs, | |
3166 | params->txop); | |
3e4f542c LB |
3167 | |
3168 | mwl8k_fw_unlock(hw); | |
a66098da | 3169 | } |
3e4f542c | 3170 | |
a66098da LB |
3171 | return rc; |
3172 | } | |
3173 | ||
3174 | static int mwl8k_get_tx_stats(struct ieee80211_hw *hw, | |
3175 | struct ieee80211_tx_queue_stats *stats) | |
3176 | { | |
3177 | struct mwl8k_priv *priv = hw->priv; | |
3178 | struct mwl8k_tx_queue *txq; | |
3179 | int index; | |
3180 | ||
3181 | spin_lock_bh(&priv->tx_lock); | |
3182 | for (index = 0; index < MWL8K_TX_QUEUES; index++) { | |
3183 | txq = priv->txq + index; | |
45eb400d | 3184 | memcpy(&stats[index], &txq->stats, |
a66098da LB |
3185 | sizeof(struct ieee80211_tx_queue_stats)); |
3186 | } | |
3187 | spin_unlock_bh(&priv->tx_lock); | |
a66098da | 3188 | |
954ef509 | 3189 | return 0; |
a66098da LB |
3190 | } |
3191 | ||
3192 | static int mwl8k_get_stats(struct ieee80211_hw *hw, | |
3193 | struct ieee80211_low_level_stats *stats) | |
3194 | { | |
55489b6e | 3195 | return mwl8k_cmd_get_stat(hw, stats); |
a66098da LB |
3196 | } |
3197 | ||
3198 | static const struct ieee80211_ops mwl8k_ops = { | |
3199 | .tx = mwl8k_tx, | |
3200 | .start = mwl8k_start, | |
3201 | .stop = mwl8k_stop, | |
3202 | .add_interface = mwl8k_add_interface, | |
3203 | .remove_interface = mwl8k_remove_interface, | |
3204 | .config = mwl8k_config, | |
a66098da | 3205 | .bss_info_changed = mwl8k_bss_info_changed, |
3ac64bee | 3206 | .prepare_multicast = mwl8k_prepare_multicast, |
a66098da LB |
3207 | .configure_filter = mwl8k_configure_filter, |
3208 | .set_rts_threshold = mwl8k_set_rts_threshold, | |
3209 | .conf_tx = mwl8k_conf_tx, | |
3210 | .get_tx_stats = mwl8k_get_tx_stats, | |
3211 | .get_stats = mwl8k_get_stats, | |
3212 | }; | |
3213 | ||
3214 | static void mwl8k_tx_reclaim_handler(unsigned long data) | |
3215 | { | |
3216 | int i; | |
3217 | struct ieee80211_hw *hw = (struct ieee80211_hw *) data; | |
3218 | struct mwl8k_priv *priv = hw->priv; | |
3219 | ||
3220 | spin_lock_bh(&priv->tx_lock); | |
3221 | for (i = 0; i < MWL8K_TX_QUEUES; i++) | |
3222 | mwl8k_txq_reclaim(hw, i, 0); | |
3223 | ||
88de754a | 3224 | if (priv->tx_wait != NULL && !priv->pending_tx_pkts) { |
ce9e2e1b LB |
3225 | complete(priv->tx_wait); |
3226 | priv->tx_wait = NULL; | |
a66098da LB |
3227 | } |
3228 | spin_unlock_bh(&priv->tx_lock); | |
3229 | } | |
3230 | ||
3231 | static void mwl8k_finalize_join_worker(struct work_struct *work) | |
3232 | { | |
3233 | struct mwl8k_priv *priv = | |
3234 | container_of(work, struct mwl8k_priv, finalize_join_worker); | |
3235 | struct sk_buff *skb = priv->beacon_skb; | |
a66098da | 3236 | |
7dc6a7a7 LB |
3237 | mwl8k_cmd_finalize_join(priv->hw, skb->data, skb->len, |
3238 | priv->vif->bss_conf.dtim_period); | |
a66098da LB |
3239 | dev_kfree_skb(skb); |
3240 | ||
3241 | priv->beacon_skb = NULL; | |
3242 | } | |
3243 | ||
bcb628d5 JL |
3244 | enum { |
3245 | MWL8687 = 0, | |
3246 | MWL8366, | |
6f6d1e9a LB |
3247 | }; |
3248 | ||
bcb628d5 | 3249 | static struct mwl8k_device_info mwl8k_info_tbl[] __devinitdata = { |
49eb691c | 3250 | [MWL8687] = { |
bcb628d5 JL |
3251 | .part_name = "88w8687", |
3252 | .helper_image = "mwl8k/helper_8687.fw", | |
3253 | .fw_image = "mwl8k/fmimage_8687.fw", | |
bcb628d5 | 3254 | }, |
49eb691c | 3255 | [MWL8366] = { |
bcb628d5 JL |
3256 | .part_name = "88w8366", |
3257 | .helper_image = "mwl8k/helper_8366.fw", | |
3258 | .fw_image = "mwl8k/fmimage_8366.fw", | |
89a91f4f | 3259 | .ap_rxd_ops = &rxd_8366_ap_ops, |
bcb628d5 | 3260 | }, |
45a390dd LB |
3261 | }; |
3262 | ||
3263 | static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = { | |
bcb628d5 JL |
3264 | { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = MWL8687, }, |
3265 | { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = MWL8687, }, | |
3266 | { PCI_VDEVICE(MARVELL, 0x2a40), .driver_data = MWL8366, }, | |
3267 | { }, | |
45a390dd LB |
3268 | }; |
3269 | MODULE_DEVICE_TABLE(pci, mwl8k_pci_id_table); | |
3270 | ||
a66098da LB |
3271 | static int __devinit mwl8k_probe(struct pci_dev *pdev, |
3272 | const struct pci_device_id *id) | |
3273 | { | |
2aa7b01f | 3274 | static int printed_version = 0; |
a66098da LB |
3275 | struct ieee80211_hw *hw; |
3276 | struct mwl8k_priv *priv; | |
a66098da LB |
3277 | int rc; |
3278 | int i; | |
2aa7b01f LB |
3279 | |
3280 | if (!printed_version) { | |
3281 | printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION); | |
3282 | printed_version = 1; | |
3283 | } | |
a66098da | 3284 | |
be695fc4 | 3285 | |
a66098da LB |
3286 | rc = pci_enable_device(pdev); |
3287 | if (rc) { | |
3288 | printk(KERN_ERR "%s: Cannot enable new PCI device\n", | |
3289 | MWL8K_NAME); | |
3290 | return rc; | |
3291 | } | |
3292 | ||
3293 | rc = pci_request_regions(pdev, MWL8K_NAME); | |
3294 | if (rc) { | |
3295 | printk(KERN_ERR "%s: Cannot obtain PCI resources\n", | |
3296 | MWL8K_NAME); | |
3db95e50 | 3297 | goto err_disable_device; |
a66098da LB |
3298 | } |
3299 | ||
3300 | pci_set_master(pdev); | |
3301 | ||
be695fc4 | 3302 | |
a66098da LB |
3303 | hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops); |
3304 | if (hw == NULL) { | |
3305 | printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME); | |
3306 | rc = -ENOMEM; | |
3307 | goto err_free_reg; | |
3308 | } | |
3309 | ||
be695fc4 LB |
3310 | SET_IEEE80211_DEV(hw, &pdev->dev); |
3311 | pci_set_drvdata(pdev, hw); | |
3312 | ||
a66098da LB |
3313 | priv = hw->priv; |
3314 | priv->hw = hw; | |
3315 | priv->pdev = pdev; | |
bcb628d5 | 3316 | priv->device_info = &mwl8k_info_tbl[id->driver_data]; |
a66098da | 3317 | |
a66098da | 3318 | |
5b9482dd LB |
3319 | priv->sram = pci_iomap(pdev, 0, 0x10000); |
3320 | if (priv->sram == NULL) { | |
3321 | printk(KERN_ERR "%s: Cannot map device SRAM\n", | |
c2c357ce | 3322 | wiphy_name(hw->wiphy)); |
a66098da LB |
3323 | goto err_iounmap; |
3324 | } | |
3325 | ||
5b9482dd LB |
3326 | /* |
3327 | * If BAR0 is a 32 bit BAR, the register BAR will be BAR1. | |
3328 | * If BAR0 is a 64 bit BAR, the register BAR will be BAR2. | |
3329 | */ | |
3330 | priv->regs = pci_iomap(pdev, 1, 0x10000); | |
3331 | if (priv->regs == NULL) { | |
3332 | priv->regs = pci_iomap(pdev, 2, 0x10000); | |
3333 | if (priv->regs == NULL) { | |
3334 | printk(KERN_ERR "%s: Cannot map device registers\n", | |
3335 | wiphy_name(hw->wiphy)); | |
3336 | goto err_iounmap; | |
3337 | } | |
3338 | } | |
3339 | ||
be695fc4 LB |
3340 | |
3341 | /* Reset firmware and hardware */ | |
3342 | mwl8k_hw_reset(priv); | |
3343 | ||
3344 | /* Ask userland hotplug daemon for the device firmware */ | |
3345 | rc = mwl8k_request_firmware(priv); | |
3346 | if (rc) { | |
3347 | printk(KERN_ERR "%s: Firmware files not found\n", | |
3348 | wiphy_name(hw->wiphy)); | |
3349 | goto err_stop_firmware; | |
3350 | } | |
3351 | ||
3352 | /* Load firmware into hardware */ | |
3353 | rc = mwl8k_load_firmware(hw); | |
3354 | if (rc) { | |
3355 | printk(KERN_ERR "%s: Cannot start firmware\n", | |
3356 | wiphy_name(hw->wiphy)); | |
3357 | goto err_stop_firmware; | |
3358 | } | |
3359 | ||
3360 | /* Reclaim memory once firmware is successfully loaded */ | |
3361 | mwl8k_release_firmware(priv); | |
3362 | ||
3363 | ||
91942230 | 3364 | if (priv->ap_fw) { |
89a91f4f | 3365 | priv->rxd_ops = priv->device_info->ap_rxd_ops; |
91942230 LB |
3366 | if (priv->rxd_ops == NULL) { |
3367 | printk(KERN_ERR "%s: Driver does not have AP " | |
3368 | "firmware image support for this hardware\n", | |
3369 | wiphy_name(hw->wiphy)); | |
3370 | goto err_stop_firmware; | |
3371 | } | |
3372 | } else { | |
89a91f4f | 3373 | priv->rxd_ops = &rxd_sta_ops; |
91942230 | 3374 | } |
be695fc4 LB |
3375 | |
3376 | priv->sniffer_enabled = false; | |
3377 | priv->wmm_enabled = false; | |
3378 | priv->pending_tx_pkts = 0; | |
3379 | ||
3380 | ||
a66098da LB |
3381 | memcpy(priv->channels, mwl8k_channels, sizeof(mwl8k_channels)); |
3382 | priv->band.band = IEEE80211_BAND_2GHZ; | |
3383 | priv->band.channels = priv->channels; | |
3384 | priv->band.n_channels = ARRAY_SIZE(mwl8k_channels); | |
3385 | priv->band.bitrates = priv->rates; | |
3386 | priv->band.n_bitrates = ARRAY_SIZE(mwl8k_rates); | |
3387 | hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band; | |
3388 | ||
3389 | BUILD_BUG_ON(sizeof(priv->rates) != sizeof(mwl8k_rates)); | |
3390 | memcpy(priv->rates, mwl8k_rates, sizeof(mwl8k_rates)); | |
3391 | ||
3392 | /* | |
3393 | * Extra headroom is the size of the required DMA header | |
3394 | * minus the size of the smallest 802.11 frame (CTS frame). | |
3395 | */ | |
3396 | hw->extra_tx_headroom = | |
3397 | sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts); | |
3398 | ||
3399 | hw->channel_change_time = 10; | |
3400 | ||
3401 | hw->queues = MWL8K_TX_QUEUES; | |
3402 | ||
a66098da | 3403 | /* Set rssi and noise values to dBm */ |
ce9e2e1b | 3404 | hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM; |
a66098da LB |
3405 | hw->vif_data_size = sizeof(struct mwl8k_vif); |
3406 | priv->vif = NULL; | |
3407 | ||
3408 | /* Set default radio state and preamble */ | |
c46563b7 | 3409 | priv->radio_on = 0; |
68ce3884 | 3410 | priv->radio_short_preamble = 0; |
a66098da LB |
3411 | |
3412 | /* Finalize join worker */ | |
3413 | INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker); | |
3414 | ||
3415 | /* TX reclaim tasklet */ | |
3416 | tasklet_init(&priv->tx_reclaim_task, | |
3417 | mwl8k_tx_reclaim_handler, (unsigned long)hw); | |
3418 | tasklet_disable(&priv->tx_reclaim_task); | |
3419 | ||
a66098da LB |
3420 | /* Power management cookie */ |
3421 | priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma); | |
3422 | if (priv->cookie == NULL) | |
be695fc4 | 3423 | goto err_stop_firmware; |
a66098da LB |
3424 | |
3425 | rc = mwl8k_rxq_init(hw, 0); | |
3426 | if (rc) | |
be695fc4 | 3427 | goto err_free_cookie; |
a66098da LB |
3428 | rxq_refill(hw, 0, INT_MAX); |
3429 | ||
618952a7 LB |
3430 | mutex_init(&priv->fw_mutex); |
3431 | priv->fw_mutex_owner = NULL; | |
3432 | priv->fw_mutex_depth = 0; | |
618952a7 LB |
3433 | priv->hostcmd_wait = NULL; |
3434 | ||
a66098da LB |
3435 | spin_lock_init(&priv->tx_lock); |
3436 | ||
88de754a LB |
3437 | priv->tx_wait = NULL; |
3438 | ||
a66098da LB |
3439 | for (i = 0; i < MWL8K_TX_QUEUES; i++) { |
3440 | rc = mwl8k_txq_init(hw, i); | |
3441 | if (rc) | |
3442 | goto err_free_queues; | |
3443 | } | |
3444 | ||
3445 | iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS); | |
c23b5a69 | 3446 | iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); |
a66098da LB |
3447 | iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL); |
3448 | iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK); | |
3449 | ||
a0607fd3 | 3450 | rc = request_irq(priv->pdev->irq, mwl8k_interrupt, |
a66098da LB |
3451 | IRQF_SHARED, MWL8K_NAME, hw); |
3452 | if (rc) { | |
3453 | printk(KERN_ERR "%s: failed to register IRQ handler\n", | |
c2c357ce | 3454 | wiphy_name(hw->wiphy)); |
a66098da LB |
3455 | goto err_free_queues; |
3456 | } | |
3457 | ||
a66098da LB |
3458 | /* |
3459 | * Temporarily enable interrupts. Initial firmware host | |
3460 | * commands use interrupts and avoids polling. Disable | |
3461 | * interrupts when done. | |
3462 | */ | |
c23b5a69 | 3463 | iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); |
a66098da LB |
3464 | |
3465 | /* Get config data, mac addrs etc */ | |
42fba21d LB |
3466 | if (priv->ap_fw) { |
3467 | rc = mwl8k_cmd_get_hw_spec_ap(hw); | |
3468 | if (!rc) | |
3469 | rc = mwl8k_cmd_set_hw_spec(hw); | |
3470 | } else { | |
3471 | rc = mwl8k_cmd_get_hw_spec_sta(hw); | |
89a91f4f LB |
3472 | |
3473 | hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION); | |
42fba21d | 3474 | } |
a66098da | 3475 | if (rc) { |
c2c357ce LB |
3476 | printk(KERN_ERR "%s: Cannot initialise firmware\n", |
3477 | wiphy_name(hw->wiphy)); | |
be695fc4 | 3478 | goto err_free_irq; |
a66098da LB |
3479 | } |
3480 | ||
3481 | /* Turn radio off */ | |
55489b6e | 3482 | rc = mwl8k_cmd_radio_disable(hw); |
a66098da | 3483 | if (rc) { |
c2c357ce | 3484 | printk(KERN_ERR "%s: Cannot disable\n", wiphy_name(hw->wiphy)); |
be695fc4 | 3485 | goto err_free_irq; |
a66098da LB |
3486 | } |
3487 | ||
32060e1b | 3488 | /* Clear MAC address */ |
55489b6e | 3489 | rc = mwl8k_cmd_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00"); |
32060e1b LB |
3490 | if (rc) { |
3491 | printk(KERN_ERR "%s: Cannot clear MAC address\n", | |
3492 | wiphy_name(hw->wiphy)); | |
be695fc4 | 3493 | goto err_free_irq; |
32060e1b LB |
3494 | } |
3495 | ||
a66098da | 3496 | /* Disable interrupts */ |
a66098da | 3497 | iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); |
a66098da LB |
3498 | free_irq(priv->pdev->irq, hw); |
3499 | ||
3500 | rc = ieee80211_register_hw(hw); | |
3501 | if (rc) { | |
c2c357ce LB |
3502 | printk(KERN_ERR "%s: Cannot register device\n", |
3503 | wiphy_name(hw->wiphy)); | |
153458ff | 3504 | goto err_free_queues; |
a66098da LB |
3505 | } |
3506 | ||
eae74e65 | 3507 | printk(KERN_INFO "%s: %s v%d, %pM, %s firmware %u.%u.%u.%u\n", |
a74b295e | 3508 | wiphy_name(hw->wiphy), priv->device_info->part_name, |
45a390dd | 3509 | priv->hw_rev, hw->wiphy->perm_addr, |
eae74e65 | 3510 | priv->ap_fw ? "AP" : "STA", |
2aa7b01f LB |
3511 | (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff, |
3512 | (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff); | |
a66098da LB |
3513 | |
3514 | return 0; | |
3515 | ||
a66098da | 3516 | err_free_irq: |
a66098da | 3517 | iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); |
a66098da LB |
3518 | free_irq(priv->pdev->irq, hw); |
3519 | ||
3520 | err_free_queues: | |
3521 | for (i = 0; i < MWL8K_TX_QUEUES; i++) | |
3522 | mwl8k_txq_deinit(hw, i); | |
3523 | mwl8k_rxq_deinit(hw, 0); | |
3524 | ||
be695fc4 | 3525 | err_free_cookie: |
a66098da LB |
3526 | if (priv->cookie != NULL) |
3527 | pci_free_consistent(priv->pdev, 4, | |
3528 | priv->cookie, priv->cookie_dma); | |
3529 | ||
be695fc4 LB |
3530 | err_stop_firmware: |
3531 | mwl8k_hw_reset(priv); | |
3532 | mwl8k_release_firmware(priv); | |
3533 | ||
3534 | err_iounmap: | |
a66098da LB |
3535 | if (priv->regs != NULL) |
3536 | pci_iounmap(pdev, priv->regs); | |
3537 | ||
5b9482dd LB |
3538 | if (priv->sram != NULL) |
3539 | pci_iounmap(pdev, priv->sram); | |
3540 | ||
a66098da LB |
3541 | pci_set_drvdata(pdev, NULL); |
3542 | ieee80211_free_hw(hw); | |
3543 | ||
3544 | err_free_reg: | |
3545 | pci_release_regions(pdev); | |
3db95e50 LB |
3546 | |
3547 | err_disable_device: | |
a66098da LB |
3548 | pci_disable_device(pdev); |
3549 | ||
3550 | return rc; | |
3551 | } | |
3552 | ||
230f7af0 | 3553 | static void __devexit mwl8k_shutdown(struct pci_dev *pdev) |
a66098da LB |
3554 | { |
3555 | printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__); | |
3556 | } | |
3557 | ||
230f7af0 | 3558 | static void __devexit mwl8k_remove(struct pci_dev *pdev) |
a66098da LB |
3559 | { |
3560 | struct ieee80211_hw *hw = pci_get_drvdata(pdev); | |
3561 | struct mwl8k_priv *priv; | |
3562 | int i; | |
3563 | ||
3564 | if (hw == NULL) | |
3565 | return; | |
3566 | priv = hw->priv; | |
3567 | ||
3568 | ieee80211_stop_queues(hw); | |
3569 | ||
60aa569f LB |
3570 | ieee80211_unregister_hw(hw); |
3571 | ||
a66098da LB |
3572 | /* Remove tx reclaim tasklet */ |
3573 | tasklet_kill(&priv->tx_reclaim_task); | |
3574 | ||
a66098da LB |
3575 | /* Stop hardware */ |
3576 | mwl8k_hw_reset(priv); | |
3577 | ||
3578 | /* Return all skbs to mac80211 */ | |
3579 | for (i = 0; i < MWL8K_TX_QUEUES; i++) | |
3580 | mwl8k_txq_reclaim(hw, i, 1); | |
3581 | ||
a66098da LB |
3582 | for (i = 0; i < MWL8K_TX_QUEUES; i++) |
3583 | mwl8k_txq_deinit(hw, i); | |
3584 | ||
3585 | mwl8k_rxq_deinit(hw, 0); | |
3586 | ||
c2c357ce | 3587 | pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma); |
a66098da LB |
3588 | |
3589 | pci_iounmap(pdev, priv->regs); | |
5b9482dd | 3590 | pci_iounmap(pdev, priv->sram); |
a66098da LB |
3591 | pci_set_drvdata(pdev, NULL); |
3592 | ieee80211_free_hw(hw); | |
3593 | pci_release_regions(pdev); | |
3594 | pci_disable_device(pdev); | |
3595 | } | |
3596 | ||
3597 | static struct pci_driver mwl8k_driver = { | |
3598 | .name = MWL8K_NAME, | |
45a390dd | 3599 | .id_table = mwl8k_pci_id_table, |
a66098da LB |
3600 | .probe = mwl8k_probe, |
3601 | .remove = __devexit_p(mwl8k_remove), | |
3602 | .shutdown = __devexit_p(mwl8k_shutdown), | |
3603 | }; | |
3604 | ||
3605 | static int __init mwl8k_init(void) | |
3606 | { | |
3607 | return pci_register_driver(&mwl8k_driver); | |
3608 | } | |
3609 | ||
3610 | static void __exit mwl8k_exit(void) | |
3611 | { | |
3612 | pci_unregister_driver(&mwl8k_driver); | |
3613 | } | |
3614 | ||
3615 | module_init(mwl8k_init); | |
3616 | module_exit(mwl8k_exit); | |
c2c357ce LB |
3617 | |
3618 | MODULE_DESCRIPTION(MWL8K_DESC); | |
3619 | MODULE_VERSION(MWL8K_VERSION); | |
3620 | MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>"); | |
3621 | MODULE_LICENSE("GPL"); |