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mwl8k: move ->peer_id from mwl8k_vif to mwl8k_sta
[deliverable/linux.git] / drivers / net / wireless / mwl8k.c
CommitLineData
a66098da 1/*
ce9e2e1b
LB		 2 * drivers/net/wireless/mwl8k.c
3 * Driver for Marvell TOPDOG 802.11 Wireless cards
a66098da 4 *
a145d575 5 * Copyright (C) 2008-2009 Marvell Semiconductor Inc.
a66098da
LB		 6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
3d76e82c 15#include <linux/sched.h>
a66098da
LB		 16#include <linux/spinlock.h>
17#include <linux/list.h>
18#include <linux/pci.h>
19#include <linux/delay.h>
20#include <linux/completion.h>
21#include <linux/etherdevice.h>
22#include <net/mac80211.h>
23#include <linux/moduleparam.h>
24#include <linux/firmware.h>
25#include <linux/workqueue.h>
26
27#define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
28#define MWL8K_NAME KBUILD_MODNAME
6976b665 29#define MWL8K_VERSION "0.11"
a66098da 30
a66098da
LB		 31/* Register definitions */
32#define MWL8K_HIU_GEN_PTR 0x00000c10
ce9e2e1b
LB		 33#define MWL8K_MODE_STA 0x0000005a
34#define MWL8K_MODE_AP 0x000000a5
a66098da 35#define MWL8K_HIU_INT_CODE 0x00000c14
ce9e2e1b
LB		 36#define MWL8K_FWSTA_READY 0xf0f1f2f4
37#define MWL8K_FWAP_READY 0xf1f2f4a5
38#define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
a66098da
LB		 39#define MWL8K_HIU_SCRATCH 0x00000c40
40
41/* Host->device communications */
42#define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
43#define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
44#define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
45#define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
46#define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
ce9e2e1b
LB		 47#define MWL8K_H2A_INT_DUMMY (1 << 20)
48#define MWL8K_H2A_INT_RESET (1 << 15)
49#define MWL8K_H2A_INT_DOORBELL (1 << 1)
50#define MWL8K_H2A_INT_PPA_READY (1 << 0)
a66098da
LB		 51
52/* Device->host communications */
53#define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
54#define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
55#define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
56#define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
57#define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
ce9e2e1b
LB		 58#define MWL8K_A2H_INT_DUMMY (1 << 20)
59#define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
60#define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
61#define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
62#define MWL8K_A2H_INT_RADIO_ON (1 << 6)
63#define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
64#define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
65#define MWL8K_A2H_INT_OPC_DONE (1 << 2)
66#define MWL8K_A2H_INT_RX_READY (1 << 1)
67#define MWL8K_A2H_INT_TX_DONE (1 << 0)
a66098da
LB		 68
69#define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
70 MWL8K_A2H_INT_CHNL_SWITCHED | \
71 MWL8K_A2H_INT_QUEUE_EMPTY | \
72 MWL8K_A2H_INT_RADAR_DETECT | \
73 MWL8K_A2H_INT_RADIO_ON | \
74 MWL8K_A2H_INT_RADIO_OFF | \
75 MWL8K_A2H_INT_MAC_EVENT | \
76 MWL8K_A2H_INT_OPC_DONE | \
77 MWL8K_A2H_INT_RX_READY | \
78 MWL8K_A2H_INT_TX_DONE)
79
a66098da
LB		 80#define MWL8K_RX_QUEUES 1
81#define MWL8K_TX_QUEUES 4
82
54bc3a0d
LB		 83struct rxd_ops {
84 int rxd_size;
85 void (*rxd_init)(void *rxd, dma_addr_t next_dma_addr);
86 void (*rxd_refill)(void *rxd, dma_addr_t addr, int len);
20f09c3d
LB		 87 int (*rxd_process)(void *rxd, struct ieee80211_rx_status *status,
88 __le16 *qos);
54bc3a0d
LB		 89};
90
45a390dd 91struct mwl8k_device_info {
a74b295e
LB		 92 char *part_name;
93 char *helper_image;
94 char *fw_image;
89a91f4f 95 struct rxd_ops *ap_rxd_ops;
45a390dd
LB		 96};
97
a66098da 98struct mwl8k_rx_queue {
45eb400d 99 int rxd_count;
a66098da
LB		 100
101 /* hw receives here */
45eb400d 102 int head;
a66098da
LB		 103
104 /* refill descs here */
45eb400d 105 int tail;
a66098da 106
54bc3a0d 107 void *rxd;
45eb400d 108 dma_addr_t rxd_dma;
788838eb
LB		 109 struct {
110 struct sk_buff *skb;
111 DECLARE_PCI_UNMAP_ADDR(dma)
112 } *buf;
a66098da
LB		 113};
114
a66098da
LB		 115struct mwl8k_tx_queue {
116 /* hw transmits here */
45eb400d 117 int head;
a66098da
LB		 118
119 /* sw appends here */
45eb400d 120 int tail;
a66098da 121
45eb400d
LB		 122 struct ieee80211_tx_queue_stats stats;
123 struct mwl8k_tx_desc *txd;
124 dma_addr_t txd_dma;
125 struct sk_buff **skb;
a66098da
LB		 126};
127
a66098da 128struct mwl8k_priv {
a66098da 129 struct ieee80211_hw *hw;
a66098da 130 struct pci_dev *pdev;
a66098da 131
45a390dd
LB		 132 struct mwl8k_device_info *device_info;
133
be695fc4
LB		 134 void __iomem *sram;
135 void __iomem *regs;
136
137 /* firmware */
22be40d9
LB		 138 struct firmware *fw_helper;
139 struct firmware *fw_ucode;
a66098da 140
be695fc4
LB		 141 /* hardware/firmware parameters */
142 bool ap_fw;
143 struct rxd_ops *rxd_ops;
144
618952a7
LB		 145 /* firmware access */
146 struct mutex fw_mutex;
147 struct task_struct *fw_mutex_owner;
148 int fw_mutex_depth;
618952a7
LB		 149 struct completion *hostcmd_wait;
150
a66098da
LB		 151 /* lock held over TX and TX reap */
152 spinlock_t tx_lock;
a66098da 153
88de754a
LB		 154 /* TX quiesce completion, protected by fw_mutex and tx_lock */
155 struct completion *tx_wait;
156
a66098da 157 struct ieee80211_vif *vif;
a66098da
LB		 158
159 struct ieee80211_channel *current_channel;
160
161 /* power management status cookie from firmware */
162 u32 *cookie;
163 dma_addr_t cookie_dma;
164
165 u16 num_mcaddrs;
a66098da 166 u8 hw_rev;
2aa7b01f 167 u32 fw_rev;
a66098da
LB		 168
169 /*
170 * Running count of TX packets in flight, to avoid
171 * iterating over the transmit rings each time.
172 */
173 int pending_tx_pkts;
174
175 struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
176 struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES];
177
178 /* PHY parameters */
179 struct ieee80211_supported_band band;
180 struct ieee80211_channel channels[14];
140eb5e2 181 struct ieee80211_rate rates[14];
a66098da 182
c46563b7 183 bool radio_on;
68ce3884 184 bool radio_short_preamble;
a43c49a8 185 bool sniffer_enabled;
0439b1f5 186 bool wmm_enabled;
a66098da 187
bbfd9128
LB		 188 struct work_struct sta_notify_worker;
189 spinlock_t sta_notify_list_lock;
190 struct list_head sta_notify_list;
191
a66098da
LB		 192 /* XXX need to convert this to handle multiple interfaces */
193 bool capture_beacon;
d89173f2 194 u8 capture_bssid[ETH_ALEN];
a66098da
LB		 195 struct sk_buff *beacon_skb;
196
197 /*
198 * This FJ worker has to be global as it is scheduled from the
199 * RX handler. At this point we don't know which interface it
200 * belongs to until the list of bssids waiting to complete join
201 * is checked.
202 */
203 struct work_struct finalize_join_worker;
204
205 /* Tasklet to reclaim TX descriptors and buffers after tx */
206 struct tasklet_struct tx_reclaim_task;
a66098da
LB		 207};
208
209/* Per interface specific private data */
210struct mwl8k_vif {
7dc6a7a7
LB		 211 /* Local MAC address. */
212 u8 mac_addr[ETH_ALEN];
a66098da 213
a66098da 214 /* Non AMPDU sequence number assigned by driver */
a680400e 215 u16 seqno;
a66098da 216};
a94cc97e 217#define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
a66098da 218
a680400e
LB		 219struct mwl8k_sta {
220 /* Index into station database. Returned by UPDATE_STADB. */
221 u8 peer_id;
222};
223#define MWL8K_STA(_sta) ((struct mwl8k_sta *)&((_sta)->drv_priv))
224
a66098da
LB		 225static const struct ieee80211_channel mwl8k_channels[] = {
226 { .center_freq = 2412, .hw_value = 1, },
227 { .center_freq = 2417, .hw_value = 2, },
228 { .center_freq = 2422, .hw_value = 3, },
229 { .center_freq = 2427, .hw_value = 4, },
230 { .center_freq = 2432, .hw_value = 5, },
231 { .center_freq = 2437, .hw_value = 6, },
232 { .center_freq = 2442, .hw_value = 7, },
233 { .center_freq = 2447, .hw_value = 8, },
234 { .center_freq = 2452, .hw_value = 9, },
235 { .center_freq = 2457, .hw_value = 10, },
236 { .center_freq = 2462, .hw_value = 11, },
647ca6b0
LB		 237 { .center_freq = 2467, .hw_value = 12, },
238 { .center_freq = 2472, .hw_value = 13, },
239 { .center_freq = 2484, .hw_value = 14, },
a66098da
LB		 240};
241
242static const struct ieee80211_rate mwl8k_rates[] = {
243 { .bitrate = 10, .hw_value = 2, },
244 { .bitrate = 20, .hw_value = 4, },
245 { .bitrate = 55, .hw_value = 11, },
5dfd3e2c
LB		 246 { .bitrate = 110, .hw_value = 22, },
247 { .bitrate = 220, .hw_value = 44, },
a66098da
LB		 248 { .bitrate = 60, .hw_value = 12, },
249 { .bitrate = 90, .hw_value = 18, },
a66098da
LB		 250 { .bitrate = 120, .hw_value = 24, },
251 { .bitrate = 180, .hw_value = 36, },
252 { .bitrate = 240, .hw_value = 48, },
253 { .bitrate = 360, .hw_value = 72, },
254 { .bitrate = 480, .hw_value = 96, },
255 { .bitrate = 540, .hw_value = 108, },
140eb5e2
LB		 256 { .bitrate = 720, .hw_value = 144, },
257};
258
259static const u8 mwl8k_rateids[12] = {
260 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108,
a66098da
LB		 261};
262
a66098da
LB		 263/* Set or get info from Firmware */
264#define MWL8K_CMD_SET 0x0001
265#define MWL8K_CMD_GET 0x0000
266
267/* Firmware command codes */
268#define MWL8K_CMD_CODE_DNLD 0x0001
269#define MWL8K_CMD_GET_HW_SPEC 0x0003
42fba21d 270#define MWL8K_CMD_SET_HW_SPEC 0x0004
a66098da
LB		 271#define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
272#define MWL8K_CMD_GET_STAT 0x0014
ff45fc60
LB		 273#define MWL8K_CMD_RADIO_CONTROL 0x001c
274#define MWL8K_CMD_RF_TX_POWER 0x001e
08b06347 275#define MWL8K_CMD_RF_ANTENNA 0x0020
a66098da
LB		 276#define MWL8K_CMD_SET_PRE_SCAN 0x0107
277#define MWL8K_CMD_SET_POST_SCAN 0x0108
ff45fc60
LB		 278#define MWL8K_CMD_SET_RF_CHANNEL 0x010a
279#define MWL8K_CMD_SET_AID 0x010d
280#define MWL8K_CMD_SET_RATE 0x0110
281#define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
282#define MWL8K_CMD_RTS_THRESHOLD 0x0113
a66098da 283#define MWL8K_CMD_SET_SLOT 0x0114
ff45fc60
LB		 284#define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
285#define MWL8K_CMD_SET_WMM_MODE 0x0123
a66098da 286#define MWL8K_CMD_MIMO_CONFIG 0x0125
ff45fc60 287#define MWL8K_CMD_USE_FIXED_RATE 0x0126
a66098da 288#define MWL8K_CMD_ENABLE_SNIFFER 0x0150
32060e1b 289#define MWL8K_CMD_SET_MAC_ADDR 0x0202
a66098da 290#define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
ff45fc60 291#define MWL8K_CMD_UPDATE_STADB 0x1123
a66098da
LB		 292
293static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize)
294{
295#define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
296 snprintf(buf, bufsize, "%s", #x);\
297 return buf;\
298 } while (0)
ce9e2e1b 299 switch (cmd & ~0x8000) {
a66098da
LB		 300 MWL8K_CMDNAME(CODE_DNLD);
301 MWL8K_CMDNAME(GET_HW_SPEC);
42fba21d 302 MWL8K_CMDNAME(SET_HW_SPEC);
a66098da
LB		 303 MWL8K_CMDNAME(MAC_MULTICAST_ADR);
304 MWL8K_CMDNAME(GET_STAT);
305 MWL8K_CMDNAME(RADIO_CONTROL);
306 MWL8K_CMDNAME(RF_TX_POWER);
08b06347 307 MWL8K_CMDNAME(RF_ANTENNA);
a66098da
LB		 308 MWL8K_CMDNAME(SET_PRE_SCAN);
309 MWL8K_CMDNAME(SET_POST_SCAN);
310 MWL8K_CMDNAME(SET_RF_CHANNEL);
ff45fc60
LB		 311 MWL8K_CMDNAME(SET_AID);
312 MWL8K_CMDNAME(SET_RATE);
313 MWL8K_CMDNAME(SET_FINALIZE_JOIN);
314 MWL8K_CMDNAME(RTS_THRESHOLD);
a66098da 315 MWL8K_CMDNAME(SET_SLOT);
ff45fc60
LB		 316 MWL8K_CMDNAME(SET_EDCA_PARAMS);
317 MWL8K_CMDNAME(SET_WMM_MODE);
a66098da 318 MWL8K_CMDNAME(MIMO_CONFIG);
ff45fc60 319 MWL8K_CMDNAME(USE_FIXED_RATE);
a66098da 320 MWL8K_CMDNAME(ENABLE_SNIFFER);
32060e1b 321 MWL8K_CMDNAME(SET_MAC_ADDR);
a66098da 322 MWL8K_CMDNAME(SET_RATEADAPT_MODE);
ff45fc60 323 MWL8K_CMDNAME(UPDATE_STADB);
a66098da
LB		 324 default:
325 snprintf(buf, bufsize, "0x%x", cmd);
326 }
327#undef MWL8K_CMDNAME
328
329 return buf;
330}
331
332/* Hardware and firmware reset */
333static void mwl8k_hw_reset(struct mwl8k_priv *priv)
334{
335 iowrite32(MWL8K_H2A_INT_RESET,
336 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
337 iowrite32(MWL8K_H2A_INT_RESET,
338 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
339 msleep(20);
340}
341
342/* Release fw image */
343static void mwl8k_release_fw(struct firmware **fw)
344{
345 if (*fw == NULL)
346 return;
347 release_firmware(*fw);
348 *fw = NULL;
349}
350
351static void mwl8k_release_firmware(struct mwl8k_priv *priv)
352{
22be40d9
LB		 353 mwl8k_release_fw(&priv->fw_ucode);
354 mwl8k_release_fw(&priv->fw_helper);
a66098da
LB		 355}
356
357/* Request fw image */
358static int mwl8k_request_fw(struct mwl8k_priv *priv,
c2c357ce 359 const char *fname, struct firmware **fw)
a66098da
LB		 360{
361 /* release current image */
362 if (*fw != NULL)
363 mwl8k_release_fw(fw);
364
365 return request_firmware((const struct firmware **)fw,
c2c357ce 366 fname, &priv->pdev->dev);
a66098da
LB		 367}
368
45a390dd 369static int mwl8k_request_firmware(struct mwl8k_priv *priv)
a66098da 370{
a74b295e 371 struct mwl8k_device_info *di = priv->device_info;
a66098da
LB		 372 int rc;
373
a74b295e 374 if (di->helper_image != NULL) {
22be40d9 375 rc = mwl8k_request_fw(priv, di->helper_image, &priv->fw_helper);
a74b295e
LB		 376 if (rc) {
377 printk(KERN_ERR "%s: Error requesting helper "
378 "firmware file %s\n", pci_name(priv->pdev),
379 di->helper_image);
380 return rc;
381 }
a66098da
LB		 382 }
383
22be40d9 384 rc = mwl8k_request_fw(priv, di->fw_image, &priv->fw_ucode);
a66098da 385 if (rc) {
c2c357ce 386 printk(KERN_ERR "%s: Error requesting firmware file %s\n",
a74b295e 387 pci_name(priv->pdev), di->fw_image);
22be40d9 388 mwl8k_release_fw(&priv->fw_helper);
a66098da
LB		 389 return rc;
390 }
391
392 return 0;
393}
394
7e75b942
BH		 395MODULE_FIRMWARE("mwl8k/helper_8687.fw");
396MODULE_FIRMWARE("mwl8k/fmimage_8687.fw");
397
a66098da
LB		 398struct mwl8k_cmd_pkt {
399 __le16 code;
400 __le16 length;
401 __le16 seq_num;
402 __le16 result;
403 char payload[0];
404} __attribute__((packed));
405
406/*
407 * Firmware loading.
408 */
409static int
410mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
411{
412 void __iomem *regs = priv->regs;
413 dma_addr_t dma_addr;
a66098da
LB		 414 int loops;
415
416 dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
417 if (pci_dma_mapping_error(priv->pdev, dma_addr))
418 return -ENOMEM;
419
420 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
421 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
422 iowrite32(MWL8K_H2A_INT_DOORBELL,
423 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
424 iowrite32(MWL8K_H2A_INT_DUMMY,
425 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
426
a66098da
LB		 427 loops = 1000;
428 do {
429 u32 int_code;
430
431 int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
432 if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
433 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
a66098da
LB		 434 break;
435 }
436
3d76e82c 437 cond_resched();
a66098da
LB		 438 udelay(1);
439 } while (--loops);
440
441 pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
442
d4b70570 443 return loops ? 0 : -ETIMEDOUT;
a66098da
LB		 444}
445
446static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
447 const u8 *data, size_t length)
448{
449 struct mwl8k_cmd_pkt *cmd;
450 int done;
451 int rc = 0;
452
453 cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
454 if (cmd == NULL)
455 return -ENOMEM;
456
457 cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
458 cmd->seq_num = 0;
459 cmd->result = 0;
460
461 done = 0;
462 while (length) {
463 int block_size = length > 256 ? 256 : length;
464
465 memcpy(cmd->payload, data + done, block_size);
466 cmd->length = cpu_to_le16(block_size);
467
468 rc = mwl8k_send_fw_load_cmd(priv, cmd,
469 sizeof(*cmd) + block_size);
470 if (rc)
471 break;
472
473 done += block_size;
474 length -= block_size;
475 }
476
477 if (!rc) {
478 cmd->length = 0;
479 rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
480 }
481
482 kfree(cmd);
483
484 return rc;
485}
486
487static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
488 const u8 *data, size_t length)
489{
490 unsigned char *buffer;
491 int may_continue, rc = 0;
492 u32 done, prev_block_size;
493
494 buffer = kmalloc(1024, GFP_KERNEL);
495 if (buffer == NULL)
496 return -ENOMEM;
497
498 done = 0;
499 prev_block_size = 0;
500 may_continue = 1000;
501 while (may_continue > 0) {
502 u32 block_size;
503
504 block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
505 if (block_size & 1) {
506 block_size &= ~1;
507 may_continue--;
508 } else {
509 done += prev_block_size;
510 length -= prev_block_size;
511 }
512
513 if (block_size > 1024 || block_size > length) {
514 rc = -EOVERFLOW;
515 break;
516 }
517
518 if (length == 0) {
519 rc = 0;
520 break;
521 }
522
523 if (block_size == 0) {
524 rc = -EPROTO;
525 may_continue--;
526 udelay(1);
527 continue;
528 }
529
530 prev_block_size = block_size;
531 memcpy(buffer, data + done, block_size);
532
533 rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
534 if (rc)
535 break;
536 }
537
538 if (!rc && length != 0)
539 rc = -EREMOTEIO;
540
541 kfree(buffer);
542
543 return rc;
544}
545
c2c357ce 546static int mwl8k_load_firmware(struct ieee80211_hw *hw)
a66098da 547{
c2c357ce 548 struct mwl8k_priv *priv = hw->priv;
22be40d9 549 struct firmware *fw = priv->fw_ucode;
c2c357ce
LB		 550 int rc;
551 int loops;
552
553 if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) {
22be40d9 554 struct firmware *helper = priv->fw_helper;
a66098da 555
c2c357ce
LB		 556 if (helper == NULL) {
557 printk(KERN_ERR "%s: helper image needed but none "
558 "given\n", pci_name(priv->pdev));
559 return -EINVAL;
560 }
a66098da 561
c2c357ce 562 rc = mwl8k_load_fw_image(priv, helper->data, helper->size);
a66098da
LB		 563 if (rc) {
564 printk(KERN_ERR "%s: unable to load firmware "
c2c357ce 565 "helper image\n", pci_name(priv->pdev));
a66098da
LB		 566 return rc;
567 }
89b872e2 568 msleep(5);
a66098da 569
c2c357ce 570 rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
a66098da 571 } else {
c2c357ce 572 rc = mwl8k_load_fw_image(priv, fw->data, fw->size);
a66098da
LB		 573 }
574
575 if (rc) {
c2c357ce
LB		 576 printk(KERN_ERR "%s: unable to load firmware image\n",
577 pci_name(priv->pdev));
a66098da
LB		 578 return rc;
579 }
580
89a91f4f 581 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
a66098da 582
89b872e2 583 loops = 500000;
a66098da 584 do {
eae74e65
LB		 585 u32 ready_code;
586
587 ready_code = ioread32(priv->regs + MWL8K_HIU_INT_CODE);
588 if (ready_code == MWL8K_FWAP_READY) {
589 priv->ap_fw = 1;
590 break;
591 } else if (ready_code == MWL8K_FWSTA_READY) {
592 priv->ap_fw = 0;
a66098da 593 break;
eae74e65
LB		 594 }
595
596 cond_resched();
a66098da
LB		 597 udelay(1);
598 } while (--loops);
599
600 return loops ? 0 : -ETIMEDOUT;
601}
602
603
a66098da
LB		 604/* DMA header used by firmware and hardware. */
605struct mwl8k_dma_data {
606 __le16 fwlen;
607 struct ieee80211_hdr wh;
20f09c3d 608 char data[0];
a66098da
LB		 609} __attribute__((packed));
610
611/* Routines to add/remove DMA header from skb. */
20f09c3d 612static inline void mwl8k_remove_dma_header(struct sk_buff *skb, __le16 qos)
a66098da 613{
20f09c3d
LB		 614 struct mwl8k_dma_data *tr;
615 int hdrlen;
616
617 tr = (struct mwl8k_dma_data *)skb->data;
618 hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
619
620 if (hdrlen != sizeof(tr->wh)) {
621 if (ieee80211_is_data_qos(tr->wh.frame_control)) {
622 memmove(tr->data - hdrlen, &tr->wh, hdrlen - 2);
623 *((__le16 *)(tr->data - 2)) = qos;
624 } else {
625 memmove(tr->data - hdrlen, &tr->wh, hdrlen);
626 }
a66098da 627 }
20f09c3d
LB		 628
629 if (hdrlen != sizeof(*tr))
630 skb_pull(skb, sizeof(*tr) - hdrlen);
a66098da
LB		 631}
632
76266b2a 633static inline void mwl8k_add_dma_header(struct sk_buff *skb)
a66098da
LB		 634{
635 struct ieee80211_hdr *wh;
ca009301 636 int hdrlen;
a66098da
LB		 637 struct mwl8k_dma_data *tr;
638
ca009301
LB		 639 /*
640 * Add a firmware DMA header; the firmware requires that we
641 * present a 2-byte payload length followed by a 4-address
642 * header (without QoS field), followed (optionally) by any
643 * WEP/ExtIV header (but only filled in for CCMP).
644 */
a66098da 645 wh = (struct ieee80211_hdr *)skb->data;
ca009301 646
a66098da 647 hdrlen = ieee80211_hdrlen(wh->frame_control);
ca009301
LB		 648 if (hdrlen != sizeof(*tr))
649 skb_push(skb, sizeof(*tr) - hdrlen);
a66098da 650
ca009301
LB		 651 if (ieee80211_is_data_qos(wh->frame_control))
652 hdrlen -= 2;
a66098da
LB		 653
654 tr = (struct mwl8k_dma_data *)skb->data;
655 if (wh != &tr->wh)
656 memmove(&tr->wh, wh, hdrlen);
ca009301
LB		 657 if (hdrlen != sizeof(tr->wh))
658 memset(((void *)&tr->wh) + hdrlen, 0, sizeof(tr->wh) - hdrlen);
a66098da
LB		 659
660 /*
661 * Firmware length is the length of the fully formed "802.11
662 * payload". That is, everything except for the 802.11 header.
663 * This includes all crypto material including the MIC.
664 */
ca009301 665 tr->fwlen = cpu_to_le16(skb->len - sizeof(*tr));
a66098da
LB		 666}
667
668
669/*
89a91f4f 670 * Packet reception for 88w8366 AP firmware.
6f6d1e9a 671 */
89a91f4f 672struct mwl8k_rxd_8366_ap {
6f6d1e9a
LB		 673 __le16 pkt_len;
674 __u8 sq2;
675 __u8 rate;
676 __le32 pkt_phys_addr;
677 __le32 next_rxd_phys_addr;
678 __le16 qos_control;
679 __le16 htsig2;
680 __le32 hw_rssi_info;
681 __le32 hw_noise_floor_info;
682 __u8 noise_floor;
683 __u8 pad0[3];
684 __u8 rssi;
685 __u8 rx_status;
686 __u8 channel;
687 __u8 rx_ctrl;
688} __attribute__((packed));
689
89a91f4f
LB		 690#define MWL8K_8366_AP_RATE_INFO_MCS_FORMAT 0x80
691#define MWL8K_8366_AP_RATE_INFO_40MHZ 0x40
692#define MWL8K_8366_AP_RATE_INFO_RATEID(x) ((x) & 0x3f)
8e9f33f0 693
89a91f4f 694#define MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST 0x80
6f6d1e9a 695
89a91f4f 696static void mwl8k_rxd_8366_ap_init(void *_rxd, dma_addr_t next_dma_addr)
6f6d1e9a 697{
89a91f4f 698 struct mwl8k_rxd_8366_ap *rxd = _rxd;
6f6d1e9a
LB		 699
700 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
89a91f4f 701 rxd->rx_ctrl = MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST;
6f6d1e9a
LB		 702}
703
89a91f4f 704static void mwl8k_rxd_8366_ap_refill(void *_rxd, dma_addr_t addr, int len)
6f6d1e9a 705{
89a91f4f 706 struct mwl8k_rxd_8366_ap *rxd = _rxd;
6f6d1e9a
LB		 707
708 rxd->pkt_len = cpu_to_le16(len);
709 rxd->pkt_phys_addr = cpu_to_le32(addr);
710 wmb();
711 rxd->rx_ctrl = 0;
712}
713
714static int
89a91f4f
LB		 715mwl8k_rxd_8366_ap_process(void *_rxd, struct ieee80211_rx_status *status,
716 __le16 *qos)
6f6d1e9a 717{
89a91f4f 718 struct mwl8k_rxd_8366_ap *rxd = _rxd;
6f6d1e9a 719
89a91f4f 720 if (!(rxd->rx_ctrl & MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST))
6f6d1e9a
LB		 721 return -1;
722 rmb();
723
724 memset(status, 0, sizeof(*status));
725
726 status->signal = -rxd->rssi;
727 status->noise = -rxd->noise_floor;
728
89a91f4f 729 if (rxd->rate & MWL8K_8366_AP_RATE_INFO_MCS_FORMAT) {
6f6d1e9a 730 status->flag |= RX_FLAG_HT;
89a91f4f 731 if (rxd->rate & MWL8K_8366_AP_RATE_INFO_40MHZ)
8e9f33f0 732 status->flag |= RX_FLAG_40MHZ;
89a91f4f 733 status->rate_idx = MWL8K_8366_AP_RATE_INFO_RATEID(rxd->rate);
6f6d1e9a
LB		 734 } else {
735 int i;
736
737 for (i = 0; i < ARRAY_SIZE(mwl8k_rates); i++) {
738 if (mwl8k_rates[i].hw_value == rxd->rate) {
739 status->rate_idx = i;
740 break;
741 }
742 }
743 }
744
745 status->band = IEEE80211_BAND_2GHZ;
746 status->freq = ieee80211_channel_to_frequency(rxd->channel);
747
20f09c3d
LB		 748 *qos = rxd->qos_control;
749
6f6d1e9a
LB		 750 return le16_to_cpu(rxd->pkt_len);
751}
752
89a91f4f
LB		 753static struct rxd_ops rxd_8366_ap_ops = {
754 .rxd_size = sizeof(struct mwl8k_rxd_8366_ap),
755 .rxd_init = mwl8k_rxd_8366_ap_init,
756 .rxd_refill = mwl8k_rxd_8366_ap_refill,
757 .rxd_process = mwl8k_rxd_8366_ap_process,
6f6d1e9a
LB		 758};
759
760/*
89a91f4f 761 * Packet reception for STA firmware.
a66098da 762 */
89a91f4f 763struct mwl8k_rxd_sta {
a66098da
LB		 764 __le16 pkt_len;
765 __u8 link_quality;
766 __u8 noise_level;
767 __le32 pkt_phys_addr;
45eb400d 768 __le32 next_rxd_phys_addr;
a66098da
LB		 769 __le16 qos_control;
770 __le16 rate_info;
771 __le32 pad0[4];
772 __u8 rssi;
773 __u8 channel;
774 __le16 pad1;
775 __u8 rx_ctrl;
776 __u8 rx_status;
777 __u8 pad2[2];
778} __attribute__((packed));
779
89a91f4f
LB		 780#define MWL8K_STA_RATE_INFO_SHORTPRE 0x8000
781#define MWL8K_STA_RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3)
782#define MWL8K_STA_RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f)
783#define MWL8K_STA_RATE_INFO_40MHZ 0x0004
784#define MWL8K_STA_RATE_INFO_SHORTGI 0x0002
785#define MWL8K_STA_RATE_INFO_MCS_FORMAT 0x0001
54bc3a0d 786
89a91f4f 787#define MWL8K_STA_RX_CTRL_OWNED_BY_HOST 0x02
54bc3a0d 788
89a91f4f 789static void mwl8k_rxd_sta_init(void *_rxd, dma_addr_t next_dma_addr)
54bc3a0d 790{
89a91f4f 791 struct mwl8k_rxd_sta *rxd = _rxd;
54bc3a0d
LB		 792
793 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
89a91f4f 794 rxd->rx_ctrl = MWL8K_STA_RX_CTRL_OWNED_BY_HOST;
54bc3a0d
LB		 795}
796
89a91f4f 797static void mwl8k_rxd_sta_refill(void *_rxd, dma_addr_t addr, int len)
54bc3a0d 798{
89a91f4f 799 struct mwl8k_rxd_sta *rxd = _rxd;
54bc3a0d
LB		 800
801 rxd->pkt_len = cpu_to_le16(len);
802 rxd->pkt_phys_addr = cpu_to_le32(addr);
803 wmb();
804 rxd->rx_ctrl = 0;
805}
806
807static int
89a91f4f 808mwl8k_rxd_sta_process(void *_rxd, struct ieee80211_rx_status *status,
20f09c3d 809 __le16 *qos)
54bc3a0d 810{
89a91f4f 811 struct mwl8k_rxd_sta *rxd = _rxd;
54bc3a0d
LB		 812 u16 rate_info;
813
89a91f4f 814 if (!(rxd->rx_ctrl & MWL8K_STA_RX_CTRL_OWNED_BY_HOST))
54bc3a0d
LB		 815 return -1;
816 rmb();
817
818 rate_info = le16_to_cpu(rxd->rate_info);
819
820 memset(status, 0, sizeof(*status));
821
822 status->signal = -rxd->rssi;
823 status->noise = -rxd->noise_level;
89a91f4f
LB		 824 status->antenna = MWL8K_STA_RATE_INFO_ANTSELECT(rate_info);
825 status->rate_idx = MWL8K_STA_RATE_INFO_RATEID(rate_info);
54bc3a0d 826
89a91f4f 827 if (rate_info & MWL8K_STA_RATE_INFO_SHORTPRE)
54bc3a0d 828 status->flag |= RX_FLAG_SHORTPRE;
89a91f4f 829 if (rate_info & MWL8K_STA_RATE_INFO_40MHZ)
54bc3a0d 830 status->flag |= RX_FLAG_40MHZ;
89a91f4f 831 if (rate_info & MWL8K_STA_RATE_INFO_SHORTGI)
54bc3a0d 832 status->flag |= RX_FLAG_SHORT_GI;
89a91f4f 833 if (rate_info & MWL8K_STA_RATE_INFO_MCS_FORMAT)
54bc3a0d
LB		 834 status->flag |= RX_FLAG_HT;
835
836 status->band = IEEE80211_BAND_2GHZ;
837 status->freq = ieee80211_channel_to_frequency(rxd->channel);
838
20f09c3d
LB		 839 *qos = rxd->qos_control;
840
54bc3a0d
LB		 841 return le16_to_cpu(rxd->pkt_len);
842}
843
89a91f4f
LB		 844static struct rxd_ops rxd_sta_ops = {
845 .rxd_size = sizeof(struct mwl8k_rxd_sta),
846 .rxd_init = mwl8k_rxd_sta_init,
847 .rxd_refill = mwl8k_rxd_sta_refill,
848 .rxd_process = mwl8k_rxd_sta_process,
54bc3a0d
LB		 849};
850
851
a66098da
LB		 852#define MWL8K_RX_DESCS 256
853#define MWL8K_RX_MAXSZ 3800
854
855static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
856{
857 struct mwl8k_priv *priv = hw->priv;
858 struct mwl8k_rx_queue *rxq = priv->rxq + index;
859 int size;
860 int i;
861
45eb400d
LB		 862 rxq->rxd_count = 0;
863 rxq->head = 0;
864 rxq->tail = 0;
a66098da 865
54bc3a0d 866 size = MWL8K_RX_DESCS * priv->rxd_ops->rxd_size;
a66098da 867
45eb400d
LB		 868 rxq->rxd = pci_alloc_consistent(priv->pdev, size, &rxq->rxd_dma);
869 if (rxq->rxd == NULL) {
a66098da 870 printk(KERN_ERR "%s: failed to alloc RX descriptors\n",
c2c357ce 871 wiphy_name(hw->wiphy));
a66098da
LB		 872 return -ENOMEM;
873 }
45eb400d 874 memset(rxq->rxd, 0, size);
a66098da 875
788838eb
LB		 876 rxq->buf = kmalloc(MWL8K_RX_DESCS * sizeof(*rxq->buf), GFP_KERNEL);
877 if (rxq->buf == NULL) {
a66098da 878 printk(KERN_ERR "%s: failed to alloc RX skbuff list\n",
c2c357ce 879 wiphy_name(hw->wiphy));
45eb400d 880 pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma);
a66098da
LB		 881 return -ENOMEM;
882 }
788838eb 883 memset(rxq->buf, 0, MWL8K_RX_DESCS * sizeof(*rxq->buf));
a66098da
LB		 884
885 for (i = 0; i < MWL8K_RX_DESCS; i++) {
54bc3a0d
LB		 886 int desc_size;
887 void *rxd;
a66098da 888 int nexti;
54bc3a0d
LB		 889 dma_addr_t next_dma_addr;
890
891 desc_size = priv->rxd_ops->rxd_size;
892 rxd = rxq->rxd + (i * priv->rxd_ops->rxd_size);
a66098da 893
54bc3a0d
LB		 894 nexti = i + 1;
895 if (nexti == MWL8K_RX_DESCS)
896 nexti = 0;
897 next_dma_addr = rxq->rxd_dma + (nexti * desc_size);
a66098da 898
54bc3a0d 899 priv->rxd_ops->rxd_init(rxd, next_dma_addr);
a66098da
LB		 900 }
901
902 return 0;
903}
904
905static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
906{
907 struct mwl8k_priv *priv = hw->priv;
908 struct mwl8k_rx_queue *rxq = priv->rxq + index;
909 int refilled;
910
911 refilled = 0;
45eb400d 912 while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) {
a66098da 913 struct sk_buff *skb;
788838eb 914 dma_addr_t addr;
a66098da 915 int rx;
54bc3a0d 916 void *rxd;
a66098da
LB		 917
918 skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
919 if (skb == NULL)
920 break;
921
788838eb
LB		 922 addr = pci_map_single(priv->pdev, skb->data,
923 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE);
a66098da 924
54bc3a0d
LB		 925 rxq->rxd_count++;
926 rx = rxq->tail++;
927 if (rxq->tail == MWL8K_RX_DESCS)
928 rxq->tail = 0;
788838eb
LB		 929 rxq->buf[rx].skb = skb;
930 pci_unmap_addr_set(&rxq->buf[rx], dma, addr);
54bc3a0d
LB		 931
932 rxd = rxq->rxd + (rx * priv->rxd_ops->rxd_size);
933 priv->rxd_ops->rxd_refill(rxd, addr, MWL8K_RX_MAXSZ);
a66098da
LB		 934
935 refilled++;
936 }
937
938 return refilled;
939}
940
941/* Must be called only when the card's reception is completely halted */
942static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
943{
944 struct mwl8k_priv *priv = hw->priv;
945 struct mwl8k_rx_queue *rxq = priv->rxq + index;
946 int i;
947
948 for (i = 0; i < MWL8K_RX_DESCS; i++) {
788838eb
LB		 949 if (rxq->buf[i].skb != NULL) {
950 pci_unmap_single(priv->pdev,
951 pci_unmap_addr(&rxq->buf[i], dma),
952 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
953 pci_unmap_addr_set(&rxq->buf[i], dma, 0);
954
955 kfree_skb(rxq->buf[i].skb);
956 rxq->buf[i].skb = NULL;
a66098da
LB		 957 }
958 }
959
788838eb
LB		 960 kfree(rxq->buf);
961 rxq->buf = NULL;
a66098da
LB		 962
963 pci_free_consistent(priv->pdev,
54bc3a0d 964 MWL8K_RX_DESCS * priv->rxd_ops->rxd_size,
45eb400d
LB		 965 rxq->rxd, rxq->rxd_dma);
966 rxq->rxd = NULL;
a66098da
LB		 967}
968
969
970/*
971 * Scan a list of BSSIDs to process for finalize join.
972 * Allows for extension to process multiple BSSIDs.
973 */
974static inline int
975mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
976{
977 return priv->capture_beacon &&
978 ieee80211_is_beacon(wh->frame_control) &&
979 !compare_ether_addr(wh->addr3, priv->capture_bssid);
980}
981
3779752d
LB		 982static inline void mwl8k_save_beacon(struct ieee80211_hw *hw,
983 struct sk_buff *skb)
a66098da 984{
3779752d
LB		 985 struct mwl8k_priv *priv = hw->priv;
986
a66098da 987 priv->capture_beacon = false;
d89173f2 988 memset(priv->capture_bssid, 0, ETH_ALEN);
a66098da
LB		 989
990 /*
991 * Use GFP_ATOMIC as rxq_process is called from
992 * the primary interrupt handler, memory allocation call
993 * must not sleep.
994 */
995 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
996 if (priv->beacon_skb != NULL)
3779752d 997 ieee80211_queue_work(hw, &priv->finalize_join_worker);
a66098da
LB		 998}
999
1000static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
1001{
1002 struct mwl8k_priv *priv = hw->priv;
1003 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1004 int processed;
1005
1006 processed = 0;
45eb400d 1007 while (rxq->rxd_count && limit--) {
a66098da 1008 struct sk_buff *skb;
54bc3a0d
LB		 1009 void *rxd;
1010 int pkt_len;
a66098da 1011 struct ieee80211_rx_status status;
20f09c3d 1012 __le16 qos;
a66098da 1013
788838eb 1014 skb = rxq->buf[rxq->head].skb;
d25f9f13
LB		 1015 if (skb == NULL)
1016 break;
54bc3a0d
LB		 1017
1018 rxd = rxq->rxd + (rxq->head * priv->rxd_ops->rxd_size);
1019
20f09c3d 1020 pkt_len = priv->rxd_ops->rxd_process(rxd, &status, &qos);
54bc3a0d
LB		 1021 if (pkt_len < 0)
1022 break;
1023
788838eb
LB		 1024 rxq->buf[rxq->head].skb = NULL;
1025
1026 pci_unmap_single(priv->pdev,
1027 pci_unmap_addr(&rxq->buf[rxq->head], dma),
1028 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
1029 pci_unmap_addr_set(&rxq->buf[rxq->head], dma, 0);
a66098da 1030
54bc3a0d
LB		 1031 rxq->head++;
1032 if (rxq->head == MWL8K_RX_DESCS)
1033 rxq->head = 0;
1034
45eb400d 1035 rxq->rxd_count--;
a66098da 1036
54bc3a0d 1037 skb_put(skb, pkt_len);
20f09c3d 1038 mwl8k_remove_dma_header(skb, qos);
a66098da 1039
a66098da 1040 /*
c2c357ce
LB		 1041 * Check for a pending join operation. Save a
1042 * copy of the beacon and schedule a tasklet to
1043 * send a FINALIZE_JOIN command to the firmware.
a66098da 1044 */
54bc3a0d 1045 if (mwl8k_capture_bssid(priv, (void *)skb->data))
3779752d 1046 mwl8k_save_beacon(hw, skb);
a66098da 1047
f1d58c25
JB		 1048 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
1049 ieee80211_rx_irqsafe(hw, skb);
a66098da
LB		 1050
1051 processed++;
1052 }
1053
1054 return processed;
1055}
1056
1057
1058/*
1059 * Packet transmission.
1060 */
1061
a66098da
LB		 1062#define MWL8K_TXD_STATUS_OK 0x00000001
1063#define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
1064#define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
1065#define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
a66098da 1066#define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
a66098da 1067
e0493a8d
LB		 1068#define MWL8K_QOS_QLEN_UNSPEC 0xff00
1069#define MWL8K_QOS_ACK_POLICY_MASK 0x0060
1070#define MWL8K_QOS_ACK_POLICY_NORMAL 0x0000
1071#define MWL8K_QOS_ACK_POLICY_BLOCKACK 0x0060
1072#define MWL8K_QOS_EOSP 0x0010
1073
a66098da
LB		 1074struct mwl8k_tx_desc {
1075 __le32 status;
1076 __u8 data_rate;
1077 __u8 tx_priority;
1078 __le16 qos_control;
1079 __le32 pkt_phys_addr;
1080 __le16 pkt_len;
d89173f2 1081 __u8 dest_MAC_addr[ETH_ALEN];
45eb400d 1082 __le32 next_txd_phys_addr;
a66098da
LB		 1083 __le32 reserved;
1084 __le16 rate_info;
1085 __u8 peer_id;
1086 __u8 tx_frag_cnt;
1087} __attribute__((packed));
1088
1089#define MWL8K_TX_DESCS 128
1090
1091static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
1092{
1093 struct mwl8k_priv *priv = hw->priv;
1094 struct mwl8k_tx_queue *txq = priv->txq + index;
1095 int size;
1096 int i;
1097
45eb400d
LB		 1098 memset(&txq->stats, 0, sizeof(struct ieee80211_tx_queue_stats));
1099 txq->stats.limit = MWL8K_TX_DESCS;
1100 txq->head = 0;
1101 txq->tail = 0;
a66098da
LB		 1102
1103 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
1104
45eb400d
LB		 1105 txq->txd = pci_alloc_consistent(priv->pdev, size, &txq->txd_dma);
1106 if (txq->txd == NULL) {
a66098da 1107 printk(KERN_ERR "%s: failed to alloc TX descriptors\n",
c2c357ce 1108 wiphy_name(hw->wiphy));
a66098da
LB		 1109 return -ENOMEM;
1110 }
45eb400d 1111 memset(txq->txd, 0, size);
a66098da 1112
45eb400d
LB		 1113 txq->skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->skb), GFP_KERNEL);
1114 if (txq->skb == NULL) {
a66098da 1115 printk(KERN_ERR "%s: failed to alloc TX skbuff list\n",
c2c357ce 1116 wiphy_name(hw->wiphy));
45eb400d 1117 pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma);
a66098da
LB		 1118 return -ENOMEM;
1119 }
45eb400d 1120 memset(txq->skb, 0, MWL8K_TX_DESCS * sizeof(*txq->skb));
a66098da
LB		 1121
1122 for (i = 0; i < MWL8K_TX_DESCS; i++) {
1123 struct mwl8k_tx_desc *tx_desc;
1124 int nexti;
1125
45eb400d 1126 tx_desc = txq->txd + i;
a66098da
LB		 1127 nexti = (i + 1) % MWL8K_TX_DESCS;
1128
1129 tx_desc->status = 0;
45eb400d
LB		 1130 tx_desc->next_txd_phys_addr =
1131 cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc));
a66098da
LB		 1132 }
1133
1134 return 0;
1135}
1136
1137static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
1138{
1139 iowrite32(MWL8K_H2A_INT_PPA_READY,
1140 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1141 iowrite32(MWL8K_H2A_INT_DUMMY,
1142 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1143 ioread32(priv->regs + MWL8K_HIU_INT_CODE);
1144}
1145
7e1112d3 1146static void mwl8k_dump_tx_rings(struct ieee80211_hw *hw)
a66098da 1147{
7e1112d3
LB		 1148 struct mwl8k_priv *priv = hw->priv;
1149 int i;
1150
1151 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
1152 struct mwl8k_tx_queue *txq = priv->txq + i;
1153 int fw_owned = 0;
1154 int drv_owned = 0;
1155 int unused = 0;
1156 int desc;
1157
a66098da 1158 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
7e1112d3
LB		 1159 struct mwl8k_tx_desc *tx_desc = txq->txd + desc;
1160 u32 status;
a66098da 1161
7e1112d3 1162 status = le32_to_cpu(tx_desc->status);
a66098da 1163 if (status & MWL8K_TXD_STATUS_FW_OWNED)
7e1112d3 1164 fw_owned++;
a66098da 1165 else
7e1112d3 1166 drv_owned++;
a66098da
LB		 1167
1168 if (tx_desc->pkt_len == 0)
7e1112d3 1169 unused++;
a66098da 1170 }
a66098da 1171
7e1112d3
LB		 1172 printk(KERN_ERR "%s: txq[%d] len=%d head=%d tail=%d "
1173 "fw_owned=%d drv_owned=%d unused=%d\n",
1174 wiphy_name(hw->wiphy), i,
1175 txq->stats.len, txq->head, txq->tail,
1176 fw_owned, drv_owned, unused);
1177 }
a66098da
LB		 1178}
1179
618952a7 1180/*
88de754a 1181 * Must be called with priv->fw_mutex held and tx queues stopped.
618952a7 1182 */
7e1112d3
LB		 1183#define MWL8K_TX_WAIT_TIMEOUT_MS 1000
1184
950d5b01 1185static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
a66098da 1186{
a66098da 1187 struct mwl8k_priv *priv = hw->priv;
88de754a 1188 DECLARE_COMPLETION_ONSTACK(tx_wait);
7e1112d3
LB		 1189 int retry;
1190 int rc;
a66098da
LB		 1191
1192 might_sleep();
1193
7e1112d3
LB		 1194 /*
1195 * The TX queues are stopped at this point, so this test
1196 * doesn't need to take ->tx_lock.
1197 */
1198 if (!priv->pending_tx_pkts)
1199 return 0;
1200
1201 retry = 0;
1202 rc = 0;
1203
a66098da 1204 spin_lock_bh(&priv->tx_lock);
7e1112d3
LB		 1205 priv->tx_wait = &tx_wait;
1206 while (!rc) {
1207 int oldcount;
1208 unsigned long timeout;
a66098da 1209
7e1112d3 1210 oldcount = priv->pending_tx_pkts;
a66098da 1211
7e1112d3 1212 spin_unlock_bh(&priv->tx_lock);
88de754a 1213 timeout = wait_for_completion_timeout(&tx_wait,
7e1112d3 1214 msecs_to_jiffies(MWL8K_TX_WAIT_TIMEOUT_MS));
a66098da 1215 spin_lock_bh(&priv->tx_lock);
7e1112d3
LB		 1216
1217 if (timeout) {
1218 WARN_ON(priv->pending_tx_pkts);
1219 if (retry) {
1220 printk(KERN_NOTICE "%s: tx rings drained\n",
1221 wiphy_name(hw->wiphy));
1222 }
1223 break;
1224 }
1225
1226 if (priv->pending_tx_pkts < oldcount) {
9a2303b9
LB		 1227 printk(KERN_NOTICE "%s: waiting for tx rings "
1228 "to drain (%d -> %d pkts)\n",
7e1112d3
LB		 1229 wiphy_name(hw->wiphy), oldcount,
1230 priv->pending_tx_pkts);
1231 retry = 1;
1232 continue;
1233 }
1234
a66098da 1235 priv->tx_wait = NULL;
a66098da 1236
7e1112d3
LB		 1237 printk(KERN_ERR "%s: tx rings stuck for %d ms\n",
1238 wiphy_name(hw->wiphy), MWL8K_TX_WAIT_TIMEOUT_MS);
1239 mwl8k_dump_tx_rings(hw);
1240
1241 rc = -ETIMEDOUT;
a66098da 1242 }
7e1112d3 1243 spin_unlock_bh(&priv->tx_lock);
a66098da 1244
7e1112d3 1245 return rc;
a66098da
LB		 1246}
1247
c23b5a69
LB		 1248#define MWL8K_TXD_SUCCESS(status) \
1249 ((status) & (MWL8K_TXD_STATUS_OK | \
1250 MWL8K_TXD_STATUS_OK_RETRY | \
1251 MWL8K_TXD_STATUS_OK_MORE_RETRY))
a66098da
LB		 1252
1253static void mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int force)
1254{
1255 struct mwl8k_priv *priv = hw->priv;
1256 struct mwl8k_tx_queue *txq = priv->txq + index;
1257 int wake = 0;
1258
45eb400d 1259 while (txq->stats.len > 0) {
a66098da 1260 int tx;
a66098da
LB		 1261 struct mwl8k_tx_desc *tx_desc;
1262 unsigned long addr;
ce9e2e1b 1263 int size;
a66098da
LB		 1264 struct sk_buff *skb;
1265 struct ieee80211_tx_info *info;
1266 u32 status;
1267
45eb400d
LB		 1268 tx = txq->head;
1269 tx_desc = txq->txd + tx;
a66098da
LB		 1270
1271 status = le32_to_cpu(tx_desc->status);
1272
1273 if (status & MWL8K_TXD_STATUS_FW_OWNED) {
1274 if (!force)
1275 break;
1276 tx_desc->status &=
1277 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
1278 }
1279
45eb400d
LB		 1280 txq->head = (tx + 1) % MWL8K_TX_DESCS;
1281 BUG_ON(txq->stats.len == 0);
1282 txq->stats.len--;
a66098da
LB		 1283 priv->pending_tx_pkts--;
1284
1285 addr = le32_to_cpu(tx_desc->pkt_phys_addr);
ce9e2e1b 1286 size = le16_to_cpu(tx_desc->pkt_len);
45eb400d
LB		 1287 skb = txq->skb[tx];
1288 txq->skb[tx] = NULL;
a66098da
LB		 1289
1290 BUG_ON(skb == NULL);
1291 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
1292
20f09c3d 1293 mwl8k_remove_dma_header(skb, tx_desc->qos_control);
a66098da
LB		 1294
1295 /* Mark descriptor as unused */
1296 tx_desc->pkt_phys_addr = 0;
1297 tx_desc->pkt_len = 0;
1298
a66098da
LB		 1299 info = IEEE80211_SKB_CB(skb);
1300 ieee80211_tx_info_clear_status(info);
ce9e2e1b 1301 if (MWL8K_TXD_SUCCESS(status))
a66098da 1302 info->flags |= IEEE80211_TX_STAT_ACK;
a66098da
LB		 1303
1304 ieee80211_tx_status_irqsafe(hw, skb);
1305
618952a7 1306 wake = 1;
a66098da
LB		 1307 }
1308
618952a7 1309 if (wake && priv->radio_on && !mutex_is_locked(&priv->fw_mutex))
a66098da
LB		 1310 ieee80211_wake_queue(hw, index);
1311}
1312
1313/* must be called only when the card's transmit is completely halted */
1314static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
1315{
1316 struct mwl8k_priv *priv = hw->priv;
1317 struct mwl8k_tx_queue *txq = priv->txq + index;
1318
1319 mwl8k_txq_reclaim(hw, index, 1);
1320
45eb400d
LB		 1321 kfree(txq->skb);
1322 txq->skb = NULL;
a66098da
LB		 1323
1324 pci_free_consistent(priv->pdev,
1325 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
45eb400d
LB		 1326 txq->txd, txq->txd_dma);
1327 txq->txd = NULL;
a66098da
LB		 1328}
1329
1330static int
1331mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
1332{
1333 struct mwl8k_priv *priv = hw->priv;
1334 struct ieee80211_tx_info *tx_info;
23b33906 1335 struct mwl8k_vif *mwl8k_vif;
a66098da
LB		 1336 struct ieee80211_hdr *wh;
1337 struct mwl8k_tx_queue *txq;
1338 struct mwl8k_tx_desc *tx;
a66098da 1339 dma_addr_t dma;
23b33906
LB		 1340 u32 txstatus;
1341 u8 txdatarate;
1342 u16 qos;
a66098da 1343
23b33906
LB		 1344 wh = (struct ieee80211_hdr *)skb->data;
1345 if (ieee80211_is_data_qos(wh->frame_control))
1346 qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
1347 else
1348 qos = 0;
a66098da 1349
76266b2a 1350 mwl8k_add_dma_header(skb);
23b33906 1351 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
a66098da
LB		 1352
1353 tx_info = IEEE80211_SKB_CB(skb);
1354 mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
a66098da
LB		 1355
1356 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1357 u16 seqno = mwl8k_vif->seqno;
23b33906 1358
a66098da
LB		 1359 wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1360 wh->seq_ctrl |= cpu_to_le16(seqno << 4);
1361 mwl8k_vif->seqno = seqno++ % 4096;
1362 }
1363
23b33906
LB		 1364 /* Setup firmware control bit fields for each frame type. */
1365 txstatus = 0;
1366 txdatarate = 0;
1367 if (ieee80211_is_mgmt(wh->frame_control) ||
1368 ieee80211_is_ctl(wh->frame_control)) {
1369 txdatarate = 0;
e0493a8d 1370 qos |= MWL8K_QOS_QLEN_UNSPEC | MWL8K_QOS_EOSP;
23b33906
LB		 1371 } else if (ieee80211_is_data(wh->frame_control)) {
1372 txdatarate = 1;
1373 if (is_multicast_ether_addr(wh->addr1))
1374 txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
1375
e0493a8d 1376 qos &= ~MWL8K_QOS_ACK_POLICY_MASK;
23b33906 1377 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
e0493a8d 1378 qos |= MWL8K_QOS_ACK_POLICY_BLOCKACK;
23b33906 1379 else
e0493a8d 1380 qos |= MWL8K_QOS_ACK_POLICY_NORMAL;
23b33906 1381 }
a66098da
LB		 1382
1383 dma = pci_map_single(priv->pdev, skb->data,
1384 skb->len, PCI_DMA_TODEVICE);
1385
1386 if (pci_dma_mapping_error(priv->pdev, dma)) {
1387 printk(KERN_DEBUG "%s: failed to dma map skb, "
c2c357ce 1388 "dropping TX frame.\n", wiphy_name(hw->wiphy));
23b33906 1389 dev_kfree_skb(skb);
a66098da
LB		 1390 return NETDEV_TX_OK;
1391 }
1392
23b33906 1393 spin_lock_bh(&priv->tx_lock);
a66098da 1394
23b33906 1395 txq = priv->txq + index;
a66098da 1396
45eb400d
LB		 1397 BUG_ON(txq->skb[txq->tail] != NULL);
1398 txq->skb[txq->tail] = skb;
a66098da 1399
45eb400d 1400 tx = txq->txd + txq->tail;
23b33906
LB		 1401 tx->data_rate = txdatarate;
1402 tx->tx_priority = index;
a66098da 1403 tx->qos_control = cpu_to_le16(qos);
a66098da
LB		 1404 tx->pkt_phys_addr = cpu_to_le32(dma);
1405 tx->pkt_len = cpu_to_le16(skb->len);
23b33906 1406 tx->rate_info = 0;
a680400e
LB		 1407 if (!priv->ap_fw && tx_info->control.sta != NULL)
1408 tx->peer_id = MWL8K_STA(tx_info->control.sta)->peer_id;
1409 else
1410 tx->peer_id = 0;
a66098da 1411 wmb();
23b33906
LB		 1412 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus);
1413
45eb400d
LB		 1414 txq->stats.count++;
1415 txq->stats.len++;
a66098da 1416 priv->pending_tx_pkts++;
a66098da 1417
45eb400d
LB		 1418 txq->tail++;
1419 if (txq->tail == MWL8K_TX_DESCS)
1420 txq->tail = 0;
23b33906 1421
45eb400d 1422 if (txq->head == txq->tail)
a66098da
LB		 1423 ieee80211_stop_queue(hw, index);
1424
23b33906 1425 mwl8k_tx_start(priv);
a66098da
LB		 1426
1427 spin_unlock_bh(&priv->tx_lock);
1428
1429 return NETDEV_TX_OK;
1430}
1431
1432
618952a7
LB		 1433/*
1434 * Firmware access.
1435 *
1436 * We have the following requirements for issuing firmware commands:
1437 * - Some commands require that the packet transmit path is idle when
1438 * the command is issued. (For simplicity, we'll just quiesce the
1439 * transmit path for every command.)
1440 * - There are certain sequences of commands that need to be issued to
1441 * the hardware sequentially, with no other intervening commands.
1442 *
1443 * This leads to an implementation of a "firmware lock" as a mutex that
1444 * can be taken recursively, and which is taken by both the low-level
1445 * command submission function (mwl8k_post_cmd) as well as any users of
1446 * that function that require issuing of an atomic sequence of commands,
1447 * and quiesces the transmit path whenever it's taken.
1448 */
1449static int mwl8k_fw_lock(struct ieee80211_hw *hw)
1450{
1451 struct mwl8k_priv *priv = hw->priv;
1452
1453 if (priv->fw_mutex_owner != current) {
1454 int rc;
1455
1456 mutex_lock(&priv->fw_mutex);
1457 ieee80211_stop_queues(hw);
1458
1459 rc = mwl8k_tx_wait_empty(hw);
1460 if (rc) {
1461 ieee80211_wake_queues(hw);
1462 mutex_unlock(&priv->fw_mutex);
1463
1464 return rc;
1465 }
1466
1467 priv->fw_mutex_owner = current;
1468 }
1469
1470 priv->fw_mutex_depth++;
1471
1472 return 0;
1473}
1474
1475static void mwl8k_fw_unlock(struct ieee80211_hw *hw)
1476{
1477 struct mwl8k_priv *priv = hw->priv;
1478
1479 if (!--priv->fw_mutex_depth) {
1480 ieee80211_wake_queues(hw);
1481 priv->fw_mutex_owner = NULL;
1482 mutex_unlock(&priv->fw_mutex);
1483 }
1484}
1485
1486
a66098da
LB		 1487/*
1488 * Command processing.
1489 */
1490
0c9cc640
LB		 1491/* Timeout firmware commands after 10s */
1492#define MWL8K_CMD_TIMEOUT_MS 10000
a66098da
LB		 1493
1494static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
1495{
1496 DECLARE_COMPLETION_ONSTACK(cmd_wait);
1497 struct mwl8k_priv *priv = hw->priv;
1498 void __iomem *regs = priv->regs;
1499 dma_addr_t dma_addr;
1500 unsigned int dma_size;
1501 int rc;
a66098da
LB		 1502 unsigned long timeout = 0;
1503 u8 buf[32];
1504
c2c357ce 1505 cmd->result = 0xffff;
a66098da
LB		 1506 dma_size = le16_to_cpu(cmd->length);
1507 dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
1508 PCI_DMA_BIDIRECTIONAL);
1509 if (pci_dma_mapping_error(priv->pdev, dma_addr))
1510 return -ENOMEM;
1511
618952a7 1512 rc = mwl8k_fw_lock(hw);
39a1e42e
LB		 1513 if (rc) {
1514 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1515 PCI_DMA_BIDIRECTIONAL);
618952a7 1516 return rc;
39a1e42e 1517 }
a66098da 1518
a66098da
LB		 1519 priv->hostcmd_wait = &cmd_wait;
1520 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
1521 iowrite32(MWL8K_H2A_INT_DOORBELL,
1522 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1523 iowrite32(MWL8K_H2A_INT_DUMMY,
1524 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
a66098da
LB		 1525
1526 timeout = wait_for_completion_timeout(&cmd_wait,
1527 msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
1528
618952a7
LB		 1529 priv->hostcmd_wait = NULL;
1530
1531 mwl8k_fw_unlock(hw);
1532
37055bd4
LB		 1533 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1534 PCI_DMA_BIDIRECTIONAL);
1535
a66098da 1536 if (!timeout) {
a66098da 1537 printk(KERN_ERR "%s: Command %s timeout after %u ms\n",
c2c357ce 1538 wiphy_name(hw->wiphy),
a66098da
LB		 1539 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1540 MWL8K_CMD_TIMEOUT_MS);
1541 rc = -ETIMEDOUT;
1542 } else {
0c9cc640
LB		 1543 int ms;
1544
1545 ms = MWL8K_CMD_TIMEOUT_MS - jiffies_to_msecs(timeout);
1546
ce9e2e1b 1547 rc = cmd->result ? -EINVAL : 0;
a66098da
LB		 1548 if (rc)
1549 printk(KERN_ERR "%s: Command %s error 0x%x\n",
c2c357ce 1550 wiphy_name(hw->wiphy),
a66098da 1551 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
76c962a2 1552 le16_to_cpu(cmd->result));
0c9cc640
LB		 1553 else if (ms > 2000)
1554 printk(KERN_NOTICE "%s: Command %s took %d ms\n",
1555 wiphy_name(hw->wiphy),
1556 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1557 ms);
a66098da
LB		 1558 }
1559
a66098da
LB		 1560 return rc;
1561}
1562
1563/*
04b147b1 1564 * CMD_GET_HW_SPEC (STA version).
a66098da 1565 */
04b147b1 1566struct mwl8k_cmd_get_hw_spec_sta {
a66098da
LB		 1567 struct mwl8k_cmd_pkt header;
1568 __u8 hw_rev;
1569 __u8 host_interface;
1570 __le16 num_mcaddrs;
d89173f2 1571 __u8 perm_addr[ETH_ALEN];
a66098da
LB		 1572 __le16 region_code;
1573 __le32 fw_rev;
1574 __le32 ps_cookie;
1575 __le32 caps;
1576 __u8 mcs_bitmap[16];
1577 __le32 rx_queue_ptr;
1578 __le32 num_tx_queues;
1579 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1580 __le32 caps2;
1581 __le32 num_tx_desc_per_queue;
45eb400d 1582 __le32 total_rxd;
a66098da
LB		 1583} __attribute__((packed));
1584
04b147b1 1585static int mwl8k_cmd_get_hw_spec_sta(struct ieee80211_hw *hw)
a66098da
LB		 1586{
1587 struct mwl8k_priv *priv = hw->priv;
04b147b1 1588 struct mwl8k_cmd_get_hw_spec_sta *cmd;
a66098da
LB		 1589 int rc;
1590 int i;
1591
1592 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1593 if (cmd == NULL)
1594 return -ENOMEM;
1595
1596 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1597 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1598
1599 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1600 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
45eb400d 1601 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
4ff6432e 1602 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
a66098da 1603 for (i = 0; i < MWL8K_TX_QUEUES; i++)
45eb400d 1604 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
4ff6432e 1605 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
45eb400d 1606 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
a66098da
LB		 1607
1608 rc = mwl8k_post_cmd(hw, &cmd->header);
1609
1610 if (!rc) {
1611 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1612 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
4ff6432e 1613 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
a66098da 1614 priv->hw_rev = cmd->hw_rev;
a66098da
LB		 1615 }
1616
1617 kfree(cmd);
1618 return rc;
1619}
1620
42fba21d
LB		 1621/*
1622 * CMD_GET_HW_SPEC (AP version).
1623 */
1624struct mwl8k_cmd_get_hw_spec_ap {
1625 struct mwl8k_cmd_pkt header;
1626 __u8 hw_rev;
1627 __u8 host_interface;
1628 __le16 num_wcb;
1629 __le16 num_mcaddrs;
1630 __u8 perm_addr[ETH_ALEN];
1631 __le16 region_code;
1632 __le16 num_antenna;
1633 __le32 fw_rev;
1634 __le32 wcbbase0;
1635 __le32 rxwrptr;
1636 __le32 rxrdptr;
1637 __le32 ps_cookie;
1638 __le32 wcbbase1;
1639 __le32 wcbbase2;
1640 __le32 wcbbase3;
1641} __attribute__((packed));
1642
1643static int mwl8k_cmd_get_hw_spec_ap(struct ieee80211_hw *hw)
1644{
1645 struct mwl8k_priv *priv = hw->priv;
1646 struct mwl8k_cmd_get_hw_spec_ap *cmd;
1647 int rc;
1648
1649 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1650 if (cmd == NULL)
1651 return -ENOMEM;
1652
1653 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1654 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1655
1656 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1657 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1658
1659 rc = mwl8k_post_cmd(hw, &cmd->header);
1660
1661 if (!rc) {
1662 int off;
1663
1664 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1665 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
1666 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
1667 priv->hw_rev = cmd->hw_rev;
1668
1669 off = le32_to_cpu(cmd->wcbbase0) & 0xffff;
1670 iowrite32(cpu_to_le32(priv->txq[0].txd_dma), priv->sram + off);
1671
1672 off = le32_to_cpu(cmd->rxwrptr) & 0xffff;
1673 iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
1674
1675 off = le32_to_cpu(cmd->rxrdptr) & 0xffff;
1676 iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
1677
1678 off = le32_to_cpu(cmd->wcbbase1) & 0xffff;
1679 iowrite32(cpu_to_le32(priv->txq[1].txd_dma), priv->sram + off);
1680
1681 off = le32_to_cpu(cmd->wcbbase2) & 0xffff;
1682 iowrite32(cpu_to_le32(priv->txq[2].txd_dma), priv->sram + off);
1683
1684 off = le32_to_cpu(cmd->wcbbase3) & 0xffff;
1685 iowrite32(cpu_to_le32(priv->txq[3].txd_dma), priv->sram + off);
1686 }
1687
1688 kfree(cmd);
1689 return rc;
1690}
1691
1692/*
1693 * CMD_SET_HW_SPEC.
1694 */
1695struct mwl8k_cmd_set_hw_spec {
1696 struct mwl8k_cmd_pkt header;
1697 __u8 hw_rev;
1698 __u8 host_interface;
1699 __le16 num_mcaddrs;
1700 __u8 perm_addr[ETH_ALEN];
1701 __le16 region_code;
1702 __le32 fw_rev;
1703 __le32 ps_cookie;
1704 __le32 caps;
1705 __le32 rx_queue_ptr;
1706 __le32 num_tx_queues;
1707 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1708 __le32 flags;
1709 __le32 num_tx_desc_per_queue;
1710 __le32 total_rxd;
1711} __attribute__((packed));
1712
1713#define MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT 0x00000080
1714
1715static int mwl8k_cmd_set_hw_spec(struct ieee80211_hw *hw)
1716{
1717 struct mwl8k_priv *priv = hw->priv;
1718 struct mwl8k_cmd_set_hw_spec *cmd;
1719 int rc;
1720 int i;
1721
1722 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1723 if (cmd == NULL)
1724 return -ENOMEM;
1725
1726 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_HW_SPEC);
1727 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1728
1729 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1730 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
1731 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
1732 for (i = 0; i < MWL8K_TX_QUEUES; i++)
1733 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
1734 cmd->flags = cpu_to_le32(MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT);
1735 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
1736 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
1737
1738 rc = mwl8k_post_cmd(hw, &cmd->header);
1739 kfree(cmd);
1740
1741 return rc;
1742}
1743
a66098da
LB		 1744/*
1745 * CMD_MAC_MULTICAST_ADR.
1746 */
1747struct mwl8k_cmd_mac_multicast_adr {
1748 struct mwl8k_cmd_pkt header;
1749 __le16 action;
1750 __le16 numaddr;
ce9e2e1b 1751 __u8 addr[0][ETH_ALEN];
a66098da
LB		 1752};
1753
d5e30845
LB		 1754#define MWL8K_ENABLE_RX_DIRECTED 0x0001
1755#define MWL8K_ENABLE_RX_MULTICAST 0x0002
1756#define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004
1757#define MWL8K_ENABLE_RX_BROADCAST 0x0008
ce9e2e1b 1758
e81cd2d6 1759static struct mwl8k_cmd_pkt *
447ced07 1760__mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti,
e81cd2d6 1761 int mc_count, struct dev_addr_list *mclist)
a66098da 1762{
e81cd2d6 1763 struct mwl8k_priv *priv = hw->priv;
a66098da 1764 struct mwl8k_cmd_mac_multicast_adr *cmd;
e81cd2d6 1765 int size;
e81cd2d6 1766
447ced07 1767 if (allmulti || mc_count > priv->num_mcaddrs) {
d5e30845
LB		 1768 allmulti = 1;
1769 mc_count = 0;
1770 }
e81cd2d6
LB		 1771
1772 size = sizeof(*cmd) + mc_count * ETH_ALEN;
ce9e2e1b 1773
e81cd2d6 1774 cmd = kzalloc(size, GFP_ATOMIC);
a66098da 1775 if (cmd == NULL)
e81cd2d6 1776 return NULL;
a66098da
LB		 1777
1778 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
1779 cmd->header.length = cpu_to_le16(size);
d5e30845
LB		 1780 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED |
1781 MWL8K_ENABLE_RX_BROADCAST);
1782
1783 if (allmulti) {
1784 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST);
1785 } else if (mc_count) {
1786 int i;
1787
1788 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
1789 cmd->numaddr = cpu_to_le16(mc_count);
1790 for (i = 0; i < mc_count && mclist; i++) {
1791 if (mclist->da_addrlen != ETH_ALEN) {
1792 kfree(cmd);
1793 return NULL;
1794 }
1795 memcpy(cmd->addr[i], mclist->da_addr, ETH_ALEN);
1796 mclist = mclist->next;
a66098da 1797 }
a66098da
LB		 1798 }
1799
e81cd2d6 1800 return &cmd->header;
a66098da
LB		 1801}
1802
1803/*
55489b6e 1804 * CMD_GET_STAT.
a66098da 1805 */
55489b6e 1806struct mwl8k_cmd_get_stat {
a66098da 1807 struct mwl8k_cmd_pkt header;
a66098da
LB		 1808 __le32 stats[64];
1809} __attribute__((packed));
1810
1811#define MWL8K_STAT_ACK_FAILURE 9
1812#define MWL8K_STAT_RTS_FAILURE 12
1813#define MWL8K_STAT_FCS_ERROR 24
1814#define MWL8K_STAT_RTS_SUCCESS 11
1815
55489b6e
LB		 1816static int mwl8k_cmd_get_stat(struct ieee80211_hw *hw,
1817 struct ieee80211_low_level_stats *stats)
a66098da 1818{
55489b6e 1819 struct mwl8k_cmd_get_stat *cmd;
a66098da
LB		 1820 int rc;
1821
1822 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1823 if (cmd == NULL)
1824 return -ENOMEM;
1825
1826 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
1827 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB		 1828
1829 rc = mwl8k_post_cmd(hw, &cmd->header);
1830 if (!rc) {
1831 stats->dot11ACKFailureCount =
1832 le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
1833 stats->dot11RTSFailureCount =
1834 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
1835 stats->dot11FCSErrorCount =
1836 le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
1837 stats->dot11RTSSuccessCount =
1838 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
1839 }
1840 kfree(cmd);
1841
1842 return rc;
1843}
1844
1845/*
55489b6e 1846 * CMD_RADIO_CONTROL.
a66098da 1847 */
55489b6e 1848struct mwl8k_cmd_radio_control {
a66098da
LB		 1849 struct mwl8k_cmd_pkt header;
1850 __le16 action;
1851 __le16 control;
1852 __le16 radio_on;
1853} __attribute__((packed));
1854
c46563b7 1855static int
55489b6e 1856mwl8k_cmd_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
a66098da
LB		 1857{
1858 struct mwl8k_priv *priv = hw->priv;
55489b6e 1859 struct mwl8k_cmd_radio_control *cmd;
a66098da
LB		 1860 int rc;
1861
c46563b7 1862 if (enable == priv->radio_on && !force)
a66098da
LB		 1863 return 0;
1864
a66098da
LB		 1865 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1866 if (cmd == NULL)
1867 return -ENOMEM;
1868
1869 cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
1870 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1871 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
68ce3884 1872 cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
a66098da
LB		 1873 cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
1874
1875 rc = mwl8k_post_cmd(hw, &cmd->header);
1876 kfree(cmd);
1877
1878 if (!rc)
c46563b7 1879 priv->radio_on = enable;
a66098da
LB		 1880
1881 return rc;
1882}
1883
55489b6e 1884static int mwl8k_cmd_radio_disable(struct ieee80211_hw *hw)
c46563b7 1885{
55489b6e 1886 return mwl8k_cmd_radio_control(hw, 0, 0);
c46563b7
LB		 1887}
1888
55489b6e 1889static int mwl8k_cmd_radio_enable(struct ieee80211_hw *hw)
c46563b7 1890{
55489b6e 1891 return mwl8k_cmd_radio_control(hw, 1, 0);
c46563b7
LB		 1892}
1893
a66098da
LB		 1894static int
1895mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
1896{
99200a99 1897 struct mwl8k_priv *priv = hw->priv;
a66098da 1898
68ce3884 1899 priv->radio_short_preamble = short_preamble;
a66098da 1900
55489b6e 1901 return mwl8k_cmd_radio_control(hw, 1, 1);
a66098da
LB		 1902}
1903
1904/*
55489b6e 1905 * CMD_RF_TX_POWER.
a66098da
LB		 1906 */
1907#define MWL8K_TX_POWER_LEVEL_TOTAL 8
1908
55489b6e 1909struct mwl8k_cmd_rf_tx_power {
a66098da
LB		 1910 struct mwl8k_cmd_pkt header;
1911 __le16 action;
1912 __le16 support_level;
1913 __le16 current_level;
1914 __le16 reserved;
1915 __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
1916} __attribute__((packed));
1917
55489b6e 1918static int mwl8k_cmd_rf_tx_power(struct ieee80211_hw *hw, int dBm)
a66098da 1919{
55489b6e 1920 struct mwl8k_cmd_rf_tx_power *cmd;
a66098da
LB		 1921 int rc;
1922
1923 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1924 if (cmd == NULL)
1925 return -ENOMEM;
1926
1927 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
1928 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1929 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1930 cmd->support_level = cpu_to_le16(dBm);
1931
1932 rc = mwl8k_post_cmd(hw, &cmd->header);
1933 kfree(cmd);
1934
1935 return rc;
1936}
1937
08b06347
LB		 1938/*
1939 * CMD_RF_ANTENNA.
1940 */
1941struct mwl8k_cmd_rf_antenna {
1942 struct mwl8k_cmd_pkt header;
1943 __le16 antenna;
1944 __le16 mode;
1945} __attribute__((packed));
1946
1947#define MWL8K_RF_ANTENNA_RX 1
1948#define MWL8K_RF_ANTENNA_TX 2
1949
1950static int
1951mwl8k_cmd_rf_antenna(struct ieee80211_hw *hw, int antenna, int mask)
1952{
1953 struct mwl8k_cmd_rf_antenna *cmd;
1954 int rc;
1955
1956 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1957 if (cmd == NULL)
1958 return -ENOMEM;
1959
1960 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_ANTENNA);
1961 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1962 cmd->antenna = cpu_to_le16(antenna);
1963 cmd->mode = cpu_to_le16(mask);
1964
1965 rc = mwl8k_post_cmd(hw, &cmd->header);
1966 kfree(cmd);
1967
1968 return rc;
1969}
1970
a66098da
LB		 1971/*
1972 * CMD_SET_PRE_SCAN.
1973 */
1974struct mwl8k_cmd_set_pre_scan {
1975 struct mwl8k_cmd_pkt header;
1976} __attribute__((packed));
1977
1978static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
1979{
1980 struct mwl8k_cmd_set_pre_scan *cmd;
1981 int rc;
1982
1983 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1984 if (cmd == NULL)
1985 return -ENOMEM;
1986
1987 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
1988 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1989
1990 rc = mwl8k_post_cmd(hw, &cmd->header);
1991 kfree(cmd);
1992
1993 return rc;
1994}
1995
1996/*
1997 * CMD_SET_POST_SCAN.
1998 */
1999struct mwl8k_cmd_set_post_scan {
2000 struct mwl8k_cmd_pkt header;
2001 __le32 isibss;
d89173f2 2002 __u8 bssid[ETH_ALEN];
a66098da
LB		 2003} __attribute__((packed));
2004
2005static int
0a11dfc3 2006mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, const __u8 *mac)
a66098da
LB		 2007{
2008 struct mwl8k_cmd_set_post_scan *cmd;
2009 int rc;
2010
2011 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2012 if (cmd == NULL)
2013 return -ENOMEM;
2014
2015 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
2016 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2017 cmd->isibss = 0;
d89173f2 2018 memcpy(cmd->bssid, mac, ETH_ALEN);
a66098da
LB		 2019
2020 rc = mwl8k_post_cmd(hw, &cmd->header);
2021 kfree(cmd);
2022
2023 return rc;
2024}
2025
2026/*
2027 * CMD_SET_RF_CHANNEL.
2028 */
2029struct mwl8k_cmd_set_rf_channel {
2030 struct mwl8k_cmd_pkt header;
2031 __le16 action;
2032 __u8 current_channel;
2033 __le32 channel_flags;
2034} __attribute__((packed));
2035
2036static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
2037 struct ieee80211_channel *channel)
2038{
2039 struct mwl8k_cmd_set_rf_channel *cmd;
2040 int rc;
2041
2042 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2043 if (cmd == NULL)
2044 return -ENOMEM;
2045
2046 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
2047 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2048 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2049 cmd->current_channel = channel->hw_value;
2050 if (channel->band == IEEE80211_BAND_2GHZ)
2051 cmd->channel_flags = cpu_to_le32(0x00000081);
2052 else
2053 cmd->channel_flags = cpu_to_le32(0x00000000);
2054
2055 rc = mwl8k_post_cmd(hw, &cmd->header);
2056 kfree(cmd);
2057
2058 return rc;
2059}
2060
2061/*
55489b6e 2062 * CMD_SET_AID.
a66098da 2063 */
55489b6e
LB		 2064#define MWL8K_FRAME_PROT_DISABLED 0x00
2065#define MWL8K_FRAME_PROT_11G 0x07
2066#define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
2067#define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
a66098da 2068
55489b6e
LB		 2069struct mwl8k_cmd_update_set_aid {
2070 struct mwl8k_cmd_pkt header;
2071 __le16 aid;
a66098da 2072
55489b6e
LB		 2073 /* AP's MAC address (BSSID) */
2074 __u8 bssid[ETH_ALEN];
2075 __le16 protection_mode;
2076 __u8 supp_rates[14];
a66098da
LB		 2077} __attribute__((packed));
2078
55489b6e
LB		 2079static int
2080mwl8k_cmd_set_aid(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
a66098da 2081{
55489b6e
LB		 2082 struct mwl8k_cmd_update_set_aid *cmd;
2083 u16 prot_mode;
a66098da
LB		 2084 int rc;
2085
2086 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2087 if (cmd == NULL)
2088 return -ENOMEM;
2089
55489b6e 2090 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
a66098da 2091 cmd->header.length = cpu_to_le16(sizeof(*cmd));
7dc6a7a7 2092 cmd->aid = cpu_to_le16(vif->bss_conf.aid);
a66098da 2093
0a11dfc3 2094 memcpy(cmd->bssid, vif->bss_conf.bssid, ETH_ALEN);
a66098da 2095
7dc6a7a7 2096 if (vif->bss_conf.use_cts_prot) {
55489b6e
LB		 2097 prot_mode = MWL8K_FRAME_PROT_11G;
2098 } else {
7dc6a7a7 2099 switch (vif->bss_conf.ht_operation_mode &
55489b6e
LB		 2100 IEEE80211_HT_OP_MODE_PROTECTION) {
2101 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
2102 prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
2103 break;
2104 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
2105 prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
2106 break;
2107 default:
2108 prot_mode = MWL8K_FRAME_PROT_DISABLED;
2109 break;
2110 }
2111 }
2112 cmd->protection_mode = cpu_to_le16(prot_mode);
a66098da 2113
55489b6e 2114 memcpy(cmd->supp_rates, mwl8k_rateids, sizeof(mwl8k_rateids));
a66098da
LB		 2115
2116 rc = mwl8k_post_cmd(hw, &cmd->header);
2117 kfree(cmd);
2118
2119 return rc;
2120}
2121
32060e1b 2122/*
55489b6e 2123 * CMD_SET_RATE.
32060e1b 2124 */
55489b6e
LB		 2125struct mwl8k_cmd_set_rate {
2126 struct mwl8k_cmd_pkt header;
2127 __u8 legacy_rates[14];
2128
2129 /* Bitmap for supported MCS codes. */
2130 __u8 mcs_set[16];
2131 __u8 reserved[16];
32060e1b
LB		 2132} __attribute__((packed));
2133
55489b6e
LB		 2134static int
2135mwl8k_cmd_set_rate(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
32060e1b 2136{
55489b6e 2137 struct mwl8k_cmd_set_rate *cmd;
32060e1b
LB		 2138 int rc;
2139
2140 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2141 if (cmd == NULL)
2142 return -ENOMEM;
2143
55489b6e 2144 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
32060e1b 2145 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e 2146 memcpy(cmd->legacy_rates, mwl8k_rateids, sizeof(mwl8k_rateids));
32060e1b
LB		 2147
2148 rc = mwl8k_post_cmd(hw, &cmd->header);
2149 kfree(cmd);
2150
2151 return rc;
2152}
2153
a66098da 2154/*
55489b6e 2155 * CMD_FINALIZE_JOIN.
a66098da 2156 */
55489b6e
LB		 2157#define MWL8K_FJ_BEACON_MAXLEN 128
2158
2159struct mwl8k_cmd_finalize_join {
a66098da 2160 struct mwl8k_cmd_pkt header;
55489b6e
LB		 2161 __le32 sleep_interval; /* Number of beacon periods to sleep */
2162 __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
a66098da
LB		 2163} __attribute__((packed));
2164
55489b6e
LB		 2165static int mwl8k_cmd_finalize_join(struct ieee80211_hw *hw, void *frame,
2166 int framelen, int dtim)
a66098da 2167{
55489b6e
LB		 2168 struct mwl8k_cmd_finalize_join *cmd;
2169 struct ieee80211_mgmt *payload = frame;
2170 int payload_len;
a66098da
LB		 2171 int rc;
2172
2173 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2174 if (cmd == NULL)
2175 return -ENOMEM;
2176
55489b6e 2177 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
a66098da 2178 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB		 2179 cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
2180
2181 payload_len = framelen - ieee80211_hdrlen(payload->frame_control);
2182 if (payload_len < 0)
2183 payload_len = 0;
2184 else if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2185 payload_len = MWL8K_FJ_BEACON_MAXLEN;
2186
2187 memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
a66098da
LB		 2188
2189 rc = mwl8k_post_cmd(hw, &cmd->header);
2190 kfree(cmd);
2191
2192 return rc;
2193}
2194
2195/*
55489b6e 2196 * CMD_SET_RTS_THRESHOLD.
a66098da 2197 */
55489b6e 2198struct mwl8k_cmd_set_rts_threshold {
a66098da
LB		 2199 struct mwl8k_cmd_pkt header;
2200 __le16 action;
55489b6e 2201 __le16 threshold;
a66098da
LB		 2202} __attribute__((packed));
2203
55489b6e
LB		 2204static int mwl8k_cmd_set_rts_threshold(struct ieee80211_hw *hw,
2205 u16 action, u16 threshold)
a66098da 2206{
55489b6e 2207 struct mwl8k_cmd_set_rts_threshold *cmd;
a66098da
LB		 2208 int rc;
2209
2210 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2211 if (cmd == NULL)
2212 return -ENOMEM;
2213
55489b6e 2214 cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
a66098da 2215 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB		 2216 cmd->action = cpu_to_le16(action);
2217 cmd->threshold = cpu_to_le16(threshold);
a66098da
LB		 2218
2219 rc = mwl8k_post_cmd(hw, &cmd->header);
2220 kfree(cmd);
2221
a66098da
LB		 2222 return rc;
2223}
2224
2225/*
55489b6e 2226 * CMD_SET_SLOT.
a66098da 2227 */
55489b6e 2228struct mwl8k_cmd_set_slot {
a66098da
LB		 2229 struct mwl8k_cmd_pkt header;
2230 __le16 action;
55489b6e 2231 __u8 short_slot;
a66098da
LB		 2232} __attribute__((packed));
2233
55489b6e 2234static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time)
a66098da 2235{
55489b6e 2236 struct mwl8k_cmd_set_slot *cmd;
a66098da
LB		 2237 int rc;
2238
2239 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2240 if (cmd == NULL)
2241 return -ENOMEM;
2242
55489b6e 2243 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
a66098da 2244 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB		 2245 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2246 cmd->short_slot = short_slot_time;
a66098da
LB		 2247
2248 rc = mwl8k_post_cmd(hw, &cmd->header);
2249 kfree(cmd);
2250
2251 return rc;
2252}
2253
2254/*
2255 * CMD_SET_EDCA_PARAMS.
2256 */
2257struct mwl8k_cmd_set_edca_params {
2258 struct mwl8k_cmd_pkt header;
2259
2260 /* See MWL8K_SET_EDCA_XXX below */
2261 __le16 action;
2262
2263 /* TX opportunity in units of 32 us */
2264 __le16 txop;
2265
2e484c89
LB		 2266 union {
2267 struct {
2268 /* Log exponent of max contention period: 0...15 */
2269 __le32 log_cw_max;
2270
2271 /* Log exponent of min contention period: 0...15 */
2272 __le32 log_cw_min;
2273
2274 /* Adaptive interframe spacing in units of 32us */
2275 __u8 aifs;
2276
2277 /* TX queue to configure */
2278 __u8 txq;
2279 } ap;
2280 struct {
2281 /* Log exponent of max contention period: 0...15 */
2282 __u8 log_cw_max;
a66098da 2283
2e484c89
LB		 2284 /* Log exponent of min contention period: 0...15 */
2285 __u8 log_cw_min;
a66098da 2286
2e484c89
LB		 2287 /* Adaptive interframe spacing in units of 32us */
2288 __u8 aifs;
a66098da 2289
2e484c89
LB		 2290 /* TX queue to configure */
2291 __u8 txq;
2292 } sta;
2293 };
a66098da
LB		 2294} __attribute__((packed));
2295
a66098da
LB		 2296#define MWL8K_SET_EDCA_CW 0x01
2297#define MWL8K_SET_EDCA_TXOP 0x02
2298#define MWL8K_SET_EDCA_AIFS 0x04
2299
2300#define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
2301 MWL8K_SET_EDCA_TXOP | \
2302 MWL8K_SET_EDCA_AIFS)
2303
2304static int
55489b6e
LB		 2305mwl8k_cmd_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
2306 __u16 cw_min, __u16 cw_max,
2307 __u8 aifs, __u16 txop)
a66098da 2308{
2e484c89 2309 struct mwl8k_priv *priv = hw->priv;
a66098da 2310 struct mwl8k_cmd_set_edca_params *cmd;
a66098da
LB		 2311 int rc;
2312
2313 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2314 if (cmd == NULL)
2315 return -ENOMEM;
2316
22995b24
LB		 2317 /*
2318 * Queues 0 (BE) and 1 (BK) are swapped in hardware for
2319 * this call.
2320 */
2321 qnum ^= !(qnum >> 1);
2322
a66098da
LB		 2323 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
2324 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB		 2325 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
2326 cmd->txop = cpu_to_le16(txop);
2e484c89
LB		 2327 if (priv->ap_fw) {
2328 cmd->ap.log_cw_max = cpu_to_le32(ilog2(cw_max + 1));
2329 cmd->ap.log_cw_min = cpu_to_le32(ilog2(cw_min + 1));
2330 cmd->ap.aifs = aifs;
2331 cmd->ap.txq = qnum;
2332 } else {
2333 cmd->sta.log_cw_max = (u8)ilog2(cw_max + 1);
2334 cmd->sta.log_cw_min = (u8)ilog2(cw_min + 1);
2335 cmd->sta.aifs = aifs;
2336 cmd->sta.txq = qnum;
2337 }
a66098da
LB		 2338
2339 rc = mwl8k_post_cmd(hw, &cmd->header);
2340 kfree(cmd);
2341
2342 return rc;
2343}
2344
2345/*
55489b6e 2346 * CMD_SET_WMM_MODE.
a66098da 2347 */
55489b6e 2348struct mwl8k_cmd_set_wmm_mode {
a66098da 2349 struct mwl8k_cmd_pkt header;
55489b6e 2350 __le16 action;
a66098da
LB		 2351} __attribute__((packed));
2352
55489b6e 2353static int mwl8k_cmd_set_wmm_mode(struct ieee80211_hw *hw, bool enable)
a66098da 2354{
55489b6e
LB		 2355 struct mwl8k_priv *priv = hw->priv;
2356 struct mwl8k_cmd_set_wmm_mode *cmd;
a66098da
LB		 2357 int rc;
2358
a66098da
LB		 2359 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2360 if (cmd == NULL)
2361 return -ENOMEM;
2362
55489b6e 2363 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
a66098da 2364 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e 2365 cmd->action = cpu_to_le16(!!enable);
a66098da
LB		 2366
2367 rc = mwl8k_post_cmd(hw, &cmd->header);
2368 kfree(cmd);
16cec43d 2369
55489b6e
LB		 2370 if (!rc)
2371 priv->wmm_enabled = enable;
a66098da
LB		 2372
2373 return rc;
2374}
2375
2376/*
55489b6e 2377 * CMD_MIMO_CONFIG.
a66098da 2378 */
55489b6e
LB		 2379struct mwl8k_cmd_mimo_config {
2380 struct mwl8k_cmd_pkt header;
2381 __le32 action;
2382 __u8 rx_antenna_map;
2383 __u8 tx_antenna_map;
a66098da
LB		 2384} __attribute__((packed));
2385
55489b6e 2386static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
a66098da 2387{
55489b6e 2388 struct mwl8k_cmd_mimo_config *cmd;
a66098da
LB		 2389 int rc;
2390
2391 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2392 if (cmd == NULL)
2393 return -ENOMEM;
2394
55489b6e 2395 cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
a66098da 2396 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB		 2397 cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
2398 cmd->rx_antenna_map = rx;
2399 cmd->tx_antenna_map = tx;
a66098da
LB		 2400
2401 rc = mwl8k_post_cmd(hw, &cmd->header);
2402 kfree(cmd);
2403
2404 return rc;
2405}
2406
2407/*
2408 * CMD_USE_FIXED_RATE.
2409 */
2410#define MWL8K_RATE_TABLE_SIZE 8
2411#define MWL8K_UCAST_RATE 0
a66098da
LB		 2412#define MWL8K_USE_AUTO_RATE 0x0002
2413
2414struct mwl8k_rate_entry {
2415 /* Set to 1 if HT rate, 0 if legacy. */
2416 __le32 is_ht_rate;
2417
2418 /* Set to 1 to use retry_count field. */
2419 __le32 enable_retry;
2420
2421 /* Specified legacy rate or MCS. */
2422 __le32 rate;
2423
2424 /* Number of allowed retries. */
2425 __le32 retry_count;
2426} __attribute__((packed));
2427
2428struct mwl8k_rate_table {
2429 /* 1 to allow specified rate and below */
2430 __le32 allow_rate_drop;
2431 __le32 num_rates;
2432 struct mwl8k_rate_entry rate_entry[MWL8K_RATE_TABLE_SIZE];
2433} __attribute__((packed));
2434
2435struct mwl8k_cmd_use_fixed_rate {
2436 struct mwl8k_cmd_pkt header;
2437 __le32 action;
2438 struct mwl8k_rate_table rate_table;
2439
2440 /* Unicast, Broadcast or Multicast */
2441 __le32 rate_type;
2442 __le32 reserved1;
2443 __le32 reserved2;
2444} __attribute__((packed));
2445
2446static int mwl8k_cmd_use_fixed_rate(struct ieee80211_hw *hw,
2447 u32 action, u32 rate_type, struct mwl8k_rate_table *rate_table)
2448{
2449 struct mwl8k_cmd_use_fixed_rate *cmd;
2450 int count;
2451 int rc;
2452
2453 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2454 if (cmd == NULL)
2455 return -ENOMEM;
2456
2457 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
2458 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2459
2460 cmd->action = cpu_to_le32(action);
2461 cmd->rate_type = cpu_to_le32(rate_type);
2462
2463 if (rate_table != NULL) {
c2c357ce
LB		 2464 /*
2465 * Copy over each field manually so that endian
2466 * conversion can be done.
2467 */
a66098da
LB		 2468 cmd->rate_table.allow_rate_drop =
2469 cpu_to_le32(rate_table->allow_rate_drop);
2470 cmd->rate_table.num_rates =
2471 cpu_to_le32(rate_table->num_rates);
2472
2473 for (count = 0; count < rate_table->num_rates; count++) {
2474 struct mwl8k_rate_entry *dst =
2475 &cmd->rate_table.rate_entry[count];
2476 struct mwl8k_rate_entry *src =
2477 &rate_table->rate_entry[count];
2478
2479 dst->is_ht_rate = cpu_to_le32(src->is_ht_rate);
2480 dst->enable_retry = cpu_to_le32(src->enable_retry);
2481 dst->rate = cpu_to_le32(src->rate);
2482 dst->retry_count = cpu_to_le32(src->retry_count);
2483 }
2484 }
2485
2486 rc = mwl8k_post_cmd(hw, &cmd->header);
2487 kfree(cmd);
2488
2489 return rc;
2490}
2491
55489b6e
LB		 2492/*
2493 * CMD_ENABLE_SNIFFER.
2494 */
2495struct mwl8k_cmd_enable_sniffer {
2496 struct mwl8k_cmd_pkt header;
2497 __le32 action;
2498} __attribute__((packed));
2499
2500static int mwl8k_cmd_enable_sniffer(struct ieee80211_hw *hw, bool enable)
2501{
2502 struct mwl8k_cmd_enable_sniffer *cmd;
2503 int rc;
2504
2505 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2506 if (cmd == NULL)
2507 return -ENOMEM;
2508
2509 cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
2510 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2511 cmd->action = cpu_to_le32(!!enable);
2512
2513 rc = mwl8k_post_cmd(hw, &cmd->header);
2514 kfree(cmd);
2515
2516 return rc;
2517}
2518
2519/*
2520 * CMD_SET_MAC_ADDR.
2521 */
2522struct mwl8k_cmd_set_mac_addr {
2523 struct mwl8k_cmd_pkt header;
2524 union {
2525 struct {
2526 __le16 mac_type;
2527 __u8 mac_addr[ETH_ALEN];
2528 } mbss;
2529 __u8 mac_addr[ETH_ALEN];
2530 };
2531} __attribute__((packed));
2532
2533static int mwl8k_cmd_set_mac_addr(struct ieee80211_hw *hw, u8 *mac)
2534{
2535 struct mwl8k_priv *priv = hw->priv;
2536 struct mwl8k_cmd_set_mac_addr *cmd;
2537 int rc;
2538
2539 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2540 if (cmd == NULL)
2541 return -ENOMEM;
2542
2543 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR);
2544 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2545 if (priv->ap_fw) {
2546 cmd->mbss.mac_type = 0;
2547 memcpy(cmd->mbss.mac_addr, mac, ETH_ALEN);
2548 } else {
2549 memcpy(cmd->mac_addr, mac, ETH_ALEN);
2550 }
2551
2552 rc = mwl8k_post_cmd(hw, &cmd->header);
2553 kfree(cmd);
2554
2555 return rc;
2556}
2557
2558/*
2559 * CMD_SET_RATEADAPT_MODE.
2560 */
2561struct mwl8k_cmd_set_rate_adapt_mode {
2562 struct mwl8k_cmd_pkt header;
2563 __le16 action;
2564 __le16 mode;
2565} __attribute__((packed));
2566
2567static int mwl8k_cmd_set_rateadapt_mode(struct ieee80211_hw *hw, __u16 mode)
2568{
2569 struct mwl8k_cmd_set_rate_adapt_mode *cmd;
2570 int rc;
2571
2572 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2573 if (cmd == NULL)
2574 return -ENOMEM;
2575
2576 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
2577 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2578 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2579 cmd->mode = cpu_to_le16(mode);
2580
2581 rc = mwl8k_post_cmd(hw, &cmd->header);
2582 kfree(cmd);
2583
2584 return rc;
2585}
2586
2587/*
2588 * CMD_UPDATE_STADB.
2589 */
25d81b1e
LB		 2590struct ewc_ht_info {
2591 __le16 control1;
2592 __le16 control2;
2593 __le16 control3;
2594} __attribute__((packed));
2595
2596struct peer_capability_info {
2597 /* Peer type - AP vs. STA. */
2598 __u8 peer_type;
2599
2600 /* Basic 802.11 capabilities from assoc resp. */
2601 __le16 basic_caps;
2602
2603 /* Set if peer supports 802.11n high throughput (HT). */
2604 __u8 ht_support;
2605
2606 /* Valid if HT is supported. */
2607 __le16 ht_caps;
2608 __u8 extended_ht_caps;
2609 struct ewc_ht_info ewc_info;
2610
2611 /* Legacy rate table. Intersection of our rates and peer rates. */
2612 __u8 legacy_rates[12];
2613
2614 /* HT rate table. Intersection of our rates and peer rates. */
2615 __u8 ht_rates[16];
2616 __u8 pad[16];
2617
2618 /* If set, interoperability mode, no proprietary extensions. */
2619 __u8 interop;
2620 __u8 pad2;
2621 __u8 station_id;
2622 __le16 amsdu_enabled;
2623} __attribute__((packed));
2624
55489b6e
LB		 2625struct mwl8k_cmd_update_stadb {
2626 struct mwl8k_cmd_pkt header;
2627
2628 /* See STADB_ACTION_TYPE */
2629 __le32 action;
2630
2631 /* Peer MAC address */
2632 __u8 peer_addr[ETH_ALEN];
2633
2634 __le32 reserved;
2635
2636 /* Peer info - valid during add/update. */
2637 struct peer_capability_info peer_info;
2638} __attribute__((packed));
2639
a680400e
LB		 2640#define MWL8K_STA_DB_MODIFY_ENTRY 1
2641#define MWL8K_STA_DB_DEL_ENTRY 2
2642
2643/* Peer Entry flags - used to define the type of the peer node */
2644#define MWL8K_PEER_TYPE_ACCESSPOINT 2
2645
2646static int mwl8k_cmd_update_stadb_add(struct ieee80211_hw *hw,
2647 struct ieee80211_vif *vif, u8 *addr)
55489b6e 2648{
55489b6e 2649 struct mwl8k_cmd_update_stadb *cmd;
a680400e 2650 struct peer_capability_info *p;
55489b6e
LB		 2651 int rc;
2652
2653 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2654 if (cmd == NULL)
2655 return -ENOMEM;
2656
2657 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
2658 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a680400e
LB		 2659 cmd->action = cpu_to_le32(MWL8K_STA_DB_MODIFY_ENTRY);
2660 memcpy(cmd->peer_addr, addr, ETH_ALEN);
55489b6e 2661
a680400e
LB		 2662 p = &cmd->peer_info;
2663 p->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
2664 p->basic_caps = cpu_to_le16(vif->bss_conf.assoc_capability);
2665 memcpy(p->legacy_rates, mwl8k_rateids, sizeof(mwl8k_rateids));
2666 p->interop = 1;
2667 p->amsdu_enabled = 0;
2668
2669 rc = mwl8k_post_cmd(hw, &cmd->header);
2670 kfree(cmd);
2671
2672 return rc ? rc : p->station_id;
2673}
2674
2675static int mwl8k_cmd_update_stadb_del(struct ieee80211_hw *hw,
2676 struct ieee80211_vif *vif, u8 *addr)
2677{
2678 struct mwl8k_cmd_update_stadb *cmd;
2679 int rc;
2680
2681 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2682 if (cmd == NULL)
2683 return -ENOMEM;
2684
2685 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
2686 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2687 cmd->action = cpu_to_le32(MWL8K_STA_DB_DEL_ENTRY);
bbfd9128 2688 memcpy(cmd->peer_addr, addr, ETH_ALEN);
55489b6e 2689
a680400e 2690 rc = mwl8k_post_cmd(hw, &cmd->header);
55489b6e
LB		 2691 kfree(cmd);
2692
2693 return rc;
2694}
2695
a66098da
LB		 2696
2697/*
2698 * Interrupt handling.
2699 */
2700static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
2701{
2702 struct ieee80211_hw *hw = dev_id;
2703 struct mwl8k_priv *priv = hw->priv;
2704 u32 status;
2705
2706 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2707 iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2708
a66098da
LB		 2709 if (!status)
2710 return IRQ_NONE;
2711
2712 if (status & MWL8K_A2H_INT_TX_DONE)
2713 tasklet_schedule(&priv->tx_reclaim_task);
2714
2715 if (status & MWL8K_A2H_INT_RX_READY) {
2716 while (rxq_process(hw, 0, 1))
2717 rxq_refill(hw, 0, 1);
2718 }
2719
2720 if (status & MWL8K_A2H_INT_OPC_DONE) {
618952a7 2721 if (priv->hostcmd_wait != NULL)
a66098da 2722 complete(priv->hostcmd_wait);
a66098da
LB		 2723 }
2724
2725 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
618952a7 2726 if (!mutex_is_locked(&priv->fw_mutex) &&
88de754a 2727 priv->radio_on && priv->pending_tx_pkts)
618952a7 2728 mwl8k_tx_start(priv);
a66098da
LB		 2729 }
2730
2731 return IRQ_HANDLED;
2732}
2733
2734
2735/*
2736 * Core driver operations.
2737 */
2738static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2739{
2740 struct mwl8k_priv *priv = hw->priv;
2741 int index = skb_get_queue_mapping(skb);
2742 int rc;
2743
2744 if (priv->current_channel == NULL) {
2745 printk(KERN_DEBUG "%s: dropped TX frame since radio "
c2c357ce 2746 "disabled\n", wiphy_name(hw->wiphy));
a66098da
LB		 2747 dev_kfree_skb(skb);
2748 return NETDEV_TX_OK;
2749 }
2750
2751 rc = mwl8k_txq_xmit(hw, index, skb);
2752
2753 return rc;
2754}
2755
a66098da
LB		 2756static int mwl8k_start(struct ieee80211_hw *hw)
2757{
a66098da
LB		 2758 struct mwl8k_priv *priv = hw->priv;
2759 int rc;
2760
a0607fd3 2761 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
a66098da
LB		 2762 IRQF_SHARED, MWL8K_NAME, hw);
2763 if (rc) {
2764 printk(KERN_ERR "%s: failed to register IRQ handler\n",
c2c357ce 2765 wiphy_name(hw->wiphy));
2ec610cb 2766 return -EIO;
a66098da
LB		 2767 }
2768
2ec610cb
LB		 2769 /* Enable tx reclaim tasklet */
2770 tasklet_enable(&priv->tx_reclaim_task);
2771
a66098da 2772 /* Enable interrupts */
c23b5a69 2773 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da 2774
2ec610cb
LB		 2775 rc = mwl8k_fw_lock(hw);
2776 if (!rc) {
55489b6e 2777 rc = mwl8k_cmd_radio_enable(hw);
a66098da 2778
5e4cf166
LB		 2779 if (!priv->ap_fw) {
2780 if (!rc)
55489b6e 2781 rc = mwl8k_cmd_enable_sniffer(hw, 0);
a66098da 2782
5e4cf166
LB		 2783 if (!rc)
2784 rc = mwl8k_cmd_set_pre_scan(hw);
2785
2786 if (!rc)
2787 rc = mwl8k_cmd_set_post_scan(hw,
2788 "\x00\x00\x00\x00\x00\x00");
2789 }
2ec610cb
LB		 2790
2791 if (!rc)
55489b6e 2792 rc = mwl8k_cmd_set_rateadapt_mode(hw, 0);
a66098da 2793
2ec610cb 2794 if (!rc)
55489b6e 2795 rc = mwl8k_cmd_set_wmm_mode(hw, 0);
a66098da 2796
2ec610cb
LB		 2797 mwl8k_fw_unlock(hw);
2798 }
2799
2800 if (rc) {
2801 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2802 free_irq(priv->pdev->irq, hw);
2803 tasklet_disable(&priv->tx_reclaim_task);
2804 }
a66098da
LB		 2805
2806 return rc;
2807}
2808
a66098da
LB		 2809static void mwl8k_stop(struct ieee80211_hw *hw)
2810{
a66098da
LB		 2811 struct mwl8k_priv *priv = hw->priv;
2812 int i;
2813
55489b6e 2814 mwl8k_cmd_radio_disable(hw);
a66098da
LB		 2815
2816 ieee80211_stop_queues(hw);
2817
a66098da 2818 /* Disable interrupts */
a66098da 2819 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 2820 free_irq(priv->pdev->irq, hw);
2821
2822 /* Stop finalize join worker */
2823 cancel_work_sync(&priv->finalize_join_worker);
2824 if (priv->beacon_skb != NULL)
2825 dev_kfree_skb(priv->beacon_skb);
2826
2827 /* Stop tx reclaim tasklet */
2828 tasklet_disable(&priv->tx_reclaim_task);
2829
a66098da
LB		 2830 /* Return all skbs to mac80211 */
2831 for (i = 0; i < MWL8K_TX_QUEUES; i++)
2832 mwl8k_txq_reclaim(hw, i, 1);
2833}
2834
2835static int mwl8k_add_interface(struct ieee80211_hw *hw,
1ed32e4f 2836 struct ieee80211_vif *vif)
a66098da
LB		 2837{
2838 struct mwl8k_priv *priv = hw->priv;
2839 struct mwl8k_vif *mwl8k_vif;
2840
2841 /*
2842 * We only support one active interface at a time.
2843 */
2844 if (priv->vif != NULL)
2845 return -EBUSY;
2846
2847 /*
2848 * We only support managed interfaces for now.
2849 */
1ed32e4f 2850 if (vif->type != NL80211_IFTYPE_STATION)
a66098da
LB		 2851 return -EINVAL;
2852
a43c49a8
LB		 2853 /*
2854 * Reject interface creation if sniffer mode is active, as
2855 * STA operation is mutually exclusive with hardware sniffer
2856 * mode.
2857 */
2858 if (priv->sniffer_enabled) {
2859 printk(KERN_INFO "%s: unable to create STA "
2860 "interface due to sniffer mode being enabled\n",
2861 wiphy_name(hw->wiphy));
2862 return -EINVAL;
2863 }
2864
a66098da 2865 /* Clean out driver private area */
1ed32e4f 2866 mwl8k_vif = MWL8K_VIF(vif);
a66098da
LB		 2867 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
2868
32060e1b 2869 /* Set and save the mac address */
1ed32e4f
JB		 2870 mwl8k_cmd_set_mac_addr(hw, vif->addr);
2871 memcpy(mwl8k_vif->mac_addr, vif->addr, ETH_ALEN);
a66098da 2872
a66098da
LB		 2873 /* Set Initial sequence number to zero */
2874 mwl8k_vif->seqno = 0;
2875
1ed32e4f 2876 priv->vif = vif;
a66098da
LB		 2877 priv->current_channel = NULL;
2878
2879 return 0;
2880}
2881
2882static void mwl8k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 2883 struct ieee80211_vif *vif)
a66098da
LB		 2884{
2885 struct mwl8k_priv *priv = hw->priv;
2886
2887 if (priv->vif == NULL)
2888 return;
2889
55489b6e 2890 mwl8k_cmd_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
32060e1b 2891
a66098da
LB		 2892 priv->vif = NULL;
2893}
2894
ee03a932 2895static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
a66098da 2896{
a66098da
LB		 2897 struct ieee80211_conf *conf = &hw->conf;
2898 struct mwl8k_priv *priv = hw->priv;
ee03a932 2899 int rc;
a66098da 2900
7595d67a 2901 if (conf->flags & IEEE80211_CONF_IDLE) {
55489b6e 2902 mwl8k_cmd_radio_disable(hw);
7595d67a 2903 priv->current_channel = NULL;
ee03a932 2904 return 0;
7595d67a
LB		 2905 }
2906
ee03a932
LB		 2907 rc = mwl8k_fw_lock(hw);
2908 if (rc)
2909 return rc;
a66098da 2910
55489b6e 2911 rc = mwl8k_cmd_radio_enable(hw);
ee03a932
LB		 2912 if (rc)
2913 goto out;
a66098da 2914
ee03a932
LB		 2915 rc = mwl8k_cmd_set_rf_channel(hw, conf->channel);
2916 if (rc)
2917 goto out;
2918
2919 priv->current_channel = conf->channel;
a66098da
LB		 2920
2921 if (conf->power_level > 18)
2922 conf->power_level = 18;
55489b6e 2923 rc = mwl8k_cmd_rf_tx_power(hw, conf->power_level);
ee03a932
LB		 2924 if (rc)
2925 goto out;
a66098da 2926
08b06347
LB		 2927 if (priv->ap_fw) {
2928 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_RX, 0x7);
2929 if (!rc)
2930 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_TX, 0x7);
2931 } else {
2932 rc = mwl8k_cmd_mimo_config(hw, 0x7, 0x7);
2933 }
a66098da 2934
ee03a932
LB		 2935out:
2936 mwl8k_fw_unlock(hw);
a66098da 2937
ee03a932 2938 return rc;
a66098da
LB		 2939}
2940
3a980d0a
LB		 2941static void mwl8k_bss_info_changed(struct ieee80211_hw *hw,
2942 struct ieee80211_vif *vif,
2943 struct ieee80211_bss_conf *info,
2944 u32 changed)
a66098da 2945{
a66098da 2946 struct mwl8k_priv *priv = hw->priv;
3a980d0a
LB		 2947 int rc;
2948
3a980d0a
LB		 2949 if ((changed & BSS_CHANGED_ASSOC) == 0)
2950 return;
a66098da 2951
a66098da
LB		 2952 priv->capture_beacon = false;
2953
3a980d0a 2954 rc = mwl8k_fw_lock(hw);
942457d6 2955 if (rc)
3a980d0a
LB		 2956 return;
2957
7dc6a7a7 2958 if (vif->bss_conf.assoc) {
a66098da 2959 /* Install rates */
55489b6e 2960 rc = mwl8k_cmd_set_rate(hw, vif);
3a980d0a
LB		 2961 if (rc)
2962 goto out;
a66098da
LB		 2963
2964 /* Turn on rate adaptation */
3a980d0a
LB		 2965 rc = mwl8k_cmd_use_fixed_rate(hw, MWL8K_USE_AUTO_RATE,
2966 MWL8K_UCAST_RATE, NULL);
2967 if (rc)
2968 goto out;
a66098da
LB		 2969
2970 /* Set radio preamble */
7dc6a7a7
LB		 2971 rc = mwl8k_set_radio_preamble(hw,
2972 vif->bss_conf.use_short_preamble);
3a980d0a
LB		 2973 if (rc)
2974 goto out;
a66098da
LB		 2975
2976 /* Set slot time */
7dc6a7a7 2977 rc = mwl8k_cmd_set_slot(hw, vif->bss_conf.use_short_slot);
3a980d0a
LB		 2978 if (rc)
2979 goto out;
a66098da 2980
a66098da 2981 /* Set AID */
3a980d0a
LB		 2982 rc = mwl8k_cmd_set_aid(hw, vif);
2983 if (rc)
2984 goto out;
a66098da
LB		 2985
2986 /*
2987 * Finalize the join. Tell rx handler to process
2988 * next beacon from our BSSID.
2989 */
0a11dfc3 2990 memcpy(priv->capture_bssid, vif->bss_conf.bssid, ETH_ALEN);
a66098da 2991 priv->capture_beacon = true;
a66098da
LB		 2992 }
2993
3a980d0a
LB		 2994out:
2995 mwl8k_fw_unlock(hw);
a66098da
LB		 2996}
2997
e81cd2d6
LB		 2998static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
2999 int mc_count, struct dev_addr_list *mclist)
3000{
3001 struct mwl8k_cmd_pkt *cmd;
3002
447ced07
LB		 3003 /*
3004 * Synthesize and return a command packet that programs the
3005 * hardware multicast address filter. At this point we don't
3006 * know whether FIF_ALLMULTI is being requested, but if it is,
3007 * we'll end up throwing this packet away and creating a new
3008 * one in mwl8k_configure_filter().
3009 */
3010 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_count, mclist);
e81cd2d6
LB		 3011
3012 return (unsigned long)cmd;
3013}
3014
a43c49a8
LB		 3015static int
3016mwl8k_configure_filter_sniffer(struct ieee80211_hw *hw,
3017 unsigned int changed_flags,
3018 unsigned int *total_flags)
3019{
3020 struct mwl8k_priv *priv = hw->priv;
3021
3022 /*
3023 * Hardware sniffer mode is mutually exclusive with STA
3024 * operation, so refuse to enable sniffer mode if a STA
3025 * interface is active.
3026 */
3027 if (priv->vif != NULL) {
3028 if (net_ratelimit())
3029 printk(KERN_INFO "%s: not enabling sniffer "
3030 "mode because STA interface is active\n",
3031 wiphy_name(hw->wiphy));
3032 return 0;
3033 }
3034
3035 if (!priv->sniffer_enabled) {
55489b6e 3036 if (mwl8k_cmd_enable_sniffer(hw, 1))
a43c49a8
LB		 3037 return 0;
3038 priv->sniffer_enabled = true;
3039 }
3040
3041 *total_flags &= FIF_PROMISC_IN_BSS | FIF_ALLMULTI |
3042 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL |
3043 FIF_OTHER_BSS;
3044
3045 return 1;
3046}
3047
e6935ea1
LB		 3048static void mwl8k_configure_filter(struct ieee80211_hw *hw,
3049 unsigned int changed_flags,
3050 unsigned int *total_flags,
3051 u64 multicast)
3052{
3053 struct mwl8k_priv *priv = hw->priv;
a43c49a8
LB		 3054 struct mwl8k_cmd_pkt *cmd = (void *)(unsigned long)multicast;
3055
c0adae2c
LB		 3056 /*
3057 * AP firmware doesn't allow fine-grained control over
3058 * the receive filter.
3059 */
3060 if (priv->ap_fw) {
3061 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
3062 kfree(cmd);
3063 return;
3064 }
3065
a43c49a8
LB		 3066 /*
3067 * Enable hardware sniffer mode if FIF_CONTROL or
3068 * FIF_OTHER_BSS is requested.
3069 */
3070 if (*total_flags & (FIF_CONTROL | FIF_OTHER_BSS) &&
3071 mwl8k_configure_filter_sniffer(hw, changed_flags, total_flags)) {
3072 kfree(cmd);
3073 return;
3074 }
a66098da 3075
e6935ea1 3076 /* Clear unsupported feature flags */
447ced07 3077 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
a66098da 3078
e6935ea1
LB		 3079 if (mwl8k_fw_lock(hw))
3080 return;
a66098da 3081
a43c49a8 3082 if (priv->sniffer_enabled) {
55489b6e 3083 mwl8k_cmd_enable_sniffer(hw, 0);
a43c49a8
LB		 3084 priv->sniffer_enabled = false;
3085 }
3086
e6935ea1 3087 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
77165d88
LB		 3088 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
3089 /*
3090 * Disable the BSS filter.
3091 */
e6935ea1 3092 mwl8k_cmd_set_pre_scan(hw);
77165d88 3093 } else {
0a11dfc3 3094 const u8 *bssid;
a94cc97e 3095
77165d88
LB		 3096 /*
3097 * Enable the BSS filter.
3098 *
3099 * If there is an active STA interface, use that
3100 * interface's BSSID, otherwise use a dummy one
3101 * (where the OUI part needs to be nonzero for
3102 * the BSSID to be accepted by POST_SCAN).
3103 */
3104 bssid = "\x01\x00\x00\x00\x00\x00";
a94cc97e 3105 if (priv->vif != NULL)
0a11dfc3 3106 bssid = priv->vif->bss_conf.bssid;
a94cc97e 3107
e6935ea1 3108 mwl8k_cmd_set_post_scan(hw, bssid);
a66098da
LB		 3109 }
3110 }
3111
447ced07
LB		 3112 /*
3113 * If FIF_ALLMULTI is being requested, throw away the command
3114 * packet that ->prepare_multicast() built and replace it with
3115 * a command packet that enables reception of all multicast
3116 * packets.
3117 */
3118 if (*total_flags & FIF_ALLMULTI) {
3119 kfree(cmd);
3120 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, 0, NULL);
3121 }
3122
3123 if (cmd != NULL) {
3124 mwl8k_post_cmd(hw, cmd);
3125 kfree(cmd);
e6935ea1 3126 }
a66098da 3127
e6935ea1 3128 mwl8k_fw_unlock(hw);
a66098da
LB		 3129}
3130
a66098da
LB		 3131static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
3132{
55489b6e 3133 return mwl8k_cmd_set_rts_threshold(hw, MWL8K_CMD_SET, value);
a66098da
LB		 3134}
3135
bbfd9128
LB		 3136struct mwl8k_sta_notify_item
3137{
3138 struct list_head list;
3139 struct ieee80211_vif *vif;
3140 enum sta_notify_cmd cmd;
3141 u8 addr[ETH_ALEN];
3142};
3143
3144static void mwl8k_sta_notify_worker(struct work_struct *work)
3145{
3146 struct mwl8k_priv *priv =
3147 container_of(work, struct mwl8k_priv, sta_notify_worker);
a680400e 3148 struct ieee80211_hw *hw = priv->hw;
bbfd9128
LB		 3149
3150 spin_lock_bh(&priv->sta_notify_list_lock);
3151 while (!list_empty(&priv->sta_notify_list)) {
3152 struct mwl8k_sta_notify_item *s;
bbfd9128
LB		 3153
3154 s = list_entry(priv->sta_notify_list.next,
3155 struct mwl8k_sta_notify_item, list);
3156 list_del(&s->list);
3157
3158 spin_unlock_bh(&priv->sta_notify_list_lock);
3159
a680400e
LB		 3160 if (s->cmd == STA_NOTIFY_ADD) {
3161 int rc;
3162
3163 rc = mwl8k_cmd_update_stadb_add(hw, s->vif, s->addr);
3164 if (rc >= 0) {
3165 struct ieee80211_sta *sta;
3166
3167 rcu_read_lock();
3168 sta = ieee80211_find_sta(s->vif, s->addr);
3169 if (sta != NULL)
3170 MWL8K_STA(sta)->peer_id = rc;
3171 rcu_read_unlock();
3172 }
3173 } else {
3174 mwl8k_cmd_update_stadb_del(hw, s->vif, s->addr);
3175 }
bbfd9128
LB		 3176
3177 kfree(s);
3178
3179 spin_lock_bh(&priv->sta_notify_list_lock);
3180 }
3181 spin_unlock_bh(&priv->sta_notify_list_lock);
3182}
3183
3184static void
3185mwl8k_sta_notify(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3186 enum sta_notify_cmd cmd, struct ieee80211_sta *sta)
3187{
3188 struct mwl8k_priv *priv = hw->priv;
3189 struct mwl8k_sta_notify_item *s;
3190
3191 if (cmd != STA_NOTIFY_ADD && cmd != STA_NOTIFY_REMOVE)
3192 return;
3193
3194 s = kmalloc(sizeof(*s), GFP_ATOMIC);
3195 if (s != NULL) {
3196 s->vif = vif;
3197 s->cmd = cmd;
3198 memcpy(s->addr, sta->addr, ETH_ALEN);
3199
3200 spin_lock(&priv->sta_notify_list_lock);
3201 list_add_tail(&s->list, &priv->sta_notify_list);
3202 spin_unlock(&priv->sta_notify_list_lock);
3203
3204 ieee80211_queue_work(hw, &priv->sta_notify_worker);
3205 }
3206}
3207
a66098da
LB		 3208static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue,
3209 const struct ieee80211_tx_queue_params *params)
3210{
3e4f542c 3211 struct mwl8k_priv *priv = hw->priv;
a66098da 3212 int rc;
a66098da 3213
3e4f542c
LB		 3214 rc = mwl8k_fw_lock(hw);
3215 if (!rc) {
3216 if (!priv->wmm_enabled)
55489b6e 3217 rc = mwl8k_cmd_set_wmm_mode(hw, 1);
a66098da 3218
3e4f542c 3219 if (!rc)
55489b6e
LB		 3220 rc = mwl8k_cmd_set_edca_params(hw, queue,
3221 params->cw_min,
3222 params->cw_max,
3223 params->aifs,
3224 params->txop);
3e4f542c
LB		 3225
3226 mwl8k_fw_unlock(hw);
a66098da 3227 }
3e4f542c 3228
a66098da
LB		 3229 return rc;
3230}
3231
3232static int mwl8k_get_tx_stats(struct ieee80211_hw *hw,
3233 struct ieee80211_tx_queue_stats *stats)
3234{
3235 struct mwl8k_priv *priv = hw->priv;
3236 struct mwl8k_tx_queue *txq;
3237 int index;
3238
3239 spin_lock_bh(&priv->tx_lock);
3240 for (index = 0; index < MWL8K_TX_QUEUES; index++) {
3241 txq = priv->txq + index;
45eb400d 3242 memcpy(&stats[index], &txq->stats,
a66098da
LB		 3243 sizeof(struct ieee80211_tx_queue_stats));
3244 }
3245 spin_unlock_bh(&priv->tx_lock);
a66098da 3246
954ef509 3247 return 0;
a66098da
LB		 3248}
3249
3250static int mwl8k_get_stats(struct ieee80211_hw *hw,
3251 struct ieee80211_low_level_stats *stats)
3252{
55489b6e 3253 return mwl8k_cmd_get_stat(hw, stats);
a66098da
LB		 3254}
3255
3256static const struct ieee80211_ops mwl8k_ops = {
3257 .tx = mwl8k_tx,
3258 .start = mwl8k_start,
3259 .stop = mwl8k_stop,
3260 .add_interface = mwl8k_add_interface,
3261 .remove_interface = mwl8k_remove_interface,
3262 .config = mwl8k_config,
a66098da 3263 .bss_info_changed = mwl8k_bss_info_changed,
3ac64bee 3264 .prepare_multicast = mwl8k_prepare_multicast,
a66098da
LB		 3265 .configure_filter = mwl8k_configure_filter,
3266 .set_rts_threshold = mwl8k_set_rts_threshold,
bbfd9128 3267 .sta_notify = mwl8k_sta_notify,
a66098da
LB		 3268 .conf_tx = mwl8k_conf_tx,
3269 .get_tx_stats = mwl8k_get_tx_stats,
3270 .get_stats = mwl8k_get_stats,
3271};
3272
3273static void mwl8k_tx_reclaim_handler(unsigned long data)
3274{
3275 int i;
3276 struct ieee80211_hw *hw = (struct ieee80211_hw *) data;
3277 struct mwl8k_priv *priv = hw->priv;
3278
3279 spin_lock_bh(&priv->tx_lock);
3280 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3281 mwl8k_txq_reclaim(hw, i, 0);
3282
88de754a 3283 if (priv->tx_wait != NULL && !priv->pending_tx_pkts) {
ce9e2e1b
LB		 3284 complete(priv->tx_wait);
3285 priv->tx_wait = NULL;
a66098da
LB		 3286 }
3287 spin_unlock_bh(&priv->tx_lock);
3288}
3289
3290static void mwl8k_finalize_join_worker(struct work_struct *work)
3291{
3292 struct mwl8k_priv *priv =
3293 container_of(work, struct mwl8k_priv, finalize_join_worker);
3294 struct sk_buff *skb = priv->beacon_skb;
a66098da 3295
7dc6a7a7
LB		 3296 mwl8k_cmd_finalize_join(priv->hw, skb->data, skb->len,
3297 priv->vif->bss_conf.dtim_period);
a66098da
LB		 3298 dev_kfree_skb(skb);
3299
3300 priv->beacon_skb = NULL;
3301}
3302
bcb628d5
JL		 3303enum {
3304 MWL8687 = 0,
3305 MWL8366,
6f6d1e9a
LB		 3306};
3307
bcb628d5 3308static struct mwl8k_device_info mwl8k_info_tbl[] __devinitdata = {
49eb691c 3309 [MWL8687] = {
bcb628d5
JL		 3310 .part_name = "88w8687",
3311 .helper_image = "mwl8k/helper_8687.fw",
3312 .fw_image = "mwl8k/fmimage_8687.fw",
bcb628d5 3313 },
49eb691c 3314 [MWL8366] = {
bcb628d5
JL		 3315 .part_name = "88w8366",
3316 .helper_image = "mwl8k/helper_8366.fw",
3317 .fw_image = "mwl8k/fmimage_8366.fw",
89a91f4f 3318 .ap_rxd_ops = &rxd_8366_ap_ops,
bcb628d5 3319 },
45a390dd
LB		 3320};
3321
3322static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = {
bcb628d5
JL		 3323 { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = MWL8687, },
3324 { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = MWL8687, },
3325 { PCI_VDEVICE(MARVELL, 0x2a40), .driver_data = MWL8366, },
3326 { },
45a390dd
LB		 3327};
3328MODULE_DEVICE_TABLE(pci, mwl8k_pci_id_table);
3329
a66098da
LB		 3330static int __devinit mwl8k_probe(struct pci_dev *pdev,
3331 const struct pci_device_id *id)
3332{
2aa7b01f 3333 static int printed_version = 0;
a66098da
LB		 3334 struct ieee80211_hw *hw;
3335 struct mwl8k_priv *priv;
a66098da
LB		 3336 int rc;
3337 int i;
2aa7b01f
LB		 3338
3339 if (!printed_version) {
3340 printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
3341 printed_version = 1;
3342 }
a66098da 3343
be695fc4 3344
a66098da
LB		 3345 rc = pci_enable_device(pdev);
3346 if (rc) {
3347 printk(KERN_ERR "%s: Cannot enable new PCI device\n",
3348 MWL8K_NAME);
3349 return rc;
3350 }
3351
3352 rc = pci_request_regions(pdev, MWL8K_NAME);
3353 if (rc) {
3354 printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
3355 MWL8K_NAME);
3db95e50 3356 goto err_disable_device;
a66098da
LB		 3357 }
3358
3359 pci_set_master(pdev);
3360
be695fc4 3361
a66098da
LB		 3362 hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
3363 if (hw == NULL) {
3364 printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
3365 rc = -ENOMEM;
3366 goto err_free_reg;
3367 }
3368
be695fc4
LB		 3369 SET_IEEE80211_DEV(hw, &pdev->dev);
3370 pci_set_drvdata(pdev, hw);
3371
a66098da
LB		 3372 priv = hw->priv;
3373 priv->hw = hw;
3374 priv->pdev = pdev;
bcb628d5 3375 priv->device_info = &mwl8k_info_tbl[id->driver_data];
a66098da 3376
a66098da 3377
5b9482dd
LB		 3378 priv->sram = pci_iomap(pdev, 0, 0x10000);
3379 if (priv->sram == NULL) {
3380 printk(KERN_ERR "%s: Cannot map device SRAM\n",
c2c357ce 3381 wiphy_name(hw->wiphy));
a66098da
LB		 3382 goto err_iounmap;
3383 }
3384
5b9482dd
LB		 3385 /*
3386 * If BAR0 is a 32 bit BAR, the register BAR will be BAR1.
3387 * If BAR0 is a 64 bit BAR, the register BAR will be BAR2.
3388 */
3389 priv->regs = pci_iomap(pdev, 1, 0x10000);
3390 if (priv->regs == NULL) {
3391 priv->regs = pci_iomap(pdev, 2, 0x10000);
3392 if (priv->regs == NULL) {
3393 printk(KERN_ERR "%s: Cannot map device registers\n",
3394 wiphy_name(hw->wiphy));
3395 goto err_iounmap;
3396 }
3397 }
3398
be695fc4
LB		 3399
3400 /* Reset firmware and hardware */
3401 mwl8k_hw_reset(priv);
3402
3403 /* Ask userland hotplug daemon for the device firmware */
3404 rc = mwl8k_request_firmware(priv);
3405 if (rc) {
3406 printk(KERN_ERR "%s: Firmware files not found\n",
3407 wiphy_name(hw->wiphy));
3408 goto err_stop_firmware;
3409 }
3410
3411 /* Load firmware into hardware */
3412 rc = mwl8k_load_firmware(hw);
3413 if (rc) {
3414 printk(KERN_ERR "%s: Cannot start firmware\n",
3415 wiphy_name(hw->wiphy));
3416 goto err_stop_firmware;
3417 }
3418
3419 /* Reclaim memory once firmware is successfully loaded */
3420 mwl8k_release_firmware(priv);
3421
3422
91942230 3423 if (priv->ap_fw) {
89a91f4f 3424 priv->rxd_ops = priv->device_info->ap_rxd_ops;
91942230
LB		 3425 if (priv->rxd_ops == NULL) {
3426 printk(KERN_ERR "%s: Driver does not have AP "
3427 "firmware image support for this hardware\n",
3428 wiphy_name(hw->wiphy));
3429 goto err_stop_firmware;
3430 }
3431 } else {
89a91f4f 3432 priv->rxd_ops = &rxd_sta_ops;
91942230 3433 }
be695fc4
LB		 3434
3435 priv->sniffer_enabled = false;
3436 priv->wmm_enabled = false;
3437 priv->pending_tx_pkts = 0;
3438
3439
a66098da
LB		 3440 memcpy(priv->channels, mwl8k_channels, sizeof(mwl8k_channels));
3441 priv->band.band = IEEE80211_BAND_2GHZ;
3442 priv->band.channels = priv->channels;
3443 priv->band.n_channels = ARRAY_SIZE(mwl8k_channels);
3444 priv->band.bitrates = priv->rates;
3445 priv->band.n_bitrates = ARRAY_SIZE(mwl8k_rates);
3446 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
3447
3448 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(mwl8k_rates));
3449 memcpy(priv->rates, mwl8k_rates, sizeof(mwl8k_rates));
3450
3451 /*
3452 * Extra headroom is the size of the required DMA header
3453 * minus the size of the smallest 802.11 frame (CTS frame).
3454 */
3455 hw->extra_tx_headroom =
3456 sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
3457
3458 hw->channel_change_time = 10;
3459
3460 hw->queues = MWL8K_TX_QUEUES;
3461
a66098da 3462 /* Set rssi and noise values to dBm */
ce9e2e1b 3463 hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM;
a66098da 3464 hw->vif_data_size = sizeof(struct mwl8k_vif);
a680400e 3465 hw->sta_data_size = sizeof(struct mwl8k_sta);
a66098da
LB		 3466 priv->vif = NULL;
3467
3468 /* Set default radio state and preamble */
c46563b7 3469 priv->radio_on = 0;
68ce3884 3470 priv->radio_short_preamble = 0;
a66098da 3471
bbfd9128
LB		 3472 /* Station database handling */
3473 INIT_WORK(&priv->sta_notify_worker, mwl8k_sta_notify_worker);
3474 spin_lock_init(&priv->sta_notify_list_lock);
3475 INIT_LIST_HEAD(&priv->sta_notify_list);
3476
a66098da
LB		 3477 /* Finalize join worker */
3478 INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
3479
3480 /* TX reclaim tasklet */
3481 tasklet_init(&priv->tx_reclaim_task,
3482 mwl8k_tx_reclaim_handler, (unsigned long)hw);
3483 tasklet_disable(&priv->tx_reclaim_task);
3484
a66098da
LB		 3485 /* Power management cookie */
3486 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
3487 if (priv->cookie == NULL)
be695fc4 3488 goto err_stop_firmware;
a66098da
LB		 3489
3490 rc = mwl8k_rxq_init(hw, 0);
3491 if (rc)
be695fc4 3492 goto err_free_cookie;
a66098da
LB		 3493 rxq_refill(hw, 0, INT_MAX);
3494
618952a7
LB		 3495 mutex_init(&priv->fw_mutex);
3496 priv->fw_mutex_owner = NULL;
3497 priv->fw_mutex_depth = 0;
618952a7
LB		 3498 priv->hostcmd_wait = NULL;
3499
a66098da
LB		 3500 spin_lock_init(&priv->tx_lock);
3501
88de754a
LB		 3502 priv->tx_wait = NULL;
3503
a66098da
LB		 3504 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
3505 rc = mwl8k_txq_init(hw, i);
3506 if (rc)
3507 goto err_free_queues;
3508 }
3509
3510 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
c23b5a69 3511 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3512 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
3513 iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
3514
a0607fd3 3515 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
a66098da
LB		 3516 IRQF_SHARED, MWL8K_NAME, hw);
3517 if (rc) {
3518 printk(KERN_ERR "%s: failed to register IRQ handler\n",
c2c357ce 3519 wiphy_name(hw->wiphy));
a66098da
LB		 3520 goto err_free_queues;
3521 }
3522
a66098da
LB		 3523 /*
3524 * Temporarily enable interrupts. Initial firmware host
3525 * commands use interrupts and avoids polling. Disable
3526 * interrupts when done.
3527 */
c23b5a69 3528 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3529
3530 /* Get config data, mac addrs etc */
42fba21d
LB		 3531 if (priv->ap_fw) {
3532 rc = mwl8k_cmd_get_hw_spec_ap(hw);
3533 if (!rc)
3534 rc = mwl8k_cmd_set_hw_spec(hw);
3535 } else {
3536 rc = mwl8k_cmd_get_hw_spec_sta(hw);
89a91f4f
LB		 3537
3538 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
42fba21d 3539 }
a66098da 3540 if (rc) {
c2c357ce
LB		 3541 printk(KERN_ERR "%s: Cannot initialise firmware\n",
3542 wiphy_name(hw->wiphy));
be695fc4 3543 goto err_free_irq;
a66098da
LB		 3544 }
3545
3546 /* Turn radio off */
55489b6e 3547 rc = mwl8k_cmd_radio_disable(hw);
a66098da 3548 if (rc) {
c2c357ce 3549 printk(KERN_ERR "%s: Cannot disable\n", wiphy_name(hw->wiphy));
be695fc4 3550 goto err_free_irq;
a66098da
LB		 3551 }
3552
32060e1b 3553 /* Clear MAC address */
55489b6e 3554 rc = mwl8k_cmd_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
32060e1b
LB		 3555 if (rc) {
3556 printk(KERN_ERR "%s: Cannot clear MAC address\n",
3557 wiphy_name(hw->wiphy));
be695fc4 3558 goto err_free_irq;
32060e1b
LB		 3559 }
3560
a66098da 3561 /* Disable interrupts */
a66098da 3562 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3563 free_irq(priv->pdev->irq, hw);
3564
3565 rc = ieee80211_register_hw(hw);
3566 if (rc) {
c2c357ce
LB		 3567 printk(KERN_ERR "%s: Cannot register device\n",
3568 wiphy_name(hw->wiphy));
153458ff 3569 goto err_free_queues;
a66098da
LB		 3570 }
3571
eae74e65 3572 printk(KERN_INFO "%s: %s v%d, %pM, %s firmware %u.%u.%u.%u\n",
a74b295e 3573 wiphy_name(hw->wiphy), priv->device_info->part_name,
45a390dd 3574 priv->hw_rev, hw->wiphy->perm_addr,
eae74e65 3575 priv->ap_fw ? "AP" : "STA",
2aa7b01f
LB		 3576 (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff,
3577 (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff);
a66098da
LB		 3578
3579 return 0;
3580
a66098da 3581err_free_irq:
a66098da 3582 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3583 free_irq(priv->pdev->irq, hw);
3584
3585err_free_queues:
3586 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3587 mwl8k_txq_deinit(hw, i);
3588 mwl8k_rxq_deinit(hw, 0);
3589
be695fc4 3590err_free_cookie:
a66098da
LB		 3591 if (priv->cookie != NULL)
3592 pci_free_consistent(priv->pdev, 4,
3593 priv->cookie, priv->cookie_dma);
3594
be695fc4
LB		 3595err_stop_firmware:
3596 mwl8k_hw_reset(priv);
3597 mwl8k_release_firmware(priv);
3598
3599err_iounmap:
a66098da
LB		 3600 if (priv->regs != NULL)
3601 pci_iounmap(pdev, priv->regs);
3602
5b9482dd
LB		 3603 if (priv->sram != NULL)
3604 pci_iounmap(pdev, priv->sram);
3605
a66098da
LB		 3606 pci_set_drvdata(pdev, NULL);
3607 ieee80211_free_hw(hw);
3608
3609err_free_reg:
3610 pci_release_regions(pdev);
3db95e50
LB		 3611
3612err_disable_device:
a66098da
LB		 3613 pci_disable_device(pdev);
3614
3615 return rc;
3616}
3617
230f7af0 3618static void __devexit mwl8k_shutdown(struct pci_dev *pdev)
a66098da
LB		 3619{
3620 printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__);
3621}
3622
230f7af0 3623static void __devexit mwl8k_remove(struct pci_dev *pdev)
a66098da
LB		 3624{
3625 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
3626 struct mwl8k_priv *priv;
3627 int i;
3628
3629 if (hw == NULL)
3630 return;
3631 priv = hw->priv;
3632
3633 ieee80211_stop_queues(hw);
3634
60aa569f
LB		 3635 ieee80211_unregister_hw(hw);
3636
a66098da
LB		 3637 /* Remove tx reclaim tasklet */
3638 tasklet_kill(&priv->tx_reclaim_task);
3639
a66098da
LB		 3640 /* Stop hardware */
3641 mwl8k_hw_reset(priv);
3642
3643 /* Return all skbs to mac80211 */
3644 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3645 mwl8k_txq_reclaim(hw, i, 1);
3646
a66098da
LB		 3647 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3648 mwl8k_txq_deinit(hw, i);
3649
3650 mwl8k_rxq_deinit(hw, 0);
3651
c2c357ce 3652 pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma);
a66098da
LB		 3653
3654 pci_iounmap(pdev, priv->regs);
5b9482dd 3655 pci_iounmap(pdev, priv->sram);
a66098da
LB		 3656 pci_set_drvdata(pdev, NULL);
3657 ieee80211_free_hw(hw);
3658 pci_release_regions(pdev);
3659 pci_disable_device(pdev);
3660}
3661
3662static struct pci_driver mwl8k_driver = {
3663 .name = MWL8K_NAME,
45a390dd 3664 .id_table = mwl8k_pci_id_table,
a66098da
LB		 3665 .probe = mwl8k_probe,
3666 .remove = __devexit_p(mwl8k_remove),
3667 .shutdown = __devexit_p(mwl8k_shutdown),
3668};
3669
3670static int __init mwl8k_init(void)
3671{
3672 return pci_register_driver(&mwl8k_driver);
3673}
3674
3675static void __exit mwl8k_exit(void)
3676{
3677 pci_unregister_driver(&mwl8k_driver);
3678}
3679
3680module_init(mwl8k_init);
3681module_exit(mwl8k_exit);
c2c357ce
LB		 3682
3683MODULE_DESCRIPTION(MWL8K_DESC);
3684MODULE_VERSION(MWL8K_VERSION);
3685MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
3686MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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