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mwl8k: honor peer rate set
[deliverable/linux.git] / drivers / net / wireless / mwl8k.c
CommitLineData
a66098da 1/*
ce9e2e1b
LB		 2 * drivers/net/wireless/mwl8k.c
3 * Driver for Marvell TOPDOG 802.11 Wireless cards
a66098da 4 *
a145d575 5 * Copyright (C) 2008-2009 Marvell Semiconductor Inc.
a66098da
LB		 6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
3d76e82c 15#include <linux/sched.h>
a66098da
LB		 16#include <linux/spinlock.h>
17#include <linux/list.h>
18#include <linux/pci.h>
19#include <linux/delay.h>
20#include <linux/completion.h>
21#include <linux/etherdevice.h>
22#include <net/mac80211.h>
23#include <linux/moduleparam.h>
24#include <linux/firmware.h>
25#include <linux/workqueue.h>
26
27#define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
28#define MWL8K_NAME KBUILD_MODNAME
6976b665 29#define MWL8K_VERSION "0.11"
a66098da 30
a66098da
LB		 31/* Register definitions */
32#define MWL8K_HIU_GEN_PTR 0x00000c10
ce9e2e1b
LB		 33#define MWL8K_MODE_STA 0x0000005a
34#define MWL8K_MODE_AP 0x000000a5
a66098da 35#define MWL8K_HIU_INT_CODE 0x00000c14
ce9e2e1b
LB		 36#define MWL8K_FWSTA_READY 0xf0f1f2f4
37#define MWL8K_FWAP_READY 0xf1f2f4a5
38#define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
a66098da
LB		 39#define MWL8K_HIU_SCRATCH 0x00000c40
40
41/* Host->device communications */
42#define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
43#define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
44#define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
45#define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
46#define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
ce9e2e1b
LB		 47#define MWL8K_H2A_INT_DUMMY (1 << 20)
48#define MWL8K_H2A_INT_RESET (1 << 15)
49#define MWL8K_H2A_INT_DOORBELL (1 << 1)
50#define MWL8K_H2A_INT_PPA_READY (1 << 0)
a66098da
LB		 51
52/* Device->host communications */
53#define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
54#define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
55#define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
56#define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
57#define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
ce9e2e1b
LB		 58#define MWL8K_A2H_INT_DUMMY (1 << 20)
59#define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
60#define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
61#define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
62#define MWL8K_A2H_INT_RADIO_ON (1 << 6)
63#define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
64#define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
65#define MWL8K_A2H_INT_OPC_DONE (1 << 2)
66#define MWL8K_A2H_INT_RX_READY (1 << 1)
67#define MWL8K_A2H_INT_TX_DONE (1 << 0)
a66098da
LB		 68
69#define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
70 MWL8K_A2H_INT_CHNL_SWITCHED | \
71 MWL8K_A2H_INT_QUEUE_EMPTY | \
72 MWL8K_A2H_INT_RADAR_DETECT | \
73 MWL8K_A2H_INT_RADIO_ON | \
74 MWL8K_A2H_INT_RADIO_OFF | \
75 MWL8K_A2H_INT_MAC_EVENT | \
76 MWL8K_A2H_INT_OPC_DONE | \
77 MWL8K_A2H_INT_RX_READY | \
78 MWL8K_A2H_INT_TX_DONE)
79
a66098da
LB		 80#define MWL8K_RX_QUEUES 1
81#define MWL8K_TX_QUEUES 4
82
54bc3a0d
LB		 83struct rxd_ops {
84 int rxd_size;
85 void (*rxd_init)(void *rxd, dma_addr_t next_dma_addr);
86 void (*rxd_refill)(void *rxd, dma_addr_t addr, int len);
20f09c3d
LB		 87 int (*rxd_process)(void *rxd, struct ieee80211_rx_status *status,
88 __le16 *qos);
54bc3a0d
LB		 89};
90
45a390dd 91struct mwl8k_device_info {
a74b295e
LB		 92 char *part_name;
93 char *helper_image;
94 char *fw_image;
89a91f4f 95 struct rxd_ops *ap_rxd_ops;
45a390dd
LB		 96};
97
a66098da 98struct mwl8k_rx_queue {
45eb400d 99 int rxd_count;
a66098da
LB		 100
101 /* hw receives here */
45eb400d 102 int head;
a66098da
LB		 103
104 /* refill descs here */
45eb400d 105 int tail;
a66098da 106
54bc3a0d 107 void *rxd;
45eb400d 108 dma_addr_t rxd_dma;
788838eb
LB		 109 struct {
110 struct sk_buff *skb;
111 DECLARE_PCI_UNMAP_ADDR(dma)
112 } *buf;
a66098da
LB		 113};
114
a66098da
LB		 115struct mwl8k_tx_queue {
116 /* hw transmits here */
45eb400d 117 int head;
a66098da
LB		 118
119 /* sw appends here */
45eb400d 120 int tail;
a66098da 121
45eb400d
LB		 122 struct ieee80211_tx_queue_stats stats;
123 struct mwl8k_tx_desc *txd;
124 dma_addr_t txd_dma;
125 struct sk_buff **skb;
a66098da
LB		 126};
127
a66098da 128struct mwl8k_priv {
a66098da 129 struct ieee80211_hw *hw;
a66098da 130 struct pci_dev *pdev;
a66098da 131
45a390dd
LB		 132 struct mwl8k_device_info *device_info;
133
be695fc4
LB		 134 void __iomem *sram;
135 void __iomem *regs;
136
137 /* firmware */
22be40d9
LB		 138 struct firmware *fw_helper;
139 struct firmware *fw_ucode;
a66098da 140
be695fc4
LB		 141 /* hardware/firmware parameters */
142 bool ap_fw;
143 struct rxd_ops *rxd_ops;
144
618952a7
LB		 145 /* firmware access */
146 struct mutex fw_mutex;
147 struct task_struct *fw_mutex_owner;
148 int fw_mutex_depth;
618952a7
LB		 149 struct completion *hostcmd_wait;
150
a66098da
LB		 151 /* lock held over TX and TX reap */
152 spinlock_t tx_lock;
a66098da 153
88de754a
LB		 154 /* TX quiesce completion, protected by fw_mutex and tx_lock */
155 struct completion *tx_wait;
156
a66098da 157 struct ieee80211_vif *vif;
a66098da
LB		 158
159 struct ieee80211_channel *current_channel;
160
161 /* power management status cookie from firmware */
162 u32 *cookie;
163 dma_addr_t cookie_dma;
164
165 u16 num_mcaddrs;
a66098da 166 u8 hw_rev;
2aa7b01f 167 u32 fw_rev;
a66098da
LB		 168
169 /*
170 * Running count of TX packets in flight, to avoid
171 * iterating over the transmit rings each time.
172 */
173 int pending_tx_pkts;
174
175 struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
176 struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES];
177
178 /* PHY parameters */
179 struct ieee80211_supported_band band;
180 struct ieee80211_channel channels[14];
140eb5e2 181 struct ieee80211_rate rates[14];
a66098da 182
c46563b7 183 bool radio_on;
68ce3884 184 bool radio_short_preamble;
a43c49a8 185 bool sniffer_enabled;
0439b1f5 186 bool wmm_enabled;
a66098da 187
bbfd9128
LB		 188 struct work_struct sta_notify_worker;
189 spinlock_t sta_notify_list_lock;
190 struct list_head sta_notify_list;
191
a66098da
LB		 192 /* XXX need to convert this to handle multiple interfaces */
193 bool capture_beacon;
d89173f2 194 u8 capture_bssid[ETH_ALEN];
a66098da
LB		 195 struct sk_buff *beacon_skb;
196
197 /*
198 * This FJ worker has to be global as it is scheduled from the
199 * RX handler. At this point we don't know which interface it
200 * belongs to until the list of bssids waiting to complete join
201 * is checked.
202 */
203 struct work_struct finalize_join_worker;
204
205 /* Tasklet to reclaim TX descriptors and buffers after tx */
206 struct tasklet_struct tx_reclaim_task;
a66098da
LB		 207};
208
209/* Per interface specific private data */
210struct mwl8k_vif {
7dc6a7a7
LB		 211 /* Local MAC address. */
212 u8 mac_addr[ETH_ALEN];
a66098da 213
a66098da 214 /* Non AMPDU sequence number assigned by driver */
a680400e 215 u16 seqno;
a66098da 216};
a94cc97e 217#define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
a66098da 218
a680400e
LB		 219struct mwl8k_sta {
220 /* Index into station database. Returned by UPDATE_STADB. */
221 u8 peer_id;
222};
223#define MWL8K_STA(_sta) ((struct mwl8k_sta *)&((_sta)->drv_priv))
224
a66098da
LB		 225static const struct ieee80211_channel mwl8k_channels[] = {
226 { .center_freq = 2412, .hw_value = 1, },
227 { .center_freq = 2417, .hw_value = 2, },
228 { .center_freq = 2422, .hw_value = 3, },
229 { .center_freq = 2427, .hw_value = 4, },
230 { .center_freq = 2432, .hw_value = 5, },
231 { .center_freq = 2437, .hw_value = 6, },
232 { .center_freq = 2442, .hw_value = 7, },
233 { .center_freq = 2447, .hw_value = 8, },
234 { .center_freq = 2452, .hw_value = 9, },
235 { .center_freq = 2457, .hw_value = 10, },
236 { .center_freq = 2462, .hw_value = 11, },
647ca6b0
LB		 237 { .center_freq = 2467, .hw_value = 12, },
238 { .center_freq = 2472, .hw_value = 13, },
239 { .center_freq = 2484, .hw_value = 14, },
a66098da
LB		 240};
241
242static const struct ieee80211_rate mwl8k_rates[] = {
243 { .bitrate = 10, .hw_value = 2, },
244 { .bitrate = 20, .hw_value = 4, },
245 { .bitrate = 55, .hw_value = 11, },
5dfd3e2c
LB		 246 { .bitrate = 110, .hw_value = 22, },
247 { .bitrate = 220, .hw_value = 44, },
a66098da
LB		 248 { .bitrate = 60, .hw_value = 12, },
249 { .bitrate = 90, .hw_value = 18, },
a66098da
LB		 250 { .bitrate = 120, .hw_value = 24, },
251 { .bitrate = 180, .hw_value = 36, },
252 { .bitrate = 240, .hw_value = 48, },
253 { .bitrate = 360, .hw_value = 72, },
254 { .bitrate = 480, .hw_value = 96, },
255 { .bitrate = 540, .hw_value = 108, },
140eb5e2
LB		 256 { .bitrate = 720, .hw_value = 144, },
257};
258
a66098da
LB		 259/* Set or get info from Firmware */
260#define MWL8K_CMD_SET 0x0001
261#define MWL8K_CMD_GET 0x0000
262
263/* Firmware command codes */
264#define MWL8K_CMD_CODE_DNLD 0x0001
265#define MWL8K_CMD_GET_HW_SPEC 0x0003
42fba21d 266#define MWL8K_CMD_SET_HW_SPEC 0x0004
a66098da
LB		 267#define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
268#define MWL8K_CMD_GET_STAT 0x0014
ff45fc60
LB		 269#define MWL8K_CMD_RADIO_CONTROL 0x001c
270#define MWL8K_CMD_RF_TX_POWER 0x001e
08b06347 271#define MWL8K_CMD_RF_ANTENNA 0x0020
a66098da
LB		 272#define MWL8K_CMD_SET_PRE_SCAN 0x0107
273#define MWL8K_CMD_SET_POST_SCAN 0x0108
ff45fc60
LB		 274#define MWL8K_CMD_SET_RF_CHANNEL 0x010a
275#define MWL8K_CMD_SET_AID 0x010d
276#define MWL8K_CMD_SET_RATE 0x0110
277#define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
278#define MWL8K_CMD_RTS_THRESHOLD 0x0113
a66098da 279#define MWL8K_CMD_SET_SLOT 0x0114
ff45fc60
LB		 280#define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
281#define MWL8K_CMD_SET_WMM_MODE 0x0123
a66098da 282#define MWL8K_CMD_MIMO_CONFIG 0x0125
ff45fc60 283#define MWL8K_CMD_USE_FIXED_RATE 0x0126
a66098da 284#define MWL8K_CMD_ENABLE_SNIFFER 0x0150
32060e1b 285#define MWL8K_CMD_SET_MAC_ADDR 0x0202
a66098da 286#define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
ff45fc60 287#define MWL8K_CMD_UPDATE_STADB 0x1123
a66098da
LB		 288
289static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize)
290{
291#define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
292 snprintf(buf, bufsize, "%s", #x);\
293 return buf;\
294 } while (0)
ce9e2e1b 295 switch (cmd & ~0x8000) {
a66098da
LB		 296 MWL8K_CMDNAME(CODE_DNLD);
297 MWL8K_CMDNAME(GET_HW_SPEC);
42fba21d 298 MWL8K_CMDNAME(SET_HW_SPEC);
a66098da
LB		 299 MWL8K_CMDNAME(MAC_MULTICAST_ADR);
300 MWL8K_CMDNAME(GET_STAT);
301 MWL8K_CMDNAME(RADIO_CONTROL);
302 MWL8K_CMDNAME(RF_TX_POWER);
08b06347 303 MWL8K_CMDNAME(RF_ANTENNA);
a66098da
LB		 304 MWL8K_CMDNAME(SET_PRE_SCAN);
305 MWL8K_CMDNAME(SET_POST_SCAN);
306 MWL8K_CMDNAME(SET_RF_CHANNEL);
ff45fc60
LB		 307 MWL8K_CMDNAME(SET_AID);
308 MWL8K_CMDNAME(SET_RATE);
309 MWL8K_CMDNAME(SET_FINALIZE_JOIN);
310 MWL8K_CMDNAME(RTS_THRESHOLD);
a66098da 311 MWL8K_CMDNAME(SET_SLOT);
ff45fc60
LB		 312 MWL8K_CMDNAME(SET_EDCA_PARAMS);
313 MWL8K_CMDNAME(SET_WMM_MODE);
a66098da 314 MWL8K_CMDNAME(MIMO_CONFIG);
ff45fc60 315 MWL8K_CMDNAME(USE_FIXED_RATE);
a66098da 316 MWL8K_CMDNAME(ENABLE_SNIFFER);
32060e1b 317 MWL8K_CMDNAME(SET_MAC_ADDR);
a66098da 318 MWL8K_CMDNAME(SET_RATEADAPT_MODE);
ff45fc60 319 MWL8K_CMDNAME(UPDATE_STADB);
a66098da
LB		 320 default:
321 snprintf(buf, bufsize, "0x%x", cmd);
322 }
323#undef MWL8K_CMDNAME
324
325 return buf;
326}
327
328/* Hardware and firmware reset */
329static void mwl8k_hw_reset(struct mwl8k_priv *priv)
330{
331 iowrite32(MWL8K_H2A_INT_RESET,
332 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
333 iowrite32(MWL8K_H2A_INT_RESET,
334 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
335 msleep(20);
336}
337
338/* Release fw image */
339static void mwl8k_release_fw(struct firmware **fw)
340{
341 if (*fw == NULL)
342 return;
343 release_firmware(*fw);
344 *fw = NULL;
345}
346
347static void mwl8k_release_firmware(struct mwl8k_priv *priv)
348{
22be40d9
LB		 349 mwl8k_release_fw(&priv->fw_ucode);
350 mwl8k_release_fw(&priv->fw_helper);
a66098da
LB		 351}
352
353/* Request fw image */
354static int mwl8k_request_fw(struct mwl8k_priv *priv,
c2c357ce 355 const char *fname, struct firmware **fw)
a66098da
LB		 356{
357 /* release current image */
358 if (*fw != NULL)
359 mwl8k_release_fw(fw);
360
361 return request_firmware((const struct firmware **)fw,
c2c357ce 362 fname, &priv->pdev->dev);
a66098da
LB		 363}
364
45a390dd 365static int mwl8k_request_firmware(struct mwl8k_priv *priv)
a66098da 366{
a74b295e 367 struct mwl8k_device_info *di = priv->device_info;
a66098da
LB		 368 int rc;
369
a74b295e 370 if (di->helper_image != NULL) {
22be40d9 371 rc = mwl8k_request_fw(priv, di->helper_image, &priv->fw_helper);
a74b295e
LB		 372 if (rc) {
373 printk(KERN_ERR "%s: Error requesting helper "
374 "firmware file %s\n", pci_name(priv->pdev),
375 di->helper_image);
376 return rc;
377 }
a66098da
LB		 378 }
379
22be40d9 380 rc = mwl8k_request_fw(priv, di->fw_image, &priv->fw_ucode);
a66098da 381 if (rc) {
c2c357ce 382 printk(KERN_ERR "%s: Error requesting firmware file %s\n",
a74b295e 383 pci_name(priv->pdev), di->fw_image);
22be40d9 384 mwl8k_release_fw(&priv->fw_helper);
a66098da
LB		 385 return rc;
386 }
387
388 return 0;
389}
390
7e75b942
BH		 391MODULE_FIRMWARE("mwl8k/helper_8687.fw");
392MODULE_FIRMWARE("mwl8k/fmimage_8687.fw");
393
a66098da
LB		 394struct mwl8k_cmd_pkt {
395 __le16 code;
396 __le16 length;
397 __le16 seq_num;
398 __le16 result;
399 char payload[0];
400} __attribute__((packed));
401
402/*
403 * Firmware loading.
404 */
405static int
406mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
407{
408 void __iomem *regs = priv->regs;
409 dma_addr_t dma_addr;
a66098da
LB		 410 int loops;
411
412 dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
413 if (pci_dma_mapping_error(priv->pdev, dma_addr))
414 return -ENOMEM;
415
416 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
417 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
418 iowrite32(MWL8K_H2A_INT_DOORBELL,
419 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
420 iowrite32(MWL8K_H2A_INT_DUMMY,
421 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
422
a66098da
LB		 423 loops = 1000;
424 do {
425 u32 int_code;
426
427 int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
428 if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
429 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
a66098da
LB		 430 break;
431 }
432
3d76e82c 433 cond_resched();
a66098da
LB		 434 udelay(1);
435 } while (--loops);
436
437 pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
438
d4b70570 439 return loops ? 0 : -ETIMEDOUT;
a66098da
LB		 440}
441
442static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
443 const u8 *data, size_t length)
444{
445 struct mwl8k_cmd_pkt *cmd;
446 int done;
447 int rc = 0;
448
449 cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
450 if (cmd == NULL)
451 return -ENOMEM;
452
453 cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
454 cmd->seq_num = 0;
455 cmd->result = 0;
456
457 done = 0;
458 while (length) {
459 int block_size = length > 256 ? 256 : length;
460
461 memcpy(cmd->payload, data + done, block_size);
462 cmd->length = cpu_to_le16(block_size);
463
464 rc = mwl8k_send_fw_load_cmd(priv, cmd,
465 sizeof(*cmd) + block_size);
466 if (rc)
467 break;
468
469 done += block_size;
470 length -= block_size;
471 }
472
473 if (!rc) {
474 cmd->length = 0;
475 rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
476 }
477
478 kfree(cmd);
479
480 return rc;
481}
482
483static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
484 const u8 *data, size_t length)
485{
486 unsigned char *buffer;
487 int may_continue, rc = 0;
488 u32 done, prev_block_size;
489
490 buffer = kmalloc(1024, GFP_KERNEL);
491 if (buffer == NULL)
492 return -ENOMEM;
493
494 done = 0;
495 prev_block_size = 0;
496 may_continue = 1000;
497 while (may_continue > 0) {
498 u32 block_size;
499
500 block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
501 if (block_size & 1) {
502 block_size &= ~1;
503 may_continue--;
504 } else {
505 done += prev_block_size;
506 length -= prev_block_size;
507 }
508
509 if (block_size > 1024 || block_size > length) {
510 rc = -EOVERFLOW;
511 break;
512 }
513
514 if (length == 0) {
515 rc = 0;
516 break;
517 }
518
519 if (block_size == 0) {
520 rc = -EPROTO;
521 may_continue--;
522 udelay(1);
523 continue;
524 }
525
526 prev_block_size = block_size;
527 memcpy(buffer, data + done, block_size);
528
529 rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
530 if (rc)
531 break;
532 }
533
534 if (!rc && length != 0)
535 rc = -EREMOTEIO;
536
537 kfree(buffer);
538
539 return rc;
540}
541
c2c357ce 542static int mwl8k_load_firmware(struct ieee80211_hw *hw)
a66098da 543{
c2c357ce 544 struct mwl8k_priv *priv = hw->priv;
22be40d9 545 struct firmware *fw = priv->fw_ucode;
c2c357ce
LB		 546 int rc;
547 int loops;
548
549 if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) {
22be40d9 550 struct firmware *helper = priv->fw_helper;
a66098da 551
c2c357ce
LB		 552 if (helper == NULL) {
553 printk(KERN_ERR "%s: helper image needed but none "
554 "given\n", pci_name(priv->pdev));
555 return -EINVAL;
556 }
a66098da 557
c2c357ce 558 rc = mwl8k_load_fw_image(priv, helper->data, helper->size);
a66098da
LB		 559 if (rc) {
560 printk(KERN_ERR "%s: unable to load firmware "
c2c357ce 561 "helper image\n", pci_name(priv->pdev));
a66098da
LB		 562 return rc;
563 }
89b872e2 564 msleep(5);
a66098da 565
c2c357ce 566 rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
a66098da 567 } else {
c2c357ce 568 rc = mwl8k_load_fw_image(priv, fw->data, fw->size);
a66098da
LB		 569 }
570
571 if (rc) {
c2c357ce
LB		 572 printk(KERN_ERR "%s: unable to load firmware image\n",
573 pci_name(priv->pdev));
a66098da
LB		 574 return rc;
575 }
576
89a91f4f 577 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
a66098da 578
89b872e2 579 loops = 500000;
a66098da 580 do {
eae74e65
LB		 581 u32 ready_code;
582
583 ready_code = ioread32(priv->regs + MWL8K_HIU_INT_CODE);
584 if (ready_code == MWL8K_FWAP_READY) {
585 priv->ap_fw = 1;
586 break;
587 } else if (ready_code == MWL8K_FWSTA_READY) {
588 priv->ap_fw = 0;
a66098da 589 break;
eae74e65
LB		 590 }
591
592 cond_resched();
a66098da
LB		 593 udelay(1);
594 } while (--loops);
595
596 return loops ? 0 : -ETIMEDOUT;
597}
598
599
a66098da
LB		 600/* DMA header used by firmware and hardware. */
601struct mwl8k_dma_data {
602 __le16 fwlen;
603 struct ieee80211_hdr wh;
20f09c3d 604 char data[0];
a66098da
LB		 605} __attribute__((packed));
606
607/* Routines to add/remove DMA header from skb. */
20f09c3d 608static inline void mwl8k_remove_dma_header(struct sk_buff *skb, __le16 qos)
a66098da 609{
20f09c3d
LB		 610 struct mwl8k_dma_data *tr;
611 int hdrlen;
612
613 tr = (struct mwl8k_dma_data *)skb->data;
614 hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
615
616 if (hdrlen != sizeof(tr->wh)) {
617 if (ieee80211_is_data_qos(tr->wh.frame_control)) {
618 memmove(tr->data - hdrlen, &tr->wh, hdrlen - 2);
619 *((__le16 *)(tr->data - 2)) = qos;
620 } else {
621 memmove(tr->data - hdrlen, &tr->wh, hdrlen);
622 }
a66098da 623 }
20f09c3d
LB		 624
625 if (hdrlen != sizeof(*tr))
626 skb_pull(skb, sizeof(*tr) - hdrlen);
a66098da
LB		 627}
628
76266b2a 629static inline void mwl8k_add_dma_header(struct sk_buff *skb)
a66098da
LB		 630{
631 struct ieee80211_hdr *wh;
ca009301 632 int hdrlen;
a66098da
LB		 633 struct mwl8k_dma_data *tr;
634
ca009301
LB		 635 /*
636 * Add a firmware DMA header; the firmware requires that we
637 * present a 2-byte payload length followed by a 4-address
638 * header (without QoS field), followed (optionally) by any
639 * WEP/ExtIV header (but only filled in for CCMP).
640 */
a66098da 641 wh = (struct ieee80211_hdr *)skb->data;
ca009301 642
a66098da 643 hdrlen = ieee80211_hdrlen(wh->frame_control);
ca009301
LB		 644 if (hdrlen != sizeof(*tr))
645 skb_push(skb, sizeof(*tr) - hdrlen);
a66098da 646
ca009301
LB		 647 if (ieee80211_is_data_qos(wh->frame_control))
648 hdrlen -= 2;
a66098da
LB		 649
650 tr = (struct mwl8k_dma_data *)skb->data;
651 if (wh != &tr->wh)
652 memmove(&tr->wh, wh, hdrlen);
ca009301
LB		 653 if (hdrlen != sizeof(tr->wh))
654 memset(((void *)&tr->wh) + hdrlen, 0, sizeof(tr->wh) - hdrlen);
a66098da
LB		 655
656 /*
657 * Firmware length is the length of the fully formed "802.11
658 * payload". That is, everything except for the 802.11 header.
659 * This includes all crypto material including the MIC.
660 */
ca009301 661 tr->fwlen = cpu_to_le16(skb->len - sizeof(*tr));
a66098da
LB		 662}
663
664
665/*
89a91f4f 666 * Packet reception for 88w8366 AP firmware.
6f6d1e9a 667 */
89a91f4f 668struct mwl8k_rxd_8366_ap {
6f6d1e9a
LB		 669 __le16 pkt_len;
670 __u8 sq2;
671 __u8 rate;
672 __le32 pkt_phys_addr;
673 __le32 next_rxd_phys_addr;
674 __le16 qos_control;
675 __le16 htsig2;
676 __le32 hw_rssi_info;
677 __le32 hw_noise_floor_info;
678 __u8 noise_floor;
679 __u8 pad0[3];
680 __u8 rssi;
681 __u8 rx_status;
682 __u8 channel;
683 __u8 rx_ctrl;
684} __attribute__((packed));
685
89a91f4f
LB		 686#define MWL8K_8366_AP_RATE_INFO_MCS_FORMAT 0x80
687#define MWL8K_8366_AP_RATE_INFO_40MHZ 0x40
688#define MWL8K_8366_AP_RATE_INFO_RATEID(x) ((x) & 0x3f)
8e9f33f0 689
89a91f4f 690#define MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST 0x80
6f6d1e9a 691
89a91f4f 692static void mwl8k_rxd_8366_ap_init(void *_rxd, dma_addr_t next_dma_addr)
6f6d1e9a 693{
89a91f4f 694 struct mwl8k_rxd_8366_ap *rxd = _rxd;
6f6d1e9a
LB		 695
696 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
89a91f4f 697 rxd->rx_ctrl = MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST;
6f6d1e9a
LB		 698}
699
89a91f4f 700static void mwl8k_rxd_8366_ap_refill(void *_rxd, dma_addr_t addr, int len)
6f6d1e9a 701{
89a91f4f 702 struct mwl8k_rxd_8366_ap *rxd = _rxd;
6f6d1e9a
LB		 703
704 rxd->pkt_len = cpu_to_le16(len);
705 rxd->pkt_phys_addr = cpu_to_le32(addr);
706 wmb();
707 rxd->rx_ctrl = 0;
708}
709
710static int
89a91f4f
LB		 711mwl8k_rxd_8366_ap_process(void *_rxd, struct ieee80211_rx_status *status,
712 __le16 *qos)
6f6d1e9a 713{
89a91f4f 714 struct mwl8k_rxd_8366_ap *rxd = _rxd;
6f6d1e9a 715
89a91f4f 716 if (!(rxd->rx_ctrl & MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST))
6f6d1e9a
LB		 717 return -1;
718 rmb();
719
720 memset(status, 0, sizeof(*status));
721
722 status->signal = -rxd->rssi;
723 status->noise = -rxd->noise_floor;
724
89a91f4f 725 if (rxd->rate & MWL8K_8366_AP_RATE_INFO_MCS_FORMAT) {
6f6d1e9a 726 status->flag |= RX_FLAG_HT;
89a91f4f 727 if (rxd->rate & MWL8K_8366_AP_RATE_INFO_40MHZ)
8e9f33f0 728 status->flag |= RX_FLAG_40MHZ;
89a91f4f 729 status->rate_idx = MWL8K_8366_AP_RATE_INFO_RATEID(rxd->rate);
6f6d1e9a
LB		 730 } else {
731 int i;
732
733 for (i = 0; i < ARRAY_SIZE(mwl8k_rates); i++) {
734 if (mwl8k_rates[i].hw_value == rxd->rate) {
735 status->rate_idx = i;
736 break;
737 }
738 }
739 }
740
741 status->band = IEEE80211_BAND_2GHZ;
742 status->freq = ieee80211_channel_to_frequency(rxd->channel);
743
20f09c3d
LB		 744 *qos = rxd->qos_control;
745
6f6d1e9a
LB		 746 return le16_to_cpu(rxd->pkt_len);
747}
748
89a91f4f
LB		 749static struct rxd_ops rxd_8366_ap_ops = {
750 .rxd_size = sizeof(struct mwl8k_rxd_8366_ap),
751 .rxd_init = mwl8k_rxd_8366_ap_init,
752 .rxd_refill = mwl8k_rxd_8366_ap_refill,
753 .rxd_process = mwl8k_rxd_8366_ap_process,
6f6d1e9a
LB		 754};
755
756/*
89a91f4f 757 * Packet reception for STA firmware.
a66098da 758 */
89a91f4f 759struct mwl8k_rxd_sta {
a66098da
LB		 760 __le16 pkt_len;
761 __u8 link_quality;
762 __u8 noise_level;
763 __le32 pkt_phys_addr;
45eb400d 764 __le32 next_rxd_phys_addr;
a66098da
LB		 765 __le16 qos_control;
766 __le16 rate_info;
767 __le32 pad0[4];
768 __u8 rssi;
769 __u8 channel;
770 __le16 pad1;
771 __u8 rx_ctrl;
772 __u8 rx_status;
773 __u8 pad2[2];
774} __attribute__((packed));
775
89a91f4f
LB		 776#define MWL8K_STA_RATE_INFO_SHORTPRE 0x8000
777#define MWL8K_STA_RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3)
778#define MWL8K_STA_RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f)
779#define MWL8K_STA_RATE_INFO_40MHZ 0x0004
780#define MWL8K_STA_RATE_INFO_SHORTGI 0x0002
781#define MWL8K_STA_RATE_INFO_MCS_FORMAT 0x0001
54bc3a0d 782
89a91f4f 783#define MWL8K_STA_RX_CTRL_OWNED_BY_HOST 0x02
54bc3a0d 784
89a91f4f 785static void mwl8k_rxd_sta_init(void *_rxd, dma_addr_t next_dma_addr)
54bc3a0d 786{
89a91f4f 787 struct mwl8k_rxd_sta *rxd = _rxd;
54bc3a0d
LB		 788
789 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
89a91f4f 790 rxd->rx_ctrl = MWL8K_STA_RX_CTRL_OWNED_BY_HOST;
54bc3a0d
LB		 791}
792
89a91f4f 793static void mwl8k_rxd_sta_refill(void *_rxd, dma_addr_t addr, int len)
54bc3a0d 794{
89a91f4f 795 struct mwl8k_rxd_sta *rxd = _rxd;
54bc3a0d
LB		 796
797 rxd->pkt_len = cpu_to_le16(len);
798 rxd->pkt_phys_addr = cpu_to_le32(addr);
799 wmb();
800 rxd->rx_ctrl = 0;
801}
802
803static int
89a91f4f 804mwl8k_rxd_sta_process(void *_rxd, struct ieee80211_rx_status *status,
20f09c3d 805 __le16 *qos)
54bc3a0d 806{
89a91f4f 807 struct mwl8k_rxd_sta *rxd = _rxd;
54bc3a0d
LB		 808 u16 rate_info;
809
89a91f4f 810 if (!(rxd->rx_ctrl & MWL8K_STA_RX_CTRL_OWNED_BY_HOST))
54bc3a0d
LB		 811 return -1;
812 rmb();
813
814 rate_info = le16_to_cpu(rxd->rate_info);
815
816 memset(status, 0, sizeof(*status));
817
818 status->signal = -rxd->rssi;
819 status->noise = -rxd->noise_level;
89a91f4f
LB		 820 status->antenna = MWL8K_STA_RATE_INFO_ANTSELECT(rate_info);
821 status->rate_idx = MWL8K_STA_RATE_INFO_RATEID(rate_info);
54bc3a0d 822
89a91f4f 823 if (rate_info & MWL8K_STA_RATE_INFO_SHORTPRE)
54bc3a0d 824 status->flag |= RX_FLAG_SHORTPRE;
89a91f4f 825 if (rate_info & MWL8K_STA_RATE_INFO_40MHZ)
54bc3a0d 826 status->flag |= RX_FLAG_40MHZ;
89a91f4f 827 if (rate_info & MWL8K_STA_RATE_INFO_SHORTGI)
54bc3a0d 828 status->flag |= RX_FLAG_SHORT_GI;
89a91f4f 829 if (rate_info & MWL8K_STA_RATE_INFO_MCS_FORMAT)
54bc3a0d
LB		 830 status->flag |= RX_FLAG_HT;
831
832 status->band = IEEE80211_BAND_2GHZ;
833 status->freq = ieee80211_channel_to_frequency(rxd->channel);
834
20f09c3d
LB		 835 *qos = rxd->qos_control;
836
54bc3a0d
LB		 837 return le16_to_cpu(rxd->pkt_len);
838}
839
89a91f4f
LB		 840static struct rxd_ops rxd_sta_ops = {
841 .rxd_size = sizeof(struct mwl8k_rxd_sta),
842 .rxd_init = mwl8k_rxd_sta_init,
843 .rxd_refill = mwl8k_rxd_sta_refill,
844 .rxd_process = mwl8k_rxd_sta_process,
54bc3a0d
LB		 845};
846
847
a66098da
LB		 848#define MWL8K_RX_DESCS 256
849#define MWL8K_RX_MAXSZ 3800
850
851static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
852{
853 struct mwl8k_priv *priv = hw->priv;
854 struct mwl8k_rx_queue *rxq = priv->rxq + index;
855 int size;
856 int i;
857
45eb400d
LB		 858 rxq->rxd_count = 0;
859 rxq->head = 0;
860 rxq->tail = 0;
a66098da 861
54bc3a0d 862 size = MWL8K_RX_DESCS * priv->rxd_ops->rxd_size;
a66098da 863
45eb400d
LB		 864 rxq->rxd = pci_alloc_consistent(priv->pdev, size, &rxq->rxd_dma);
865 if (rxq->rxd == NULL) {
a66098da 866 printk(KERN_ERR "%s: failed to alloc RX descriptors\n",
c2c357ce 867 wiphy_name(hw->wiphy));
a66098da
LB		 868 return -ENOMEM;
869 }
45eb400d 870 memset(rxq->rxd, 0, size);
a66098da 871
788838eb
LB		 872 rxq->buf = kmalloc(MWL8K_RX_DESCS * sizeof(*rxq->buf), GFP_KERNEL);
873 if (rxq->buf == NULL) {
a66098da 874 printk(KERN_ERR "%s: failed to alloc RX skbuff list\n",
c2c357ce 875 wiphy_name(hw->wiphy));
45eb400d 876 pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma);
a66098da
LB		 877 return -ENOMEM;
878 }
788838eb 879 memset(rxq->buf, 0, MWL8K_RX_DESCS * sizeof(*rxq->buf));
a66098da
LB		 880
881 for (i = 0; i < MWL8K_RX_DESCS; i++) {
54bc3a0d
LB		 882 int desc_size;
883 void *rxd;
a66098da 884 int nexti;
54bc3a0d
LB		 885 dma_addr_t next_dma_addr;
886
887 desc_size = priv->rxd_ops->rxd_size;
888 rxd = rxq->rxd + (i * priv->rxd_ops->rxd_size);
a66098da 889
54bc3a0d
LB		 890 nexti = i + 1;
891 if (nexti == MWL8K_RX_DESCS)
892 nexti = 0;
893 next_dma_addr = rxq->rxd_dma + (nexti * desc_size);
a66098da 894
54bc3a0d 895 priv->rxd_ops->rxd_init(rxd, next_dma_addr);
a66098da
LB		 896 }
897
898 return 0;
899}
900
901static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
902{
903 struct mwl8k_priv *priv = hw->priv;
904 struct mwl8k_rx_queue *rxq = priv->rxq + index;
905 int refilled;
906
907 refilled = 0;
45eb400d 908 while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) {
a66098da 909 struct sk_buff *skb;
788838eb 910 dma_addr_t addr;
a66098da 911 int rx;
54bc3a0d 912 void *rxd;
a66098da
LB		 913
914 skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
915 if (skb == NULL)
916 break;
917
788838eb
LB		 918 addr = pci_map_single(priv->pdev, skb->data,
919 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE);
a66098da 920
54bc3a0d
LB		 921 rxq->rxd_count++;
922 rx = rxq->tail++;
923 if (rxq->tail == MWL8K_RX_DESCS)
924 rxq->tail = 0;
788838eb
LB		 925 rxq->buf[rx].skb = skb;
926 pci_unmap_addr_set(&rxq->buf[rx], dma, addr);
54bc3a0d
LB		 927
928 rxd = rxq->rxd + (rx * priv->rxd_ops->rxd_size);
929 priv->rxd_ops->rxd_refill(rxd, addr, MWL8K_RX_MAXSZ);
a66098da
LB		 930
931 refilled++;
932 }
933
934 return refilled;
935}
936
937/* Must be called only when the card's reception is completely halted */
938static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
939{
940 struct mwl8k_priv *priv = hw->priv;
941 struct mwl8k_rx_queue *rxq = priv->rxq + index;
942 int i;
943
944 for (i = 0; i < MWL8K_RX_DESCS; i++) {
788838eb
LB		 945 if (rxq->buf[i].skb != NULL) {
946 pci_unmap_single(priv->pdev,
947 pci_unmap_addr(&rxq->buf[i], dma),
948 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
949 pci_unmap_addr_set(&rxq->buf[i], dma, 0);
950
951 kfree_skb(rxq->buf[i].skb);
952 rxq->buf[i].skb = NULL;
a66098da
LB		 953 }
954 }
955
788838eb
LB		 956 kfree(rxq->buf);
957 rxq->buf = NULL;
a66098da
LB		 958
959 pci_free_consistent(priv->pdev,
54bc3a0d 960 MWL8K_RX_DESCS * priv->rxd_ops->rxd_size,
45eb400d
LB		 961 rxq->rxd, rxq->rxd_dma);
962 rxq->rxd = NULL;
a66098da
LB		 963}
964
965
966/*
967 * Scan a list of BSSIDs to process for finalize join.
968 * Allows for extension to process multiple BSSIDs.
969 */
970static inline int
971mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
972{
973 return priv->capture_beacon &&
974 ieee80211_is_beacon(wh->frame_control) &&
975 !compare_ether_addr(wh->addr3, priv->capture_bssid);
976}
977
3779752d
LB		 978static inline void mwl8k_save_beacon(struct ieee80211_hw *hw,
979 struct sk_buff *skb)
a66098da 980{
3779752d
LB		 981 struct mwl8k_priv *priv = hw->priv;
982
a66098da 983 priv->capture_beacon = false;
d89173f2 984 memset(priv->capture_bssid, 0, ETH_ALEN);
a66098da
LB		 985
986 /*
987 * Use GFP_ATOMIC as rxq_process is called from
988 * the primary interrupt handler, memory allocation call
989 * must not sleep.
990 */
991 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
992 if (priv->beacon_skb != NULL)
3779752d 993 ieee80211_queue_work(hw, &priv->finalize_join_worker);
a66098da
LB		 994}
995
996static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
997{
998 struct mwl8k_priv *priv = hw->priv;
999 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1000 int processed;
1001
1002 processed = 0;
45eb400d 1003 while (rxq->rxd_count && limit--) {
a66098da 1004 struct sk_buff *skb;
54bc3a0d
LB		 1005 void *rxd;
1006 int pkt_len;
a66098da 1007 struct ieee80211_rx_status status;
20f09c3d 1008 __le16 qos;
a66098da 1009
788838eb 1010 skb = rxq->buf[rxq->head].skb;
d25f9f13
LB		 1011 if (skb == NULL)
1012 break;
54bc3a0d
LB		 1013
1014 rxd = rxq->rxd + (rxq->head * priv->rxd_ops->rxd_size);
1015
20f09c3d 1016 pkt_len = priv->rxd_ops->rxd_process(rxd, &status, &qos);
54bc3a0d
LB		 1017 if (pkt_len < 0)
1018 break;
1019
788838eb
LB		 1020 rxq->buf[rxq->head].skb = NULL;
1021
1022 pci_unmap_single(priv->pdev,
1023 pci_unmap_addr(&rxq->buf[rxq->head], dma),
1024 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
1025 pci_unmap_addr_set(&rxq->buf[rxq->head], dma, 0);
a66098da 1026
54bc3a0d
LB		 1027 rxq->head++;
1028 if (rxq->head == MWL8K_RX_DESCS)
1029 rxq->head = 0;
1030
45eb400d 1031 rxq->rxd_count--;
a66098da 1032
54bc3a0d 1033 skb_put(skb, pkt_len);
20f09c3d 1034 mwl8k_remove_dma_header(skb, qos);
a66098da 1035
a66098da 1036 /*
c2c357ce
LB		 1037 * Check for a pending join operation. Save a
1038 * copy of the beacon and schedule a tasklet to
1039 * send a FINALIZE_JOIN command to the firmware.
a66098da 1040 */
54bc3a0d 1041 if (mwl8k_capture_bssid(priv, (void *)skb->data))
3779752d 1042 mwl8k_save_beacon(hw, skb);
a66098da 1043
f1d58c25
JB		 1044 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
1045 ieee80211_rx_irqsafe(hw, skb);
a66098da
LB		 1046
1047 processed++;
1048 }
1049
1050 return processed;
1051}
1052
1053
1054/*
1055 * Packet transmission.
1056 */
1057
a66098da
LB		 1058#define MWL8K_TXD_STATUS_OK 0x00000001
1059#define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
1060#define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
1061#define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
a66098da 1062#define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
a66098da 1063
e0493a8d
LB		 1064#define MWL8K_QOS_QLEN_UNSPEC 0xff00
1065#define MWL8K_QOS_ACK_POLICY_MASK 0x0060
1066#define MWL8K_QOS_ACK_POLICY_NORMAL 0x0000
1067#define MWL8K_QOS_ACK_POLICY_BLOCKACK 0x0060
1068#define MWL8K_QOS_EOSP 0x0010
1069
a66098da
LB		 1070struct mwl8k_tx_desc {
1071 __le32 status;
1072 __u8 data_rate;
1073 __u8 tx_priority;
1074 __le16 qos_control;
1075 __le32 pkt_phys_addr;
1076 __le16 pkt_len;
d89173f2 1077 __u8 dest_MAC_addr[ETH_ALEN];
45eb400d 1078 __le32 next_txd_phys_addr;
a66098da
LB		 1079 __le32 reserved;
1080 __le16 rate_info;
1081 __u8 peer_id;
1082 __u8 tx_frag_cnt;
1083} __attribute__((packed));
1084
1085#define MWL8K_TX_DESCS 128
1086
1087static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
1088{
1089 struct mwl8k_priv *priv = hw->priv;
1090 struct mwl8k_tx_queue *txq = priv->txq + index;
1091 int size;
1092 int i;
1093
45eb400d
LB		 1094 memset(&txq->stats, 0, sizeof(struct ieee80211_tx_queue_stats));
1095 txq->stats.limit = MWL8K_TX_DESCS;
1096 txq->head = 0;
1097 txq->tail = 0;
a66098da
LB		 1098
1099 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
1100
45eb400d
LB		 1101 txq->txd = pci_alloc_consistent(priv->pdev, size, &txq->txd_dma);
1102 if (txq->txd == NULL) {
a66098da 1103 printk(KERN_ERR "%s: failed to alloc TX descriptors\n",
c2c357ce 1104 wiphy_name(hw->wiphy));
a66098da
LB		 1105 return -ENOMEM;
1106 }
45eb400d 1107 memset(txq->txd, 0, size);
a66098da 1108
45eb400d
LB		 1109 txq->skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->skb), GFP_KERNEL);
1110 if (txq->skb == NULL) {
a66098da 1111 printk(KERN_ERR "%s: failed to alloc TX skbuff list\n",
c2c357ce 1112 wiphy_name(hw->wiphy));
45eb400d 1113 pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma);
a66098da
LB		 1114 return -ENOMEM;
1115 }
45eb400d 1116 memset(txq->skb, 0, MWL8K_TX_DESCS * sizeof(*txq->skb));
a66098da
LB		 1117
1118 for (i = 0; i < MWL8K_TX_DESCS; i++) {
1119 struct mwl8k_tx_desc *tx_desc;
1120 int nexti;
1121
45eb400d 1122 tx_desc = txq->txd + i;
a66098da
LB		 1123 nexti = (i + 1) % MWL8K_TX_DESCS;
1124
1125 tx_desc->status = 0;
45eb400d
LB		 1126 tx_desc->next_txd_phys_addr =
1127 cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc));
a66098da
LB		 1128 }
1129
1130 return 0;
1131}
1132
1133static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
1134{
1135 iowrite32(MWL8K_H2A_INT_PPA_READY,
1136 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1137 iowrite32(MWL8K_H2A_INT_DUMMY,
1138 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1139 ioread32(priv->regs + MWL8K_HIU_INT_CODE);
1140}
1141
7e1112d3 1142static void mwl8k_dump_tx_rings(struct ieee80211_hw *hw)
a66098da 1143{
7e1112d3
LB		 1144 struct mwl8k_priv *priv = hw->priv;
1145 int i;
1146
1147 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
1148 struct mwl8k_tx_queue *txq = priv->txq + i;
1149 int fw_owned = 0;
1150 int drv_owned = 0;
1151 int unused = 0;
1152 int desc;
1153
a66098da 1154 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
7e1112d3
LB		 1155 struct mwl8k_tx_desc *tx_desc = txq->txd + desc;
1156 u32 status;
a66098da 1157
7e1112d3 1158 status = le32_to_cpu(tx_desc->status);
a66098da 1159 if (status & MWL8K_TXD_STATUS_FW_OWNED)
7e1112d3 1160 fw_owned++;
a66098da 1161 else
7e1112d3 1162 drv_owned++;
a66098da
LB		 1163
1164 if (tx_desc->pkt_len == 0)
7e1112d3 1165 unused++;
a66098da 1166 }
a66098da 1167
7e1112d3
LB		 1168 printk(KERN_ERR "%s: txq[%d] len=%d head=%d tail=%d "
1169 "fw_owned=%d drv_owned=%d unused=%d\n",
1170 wiphy_name(hw->wiphy), i,
1171 txq->stats.len, txq->head, txq->tail,
1172 fw_owned, drv_owned, unused);
1173 }
a66098da
LB		 1174}
1175
618952a7 1176/*
88de754a 1177 * Must be called with priv->fw_mutex held and tx queues stopped.
618952a7 1178 */
7e1112d3
LB		 1179#define MWL8K_TX_WAIT_TIMEOUT_MS 1000
1180
950d5b01 1181static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
a66098da 1182{
a66098da 1183 struct mwl8k_priv *priv = hw->priv;
88de754a 1184 DECLARE_COMPLETION_ONSTACK(tx_wait);
7e1112d3
LB		 1185 int retry;
1186 int rc;
a66098da
LB		 1187
1188 might_sleep();
1189
7e1112d3
LB		 1190 /*
1191 * The TX queues are stopped at this point, so this test
1192 * doesn't need to take ->tx_lock.
1193 */
1194 if (!priv->pending_tx_pkts)
1195 return 0;
1196
1197 retry = 0;
1198 rc = 0;
1199
a66098da 1200 spin_lock_bh(&priv->tx_lock);
7e1112d3
LB		 1201 priv->tx_wait = &tx_wait;
1202 while (!rc) {
1203 int oldcount;
1204 unsigned long timeout;
a66098da 1205
7e1112d3 1206 oldcount = priv->pending_tx_pkts;
a66098da 1207
7e1112d3 1208 spin_unlock_bh(&priv->tx_lock);
88de754a 1209 timeout = wait_for_completion_timeout(&tx_wait,
7e1112d3 1210 msecs_to_jiffies(MWL8K_TX_WAIT_TIMEOUT_MS));
a66098da 1211 spin_lock_bh(&priv->tx_lock);
7e1112d3
LB		 1212
1213 if (timeout) {
1214 WARN_ON(priv->pending_tx_pkts);
1215 if (retry) {
1216 printk(KERN_NOTICE "%s: tx rings drained\n",
1217 wiphy_name(hw->wiphy));
1218 }
1219 break;
1220 }
1221
1222 if (priv->pending_tx_pkts < oldcount) {
9a2303b9
LB		 1223 printk(KERN_NOTICE "%s: waiting for tx rings "
1224 "to drain (%d -> %d pkts)\n",
7e1112d3
LB		 1225 wiphy_name(hw->wiphy), oldcount,
1226 priv->pending_tx_pkts);
1227 retry = 1;
1228 continue;
1229 }
1230
a66098da 1231 priv->tx_wait = NULL;
a66098da 1232
7e1112d3
LB		 1233 printk(KERN_ERR "%s: tx rings stuck for %d ms\n",
1234 wiphy_name(hw->wiphy), MWL8K_TX_WAIT_TIMEOUT_MS);
1235 mwl8k_dump_tx_rings(hw);
1236
1237 rc = -ETIMEDOUT;
a66098da 1238 }
7e1112d3 1239 spin_unlock_bh(&priv->tx_lock);
a66098da 1240
7e1112d3 1241 return rc;
a66098da
LB		 1242}
1243
c23b5a69
LB		 1244#define MWL8K_TXD_SUCCESS(status) \
1245 ((status) & (MWL8K_TXD_STATUS_OK | \
1246 MWL8K_TXD_STATUS_OK_RETRY | \
1247 MWL8K_TXD_STATUS_OK_MORE_RETRY))
a66098da
LB		 1248
1249static void mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int force)
1250{
1251 struct mwl8k_priv *priv = hw->priv;
1252 struct mwl8k_tx_queue *txq = priv->txq + index;
1253 int wake = 0;
1254
45eb400d 1255 while (txq->stats.len > 0) {
a66098da 1256 int tx;
a66098da
LB		 1257 struct mwl8k_tx_desc *tx_desc;
1258 unsigned long addr;
ce9e2e1b 1259 int size;
a66098da
LB		 1260 struct sk_buff *skb;
1261 struct ieee80211_tx_info *info;
1262 u32 status;
1263
45eb400d
LB		 1264 tx = txq->head;
1265 tx_desc = txq->txd + tx;
a66098da
LB		 1266
1267 status = le32_to_cpu(tx_desc->status);
1268
1269 if (status & MWL8K_TXD_STATUS_FW_OWNED) {
1270 if (!force)
1271 break;
1272 tx_desc->status &=
1273 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
1274 }
1275
45eb400d
LB		 1276 txq->head = (tx + 1) % MWL8K_TX_DESCS;
1277 BUG_ON(txq->stats.len == 0);
1278 txq->stats.len--;
a66098da
LB		 1279 priv->pending_tx_pkts--;
1280
1281 addr = le32_to_cpu(tx_desc->pkt_phys_addr);
ce9e2e1b 1282 size = le16_to_cpu(tx_desc->pkt_len);
45eb400d
LB		 1283 skb = txq->skb[tx];
1284 txq->skb[tx] = NULL;
a66098da
LB		 1285
1286 BUG_ON(skb == NULL);
1287 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
1288
20f09c3d 1289 mwl8k_remove_dma_header(skb, tx_desc->qos_control);
a66098da
LB		 1290
1291 /* Mark descriptor as unused */
1292 tx_desc->pkt_phys_addr = 0;
1293 tx_desc->pkt_len = 0;
1294
a66098da
LB		 1295 info = IEEE80211_SKB_CB(skb);
1296 ieee80211_tx_info_clear_status(info);
ce9e2e1b 1297 if (MWL8K_TXD_SUCCESS(status))
a66098da 1298 info->flags |= IEEE80211_TX_STAT_ACK;
a66098da
LB		 1299
1300 ieee80211_tx_status_irqsafe(hw, skb);
1301
618952a7 1302 wake = 1;
a66098da
LB		 1303 }
1304
618952a7 1305 if (wake && priv->radio_on && !mutex_is_locked(&priv->fw_mutex))
a66098da
LB		 1306 ieee80211_wake_queue(hw, index);
1307}
1308
1309/* must be called only when the card's transmit is completely halted */
1310static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
1311{
1312 struct mwl8k_priv *priv = hw->priv;
1313 struct mwl8k_tx_queue *txq = priv->txq + index;
1314
1315 mwl8k_txq_reclaim(hw, index, 1);
1316
45eb400d
LB		 1317 kfree(txq->skb);
1318 txq->skb = NULL;
a66098da
LB		 1319
1320 pci_free_consistent(priv->pdev,
1321 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
45eb400d
LB		 1322 txq->txd, txq->txd_dma);
1323 txq->txd = NULL;
a66098da
LB		 1324}
1325
1326static int
1327mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
1328{
1329 struct mwl8k_priv *priv = hw->priv;
1330 struct ieee80211_tx_info *tx_info;
23b33906 1331 struct mwl8k_vif *mwl8k_vif;
a66098da
LB		 1332 struct ieee80211_hdr *wh;
1333 struct mwl8k_tx_queue *txq;
1334 struct mwl8k_tx_desc *tx;
a66098da 1335 dma_addr_t dma;
23b33906
LB		 1336 u32 txstatus;
1337 u8 txdatarate;
1338 u16 qos;
a66098da 1339
23b33906
LB		 1340 wh = (struct ieee80211_hdr *)skb->data;
1341 if (ieee80211_is_data_qos(wh->frame_control))
1342 qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
1343 else
1344 qos = 0;
a66098da 1345
76266b2a 1346 mwl8k_add_dma_header(skb);
23b33906 1347 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
a66098da
LB		 1348
1349 tx_info = IEEE80211_SKB_CB(skb);
1350 mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
a66098da
LB		 1351
1352 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1353 u16 seqno = mwl8k_vif->seqno;
23b33906 1354
a66098da
LB		 1355 wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1356 wh->seq_ctrl |= cpu_to_le16(seqno << 4);
1357 mwl8k_vif->seqno = seqno++ % 4096;
1358 }
1359
23b33906
LB		 1360 /* Setup firmware control bit fields for each frame type. */
1361 txstatus = 0;
1362 txdatarate = 0;
1363 if (ieee80211_is_mgmt(wh->frame_control) ||
1364 ieee80211_is_ctl(wh->frame_control)) {
1365 txdatarate = 0;
e0493a8d 1366 qos |= MWL8K_QOS_QLEN_UNSPEC | MWL8K_QOS_EOSP;
23b33906
LB		 1367 } else if (ieee80211_is_data(wh->frame_control)) {
1368 txdatarate = 1;
1369 if (is_multicast_ether_addr(wh->addr1))
1370 txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
1371
e0493a8d 1372 qos &= ~MWL8K_QOS_ACK_POLICY_MASK;
23b33906 1373 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
e0493a8d 1374 qos |= MWL8K_QOS_ACK_POLICY_BLOCKACK;
23b33906 1375 else
e0493a8d 1376 qos |= MWL8K_QOS_ACK_POLICY_NORMAL;
23b33906 1377 }
a66098da
LB		 1378
1379 dma = pci_map_single(priv->pdev, skb->data,
1380 skb->len, PCI_DMA_TODEVICE);
1381
1382 if (pci_dma_mapping_error(priv->pdev, dma)) {
1383 printk(KERN_DEBUG "%s: failed to dma map skb, "
c2c357ce 1384 "dropping TX frame.\n", wiphy_name(hw->wiphy));
23b33906 1385 dev_kfree_skb(skb);
a66098da
LB		 1386 return NETDEV_TX_OK;
1387 }
1388
23b33906 1389 spin_lock_bh(&priv->tx_lock);
a66098da 1390
23b33906 1391 txq = priv->txq + index;
a66098da 1392
45eb400d
LB		 1393 BUG_ON(txq->skb[txq->tail] != NULL);
1394 txq->skb[txq->tail] = skb;
a66098da 1395
45eb400d 1396 tx = txq->txd + txq->tail;
23b33906
LB		 1397 tx->data_rate = txdatarate;
1398 tx->tx_priority = index;
a66098da 1399 tx->qos_control = cpu_to_le16(qos);
a66098da
LB		 1400 tx->pkt_phys_addr = cpu_to_le32(dma);
1401 tx->pkt_len = cpu_to_le16(skb->len);
23b33906 1402 tx->rate_info = 0;
a680400e
LB		 1403 if (!priv->ap_fw && tx_info->control.sta != NULL)
1404 tx->peer_id = MWL8K_STA(tx_info->control.sta)->peer_id;
1405 else
1406 tx->peer_id = 0;
a66098da 1407 wmb();
23b33906
LB		 1408 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus);
1409
45eb400d
LB		 1410 txq->stats.count++;
1411 txq->stats.len++;
a66098da 1412 priv->pending_tx_pkts++;
a66098da 1413
45eb400d
LB		 1414 txq->tail++;
1415 if (txq->tail == MWL8K_TX_DESCS)
1416 txq->tail = 0;
23b33906 1417
45eb400d 1418 if (txq->head == txq->tail)
a66098da
LB		 1419 ieee80211_stop_queue(hw, index);
1420
23b33906 1421 mwl8k_tx_start(priv);
a66098da
LB		 1422
1423 spin_unlock_bh(&priv->tx_lock);
1424
1425 return NETDEV_TX_OK;
1426}
1427
1428
618952a7
LB		 1429/*
1430 * Firmware access.
1431 *
1432 * We have the following requirements for issuing firmware commands:
1433 * - Some commands require that the packet transmit path is idle when
1434 * the command is issued. (For simplicity, we'll just quiesce the
1435 * transmit path for every command.)
1436 * - There are certain sequences of commands that need to be issued to
1437 * the hardware sequentially, with no other intervening commands.
1438 *
1439 * This leads to an implementation of a "firmware lock" as a mutex that
1440 * can be taken recursively, and which is taken by both the low-level
1441 * command submission function (mwl8k_post_cmd) as well as any users of
1442 * that function that require issuing of an atomic sequence of commands,
1443 * and quiesces the transmit path whenever it's taken.
1444 */
1445static int mwl8k_fw_lock(struct ieee80211_hw *hw)
1446{
1447 struct mwl8k_priv *priv = hw->priv;
1448
1449 if (priv->fw_mutex_owner != current) {
1450 int rc;
1451
1452 mutex_lock(&priv->fw_mutex);
1453 ieee80211_stop_queues(hw);
1454
1455 rc = mwl8k_tx_wait_empty(hw);
1456 if (rc) {
1457 ieee80211_wake_queues(hw);
1458 mutex_unlock(&priv->fw_mutex);
1459
1460 return rc;
1461 }
1462
1463 priv->fw_mutex_owner = current;
1464 }
1465
1466 priv->fw_mutex_depth++;
1467
1468 return 0;
1469}
1470
1471static void mwl8k_fw_unlock(struct ieee80211_hw *hw)
1472{
1473 struct mwl8k_priv *priv = hw->priv;
1474
1475 if (!--priv->fw_mutex_depth) {
1476 ieee80211_wake_queues(hw);
1477 priv->fw_mutex_owner = NULL;
1478 mutex_unlock(&priv->fw_mutex);
1479 }
1480}
1481
1482
a66098da
LB		 1483/*
1484 * Command processing.
1485 */
1486
0c9cc640
LB		 1487/* Timeout firmware commands after 10s */
1488#define MWL8K_CMD_TIMEOUT_MS 10000
a66098da
LB		 1489
1490static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
1491{
1492 DECLARE_COMPLETION_ONSTACK(cmd_wait);
1493 struct mwl8k_priv *priv = hw->priv;
1494 void __iomem *regs = priv->regs;
1495 dma_addr_t dma_addr;
1496 unsigned int dma_size;
1497 int rc;
a66098da
LB		 1498 unsigned long timeout = 0;
1499 u8 buf[32];
1500
c2c357ce 1501 cmd->result = 0xffff;
a66098da
LB		 1502 dma_size = le16_to_cpu(cmd->length);
1503 dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
1504 PCI_DMA_BIDIRECTIONAL);
1505 if (pci_dma_mapping_error(priv->pdev, dma_addr))
1506 return -ENOMEM;
1507
618952a7 1508 rc = mwl8k_fw_lock(hw);
39a1e42e
LB		 1509 if (rc) {
1510 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1511 PCI_DMA_BIDIRECTIONAL);
618952a7 1512 return rc;
39a1e42e 1513 }
a66098da 1514
a66098da
LB		 1515 priv->hostcmd_wait = &cmd_wait;
1516 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
1517 iowrite32(MWL8K_H2A_INT_DOORBELL,
1518 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1519 iowrite32(MWL8K_H2A_INT_DUMMY,
1520 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
a66098da
LB		 1521
1522 timeout = wait_for_completion_timeout(&cmd_wait,
1523 msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
1524
618952a7
LB		 1525 priv->hostcmd_wait = NULL;
1526
1527 mwl8k_fw_unlock(hw);
1528
37055bd4
LB		 1529 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1530 PCI_DMA_BIDIRECTIONAL);
1531
a66098da 1532 if (!timeout) {
a66098da 1533 printk(KERN_ERR "%s: Command %s timeout after %u ms\n",
c2c357ce 1534 wiphy_name(hw->wiphy),
a66098da
LB		 1535 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1536 MWL8K_CMD_TIMEOUT_MS);
1537 rc = -ETIMEDOUT;
1538 } else {
0c9cc640
LB		 1539 int ms;
1540
1541 ms = MWL8K_CMD_TIMEOUT_MS - jiffies_to_msecs(timeout);
1542
ce9e2e1b 1543 rc = cmd->result ? -EINVAL : 0;
a66098da
LB		 1544 if (rc)
1545 printk(KERN_ERR "%s: Command %s error 0x%x\n",
c2c357ce 1546 wiphy_name(hw->wiphy),
a66098da 1547 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
76c962a2 1548 le16_to_cpu(cmd->result));
0c9cc640
LB		 1549 else if (ms > 2000)
1550 printk(KERN_NOTICE "%s: Command %s took %d ms\n",
1551 wiphy_name(hw->wiphy),
1552 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1553 ms);
a66098da
LB		 1554 }
1555
a66098da
LB		 1556 return rc;
1557}
1558
1559/*
04b147b1 1560 * CMD_GET_HW_SPEC (STA version).
a66098da 1561 */
04b147b1 1562struct mwl8k_cmd_get_hw_spec_sta {
a66098da
LB		 1563 struct mwl8k_cmd_pkt header;
1564 __u8 hw_rev;
1565 __u8 host_interface;
1566 __le16 num_mcaddrs;
d89173f2 1567 __u8 perm_addr[ETH_ALEN];
a66098da
LB		 1568 __le16 region_code;
1569 __le32 fw_rev;
1570 __le32 ps_cookie;
1571 __le32 caps;
1572 __u8 mcs_bitmap[16];
1573 __le32 rx_queue_ptr;
1574 __le32 num_tx_queues;
1575 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1576 __le32 caps2;
1577 __le32 num_tx_desc_per_queue;
45eb400d 1578 __le32 total_rxd;
a66098da
LB		 1579} __attribute__((packed));
1580
04b147b1 1581static int mwl8k_cmd_get_hw_spec_sta(struct ieee80211_hw *hw)
a66098da
LB		 1582{
1583 struct mwl8k_priv *priv = hw->priv;
04b147b1 1584 struct mwl8k_cmd_get_hw_spec_sta *cmd;
a66098da
LB		 1585 int rc;
1586 int i;
1587
1588 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1589 if (cmd == NULL)
1590 return -ENOMEM;
1591
1592 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1593 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1594
1595 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1596 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
45eb400d 1597 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
4ff6432e 1598 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
a66098da 1599 for (i = 0; i < MWL8K_TX_QUEUES; i++)
45eb400d 1600 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
4ff6432e 1601 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
45eb400d 1602 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
a66098da
LB		 1603
1604 rc = mwl8k_post_cmd(hw, &cmd->header);
1605
1606 if (!rc) {
1607 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1608 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
4ff6432e 1609 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
a66098da 1610 priv->hw_rev = cmd->hw_rev;
a66098da
LB		 1611 }
1612
1613 kfree(cmd);
1614 return rc;
1615}
1616
42fba21d
LB		 1617/*
1618 * CMD_GET_HW_SPEC (AP version).
1619 */
1620struct mwl8k_cmd_get_hw_spec_ap {
1621 struct mwl8k_cmd_pkt header;
1622 __u8 hw_rev;
1623 __u8 host_interface;
1624 __le16 num_wcb;
1625 __le16 num_mcaddrs;
1626 __u8 perm_addr[ETH_ALEN];
1627 __le16 region_code;
1628 __le16 num_antenna;
1629 __le32 fw_rev;
1630 __le32 wcbbase0;
1631 __le32 rxwrptr;
1632 __le32 rxrdptr;
1633 __le32 ps_cookie;
1634 __le32 wcbbase1;
1635 __le32 wcbbase2;
1636 __le32 wcbbase3;
1637} __attribute__((packed));
1638
1639static int mwl8k_cmd_get_hw_spec_ap(struct ieee80211_hw *hw)
1640{
1641 struct mwl8k_priv *priv = hw->priv;
1642 struct mwl8k_cmd_get_hw_spec_ap *cmd;
1643 int rc;
1644
1645 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1646 if (cmd == NULL)
1647 return -ENOMEM;
1648
1649 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1650 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1651
1652 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1653 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1654
1655 rc = mwl8k_post_cmd(hw, &cmd->header);
1656
1657 if (!rc) {
1658 int off;
1659
1660 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1661 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
1662 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
1663 priv->hw_rev = cmd->hw_rev;
1664
1665 off = le32_to_cpu(cmd->wcbbase0) & 0xffff;
1666 iowrite32(cpu_to_le32(priv->txq[0].txd_dma), priv->sram + off);
1667
1668 off = le32_to_cpu(cmd->rxwrptr) & 0xffff;
1669 iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
1670
1671 off = le32_to_cpu(cmd->rxrdptr) & 0xffff;
1672 iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
1673
1674 off = le32_to_cpu(cmd->wcbbase1) & 0xffff;
1675 iowrite32(cpu_to_le32(priv->txq[1].txd_dma), priv->sram + off);
1676
1677 off = le32_to_cpu(cmd->wcbbase2) & 0xffff;
1678 iowrite32(cpu_to_le32(priv->txq[2].txd_dma), priv->sram + off);
1679
1680 off = le32_to_cpu(cmd->wcbbase3) & 0xffff;
1681 iowrite32(cpu_to_le32(priv->txq[3].txd_dma), priv->sram + off);
1682 }
1683
1684 kfree(cmd);
1685 return rc;
1686}
1687
1688/*
1689 * CMD_SET_HW_SPEC.
1690 */
1691struct mwl8k_cmd_set_hw_spec {
1692 struct mwl8k_cmd_pkt header;
1693 __u8 hw_rev;
1694 __u8 host_interface;
1695 __le16 num_mcaddrs;
1696 __u8 perm_addr[ETH_ALEN];
1697 __le16 region_code;
1698 __le32 fw_rev;
1699 __le32 ps_cookie;
1700 __le32 caps;
1701 __le32 rx_queue_ptr;
1702 __le32 num_tx_queues;
1703 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1704 __le32 flags;
1705 __le32 num_tx_desc_per_queue;
1706 __le32 total_rxd;
1707} __attribute__((packed));
1708
1709#define MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT 0x00000080
1710
1711static int mwl8k_cmd_set_hw_spec(struct ieee80211_hw *hw)
1712{
1713 struct mwl8k_priv *priv = hw->priv;
1714 struct mwl8k_cmd_set_hw_spec *cmd;
1715 int rc;
1716 int i;
1717
1718 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1719 if (cmd == NULL)
1720 return -ENOMEM;
1721
1722 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_HW_SPEC);
1723 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1724
1725 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1726 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
1727 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
1728 for (i = 0; i < MWL8K_TX_QUEUES; i++)
1729 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
1730 cmd->flags = cpu_to_le32(MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT);
1731 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
1732 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
1733
1734 rc = mwl8k_post_cmd(hw, &cmd->header);
1735 kfree(cmd);
1736
1737 return rc;
1738}
1739
a66098da
LB		 1740/*
1741 * CMD_MAC_MULTICAST_ADR.
1742 */
1743struct mwl8k_cmd_mac_multicast_adr {
1744 struct mwl8k_cmd_pkt header;
1745 __le16 action;
1746 __le16 numaddr;
ce9e2e1b 1747 __u8 addr[0][ETH_ALEN];
a66098da
LB		 1748};
1749
d5e30845
LB		 1750#define MWL8K_ENABLE_RX_DIRECTED 0x0001
1751#define MWL8K_ENABLE_RX_MULTICAST 0x0002
1752#define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004
1753#define MWL8K_ENABLE_RX_BROADCAST 0x0008
ce9e2e1b 1754
e81cd2d6 1755static struct mwl8k_cmd_pkt *
447ced07 1756__mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti,
e81cd2d6 1757 int mc_count, struct dev_addr_list *mclist)
a66098da 1758{
e81cd2d6 1759 struct mwl8k_priv *priv = hw->priv;
a66098da 1760 struct mwl8k_cmd_mac_multicast_adr *cmd;
e81cd2d6 1761 int size;
e81cd2d6 1762
447ced07 1763 if (allmulti || mc_count > priv->num_mcaddrs) {
d5e30845
LB		 1764 allmulti = 1;
1765 mc_count = 0;
1766 }
e81cd2d6
LB		 1767
1768 size = sizeof(*cmd) + mc_count * ETH_ALEN;
ce9e2e1b 1769
e81cd2d6 1770 cmd = kzalloc(size, GFP_ATOMIC);
a66098da 1771 if (cmd == NULL)
e81cd2d6 1772 return NULL;
a66098da
LB		 1773
1774 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
1775 cmd->header.length = cpu_to_le16(size);
d5e30845
LB		 1776 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED |
1777 MWL8K_ENABLE_RX_BROADCAST);
1778
1779 if (allmulti) {
1780 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST);
1781 } else if (mc_count) {
1782 int i;
1783
1784 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
1785 cmd->numaddr = cpu_to_le16(mc_count);
1786 for (i = 0; i < mc_count && mclist; i++) {
1787 if (mclist->da_addrlen != ETH_ALEN) {
1788 kfree(cmd);
1789 return NULL;
1790 }
1791 memcpy(cmd->addr[i], mclist->da_addr, ETH_ALEN);
1792 mclist = mclist->next;
a66098da 1793 }
a66098da
LB		 1794 }
1795
e81cd2d6 1796 return &cmd->header;
a66098da
LB		 1797}
1798
1799/*
55489b6e 1800 * CMD_GET_STAT.
a66098da 1801 */
55489b6e 1802struct mwl8k_cmd_get_stat {
a66098da 1803 struct mwl8k_cmd_pkt header;
a66098da
LB		 1804 __le32 stats[64];
1805} __attribute__((packed));
1806
1807#define MWL8K_STAT_ACK_FAILURE 9
1808#define MWL8K_STAT_RTS_FAILURE 12
1809#define MWL8K_STAT_FCS_ERROR 24
1810#define MWL8K_STAT_RTS_SUCCESS 11
1811
55489b6e
LB		 1812static int mwl8k_cmd_get_stat(struct ieee80211_hw *hw,
1813 struct ieee80211_low_level_stats *stats)
a66098da 1814{
55489b6e 1815 struct mwl8k_cmd_get_stat *cmd;
a66098da
LB		 1816 int rc;
1817
1818 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1819 if (cmd == NULL)
1820 return -ENOMEM;
1821
1822 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
1823 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB		 1824
1825 rc = mwl8k_post_cmd(hw, &cmd->header);
1826 if (!rc) {
1827 stats->dot11ACKFailureCount =
1828 le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
1829 stats->dot11RTSFailureCount =
1830 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
1831 stats->dot11FCSErrorCount =
1832 le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
1833 stats->dot11RTSSuccessCount =
1834 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
1835 }
1836 kfree(cmd);
1837
1838 return rc;
1839}
1840
1841/*
55489b6e 1842 * CMD_RADIO_CONTROL.
a66098da 1843 */
55489b6e 1844struct mwl8k_cmd_radio_control {
a66098da
LB		 1845 struct mwl8k_cmd_pkt header;
1846 __le16 action;
1847 __le16 control;
1848 __le16 radio_on;
1849} __attribute__((packed));
1850
c46563b7 1851static int
55489b6e 1852mwl8k_cmd_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
a66098da
LB		 1853{
1854 struct mwl8k_priv *priv = hw->priv;
55489b6e 1855 struct mwl8k_cmd_radio_control *cmd;
a66098da
LB		 1856 int rc;
1857
c46563b7 1858 if (enable == priv->radio_on && !force)
a66098da
LB		 1859 return 0;
1860
a66098da
LB		 1861 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1862 if (cmd == NULL)
1863 return -ENOMEM;
1864
1865 cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
1866 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1867 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
68ce3884 1868 cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
a66098da
LB		 1869 cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
1870
1871 rc = mwl8k_post_cmd(hw, &cmd->header);
1872 kfree(cmd);
1873
1874 if (!rc)
c46563b7 1875 priv->radio_on = enable;
a66098da
LB		 1876
1877 return rc;
1878}
1879
55489b6e 1880static int mwl8k_cmd_radio_disable(struct ieee80211_hw *hw)
c46563b7 1881{
55489b6e 1882 return mwl8k_cmd_radio_control(hw, 0, 0);
c46563b7
LB		 1883}
1884
55489b6e 1885static int mwl8k_cmd_radio_enable(struct ieee80211_hw *hw)
c46563b7 1886{
55489b6e 1887 return mwl8k_cmd_radio_control(hw, 1, 0);
c46563b7
LB		 1888}
1889
a66098da
LB		 1890static int
1891mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
1892{
99200a99 1893 struct mwl8k_priv *priv = hw->priv;
a66098da 1894
68ce3884 1895 priv->radio_short_preamble = short_preamble;
a66098da 1896
55489b6e 1897 return mwl8k_cmd_radio_control(hw, 1, 1);
a66098da
LB		 1898}
1899
1900/*
55489b6e 1901 * CMD_RF_TX_POWER.
a66098da
LB		 1902 */
1903#define MWL8K_TX_POWER_LEVEL_TOTAL 8
1904
55489b6e 1905struct mwl8k_cmd_rf_tx_power {
a66098da
LB		 1906 struct mwl8k_cmd_pkt header;
1907 __le16 action;
1908 __le16 support_level;
1909 __le16 current_level;
1910 __le16 reserved;
1911 __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
1912} __attribute__((packed));
1913
55489b6e 1914static int mwl8k_cmd_rf_tx_power(struct ieee80211_hw *hw, int dBm)
a66098da 1915{
55489b6e 1916 struct mwl8k_cmd_rf_tx_power *cmd;
a66098da
LB		 1917 int rc;
1918
1919 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1920 if (cmd == NULL)
1921 return -ENOMEM;
1922
1923 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
1924 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1925 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1926 cmd->support_level = cpu_to_le16(dBm);
1927
1928 rc = mwl8k_post_cmd(hw, &cmd->header);
1929 kfree(cmd);
1930
1931 return rc;
1932}
1933
08b06347
LB		 1934/*
1935 * CMD_RF_ANTENNA.
1936 */
1937struct mwl8k_cmd_rf_antenna {
1938 struct mwl8k_cmd_pkt header;
1939 __le16 antenna;
1940 __le16 mode;
1941} __attribute__((packed));
1942
1943#define MWL8K_RF_ANTENNA_RX 1
1944#define MWL8K_RF_ANTENNA_TX 2
1945
1946static int
1947mwl8k_cmd_rf_antenna(struct ieee80211_hw *hw, int antenna, int mask)
1948{
1949 struct mwl8k_cmd_rf_antenna *cmd;
1950 int rc;
1951
1952 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1953 if (cmd == NULL)
1954 return -ENOMEM;
1955
1956 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_ANTENNA);
1957 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1958 cmd->antenna = cpu_to_le16(antenna);
1959 cmd->mode = cpu_to_le16(mask);
1960
1961 rc = mwl8k_post_cmd(hw, &cmd->header);
1962 kfree(cmd);
1963
1964 return rc;
1965}
1966
a66098da
LB		 1967/*
1968 * CMD_SET_PRE_SCAN.
1969 */
1970struct mwl8k_cmd_set_pre_scan {
1971 struct mwl8k_cmd_pkt header;
1972} __attribute__((packed));
1973
1974static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
1975{
1976 struct mwl8k_cmd_set_pre_scan *cmd;
1977 int rc;
1978
1979 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1980 if (cmd == NULL)
1981 return -ENOMEM;
1982
1983 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
1984 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1985
1986 rc = mwl8k_post_cmd(hw, &cmd->header);
1987 kfree(cmd);
1988
1989 return rc;
1990}
1991
1992/*
1993 * CMD_SET_POST_SCAN.
1994 */
1995struct mwl8k_cmd_set_post_scan {
1996 struct mwl8k_cmd_pkt header;
1997 __le32 isibss;
d89173f2 1998 __u8 bssid[ETH_ALEN];
a66098da
LB		 1999} __attribute__((packed));
2000
2001static int
0a11dfc3 2002mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, const __u8 *mac)
a66098da
LB		 2003{
2004 struct mwl8k_cmd_set_post_scan *cmd;
2005 int rc;
2006
2007 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2008 if (cmd == NULL)
2009 return -ENOMEM;
2010
2011 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
2012 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2013 cmd->isibss = 0;
d89173f2 2014 memcpy(cmd->bssid, mac, ETH_ALEN);
a66098da
LB		 2015
2016 rc = mwl8k_post_cmd(hw, &cmd->header);
2017 kfree(cmd);
2018
2019 return rc;
2020}
2021
2022/*
2023 * CMD_SET_RF_CHANNEL.
2024 */
2025struct mwl8k_cmd_set_rf_channel {
2026 struct mwl8k_cmd_pkt header;
2027 __le16 action;
2028 __u8 current_channel;
2029 __le32 channel_flags;
2030} __attribute__((packed));
2031
2032static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
2033 struct ieee80211_channel *channel)
2034{
2035 struct mwl8k_cmd_set_rf_channel *cmd;
2036 int rc;
2037
2038 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2039 if (cmd == NULL)
2040 return -ENOMEM;
2041
2042 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
2043 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2044 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2045 cmd->current_channel = channel->hw_value;
2046 if (channel->band == IEEE80211_BAND_2GHZ)
2047 cmd->channel_flags = cpu_to_le32(0x00000081);
2048 else
2049 cmd->channel_flags = cpu_to_le32(0x00000000);
2050
2051 rc = mwl8k_post_cmd(hw, &cmd->header);
2052 kfree(cmd);
2053
2054 return rc;
2055}
2056
2057/*
55489b6e 2058 * CMD_SET_AID.
a66098da 2059 */
55489b6e
LB		 2060#define MWL8K_FRAME_PROT_DISABLED 0x00
2061#define MWL8K_FRAME_PROT_11G 0x07
2062#define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
2063#define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
a66098da 2064
55489b6e
LB		 2065struct mwl8k_cmd_update_set_aid {
2066 struct mwl8k_cmd_pkt header;
2067 __le16 aid;
a66098da 2068
55489b6e
LB		 2069 /* AP's MAC address (BSSID) */
2070 __u8 bssid[ETH_ALEN];
2071 __le16 protection_mode;
2072 __u8 supp_rates[14];
a66098da
LB		 2073} __attribute__((packed));
2074
c6e96010
LB		 2075static void legacy_rate_mask_to_array(u8 *rates, u32 mask)
2076{
2077 int i;
2078 int j;
2079
2080 /*
2081 * Clear nonstandard rates 4 and 13.
2082 */
2083 mask &= 0x1fef;
2084
2085 for (i = 0, j = 0; i < 14; i++) {
2086 if (mask & (1 << i))
2087 rates[j++] = mwl8k_rates[i].hw_value;
2088 }
2089}
2090
55489b6e 2091static int
c6e96010
LB		 2092mwl8k_cmd_set_aid(struct ieee80211_hw *hw,
2093 struct ieee80211_vif *vif, u32 legacy_rate_mask)
a66098da 2094{
55489b6e
LB		 2095 struct mwl8k_cmd_update_set_aid *cmd;
2096 u16 prot_mode;
a66098da
LB		 2097 int rc;
2098
2099 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2100 if (cmd == NULL)
2101 return -ENOMEM;
2102
55489b6e 2103 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
a66098da 2104 cmd->header.length = cpu_to_le16(sizeof(*cmd));
7dc6a7a7 2105 cmd->aid = cpu_to_le16(vif->bss_conf.aid);
0a11dfc3 2106 memcpy(cmd->bssid, vif->bss_conf.bssid, ETH_ALEN);
a66098da 2107
7dc6a7a7 2108 if (vif->bss_conf.use_cts_prot) {
55489b6e
LB		 2109 prot_mode = MWL8K_FRAME_PROT_11G;
2110 } else {
7dc6a7a7 2111 switch (vif->bss_conf.ht_operation_mode &
55489b6e
LB		 2112 IEEE80211_HT_OP_MODE_PROTECTION) {
2113 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
2114 prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
2115 break;
2116 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
2117 prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
2118 break;
2119 default:
2120 prot_mode = MWL8K_FRAME_PROT_DISABLED;
2121 break;
2122 }
2123 }
2124 cmd->protection_mode = cpu_to_le16(prot_mode);
a66098da 2125
c6e96010 2126 legacy_rate_mask_to_array(cmd->supp_rates, legacy_rate_mask);
a66098da
LB		 2127
2128 rc = mwl8k_post_cmd(hw, &cmd->header);
2129 kfree(cmd);
2130
2131 return rc;
2132}
2133
32060e1b 2134/*
55489b6e 2135 * CMD_SET_RATE.
32060e1b 2136 */
55489b6e
LB		 2137struct mwl8k_cmd_set_rate {
2138 struct mwl8k_cmd_pkt header;
2139 __u8 legacy_rates[14];
2140
2141 /* Bitmap for supported MCS codes. */
2142 __u8 mcs_set[16];
2143 __u8 reserved[16];
32060e1b
LB		 2144} __attribute__((packed));
2145
55489b6e 2146static int
c6e96010
LB		 2147mwl8k_cmd_set_rate(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2148 u32 legacy_rate_mask)
32060e1b 2149{
55489b6e 2150 struct mwl8k_cmd_set_rate *cmd;
32060e1b
LB		 2151 int rc;
2152
2153 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2154 if (cmd == NULL)
2155 return -ENOMEM;
2156
55489b6e 2157 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
32060e1b 2158 cmd->header.length = cpu_to_le16(sizeof(*cmd));
c6e96010 2159 legacy_rate_mask_to_array(cmd->legacy_rates, legacy_rate_mask);
32060e1b
LB		 2160
2161 rc = mwl8k_post_cmd(hw, &cmd->header);
2162 kfree(cmd);
2163
2164 return rc;
2165}
2166
a66098da 2167/*
55489b6e 2168 * CMD_FINALIZE_JOIN.
a66098da 2169 */
55489b6e
LB		 2170#define MWL8K_FJ_BEACON_MAXLEN 128
2171
2172struct mwl8k_cmd_finalize_join {
a66098da 2173 struct mwl8k_cmd_pkt header;
55489b6e
LB		 2174 __le32 sleep_interval; /* Number of beacon periods to sleep */
2175 __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
a66098da
LB		 2176} __attribute__((packed));
2177
55489b6e
LB		 2178static int mwl8k_cmd_finalize_join(struct ieee80211_hw *hw, void *frame,
2179 int framelen, int dtim)
a66098da 2180{
55489b6e
LB		 2181 struct mwl8k_cmd_finalize_join *cmd;
2182 struct ieee80211_mgmt *payload = frame;
2183 int payload_len;
a66098da
LB		 2184 int rc;
2185
2186 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2187 if (cmd == NULL)
2188 return -ENOMEM;
2189
55489b6e 2190 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
a66098da 2191 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB		 2192 cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
2193
2194 payload_len = framelen - ieee80211_hdrlen(payload->frame_control);
2195 if (payload_len < 0)
2196 payload_len = 0;
2197 else if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2198 payload_len = MWL8K_FJ_BEACON_MAXLEN;
2199
2200 memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
a66098da
LB		 2201
2202 rc = mwl8k_post_cmd(hw, &cmd->header);
2203 kfree(cmd);
2204
2205 return rc;
2206}
2207
2208/*
55489b6e 2209 * CMD_SET_RTS_THRESHOLD.
a66098da 2210 */
55489b6e 2211struct mwl8k_cmd_set_rts_threshold {
a66098da
LB		 2212 struct mwl8k_cmd_pkt header;
2213 __le16 action;
55489b6e 2214 __le16 threshold;
a66098da
LB		 2215} __attribute__((packed));
2216
55489b6e
LB		 2217static int mwl8k_cmd_set_rts_threshold(struct ieee80211_hw *hw,
2218 u16 action, u16 threshold)
a66098da 2219{
55489b6e 2220 struct mwl8k_cmd_set_rts_threshold *cmd;
a66098da
LB		 2221 int rc;
2222
2223 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2224 if (cmd == NULL)
2225 return -ENOMEM;
2226
55489b6e 2227 cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
a66098da 2228 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB		 2229 cmd->action = cpu_to_le16(action);
2230 cmd->threshold = cpu_to_le16(threshold);
a66098da
LB		 2231
2232 rc = mwl8k_post_cmd(hw, &cmd->header);
2233 kfree(cmd);
2234
a66098da
LB		 2235 return rc;
2236}
2237
2238/*
55489b6e 2239 * CMD_SET_SLOT.
a66098da 2240 */
55489b6e 2241struct mwl8k_cmd_set_slot {
a66098da
LB		 2242 struct mwl8k_cmd_pkt header;
2243 __le16 action;
55489b6e 2244 __u8 short_slot;
a66098da
LB		 2245} __attribute__((packed));
2246
55489b6e 2247static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time)
a66098da 2248{
55489b6e 2249 struct mwl8k_cmd_set_slot *cmd;
a66098da
LB		 2250 int rc;
2251
2252 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2253 if (cmd == NULL)
2254 return -ENOMEM;
2255
55489b6e 2256 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
a66098da 2257 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB		 2258 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2259 cmd->short_slot = short_slot_time;
a66098da
LB		 2260
2261 rc = mwl8k_post_cmd(hw, &cmd->header);
2262 kfree(cmd);
2263
2264 return rc;
2265}
2266
2267/*
2268 * CMD_SET_EDCA_PARAMS.
2269 */
2270struct mwl8k_cmd_set_edca_params {
2271 struct mwl8k_cmd_pkt header;
2272
2273 /* See MWL8K_SET_EDCA_XXX below */
2274 __le16 action;
2275
2276 /* TX opportunity in units of 32 us */
2277 __le16 txop;
2278
2e484c89
LB		 2279 union {
2280 struct {
2281 /* Log exponent of max contention period: 0...15 */
2282 __le32 log_cw_max;
2283
2284 /* Log exponent of min contention period: 0...15 */
2285 __le32 log_cw_min;
2286
2287 /* Adaptive interframe spacing in units of 32us */
2288 __u8 aifs;
2289
2290 /* TX queue to configure */
2291 __u8 txq;
2292 } ap;
2293 struct {
2294 /* Log exponent of max contention period: 0...15 */
2295 __u8 log_cw_max;
a66098da 2296
2e484c89
LB		 2297 /* Log exponent of min contention period: 0...15 */
2298 __u8 log_cw_min;
a66098da 2299
2e484c89
LB		 2300 /* Adaptive interframe spacing in units of 32us */
2301 __u8 aifs;
a66098da 2302
2e484c89
LB		 2303 /* TX queue to configure */
2304 __u8 txq;
2305 } sta;
2306 };
a66098da
LB		 2307} __attribute__((packed));
2308
a66098da
LB		 2309#define MWL8K_SET_EDCA_CW 0x01
2310#define MWL8K_SET_EDCA_TXOP 0x02
2311#define MWL8K_SET_EDCA_AIFS 0x04
2312
2313#define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
2314 MWL8K_SET_EDCA_TXOP | \
2315 MWL8K_SET_EDCA_AIFS)
2316
2317static int
55489b6e
LB		 2318mwl8k_cmd_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
2319 __u16 cw_min, __u16 cw_max,
2320 __u8 aifs, __u16 txop)
a66098da 2321{
2e484c89 2322 struct mwl8k_priv *priv = hw->priv;
a66098da 2323 struct mwl8k_cmd_set_edca_params *cmd;
a66098da
LB		 2324 int rc;
2325
2326 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2327 if (cmd == NULL)
2328 return -ENOMEM;
2329
22995b24
LB		 2330 /*
2331 * Queues 0 (BE) and 1 (BK) are swapped in hardware for
2332 * this call.
2333 */
2334 qnum ^= !(qnum >> 1);
2335
a66098da
LB		 2336 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
2337 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB		 2338 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
2339 cmd->txop = cpu_to_le16(txop);
2e484c89
LB		 2340 if (priv->ap_fw) {
2341 cmd->ap.log_cw_max = cpu_to_le32(ilog2(cw_max + 1));
2342 cmd->ap.log_cw_min = cpu_to_le32(ilog2(cw_min + 1));
2343 cmd->ap.aifs = aifs;
2344 cmd->ap.txq = qnum;
2345 } else {
2346 cmd->sta.log_cw_max = (u8)ilog2(cw_max + 1);
2347 cmd->sta.log_cw_min = (u8)ilog2(cw_min + 1);
2348 cmd->sta.aifs = aifs;
2349 cmd->sta.txq = qnum;
2350 }
a66098da
LB		 2351
2352 rc = mwl8k_post_cmd(hw, &cmd->header);
2353 kfree(cmd);
2354
2355 return rc;
2356}
2357
2358/*
55489b6e 2359 * CMD_SET_WMM_MODE.
a66098da 2360 */
55489b6e 2361struct mwl8k_cmd_set_wmm_mode {
a66098da 2362 struct mwl8k_cmd_pkt header;
55489b6e 2363 __le16 action;
a66098da
LB		 2364} __attribute__((packed));
2365
55489b6e 2366static int mwl8k_cmd_set_wmm_mode(struct ieee80211_hw *hw, bool enable)
a66098da 2367{
55489b6e
LB		 2368 struct mwl8k_priv *priv = hw->priv;
2369 struct mwl8k_cmd_set_wmm_mode *cmd;
a66098da
LB		 2370 int rc;
2371
a66098da
LB		 2372 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2373 if (cmd == NULL)
2374 return -ENOMEM;
2375
55489b6e 2376 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
a66098da 2377 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e 2378 cmd->action = cpu_to_le16(!!enable);
a66098da
LB		 2379
2380 rc = mwl8k_post_cmd(hw, &cmd->header);
2381 kfree(cmd);
16cec43d 2382
55489b6e
LB		 2383 if (!rc)
2384 priv->wmm_enabled = enable;
a66098da
LB		 2385
2386 return rc;
2387}
2388
2389/*
55489b6e 2390 * CMD_MIMO_CONFIG.
a66098da 2391 */
55489b6e
LB		 2392struct mwl8k_cmd_mimo_config {
2393 struct mwl8k_cmd_pkt header;
2394 __le32 action;
2395 __u8 rx_antenna_map;
2396 __u8 tx_antenna_map;
a66098da
LB		 2397} __attribute__((packed));
2398
55489b6e 2399static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
a66098da 2400{
55489b6e 2401 struct mwl8k_cmd_mimo_config *cmd;
a66098da
LB		 2402 int rc;
2403
2404 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2405 if (cmd == NULL)
2406 return -ENOMEM;
2407
55489b6e 2408 cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
a66098da 2409 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB		 2410 cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
2411 cmd->rx_antenna_map = rx;
2412 cmd->tx_antenna_map = tx;
a66098da
LB		 2413
2414 rc = mwl8k_post_cmd(hw, &cmd->header);
2415 kfree(cmd);
2416
2417 return rc;
2418}
2419
2420/*
2421 * CMD_USE_FIXED_RATE.
2422 */
2423#define MWL8K_RATE_TABLE_SIZE 8
2424#define MWL8K_UCAST_RATE 0
a66098da
LB		 2425#define MWL8K_USE_AUTO_RATE 0x0002
2426
2427struct mwl8k_rate_entry {
2428 /* Set to 1 if HT rate, 0 if legacy. */
2429 __le32 is_ht_rate;
2430
2431 /* Set to 1 to use retry_count field. */
2432 __le32 enable_retry;
2433
2434 /* Specified legacy rate or MCS. */
2435 __le32 rate;
2436
2437 /* Number of allowed retries. */
2438 __le32 retry_count;
2439} __attribute__((packed));
2440
2441struct mwl8k_rate_table {
2442 /* 1 to allow specified rate and below */
2443 __le32 allow_rate_drop;
2444 __le32 num_rates;
2445 struct mwl8k_rate_entry rate_entry[MWL8K_RATE_TABLE_SIZE];
2446} __attribute__((packed));
2447
2448struct mwl8k_cmd_use_fixed_rate {
2449 struct mwl8k_cmd_pkt header;
2450 __le32 action;
2451 struct mwl8k_rate_table rate_table;
2452
2453 /* Unicast, Broadcast or Multicast */
2454 __le32 rate_type;
2455 __le32 reserved1;
2456 __le32 reserved2;
2457} __attribute__((packed));
2458
2459static int mwl8k_cmd_use_fixed_rate(struct ieee80211_hw *hw,
2460 u32 action, u32 rate_type, struct mwl8k_rate_table *rate_table)
2461{
2462 struct mwl8k_cmd_use_fixed_rate *cmd;
2463 int count;
2464 int rc;
2465
2466 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2467 if (cmd == NULL)
2468 return -ENOMEM;
2469
2470 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
2471 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2472
2473 cmd->action = cpu_to_le32(action);
2474 cmd->rate_type = cpu_to_le32(rate_type);
2475
2476 if (rate_table != NULL) {
c2c357ce
LB		 2477 /*
2478 * Copy over each field manually so that endian
2479 * conversion can be done.
2480 */
a66098da
LB		 2481 cmd->rate_table.allow_rate_drop =
2482 cpu_to_le32(rate_table->allow_rate_drop);
2483 cmd->rate_table.num_rates =
2484 cpu_to_le32(rate_table->num_rates);
2485
2486 for (count = 0; count < rate_table->num_rates; count++) {
2487 struct mwl8k_rate_entry *dst =
2488 &cmd->rate_table.rate_entry[count];
2489 struct mwl8k_rate_entry *src =
2490 &rate_table->rate_entry[count];
2491
2492 dst->is_ht_rate = cpu_to_le32(src->is_ht_rate);
2493 dst->enable_retry = cpu_to_le32(src->enable_retry);
2494 dst->rate = cpu_to_le32(src->rate);
2495 dst->retry_count = cpu_to_le32(src->retry_count);
2496 }
2497 }
2498
2499 rc = mwl8k_post_cmd(hw, &cmd->header);
2500 kfree(cmd);
2501
2502 return rc;
2503}
2504
55489b6e
LB		 2505/*
2506 * CMD_ENABLE_SNIFFER.
2507 */
2508struct mwl8k_cmd_enable_sniffer {
2509 struct mwl8k_cmd_pkt header;
2510 __le32 action;
2511} __attribute__((packed));
2512
2513static int mwl8k_cmd_enable_sniffer(struct ieee80211_hw *hw, bool enable)
2514{
2515 struct mwl8k_cmd_enable_sniffer *cmd;
2516 int rc;
2517
2518 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2519 if (cmd == NULL)
2520 return -ENOMEM;
2521
2522 cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
2523 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2524 cmd->action = cpu_to_le32(!!enable);
2525
2526 rc = mwl8k_post_cmd(hw, &cmd->header);
2527 kfree(cmd);
2528
2529 return rc;
2530}
2531
2532/*
2533 * CMD_SET_MAC_ADDR.
2534 */
2535struct mwl8k_cmd_set_mac_addr {
2536 struct mwl8k_cmd_pkt header;
2537 union {
2538 struct {
2539 __le16 mac_type;
2540 __u8 mac_addr[ETH_ALEN];
2541 } mbss;
2542 __u8 mac_addr[ETH_ALEN];
2543 };
2544} __attribute__((packed));
2545
2546static int mwl8k_cmd_set_mac_addr(struct ieee80211_hw *hw, u8 *mac)
2547{
2548 struct mwl8k_priv *priv = hw->priv;
2549 struct mwl8k_cmd_set_mac_addr *cmd;
2550 int rc;
2551
2552 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2553 if (cmd == NULL)
2554 return -ENOMEM;
2555
2556 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR);
2557 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2558 if (priv->ap_fw) {
2559 cmd->mbss.mac_type = 0;
2560 memcpy(cmd->mbss.mac_addr, mac, ETH_ALEN);
2561 } else {
2562 memcpy(cmd->mac_addr, mac, ETH_ALEN);
2563 }
2564
2565 rc = mwl8k_post_cmd(hw, &cmd->header);
2566 kfree(cmd);
2567
2568 return rc;
2569}
2570
2571/*
2572 * CMD_SET_RATEADAPT_MODE.
2573 */
2574struct mwl8k_cmd_set_rate_adapt_mode {
2575 struct mwl8k_cmd_pkt header;
2576 __le16 action;
2577 __le16 mode;
2578} __attribute__((packed));
2579
2580static int mwl8k_cmd_set_rateadapt_mode(struct ieee80211_hw *hw, __u16 mode)
2581{
2582 struct mwl8k_cmd_set_rate_adapt_mode *cmd;
2583 int rc;
2584
2585 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2586 if (cmd == NULL)
2587 return -ENOMEM;
2588
2589 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
2590 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2591 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2592 cmd->mode = cpu_to_le16(mode);
2593
2594 rc = mwl8k_post_cmd(hw, &cmd->header);
2595 kfree(cmd);
2596
2597 return rc;
2598}
2599
2600/*
2601 * CMD_UPDATE_STADB.
2602 */
25d81b1e
LB		 2603struct ewc_ht_info {
2604 __le16 control1;
2605 __le16 control2;
2606 __le16 control3;
2607} __attribute__((packed));
2608
2609struct peer_capability_info {
2610 /* Peer type - AP vs. STA. */
2611 __u8 peer_type;
2612
2613 /* Basic 802.11 capabilities from assoc resp. */
2614 __le16 basic_caps;
2615
2616 /* Set if peer supports 802.11n high throughput (HT). */
2617 __u8 ht_support;
2618
2619 /* Valid if HT is supported. */
2620 __le16 ht_caps;
2621 __u8 extended_ht_caps;
2622 struct ewc_ht_info ewc_info;
2623
2624 /* Legacy rate table. Intersection of our rates and peer rates. */
2625 __u8 legacy_rates[12];
2626
2627 /* HT rate table. Intersection of our rates and peer rates. */
2628 __u8 ht_rates[16];
2629 __u8 pad[16];
2630
2631 /* If set, interoperability mode, no proprietary extensions. */
2632 __u8 interop;
2633 __u8 pad2;
2634 __u8 station_id;
2635 __le16 amsdu_enabled;
2636} __attribute__((packed));
2637
55489b6e
LB		 2638struct mwl8k_cmd_update_stadb {
2639 struct mwl8k_cmd_pkt header;
2640
2641 /* See STADB_ACTION_TYPE */
2642 __le32 action;
2643
2644 /* Peer MAC address */
2645 __u8 peer_addr[ETH_ALEN];
2646
2647 __le32 reserved;
2648
2649 /* Peer info - valid during add/update. */
2650 struct peer_capability_info peer_info;
2651} __attribute__((packed));
2652
a680400e
LB		 2653#define MWL8K_STA_DB_MODIFY_ENTRY 1
2654#define MWL8K_STA_DB_DEL_ENTRY 2
2655
2656/* Peer Entry flags - used to define the type of the peer node */
2657#define MWL8K_PEER_TYPE_ACCESSPOINT 2
2658
2659static int mwl8k_cmd_update_stadb_add(struct ieee80211_hw *hw,
c6e96010
LB		 2660 struct ieee80211_vif *vif,
2661 u8 *addr, u32 legacy_rate_mask)
55489b6e 2662{
55489b6e 2663 struct mwl8k_cmd_update_stadb *cmd;
a680400e 2664 struct peer_capability_info *p;
55489b6e
LB		 2665 int rc;
2666
2667 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2668 if (cmd == NULL)
2669 return -ENOMEM;
2670
2671 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
2672 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a680400e
LB		 2673 cmd->action = cpu_to_le32(MWL8K_STA_DB_MODIFY_ENTRY);
2674 memcpy(cmd->peer_addr, addr, ETH_ALEN);
55489b6e 2675
a680400e
LB		 2676 p = &cmd->peer_info;
2677 p->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
2678 p->basic_caps = cpu_to_le16(vif->bss_conf.assoc_capability);
c6e96010 2679 legacy_rate_mask_to_array(p->legacy_rates, legacy_rate_mask);
a680400e
LB		 2680 p->interop = 1;
2681 p->amsdu_enabled = 0;
2682
2683 rc = mwl8k_post_cmd(hw, &cmd->header);
2684 kfree(cmd);
2685
2686 return rc ? rc : p->station_id;
2687}
2688
2689static int mwl8k_cmd_update_stadb_del(struct ieee80211_hw *hw,
2690 struct ieee80211_vif *vif, u8 *addr)
2691{
2692 struct mwl8k_cmd_update_stadb *cmd;
2693 int rc;
2694
2695 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2696 if (cmd == NULL)
2697 return -ENOMEM;
2698
2699 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
2700 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2701 cmd->action = cpu_to_le32(MWL8K_STA_DB_DEL_ENTRY);
bbfd9128 2702 memcpy(cmd->peer_addr, addr, ETH_ALEN);
55489b6e 2703
a680400e 2704 rc = mwl8k_post_cmd(hw, &cmd->header);
55489b6e
LB		 2705 kfree(cmd);
2706
2707 return rc;
2708}
2709
a66098da
LB		 2710
2711/*
2712 * Interrupt handling.
2713 */
2714static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
2715{
2716 struct ieee80211_hw *hw = dev_id;
2717 struct mwl8k_priv *priv = hw->priv;
2718 u32 status;
2719
2720 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2721 iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2722
a66098da
LB		 2723 if (!status)
2724 return IRQ_NONE;
2725
2726 if (status & MWL8K_A2H_INT_TX_DONE)
2727 tasklet_schedule(&priv->tx_reclaim_task);
2728
2729 if (status & MWL8K_A2H_INT_RX_READY) {
2730 while (rxq_process(hw, 0, 1))
2731 rxq_refill(hw, 0, 1);
2732 }
2733
2734 if (status & MWL8K_A2H_INT_OPC_DONE) {
618952a7 2735 if (priv->hostcmd_wait != NULL)
a66098da 2736 complete(priv->hostcmd_wait);
a66098da
LB		 2737 }
2738
2739 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
618952a7 2740 if (!mutex_is_locked(&priv->fw_mutex) &&
88de754a 2741 priv->radio_on && priv->pending_tx_pkts)
618952a7 2742 mwl8k_tx_start(priv);
a66098da
LB		 2743 }
2744
2745 return IRQ_HANDLED;
2746}
2747
2748
2749/*
2750 * Core driver operations.
2751 */
2752static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2753{
2754 struct mwl8k_priv *priv = hw->priv;
2755 int index = skb_get_queue_mapping(skb);
2756 int rc;
2757
2758 if (priv->current_channel == NULL) {
2759 printk(KERN_DEBUG "%s: dropped TX frame since radio "
c2c357ce 2760 "disabled\n", wiphy_name(hw->wiphy));
a66098da
LB		 2761 dev_kfree_skb(skb);
2762 return NETDEV_TX_OK;
2763 }
2764
2765 rc = mwl8k_txq_xmit(hw, index, skb);
2766
2767 return rc;
2768}
2769
a66098da
LB		 2770static int mwl8k_start(struct ieee80211_hw *hw)
2771{
a66098da
LB		 2772 struct mwl8k_priv *priv = hw->priv;
2773 int rc;
2774
a0607fd3 2775 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
a66098da
LB		 2776 IRQF_SHARED, MWL8K_NAME, hw);
2777 if (rc) {
2778 printk(KERN_ERR "%s: failed to register IRQ handler\n",
c2c357ce 2779 wiphy_name(hw->wiphy));
2ec610cb 2780 return -EIO;
a66098da
LB		 2781 }
2782
2ec610cb
LB		 2783 /* Enable tx reclaim tasklet */
2784 tasklet_enable(&priv->tx_reclaim_task);
2785
a66098da 2786 /* Enable interrupts */
c23b5a69 2787 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da 2788
2ec610cb
LB		 2789 rc = mwl8k_fw_lock(hw);
2790 if (!rc) {
55489b6e 2791 rc = mwl8k_cmd_radio_enable(hw);
a66098da 2792
5e4cf166
LB		 2793 if (!priv->ap_fw) {
2794 if (!rc)
55489b6e 2795 rc = mwl8k_cmd_enable_sniffer(hw, 0);
a66098da 2796
5e4cf166
LB		 2797 if (!rc)
2798 rc = mwl8k_cmd_set_pre_scan(hw);
2799
2800 if (!rc)
2801 rc = mwl8k_cmd_set_post_scan(hw,
2802 "\x00\x00\x00\x00\x00\x00");
2803 }
2ec610cb
LB		 2804
2805 if (!rc)
55489b6e 2806 rc = mwl8k_cmd_set_rateadapt_mode(hw, 0);
a66098da 2807
2ec610cb 2808 if (!rc)
55489b6e 2809 rc = mwl8k_cmd_set_wmm_mode(hw, 0);
a66098da 2810
2ec610cb
LB		 2811 mwl8k_fw_unlock(hw);
2812 }
2813
2814 if (rc) {
2815 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2816 free_irq(priv->pdev->irq, hw);
2817 tasklet_disable(&priv->tx_reclaim_task);
2818 }
a66098da
LB		 2819
2820 return rc;
2821}
2822
a66098da
LB		 2823static void mwl8k_stop(struct ieee80211_hw *hw)
2824{
a66098da
LB		 2825 struct mwl8k_priv *priv = hw->priv;
2826 int i;
2827
55489b6e 2828 mwl8k_cmd_radio_disable(hw);
a66098da
LB		 2829
2830 ieee80211_stop_queues(hw);
2831
a66098da 2832 /* Disable interrupts */
a66098da 2833 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 2834 free_irq(priv->pdev->irq, hw);
2835
2836 /* Stop finalize join worker */
2837 cancel_work_sync(&priv->finalize_join_worker);
2838 if (priv->beacon_skb != NULL)
2839 dev_kfree_skb(priv->beacon_skb);
2840
2841 /* Stop tx reclaim tasklet */
2842 tasklet_disable(&priv->tx_reclaim_task);
2843
a66098da
LB		 2844 /* Return all skbs to mac80211 */
2845 for (i = 0; i < MWL8K_TX_QUEUES; i++)
2846 mwl8k_txq_reclaim(hw, i, 1);
2847}
2848
2849static int mwl8k_add_interface(struct ieee80211_hw *hw,
1ed32e4f 2850 struct ieee80211_vif *vif)
a66098da
LB		 2851{
2852 struct mwl8k_priv *priv = hw->priv;
2853 struct mwl8k_vif *mwl8k_vif;
2854
2855 /*
2856 * We only support one active interface at a time.
2857 */
2858 if (priv->vif != NULL)
2859 return -EBUSY;
2860
2861 /*
2862 * We only support managed interfaces for now.
2863 */
1ed32e4f 2864 if (vif->type != NL80211_IFTYPE_STATION)
a66098da
LB		 2865 return -EINVAL;
2866
a43c49a8
LB		 2867 /*
2868 * Reject interface creation if sniffer mode is active, as
2869 * STA operation is mutually exclusive with hardware sniffer
2870 * mode.
2871 */
2872 if (priv->sniffer_enabled) {
2873 printk(KERN_INFO "%s: unable to create STA "
2874 "interface due to sniffer mode being enabled\n",
2875 wiphy_name(hw->wiphy));
2876 return -EINVAL;
2877 }
2878
a66098da 2879 /* Clean out driver private area */
1ed32e4f 2880 mwl8k_vif = MWL8K_VIF(vif);
a66098da
LB		 2881 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
2882
32060e1b 2883 /* Set and save the mac address */
1ed32e4f
JB		 2884 mwl8k_cmd_set_mac_addr(hw, vif->addr);
2885 memcpy(mwl8k_vif->mac_addr, vif->addr, ETH_ALEN);
a66098da 2886
a66098da
LB		 2887 /* Set Initial sequence number to zero */
2888 mwl8k_vif->seqno = 0;
2889
1ed32e4f 2890 priv->vif = vif;
a66098da
LB		 2891 priv->current_channel = NULL;
2892
2893 return 0;
2894}
2895
2896static void mwl8k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 2897 struct ieee80211_vif *vif)
a66098da
LB		 2898{
2899 struct mwl8k_priv *priv = hw->priv;
2900
2901 if (priv->vif == NULL)
2902 return;
2903
55489b6e 2904 mwl8k_cmd_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
32060e1b 2905
a66098da
LB		 2906 priv->vif = NULL;
2907}
2908
ee03a932 2909static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
a66098da 2910{
a66098da
LB		 2911 struct ieee80211_conf *conf = &hw->conf;
2912 struct mwl8k_priv *priv = hw->priv;
ee03a932 2913 int rc;
a66098da 2914
7595d67a 2915 if (conf->flags & IEEE80211_CONF_IDLE) {
55489b6e 2916 mwl8k_cmd_radio_disable(hw);
7595d67a 2917 priv->current_channel = NULL;
ee03a932 2918 return 0;
7595d67a
LB		 2919 }
2920
ee03a932
LB		 2921 rc = mwl8k_fw_lock(hw);
2922 if (rc)
2923 return rc;
a66098da 2924
55489b6e 2925 rc = mwl8k_cmd_radio_enable(hw);
ee03a932
LB		 2926 if (rc)
2927 goto out;
a66098da 2928
ee03a932
LB		 2929 rc = mwl8k_cmd_set_rf_channel(hw, conf->channel);
2930 if (rc)
2931 goto out;
2932
2933 priv->current_channel = conf->channel;
a66098da
LB		 2934
2935 if (conf->power_level > 18)
2936 conf->power_level = 18;
55489b6e 2937 rc = mwl8k_cmd_rf_tx_power(hw, conf->power_level);
ee03a932
LB		 2938 if (rc)
2939 goto out;
a66098da 2940
08b06347
LB		 2941 if (priv->ap_fw) {
2942 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_RX, 0x7);
2943 if (!rc)
2944 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_TX, 0x7);
2945 } else {
2946 rc = mwl8k_cmd_mimo_config(hw, 0x7, 0x7);
2947 }
a66098da 2948
ee03a932
LB		 2949out:
2950 mwl8k_fw_unlock(hw);
a66098da 2951
ee03a932 2952 return rc;
a66098da
LB		 2953}
2954
3a980d0a
LB		 2955static void mwl8k_bss_info_changed(struct ieee80211_hw *hw,
2956 struct ieee80211_vif *vif,
2957 struct ieee80211_bss_conf *info,
2958 u32 changed)
a66098da 2959{
a66098da 2960 struct mwl8k_priv *priv = hw->priv;
3a980d0a
LB		 2961 int rc;
2962
3a980d0a
LB		 2963 if ((changed & BSS_CHANGED_ASSOC) == 0)
2964 return;
a66098da 2965
a66098da
LB		 2966 priv->capture_beacon = false;
2967
3a980d0a 2968 rc = mwl8k_fw_lock(hw);
942457d6 2969 if (rc)
3a980d0a
LB		 2970 return;
2971
7dc6a7a7 2972 if (vif->bss_conf.assoc) {
c6e96010
LB		 2973 struct ieee80211_sta *ap;
2974 u32 legacy_rate_mask;
2975
2976 rcu_read_lock();
2977 ap = ieee80211_find_sta(vif, vif->bss_conf.bssid);
2978 if (ap != NULL)
2979 legacy_rate_mask = ap->supp_rates[IEEE80211_BAND_2GHZ];
2980 rcu_read_unlock();
2981
2982 if (ap == NULL)
2983 goto out;
2984
a66098da 2985 /* Install rates */
c6e96010 2986 rc = mwl8k_cmd_set_rate(hw, vif, legacy_rate_mask);
3a980d0a
LB		 2987 if (rc)
2988 goto out;
a66098da
LB		 2989
2990 /* Turn on rate adaptation */
3a980d0a
LB		 2991 rc = mwl8k_cmd_use_fixed_rate(hw, MWL8K_USE_AUTO_RATE,
2992 MWL8K_UCAST_RATE, NULL);
2993 if (rc)
2994 goto out;
a66098da
LB		 2995
2996 /* Set radio preamble */
7dc6a7a7
LB		 2997 rc = mwl8k_set_radio_preamble(hw,
2998 vif->bss_conf.use_short_preamble);
3a980d0a
LB		 2999 if (rc)
3000 goto out;
a66098da
LB		 3001
3002 /* Set slot time */
7dc6a7a7 3003 rc = mwl8k_cmd_set_slot(hw, vif->bss_conf.use_short_slot);
3a980d0a
LB		 3004 if (rc)
3005 goto out;
a66098da 3006
a66098da 3007 /* Set AID */
c6e96010 3008 rc = mwl8k_cmd_set_aid(hw, vif, legacy_rate_mask);
3a980d0a
LB		 3009 if (rc)
3010 goto out;
a66098da
LB		 3011
3012 /*
3013 * Finalize the join. Tell rx handler to process
3014 * next beacon from our BSSID.
3015 */
0a11dfc3 3016 memcpy(priv->capture_bssid, vif->bss_conf.bssid, ETH_ALEN);
a66098da 3017 priv->capture_beacon = true;
a66098da
LB		 3018 }
3019
3a980d0a
LB		 3020out:
3021 mwl8k_fw_unlock(hw);
a66098da
LB		 3022}
3023
e81cd2d6
LB		 3024static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
3025 int mc_count, struct dev_addr_list *mclist)
3026{
3027 struct mwl8k_cmd_pkt *cmd;
3028
447ced07
LB		 3029 /*
3030 * Synthesize and return a command packet that programs the
3031 * hardware multicast address filter. At this point we don't
3032 * know whether FIF_ALLMULTI is being requested, but if it is,
3033 * we'll end up throwing this packet away and creating a new
3034 * one in mwl8k_configure_filter().
3035 */
3036 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_count, mclist);
e81cd2d6
LB		 3037
3038 return (unsigned long)cmd;
3039}
3040
a43c49a8
LB		 3041static int
3042mwl8k_configure_filter_sniffer(struct ieee80211_hw *hw,
3043 unsigned int changed_flags,
3044 unsigned int *total_flags)
3045{
3046 struct mwl8k_priv *priv = hw->priv;
3047
3048 /*
3049 * Hardware sniffer mode is mutually exclusive with STA
3050 * operation, so refuse to enable sniffer mode if a STA
3051 * interface is active.
3052 */
3053 if (priv->vif != NULL) {
3054 if (net_ratelimit())
3055 printk(KERN_INFO "%s: not enabling sniffer "
3056 "mode because STA interface is active\n",
3057 wiphy_name(hw->wiphy));
3058 return 0;
3059 }
3060
3061 if (!priv->sniffer_enabled) {
55489b6e 3062 if (mwl8k_cmd_enable_sniffer(hw, 1))
a43c49a8
LB		 3063 return 0;
3064 priv->sniffer_enabled = true;
3065 }
3066
3067 *total_flags &= FIF_PROMISC_IN_BSS | FIF_ALLMULTI |
3068 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL |
3069 FIF_OTHER_BSS;
3070
3071 return 1;
3072}
3073
e6935ea1
LB		 3074static void mwl8k_configure_filter(struct ieee80211_hw *hw,
3075 unsigned int changed_flags,
3076 unsigned int *total_flags,
3077 u64 multicast)
3078{
3079 struct mwl8k_priv *priv = hw->priv;
a43c49a8
LB		 3080 struct mwl8k_cmd_pkt *cmd = (void *)(unsigned long)multicast;
3081
c0adae2c
LB		 3082 /*
3083 * AP firmware doesn't allow fine-grained control over
3084 * the receive filter.
3085 */
3086 if (priv->ap_fw) {
3087 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
3088 kfree(cmd);
3089 return;
3090 }
3091
a43c49a8
LB		 3092 /*
3093 * Enable hardware sniffer mode if FIF_CONTROL or
3094 * FIF_OTHER_BSS is requested.
3095 */
3096 if (*total_flags & (FIF_CONTROL | FIF_OTHER_BSS) &&
3097 mwl8k_configure_filter_sniffer(hw, changed_flags, total_flags)) {
3098 kfree(cmd);
3099 return;
3100 }
a66098da 3101
e6935ea1 3102 /* Clear unsupported feature flags */
447ced07 3103 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
a66098da 3104
e6935ea1
LB		 3105 if (mwl8k_fw_lock(hw))
3106 return;
a66098da 3107
a43c49a8 3108 if (priv->sniffer_enabled) {
55489b6e 3109 mwl8k_cmd_enable_sniffer(hw, 0);
a43c49a8
LB		 3110 priv->sniffer_enabled = false;
3111 }
3112
e6935ea1 3113 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
77165d88
LB		 3114 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
3115 /*
3116 * Disable the BSS filter.
3117 */
e6935ea1 3118 mwl8k_cmd_set_pre_scan(hw);
77165d88 3119 } else {
0a11dfc3 3120 const u8 *bssid;
a94cc97e 3121
77165d88
LB		 3122 /*
3123 * Enable the BSS filter.
3124 *
3125 * If there is an active STA interface, use that
3126 * interface's BSSID, otherwise use a dummy one
3127 * (where the OUI part needs to be nonzero for
3128 * the BSSID to be accepted by POST_SCAN).
3129 */
3130 bssid = "\x01\x00\x00\x00\x00\x00";
a94cc97e 3131 if (priv->vif != NULL)
0a11dfc3 3132 bssid = priv->vif->bss_conf.bssid;
a94cc97e 3133
e6935ea1 3134 mwl8k_cmd_set_post_scan(hw, bssid);
a66098da
LB		 3135 }
3136 }
3137
447ced07
LB		 3138 /*
3139 * If FIF_ALLMULTI is being requested, throw away the command
3140 * packet that ->prepare_multicast() built and replace it with
3141 * a command packet that enables reception of all multicast
3142 * packets.
3143 */
3144 if (*total_flags & FIF_ALLMULTI) {
3145 kfree(cmd);
3146 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, 0, NULL);
3147 }
3148
3149 if (cmd != NULL) {
3150 mwl8k_post_cmd(hw, cmd);
3151 kfree(cmd);
e6935ea1 3152 }
a66098da 3153
e6935ea1 3154 mwl8k_fw_unlock(hw);
a66098da
LB		 3155}
3156
a66098da
LB		 3157static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
3158{
55489b6e 3159 return mwl8k_cmd_set_rts_threshold(hw, MWL8K_CMD_SET, value);
a66098da
LB		 3160}
3161
bbfd9128
LB		 3162struct mwl8k_sta_notify_item
3163{
3164 struct list_head list;
3165 struct ieee80211_vif *vif;
3166 enum sta_notify_cmd cmd;
3167 u8 addr[ETH_ALEN];
c6e96010 3168 u32 legacy_rate_mask;
bbfd9128
LB		 3169};
3170
3171static void mwl8k_sta_notify_worker(struct work_struct *work)
3172{
3173 struct mwl8k_priv *priv =
3174 container_of(work, struct mwl8k_priv, sta_notify_worker);
a680400e 3175 struct ieee80211_hw *hw = priv->hw;
bbfd9128
LB		 3176
3177 spin_lock_bh(&priv->sta_notify_list_lock);
3178 while (!list_empty(&priv->sta_notify_list)) {
3179 struct mwl8k_sta_notify_item *s;
bbfd9128
LB		 3180
3181 s = list_entry(priv->sta_notify_list.next,
3182 struct mwl8k_sta_notify_item, list);
3183 list_del(&s->list);
3184
3185 spin_unlock_bh(&priv->sta_notify_list_lock);
3186
a680400e
LB		 3187 if (s->cmd == STA_NOTIFY_ADD) {
3188 int rc;
3189
c6e96010
LB		 3190 rc = mwl8k_cmd_update_stadb_add(hw, s->vif,
3191 s->addr, s->legacy_rate_mask);
a680400e
LB		 3192 if (rc >= 0) {
3193 struct ieee80211_sta *sta;
3194
3195 rcu_read_lock();
3196 sta = ieee80211_find_sta(s->vif, s->addr);
3197 if (sta != NULL)
3198 MWL8K_STA(sta)->peer_id = rc;
3199 rcu_read_unlock();
3200 }
3201 } else {
3202 mwl8k_cmd_update_stadb_del(hw, s->vif, s->addr);
3203 }
bbfd9128
LB		 3204
3205 kfree(s);
3206
3207 spin_lock_bh(&priv->sta_notify_list_lock);
3208 }
3209 spin_unlock_bh(&priv->sta_notify_list_lock);
3210}
3211
3212static void
3213mwl8k_sta_notify(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3214 enum sta_notify_cmd cmd, struct ieee80211_sta *sta)
3215{
3216 struct mwl8k_priv *priv = hw->priv;
3217 struct mwl8k_sta_notify_item *s;
3218
3219 if (cmd != STA_NOTIFY_ADD && cmd != STA_NOTIFY_REMOVE)
3220 return;
3221
3222 s = kmalloc(sizeof(*s), GFP_ATOMIC);
3223 if (s != NULL) {
3224 s->vif = vif;
3225 s->cmd = cmd;
3226 memcpy(s->addr, sta->addr, ETH_ALEN);
c6e96010 3227 s->legacy_rate_mask = sta->supp_rates[IEEE80211_BAND_2GHZ];
bbfd9128
LB		 3228
3229 spin_lock(&priv->sta_notify_list_lock);
3230 list_add_tail(&s->list, &priv->sta_notify_list);
3231 spin_unlock(&priv->sta_notify_list_lock);
3232
3233 ieee80211_queue_work(hw, &priv->sta_notify_worker);
3234 }
3235}
3236
a66098da
LB		 3237static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue,
3238 const struct ieee80211_tx_queue_params *params)
3239{
3e4f542c 3240 struct mwl8k_priv *priv = hw->priv;
a66098da 3241 int rc;
a66098da 3242
3e4f542c
LB		 3243 rc = mwl8k_fw_lock(hw);
3244 if (!rc) {
3245 if (!priv->wmm_enabled)
55489b6e 3246 rc = mwl8k_cmd_set_wmm_mode(hw, 1);
a66098da 3247
3e4f542c 3248 if (!rc)
55489b6e
LB		 3249 rc = mwl8k_cmd_set_edca_params(hw, queue,
3250 params->cw_min,
3251 params->cw_max,
3252 params->aifs,
3253 params->txop);
3e4f542c
LB		 3254
3255 mwl8k_fw_unlock(hw);
a66098da 3256 }
3e4f542c 3257
a66098da
LB		 3258 return rc;
3259}
3260
3261static int mwl8k_get_tx_stats(struct ieee80211_hw *hw,
3262 struct ieee80211_tx_queue_stats *stats)
3263{
3264 struct mwl8k_priv *priv = hw->priv;
3265 struct mwl8k_tx_queue *txq;
3266 int index;
3267
3268 spin_lock_bh(&priv->tx_lock);
3269 for (index = 0; index < MWL8K_TX_QUEUES; index++) {
3270 txq = priv->txq + index;
45eb400d 3271 memcpy(&stats[index], &txq->stats,
a66098da
LB		 3272 sizeof(struct ieee80211_tx_queue_stats));
3273 }
3274 spin_unlock_bh(&priv->tx_lock);
a66098da 3275
954ef509 3276 return 0;
a66098da
LB		 3277}
3278
3279static int mwl8k_get_stats(struct ieee80211_hw *hw,
3280 struct ieee80211_low_level_stats *stats)
3281{
55489b6e 3282 return mwl8k_cmd_get_stat(hw, stats);
a66098da
LB		 3283}
3284
3285static const struct ieee80211_ops mwl8k_ops = {
3286 .tx = mwl8k_tx,
3287 .start = mwl8k_start,
3288 .stop = mwl8k_stop,
3289 .add_interface = mwl8k_add_interface,
3290 .remove_interface = mwl8k_remove_interface,
3291 .config = mwl8k_config,
a66098da 3292 .bss_info_changed = mwl8k_bss_info_changed,
3ac64bee 3293 .prepare_multicast = mwl8k_prepare_multicast,
a66098da
LB		 3294 .configure_filter = mwl8k_configure_filter,
3295 .set_rts_threshold = mwl8k_set_rts_threshold,
bbfd9128 3296 .sta_notify = mwl8k_sta_notify,
a66098da
LB		 3297 .conf_tx = mwl8k_conf_tx,
3298 .get_tx_stats = mwl8k_get_tx_stats,
3299 .get_stats = mwl8k_get_stats,
3300};
3301
3302static void mwl8k_tx_reclaim_handler(unsigned long data)
3303{
3304 int i;
3305 struct ieee80211_hw *hw = (struct ieee80211_hw *) data;
3306 struct mwl8k_priv *priv = hw->priv;
3307
3308 spin_lock_bh(&priv->tx_lock);
3309 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3310 mwl8k_txq_reclaim(hw, i, 0);
3311
88de754a 3312 if (priv->tx_wait != NULL && !priv->pending_tx_pkts) {
ce9e2e1b
LB		 3313 complete(priv->tx_wait);
3314 priv->tx_wait = NULL;
a66098da
LB		 3315 }
3316 spin_unlock_bh(&priv->tx_lock);
3317}
3318
3319static void mwl8k_finalize_join_worker(struct work_struct *work)
3320{
3321 struct mwl8k_priv *priv =
3322 container_of(work, struct mwl8k_priv, finalize_join_worker);
3323 struct sk_buff *skb = priv->beacon_skb;
a66098da 3324
7dc6a7a7
LB		 3325 mwl8k_cmd_finalize_join(priv->hw, skb->data, skb->len,
3326 priv->vif->bss_conf.dtim_period);
a66098da
LB		 3327 dev_kfree_skb(skb);
3328
3329 priv->beacon_skb = NULL;
3330}
3331
bcb628d5
JL		 3332enum {
3333 MWL8687 = 0,
3334 MWL8366,
6f6d1e9a
LB		 3335};
3336
bcb628d5 3337static struct mwl8k_device_info mwl8k_info_tbl[] __devinitdata = {
49eb691c 3338 [MWL8687] = {
bcb628d5
JL		 3339 .part_name = "88w8687",
3340 .helper_image = "mwl8k/helper_8687.fw",
3341 .fw_image = "mwl8k/fmimage_8687.fw",
bcb628d5 3342 },
49eb691c 3343 [MWL8366] = {
bcb628d5
JL		 3344 .part_name = "88w8366",
3345 .helper_image = "mwl8k/helper_8366.fw",
3346 .fw_image = "mwl8k/fmimage_8366.fw",
89a91f4f 3347 .ap_rxd_ops = &rxd_8366_ap_ops,
bcb628d5 3348 },
45a390dd
LB		 3349};
3350
3351static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = {
bcb628d5
JL		 3352 { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = MWL8687, },
3353 { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = MWL8687, },
3354 { PCI_VDEVICE(MARVELL, 0x2a40), .driver_data = MWL8366, },
3355 { },
45a390dd
LB		 3356};
3357MODULE_DEVICE_TABLE(pci, mwl8k_pci_id_table);
3358
a66098da
LB		 3359static int __devinit mwl8k_probe(struct pci_dev *pdev,
3360 const struct pci_device_id *id)
3361{
2aa7b01f 3362 static int printed_version = 0;
a66098da
LB		 3363 struct ieee80211_hw *hw;
3364 struct mwl8k_priv *priv;
a66098da
LB		 3365 int rc;
3366 int i;
2aa7b01f
LB		 3367
3368 if (!printed_version) {
3369 printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
3370 printed_version = 1;
3371 }
a66098da 3372
be695fc4 3373
a66098da
LB		 3374 rc = pci_enable_device(pdev);
3375 if (rc) {
3376 printk(KERN_ERR "%s: Cannot enable new PCI device\n",
3377 MWL8K_NAME);
3378 return rc;
3379 }
3380
3381 rc = pci_request_regions(pdev, MWL8K_NAME);
3382 if (rc) {
3383 printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
3384 MWL8K_NAME);
3db95e50 3385 goto err_disable_device;
a66098da
LB		 3386 }
3387
3388 pci_set_master(pdev);
3389
be695fc4 3390
a66098da
LB		 3391 hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
3392 if (hw == NULL) {
3393 printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
3394 rc = -ENOMEM;
3395 goto err_free_reg;
3396 }
3397
be695fc4
LB		 3398 SET_IEEE80211_DEV(hw, &pdev->dev);
3399 pci_set_drvdata(pdev, hw);
3400
a66098da
LB		 3401 priv = hw->priv;
3402 priv->hw = hw;
3403 priv->pdev = pdev;
bcb628d5 3404 priv->device_info = &mwl8k_info_tbl[id->driver_data];
a66098da 3405
a66098da 3406
5b9482dd
LB		 3407 priv->sram = pci_iomap(pdev, 0, 0x10000);
3408 if (priv->sram == NULL) {
3409 printk(KERN_ERR "%s: Cannot map device SRAM\n",
c2c357ce 3410 wiphy_name(hw->wiphy));
a66098da
LB		 3411 goto err_iounmap;
3412 }
3413
5b9482dd
LB		 3414 /*
3415 * If BAR0 is a 32 bit BAR, the register BAR will be BAR1.
3416 * If BAR0 is a 64 bit BAR, the register BAR will be BAR2.
3417 */
3418 priv->regs = pci_iomap(pdev, 1, 0x10000);
3419 if (priv->regs == NULL) {
3420 priv->regs = pci_iomap(pdev, 2, 0x10000);
3421 if (priv->regs == NULL) {
3422 printk(KERN_ERR "%s: Cannot map device registers\n",
3423 wiphy_name(hw->wiphy));
3424 goto err_iounmap;
3425 }
3426 }
3427
be695fc4
LB		 3428
3429 /* Reset firmware and hardware */
3430 mwl8k_hw_reset(priv);
3431
3432 /* Ask userland hotplug daemon for the device firmware */
3433 rc = mwl8k_request_firmware(priv);
3434 if (rc) {
3435 printk(KERN_ERR "%s: Firmware files not found\n",
3436 wiphy_name(hw->wiphy));
3437 goto err_stop_firmware;
3438 }
3439
3440 /* Load firmware into hardware */
3441 rc = mwl8k_load_firmware(hw);
3442 if (rc) {
3443 printk(KERN_ERR "%s: Cannot start firmware\n",
3444 wiphy_name(hw->wiphy));
3445 goto err_stop_firmware;
3446 }
3447
3448 /* Reclaim memory once firmware is successfully loaded */
3449 mwl8k_release_firmware(priv);
3450
3451
91942230 3452 if (priv->ap_fw) {
89a91f4f 3453 priv->rxd_ops = priv->device_info->ap_rxd_ops;
91942230
LB		 3454 if (priv->rxd_ops == NULL) {
3455 printk(KERN_ERR "%s: Driver does not have AP "
3456 "firmware image support for this hardware\n",
3457 wiphy_name(hw->wiphy));
3458 goto err_stop_firmware;
3459 }
3460 } else {
89a91f4f 3461 priv->rxd_ops = &rxd_sta_ops;
91942230 3462 }
be695fc4
LB		 3463
3464 priv->sniffer_enabled = false;
3465 priv->wmm_enabled = false;
3466 priv->pending_tx_pkts = 0;
3467
3468
a66098da
LB		 3469 memcpy(priv->channels, mwl8k_channels, sizeof(mwl8k_channels));
3470 priv->band.band = IEEE80211_BAND_2GHZ;
3471 priv->band.channels = priv->channels;
3472 priv->band.n_channels = ARRAY_SIZE(mwl8k_channels);
3473 priv->band.bitrates = priv->rates;
3474 priv->band.n_bitrates = ARRAY_SIZE(mwl8k_rates);
3475 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
3476
3477 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(mwl8k_rates));
3478 memcpy(priv->rates, mwl8k_rates, sizeof(mwl8k_rates));
3479
3480 /*
3481 * Extra headroom is the size of the required DMA header
3482 * minus the size of the smallest 802.11 frame (CTS frame).
3483 */
3484 hw->extra_tx_headroom =
3485 sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
3486
3487 hw->channel_change_time = 10;
3488
3489 hw->queues = MWL8K_TX_QUEUES;
3490
a66098da 3491 /* Set rssi and noise values to dBm */
ce9e2e1b 3492 hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM;
a66098da 3493 hw->vif_data_size = sizeof(struct mwl8k_vif);
a680400e 3494 hw->sta_data_size = sizeof(struct mwl8k_sta);
a66098da
LB		 3495 priv->vif = NULL;
3496
3497 /* Set default radio state and preamble */
c46563b7 3498 priv->radio_on = 0;
68ce3884 3499 priv->radio_short_preamble = 0;
a66098da 3500
bbfd9128
LB		 3501 /* Station database handling */
3502 INIT_WORK(&priv->sta_notify_worker, mwl8k_sta_notify_worker);
3503 spin_lock_init(&priv->sta_notify_list_lock);
3504 INIT_LIST_HEAD(&priv->sta_notify_list);
3505
a66098da
LB		 3506 /* Finalize join worker */
3507 INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
3508
3509 /* TX reclaim tasklet */
3510 tasklet_init(&priv->tx_reclaim_task,
3511 mwl8k_tx_reclaim_handler, (unsigned long)hw);
3512 tasklet_disable(&priv->tx_reclaim_task);
3513
a66098da
LB		 3514 /* Power management cookie */
3515 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
3516 if (priv->cookie == NULL)
be695fc4 3517 goto err_stop_firmware;
a66098da
LB		 3518
3519 rc = mwl8k_rxq_init(hw, 0);
3520 if (rc)
be695fc4 3521 goto err_free_cookie;
a66098da
LB		 3522 rxq_refill(hw, 0, INT_MAX);
3523
618952a7
LB		 3524 mutex_init(&priv->fw_mutex);
3525 priv->fw_mutex_owner = NULL;
3526 priv->fw_mutex_depth = 0;
618952a7
LB		 3527 priv->hostcmd_wait = NULL;
3528
a66098da
LB		 3529 spin_lock_init(&priv->tx_lock);
3530
88de754a
LB		 3531 priv->tx_wait = NULL;
3532
a66098da
LB		 3533 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
3534 rc = mwl8k_txq_init(hw, i);
3535 if (rc)
3536 goto err_free_queues;
3537 }
3538
3539 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
c23b5a69 3540 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3541 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
3542 iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
3543
a0607fd3 3544 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
a66098da
LB		 3545 IRQF_SHARED, MWL8K_NAME, hw);
3546 if (rc) {
3547 printk(KERN_ERR "%s: failed to register IRQ handler\n",
c2c357ce 3548 wiphy_name(hw->wiphy));
a66098da
LB		 3549 goto err_free_queues;
3550 }
3551
a66098da
LB		 3552 /*
3553 * Temporarily enable interrupts. Initial firmware host
3554 * commands use interrupts and avoids polling. Disable
3555 * interrupts when done.
3556 */
c23b5a69 3557 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3558
3559 /* Get config data, mac addrs etc */
42fba21d
LB		 3560 if (priv->ap_fw) {
3561 rc = mwl8k_cmd_get_hw_spec_ap(hw);
3562 if (!rc)
3563 rc = mwl8k_cmd_set_hw_spec(hw);
3564 } else {
3565 rc = mwl8k_cmd_get_hw_spec_sta(hw);
89a91f4f
LB		 3566
3567 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
42fba21d 3568 }
a66098da 3569 if (rc) {
c2c357ce
LB		 3570 printk(KERN_ERR "%s: Cannot initialise firmware\n",
3571 wiphy_name(hw->wiphy));
be695fc4 3572 goto err_free_irq;
a66098da
LB		 3573 }
3574
3575 /* Turn radio off */
55489b6e 3576 rc = mwl8k_cmd_radio_disable(hw);
a66098da 3577 if (rc) {
c2c357ce 3578 printk(KERN_ERR "%s: Cannot disable\n", wiphy_name(hw->wiphy));
be695fc4 3579 goto err_free_irq;
a66098da
LB		 3580 }
3581
32060e1b 3582 /* Clear MAC address */
55489b6e 3583 rc = mwl8k_cmd_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
32060e1b
LB		 3584 if (rc) {
3585 printk(KERN_ERR "%s: Cannot clear MAC address\n",
3586 wiphy_name(hw->wiphy));
be695fc4 3587 goto err_free_irq;
32060e1b
LB		 3588 }
3589
a66098da 3590 /* Disable interrupts */
a66098da 3591 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3592 free_irq(priv->pdev->irq, hw);
3593
3594 rc = ieee80211_register_hw(hw);
3595 if (rc) {
c2c357ce
LB		 3596 printk(KERN_ERR "%s: Cannot register device\n",
3597 wiphy_name(hw->wiphy));
153458ff 3598 goto err_free_queues;
a66098da
LB		 3599 }
3600
eae74e65 3601 printk(KERN_INFO "%s: %s v%d, %pM, %s firmware %u.%u.%u.%u\n",
a74b295e 3602 wiphy_name(hw->wiphy), priv->device_info->part_name,
45a390dd 3603 priv->hw_rev, hw->wiphy->perm_addr,
eae74e65 3604 priv->ap_fw ? "AP" : "STA",
2aa7b01f
LB		 3605 (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff,
3606 (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff);
a66098da
LB		 3607
3608 return 0;
3609
a66098da 3610err_free_irq:
a66098da 3611 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3612 free_irq(priv->pdev->irq, hw);
3613
3614err_free_queues:
3615 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3616 mwl8k_txq_deinit(hw, i);
3617 mwl8k_rxq_deinit(hw, 0);
3618
be695fc4 3619err_free_cookie:
a66098da
LB		 3620 if (priv->cookie != NULL)
3621 pci_free_consistent(priv->pdev, 4,
3622 priv->cookie, priv->cookie_dma);
3623
be695fc4
LB		 3624err_stop_firmware:
3625 mwl8k_hw_reset(priv);
3626 mwl8k_release_firmware(priv);
3627
3628err_iounmap:
a66098da
LB		 3629 if (priv->regs != NULL)
3630 pci_iounmap(pdev, priv->regs);
3631
5b9482dd
LB		 3632 if (priv->sram != NULL)
3633 pci_iounmap(pdev, priv->sram);
3634
a66098da
LB		 3635 pci_set_drvdata(pdev, NULL);
3636 ieee80211_free_hw(hw);
3637
3638err_free_reg:
3639 pci_release_regions(pdev);
3db95e50
LB		 3640
3641err_disable_device:
a66098da
LB		 3642 pci_disable_device(pdev);
3643
3644 return rc;
3645}
3646
230f7af0 3647static void __devexit mwl8k_shutdown(struct pci_dev *pdev)
a66098da
LB		 3648{
3649 printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__);
3650}
3651
230f7af0 3652static void __devexit mwl8k_remove(struct pci_dev *pdev)
a66098da
LB		 3653{
3654 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
3655 struct mwl8k_priv *priv;
3656 int i;
3657
3658 if (hw == NULL)
3659 return;
3660 priv = hw->priv;
3661
3662 ieee80211_stop_queues(hw);
3663
60aa569f
LB		 3664 ieee80211_unregister_hw(hw);
3665
a66098da
LB		 3666 /* Remove tx reclaim tasklet */
3667 tasklet_kill(&priv->tx_reclaim_task);
3668
a66098da
LB		 3669 /* Stop hardware */
3670 mwl8k_hw_reset(priv);
3671
3672 /* Return all skbs to mac80211 */
3673 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3674 mwl8k_txq_reclaim(hw, i, 1);
3675
a66098da
LB		 3676 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3677 mwl8k_txq_deinit(hw, i);
3678
3679 mwl8k_rxq_deinit(hw, 0);
3680
c2c357ce 3681 pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma);
a66098da
LB		 3682
3683 pci_iounmap(pdev, priv->regs);
5b9482dd 3684 pci_iounmap(pdev, priv->sram);
a66098da
LB		 3685 pci_set_drvdata(pdev, NULL);
3686 ieee80211_free_hw(hw);
3687 pci_release_regions(pdev);
3688 pci_disable_device(pdev);
3689}
3690
3691static struct pci_driver mwl8k_driver = {
3692 .name = MWL8K_NAME,
45a390dd 3693 .id_table = mwl8k_pci_id_table,
a66098da
LB		 3694 .probe = mwl8k_probe,
3695 .remove = __devexit_p(mwl8k_remove),
3696 .shutdown = __devexit_p(mwl8k_shutdown),
3697};
3698
3699static int __init mwl8k_init(void)
3700{
3701 return pci_register_driver(&mwl8k_driver);
3702}
3703
3704static void __exit mwl8k_exit(void)
3705{
3706 pci_unregister_driver(&mwl8k_driver);
3707}
3708
3709module_init(mwl8k_init);
3710module_exit(mwl8k_exit);
c2c357ce
LB		 3711
3712MODULE_DESCRIPTION(MWL8K_DESC);
3713MODULE_VERSION(MWL8K_VERSION);
3714MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
3715MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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