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mwl8k: update MODULE_FIRMWARE tags
[deliverable/linux.git] / drivers / net / wireless / mwl8k.c
CommitLineData
a66098da 1/*
ce9e2e1b
LB		 2 * drivers/net/wireless/mwl8k.c
3 * Driver for Marvell TOPDOG 802.11 Wireless cards
a66098da 4 *
a145d575 5 * Copyright (C) 2008-2009 Marvell Semiconductor Inc.
a66098da
LB		 6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
3d76e82c 15#include <linux/sched.h>
a66098da
LB		 16#include <linux/spinlock.h>
17#include <linux/list.h>
18#include <linux/pci.h>
19#include <linux/delay.h>
20#include <linux/completion.h>
21#include <linux/etherdevice.h>
22#include <net/mac80211.h>
23#include <linux/moduleparam.h>
24#include <linux/firmware.h>
25#include <linux/workqueue.h>
26
27#define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
28#define MWL8K_NAME KBUILD_MODNAME
6976b665 29#define MWL8K_VERSION "0.11"
a66098da 30
a66098da
LB		 31/* Register definitions */
32#define MWL8K_HIU_GEN_PTR 0x00000c10
ce9e2e1b
LB		 33#define MWL8K_MODE_STA 0x0000005a
34#define MWL8K_MODE_AP 0x000000a5
a66098da 35#define MWL8K_HIU_INT_CODE 0x00000c14
ce9e2e1b
LB		 36#define MWL8K_FWSTA_READY 0xf0f1f2f4
37#define MWL8K_FWAP_READY 0xf1f2f4a5
38#define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
a66098da
LB		 39#define MWL8K_HIU_SCRATCH 0x00000c40
40
41/* Host->device communications */
42#define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
43#define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
44#define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
45#define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
46#define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
ce9e2e1b
LB		 47#define MWL8K_H2A_INT_DUMMY (1 << 20)
48#define MWL8K_H2A_INT_RESET (1 << 15)
49#define MWL8K_H2A_INT_DOORBELL (1 << 1)
50#define MWL8K_H2A_INT_PPA_READY (1 << 0)
a66098da
LB		 51
52/* Device->host communications */
53#define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
54#define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
55#define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
56#define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
57#define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
ce9e2e1b
LB		 58#define MWL8K_A2H_INT_DUMMY (1 << 20)
59#define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
60#define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
61#define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
62#define MWL8K_A2H_INT_RADIO_ON (1 << 6)
63#define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
64#define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
65#define MWL8K_A2H_INT_OPC_DONE (1 << 2)
66#define MWL8K_A2H_INT_RX_READY (1 << 1)
67#define MWL8K_A2H_INT_TX_DONE (1 << 0)
a66098da
LB		 68
69#define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
70 MWL8K_A2H_INT_CHNL_SWITCHED | \
71 MWL8K_A2H_INT_QUEUE_EMPTY | \
72 MWL8K_A2H_INT_RADAR_DETECT | \
73 MWL8K_A2H_INT_RADIO_ON | \
74 MWL8K_A2H_INT_RADIO_OFF | \
75 MWL8K_A2H_INT_MAC_EVENT | \
76 MWL8K_A2H_INT_OPC_DONE | \
77 MWL8K_A2H_INT_RX_READY | \
78 MWL8K_A2H_INT_TX_DONE)
79
a66098da
LB		 80#define MWL8K_RX_QUEUES 1
81#define MWL8K_TX_QUEUES 4
82
54bc3a0d
LB		 83struct rxd_ops {
84 int rxd_size;
85 void (*rxd_init)(void *rxd, dma_addr_t next_dma_addr);
86 void (*rxd_refill)(void *rxd, dma_addr_t addr, int len);
20f09c3d
LB		 87 int (*rxd_process)(void *rxd, struct ieee80211_rx_status *status,
88 __le16 *qos);
54bc3a0d
LB		 89};
90
45a390dd 91struct mwl8k_device_info {
a74b295e
LB		 92 char *part_name;
93 char *helper_image;
94 char *fw_image;
89a91f4f 95 struct rxd_ops *ap_rxd_ops;
45a390dd
LB		 96};
97
a66098da 98struct mwl8k_rx_queue {
45eb400d 99 int rxd_count;
a66098da
LB		 100
101 /* hw receives here */
45eb400d 102 int head;
a66098da
LB		 103
104 /* refill descs here */
45eb400d 105 int tail;
a66098da 106
54bc3a0d 107 void *rxd;
45eb400d 108 dma_addr_t rxd_dma;
788838eb
LB		 109 struct {
110 struct sk_buff *skb;
111 DECLARE_PCI_UNMAP_ADDR(dma)
112 } *buf;
a66098da
LB		 113};
114
a66098da
LB		 115struct mwl8k_tx_queue {
116 /* hw transmits here */
45eb400d 117 int head;
a66098da
LB		 118
119 /* sw appends here */
45eb400d 120 int tail;
a66098da 121
45eb400d
LB		 122 struct ieee80211_tx_queue_stats stats;
123 struct mwl8k_tx_desc *txd;
124 dma_addr_t txd_dma;
125 struct sk_buff **skb;
a66098da
LB		 126};
127
a66098da 128struct mwl8k_priv {
a66098da 129 struct ieee80211_hw *hw;
a66098da 130 struct pci_dev *pdev;
a66098da 131
45a390dd
LB		 132 struct mwl8k_device_info *device_info;
133
be695fc4
LB		 134 void __iomem *sram;
135 void __iomem *regs;
136
137 /* firmware */
22be40d9
LB		 138 struct firmware *fw_helper;
139 struct firmware *fw_ucode;
a66098da 140
be695fc4
LB		 141 /* hardware/firmware parameters */
142 bool ap_fw;
143 struct rxd_ops *rxd_ops;
144
618952a7
LB		 145 /* firmware access */
146 struct mutex fw_mutex;
147 struct task_struct *fw_mutex_owner;
148 int fw_mutex_depth;
618952a7
LB		 149 struct completion *hostcmd_wait;
150
a66098da
LB		 151 /* lock held over TX and TX reap */
152 spinlock_t tx_lock;
a66098da 153
88de754a
LB		 154 /* TX quiesce completion, protected by fw_mutex and tx_lock */
155 struct completion *tx_wait;
156
a66098da 157 struct ieee80211_vif *vif;
a66098da
LB		 158
159 struct ieee80211_channel *current_channel;
160
161 /* power management status cookie from firmware */
162 u32 *cookie;
163 dma_addr_t cookie_dma;
164
165 u16 num_mcaddrs;
a66098da 166 u8 hw_rev;
2aa7b01f 167 u32 fw_rev;
a66098da
LB		 168
169 /*
170 * Running count of TX packets in flight, to avoid
171 * iterating over the transmit rings each time.
172 */
173 int pending_tx_pkts;
174
175 struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
176 struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES];
177
178 /* PHY parameters */
179 struct ieee80211_supported_band band;
180 struct ieee80211_channel channels[14];
140eb5e2 181 struct ieee80211_rate rates[14];
a66098da 182
c46563b7 183 bool radio_on;
68ce3884 184 bool radio_short_preamble;
a43c49a8 185 bool sniffer_enabled;
0439b1f5 186 bool wmm_enabled;
a66098da 187
bbfd9128
LB		 188 struct work_struct sta_notify_worker;
189 spinlock_t sta_notify_list_lock;
190 struct list_head sta_notify_list;
191
a66098da
LB		 192 /* XXX need to convert this to handle multiple interfaces */
193 bool capture_beacon;
d89173f2 194 u8 capture_bssid[ETH_ALEN];
a66098da
LB		 195 struct sk_buff *beacon_skb;
196
197 /*
198 * This FJ worker has to be global as it is scheduled from the
199 * RX handler. At this point we don't know which interface it
200 * belongs to until the list of bssids waiting to complete join
201 * is checked.
202 */
203 struct work_struct finalize_join_worker;
204
1e9f9de3
LB		 205 /* Tasklet to perform TX reclaim. */
206 struct tasklet_struct poll_tx_task;
67e2eb27
LB		 207
208 /* Tasklet to perform RX. */
209 struct tasklet_struct poll_rx_task;
a66098da
LB		 210};
211
212/* Per interface specific private data */
213struct mwl8k_vif {
c2c2b12a 214 /* Non AMPDU sequence number assigned by driver. */
a680400e 215 u16 seqno;
a66098da 216};
a94cc97e 217#define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
a66098da 218
a680400e
LB		 219struct mwl8k_sta {
220 /* Index into station database. Returned by UPDATE_STADB. */
221 u8 peer_id;
222};
223#define MWL8K_STA(_sta) ((struct mwl8k_sta *)&((_sta)->drv_priv))
224
a66098da
LB		 225static const struct ieee80211_channel mwl8k_channels[] = {
226 { .center_freq = 2412, .hw_value = 1, },
227 { .center_freq = 2417, .hw_value = 2, },
228 { .center_freq = 2422, .hw_value = 3, },
229 { .center_freq = 2427, .hw_value = 4, },
230 { .center_freq = 2432, .hw_value = 5, },
231 { .center_freq = 2437, .hw_value = 6, },
232 { .center_freq = 2442, .hw_value = 7, },
233 { .center_freq = 2447, .hw_value = 8, },
234 { .center_freq = 2452, .hw_value = 9, },
235 { .center_freq = 2457, .hw_value = 10, },
236 { .center_freq = 2462, .hw_value = 11, },
647ca6b0
LB		 237 { .center_freq = 2467, .hw_value = 12, },
238 { .center_freq = 2472, .hw_value = 13, },
239 { .center_freq = 2484, .hw_value = 14, },
a66098da
LB		 240};
241
242static const struct ieee80211_rate mwl8k_rates[] = {
243 { .bitrate = 10, .hw_value = 2, },
244 { .bitrate = 20, .hw_value = 4, },
245 { .bitrate = 55, .hw_value = 11, },
5dfd3e2c
LB		 246 { .bitrate = 110, .hw_value = 22, },
247 { .bitrate = 220, .hw_value = 44, },
a66098da
LB		 248 { .bitrate = 60, .hw_value = 12, },
249 { .bitrate = 90, .hw_value = 18, },
a66098da
LB		 250 { .bitrate = 120, .hw_value = 24, },
251 { .bitrate = 180, .hw_value = 36, },
252 { .bitrate = 240, .hw_value = 48, },
253 { .bitrate = 360, .hw_value = 72, },
254 { .bitrate = 480, .hw_value = 96, },
255 { .bitrate = 540, .hw_value = 108, },
140eb5e2
LB		 256 { .bitrate = 720, .hw_value = 144, },
257};
258
a66098da
LB		 259/* Set or get info from Firmware */
260#define MWL8K_CMD_SET 0x0001
261#define MWL8K_CMD_GET 0x0000
262
263/* Firmware command codes */
264#define MWL8K_CMD_CODE_DNLD 0x0001
265#define MWL8K_CMD_GET_HW_SPEC 0x0003
42fba21d 266#define MWL8K_CMD_SET_HW_SPEC 0x0004
a66098da
LB		 267#define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
268#define MWL8K_CMD_GET_STAT 0x0014
ff45fc60
LB		 269#define MWL8K_CMD_RADIO_CONTROL 0x001c
270#define MWL8K_CMD_RF_TX_POWER 0x001e
08b06347 271#define MWL8K_CMD_RF_ANTENNA 0x0020
b64fe619 272#define MWL8K_CMD_SET_BEACON 0x0100
a66098da
LB		 273#define MWL8K_CMD_SET_PRE_SCAN 0x0107
274#define MWL8K_CMD_SET_POST_SCAN 0x0108
ff45fc60
LB		 275#define MWL8K_CMD_SET_RF_CHANNEL 0x010a
276#define MWL8K_CMD_SET_AID 0x010d
277#define MWL8K_CMD_SET_RATE 0x0110
278#define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
279#define MWL8K_CMD_RTS_THRESHOLD 0x0113
a66098da 280#define MWL8K_CMD_SET_SLOT 0x0114
ff45fc60
LB		 281#define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
282#define MWL8K_CMD_SET_WMM_MODE 0x0123
a66098da 283#define MWL8K_CMD_MIMO_CONFIG 0x0125
ff45fc60 284#define MWL8K_CMD_USE_FIXED_RATE 0x0126
a66098da 285#define MWL8K_CMD_ENABLE_SNIFFER 0x0150
32060e1b 286#define MWL8K_CMD_SET_MAC_ADDR 0x0202
a66098da 287#define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
b64fe619 288#define MWL8K_CMD_BSS_START 0x1100
3f5610ff 289#define MWL8K_CMD_SET_NEW_STN 0x1111
ff45fc60 290#define MWL8K_CMD_UPDATE_STADB 0x1123
a66098da
LB		 291
292static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize)
293{
294#define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
295 snprintf(buf, bufsize, "%s", #x);\
296 return buf;\
297 } while (0)
ce9e2e1b 298 switch (cmd & ~0x8000) {
a66098da
LB		 299 MWL8K_CMDNAME(CODE_DNLD);
300 MWL8K_CMDNAME(GET_HW_SPEC);
42fba21d 301 MWL8K_CMDNAME(SET_HW_SPEC);
a66098da
LB		 302 MWL8K_CMDNAME(MAC_MULTICAST_ADR);
303 MWL8K_CMDNAME(GET_STAT);
304 MWL8K_CMDNAME(RADIO_CONTROL);
305 MWL8K_CMDNAME(RF_TX_POWER);
08b06347 306 MWL8K_CMDNAME(RF_ANTENNA);
b64fe619 307 MWL8K_CMDNAME(SET_BEACON);
a66098da
LB		 308 MWL8K_CMDNAME(SET_PRE_SCAN);
309 MWL8K_CMDNAME(SET_POST_SCAN);
310 MWL8K_CMDNAME(SET_RF_CHANNEL);
ff45fc60
LB		 311 MWL8K_CMDNAME(SET_AID);
312 MWL8K_CMDNAME(SET_RATE);
313 MWL8K_CMDNAME(SET_FINALIZE_JOIN);
314 MWL8K_CMDNAME(RTS_THRESHOLD);
a66098da 315 MWL8K_CMDNAME(SET_SLOT);
ff45fc60
LB		 316 MWL8K_CMDNAME(SET_EDCA_PARAMS);
317 MWL8K_CMDNAME(SET_WMM_MODE);
a66098da 318 MWL8K_CMDNAME(MIMO_CONFIG);
ff45fc60 319 MWL8K_CMDNAME(USE_FIXED_RATE);
a66098da 320 MWL8K_CMDNAME(ENABLE_SNIFFER);
32060e1b 321 MWL8K_CMDNAME(SET_MAC_ADDR);
a66098da 322 MWL8K_CMDNAME(SET_RATEADAPT_MODE);
b64fe619 323 MWL8K_CMDNAME(BSS_START);
3f5610ff 324 MWL8K_CMDNAME(SET_NEW_STN);
ff45fc60 325 MWL8K_CMDNAME(UPDATE_STADB);
a66098da
LB		 326 default:
327 snprintf(buf, bufsize, "0x%x", cmd);
328 }
329#undef MWL8K_CMDNAME
330
331 return buf;
332}
333
334/* Hardware and firmware reset */
335static void mwl8k_hw_reset(struct mwl8k_priv *priv)
336{
337 iowrite32(MWL8K_H2A_INT_RESET,
338 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
339 iowrite32(MWL8K_H2A_INT_RESET,
340 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
341 msleep(20);
342}
343
344/* Release fw image */
345static void mwl8k_release_fw(struct firmware **fw)
346{
347 if (*fw == NULL)
348 return;
349 release_firmware(*fw);
350 *fw = NULL;
351}
352
353static void mwl8k_release_firmware(struct mwl8k_priv *priv)
354{
22be40d9
LB		 355 mwl8k_release_fw(&priv->fw_ucode);
356 mwl8k_release_fw(&priv->fw_helper);
a66098da
LB		 357}
358
359/* Request fw image */
360static int mwl8k_request_fw(struct mwl8k_priv *priv,
c2c357ce 361 const char *fname, struct firmware **fw)
a66098da
LB		 362{
363 /* release current image */
364 if (*fw != NULL)
365 mwl8k_release_fw(fw);
366
367 return request_firmware((const struct firmware **)fw,
c2c357ce 368 fname, &priv->pdev->dev);
a66098da
LB		 369}
370
45a390dd 371static int mwl8k_request_firmware(struct mwl8k_priv *priv)
a66098da 372{
a74b295e 373 struct mwl8k_device_info *di = priv->device_info;
a66098da
LB		 374 int rc;
375
a74b295e 376 if (di->helper_image != NULL) {
22be40d9 377 rc = mwl8k_request_fw(priv, di->helper_image, &priv->fw_helper);
a74b295e
LB		 378 if (rc) {
379 printk(KERN_ERR "%s: Error requesting helper "
380 "firmware file %s\n", pci_name(priv->pdev),
381 di->helper_image);
382 return rc;
383 }
a66098da
LB		 384 }
385
22be40d9 386 rc = mwl8k_request_fw(priv, di->fw_image, &priv->fw_ucode);
a66098da 387 if (rc) {
c2c357ce 388 printk(KERN_ERR "%s: Error requesting firmware file %s\n",
a74b295e 389 pci_name(priv->pdev), di->fw_image);
22be40d9 390 mwl8k_release_fw(&priv->fw_helper);
a66098da
LB		 391 return rc;
392 }
393
394 return 0;
395}
396
397struct mwl8k_cmd_pkt {
398 __le16 code;
399 __le16 length;
400 __le16 seq_num;
401 __le16 result;
402 char payload[0];
403} __attribute__((packed));
404
405/*
406 * Firmware loading.
407 */
408static int
409mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
410{
411 void __iomem *regs = priv->regs;
412 dma_addr_t dma_addr;
a66098da
LB		 413 int loops;
414
415 dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
416 if (pci_dma_mapping_error(priv->pdev, dma_addr))
417 return -ENOMEM;
418
419 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
420 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
421 iowrite32(MWL8K_H2A_INT_DOORBELL,
422 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
423 iowrite32(MWL8K_H2A_INT_DUMMY,
424 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
425
a66098da
LB		 426 loops = 1000;
427 do {
428 u32 int_code;
429
430 int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
431 if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
432 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
a66098da
LB		 433 break;
434 }
435
3d76e82c 436 cond_resched();
a66098da
LB		 437 udelay(1);
438 } while (--loops);
439
440 pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
441
d4b70570 442 return loops ? 0 : -ETIMEDOUT;
a66098da
LB		 443}
444
445static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
446 const u8 *data, size_t length)
447{
448 struct mwl8k_cmd_pkt *cmd;
449 int done;
450 int rc = 0;
451
452 cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
453 if (cmd == NULL)
454 return -ENOMEM;
455
456 cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
457 cmd->seq_num = 0;
458 cmd->result = 0;
459
460 done = 0;
461 while (length) {
462 int block_size = length > 256 ? 256 : length;
463
464 memcpy(cmd->payload, data + done, block_size);
465 cmd->length = cpu_to_le16(block_size);
466
467 rc = mwl8k_send_fw_load_cmd(priv, cmd,
468 sizeof(*cmd) + block_size);
469 if (rc)
470 break;
471
472 done += block_size;
473 length -= block_size;
474 }
475
476 if (!rc) {
477 cmd->length = 0;
478 rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
479 }
480
481 kfree(cmd);
482
483 return rc;
484}
485
486static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
487 const u8 *data, size_t length)
488{
489 unsigned char *buffer;
490 int may_continue, rc = 0;
491 u32 done, prev_block_size;
492
493 buffer = kmalloc(1024, GFP_KERNEL);
494 if (buffer == NULL)
495 return -ENOMEM;
496
497 done = 0;
498 prev_block_size = 0;
499 may_continue = 1000;
500 while (may_continue > 0) {
501 u32 block_size;
502
503 block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
504 if (block_size & 1) {
505 block_size &= ~1;
506 may_continue--;
507 } else {
508 done += prev_block_size;
509 length -= prev_block_size;
510 }
511
512 if (block_size > 1024 || block_size > length) {
513 rc = -EOVERFLOW;
514 break;
515 }
516
517 if (length == 0) {
518 rc = 0;
519 break;
520 }
521
522 if (block_size == 0) {
523 rc = -EPROTO;
524 may_continue--;
525 udelay(1);
526 continue;
527 }
528
529 prev_block_size = block_size;
530 memcpy(buffer, data + done, block_size);
531
532 rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
533 if (rc)
534 break;
535 }
536
537 if (!rc && length != 0)
538 rc = -EREMOTEIO;
539
540 kfree(buffer);
541
542 return rc;
543}
544
c2c357ce 545static int mwl8k_load_firmware(struct ieee80211_hw *hw)
a66098da 546{
c2c357ce 547 struct mwl8k_priv *priv = hw->priv;
22be40d9 548 struct firmware *fw = priv->fw_ucode;
c2c357ce
LB		 549 int rc;
550 int loops;
551
552 if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) {
22be40d9 553 struct firmware *helper = priv->fw_helper;
a66098da 554
c2c357ce
LB		 555 if (helper == NULL) {
556 printk(KERN_ERR "%s: helper image needed but none "
557 "given\n", pci_name(priv->pdev));
558 return -EINVAL;
559 }
a66098da 560
c2c357ce 561 rc = mwl8k_load_fw_image(priv, helper->data, helper->size);
a66098da
LB		 562 if (rc) {
563 printk(KERN_ERR "%s: unable to load firmware "
c2c357ce 564 "helper image\n", pci_name(priv->pdev));
a66098da
LB		 565 return rc;
566 }
89b872e2 567 msleep(5);
a66098da 568
c2c357ce 569 rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
a66098da 570 } else {
c2c357ce 571 rc = mwl8k_load_fw_image(priv, fw->data, fw->size);
a66098da
LB		 572 }
573
574 if (rc) {
c2c357ce
LB		 575 printk(KERN_ERR "%s: unable to load firmware image\n",
576 pci_name(priv->pdev));
a66098da
LB		 577 return rc;
578 }
579
89a91f4f 580 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
a66098da 581
89b872e2 582 loops = 500000;
a66098da 583 do {
eae74e65
LB		 584 u32 ready_code;
585
586 ready_code = ioread32(priv->regs + MWL8K_HIU_INT_CODE);
587 if (ready_code == MWL8K_FWAP_READY) {
588 priv->ap_fw = 1;
589 break;
590 } else if (ready_code == MWL8K_FWSTA_READY) {
591 priv->ap_fw = 0;
a66098da 592 break;
eae74e65
LB		 593 }
594
595 cond_resched();
a66098da
LB		 596 udelay(1);
597 } while (--loops);
598
599 return loops ? 0 : -ETIMEDOUT;
600}
601
602
a66098da
LB		 603/* DMA header used by firmware and hardware. */
604struct mwl8k_dma_data {
605 __le16 fwlen;
606 struct ieee80211_hdr wh;
20f09c3d 607 char data[0];
a66098da
LB		 608} __attribute__((packed));
609
610/* Routines to add/remove DMA header from skb. */
20f09c3d 611static inline void mwl8k_remove_dma_header(struct sk_buff *skb, __le16 qos)
a66098da 612{
20f09c3d
LB		 613 struct mwl8k_dma_data *tr;
614 int hdrlen;
615
616 tr = (struct mwl8k_dma_data *)skb->data;
617 hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
618
619 if (hdrlen != sizeof(tr->wh)) {
620 if (ieee80211_is_data_qos(tr->wh.frame_control)) {
621 memmove(tr->data - hdrlen, &tr->wh, hdrlen - 2);
622 *((__le16 *)(tr->data - 2)) = qos;
623 } else {
624 memmove(tr->data - hdrlen, &tr->wh, hdrlen);
625 }
a66098da 626 }
20f09c3d
LB		 627
628 if (hdrlen != sizeof(*tr))
629 skb_pull(skb, sizeof(*tr) - hdrlen);
a66098da
LB		 630}
631
76266b2a 632static inline void mwl8k_add_dma_header(struct sk_buff *skb)
a66098da
LB		 633{
634 struct ieee80211_hdr *wh;
ca009301 635 int hdrlen;
a66098da
LB		 636 struct mwl8k_dma_data *tr;
637
ca009301
LB		 638 /*
639 * Add a firmware DMA header; the firmware requires that we
640 * present a 2-byte payload length followed by a 4-address
641 * header (without QoS field), followed (optionally) by any
642 * WEP/ExtIV header (but only filled in for CCMP).
643 */
a66098da 644 wh = (struct ieee80211_hdr *)skb->data;
ca009301 645
a66098da 646 hdrlen = ieee80211_hdrlen(wh->frame_control);
ca009301
LB		 647 if (hdrlen != sizeof(*tr))
648 skb_push(skb, sizeof(*tr) - hdrlen);
a66098da 649
ca009301
LB		 650 if (ieee80211_is_data_qos(wh->frame_control))
651 hdrlen -= 2;
a66098da
LB		 652
653 tr = (struct mwl8k_dma_data *)skb->data;
654 if (wh != &tr->wh)
655 memmove(&tr->wh, wh, hdrlen);
ca009301
LB		 656 if (hdrlen != sizeof(tr->wh))
657 memset(((void *)&tr->wh) + hdrlen, 0, sizeof(tr->wh) - hdrlen);
a66098da
LB		 658
659 /*
660 * Firmware length is the length of the fully formed "802.11
661 * payload". That is, everything except for the 802.11 header.
662 * This includes all crypto material including the MIC.
663 */
ca009301 664 tr->fwlen = cpu_to_le16(skb->len - sizeof(*tr));
a66098da
LB		 665}
666
667
668/*
89a91f4f 669 * Packet reception for 88w8366 AP firmware.
6f6d1e9a 670 */
89a91f4f 671struct mwl8k_rxd_8366_ap {
6f6d1e9a
LB		 672 __le16 pkt_len;
673 __u8 sq2;
674 __u8 rate;
675 __le32 pkt_phys_addr;
676 __le32 next_rxd_phys_addr;
677 __le16 qos_control;
678 __le16 htsig2;
679 __le32 hw_rssi_info;
680 __le32 hw_noise_floor_info;
681 __u8 noise_floor;
682 __u8 pad0[3];
683 __u8 rssi;
684 __u8 rx_status;
685 __u8 channel;
686 __u8 rx_ctrl;
687} __attribute__((packed));
688
89a91f4f
LB		 689#define MWL8K_8366_AP_RATE_INFO_MCS_FORMAT 0x80
690#define MWL8K_8366_AP_RATE_INFO_40MHZ 0x40
691#define MWL8K_8366_AP_RATE_INFO_RATEID(x) ((x) & 0x3f)
8e9f33f0 692
89a91f4f 693#define MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST 0x80
6f6d1e9a 694
89a91f4f 695static void mwl8k_rxd_8366_ap_init(void *_rxd, dma_addr_t next_dma_addr)
6f6d1e9a 696{
89a91f4f 697 struct mwl8k_rxd_8366_ap *rxd = _rxd;
6f6d1e9a
LB		 698
699 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
89a91f4f 700 rxd->rx_ctrl = MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST;
6f6d1e9a
LB		 701}
702
89a91f4f 703static void mwl8k_rxd_8366_ap_refill(void *_rxd, dma_addr_t addr, int len)
6f6d1e9a 704{
89a91f4f 705 struct mwl8k_rxd_8366_ap *rxd = _rxd;
6f6d1e9a
LB		 706
707 rxd->pkt_len = cpu_to_le16(len);
708 rxd->pkt_phys_addr = cpu_to_le32(addr);
709 wmb();
710 rxd->rx_ctrl = 0;
711}
712
713static int
89a91f4f
LB		 714mwl8k_rxd_8366_ap_process(void *_rxd, struct ieee80211_rx_status *status,
715 __le16 *qos)
6f6d1e9a 716{
89a91f4f 717 struct mwl8k_rxd_8366_ap *rxd = _rxd;
6f6d1e9a 718
89a91f4f 719 if (!(rxd->rx_ctrl & MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST))
6f6d1e9a
LB		 720 return -1;
721 rmb();
722
723 memset(status, 0, sizeof(*status));
724
725 status->signal = -rxd->rssi;
726 status->noise = -rxd->noise_floor;
727
89a91f4f 728 if (rxd->rate & MWL8K_8366_AP_RATE_INFO_MCS_FORMAT) {
6f6d1e9a 729 status->flag |= RX_FLAG_HT;
89a91f4f 730 if (rxd->rate & MWL8K_8366_AP_RATE_INFO_40MHZ)
8e9f33f0 731 status->flag |= RX_FLAG_40MHZ;
89a91f4f 732 status->rate_idx = MWL8K_8366_AP_RATE_INFO_RATEID(rxd->rate);
6f6d1e9a
LB		 733 } else {
734 int i;
735
736 for (i = 0; i < ARRAY_SIZE(mwl8k_rates); i++) {
737 if (mwl8k_rates[i].hw_value == rxd->rate) {
738 status->rate_idx = i;
739 break;
740 }
741 }
742 }
743
744 status->band = IEEE80211_BAND_2GHZ;
745 status->freq = ieee80211_channel_to_frequency(rxd->channel);
746
20f09c3d
LB		 747 *qos = rxd->qos_control;
748
6f6d1e9a
LB		 749 return le16_to_cpu(rxd->pkt_len);
750}
751
89a91f4f
LB		 752static struct rxd_ops rxd_8366_ap_ops = {
753 .rxd_size = sizeof(struct mwl8k_rxd_8366_ap),
754 .rxd_init = mwl8k_rxd_8366_ap_init,
755 .rxd_refill = mwl8k_rxd_8366_ap_refill,
756 .rxd_process = mwl8k_rxd_8366_ap_process,
6f6d1e9a
LB		 757};
758
759/*
89a91f4f 760 * Packet reception for STA firmware.
a66098da 761 */
89a91f4f 762struct mwl8k_rxd_sta {
a66098da
LB		 763 __le16 pkt_len;
764 __u8 link_quality;
765 __u8 noise_level;
766 __le32 pkt_phys_addr;
45eb400d 767 __le32 next_rxd_phys_addr;
a66098da
LB		 768 __le16 qos_control;
769 __le16 rate_info;
770 __le32 pad0[4];
771 __u8 rssi;
772 __u8 channel;
773 __le16 pad1;
774 __u8 rx_ctrl;
775 __u8 rx_status;
776 __u8 pad2[2];
777} __attribute__((packed));
778
89a91f4f
LB		 779#define MWL8K_STA_RATE_INFO_SHORTPRE 0x8000
780#define MWL8K_STA_RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3)
781#define MWL8K_STA_RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f)
782#define MWL8K_STA_RATE_INFO_40MHZ 0x0004
783#define MWL8K_STA_RATE_INFO_SHORTGI 0x0002
784#define MWL8K_STA_RATE_INFO_MCS_FORMAT 0x0001
54bc3a0d 785
89a91f4f 786#define MWL8K_STA_RX_CTRL_OWNED_BY_HOST 0x02
54bc3a0d 787
89a91f4f 788static void mwl8k_rxd_sta_init(void *_rxd, dma_addr_t next_dma_addr)
54bc3a0d 789{
89a91f4f 790 struct mwl8k_rxd_sta *rxd = _rxd;
54bc3a0d
LB		 791
792 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
89a91f4f 793 rxd->rx_ctrl = MWL8K_STA_RX_CTRL_OWNED_BY_HOST;
54bc3a0d
LB		 794}
795
89a91f4f 796static void mwl8k_rxd_sta_refill(void *_rxd, dma_addr_t addr, int len)
54bc3a0d 797{
89a91f4f 798 struct mwl8k_rxd_sta *rxd = _rxd;
54bc3a0d
LB		 799
800 rxd->pkt_len = cpu_to_le16(len);
801 rxd->pkt_phys_addr = cpu_to_le32(addr);
802 wmb();
803 rxd->rx_ctrl = 0;
804}
805
806static int
89a91f4f 807mwl8k_rxd_sta_process(void *_rxd, struct ieee80211_rx_status *status,
20f09c3d 808 __le16 *qos)
54bc3a0d 809{
89a91f4f 810 struct mwl8k_rxd_sta *rxd = _rxd;
54bc3a0d
LB		 811 u16 rate_info;
812
89a91f4f 813 if (!(rxd->rx_ctrl & MWL8K_STA_RX_CTRL_OWNED_BY_HOST))
54bc3a0d
LB		 814 return -1;
815 rmb();
816
817 rate_info = le16_to_cpu(rxd->rate_info);
818
819 memset(status, 0, sizeof(*status));
820
821 status->signal = -rxd->rssi;
822 status->noise = -rxd->noise_level;
89a91f4f
LB		 823 status->antenna = MWL8K_STA_RATE_INFO_ANTSELECT(rate_info);
824 status->rate_idx = MWL8K_STA_RATE_INFO_RATEID(rate_info);
54bc3a0d 825
89a91f4f 826 if (rate_info & MWL8K_STA_RATE_INFO_SHORTPRE)
54bc3a0d 827 status->flag |= RX_FLAG_SHORTPRE;
89a91f4f 828 if (rate_info & MWL8K_STA_RATE_INFO_40MHZ)
54bc3a0d 829 status->flag |= RX_FLAG_40MHZ;
89a91f4f 830 if (rate_info & MWL8K_STA_RATE_INFO_SHORTGI)
54bc3a0d 831 status->flag |= RX_FLAG_SHORT_GI;
89a91f4f 832 if (rate_info & MWL8K_STA_RATE_INFO_MCS_FORMAT)
54bc3a0d
LB		 833 status->flag |= RX_FLAG_HT;
834
835 status->band = IEEE80211_BAND_2GHZ;
836 status->freq = ieee80211_channel_to_frequency(rxd->channel);
837
20f09c3d
LB		 838 *qos = rxd->qos_control;
839
54bc3a0d
LB		 840 return le16_to_cpu(rxd->pkt_len);
841}
842
89a91f4f
LB		 843static struct rxd_ops rxd_sta_ops = {
844 .rxd_size = sizeof(struct mwl8k_rxd_sta),
845 .rxd_init = mwl8k_rxd_sta_init,
846 .rxd_refill = mwl8k_rxd_sta_refill,
847 .rxd_process = mwl8k_rxd_sta_process,
54bc3a0d
LB		 848};
849
850
a66098da
LB		 851#define MWL8K_RX_DESCS 256
852#define MWL8K_RX_MAXSZ 3800
853
854static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
855{
856 struct mwl8k_priv *priv = hw->priv;
857 struct mwl8k_rx_queue *rxq = priv->rxq + index;
858 int size;
859 int i;
860
45eb400d
LB		 861 rxq->rxd_count = 0;
862 rxq->head = 0;
863 rxq->tail = 0;
a66098da 864
54bc3a0d 865 size = MWL8K_RX_DESCS * priv->rxd_ops->rxd_size;
a66098da 866
45eb400d
LB		 867 rxq->rxd = pci_alloc_consistent(priv->pdev, size, &rxq->rxd_dma);
868 if (rxq->rxd == NULL) {
a66098da 869 printk(KERN_ERR "%s: failed to alloc RX descriptors\n",
c2c357ce 870 wiphy_name(hw->wiphy));
a66098da
LB		 871 return -ENOMEM;
872 }
45eb400d 873 memset(rxq->rxd, 0, size);
a66098da 874
788838eb
LB		 875 rxq->buf = kmalloc(MWL8K_RX_DESCS * sizeof(*rxq->buf), GFP_KERNEL);
876 if (rxq->buf == NULL) {
a66098da 877 printk(KERN_ERR "%s: failed to alloc RX skbuff list\n",
c2c357ce 878 wiphy_name(hw->wiphy));
45eb400d 879 pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma);
a66098da
LB		 880 return -ENOMEM;
881 }
788838eb 882 memset(rxq->buf, 0, MWL8K_RX_DESCS * sizeof(*rxq->buf));
a66098da
LB		 883
884 for (i = 0; i < MWL8K_RX_DESCS; i++) {
54bc3a0d
LB		 885 int desc_size;
886 void *rxd;
a66098da 887 int nexti;
54bc3a0d
LB		 888 dma_addr_t next_dma_addr;
889
890 desc_size = priv->rxd_ops->rxd_size;
891 rxd = rxq->rxd + (i * priv->rxd_ops->rxd_size);
a66098da 892
54bc3a0d
LB		 893 nexti = i + 1;
894 if (nexti == MWL8K_RX_DESCS)
895 nexti = 0;
896 next_dma_addr = rxq->rxd_dma + (nexti * desc_size);
a66098da 897
54bc3a0d 898 priv->rxd_ops->rxd_init(rxd, next_dma_addr);
a66098da
LB		 899 }
900
901 return 0;
902}
903
904static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
905{
906 struct mwl8k_priv *priv = hw->priv;
907 struct mwl8k_rx_queue *rxq = priv->rxq + index;
908 int refilled;
909
910 refilled = 0;
45eb400d 911 while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) {
a66098da 912 struct sk_buff *skb;
788838eb 913 dma_addr_t addr;
a66098da 914 int rx;
54bc3a0d 915 void *rxd;
a66098da
LB		 916
917 skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
918 if (skb == NULL)
919 break;
920
788838eb
LB		 921 addr = pci_map_single(priv->pdev, skb->data,
922 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE);
a66098da 923
54bc3a0d
LB		 924 rxq->rxd_count++;
925 rx = rxq->tail++;
926 if (rxq->tail == MWL8K_RX_DESCS)
927 rxq->tail = 0;
788838eb
LB		 928 rxq->buf[rx].skb = skb;
929 pci_unmap_addr_set(&rxq->buf[rx], dma, addr);
54bc3a0d
LB		 930
931 rxd = rxq->rxd + (rx * priv->rxd_ops->rxd_size);
932 priv->rxd_ops->rxd_refill(rxd, addr, MWL8K_RX_MAXSZ);
a66098da
LB		 933
934 refilled++;
935 }
936
937 return refilled;
938}
939
940/* Must be called only when the card's reception is completely halted */
941static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
942{
943 struct mwl8k_priv *priv = hw->priv;
944 struct mwl8k_rx_queue *rxq = priv->rxq + index;
945 int i;
946
947 for (i = 0; i < MWL8K_RX_DESCS; i++) {
788838eb
LB		 948 if (rxq->buf[i].skb != NULL) {
949 pci_unmap_single(priv->pdev,
950 pci_unmap_addr(&rxq->buf[i], dma),
951 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
952 pci_unmap_addr_set(&rxq->buf[i], dma, 0);
953
954 kfree_skb(rxq->buf[i].skb);
955 rxq->buf[i].skb = NULL;
a66098da
LB		 956 }
957 }
958
788838eb
LB		 959 kfree(rxq->buf);
960 rxq->buf = NULL;
a66098da
LB		 961
962 pci_free_consistent(priv->pdev,
54bc3a0d 963 MWL8K_RX_DESCS * priv->rxd_ops->rxd_size,
45eb400d
LB		 964 rxq->rxd, rxq->rxd_dma);
965 rxq->rxd = NULL;
a66098da
LB		 966}
967
968
969/*
970 * Scan a list of BSSIDs to process for finalize join.
971 * Allows for extension to process multiple BSSIDs.
972 */
973static inline int
974mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
975{
976 return priv->capture_beacon &&
977 ieee80211_is_beacon(wh->frame_control) &&
978 !compare_ether_addr(wh->addr3, priv->capture_bssid);
979}
980
3779752d
LB		 981static inline void mwl8k_save_beacon(struct ieee80211_hw *hw,
982 struct sk_buff *skb)
a66098da 983{
3779752d
LB		 984 struct mwl8k_priv *priv = hw->priv;
985
a66098da 986 priv->capture_beacon = false;
d89173f2 987 memset(priv->capture_bssid, 0, ETH_ALEN);
a66098da
LB		 988
989 /*
990 * Use GFP_ATOMIC as rxq_process is called from
991 * the primary interrupt handler, memory allocation call
992 * must not sleep.
993 */
994 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
995 if (priv->beacon_skb != NULL)
3779752d 996 ieee80211_queue_work(hw, &priv->finalize_join_worker);
a66098da
LB		 997}
998
999static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
1000{
1001 struct mwl8k_priv *priv = hw->priv;
1002 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1003 int processed;
1004
1005 processed = 0;
45eb400d 1006 while (rxq->rxd_count && limit--) {
a66098da 1007 struct sk_buff *skb;
54bc3a0d
LB		 1008 void *rxd;
1009 int pkt_len;
a66098da 1010 struct ieee80211_rx_status status;
20f09c3d 1011 __le16 qos;
a66098da 1012
788838eb 1013 skb = rxq->buf[rxq->head].skb;
d25f9f13
LB		 1014 if (skb == NULL)
1015 break;
54bc3a0d
LB		 1016
1017 rxd = rxq->rxd + (rxq->head * priv->rxd_ops->rxd_size);
1018
20f09c3d 1019 pkt_len = priv->rxd_ops->rxd_process(rxd, &status, &qos);
54bc3a0d
LB		 1020 if (pkt_len < 0)
1021 break;
1022
788838eb
LB		 1023 rxq->buf[rxq->head].skb = NULL;
1024
1025 pci_unmap_single(priv->pdev,
1026 pci_unmap_addr(&rxq->buf[rxq->head], dma),
1027 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
1028 pci_unmap_addr_set(&rxq->buf[rxq->head], dma, 0);
a66098da 1029
54bc3a0d
LB		 1030 rxq->head++;
1031 if (rxq->head == MWL8K_RX_DESCS)
1032 rxq->head = 0;
1033
45eb400d 1034 rxq->rxd_count--;
a66098da 1035
54bc3a0d 1036 skb_put(skb, pkt_len);
20f09c3d 1037 mwl8k_remove_dma_header(skb, qos);
a66098da 1038
a66098da 1039 /*
c2c357ce
LB		 1040 * Check for a pending join operation. Save a
1041 * copy of the beacon and schedule a tasklet to
1042 * send a FINALIZE_JOIN command to the firmware.
a66098da 1043 */
54bc3a0d 1044 if (mwl8k_capture_bssid(priv, (void *)skb->data))
3779752d 1045 mwl8k_save_beacon(hw, skb);
a66098da 1046
f1d58c25
JB		 1047 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
1048 ieee80211_rx_irqsafe(hw, skb);
a66098da
LB		 1049
1050 processed++;
1051 }
1052
1053 return processed;
1054}
1055
1056
1057/*
1058 * Packet transmission.
1059 */
1060
a66098da
LB		 1061#define MWL8K_TXD_STATUS_OK 0x00000001
1062#define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
1063#define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
1064#define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
a66098da 1065#define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
a66098da 1066
e0493a8d
LB		 1067#define MWL8K_QOS_QLEN_UNSPEC 0xff00
1068#define MWL8K_QOS_ACK_POLICY_MASK 0x0060
1069#define MWL8K_QOS_ACK_POLICY_NORMAL 0x0000
1070#define MWL8K_QOS_ACK_POLICY_BLOCKACK 0x0060
1071#define MWL8K_QOS_EOSP 0x0010
1072
a66098da
LB		 1073struct mwl8k_tx_desc {
1074 __le32 status;
1075 __u8 data_rate;
1076 __u8 tx_priority;
1077 __le16 qos_control;
1078 __le32 pkt_phys_addr;
1079 __le16 pkt_len;
d89173f2 1080 __u8 dest_MAC_addr[ETH_ALEN];
45eb400d 1081 __le32 next_txd_phys_addr;
a66098da
LB		 1082 __le32 reserved;
1083 __le16 rate_info;
1084 __u8 peer_id;
1085 __u8 tx_frag_cnt;
1086} __attribute__((packed));
1087
1088#define MWL8K_TX_DESCS 128
1089
1090static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
1091{
1092 struct mwl8k_priv *priv = hw->priv;
1093 struct mwl8k_tx_queue *txq = priv->txq + index;
1094 int size;
1095 int i;
1096
45eb400d
LB		 1097 memset(&txq->stats, 0, sizeof(struct ieee80211_tx_queue_stats));
1098 txq->stats.limit = MWL8K_TX_DESCS;
1099 txq->head = 0;
1100 txq->tail = 0;
a66098da
LB		 1101
1102 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
1103
45eb400d
LB		 1104 txq->txd = pci_alloc_consistent(priv->pdev, size, &txq->txd_dma);
1105 if (txq->txd == NULL) {
a66098da 1106 printk(KERN_ERR "%s: failed to alloc TX descriptors\n",
c2c357ce 1107 wiphy_name(hw->wiphy));
a66098da
LB		 1108 return -ENOMEM;
1109 }
45eb400d 1110 memset(txq->txd, 0, size);
a66098da 1111
45eb400d
LB		 1112 txq->skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->skb), GFP_KERNEL);
1113 if (txq->skb == NULL) {
a66098da 1114 printk(KERN_ERR "%s: failed to alloc TX skbuff list\n",
c2c357ce 1115 wiphy_name(hw->wiphy));
45eb400d 1116 pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma);
a66098da
LB		 1117 return -ENOMEM;
1118 }
45eb400d 1119 memset(txq->skb, 0, MWL8K_TX_DESCS * sizeof(*txq->skb));
a66098da
LB		 1120
1121 for (i = 0; i < MWL8K_TX_DESCS; i++) {
1122 struct mwl8k_tx_desc *tx_desc;
1123 int nexti;
1124
45eb400d 1125 tx_desc = txq->txd + i;
a66098da
LB		 1126 nexti = (i + 1) % MWL8K_TX_DESCS;
1127
1128 tx_desc->status = 0;
45eb400d
LB		 1129 tx_desc->next_txd_phys_addr =
1130 cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc));
a66098da
LB		 1131 }
1132
1133 return 0;
1134}
1135
1136static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
1137{
1138 iowrite32(MWL8K_H2A_INT_PPA_READY,
1139 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1140 iowrite32(MWL8K_H2A_INT_DUMMY,
1141 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1142 ioread32(priv->regs + MWL8K_HIU_INT_CODE);
1143}
1144
7e1112d3 1145static void mwl8k_dump_tx_rings(struct ieee80211_hw *hw)
a66098da 1146{
7e1112d3
LB		 1147 struct mwl8k_priv *priv = hw->priv;
1148 int i;
1149
1150 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
1151 struct mwl8k_tx_queue *txq = priv->txq + i;
1152 int fw_owned = 0;
1153 int drv_owned = 0;
1154 int unused = 0;
1155 int desc;
1156
a66098da 1157 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
7e1112d3
LB		 1158 struct mwl8k_tx_desc *tx_desc = txq->txd + desc;
1159 u32 status;
a66098da 1160
7e1112d3 1161 status = le32_to_cpu(tx_desc->status);
a66098da 1162 if (status & MWL8K_TXD_STATUS_FW_OWNED)
7e1112d3 1163 fw_owned++;
a66098da 1164 else
7e1112d3 1165 drv_owned++;
a66098da
LB		 1166
1167 if (tx_desc->pkt_len == 0)
7e1112d3 1168 unused++;
a66098da 1169 }
a66098da 1170
7e1112d3
LB		 1171 printk(KERN_ERR "%s: txq[%d] len=%d head=%d tail=%d "
1172 "fw_owned=%d drv_owned=%d unused=%d\n",
1173 wiphy_name(hw->wiphy), i,
1174 txq->stats.len, txq->head, txq->tail,
1175 fw_owned, drv_owned, unused);
1176 }
a66098da
LB		 1177}
1178
618952a7 1179/*
88de754a 1180 * Must be called with priv->fw_mutex held and tx queues stopped.
618952a7 1181 */
62abd3cf 1182#define MWL8K_TX_WAIT_TIMEOUT_MS 5000
7e1112d3 1183
950d5b01 1184static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
a66098da 1185{
a66098da 1186 struct mwl8k_priv *priv = hw->priv;
88de754a 1187 DECLARE_COMPLETION_ONSTACK(tx_wait);
7e1112d3
LB		 1188 int retry;
1189 int rc;
a66098da
LB		 1190
1191 might_sleep();
1192
7e1112d3
LB		 1193 /*
1194 * The TX queues are stopped at this point, so this test
1195 * doesn't need to take ->tx_lock.
1196 */
1197 if (!priv->pending_tx_pkts)
1198 return 0;
1199
1200 retry = 0;
1201 rc = 0;
1202
a66098da 1203 spin_lock_bh(&priv->tx_lock);
7e1112d3
LB		 1204 priv->tx_wait = &tx_wait;
1205 while (!rc) {
1206 int oldcount;
1207 unsigned long timeout;
a66098da 1208
7e1112d3 1209 oldcount = priv->pending_tx_pkts;
a66098da 1210
7e1112d3 1211 spin_unlock_bh(&priv->tx_lock);
88de754a 1212 timeout = wait_for_completion_timeout(&tx_wait,
7e1112d3 1213 msecs_to_jiffies(MWL8K_TX_WAIT_TIMEOUT_MS));
a66098da 1214 spin_lock_bh(&priv->tx_lock);
7e1112d3
LB		 1215
1216 if (timeout) {
1217 WARN_ON(priv->pending_tx_pkts);
1218 if (retry) {
1219 printk(KERN_NOTICE "%s: tx rings drained\n",
1220 wiphy_name(hw->wiphy));
1221 }
1222 break;
1223 }
1224
1225 if (priv->pending_tx_pkts < oldcount) {
9a2303b9
LB		 1226 printk(KERN_NOTICE "%s: waiting for tx rings "
1227 "to drain (%d -> %d pkts)\n",
7e1112d3
LB		 1228 wiphy_name(hw->wiphy), oldcount,
1229 priv->pending_tx_pkts);
1230 retry = 1;
1231 continue;
1232 }
1233
a66098da 1234 priv->tx_wait = NULL;
a66098da 1235
7e1112d3
LB		 1236 printk(KERN_ERR "%s: tx rings stuck for %d ms\n",
1237 wiphy_name(hw->wiphy), MWL8K_TX_WAIT_TIMEOUT_MS);
1238 mwl8k_dump_tx_rings(hw);
1239
1240 rc = -ETIMEDOUT;
a66098da 1241 }
7e1112d3 1242 spin_unlock_bh(&priv->tx_lock);
a66098da 1243
7e1112d3 1244 return rc;
a66098da
LB		 1245}
1246
c23b5a69
LB		 1247#define MWL8K_TXD_SUCCESS(status) \
1248 ((status) & (MWL8K_TXD_STATUS_OK | \
1249 MWL8K_TXD_STATUS_OK_RETRY | \
1250 MWL8K_TXD_STATUS_OK_MORE_RETRY))
a66098da 1251
efb7c49a
LB		 1252static int
1253mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int limit, int force)
a66098da
LB		 1254{
1255 struct mwl8k_priv *priv = hw->priv;
1256 struct mwl8k_tx_queue *txq = priv->txq + index;
efb7c49a 1257 int processed;
a66098da 1258
efb7c49a
LB		 1259 processed = 0;
1260 while (txq->stats.len > 0 && limit--) {
a66098da 1261 int tx;
a66098da
LB		 1262 struct mwl8k_tx_desc *tx_desc;
1263 unsigned long addr;
ce9e2e1b 1264 int size;
a66098da
LB		 1265 struct sk_buff *skb;
1266 struct ieee80211_tx_info *info;
1267 u32 status;
1268
45eb400d
LB		 1269 tx = txq->head;
1270 tx_desc = txq->txd + tx;
a66098da
LB		 1271
1272 status = le32_to_cpu(tx_desc->status);
1273
1274 if (status & MWL8K_TXD_STATUS_FW_OWNED) {
1275 if (!force)
1276 break;
1277 tx_desc->status &=
1278 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
1279 }
1280
45eb400d
LB		 1281 txq->head = (tx + 1) % MWL8K_TX_DESCS;
1282 BUG_ON(txq->stats.len == 0);
1283 txq->stats.len--;
a66098da
LB		 1284 priv->pending_tx_pkts--;
1285
1286 addr = le32_to_cpu(tx_desc->pkt_phys_addr);
ce9e2e1b 1287 size = le16_to_cpu(tx_desc->pkt_len);
45eb400d
LB		 1288 skb = txq->skb[tx];
1289 txq->skb[tx] = NULL;
a66098da
LB		 1290
1291 BUG_ON(skb == NULL);
1292 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
1293
20f09c3d 1294 mwl8k_remove_dma_header(skb, tx_desc->qos_control);
a66098da
LB		 1295
1296 /* Mark descriptor as unused */
1297 tx_desc->pkt_phys_addr = 0;
1298 tx_desc->pkt_len = 0;
1299
a66098da
LB		 1300 info = IEEE80211_SKB_CB(skb);
1301 ieee80211_tx_info_clear_status(info);
ce9e2e1b 1302 if (MWL8K_TXD_SUCCESS(status))
a66098da 1303 info->flags |= IEEE80211_TX_STAT_ACK;
a66098da
LB		 1304
1305 ieee80211_tx_status_irqsafe(hw, skb);
1306
efb7c49a 1307 processed++;
a66098da
LB		 1308 }
1309
efb7c49a 1310 if (processed && priv->radio_on && !mutex_is_locked(&priv->fw_mutex))
a66098da 1311 ieee80211_wake_queue(hw, index);
efb7c49a
LB		 1312
1313 return processed;
a66098da
LB		 1314}
1315
1316/* must be called only when the card's transmit is completely halted */
1317static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
1318{
1319 struct mwl8k_priv *priv = hw->priv;
1320 struct mwl8k_tx_queue *txq = priv->txq + index;
1321
efb7c49a 1322 mwl8k_txq_reclaim(hw, index, INT_MAX, 1);
a66098da 1323
45eb400d
LB		 1324 kfree(txq->skb);
1325 txq->skb = NULL;
a66098da
LB		 1326
1327 pci_free_consistent(priv->pdev,
1328 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
45eb400d
LB		 1329 txq->txd, txq->txd_dma);
1330 txq->txd = NULL;
a66098da
LB		 1331}
1332
1333static int
1334mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
1335{
1336 struct mwl8k_priv *priv = hw->priv;
1337 struct ieee80211_tx_info *tx_info;
23b33906 1338 struct mwl8k_vif *mwl8k_vif;
a66098da
LB		 1339 struct ieee80211_hdr *wh;
1340 struct mwl8k_tx_queue *txq;
1341 struct mwl8k_tx_desc *tx;
a66098da 1342 dma_addr_t dma;
23b33906
LB		 1343 u32 txstatus;
1344 u8 txdatarate;
1345 u16 qos;
a66098da 1346
23b33906
LB		 1347 wh = (struct ieee80211_hdr *)skb->data;
1348 if (ieee80211_is_data_qos(wh->frame_control))
1349 qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
1350 else
1351 qos = 0;
a66098da 1352
76266b2a 1353 mwl8k_add_dma_header(skb);
23b33906 1354 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
a66098da
LB		 1355
1356 tx_info = IEEE80211_SKB_CB(skb);
1357 mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
a66098da
LB		 1358
1359 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1360 u16 seqno = mwl8k_vif->seqno;
23b33906 1361
a66098da
LB		 1362 wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1363 wh->seq_ctrl |= cpu_to_le16(seqno << 4);
1364 mwl8k_vif->seqno = seqno++ % 4096;
1365 }
1366
23b33906
LB		 1367 /* Setup firmware control bit fields for each frame type. */
1368 txstatus = 0;
1369 txdatarate = 0;
1370 if (ieee80211_is_mgmt(wh->frame_control) ||
1371 ieee80211_is_ctl(wh->frame_control)) {
1372 txdatarate = 0;
e0493a8d 1373 qos |= MWL8K_QOS_QLEN_UNSPEC | MWL8K_QOS_EOSP;
23b33906
LB		 1374 } else if (ieee80211_is_data(wh->frame_control)) {
1375 txdatarate = 1;
1376 if (is_multicast_ether_addr(wh->addr1))
1377 txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
1378
e0493a8d 1379 qos &= ~MWL8K_QOS_ACK_POLICY_MASK;
23b33906 1380 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
e0493a8d 1381 qos |= MWL8K_QOS_ACK_POLICY_BLOCKACK;
23b33906 1382 else
e0493a8d 1383 qos |= MWL8K_QOS_ACK_POLICY_NORMAL;
23b33906 1384 }
a66098da
LB		 1385
1386 dma = pci_map_single(priv->pdev, skb->data,
1387 skb->len, PCI_DMA_TODEVICE);
1388
1389 if (pci_dma_mapping_error(priv->pdev, dma)) {
1390 printk(KERN_DEBUG "%s: failed to dma map skb, "
c2c357ce 1391 "dropping TX frame.\n", wiphy_name(hw->wiphy));
23b33906 1392 dev_kfree_skb(skb);
a66098da
LB		 1393 return NETDEV_TX_OK;
1394 }
1395
23b33906 1396 spin_lock_bh(&priv->tx_lock);
a66098da 1397
23b33906 1398 txq = priv->txq + index;
a66098da 1399
45eb400d
LB		 1400 BUG_ON(txq->skb[txq->tail] != NULL);
1401 txq->skb[txq->tail] = skb;
a66098da 1402
45eb400d 1403 tx = txq->txd + txq->tail;
23b33906
LB		 1404 tx->data_rate = txdatarate;
1405 tx->tx_priority = index;
a66098da 1406 tx->qos_control = cpu_to_le16(qos);
a66098da
LB		 1407 tx->pkt_phys_addr = cpu_to_le32(dma);
1408 tx->pkt_len = cpu_to_le16(skb->len);
23b33906 1409 tx->rate_info = 0;
a680400e
LB		 1410 if (!priv->ap_fw && tx_info->control.sta != NULL)
1411 tx->peer_id = MWL8K_STA(tx_info->control.sta)->peer_id;
1412 else
1413 tx->peer_id = 0;
a66098da 1414 wmb();
23b33906
LB		 1415 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus);
1416
45eb400d
LB		 1417 txq->stats.count++;
1418 txq->stats.len++;
a66098da 1419 priv->pending_tx_pkts++;
a66098da 1420
45eb400d
LB		 1421 txq->tail++;
1422 if (txq->tail == MWL8K_TX_DESCS)
1423 txq->tail = 0;
23b33906 1424
45eb400d 1425 if (txq->head == txq->tail)
a66098da
LB		 1426 ieee80211_stop_queue(hw, index);
1427
23b33906 1428 mwl8k_tx_start(priv);
a66098da
LB		 1429
1430 spin_unlock_bh(&priv->tx_lock);
1431
1432 return NETDEV_TX_OK;
1433}
1434
1435
618952a7
LB		 1436/*
1437 * Firmware access.
1438 *
1439 * We have the following requirements for issuing firmware commands:
1440 * - Some commands require that the packet transmit path is idle when
1441 * the command is issued. (For simplicity, we'll just quiesce the
1442 * transmit path for every command.)
1443 * - There are certain sequences of commands that need to be issued to
1444 * the hardware sequentially, with no other intervening commands.
1445 *
1446 * This leads to an implementation of a "firmware lock" as a mutex that
1447 * can be taken recursively, and which is taken by both the low-level
1448 * command submission function (mwl8k_post_cmd) as well as any users of
1449 * that function that require issuing of an atomic sequence of commands,
1450 * and quiesces the transmit path whenever it's taken.
1451 */
1452static int mwl8k_fw_lock(struct ieee80211_hw *hw)
1453{
1454 struct mwl8k_priv *priv = hw->priv;
1455
1456 if (priv->fw_mutex_owner != current) {
1457 int rc;
1458
1459 mutex_lock(&priv->fw_mutex);
1460 ieee80211_stop_queues(hw);
1461
1462 rc = mwl8k_tx_wait_empty(hw);
1463 if (rc) {
1464 ieee80211_wake_queues(hw);
1465 mutex_unlock(&priv->fw_mutex);
1466
1467 return rc;
1468 }
1469
1470 priv->fw_mutex_owner = current;
1471 }
1472
1473 priv->fw_mutex_depth++;
1474
1475 return 0;
1476}
1477
1478static void mwl8k_fw_unlock(struct ieee80211_hw *hw)
1479{
1480 struct mwl8k_priv *priv = hw->priv;
1481
1482 if (!--priv->fw_mutex_depth) {
1483 ieee80211_wake_queues(hw);
1484 priv->fw_mutex_owner = NULL;
1485 mutex_unlock(&priv->fw_mutex);
1486 }
1487}
1488
1489
a66098da
LB		 1490/*
1491 * Command processing.
1492 */
1493
0c9cc640
LB		 1494/* Timeout firmware commands after 10s */
1495#define MWL8K_CMD_TIMEOUT_MS 10000
a66098da
LB		 1496
1497static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
1498{
1499 DECLARE_COMPLETION_ONSTACK(cmd_wait);
1500 struct mwl8k_priv *priv = hw->priv;
1501 void __iomem *regs = priv->regs;
1502 dma_addr_t dma_addr;
1503 unsigned int dma_size;
1504 int rc;
a66098da
LB		 1505 unsigned long timeout = 0;
1506 u8 buf[32];
1507
c2c357ce 1508 cmd->result = 0xffff;
a66098da
LB		 1509 dma_size = le16_to_cpu(cmd->length);
1510 dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
1511 PCI_DMA_BIDIRECTIONAL);
1512 if (pci_dma_mapping_error(priv->pdev, dma_addr))
1513 return -ENOMEM;
1514
618952a7 1515 rc = mwl8k_fw_lock(hw);
39a1e42e
LB		 1516 if (rc) {
1517 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1518 PCI_DMA_BIDIRECTIONAL);
618952a7 1519 return rc;
39a1e42e 1520 }
a66098da 1521
a66098da
LB		 1522 priv->hostcmd_wait = &cmd_wait;
1523 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
1524 iowrite32(MWL8K_H2A_INT_DOORBELL,
1525 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1526 iowrite32(MWL8K_H2A_INT_DUMMY,
1527 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
a66098da
LB		 1528
1529 timeout = wait_for_completion_timeout(&cmd_wait,
1530 msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
1531
618952a7
LB		 1532 priv->hostcmd_wait = NULL;
1533
1534 mwl8k_fw_unlock(hw);
1535
37055bd4
LB		 1536 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1537 PCI_DMA_BIDIRECTIONAL);
1538
a66098da 1539 if (!timeout) {
a66098da 1540 printk(KERN_ERR "%s: Command %s timeout after %u ms\n",
c2c357ce 1541 wiphy_name(hw->wiphy),
a66098da
LB		 1542 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1543 MWL8K_CMD_TIMEOUT_MS);
1544 rc = -ETIMEDOUT;
1545 } else {
0c9cc640
LB		 1546 int ms;
1547
1548 ms = MWL8K_CMD_TIMEOUT_MS - jiffies_to_msecs(timeout);
1549
ce9e2e1b 1550 rc = cmd->result ? -EINVAL : 0;
a66098da
LB		 1551 if (rc)
1552 printk(KERN_ERR "%s: Command %s error 0x%x\n",
c2c357ce 1553 wiphy_name(hw->wiphy),
a66098da 1554 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
76c962a2 1555 le16_to_cpu(cmd->result));
0c9cc640
LB		 1556 else if (ms > 2000)
1557 printk(KERN_NOTICE "%s: Command %s took %d ms\n",
1558 wiphy_name(hw->wiphy),
1559 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1560 ms);
a66098da
LB		 1561 }
1562
a66098da
LB		 1563 return rc;
1564}
1565
1566/*
04b147b1 1567 * CMD_GET_HW_SPEC (STA version).
a66098da 1568 */
04b147b1 1569struct mwl8k_cmd_get_hw_spec_sta {
a66098da
LB		 1570 struct mwl8k_cmd_pkt header;
1571 __u8 hw_rev;
1572 __u8 host_interface;
1573 __le16 num_mcaddrs;
d89173f2 1574 __u8 perm_addr[ETH_ALEN];
a66098da
LB		 1575 __le16 region_code;
1576 __le32 fw_rev;
1577 __le32 ps_cookie;
1578 __le32 caps;
1579 __u8 mcs_bitmap[16];
1580 __le32 rx_queue_ptr;
1581 __le32 num_tx_queues;
1582 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1583 __le32 caps2;
1584 __le32 num_tx_desc_per_queue;
45eb400d 1585 __le32 total_rxd;
a66098da
LB		 1586} __attribute__((packed));
1587
341c9791
LB		 1588#define MWL8K_CAP_MAX_AMSDU 0x20000000
1589#define MWL8K_CAP_GREENFIELD 0x08000000
1590#define MWL8K_CAP_AMPDU 0x04000000
1591#define MWL8K_CAP_RX_STBC 0x01000000
1592#define MWL8K_CAP_TX_STBC 0x00800000
1593#define MWL8K_CAP_SHORTGI_40MHZ 0x00400000
1594#define MWL8K_CAP_SHORTGI_20MHZ 0x00200000
1595#define MWL8K_CAP_RX_ANTENNA_MASK 0x000e0000
1596#define MWL8K_CAP_TX_ANTENNA_MASK 0x0001c000
1597#define MWL8K_CAP_DELAY_BA 0x00003000
1598#define MWL8K_CAP_MIMO 0x00000200
1599#define MWL8K_CAP_40MHZ 0x00000100
1600
1601static void mwl8k_set_ht_caps(struct ieee80211_hw *hw, u32 cap)
1602{
1603 struct mwl8k_priv *priv = hw->priv;
1604 int rx_streams;
1605 int tx_streams;
1606
1607 priv->band.ht_cap.ht_supported = 1;
1608
1609 if (cap & MWL8K_CAP_MAX_AMSDU)
1610 priv->band.ht_cap.cap |= IEEE80211_HT_CAP_MAX_AMSDU;
1611 if (cap & MWL8K_CAP_GREENFIELD)
1612 priv->band.ht_cap.cap |= IEEE80211_HT_CAP_GRN_FLD;
1613 if (cap & MWL8K_CAP_AMPDU) {
1614 hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION;
1615 priv->band.ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
1616 priv->band.ht_cap.ampdu_density =
1617 IEEE80211_HT_MPDU_DENSITY_NONE;
1618 }
1619 if (cap & MWL8K_CAP_RX_STBC)
1620 priv->band.ht_cap.cap |= IEEE80211_HT_CAP_RX_STBC;
1621 if (cap & MWL8K_CAP_TX_STBC)
1622 priv->band.ht_cap.cap |= IEEE80211_HT_CAP_TX_STBC;
1623 if (cap & MWL8K_CAP_SHORTGI_40MHZ)
1624 priv->band.ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
1625 if (cap & MWL8K_CAP_SHORTGI_20MHZ)
1626 priv->band.ht_cap.cap |= IEEE80211_HT_CAP_SGI_20;
1627 if (cap & MWL8K_CAP_DELAY_BA)
1628 priv->band.ht_cap.cap |= IEEE80211_HT_CAP_DELAY_BA;
1629 if (cap & MWL8K_CAP_40MHZ)
1630 priv->band.ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
1631
1632 rx_streams = hweight32(cap & MWL8K_CAP_RX_ANTENNA_MASK);
1633 tx_streams = hweight32(cap & MWL8K_CAP_TX_ANTENNA_MASK);
1634
1635 priv->band.ht_cap.mcs.rx_mask[0] = 0xff;
1636 if (rx_streams >= 2)
1637 priv->band.ht_cap.mcs.rx_mask[1] = 0xff;
1638 if (rx_streams >= 3)
1639 priv->band.ht_cap.mcs.rx_mask[2] = 0xff;
1640 priv->band.ht_cap.mcs.rx_mask[4] = 0x01;
1641 priv->band.ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
1642
1643 if (rx_streams != tx_streams) {
1644 priv->band.ht_cap.mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
1645 priv->band.ht_cap.mcs.tx_params |= (tx_streams - 1) <<
1646 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
1647 }
1648}
1649
04b147b1 1650static int mwl8k_cmd_get_hw_spec_sta(struct ieee80211_hw *hw)
a66098da
LB		 1651{
1652 struct mwl8k_priv *priv = hw->priv;
04b147b1 1653 struct mwl8k_cmd_get_hw_spec_sta *cmd;
a66098da
LB		 1654 int rc;
1655 int i;
1656
1657 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1658 if (cmd == NULL)
1659 return -ENOMEM;
1660
1661 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1662 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1663
1664 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1665 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
45eb400d 1666 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
4ff6432e 1667 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
a66098da 1668 for (i = 0; i < MWL8K_TX_QUEUES; i++)
45eb400d 1669 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
4ff6432e 1670 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
45eb400d 1671 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
a66098da
LB		 1672
1673 rc = mwl8k_post_cmd(hw, &cmd->header);
1674
1675 if (!rc) {
1676 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1677 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
4ff6432e 1678 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
a66098da 1679 priv->hw_rev = cmd->hw_rev;
341c9791
LB		 1680 if (cmd->caps & cpu_to_le32(MWL8K_CAP_MIMO))
1681 mwl8k_set_ht_caps(hw, le32_to_cpu(cmd->caps));
a66098da
LB		 1682 }
1683
1684 kfree(cmd);
1685 return rc;
1686}
1687
42fba21d
LB		 1688/*
1689 * CMD_GET_HW_SPEC (AP version).
1690 */
1691struct mwl8k_cmd_get_hw_spec_ap {
1692 struct mwl8k_cmd_pkt header;
1693 __u8 hw_rev;
1694 __u8 host_interface;
1695 __le16 num_wcb;
1696 __le16 num_mcaddrs;
1697 __u8 perm_addr[ETH_ALEN];
1698 __le16 region_code;
1699 __le16 num_antenna;
1700 __le32 fw_rev;
1701 __le32 wcbbase0;
1702 __le32 rxwrptr;
1703 __le32 rxrdptr;
1704 __le32 ps_cookie;
1705 __le32 wcbbase1;
1706 __le32 wcbbase2;
1707 __le32 wcbbase3;
1708} __attribute__((packed));
1709
1710static int mwl8k_cmd_get_hw_spec_ap(struct ieee80211_hw *hw)
1711{
1712 struct mwl8k_priv *priv = hw->priv;
1713 struct mwl8k_cmd_get_hw_spec_ap *cmd;
1714 int rc;
1715
1716 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1717 if (cmd == NULL)
1718 return -ENOMEM;
1719
1720 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1721 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1722
1723 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1724 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1725
1726 rc = mwl8k_post_cmd(hw, &cmd->header);
1727
1728 if (!rc) {
1729 int off;
1730
1731 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1732 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
1733 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
1734 priv->hw_rev = cmd->hw_rev;
1735
1736 off = le32_to_cpu(cmd->wcbbase0) & 0xffff;
1737 iowrite32(cpu_to_le32(priv->txq[0].txd_dma), priv->sram + off);
1738
1739 off = le32_to_cpu(cmd->rxwrptr) & 0xffff;
1740 iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
1741
1742 off = le32_to_cpu(cmd->rxrdptr) & 0xffff;
1743 iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
1744
1745 off = le32_to_cpu(cmd->wcbbase1) & 0xffff;
1746 iowrite32(cpu_to_le32(priv->txq[1].txd_dma), priv->sram + off);
1747
1748 off = le32_to_cpu(cmd->wcbbase2) & 0xffff;
1749 iowrite32(cpu_to_le32(priv->txq[2].txd_dma), priv->sram + off);
1750
1751 off = le32_to_cpu(cmd->wcbbase3) & 0xffff;
1752 iowrite32(cpu_to_le32(priv->txq[3].txd_dma), priv->sram + off);
1753 }
1754
1755 kfree(cmd);
1756 return rc;
1757}
1758
1759/*
1760 * CMD_SET_HW_SPEC.
1761 */
1762struct mwl8k_cmd_set_hw_spec {
1763 struct mwl8k_cmd_pkt header;
1764 __u8 hw_rev;
1765 __u8 host_interface;
1766 __le16 num_mcaddrs;
1767 __u8 perm_addr[ETH_ALEN];
1768 __le16 region_code;
1769 __le32 fw_rev;
1770 __le32 ps_cookie;
1771 __le32 caps;
1772 __le32 rx_queue_ptr;
1773 __le32 num_tx_queues;
1774 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1775 __le32 flags;
1776 __le32 num_tx_desc_per_queue;
1777 __le32 total_rxd;
1778} __attribute__((packed));
1779
b64fe619
LB		 1780#define MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT 0x00000080
1781#define MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_PROBERESP 0x00000020
1782#define MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_BEACON 0x00000010
42fba21d
LB		 1783
1784static int mwl8k_cmd_set_hw_spec(struct ieee80211_hw *hw)
1785{
1786 struct mwl8k_priv *priv = hw->priv;
1787 struct mwl8k_cmd_set_hw_spec *cmd;
1788 int rc;
1789 int i;
1790
1791 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1792 if (cmd == NULL)
1793 return -ENOMEM;
1794
1795 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_HW_SPEC);
1796 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1797
1798 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1799 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
1800 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
1801 for (i = 0; i < MWL8K_TX_QUEUES; i++)
1802 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
b64fe619
LB		 1803 cmd->flags = cpu_to_le32(MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT |
1804 MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_PROBERESP |
1805 MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_BEACON);
42fba21d
LB		 1806 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
1807 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
1808
1809 rc = mwl8k_post_cmd(hw, &cmd->header);
1810 kfree(cmd);
1811
1812 return rc;
1813}
1814
a66098da
LB		 1815/*
1816 * CMD_MAC_MULTICAST_ADR.
1817 */
1818struct mwl8k_cmd_mac_multicast_adr {
1819 struct mwl8k_cmd_pkt header;
1820 __le16 action;
1821 __le16 numaddr;
ce9e2e1b 1822 __u8 addr[0][ETH_ALEN];
a66098da
LB		 1823};
1824
d5e30845
LB		 1825#define MWL8K_ENABLE_RX_DIRECTED 0x0001
1826#define MWL8K_ENABLE_RX_MULTICAST 0x0002
1827#define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004
1828#define MWL8K_ENABLE_RX_BROADCAST 0x0008
ce9e2e1b 1829
e81cd2d6 1830static struct mwl8k_cmd_pkt *
447ced07 1831__mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti,
e81cd2d6 1832 int mc_count, struct dev_addr_list *mclist)
a66098da 1833{
e81cd2d6 1834 struct mwl8k_priv *priv = hw->priv;
a66098da 1835 struct mwl8k_cmd_mac_multicast_adr *cmd;
e81cd2d6 1836 int size;
e81cd2d6 1837
447ced07 1838 if (allmulti || mc_count > priv->num_mcaddrs) {
d5e30845
LB		 1839 allmulti = 1;
1840 mc_count = 0;
1841 }
e81cd2d6
LB		 1842
1843 size = sizeof(*cmd) + mc_count * ETH_ALEN;
ce9e2e1b 1844
e81cd2d6 1845 cmd = kzalloc(size, GFP_ATOMIC);
a66098da 1846 if (cmd == NULL)
e81cd2d6 1847 return NULL;
a66098da
LB		 1848
1849 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
1850 cmd->header.length = cpu_to_le16(size);
d5e30845
LB		 1851 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED |
1852 MWL8K_ENABLE_RX_BROADCAST);
1853
1854 if (allmulti) {
1855 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST);
1856 } else if (mc_count) {
1857 int i;
1858
1859 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
1860 cmd->numaddr = cpu_to_le16(mc_count);
1861 for (i = 0; i < mc_count && mclist; i++) {
1862 if (mclist->da_addrlen != ETH_ALEN) {
1863 kfree(cmd);
1864 return NULL;
1865 }
1866 memcpy(cmd->addr[i], mclist->da_addr, ETH_ALEN);
1867 mclist = mclist->next;
a66098da 1868 }
a66098da
LB		 1869 }
1870
e81cd2d6 1871 return &cmd->header;
a66098da
LB		 1872}
1873
1874/*
55489b6e 1875 * CMD_GET_STAT.
a66098da 1876 */
55489b6e 1877struct mwl8k_cmd_get_stat {
a66098da 1878 struct mwl8k_cmd_pkt header;
a66098da
LB		 1879 __le32 stats[64];
1880} __attribute__((packed));
1881
1882#define MWL8K_STAT_ACK_FAILURE 9
1883#define MWL8K_STAT_RTS_FAILURE 12
1884#define MWL8K_STAT_FCS_ERROR 24
1885#define MWL8K_STAT_RTS_SUCCESS 11
1886
55489b6e
LB		 1887static int mwl8k_cmd_get_stat(struct ieee80211_hw *hw,
1888 struct ieee80211_low_level_stats *stats)
a66098da 1889{
55489b6e 1890 struct mwl8k_cmd_get_stat *cmd;
a66098da
LB		 1891 int rc;
1892
1893 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1894 if (cmd == NULL)
1895 return -ENOMEM;
1896
1897 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
1898 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB		 1899
1900 rc = mwl8k_post_cmd(hw, &cmd->header);
1901 if (!rc) {
1902 stats->dot11ACKFailureCount =
1903 le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
1904 stats->dot11RTSFailureCount =
1905 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
1906 stats->dot11FCSErrorCount =
1907 le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
1908 stats->dot11RTSSuccessCount =
1909 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
1910 }
1911 kfree(cmd);
1912
1913 return rc;
1914}
1915
1916/*
55489b6e 1917 * CMD_RADIO_CONTROL.
a66098da 1918 */
55489b6e 1919struct mwl8k_cmd_radio_control {
a66098da
LB		 1920 struct mwl8k_cmd_pkt header;
1921 __le16 action;
1922 __le16 control;
1923 __le16 radio_on;
1924} __attribute__((packed));
1925
c46563b7 1926static int
55489b6e 1927mwl8k_cmd_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
a66098da
LB		 1928{
1929 struct mwl8k_priv *priv = hw->priv;
55489b6e 1930 struct mwl8k_cmd_radio_control *cmd;
a66098da
LB		 1931 int rc;
1932
c46563b7 1933 if (enable == priv->radio_on && !force)
a66098da
LB		 1934 return 0;
1935
a66098da
LB		 1936 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1937 if (cmd == NULL)
1938 return -ENOMEM;
1939
1940 cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
1941 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1942 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
68ce3884 1943 cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
a66098da
LB		 1944 cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
1945
1946 rc = mwl8k_post_cmd(hw, &cmd->header);
1947 kfree(cmd);
1948
1949 if (!rc)
c46563b7 1950 priv->radio_on = enable;
a66098da
LB		 1951
1952 return rc;
1953}
1954
55489b6e 1955static int mwl8k_cmd_radio_disable(struct ieee80211_hw *hw)
c46563b7 1956{
55489b6e 1957 return mwl8k_cmd_radio_control(hw, 0, 0);
c46563b7
LB		 1958}
1959
55489b6e 1960static int mwl8k_cmd_radio_enable(struct ieee80211_hw *hw)
c46563b7 1961{
55489b6e 1962 return mwl8k_cmd_radio_control(hw, 1, 0);
c46563b7
LB		 1963}
1964
a66098da
LB		 1965static int
1966mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
1967{
99200a99 1968 struct mwl8k_priv *priv = hw->priv;
a66098da 1969
68ce3884 1970 priv->radio_short_preamble = short_preamble;
a66098da 1971
55489b6e 1972 return mwl8k_cmd_radio_control(hw, 1, 1);
a66098da
LB		 1973}
1974
1975/*
55489b6e 1976 * CMD_RF_TX_POWER.
a66098da
LB		 1977 */
1978#define MWL8K_TX_POWER_LEVEL_TOTAL 8
1979
55489b6e 1980struct mwl8k_cmd_rf_tx_power {
a66098da
LB		 1981 struct mwl8k_cmd_pkt header;
1982 __le16 action;
1983 __le16 support_level;
1984 __le16 current_level;
1985 __le16 reserved;
1986 __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
1987} __attribute__((packed));
1988
55489b6e 1989static int mwl8k_cmd_rf_tx_power(struct ieee80211_hw *hw, int dBm)
a66098da 1990{
55489b6e 1991 struct mwl8k_cmd_rf_tx_power *cmd;
a66098da
LB		 1992 int rc;
1993
1994 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1995 if (cmd == NULL)
1996 return -ENOMEM;
1997
1998 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
1999 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2000 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2001 cmd->support_level = cpu_to_le16(dBm);
2002
2003 rc = mwl8k_post_cmd(hw, &cmd->header);
2004 kfree(cmd);
2005
2006 return rc;
2007}
2008
08b06347
LB		 2009/*
2010 * CMD_RF_ANTENNA.
2011 */
2012struct mwl8k_cmd_rf_antenna {
2013 struct mwl8k_cmd_pkt header;
2014 __le16 antenna;
2015 __le16 mode;
2016} __attribute__((packed));
2017
2018#define MWL8K_RF_ANTENNA_RX 1
2019#define MWL8K_RF_ANTENNA_TX 2
2020
2021static int
2022mwl8k_cmd_rf_antenna(struct ieee80211_hw *hw, int antenna, int mask)
2023{
2024 struct mwl8k_cmd_rf_antenna *cmd;
2025 int rc;
2026
2027 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2028 if (cmd == NULL)
2029 return -ENOMEM;
2030
2031 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_ANTENNA);
2032 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2033 cmd->antenna = cpu_to_le16(antenna);
2034 cmd->mode = cpu_to_le16(mask);
2035
2036 rc = mwl8k_post_cmd(hw, &cmd->header);
2037 kfree(cmd);
2038
2039 return rc;
2040}
2041
b64fe619
LB		 2042/*
2043 * CMD_SET_BEACON.
2044 */
2045struct mwl8k_cmd_set_beacon {
2046 struct mwl8k_cmd_pkt header;
2047 __le16 beacon_len;
2048 __u8 beacon[0];
2049};
2050
2051static int mwl8k_cmd_set_beacon(struct ieee80211_hw *hw, u8 *beacon, int len)
2052{
2053 struct mwl8k_cmd_set_beacon *cmd;
2054 int rc;
2055
2056 cmd = kzalloc(sizeof(*cmd) + len, GFP_KERNEL);
2057 if (cmd == NULL)
2058 return -ENOMEM;
2059
2060 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_BEACON);
2061 cmd->header.length = cpu_to_le16(sizeof(*cmd) + len);
2062 cmd->beacon_len = cpu_to_le16(len);
2063 memcpy(cmd->beacon, beacon, len);
2064
2065 rc = mwl8k_post_cmd(hw, &cmd->header);
2066 kfree(cmd);
2067
2068 return rc;
2069}
2070
a66098da
LB		 2071/*
2072 * CMD_SET_PRE_SCAN.
2073 */
2074struct mwl8k_cmd_set_pre_scan {
2075 struct mwl8k_cmd_pkt header;
2076} __attribute__((packed));
2077
2078static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
2079{
2080 struct mwl8k_cmd_set_pre_scan *cmd;
2081 int rc;
2082
2083 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2084 if (cmd == NULL)
2085 return -ENOMEM;
2086
2087 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
2088 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2089
2090 rc = mwl8k_post_cmd(hw, &cmd->header);
2091 kfree(cmd);
2092
2093 return rc;
2094}
2095
2096/*
2097 * CMD_SET_POST_SCAN.
2098 */
2099struct mwl8k_cmd_set_post_scan {
2100 struct mwl8k_cmd_pkt header;
2101 __le32 isibss;
d89173f2 2102 __u8 bssid[ETH_ALEN];
a66098da
LB		 2103} __attribute__((packed));
2104
2105static int
0a11dfc3 2106mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, const __u8 *mac)
a66098da
LB		 2107{
2108 struct mwl8k_cmd_set_post_scan *cmd;
2109 int rc;
2110
2111 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2112 if (cmd == NULL)
2113 return -ENOMEM;
2114
2115 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
2116 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2117 cmd->isibss = 0;
d89173f2 2118 memcpy(cmd->bssid, mac, ETH_ALEN);
a66098da
LB		 2119
2120 rc = mwl8k_post_cmd(hw, &cmd->header);
2121 kfree(cmd);
2122
2123 return rc;
2124}
2125
2126/*
2127 * CMD_SET_RF_CHANNEL.
2128 */
2129struct mwl8k_cmd_set_rf_channel {
2130 struct mwl8k_cmd_pkt header;
2131 __le16 action;
2132 __u8 current_channel;
2133 __le32 channel_flags;
2134} __attribute__((packed));
2135
2136static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
610677d2 2137 struct ieee80211_conf *conf)
a66098da 2138{
610677d2 2139 struct ieee80211_channel *channel = conf->channel;
a66098da
LB		 2140 struct mwl8k_cmd_set_rf_channel *cmd;
2141 int rc;
2142
2143 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2144 if (cmd == NULL)
2145 return -ENOMEM;
2146
2147 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
2148 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2149 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2150 cmd->current_channel = channel->hw_value;
610677d2 2151
a66098da 2152 if (channel->band == IEEE80211_BAND_2GHZ)
610677d2
LB		 2153 cmd->channel_flags |= cpu_to_le32(0x00000001);
2154
2155 if (conf->channel_type == NL80211_CHAN_NO_HT ||
2156 conf->channel_type == NL80211_CHAN_HT20)
2157 cmd->channel_flags |= cpu_to_le32(0x00000080);
2158 else if (conf->channel_type == NL80211_CHAN_HT40MINUS)
2159 cmd->channel_flags |= cpu_to_le32(0x000001900);
2160 else if (conf->channel_type == NL80211_CHAN_HT40PLUS)
2161 cmd->channel_flags |= cpu_to_le32(0x000000900);
a66098da
LB		 2162
2163 rc = mwl8k_post_cmd(hw, &cmd->header);
2164 kfree(cmd);
2165
2166 return rc;
2167}
2168
2169/*
55489b6e 2170 * CMD_SET_AID.
a66098da 2171 */
55489b6e
LB		 2172#define MWL8K_FRAME_PROT_DISABLED 0x00
2173#define MWL8K_FRAME_PROT_11G 0x07
2174#define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
2175#define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
a66098da 2176
55489b6e
LB		 2177struct mwl8k_cmd_update_set_aid {
2178 struct mwl8k_cmd_pkt header;
2179 __le16 aid;
a66098da 2180
55489b6e
LB		 2181 /* AP's MAC address (BSSID) */
2182 __u8 bssid[ETH_ALEN];
2183 __le16 protection_mode;
2184 __u8 supp_rates[14];
a66098da
LB		 2185} __attribute__((packed));
2186
c6e96010
LB		 2187static void legacy_rate_mask_to_array(u8 *rates, u32 mask)
2188{
2189 int i;
2190 int j;
2191
2192 /*
2193 * Clear nonstandard rates 4 and 13.
2194 */
2195 mask &= 0x1fef;
2196
2197 for (i = 0, j = 0; i < 14; i++) {
2198 if (mask & (1 << i))
2199 rates[j++] = mwl8k_rates[i].hw_value;
2200 }
2201}
2202
55489b6e 2203static int
c6e96010
LB		 2204mwl8k_cmd_set_aid(struct ieee80211_hw *hw,
2205 struct ieee80211_vif *vif, u32 legacy_rate_mask)
a66098da 2206{
55489b6e
LB		 2207 struct mwl8k_cmd_update_set_aid *cmd;
2208 u16 prot_mode;
a66098da
LB		 2209 int rc;
2210
2211 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2212 if (cmd == NULL)
2213 return -ENOMEM;
2214
55489b6e 2215 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
a66098da 2216 cmd->header.length = cpu_to_le16(sizeof(*cmd));
7dc6a7a7 2217 cmd->aid = cpu_to_le16(vif->bss_conf.aid);
0a11dfc3 2218 memcpy(cmd->bssid, vif->bss_conf.bssid, ETH_ALEN);
a66098da 2219
7dc6a7a7 2220 if (vif->bss_conf.use_cts_prot) {
55489b6e
LB		 2221 prot_mode = MWL8K_FRAME_PROT_11G;
2222 } else {
7dc6a7a7 2223 switch (vif->bss_conf.ht_operation_mode &
55489b6e
LB		 2224 IEEE80211_HT_OP_MODE_PROTECTION) {
2225 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
2226 prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
2227 break;
2228 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
2229 prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
2230 break;
2231 default:
2232 prot_mode = MWL8K_FRAME_PROT_DISABLED;
2233 break;
2234 }
2235 }
2236 cmd->protection_mode = cpu_to_le16(prot_mode);
a66098da 2237
c6e96010 2238 legacy_rate_mask_to_array(cmd->supp_rates, legacy_rate_mask);
a66098da
LB		 2239
2240 rc = mwl8k_post_cmd(hw, &cmd->header);
2241 kfree(cmd);
2242
2243 return rc;
2244}
2245
32060e1b 2246/*
55489b6e 2247 * CMD_SET_RATE.
32060e1b 2248 */
55489b6e
LB		 2249struct mwl8k_cmd_set_rate {
2250 struct mwl8k_cmd_pkt header;
2251 __u8 legacy_rates[14];
2252
2253 /* Bitmap for supported MCS codes. */
2254 __u8 mcs_set[16];
2255 __u8 reserved[16];
32060e1b
LB		 2256} __attribute__((packed));
2257
55489b6e 2258static int
c6e96010 2259mwl8k_cmd_set_rate(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
13935e2c 2260 u32 legacy_rate_mask, u8 *mcs_rates)
32060e1b 2261{
55489b6e 2262 struct mwl8k_cmd_set_rate *cmd;
32060e1b
LB		 2263 int rc;
2264
2265 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2266 if (cmd == NULL)
2267 return -ENOMEM;
2268
55489b6e 2269 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
32060e1b 2270 cmd->header.length = cpu_to_le16(sizeof(*cmd));
c6e96010 2271 legacy_rate_mask_to_array(cmd->legacy_rates, legacy_rate_mask);
13935e2c 2272 memcpy(cmd->mcs_set, mcs_rates, 16);
32060e1b
LB		 2273
2274 rc = mwl8k_post_cmd(hw, &cmd->header);
2275 kfree(cmd);
2276
2277 return rc;
2278}
2279
a66098da 2280/*
55489b6e 2281 * CMD_FINALIZE_JOIN.
a66098da 2282 */
55489b6e
LB		 2283#define MWL8K_FJ_BEACON_MAXLEN 128
2284
2285struct mwl8k_cmd_finalize_join {
a66098da 2286 struct mwl8k_cmd_pkt header;
55489b6e
LB		 2287 __le32 sleep_interval; /* Number of beacon periods to sleep */
2288 __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
a66098da
LB		 2289} __attribute__((packed));
2290
55489b6e
LB		 2291static int mwl8k_cmd_finalize_join(struct ieee80211_hw *hw, void *frame,
2292 int framelen, int dtim)
a66098da 2293{
55489b6e
LB		 2294 struct mwl8k_cmd_finalize_join *cmd;
2295 struct ieee80211_mgmt *payload = frame;
2296 int payload_len;
a66098da
LB		 2297 int rc;
2298
2299 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2300 if (cmd == NULL)
2301 return -ENOMEM;
2302
55489b6e 2303 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
a66098da 2304 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB		 2305 cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
2306
2307 payload_len = framelen - ieee80211_hdrlen(payload->frame_control);
2308 if (payload_len < 0)
2309 payload_len = 0;
2310 else if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2311 payload_len = MWL8K_FJ_BEACON_MAXLEN;
2312
2313 memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
a66098da
LB		 2314
2315 rc = mwl8k_post_cmd(hw, &cmd->header);
2316 kfree(cmd);
2317
2318 return rc;
2319}
2320
2321/*
55489b6e 2322 * CMD_SET_RTS_THRESHOLD.
a66098da 2323 */
55489b6e 2324struct mwl8k_cmd_set_rts_threshold {
a66098da
LB		 2325 struct mwl8k_cmd_pkt header;
2326 __le16 action;
55489b6e 2327 __le16 threshold;
a66098da
LB		 2328} __attribute__((packed));
2329
c2c2b12a
LB		 2330static int
2331mwl8k_cmd_set_rts_threshold(struct ieee80211_hw *hw, int rts_thresh)
a66098da 2332{
55489b6e 2333 struct mwl8k_cmd_set_rts_threshold *cmd;
a66098da
LB		 2334 int rc;
2335
2336 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2337 if (cmd == NULL)
2338 return -ENOMEM;
2339
55489b6e 2340 cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
a66098da 2341 cmd->header.length = cpu_to_le16(sizeof(*cmd));
c2c2b12a
LB		 2342 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2343 cmd->threshold = cpu_to_le16(rts_thresh);
a66098da
LB		 2344
2345 rc = mwl8k_post_cmd(hw, &cmd->header);
2346 kfree(cmd);
2347
a66098da
LB		 2348 return rc;
2349}
2350
2351/*
55489b6e 2352 * CMD_SET_SLOT.
a66098da 2353 */
55489b6e 2354struct mwl8k_cmd_set_slot {
a66098da
LB		 2355 struct mwl8k_cmd_pkt header;
2356 __le16 action;
55489b6e 2357 __u8 short_slot;
a66098da
LB		 2358} __attribute__((packed));
2359
55489b6e 2360static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time)
a66098da 2361{
55489b6e 2362 struct mwl8k_cmd_set_slot *cmd;
a66098da
LB		 2363 int rc;
2364
2365 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2366 if (cmd == NULL)
2367 return -ENOMEM;
2368
55489b6e 2369 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
a66098da 2370 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB		 2371 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2372 cmd->short_slot = short_slot_time;
a66098da
LB		 2373
2374 rc = mwl8k_post_cmd(hw, &cmd->header);
2375 kfree(cmd);
2376
2377 return rc;
2378}
2379
2380/*
2381 * CMD_SET_EDCA_PARAMS.
2382 */
2383struct mwl8k_cmd_set_edca_params {
2384 struct mwl8k_cmd_pkt header;
2385
2386 /* See MWL8K_SET_EDCA_XXX below */
2387 __le16 action;
2388
2389 /* TX opportunity in units of 32 us */
2390 __le16 txop;
2391
2e484c89
LB		 2392 union {
2393 struct {
2394 /* Log exponent of max contention period: 0...15 */
2395 __le32 log_cw_max;
2396
2397 /* Log exponent of min contention period: 0...15 */
2398 __le32 log_cw_min;
2399
2400 /* Adaptive interframe spacing in units of 32us */
2401 __u8 aifs;
2402
2403 /* TX queue to configure */
2404 __u8 txq;
2405 } ap;
2406 struct {
2407 /* Log exponent of max contention period: 0...15 */
2408 __u8 log_cw_max;
a66098da 2409
2e484c89
LB		 2410 /* Log exponent of min contention period: 0...15 */
2411 __u8 log_cw_min;
a66098da 2412
2e484c89
LB		 2413 /* Adaptive interframe spacing in units of 32us */
2414 __u8 aifs;
a66098da 2415
2e484c89
LB		 2416 /* TX queue to configure */
2417 __u8 txq;
2418 } sta;
2419 };
a66098da
LB		 2420} __attribute__((packed));
2421
a66098da
LB		 2422#define MWL8K_SET_EDCA_CW 0x01
2423#define MWL8K_SET_EDCA_TXOP 0x02
2424#define MWL8K_SET_EDCA_AIFS 0x04
2425
2426#define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
2427 MWL8K_SET_EDCA_TXOP | \
2428 MWL8K_SET_EDCA_AIFS)
2429
2430static int
55489b6e
LB		 2431mwl8k_cmd_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
2432 __u16 cw_min, __u16 cw_max,
2433 __u8 aifs, __u16 txop)
a66098da 2434{
2e484c89 2435 struct mwl8k_priv *priv = hw->priv;
a66098da 2436 struct mwl8k_cmd_set_edca_params *cmd;
a66098da
LB		 2437 int rc;
2438
2439 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2440 if (cmd == NULL)
2441 return -ENOMEM;
2442
a66098da
LB		 2443 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
2444 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB		 2445 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
2446 cmd->txop = cpu_to_le16(txop);
2e484c89
LB		 2447 if (priv->ap_fw) {
2448 cmd->ap.log_cw_max = cpu_to_le32(ilog2(cw_max + 1));
2449 cmd->ap.log_cw_min = cpu_to_le32(ilog2(cw_min + 1));
2450 cmd->ap.aifs = aifs;
2451 cmd->ap.txq = qnum;
2452 } else {
2453 cmd->sta.log_cw_max = (u8)ilog2(cw_max + 1);
2454 cmd->sta.log_cw_min = (u8)ilog2(cw_min + 1);
2455 cmd->sta.aifs = aifs;
2456 cmd->sta.txq = qnum;
2457 }
a66098da
LB		 2458
2459 rc = mwl8k_post_cmd(hw, &cmd->header);
2460 kfree(cmd);
2461
2462 return rc;
2463}
2464
2465/*
55489b6e 2466 * CMD_SET_WMM_MODE.
a66098da 2467 */
55489b6e 2468struct mwl8k_cmd_set_wmm_mode {
a66098da 2469 struct mwl8k_cmd_pkt header;
55489b6e 2470 __le16 action;
a66098da
LB		 2471} __attribute__((packed));
2472
55489b6e 2473static int mwl8k_cmd_set_wmm_mode(struct ieee80211_hw *hw, bool enable)
a66098da 2474{
55489b6e
LB		 2475 struct mwl8k_priv *priv = hw->priv;
2476 struct mwl8k_cmd_set_wmm_mode *cmd;
a66098da
LB		 2477 int rc;
2478
a66098da
LB		 2479 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2480 if (cmd == NULL)
2481 return -ENOMEM;
2482
55489b6e 2483 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
a66098da 2484 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e 2485 cmd->action = cpu_to_le16(!!enable);
a66098da
LB		 2486
2487 rc = mwl8k_post_cmd(hw, &cmd->header);
2488 kfree(cmd);
16cec43d 2489
55489b6e
LB		 2490 if (!rc)
2491 priv->wmm_enabled = enable;
a66098da
LB		 2492
2493 return rc;
2494}
2495
2496/*
55489b6e 2497 * CMD_MIMO_CONFIG.
a66098da 2498 */
55489b6e
LB		 2499struct mwl8k_cmd_mimo_config {
2500 struct mwl8k_cmd_pkt header;
2501 __le32 action;
2502 __u8 rx_antenna_map;
2503 __u8 tx_antenna_map;
a66098da
LB		 2504} __attribute__((packed));
2505
55489b6e 2506static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
a66098da 2507{
55489b6e 2508 struct mwl8k_cmd_mimo_config *cmd;
a66098da
LB		 2509 int rc;
2510
2511 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2512 if (cmd == NULL)
2513 return -ENOMEM;
2514
55489b6e 2515 cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
a66098da 2516 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB		 2517 cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
2518 cmd->rx_antenna_map = rx;
2519 cmd->tx_antenna_map = tx;
a66098da
LB		 2520
2521 rc = mwl8k_post_cmd(hw, &cmd->header);
2522 kfree(cmd);
2523
2524 return rc;
2525}
2526
2527/*
b71ed2c6 2528 * CMD_USE_FIXED_RATE (STA version).
a66098da 2529 */
b71ed2c6
LB		 2530struct mwl8k_cmd_use_fixed_rate_sta {
2531 struct mwl8k_cmd_pkt header;
2532 __le32 action;
2533 __le32 allow_rate_drop;
2534 __le32 num_rates;
2535 struct {
2536 __le32 is_ht_rate;
2537 __le32 enable_retry;
2538 __le32 rate;
2539 __le32 retry_count;
2540 } rate_entry[8];
2541 __le32 rate_type;
2542 __le32 reserved1;
2543 __le32 reserved2;
a66098da
LB		 2544} __attribute__((packed));
2545
b71ed2c6
LB		 2546#define MWL8K_USE_AUTO_RATE 0x0002
2547#define MWL8K_UCAST_RATE 0
a66098da 2548
b71ed2c6 2549static int mwl8k_cmd_use_fixed_rate_sta(struct ieee80211_hw *hw)
a66098da 2550{
b71ed2c6 2551 struct mwl8k_cmd_use_fixed_rate_sta *cmd;
a66098da
LB		 2552 int rc;
2553
2554 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2555 if (cmd == NULL)
2556 return -ENOMEM;
2557
2558 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
2559 cmd->header.length = cpu_to_le16(sizeof(*cmd));
b71ed2c6
LB		 2560 cmd->action = cpu_to_le32(MWL8K_USE_AUTO_RATE);
2561 cmd->rate_type = cpu_to_le32(MWL8K_UCAST_RATE);
a66098da
LB		 2562
2563 rc = mwl8k_post_cmd(hw, &cmd->header);
2564 kfree(cmd);
2565
2566 return rc;
2567}
2568
088aab8b
LB		 2569/*
2570 * CMD_USE_FIXED_RATE (AP version).
2571 */
2572struct mwl8k_cmd_use_fixed_rate_ap {
2573 struct mwl8k_cmd_pkt header;
2574 __le32 action;
2575 __le32 allow_rate_drop;
2576 __le32 num_rates;
2577 struct mwl8k_rate_entry_ap {
2578 __le32 is_ht_rate;
2579 __le32 enable_retry;
2580 __le32 rate;
2581 __le32 retry_count;
2582 } rate_entry[4];
2583 u8 multicast_rate;
2584 u8 multicast_rate_type;
2585 u8 management_rate;
2586} __attribute__((packed));
2587
2588static int
2589mwl8k_cmd_use_fixed_rate_ap(struct ieee80211_hw *hw, int mcast, int mgmt)
2590{
2591 struct mwl8k_cmd_use_fixed_rate_ap *cmd;
2592 int rc;
2593
2594 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2595 if (cmd == NULL)
2596 return -ENOMEM;
2597
2598 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
2599 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2600 cmd->action = cpu_to_le32(MWL8K_USE_AUTO_RATE);
2601 cmd->multicast_rate = mcast;
2602 cmd->management_rate = mgmt;
2603
2604 rc = mwl8k_post_cmd(hw, &cmd->header);
2605 kfree(cmd);
2606
2607 return rc;
2608}
2609
55489b6e
LB		 2610/*
2611 * CMD_ENABLE_SNIFFER.
2612 */
2613struct mwl8k_cmd_enable_sniffer {
2614 struct mwl8k_cmd_pkt header;
2615 __le32 action;
2616} __attribute__((packed));
2617
2618static int mwl8k_cmd_enable_sniffer(struct ieee80211_hw *hw, bool enable)
2619{
2620 struct mwl8k_cmd_enable_sniffer *cmd;
2621 int rc;
2622
2623 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2624 if (cmd == NULL)
2625 return -ENOMEM;
2626
2627 cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
2628 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2629 cmd->action = cpu_to_le32(!!enable);
2630
2631 rc = mwl8k_post_cmd(hw, &cmd->header);
2632 kfree(cmd);
2633
2634 return rc;
2635}
2636
2637/*
2638 * CMD_SET_MAC_ADDR.
2639 */
2640struct mwl8k_cmd_set_mac_addr {
2641 struct mwl8k_cmd_pkt header;
2642 union {
2643 struct {
2644 __le16 mac_type;
2645 __u8 mac_addr[ETH_ALEN];
2646 } mbss;
2647 __u8 mac_addr[ETH_ALEN];
2648 };
2649} __attribute__((packed));
2650
a9e00b15
LB		 2651#define MWL8K_MAC_TYPE_PRIMARY_CLIENT 0
2652#define MWL8K_MAC_TYPE_PRIMARY_AP 2
2653
55489b6e
LB		 2654static int mwl8k_cmd_set_mac_addr(struct ieee80211_hw *hw, u8 *mac)
2655{
2656 struct mwl8k_priv *priv = hw->priv;
2657 struct mwl8k_cmd_set_mac_addr *cmd;
2658 int rc;
2659
2660 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2661 if (cmd == NULL)
2662 return -ENOMEM;
2663
2664 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR);
2665 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2666 if (priv->ap_fw) {
a9e00b15 2667 cmd->mbss.mac_type = cpu_to_le16(MWL8K_MAC_TYPE_PRIMARY_AP);
55489b6e
LB		 2668 memcpy(cmd->mbss.mac_addr, mac, ETH_ALEN);
2669 } else {
2670 memcpy(cmd->mac_addr, mac, ETH_ALEN);
2671 }
2672
2673 rc = mwl8k_post_cmd(hw, &cmd->header);
2674 kfree(cmd);
2675
2676 return rc;
2677}
2678
2679/*
2680 * CMD_SET_RATEADAPT_MODE.
2681 */
2682struct mwl8k_cmd_set_rate_adapt_mode {
2683 struct mwl8k_cmd_pkt header;
2684 __le16 action;
2685 __le16 mode;
2686} __attribute__((packed));
2687
2688static int mwl8k_cmd_set_rateadapt_mode(struct ieee80211_hw *hw, __u16 mode)
2689{
2690 struct mwl8k_cmd_set_rate_adapt_mode *cmd;
2691 int rc;
2692
2693 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2694 if (cmd == NULL)
2695 return -ENOMEM;
2696
2697 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
2698 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2699 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2700 cmd->mode = cpu_to_le16(mode);
2701
2702 rc = mwl8k_post_cmd(hw, &cmd->header);
2703 kfree(cmd);
2704
2705 return rc;
2706}
2707
b64fe619
LB		 2708/*
2709 * CMD_BSS_START.
2710 */
2711struct mwl8k_cmd_bss_start {
2712 struct mwl8k_cmd_pkt header;
2713 __le32 enable;
2714} __attribute__((packed));
2715
2716static int mwl8k_cmd_bss_start(struct ieee80211_hw *hw, int enable)
2717{
2718 struct mwl8k_cmd_bss_start *cmd;
2719 int rc;
2720
2721 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2722 if (cmd == NULL)
2723 return -ENOMEM;
2724
2725 cmd->header.code = cpu_to_le16(MWL8K_CMD_BSS_START);
2726 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2727 cmd->enable = cpu_to_le32(enable);
2728
2729 rc = mwl8k_post_cmd(hw, &cmd->header);
2730 kfree(cmd);
2731
2732 return rc;
2733}
2734
3f5610ff
LB		 2735/*
2736 * CMD_SET_NEW_STN.
2737 */
2738struct mwl8k_cmd_set_new_stn {
2739 struct mwl8k_cmd_pkt header;
2740 __le16 aid;
2741 __u8 mac_addr[6];
2742 __le16 stn_id;
2743 __le16 action;
2744 __le16 rsvd;
2745 __le32 legacy_rates;
2746 __u8 ht_rates[4];
2747 __le16 cap_info;
2748 __le16 ht_capabilities_info;
2749 __u8 mac_ht_param_info;
2750 __u8 rev;
2751 __u8 control_channel;
2752 __u8 add_channel;
2753 __le16 op_mode;
2754 __le16 stbc;
2755 __u8 add_qos_info;
2756 __u8 is_qos_sta;
2757 __le32 fw_sta_ptr;
2758} __attribute__((packed));
2759
2760#define MWL8K_STA_ACTION_ADD 0
2761#define MWL8K_STA_ACTION_REMOVE 2
2762
2763static int mwl8k_cmd_set_new_stn_add(struct ieee80211_hw *hw,
2764 struct ieee80211_vif *vif,
2765 struct ieee80211_sta *sta)
2766{
2767 struct mwl8k_cmd_set_new_stn *cmd;
2768 int rc;
2769
2770 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2771 if (cmd == NULL)
2772 return -ENOMEM;
2773
2774 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
2775 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2776 cmd->aid = cpu_to_le16(sta->aid);
2777 memcpy(cmd->mac_addr, sta->addr, ETH_ALEN);
2778 cmd->stn_id = cpu_to_le16(sta->aid);
2779 cmd->action = cpu_to_le16(MWL8K_STA_ACTION_ADD);
2780 cmd->legacy_rates = cpu_to_le32(sta->supp_rates[IEEE80211_BAND_2GHZ]);
2781 if (sta->ht_cap.ht_supported) {
2782 cmd->ht_rates[0] = sta->ht_cap.mcs.rx_mask[0];
2783 cmd->ht_rates[1] = sta->ht_cap.mcs.rx_mask[1];
2784 cmd->ht_rates[2] = sta->ht_cap.mcs.rx_mask[2];
2785 cmd->ht_rates[3] = sta->ht_cap.mcs.rx_mask[3];
2786 cmd->ht_capabilities_info = cpu_to_le16(sta->ht_cap.cap);
2787 cmd->mac_ht_param_info = (sta->ht_cap.ampdu_factor & 3) |
2788 ((sta->ht_cap.ampdu_density & 7) << 2);
2789 cmd->is_qos_sta = 1;
2790 }
2791
2792 rc = mwl8k_post_cmd(hw, &cmd->header);
2793 kfree(cmd);
2794
2795 return rc;
2796}
2797
b64fe619
LB		 2798static int mwl8k_cmd_set_new_stn_add_self(struct ieee80211_hw *hw,
2799 struct ieee80211_vif *vif)
2800{
2801 struct mwl8k_cmd_set_new_stn *cmd;
2802 int rc;
2803
2804 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2805 if (cmd == NULL)
2806 return -ENOMEM;
2807
2808 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
2809 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2810 memcpy(cmd->mac_addr, vif->addr, ETH_ALEN);
2811
2812 rc = mwl8k_post_cmd(hw, &cmd->header);
2813 kfree(cmd);
2814
2815 return rc;
2816}
2817
3f5610ff
LB		 2818static int mwl8k_cmd_set_new_stn_del(struct ieee80211_hw *hw,
2819 struct ieee80211_vif *vif, u8 *addr)
2820{
2821 struct mwl8k_cmd_set_new_stn *cmd;
2822 int rc;
2823
2824 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2825 if (cmd == NULL)
2826 return -ENOMEM;
2827
2828 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
2829 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2830 memcpy(cmd->mac_addr, addr, ETH_ALEN);
2831 cmd->action = cpu_to_le16(MWL8K_STA_ACTION_REMOVE);
2832
2833 rc = mwl8k_post_cmd(hw, &cmd->header);
2834 kfree(cmd);
2835
2836 return rc;
2837}
2838
55489b6e
LB		 2839/*
2840 * CMD_UPDATE_STADB.
2841 */
25d81b1e
LB		 2842struct ewc_ht_info {
2843 __le16 control1;
2844 __le16 control2;
2845 __le16 control3;
2846} __attribute__((packed));
2847
2848struct peer_capability_info {
2849 /* Peer type - AP vs. STA. */
2850 __u8 peer_type;
2851
2852 /* Basic 802.11 capabilities from assoc resp. */
2853 __le16 basic_caps;
2854
2855 /* Set if peer supports 802.11n high throughput (HT). */
2856 __u8 ht_support;
2857
2858 /* Valid if HT is supported. */
2859 __le16 ht_caps;
2860 __u8 extended_ht_caps;
2861 struct ewc_ht_info ewc_info;
2862
2863 /* Legacy rate table. Intersection of our rates and peer rates. */
2864 __u8 legacy_rates[12];
2865
2866 /* HT rate table. Intersection of our rates and peer rates. */
2867 __u8 ht_rates[16];
2868 __u8 pad[16];
2869
2870 /* If set, interoperability mode, no proprietary extensions. */
2871 __u8 interop;
2872 __u8 pad2;
2873 __u8 station_id;
2874 __le16 amsdu_enabled;
2875} __attribute__((packed));
2876
55489b6e
LB		 2877struct mwl8k_cmd_update_stadb {
2878 struct mwl8k_cmd_pkt header;
2879
2880 /* See STADB_ACTION_TYPE */
2881 __le32 action;
2882
2883 /* Peer MAC address */
2884 __u8 peer_addr[ETH_ALEN];
2885
2886 __le32 reserved;
2887
2888 /* Peer info - valid during add/update. */
2889 struct peer_capability_info peer_info;
2890} __attribute__((packed));
2891
a680400e
LB		 2892#define MWL8K_STA_DB_MODIFY_ENTRY 1
2893#define MWL8K_STA_DB_DEL_ENTRY 2
2894
2895/* Peer Entry flags - used to define the type of the peer node */
2896#define MWL8K_PEER_TYPE_ACCESSPOINT 2
2897
2898static int mwl8k_cmd_update_stadb_add(struct ieee80211_hw *hw,
c6e96010 2899 struct ieee80211_vif *vif,
13935e2c 2900 struct ieee80211_sta *sta)
55489b6e 2901{
55489b6e 2902 struct mwl8k_cmd_update_stadb *cmd;
a680400e 2903 struct peer_capability_info *p;
55489b6e
LB		 2904 int rc;
2905
2906 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2907 if (cmd == NULL)
2908 return -ENOMEM;
2909
2910 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
2911 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a680400e 2912 cmd->action = cpu_to_le32(MWL8K_STA_DB_MODIFY_ENTRY);
13935e2c 2913 memcpy(cmd->peer_addr, sta->addr, ETH_ALEN);
55489b6e 2914
a680400e
LB		 2915 p = &cmd->peer_info;
2916 p->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
2917 p->basic_caps = cpu_to_le16(vif->bss_conf.assoc_capability);
13935e2c
LB		 2918 p->ht_support = sta->ht_cap.ht_supported;
2919 p->ht_caps = sta->ht_cap.cap;
2920 p->extended_ht_caps = (sta->ht_cap.ampdu_factor & 3) |
2921 ((sta->ht_cap.ampdu_density & 7) << 2);
2922 legacy_rate_mask_to_array(p->legacy_rates,
2923 sta->supp_rates[IEEE80211_BAND_2GHZ]);
2924 memcpy(p->ht_rates, sta->ht_cap.mcs.rx_mask, 16);
a680400e
LB		 2925 p->interop = 1;
2926 p->amsdu_enabled = 0;
2927
2928 rc = mwl8k_post_cmd(hw, &cmd->header);
2929 kfree(cmd);
2930
2931 return rc ? rc : p->station_id;
2932}
2933
2934static int mwl8k_cmd_update_stadb_del(struct ieee80211_hw *hw,
2935 struct ieee80211_vif *vif, u8 *addr)
2936{
2937 struct mwl8k_cmd_update_stadb *cmd;
2938 int rc;
2939
2940 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2941 if (cmd == NULL)
2942 return -ENOMEM;
2943
2944 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
2945 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2946 cmd->action = cpu_to_le32(MWL8K_STA_DB_DEL_ENTRY);
bbfd9128 2947 memcpy(cmd->peer_addr, addr, ETH_ALEN);
55489b6e 2948
a680400e 2949 rc = mwl8k_post_cmd(hw, &cmd->header);
55489b6e
LB		 2950 kfree(cmd);
2951
2952 return rc;
2953}
2954
a66098da
LB		 2955
2956/*
2957 * Interrupt handling.
2958 */
2959static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
2960{
2961 struct ieee80211_hw *hw = dev_id;
2962 struct mwl8k_priv *priv = hw->priv;
2963 u32 status;
2964
2965 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
a66098da
LB		 2966 if (!status)
2967 return IRQ_NONE;
2968
1e9f9de3
LB		 2969 if (status & MWL8K_A2H_INT_TX_DONE) {
2970 status &= ~MWL8K_A2H_INT_TX_DONE;
2971 tasklet_schedule(&priv->poll_tx_task);
2972 }
2973
a66098da 2974 if (status & MWL8K_A2H_INT_RX_READY) {
67e2eb27
LB		 2975 status &= ~MWL8K_A2H_INT_RX_READY;
2976 tasklet_schedule(&priv->poll_rx_task);
a66098da
LB		 2977 }
2978
67e2eb27
LB		 2979 if (status)
2980 iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2981
a66098da 2982 if (status & MWL8K_A2H_INT_OPC_DONE) {
618952a7 2983 if (priv->hostcmd_wait != NULL)
a66098da 2984 complete(priv->hostcmd_wait);
a66098da
LB		 2985 }
2986
2987 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
618952a7 2988 if (!mutex_is_locked(&priv->fw_mutex) &&
88de754a 2989 priv->radio_on && priv->pending_tx_pkts)
618952a7 2990 mwl8k_tx_start(priv);
a66098da
LB		 2991 }
2992
2993 return IRQ_HANDLED;
2994}
2995
1e9f9de3
LB		 2996static void mwl8k_tx_poll(unsigned long data)
2997{
2998 struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
2999 struct mwl8k_priv *priv = hw->priv;
3000 int limit;
3001 int i;
3002
3003 limit = 32;
3004
3005 spin_lock_bh(&priv->tx_lock);
3006
3007 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3008 limit -= mwl8k_txq_reclaim(hw, i, limit, 0);
3009
3010 if (!priv->pending_tx_pkts && priv->tx_wait != NULL) {
3011 complete(priv->tx_wait);
3012 priv->tx_wait = NULL;
3013 }
3014
3015 spin_unlock_bh(&priv->tx_lock);
3016
3017 if (limit) {
3018 writel(~MWL8K_A2H_INT_TX_DONE,
3019 priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
3020 } else {
3021 tasklet_schedule(&priv->poll_tx_task);
3022 }
3023}
3024
67e2eb27
LB		 3025static void mwl8k_rx_poll(unsigned long data)
3026{
3027 struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
3028 struct mwl8k_priv *priv = hw->priv;
3029 int limit;
3030
3031 limit = 32;
3032 limit -= rxq_process(hw, 0, limit);
3033 limit -= rxq_refill(hw, 0, limit);
3034
3035 if (limit) {
3036 writel(~MWL8K_A2H_INT_RX_READY,
3037 priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
3038 } else {
3039 tasklet_schedule(&priv->poll_rx_task);
3040 }
3041}
3042
a66098da
LB		 3043
3044/*
3045 * Core driver operations.
3046 */
3047static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
3048{
3049 struct mwl8k_priv *priv = hw->priv;
3050 int index = skb_get_queue_mapping(skb);
3051 int rc;
3052
3053 if (priv->current_channel == NULL) {
3054 printk(KERN_DEBUG "%s: dropped TX frame since radio "
c2c357ce 3055 "disabled\n", wiphy_name(hw->wiphy));
a66098da
LB		 3056 dev_kfree_skb(skb);
3057 return NETDEV_TX_OK;
3058 }
3059
3060 rc = mwl8k_txq_xmit(hw, index, skb);
3061
3062 return rc;
3063}
3064
a66098da
LB		 3065static int mwl8k_start(struct ieee80211_hw *hw)
3066{
a66098da
LB		 3067 struct mwl8k_priv *priv = hw->priv;
3068 int rc;
3069
a0607fd3 3070 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
a66098da
LB		 3071 IRQF_SHARED, MWL8K_NAME, hw);
3072 if (rc) {
3073 printk(KERN_ERR "%s: failed to register IRQ handler\n",
c2c357ce 3074 wiphy_name(hw->wiphy));
2ec610cb 3075 return -EIO;
a66098da
LB		 3076 }
3077
67e2eb27 3078 /* Enable TX reclaim and RX tasklets. */
1e9f9de3 3079 tasklet_enable(&priv->poll_tx_task);
67e2eb27 3080 tasklet_enable(&priv->poll_rx_task);
2ec610cb 3081
a66098da 3082 /* Enable interrupts */
c23b5a69 3083 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da 3084
2ec610cb
LB		 3085 rc = mwl8k_fw_lock(hw);
3086 if (!rc) {
55489b6e 3087 rc = mwl8k_cmd_radio_enable(hw);
a66098da 3088
5e4cf166
LB		 3089 if (!priv->ap_fw) {
3090 if (!rc)
55489b6e 3091 rc = mwl8k_cmd_enable_sniffer(hw, 0);
a66098da 3092
5e4cf166
LB		 3093 if (!rc)
3094 rc = mwl8k_cmd_set_pre_scan(hw);
3095
3096 if (!rc)
3097 rc = mwl8k_cmd_set_post_scan(hw,
3098 "\x00\x00\x00\x00\x00\x00");
3099 }
2ec610cb
LB		 3100
3101 if (!rc)
55489b6e 3102 rc = mwl8k_cmd_set_rateadapt_mode(hw, 0);
a66098da 3103
2ec610cb 3104 if (!rc)
55489b6e 3105 rc = mwl8k_cmd_set_wmm_mode(hw, 0);
a66098da 3106
2ec610cb
LB		 3107 mwl8k_fw_unlock(hw);
3108 }
3109
3110 if (rc) {
3111 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3112 free_irq(priv->pdev->irq, hw);
1e9f9de3 3113 tasklet_disable(&priv->poll_tx_task);
67e2eb27 3114 tasklet_disable(&priv->poll_rx_task);
2ec610cb 3115 }
a66098da
LB		 3116
3117 return rc;
3118}
3119
a66098da
LB		 3120static void mwl8k_stop(struct ieee80211_hw *hw)
3121{
a66098da
LB		 3122 struct mwl8k_priv *priv = hw->priv;
3123 int i;
3124
55489b6e 3125 mwl8k_cmd_radio_disable(hw);
a66098da
LB		 3126
3127 ieee80211_stop_queues(hw);
3128
a66098da 3129 /* Disable interrupts */
a66098da 3130 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3131 free_irq(priv->pdev->irq, hw);
3132
3133 /* Stop finalize join worker */
3134 cancel_work_sync(&priv->finalize_join_worker);
3135 if (priv->beacon_skb != NULL)
3136 dev_kfree_skb(priv->beacon_skb);
3137
67e2eb27 3138 /* Stop TX reclaim and RX tasklets. */
1e9f9de3 3139 tasklet_disable(&priv->poll_tx_task);
67e2eb27 3140 tasklet_disable(&priv->poll_rx_task);
a66098da 3141
a66098da
LB		 3142 /* Return all skbs to mac80211 */
3143 for (i = 0; i < MWL8K_TX_QUEUES; i++)
efb7c49a 3144 mwl8k_txq_reclaim(hw, i, INT_MAX, 1);
a66098da
LB		 3145}
3146
3147static int mwl8k_add_interface(struct ieee80211_hw *hw,
1ed32e4f 3148 struct ieee80211_vif *vif)
a66098da
LB		 3149{
3150 struct mwl8k_priv *priv = hw->priv;
3151 struct mwl8k_vif *mwl8k_vif;
3152
3153 /*
3154 * We only support one active interface at a time.
3155 */
3156 if (priv->vif != NULL)
3157 return -EBUSY;
3158
a43c49a8
LB		 3159 /*
3160 * Reject interface creation if sniffer mode is active, as
3161 * STA operation is mutually exclusive with hardware sniffer
b64fe619 3162 * mode. (Sniffer mode is only used on STA firmware.)
a43c49a8
LB		 3163 */
3164 if (priv->sniffer_enabled) {
3165 printk(KERN_INFO "%s: unable to create STA "
3166 "interface due to sniffer mode being enabled\n",
3167 wiphy_name(hw->wiphy));
3168 return -EINVAL;
3169 }
3170
c2c2b12a
LB		 3171 /* Set the mac address. */
3172 mwl8k_cmd_set_mac_addr(hw, vif->addr);
3173
b64fe619
LB		 3174 if (priv->ap_fw)
3175 mwl8k_cmd_set_new_stn_add_self(hw, vif);
3176
a66098da 3177 /* Clean out driver private area */
1ed32e4f 3178 mwl8k_vif = MWL8K_VIF(vif);
a66098da
LB		 3179 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
3180
a66098da
LB		 3181 /* Set Initial sequence number to zero */
3182 mwl8k_vif->seqno = 0;
3183
1ed32e4f 3184 priv->vif = vif;
a66098da
LB		 3185 priv->current_channel = NULL;
3186
3187 return 0;
3188}
3189
3190static void mwl8k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 3191 struct ieee80211_vif *vif)
a66098da
LB		 3192{
3193 struct mwl8k_priv *priv = hw->priv;
3194
b64fe619
LB		 3195 if (priv->ap_fw)
3196 mwl8k_cmd_set_new_stn_del(hw, vif, vif->addr);
3197
55489b6e 3198 mwl8k_cmd_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
32060e1b 3199
a66098da
LB		 3200 priv->vif = NULL;
3201}
3202
ee03a932 3203static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
a66098da 3204{
a66098da
LB		 3205 struct ieee80211_conf *conf = &hw->conf;
3206 struct mwl8k_priv *priv = hw->priv;
ee03a932 3207 int rc;
a66098da 3208
7595d67a 3209 if (conf->flags & IEEE80211_CONF_IDLE) {
55489b6e 3210 mwl8k_cmd_radio_disable(hw);
7595d67a 3211 priv->current_channel = NULL;
ee03a932 3212 return 0;
7595d67a
LB		 3213 }
3214
ee03a932
LB		 3215 rc = mwl8k_fw_lock(hw);
3216 if (rc)
3217 return rc;
a66098da 3218
55489b6e 3219 rc = mwl8k_cmd_radio_enable(hw);
ee03a932
LB		 3220 if (rc)
3221 goto out;
a66098da 3222
610677d2 3223 rc = mwl8k_cmd_set_rf_channel(hw, conf);
ee03a932
LB		 3224 if (rc)
3225 goto out;
3226
3227 priv->current_channel = conf->channel;
a66098da
LB		 3228
3229 if (conf->power_level > 18)
3230 conf->power_level = 18;
55489b6e 3231 rc = mwl8k_cmd_rf_tx_power(hw, conf->power_level);
ee03a932
LB		 3232 if (rc)
3233 goto out;
a66098da 3234
08b06347
LB		 3235 if (priv->ap_fw) {
3236 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_RX, 0x7);
3237 if (!rc)
3238 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_TX, 0x7);
3239 } else {
3240 rc = mwl8k_cmd_mimo_config(hw, 0x7, 0x7);
3241 }
a66098da 3242
ee03a932
LB		 3243out:
3244 mwl8k_fw_unlock(hw);
a66098da 3245
ee03a932 3246 return rc;
a66098da
LB		 3247}
3248
b64fe619
LB		 3249static void
3250mwl8k_bss_info_changed_sta(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3251 struct ieee80211_bss_conf *info, u32 changed)
a66098da 3252{
a66098da 3253 struct mwl8k_priv *priv = hw->priv;
c3cbbe8a 3254 u32 ap_legacy_rates;
13935e2c 3255 u8 ap_mcs_rates[16];
3a980d0a
LB		 3256 int rc;
3257
c3cbbe8a 3258 if (mwl8k_fw_lock(hw))
3a980d0a 3259 return;
a66098da 3260
c3cbbe8a
LB		 3261 /*
3262 * No need to capture a beacon if we're no longer associated.
3263 */
3264 if ((changed & BSS_CHANGED_ASSOC) && !vif->bss_conf.assoc)
3265 priv->capture_beacon = false;
3a980d0a 3266
c3cbbe8a 3267 /*
13935e2c 3268 * Get the AP's legacy and MCS rates.
c3cbbe8a
LB		 3269 */
3270 ap_legacy_rates = 0;
7dc6a7a7 3271 if (vif->bss_conf.assoc) {
c6e96010 3272 struct ieee80211_sta *ap;
c6e96010 3273 rcu_read_lock();
c6e96010 3274
c3cbbe8a
LB		 3275 ap = ieee80211_find_sta(vif, vif->bss_conf.bssid);
3276 if (ap == NULL) {
3277 rcu_read_unlock();
c6e96010 3278 goto out;
c3cbbe8a
LB		 3279 }
3280
3281 ap_legacy_rates = ap->supp_rates[IEEE80211_BAND_2GHZ];
13935e2c 3282 memcpy(ap_mcs_rates, ap->ht_cap.mcs.rx_mask, 16);
c3cbbe8a
LB		 3283
3284 rcu_read_unlock();
3285 }
c6e96010 3286
c3cbbe8a 3287 if ((changed & BSS_CHANGED_ASSOC) && vif->bss_conf.assoc) {
13935e2c 3288 rc = mwl8k_cmd_set_rate(hw, vif, ap_legacy_rates, ap_mcs_rates);
3a980d0a
LB		 3289 if (rc)
3290 goto out;
a66098da 3291
b71ed2c6 3292 rc = mwl8k_cmd_use_fixed_rate_sta(hw);
3a980d0a
LB		 3293 if (rc)
3294 goto out;
c3cbbe8a 3295 }
a66098da 3296
c3cbbe8a 3297 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
7dc6a7a7
LB		 3298 rc = mwl8k_set_radio_preamble(hw,
3299 vif->bss_conf.use_short_preamble);
3a980d0a
LB		 3300 if (rc)
3301 goto out;
c3cbbe8a 3302 }
a66098da 3303
c3cbbe8a 3304 if (changed & BSS_CHANGED_ERP_SLOT) {
7dc6a7a7 3305 rc = mwl8k_cmd_set_slot(hw, vif->bss_conf.use_short_slot);
3a980d0a
LB		 3306 if (rc)
3307 goto out;
c3cbbe8a 3308 }
a66098da 3309
c3cbbe8a
LB		 3310 if (((changed & BSS_CHANGED_ASSOC) && vif->bss_conf.assoc) ||
3311 (changed & (BSS_CHANGED_ERP_CTS_PROT | BSS_CHANGED_HT))) {
3312 rc = mwl8k_cmd_set_aid(hw, vif, ap_legacy_rates);
3a980d0a
LB		 3313 if (rc)
3314 goto out;
c3cbbe8a 3315 }
a66098da 3316
c3cbbe8a
LB		 3317 if (vif->bss_conf.assoc &&
3318 (changed & (BSS_CHANGED_ASSOC | BSS_CHANGED_BEACON_INT))) {
a66098da
LB		 3319 /*
3320 * Finalize the join. Tell rx handler to process
3321 * next beacon from our BSSID.
3322 */
0a11dfc3 3323 memcpy(priv->capture_bssid, vif->bss_conf.bssid, ETH_ALEN);
a66098da 3324 priv->capture_beacon = true;
a66098da
LB		 3325 }
3326
3a980d0a
LB		 3327out:
3328 mwl8k_fw_unlock(hw);
a66098da
LB		 3329}
3330
b64fe619
LB		 3331static void
3332mwl8k_bss_info_changed_ap(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3333 struct ieee80211_bss_conf *info, u32 changed)
3334{
3335 int rc;
3336
3337 if (mwl8k_fw_lock(hw))
3338 return;
3339
3340 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
3341 rc = mwl8k_set_radio_preamble(hw,
3342 vif->bss_conf.use_short_preamble);
3343 if (rc)
3344 goto out;
3345 }
3346
3347 if (changed & BSS_CHANGED_BASIC_RATES) {
3348 int idx;
3349 int rate;
3350
3351 /*
3352 * Use lowest supported basic rate for multicasts
3353 * and management frames (such as probe responses --
3354 * beacons will always go out at 1 Mb/s).
3355 */
3356 idx = ffs(vif->bss_conf.basic_rates);
3357 rate = idx ? mwl8k_rates[idx - 1].hw_value : 2;
3358
3359 mwl8k_cmd_use_fixed_rate_ap(hw, rate, rate);
3360 }
3361
3362 if (changed & (BSS_CHANGED_BEACON_INT | BSS_CHANGED_BEACON)) {
3363 struct sk_buff *skb;
3364
3365 skb = ieee80211_beacon_get(hw, vif);
3366 if (skb != NULL) {
3367 mwl8k_cmd_set_beacon(hw, skb->data, skb->len);
3368 kfree_skb(skb);
3369 }
3370 }
3371
3372 if (changed & BSS_CHANGED_BEACON_ENABLED)
3373 mwl8k_cmd_bss_start(hw, info->enable_beacon);
3374
3375out:
3376 mwl8k_fw_unlock(hw);
3377}
3378
3379static void
3380mwl8k_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3381 struct ieee80211_bss_conf *info, u32 changed)
3382{
3383 struct mwl8k_priv *priv = hw->priv;
3384
3385 if (!priv->ap_fw)
3386 mwl8k_bss_info_changed_sta(hw, vif, info, changed);
3387 else
3388 mwl8k_bss_info_changed_ap(hw, vif, info, changed);
3389}
3390
e81cd2d6
LB		 3391static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
3392 int mc_count, struct dev_addr_list *mclist)
3393{
3394 struct mwl8k_cmd_pkt *cmd;
3395
447ced07
LB		 3396 /*
3397 * Synthesize and return a command packet that programs the
3398 * hardware multicast address filter. At this point we don't
3399 * know whether FIF_ALLMULTI is being requested, but if it is,
3400 * we'll end up throwing this packet away and creating a new
3401 * one in mwl8k_configure_filter().
3402 */
3403 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_count, mclist);
e81cd2d6
LB		 3404
3405 return (unsigned long)cmd;
3406}
3407
a43c49a8
LB		 3408static int
3409mwl8k_configure_filter_sniffer(struct ieee80211_hw *hw,
3410 unsigned int changed_flags,
3411 unsigned int *total_flags)
3412{
3413 struct mwl8k_priv *priv = hw->priv;
3414
3415 /*
3416 * Hardware sniffer mode is mutually exclusive with STA
3417 * operation, so refuse to enable sniffer mode if a STA
3418 * interface is active.
3419 */
3420 if (priv->vif != NULL) {
3421 if (net_ratelimit())
3422 printk(KERN_INFO "%s: not enabling sniffer "
3423 "mode because STA interface is active\n",
3424 wiphy_name(hw->wiphy));
3425 return 0;
3426 }
3427
3428 if (!priv->sniffer_enabled) {
55489b6e 3429 if (mwl8k_cmd_enable_sniffer(hw, 1))
a43c49a8
LB		 3430 return 0;
3431 priv->sniffer_enabled = true;
3432 }
3433
3434 *total_flags &= FIF_PROMISC_IN_BSS | FIF_ALLMULTI |
3435 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL |
3436 FIF_OTHER_BSS;
3437
3438 return 1;
3439}
3440
e6935ea1
LB		 3441static void mwl8k_configure_filter(struct ieee80211_hw *hw,
3442 unsigned int changed_flags,
3443 unsigned int *total_flags,
3444 u64 multicast)
3445{
3446 struct mwl8k_priv *priv = hw->priv;
a43c49a8
LB		 3447 struct mwl8k_cmd_pkt *cmd = (void *)(unsigned long)multicast;
3448
c0adae2c
LB		 3449 /*
3450 * AP firmware doesn't allow fine-grained control over
3451 * the receive filter.
3452 */
3453 if (priv->ap_fw) {
3454 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
3455 kfree(cmd);
3456 return;
3457 }
3458
a43c49a8
LB		 3459 /*
3460 * Enable hardware sniffer mode if FIF_CONTROL or
3461 * FIF_OTHER_BSS is requested.
3462 */
3463 if (*total_flags & (FIF_CONTROL | FIF_OTHER_BSS) &&
3464 mwl8k_configure_filter_sniffer(hw, changed_flags, total_flags)) {
3465 kfree(cmd);
3466 return;
3467 }
a66098da 3468
e6935ea1 3469 /* Clear unsupported feature flags */
447ced07 3470 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
a66098da 3471
90852f7a
LB		 3472 if (mwl8k_fw_lock(hw)) {
3473 kfree(cmd);
e6935ea1 3474 return;
90852f7a 3475 }
a66098da 3476
a43c49a8 3477 if (priv->sniffer_enabled) {
55489b6e 3478 mwl8k_cmd_enable_sniffer(hw, 0);
a43c49a8
LB		 3479 priv->sniffer_enabled = false;
3480 }
3481
e6935ea1 3482 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
77165d88
LB		 3483 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
3484 /*
3485 * Disable the BSS filter.
3486 */
e6935ea1 3487 mwl8k_cmd_set_pre_scan(hw);
77165d88 3488 } else {
0a11dfc3 3489 const u8 *bssid;
a94cc97e 3490
77165d88
LB		 3491 /*
3492 * Enable the BSS filter.
3493 *
3494 * If there is an active STA interface, use that
3495 * interface's BSSID, otherwise use a dummy one
3496 * (where the OUI part needs to be nonzero for
3497 * the BSSID to be accepted by POST_SCAN).
3498 */
3499 bssid = "\x01\x00\x00\x00\x00\x00";
a94cc97e 3500 if (priv->vif != NULL)
0a11dfc3 3501 bssid = priv->vif->bss_conf.bssid;
a94cc97e 3502
e6935ea1 3503 mwl8k_cmd_set_post_scan(hw, bssid);
a66098da
LB		 3504 }
3505 }
3506
447ced07
LB		 3507 /*
3508 * If FIF_ALLMULTI is being requested, throw away the command
3509 * packet that ->prepare_multicast() built and replace it with
3510 * a command packet that enables reception of all multicast
3511 * packets.
3512 */
3513 if (*total_flags & FIF_ALLMULTI) {
3514 kfree(cmd);
3515 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, 0, NULL);
3516 }
3517
3518 if (cmd != NULL) {
3519 mwl8k_post_cmd(hw, cmd);
3520 kfree(cmd);
e6935ea1 3521 }
a66098da 3522
e6935ea1 3523 mwl8k_fw_unlock(hw);
a66098da
LB		 3524}
3525
a66098da
LB		 3526static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
3527{
c2c2b12a 3528 return mwl8k_cmd_set_rts_threshold(hw, value);
a66098da
LB		 3529}
3530
bbfd9128
LB		 3531struct mwl8k_sta_notify_item
3532{
3533 struct list_head list;
3534 struct ieee80211_vif *vif;
3535 enum sta_notify_cmd cmd;
13935e2c 3536 struct ieee80211_sta sta;
bbfd9128
LB		 3537};
3538
3f5610ff
LB		 3539static void
3540mwl8k_do_sta_notify(struct ieee80211_hw *hw, struct mwl8k_sta_notify_item *s)
3541{
3542 struct mwl8k_priv *priv = hw->priv;
3543
3544 /*
3545 * STA firmware uses UPDATE_STADB, AP firmware uses SET_NEW_STN.
3546 */
3547 if (!priv->ap_fw && s->cmd == STA_NOTIFY_ADD) {
3548 int rc;
3549
3550 rc = mwl8k_cmd_update_stadb_add(hw, s->vif, &s->sta);
3551 if (rc >= 0) {
3552 struct ieee80211_sta *sta;
3553
3554 rcu_read_lock();
3555 sta = ieee80211_find_sta(s->vif, s->sta.addr);
3556 if (sta != NULL)
3557 MWL8K_STA(sta)->peer_id = rc;
3558 rcu_read_unlock();
3559 }
3560 } else if (!priv->ap_fw && s->cmd == STA_NOTIFY_REMOVE) {
3561 mwl8k_cmd_update_stadb_del(hw, s->vif, s->sta.addr);
3562 } else if (priv->ap_fw && s->cmd == STA_NOTIFY_ADD) {
3563 mwl8k_cmd_set_new_stn_add(hw, s->vif, &s->sta);
3564 } else if (priv->ap_fw && s->cmd == STA_NOTIFY_REMOVE) {
3565 mwl8k_cmd_set_new_stn_del(hw, s->vif, s->sta.addr);
3566 }
3567}
3568
bbfd9128
LB		 3569static void mwl8k_sta_notify_worker(struct work_struct *work)
3570{
3571 struct mwl8k_priv *priv =
3572 container_of(work, struct mwl8k_priv, sta_notify_worker);
a680400e 3573 struct ieee80211_hw *hw = priv->hw;
bbfd9128
LB		 3574
3575 spin_lock_bh(&priv->sta_notify_list_lock);
3576 while (!list_empty(&priv->sta_notify_list)) {
3577 struct mwl8k_sta_notify_item *s;
bbfd9128
LB		 3578
3579 s = list_entry(priv->sta_notify_list.next,
3580 struct mwl8k_sta_notify_item, list);
3581 list_del(&s->list);
3582
3583 spin_unlock_bh(&priv->sta_notify_list_lock);
3584
3f5610ff 3585 mwl8k_do_sta_notify(hw, s);
bbfd9128
LB		 3586 kfree(s);
3587
3588 spin_lock_bh(&priv->sta_notify_list_lock);
3589 }
3590 spin_unlock_bh(&priv->sta_notify_list_lock);
3591}
3592
3593static void
3594mwl8k_sta_notify(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3595 enum sta_notify_cmd cmd, struct ieee80211_sta *sta)
3596{
3597 struct mwl8k_priv *priv = hw->priv;
3598 struct mwl8k_sta_notify_item *s;
3599
3600 if (cmd != STA_NOTIFY_ADD && cmd != STA_NOTIFY_REMOVE)
3601 return;
3602
3603 s = kmalloc(sizeof(*s), GFP_ATOMIC);
3604 if (s != NULL) {
3605 s->vif = vif;
3606 s->cmd = cmd;
13935e2c 3607 s->sta = *sta;
bbfd9128
LB		 3608
3609 spin_lock(&priv->sta_notify_list_lock);
3610 list_add_tail(&s->list, &priv->sta_notify_list);
3611 spin_unlock(&priv->sta_notify_list_lock);
3612
3613 ieee80211_queue_work(hw, &priv->sta_notify_worker);
3614 }
3615}
3616
a66098da
LB		 3617static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue,
3618 const struct ieee80211_tx_queue_params *params)
3619{
3e4f542c 3620 struct mwl8k_priv *priv = hw->priv;
a66098da 3621 int rc;
a66098da 3622
3e4f542c
LB		 3623 rc = mwl8k_fw_lock(hw);
3624 if (!rc) {
3625 if (!priv->wmm_enabled)
55489b6e 3626 rc = mwl8k_cmd_set_wmm_mode(hw, 1);
a66098da 3627
3e4f542c 3628 if (!rc)
55489b6e
LB		 3629 rc = mwl8k_cmd_set_edca_params(hw, queue,
3630 params->cw_min,
3631 params->cw_max,
3632 params->aifs,
3633 params->txop);
3e4f542c
LB		 3634
3635 mwl8k_fw_unlock(hw);
a66098da 3636 }
3e4f542c 3637
a66098da
LB		 3638 return rc;
3639}
3640
3641static int mwl8k_get_tx_stats(struct ieee80211_hw *hw,
3642 struct ieee80211_tx_queue_stats *stats)
3643{
3644 struct mwl8k_priv *priv = hw->priv;
3645 struct mwl8k_tx_queue *txq;
3646 int index;
3647
3648 spin_lock_bh(&priv->tx_lock);
3649 for (index = 0; index < MWL8K_TX_QUEUES; index++) {
3650 txq = priv->txq + index;
45eb400d 3651 memcpy(&stats[index], &txq->stats,
a66098da
LB		 3652 sizeof(struct ieee80211_tx_queue_stats));
3653 }
3654 spin_unlock_bh(&priv->tx_lock);
a66098da 3655
954ef509 3656 return 0;
a66098da
LB		 3657}
3658
3659static int mwl8k_get_stats(struct ieee80211_hw *hw,
3660 struct ieee80211_low_level_stats *stats)
3661{
55489b6e 3662 return mwl8k_cmd_get_stat(hw, stats);
a66098da
LB		 3663}
3664
a2292d83
LB		 3665static int
3666mwl8k_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3667 enum ieee80211_ampdu_mlme_action action,
3668 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
3669{
3670 switch (action) {
3671 case IEEE80211_AMPDU_RX_START:
3672 case IEEE80211_AMPDU_RX_STOP:
3673 if (!(hw->flags & IEEE80211_HW_AMPDU_AGGREGATION))
3674 return -ENOTSUPP;
3675 return 0;
3676 default:
3677 return -ENOTSUPP;
3678 }
3679}
3680
a66098da
LB		 3681static const struct ieee80211_ops mwl8k_ops = {
3682 .tx = mwl8k_tx,
3683 .start = mwl8k_start,
3684 .stop = mwl8k_stop,
3685 .add_interface = mwl8k_add_interface,
3686 .remove_interface = mwl8k_remove_interface,
3687 .config = mwl8k_config,
a66098da 3688 .bss_info_changed = mwl8k_bss_info_changed,
3ac64bee 3689 .prepare_multicast = mwl8k_prepare_multicast,
a66098da
LB		 3690 .configure_filter = mwl8k_configure_filter,
3691 .set_rts_threshold = mwl8k_set_rts_threshold,
bbfd9128 3692 .sta_notify = mwl8k_sta_notify,
a66098da
LB		 3693 .conf_tx = mwl8k_conf_tx,
3694 .get_tx_stats = mwl8k_get_tx_stats,
3695 .get_stats = mwl8k_get_stats,
a2292d83 3696 .ampdu_action = mwl8k_ampdu_action,
a66098da
LB		 3697};
3698
a66098da
LB		 3699static void mwl8k_finalize_join_worker(struct work_struct *work)
3700{
3701 struct mwl8k_priv *priv =
3702 container_of(work, struct mwl8k_priv, finalize_join_worker);
3703 struct sk_buff *skb = priv->beacon_skb;
a66098da 3704
7dc6a7a7
LB		 3705 mwl8k_cmd_finalize_join(priv->hw, skb->data, skb->len,
3706 priv->vif->bss_conf.dtim_period);
a66098da
LB		 3707 dev_kfree_skb(skb);
3708
3709 priv->beacon_skb = NULL;
3710}
3711
bcb628d5 3712enum {
9e1b17ea
LB		 3713 MWL8363 = 0,
3714 MWL8687,
bcb628d5 3715 MWL8366,
6f6d1e9a
LB		 3716};
3717
bcb628d5 3718static struct mwl8k_device_info mwl8k_info_tbl[] __devinitdata = {
9e1b17ea
LB		 3719 [MWL8363] = {
3720 .part_name = "88w8363",
3721 .helper_image = "mwl8k/helper_8363.fw",
3722 .fw_image = "mwl8k/fmimage_8363.fw",
3723 },
49eb691c 3724 [MWL8687] = {
bcb628d5
JL		 3725 .part_name = "88w8687",
3726 .helper_image = "mwl8k/helper_8687.fw",
3727 .fw_image = "mwl8k/fmimage_8687.fw",
bcb628d5 3728 },
49eb691c 3729 [MWL8366] = {
bcb628d5
JL		 3730 .part_name = "88w8366",
3731 .helper_image = "mwl8k/helper_8366.fw",
3732 .fw_image = "mwl8k/fmimage_8366.fw",
89a91f4f 3733 .ap_rxd_ops = &rxd_8366_ap_ops,
bcb628d5 3734 },
45a390dd
LB		 3735};
3736
c92d4ede
LB		 3737MODULE_FIRMWARE("mwl8k/helper_8363.fw");
3738MODULE_FIRMWARE("mwl8k/fmimage_8363.fw");
3739MODULE_FIRMWARE("mwl8k/helper_8687.fw");
3740MODULE_FIRMWARE("mwl8k/fmimage_8687.fw");
3741MODULE_FIRMWARE("mwl8k/helper_8366.fw");
3742MODULE_FIRMWARE("mwl8k/fmimage_8366.fw");
3743
45a390dd 3744static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = {
9e1b17ea
LB		 3745 { PCI_VDEVICE(MARVELL, 0x2a0c), .driver_data = MWL8363, },
3746 { PCI_VDEVICE(MARVELL, 0x2a24), .driver_data = MWL8363, },
bcb628d5
JL		 3747 { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = MWL8687, },
3748 { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = MWL8687, },
3749 { PCI_VDEVICE(MARVELL, 0x2a40), .driver_data = MWL8366, },
3750 { },
45a390dd
LB		 3751};
3752MODULE_DEVICE_TABLE(pci, mwl8k_pci_id_table);
3753
a66098da
LB		 3754static int __devinit mwl8k_probe(struct pci_dev *pdev,
3755 const struct pci_device_id *id)
3756{
2aa7b01f 3757 static int printed_version = 0;
a66098da
LB		 3758 struct ieee80211_hw *hw;
3759 struct mwl8k_priv *priv;
a66098da
LB		 3760 int rc;
3761 int i;
2aa7b01f
LB		 3762
3763 if (!printed_version) {
3764 printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
3765 printed_version = 1;
3766 }
a66098da 3767
be695fc4 3768
a66098da
LB		 3769 rc = pci_enable_device(pdev);
3770 if (rc) {
3771 printk(KERN_ERR "%s: Cannot enable new PCI device\n",
3772 MWL8K_NAME);
3773 return rc;
3774 }
3775
3776 rc = pci_request_regions(pdev, MWL8K_NAME);
3777 if (rc) {
3778 printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
3779 MWL8K_NAME);
3db95e50 3780 goto err_disable_device;
a66098da
LB		 3781 }
3782
3783 pci_set_master(pdev);
3784
be695fc4 3785
a66098da
LB		 3786 hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
3787 if (hw == NULL) {
3788 printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
3789 rc = -ENOMEM;
3790 goto err_free_reg;
3791 }
3792
be695fc4
LB		 3793 SET_IEEE80211_DEV(hw, &pdev->dev);
3794 pci_set_drvdata(pdev, hw);
3795
a66098da
LB		 3796 priv = hw->priv;
3797 priv->hw = hw;
3798 priv->pdev = pdev;
bcb628d5 3799 priv->device_info = &mwl8k_info_tbl[id->driver_data];
a66098da 3800
a66098da 3801
5b9482dd
LB		 3802 priv->sram = pci_iomap(pdev, 0, 0x10000);
3803 if (priv->sram == NULL) {
3804 printk(KERN_ERR "%s: Cannot map device SRAM\n",
c2c357ce 3805 wiphy_name(hw->wiphy));
a66098da
LB		 3806 goto err_iounmap;
3807 }
3808
5b9482dd
LB		 3809 /*
3810 * If BAR0 is a 32 bit BAR, the register BAR will be BAR1.
3811 * If BAR0 is a 64 bit BAR, the register BAR will be BAR2.
3812 */
3813 priv->regs = pci_iomap(pdev, 1, 0x10000);
3814 if (priv->regs == NULL) {
3815 priv->regs = pci_iomap(pdev, 2, 0x10000);
3816 if (priv->regs == NULL) {
3817 printk(KERN_ERR "%s: Cannot map device registers\n",
3818 wiphy_name(hw->wiphy));
3819 goto err_iounmap;
3820 }
3821 }
3822
be695fc4
LB		 3823
3824 /* Reset firmware and hardware */
3825 mwl8k_hw_reset(priv);
3826
3827 /* Ask userland hotplug daemon for the device firmware */
3828 rc = mwl8k_request_firmware(priv);
3829 if (rc) {
3830 printk(KERN_ERR "%s: Firmware files not found\n",
3831 wiphy_name(hw->wiphy));
3832 goto err_stop_firmware;
3833 }
3834
3835 /* Load firmware into hardware */
3836 rc = mwl8k_load_firmware(hw);
3837 if (rc) {
3838 printk(KERN_ERR "%s: Cannot start firmware\n",
3839 wiphy_name(hw->wiphy));
3840 goto err_stop_firmware;
3841 }
3842
3843 /* Reclaim memory once firmware is successfully loaded */
3844 mwl8k_release_firmware(priv);
3845
3846
91942230 3847 if (priv->ap_fw) {
89a91f4f 3848 priv->rxd_ops = priv->device_info->ap_rxd_ops;
91942230
LB		 3849 if (priv->rxd_ops == NULL) {
3850 printk(KERN_ERR "%s: Driver does not have AP "
3851 "firmware image support for this hardware\n",
3852 wiphy_name(hw->wiphy));
3853 goto err_stop_firmware;
3854 }
3855 } else {
89a91f4f 3856 priv->rxd_ops = &rxd_sta_ops;
91942230 3857 }
be695fc4
LB		 3858
3859 priv->sniffer_enabled = false;
3860 priv->wmm_enabled = false;
3861 priv->pending_tx_pkts = 0;
3862
3863
a66098da
LB		 3864 memcpy(priv->channels, mwl8k_channels, sizeof(mwl8k_channels));
3865 priv->band.band = IEEE80211_BAND_2GHZ;
3866 priv->band.channels = priv->channels;
3867 priv->band.n_channels = ARRAY_SIZE(mwl8k_channels);
3868 priv->band.bitrates = priv->rates;
3869 priv->band.n_bitrates = ARRAY_SIZE(mwl8k_rates);
3870 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
3871
3872 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(mwl8k_rates));
3873 memcpy(priv->rates, mwl8k_rates, sizeof(mwl8k_rates));
3874
3875 /*
3876 * Extra headroom is the size of the required DMA header
3877 * minus the size of the smallest 802.11 frame (CTS frame).
3878 */
3879 hw->extra_tx_headroom =
3880 sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
3881
3882 hw->channel_change_time = 10;
3883
3884 hw->queues = MWL8K_TX_QUEUES;
3885
a66098da 3886 /* Set rssi and noise values to dBm */
ce9e2e1b 3887 hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM;
a66098da 3888 hw->vif_data_size = sizeof(struct mwl8k_vif);
a680400e 3889 hw->sta_data_size = sizeof(struct mwl8k_sta);
a66098da
LB		 3890 priv->vif = NULL;
3891
3892 /* Set default radio state and preamble */
c46563b7 3893 priv->radio_on = 0;
68ce3884 3894 priv->radio_short_preamble = 0;
a66098da 3895
bbfd9128
LB		 3896 /* Station database handling */
3897 INIT_WORK(&priv->sta_notify_worker, mwl8k_sta_notify_worker);
3898 spin_lock_init(&priv->sta_notify_list_lock);
3899 INIT_LIST_HEAD(&priv->sta_notify_list);
3900
a66098da
LB		 3901 /* Finalize join worker */
3902 INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
3903
67e2eb27 3904 /* TX reclaim and RX tasklets. */
1e9f9de3
LB		 3905 tasklet_init(&priv->poll_tx_task, mwl8k_tx_poll, (unsigned long)hw);
3906 tasklet_disable(&priv->poll_tx_task);
67e2eb27
LB		 3907 tasklet_init(&priv->poll_rx_task, mwl8k_rx_poll, (unsigned long)hw);
3908 tasklet_disable(&priv->poll_rx_task);
a66098da 3909
a66098da
LB		 3910 /* Power management cookie */
3911 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
3912 if (priv->cookie == NULL)
be695fc4 3913 goto err_stop_firmware;
a66098da
LB		 3914
3915 rc = mwl8k_rxq_init(hw, 0);
3916 if (rc)
be695fc4 3917 goto err_free_cookie;
a66098da
LB		 3918 rxq_refill(hw, 0, INT_MAX);
3919
618952a7
LB		 3920 mutex_init(&priv->fw_mutex);
3921 priv->fw_mutex_owner = NULL;
3922 priv->fw_mutex_depth = 0;
618952a7
LB		 3923 priv->hostcmd_wait = NULL;
3924
a66098da
LB		 3925 spin_lock_init(&priv->tx_lock);
3926
88de754a
LB		 3927 priv->tx_wait = NULL;
3928
a66098da
LB		 3929 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
3930 rc = mwl8k_txq_init(hw, i);
3931 if (rc)
3932 goto err_free_queues;
3933 }
3934
3935 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
c23b5a69 3936 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
67e2eb27 3937 iowrite32(MWL8K_A2H_INT_TX_DONE | MWL8K_A2H_INT_RX_READY,
1e9f9de3 3938 priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
a66098da
LB		 3939 iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
3940
a0607fd3 3941 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
a66098da
LB		 3942 IRQF_SHARED, MWL8K_NAME, hw);
3943 if (rc) {
3944 printk(KERN_ERR "%s: failed to register IRQ handler\n",
c2c357ce 3945 wiphy_name(hw->wiphy));
a66098da
LB		 3946 goto err_free_queues;
3947 }
3948
a66098da
LB		 3949 /*
3950 * Temporarily enable interrupts. Initial firmware host
c2c2b12a 3951 * commands use interrupts and avoid polling. Disable
a66098da
LB		 3952 * interrupts when done.
3953 */
c23b5a69 3954 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3955
3956 /* Get config data, mac addrs etc */
42fba21d
LB		 3957 if (priv->ap_fw) {
3958 rc = mwl8k_cmd_get_hw_spec_ap(hw);
3959 if (!rc)
3960 rc = mwl8k_cmd_set_hw_spec(hw);
b64fe619
LB		 3961
3962 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_AP);
42fba21d
LB		 3963 } else {
3964 rc = mwl8k_cmd_get_hw_spec_sta(hw);
89a91f4f
LB		 3965
3966 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
42fba21d 3967 }
a66098da 3968 if (rc) {
c2c357ce
LB		 3969 printk(KERN_ERR "%s: Cannot initialise firmware\n",
3970 wiphy_name(hw->wiphy));
be695fc4 3971 goto err_free_irq;
a66098da
LB		 3972 }
3973
3974 /* Turn radio off */
55489b6e 3975 rc = mwl8k_cmd_radio_disable(hw);
a66098da 3976 if (rc) {
c2c357ce 3977 printk(KERN_ERR "%s: Cannot disable\n", wiphy_name(hw->wiphy));
be695fc4 3978 goto err_free_irq;
a66098da
LB		 3979 }
3980
32060e1b 3981 /* Clear MAC address */
55489b6e 3982 rc = mwl8k_cmd_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
32060e1b
LB		 3983 if (rc) {
3984 printk(KERN_ERR "%s: Cannot clear MAC address\n",
3985 wiphy_name(hw->wiphy));
be695fc4 3986 goto err_free_irq;
32060e1b
LB		 3987 }
3988
a66098da 3989 /* Disable interrupts */
a66098da 3990 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3991 free_irq(priv->pdev->irq, hw);
3992
3993 rc = ieee80211_register_hw(hw);
3994 if (rc) {
c2c357ce
LB		 3995 printk(KERN_ERR "%s: Cannot register device\n",
3996 wiphy_name(hw->wiphy));
153458ff 3997 goto err_free_queues;
a66098da
LB		 3998 }
3999
eae74e65 4000 printk(KERN_INFO "%s: %s v%d, %pM, %s firmware %u.%u.%u.%u\n",
a74b295e 4001 wiphy_name(hw->wiphy), priv->device_info->part_name,
45a390dd 4002 priv->hw_rev, hw->wiphy->perm_addr,
eae74e65 4003 priv->ap_fw ? "AP" : "STA",
2aa7b01f
LB		 4004 (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff,
4005 (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff);
a66098da
LB		 4006
4007 return 0;
4008
a66098da 4009err_free_irq:
a66098da 4010 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 4011 free_irq(priv->pdev->irq, hw);
4012
4013err_free_queues:
4014 for (i = 0; i < MWL8K_TX_QUEUES; i++)
4015 mwl8k_txq_deinit(hw, i);
4016 mwl8k_rxq_deinit(hw, 0);
4017
be695fc4 4018err_free_cookie:
a66098da
LB		 4019 if (priv->cookie != NULL)
4020 pci_free_consistent(priv->pdev, 4,
4021 priv->cookie, priv->cookie_dma);
4022
be695fc4
LB		 4023err_stop_firmware:
4024 mwl8k_hw_reset(priv);
4025 mwl8k_release_firmware(priv);
4026
4027err_iounmap:
a66098da
LB		 4028 if (priv->regs != NULL)
4029 pci_iounmap(pdev, priv->regs);
4030
5b9482dd
LB		 4031 if (priv->sram != NULL)
4032 pci_iounmap(pdev, priv->sram);
4033
a66098da
LB		 4034 pci_set_drvdata(pdev, NULL);
4035 ieee80211_free_hw(hw);
4036
4037err_free_reg:
4038 pci_release_regions(pdev);
3db95e50
LB		 4039
4040err_disable_device:
a66098da
LB		 4041 pci_disable_device(pdev);
4042
4043 return rc;
4044}
4045
230f7af0 4046static void __devexit mwl8k_shutdown(struct pci_dev *pdev)
a66098da
LB		 4047{
4048 printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__);
4049}
4050
230f7af0 4051static void __devexit mwl8k_remove(struct pci_dev *pdev)
a66098da
LB		 4052{
4053 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
4054 struct mwl8k_priv *priv;
4055 int i;
4056
4057 if (hw == NULL)
4058 return;
4059 priv = hw->priv;
4060
4061 ieee80211_stop_queues(hw);
4062
60aa569f
LB		 4063 ieee80211_unregister_hw(hw);
4064
67e2eb27 4065 /* Remove TX reclaim and RX tasklets. */
1e9f9de3 4066 tasklet_kill(&priv->poll_tx_task);
67e2eb27 4067 tasklet_kill(&priv->poll_rx_task);
a66098da 4068
a66098da
LB		 4069 /* Stop hardware */
4070 mwl8k_hw_reset(priv);
4071
4072 /* Return all skbs to mac80211 */
4073 for (i = 0; i < MWL8K_TX_QUEUES; i++)
efb7c49a 4074 mwl8k_txq_reclaim(hw, i, INT_MAX, 1);
a66098da 4075
a66098da
LB		 4076 for (i = 0; i < MWL8K_TX_QUEUES; i++)
4077 mwl8k_txq_deinit(hw, i);
4078
4079 mwl8k_rxq_deinit(hw, 0);
4080
c2c357ce 4081 pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma);
a66098da
LB		 4082
4083 pci_iounmap(pdev, priv->regs);
5b9482dd 4084 pci_iounmap(pdev, priv->sram);
a66098da
LB		 4085 pci_set_drvdata(pdev, NULL);
4086 ieee80211_free_hw(hw);
4087 pci_release_regions(pdev);
4088 pci_disable_device(pdev);
4089}
4090
4091static struct pci_driver mwl8k_driver = {
4092 .name = MWL8K_NAME,
45a390dd 4093 .id_table = mwl8k_pci_id_table,
a66098da
LB		 4094 .probe = mwl8k_probe,
4095 .remove = __devexit_p(mwl8k_remove),
4096 .shutdown = __devexit_p(mwl8k_shutdown),
4097};
4098
4099static int __init mwl8k_init(void)
4100{
4101 return pci_register_driver(&mwl8k_driver);
4102}
4103
4104static void __exit mwl8k_exit(void)
4105{
4106 pci_unregister_driver(&mwl8k_driver);
4107}
4108
4109module_init(mwl8k_init);
4110module_exit(mwl8k_exit);
c2c357ce
LB		 4111
4112MODULE_DESCRIPTION(MWL8K_DESC);
4113MODULE_VERSION(MWL8K_VERSION);
4114MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
4115MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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