projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
mwl8k: Set mac80211 rx status flags appropriately when hw crypto is enabled
[deliverable/linux.git] / drivers / net / wireless / mwl8k.c
CommitLineData
a66098da 1/*
ce9e2e1b
LB		 2 * drivers/net/wireless/mwl8k.c
3 * Driver for Marvell TOPDOG 802.11 Wireless cards
a66098da 4 *
a5fb297d 5 * Copyright (C) 2008, 2009, 2010 Marvell Semiconductor Inc.
a66098da
LB		 6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
3d76e82c 15#include <linux/sched.h>
a66098da
LB		 16#include <linux/spinlock.h>
17#include <linux/list.h>
18#include <linux/pci.h>
19#include <linux/delay.h>
20#include <linux/completion.h>
21#include <linux/etherdevice.h>
5a0e3ad6 22#include <linux/slab.h>
a66098da
LB		 23#include <net/mac80211.h>
24#include <linux/moduleparam.h>
25#include <linux/firmware.h>
26#include <linux/workqueue.h>
27
28#define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
29#define MWL8K_NAME KBUILD_MODNAME
a5fb297d 30#define MWL8K_VERSION "0.12"
a66098da 31
0863ade8
BC		 32/* Module parameters */
33static unsigned ap_mode_default;
34module_param(ap_mode_default, bool, 0);
35MODULE_PARM_DESC(ap_mode_default,
36 "Set to 1 to make ap mode the default instead of sta mode");
37
a66098da
LB		 38/* Register definitions */
39#define MWL8K_HIU_GEN_PTR 0x00000c10
ce9e2e1b
LB		 40#define MWL8K_MODE_STA 0x0000005a
41#define MWL8K_MODE_AP 0x000000a5
a66098da 42#define MWL8K_HIU_INT_CODE 0x00000c14
ce9e2e1b
LB		 43#define MWL8K_FWSTA_READY 0xf0f1f2f4
44#define MWL8K_FWAP_READY 0xf1f2f4a5
45#define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
a66098da
LB		 46#define MWL8K_HIU_SCRATCH 0x00000c40
47
48/* Host->device communications */
49#define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
50#define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
51#define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
52#define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
53#define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
ce9e2e1b
LB		 54#define MWL8K_H2A_INT_DUMMY (1 << 20)
55#define MWL8K_H2A_INT_RESET (1 << 15)
56#define MWL8K_H2A_INT_DOORBELL (1 << 1)
57#define MWL8K_H2A_INT_PPA_READY (1 << 0)
a66098da
LB		 58
59/* Device->host communications */
60#define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
61#define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
62#define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
63#define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
64#define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
ce9e2e1b
LB		 65#define MWL8K_A2H_INT_DUMMY (1 << 20)
66#define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
67#define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
68#define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
69#define MWL8K_A2H_INT_RADIO_ON (1 << 6)
70#define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
71#define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
72#define MWL8K_A2H_INT_OPC_DONE (1 << 2)
73#define MWL8K_A2H_INT_RX_READY (1 << 1)
74#define MWL8K_A2H_INT_TX_DONE (1 << 0)
a66098da
LB		 75
76#define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
77 MWL8K_A2H_INT_CHNL_SWITCHED | \
78 MWL8K_A2H_INT_QUEUE_EMPTY | \
79 MWL8K_A2H_INT_RADAR_DETECT | \
80 MWL8K_A2H_INT_RADIO_ON | \
81 MWL8K_A2H_INT_RADIO_OFF | \
82 MWL8K_A2H_INT_MAC_EVENT | \
83 MWL8K_A2H_INT_OPC_DONE | \
84 MWL8K_A2H_INT_RX_READY | \
85 MWL8K_A2H_INT_TX_DONE)
86
a66098da
LB		 87#define MWL8K_RX_QUEUES 1
88#define MWL8K_TX_QUEUES 4
89
54bc3a0d
LB		 90struct rxd_ops {
91 int rxd_size;
92 void (*rxd_init)(void *rxd, dma_addr_t next_dma_addr);
93 void (*rxd_refill)(void *rxd, dma_addr_t addr, int len);
20f09c3d 94 int (*rxd_process)(void *rxd, struct ieee80211_rx_status *status,
0d462bbb 95 __le16 *qos, s8 *noise);
54bc3a0d
LB		 96};
97
45a390dd 98struct mwl8k_device_info {
a74b295e
LB		 99 char *part_name;
100 char *helper_image;
0863ade8
BC		 101 char *fw_image_sta;
102 char *fw_image_ap;
89a91f4f 103 struct rxd_ops *ap_rxd_ops;
952a0e96 104 u32 fw_api_ap;
45a390dd
LB		 105};
106
a66098da 107struct mwl8k_rx_queue {
45eb400d 108 int rxd_count;
a66098da
LB		 109
110 /* hw receives here */
45eb400d 111 int head;
a66098da
LB		 112
113 /* refill descs here */
45eb400d 114 int tail;
a66098da 115
54bc3a0d 116 void *rxd;
45eb400d 117 dma_addr_t rxd_dma;
788838eb
LB		 118 struct {
119 struct sk_buff *skb;
53b1b3e1 120 DEFINE_DMA_UNMAP_ADDR(dma);
788838eb 121 } *buf;
a66098da
LB		 122};
123
a66098da
LB		 124struct mwl8k_tx_queue {
125 /* hw transmits here */
45eb400d 126 int head;
a66098da
LB		 127
128 /* sw appends here */
45eb400d 129 int tail;
a66098da 130
8ccbc3b8 131 unsigned int len;
45eb400d
LB		 132 struct mwl8k_tx_desc *txd;
133 dma_addr_t txd_dma;
134 struct sk_buff **skb;
a66098da
LB		 135};
136
a66098da 137struct mwl8k_priv {
a66098da 138 struct ieee80211_hw *hw;
a66098da 139 struct pci_dev *pdev;
a66098da 140
45a390dd
LB		 141 struct mwl8k_device_info *device_info;
142
be695fc4
LB		 143 void __iomem *sram;
144 void __iomem *regs;
145
146 /* firmware */
d1f9e41d
BC		 147 const struct firmware *fw_helper;
148 const struct firmware *fw_ucode;
a66098da 149
be695fc4
LB		 150 /* hardware/firmware parameters */
151 bool ap_fw;
152 struct rxd_ops *rxd_ops;
777ad375
LB		 153 struct ieee80211_supported_band band_24;
154 struct ieee80211_channel channels_24[14];
155 struct ieee80211_rate rates_24[14];
4eae9edd
LB		 156 struct ieee80211_supported_band band_50;
157 struct ieee80211_channel channels_50[4];
158 struct ieee80211_rate rates_50[9];
ee0ddf18
LB		 159 u32 ap_macids_supported;
160 u32 sta_macids_supported;
be695fc4 161
618952a7
LB		 162 /* firmware access */
163 struct mutex fw_mutex;
164 struct task_struct *fw_mutex_owner;
165 int fw_mutex_depth;
618952a7
LB		 166 struct completion *hostcmd_wait;
167
a66098da
LB		 168 /* lock held over TX and TX reap */
169 spinlock_t tx_lock;
a66098da 170
88de754a
LB		 171 /* TX quiesce completion, protected by fw_mutex and tx_lock */
172 struct completion *tx_wait;
173
f5bb87cf 174 /* List of interfaces. */
ee0ddf18 175 u32 macids_used;
f5bb87cf 176 struct list_head vif_list;
a66098da 177
a66098da
LB		 178 /* power management status cookie from firmware */
179 u32 *cookie;
180 dma_addr_t cookie_dma;
181
182 u16 num_mcaddrs;
a66098da 183 u8 hw_rev;
2aa7b01f 184 u32 fw_rev;
a66098da
LB		 185
186 /*
187 * Running count of TX packets in flight, to avoid
188 * iterating over the transmit rings each time.
189 */
190 int pending_tx_pkts;
191
192 struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
193 struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES];
194
c46563b7 195 bool radio_on;
68ce3884 196 bool radio_short_preamble;
a43c49a8 197 bool sniffer_enabled;
0439b1f5 198 bool wmm_enabled;
a66098da 199
a66098da
LB		 200 /* XXX need to convert this to handle multiple interfaces */
201 bool capture_beacon;
d89173f2 202 u8 capture_bssid[ETH_ALEN];
a66098da
LB		 203 struct sk_buff *beacon_skb;
204
205 /*
206 * This FJ worker has to be global as it is scheduled from the
207 * RX handler. At this point we don't know which interface it
208 * belongs to until the list of bssids waiting to complete join
209 * is checked.
210 */
211 struct work_struct finalize_join_worker;
212
1e9f9de3
LB		 213 /* Tasklet to perform TX reclaim. */
214 struct tasklet_struct poll_tx_task;
67e2eb27
LB		 215
216 /* Tasklet to perform RX. */
217 struct tasklet_struct poll_rx_task;
0d462bbb
JL		 218
219 /* Most recently reported noise in dBm */
220 s8 noise;
0863ade8
BC		 221
222 /*
223 * preserve the queue configurations so they can be restored if/when
224 * the firmware image is swapped.
225 */
226 struct ieee80211_tx_queue_params wmm_params[MWL8K_TX_QUEUES];
99020471
BC		 227
228 /* async firmware loading state */
229 unsigned fw_state;
230 char *fw_pref;
231 char *fw_alt;
232 struct completion firmware_loading_complete;
a66098da
LB		 233};
234
e53d9b96
NS		 235#define MAX_WEP_KEY_LEN 13
236#define NUM_WEP_KEYS 4
237
a66098da
LB		 238/* Per interface specific private data */
239struct mwl8k_vif {
f5bb87cf
LB		 240 struct list_head list;
241 struct ieee80211_vif *vif;
242
f57ca9c1
LB		 243 /* Firmware macid for this vif. */
244 int macid;
245
c2c2b12a 246 /* Non AMPDU sequence number assigned by driver. */
a680400e 247 u16 seqno;
e53d9b96
NS		 248
249 /* Saved WEP keys */
250 struct {
251 u8 enabled;
252 u8 key[sizeof(struct ieee80211_key_conf) + MAX_WEP_KEY_LEN];
253 } wep_key_conf[NUM_WEP_KEYS];
d9a07d49
NS		 254
255 /* BSSID */
256 u8 bssid[ETH_ALEN];
257
258 /* A flag to indicate is HW crypto is enabled for this bssid */
259 bool is_hw_crypto_enabled;
a66098da 260};
a94cc97e 261#define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
a66098da 262
a680400e
LB		 263struct mwl8k_sta {
264 /* Index into station database. Returned by UPDATE_STADB. */
265 u8 peer_id;
266};
267#define MWL8K_STA(_sta) ((struct mwl8k_sta *)&((_sta)->drv_priv))
268
777ad375 269static const struct ieee80211_channel mwl8k_channels_24[] = {
a66098da
LB		 270 { .center_freq = 2412, .hw_value = 1, },
271 { .center_freq = 2417, .hw_value = 2, },
272 { .center_freq = 2422, .hw_value = 3, },
273 { .center_freq = 2427, .hw_value = 4, },
274 { .center_freq = 2432, .hw_value = 5, },
275 { .center_freq = 2437, .hw_value = 6, },
276 { .center_freq = 2442, .hw_value = 7, },
277 { .center_freq = 2447, .hw_value = 8, },
278 { .center_freq = 2452, .hw_value = 9, },
279 { .center_freq = 2457, .hw_value = 10, },
280 { .center_freq = 2462, .hw_value = 11, },
647ca6b0
LB		 281 { .center_freq = 2467, .hw_value = 12, },
282 { .center_freq = 2472, .hw_value = 13, },
283 { .center_freq = 2484, .hw_value = 14, },
a66098da
LB		 284};
285
777ad375 286static const struct ieee80211_rate mwl8k_rates_24[] = {
a66098da
LB		 287 { .bitrate = 10, .hw_value = 2, },
288 { .bitrate = 20, .hw_value = 4, },
289 { .bitrate = 55, .hw_value = 11, },
5dfd3e2c
LB		 290 { .bitrate = 110, .hw_value = 22, },
291 { .bitrate = 220, .hw_value = 44, },
a66098da
LB		 292 { .bitrate = 60, .hw_value = 12, },
293 { .bitrate = 90, .hw_value = 18, },
a66098da
LB		 294 { .bitrate = 120, .hw_value = 24, },
295 { .bitrate = 180, .hw_value = 36, },
296 { .bitrate = 240, .hw_value = 48, },
297 { .bitrate = 360, .hw_value = 72, },
298 { .bitrate = 480, .hw_value = 96, },
299 { .bitrate = 540, .hw_value = 108, },
140eb5e2
LB		 300 { .bitrate = 720, .hw_value = 144, },
301};
302
4eae9edd
LB		 303static const struct ieee80211_channel mwl8k_channels_50[] = {
304 { .center_freq = 5180, .hw_value = 36, },
305 { .center_freq = 5200, .hw_value = 40, },
306 { .center_freq = 5220, .hw_value = 44, },
307 { .center_freq = 5240, .hw_value = 48, },
308};
309
310static const struct ieee80211_rate mwl8k_rates_50[] = {
311 { .bitrate = 60, .hw_value = 12, },
312 { .bitrate = 90, .hw_value = 18, },
313 { .bitrate = 120, .hw_value = 24, },
314 { .bitrate = 180, .hw_value = 36, },
315 { .bitrate = 240, .hw_value = 48, },
316 { .bitrate = 360, .hw_value = 72, },
317 { .bitrate = 480, .hw_value = 96, },
318 { .bitrate = 540, .hw_value = 108, },
319 { .bitrate = 720, .hw_value = 144, },
320};
321
a66098da 322/* Set or get info from Firmware */
a66098da 323#define MWL8K_CMD_GET 0x0000
41fdf097
NS		 324#define MWL8K_CMD_SET 0x0001
325#define MWL8K_CMD_SET_LIST 0x0002
a66098da
LB		 326
327/* Firmware command codes */
328#define MWL8K_CMD_CODE_DNLD 0x0001
329#define MWL8K_CMD_GET_HW_SPEC 0x0003
42fba21d 330#define MWL8K_CMD_SET_HW_SPEC 0x0004
a66098da
LB		 331#define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
332#define MWL8K_CMD_GET_STAT 0x0014
ff45fc60
LB		 333#define MWL8K_CMD_RADIO_CONTROL 0x001c
334#define MWL8K_CMD_RF_TX_POWER 0x001e
41fdf097 335#define MWL8K_CMD_TX_POWER 0x001f
08b06347 336#define MWL8K_CMD_RF_ANTENNA 0x0020
aa21d0f6 337#define MWL8K_CMD_SET_BEACON 0x0100 /* per-vif */
a66098da
LB		 338#define MWL8K_CMD_SET_PRE_SCAN 0x0107
339#define MWL8K_CMD_SET_POST_SCAN 0x0108
ff45fc60
LB		 340#define MWL8K_CMD_SET_RF_CHANNEL 0x010a
341#define MWL8K_CMD_SET_AID 0x010d
342#define MWL8K_CMD_SET_RATE 0x0110
343#define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
344#define MWL8K_CMD_RTS_THRESHOLD 0x0113
a66098da 345#define MWL8K_CMD_SET_SLOT 0x0114
ff45fc60
LB		 346#define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
347#define MWL8K_CMD_SET_WMM_MODE 0x0123
a66098da 348#define MWL8K_CMD_MIMO_CONFIG 0x0125
ff45fc60 349#define MWL8K_CMD_USE_FIXED_RATE 0x0126
a66098da 350#define MWL8K_CMD_ENABLE_SNIFFER 0x0150
aa21d0f6 351#define MWL8K_CMD_SET_MAC_ADDR 0x0202 /* per-vif */
a66098da 352#define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
aa21d0f6
LB		 353#define MWL8K_CMD_BSS_START 0x1100 /* per-vif */
354#define MWL8K_CMD_SET_NEW_STN 0x1111 /* per-vif */
ff45fc60 355#define MWL8K_CMD_UPDATE_STADB 0x1123
a66098da 356
b603742f 357static const char *mwl8k_cmd_name(__le16 cmd, char *buf, int bufsize)
a66098da 358{
b603742f
JL		 359 u16 command = le16_to_cpu(cmd);
360
a66098da
LB		 361#define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
362 snprintf(buf, bufsize, "%s", #x);\
363 return buf;\
364 } while (0)
b603742f 365 switch (command & ~0x8000) {
a66098da
LB		 366 MWL8K_CMDNAME(CODE_DNLD);
367 MWL8K_CMDNAME(GET_HW_SPEC);
42fba21d 368 MWL8K_CMDNAME(SET_HW_SPEC);
a66098da
LB		 369 MWL8K_CMDNAME(MAC_MULTICAST_ADR);
370 MWL8K_CMDNAME(GET_STAT);
371 MWL8K_CMDNAME(RADIO_CONTROL);
372 MWL8K_CMDNAME(RF_TX_POWER);
41fdf097 373 MWL8K_CMDNAME(TX_POWER);
08b06347 374 MWL8K_CMDNAME(RF_ANTENNA);
b64fe619 375 MWL8K_CMDNAME(SET_BEACON);
a66098da
LB		 376 MWL8K_CMDNAME(SET_PRE_SCAN);
377 MWL8K_CMDNAME(SET_POST_SCAN);
378 MWL8K_CMDNAME(SET_RF_CHANNEL);
ff45fc60
LB		 379 MWL8K_CMDNAME(SET_AID);
380 MWL8K_CMDNAME(SET_RATE);
381 MWL8K_CMDNAME(SET_FINALIZE_JOIN);
382 MWL8K_CMDNAME(RTS_THRESHOLD);
a66098da 383 MWL8K_CMDNAME(SET_SLOT);
ff45fc60
LB		 384 MWL8K_CMDNAME(SET_EDCA_PARAMS);
385 MWL8K_CMDNAME(SET_WMM_MODE);
a66098da 386 MWL8K_CMDNAME(MIMO_CONFIG);
ff45fc60 387 MWL8K_CMDNAME(USE_FIXED_RATE);
a66098da 388 MWL8K_CMDNAME(ENABLE_SNIFFER);
32060e1b 389 MWL8K_CMDNAME(SET_MAC_ADDR);
a66098da 390 MWL8K_CMDNAME(SET_RATEADAPT_MODE);
b64fe619 391 MWL8K_CMDNAME(BSS_START);
3f5610ff 392 MWL8K_CMDNAME(SET_NEW_STN);
ff45fc60 393 MWL8K_CMDNAME(UPDATE_STADB);
a66098da
LB		 394 default:
395 snprintf(buf, bufsize, "0x%x", cmd);
396 }
397#undef MWL8K_CMDNAME
398
399 return buf;
400}
401
402/* Hardware and firmware reset */
403static void mwl8k_hw_reset(struct mwl8k_priv *priv)
404{
405 iowrite32(MWL8K_H2A_INT_RESET,
406 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
407 iowrite32(MWL8K_H2A_INT_RESET,
408 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
409 msleep(20);
410}
411
412/* Release fw image */
d1f9e41d 413static void mwl8k_release_fw(const struct firmware **fw)
a66098da
LB		 414{
415 if (*fw == NULL)
416 return;
417 release_firmware(*fw);
418 *fw = NULL;
419}
420
421static void mwl8k_release_firmware(struct mwl8k_priv *priv)
422{
22be40d9
LB		 423 mwl8k_release_fw(&priv->fw_ucode);
424 mwl8k_release_fw(&priv->fw_helper);
a66098da
LB		 425}
426
99020471
BC		 427/* states for asynchronous f/w loading */
428static void mwl8k_fw_state_machine(const struct firmware *fw, void *context);
429enum {
430 FW_STATE_INIT = 0,
431 FW_STATE_LOADING_PREF,
432 FW_STATE_LOADING_ALT,
433 FW_STATE_ERROR,
434};
435
a66098da
LB		 436/* Request fw image */
437static int mwl8k_request_fw(struct mwl8k_priv *priv,
d1f9e41d 438 const char *fname, const struct firmware **fw,
99020471 439 bool nowait)
a66098da
LB		 440{
441 /* release current image */
442 if (*fw != NULL)
443 mwl8k_release_fw(fw);
444
99020471
BC		 445 if (nowait)
446 return request_firmware_nowait(THIS_MODULE, 1, fname,
447 &priv->pdev->dev, GFP_KERNEL,
448 priv, mwl8k_fw_state_machine);
449 else
d1f9e41d 450 return request_firmware(fw, fname, &priv->pdev->dev);
a66098da
LB		 451}
452
99020471
BC		 453static int mwl8k_request_firmware(struct mwl8k_priv *priv, char *fw_image,
454 bool nowait)
a66098da 455{
a74b295e 456 struct mwl8k_device_info *di = priv->device_info;
a66098da
LB		 457 int rc;
458
a74b295e 459 if (di->helper_image != NULL) {
99020471
BC		 460 if (nowait)
461 rc = mwl8k_request_fw(priv, di->helper_image,
462 &priv->fw_helper, true);
463 else
464 rc = mwl8k_request_fw(priv, di->helper_image,
465 &priv->fw_helper, false);
466 if (rc)
467 printk(KERN_ERR "%s: Error requesting helper fw %s\n",
468 pci_name(priv->pdev), di->helper_image);
469
470 if (rc || nowait)
a74b295e 471 return rc;
a66098da
LB		 472 }
473
99020471
BC		 474 if (nowait) {
475 /*
476 * if we get here, no helper image is needed. Skip the
477 * FW_STATE_INIT state.
478 */
479 priv->fw_state = FW_STATE_LOADING_PREF;
480 rc = mwl8k_request_fw(priv, fw_image,
481 &priv->fw_ucode,
482 true);
483 } else
484 rc = mwl8k_request_fw(priv, fw_image,
485 &priv->fw_ucode, false);
a66098da 486 if (rc) {
c2c357ce 487 printk(KERN_ERR "%s: Error requesting firmware file %s\n",
0863ade8 488 pci_name(priv->pdev), fw_image);
22be40d9 489 mwl8k_release_fw(&priv->fw_helper);
a66098da
LB		 490 return rc;
491 }
492
493 return 0;
494}
495
496struct mwl8k_cmd_pkt {
497 __le16 code;
498 __le16 length;
f57ca9c1
LB		 499 __u8 seq_num;
500 __u8 macid;
a66098da
LB		 501 __le16 result;
502 char payload[0];
ba2d3587 503} __packed;
a66098da
LB		 504
505/*
506 * Firmware loading.
507 */
508static int
509mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
510{
511 void __iomem *regs = priv->regs;
512 dma_addr_t dma_addr;
a66098da
LB		 513 int loops;
514
515 dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
516 if (pci_dma_mapping_error(priv->pdev, dma_addr))
517 return -ENOMEM;
518
519 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
520 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
521 iowrite32(MWL8K_H2A_INT_DOORBELL,
522 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
523 iowrite32(MWL8K_H2A_INT_DUMMY,
524 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
525
a66098da
LB		 526 loops = 1000;
527 do {
528 u32 int_code;
529
530 int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
531 if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
532 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
a66098da
LB		 533 break;
534 }
535
3d76e82c 536 cond_resched();
a66098da
LB		 537 udelay(1);
538 } while (--loops);
539
540 pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
541
d4b70570 542 return loops ? 0 : -ETIMEDOUT;
a66098da
LB		 543}
544
545static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
546 const u8 *data, size_t length)
547{
548 struct mwl8k_cmd_pkt *cmd;
549 int done;
550 int rc = 0;
551
552 cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
553 if (cmd == NULL)
554 return -ENOMEM;
555
556 cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
557 cmd->seq_num = 0;
f57ca9c1 558 cmd->macid = 0;
a66098da
LB		 559 cmd->result = 0;
560
561 done = 0;
562 while (length) {
563 int block_size = length > 256 ? 256 : length;
564
565 memcpy(cmd->payload, data + done, block_size);
566 cmd->length = cpu_to_le16(block_size);
567
568 rc = mwl8k_send_fw_load_cmd(priv, cmd,
569 sizeof(*cmd) + block_size);
570 if (rc)
571 break;
572
573 done += block_size;
574 length -= block_size;
575 }
576
577 if (!rc) {
578 cmd->length = 0;
579 rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
580 }
581
582 kfree(cmd);
583
584 return rc;
585}
586
587static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
588 const u8 *data, size_t length)
589{
590 unsigned char *buffer;
591 int may_continue, rc = 0;
592 u32 done, prev_block_size;
593
594 buffer = kmalloc(1024, GFP_KERNEL);
595 if (buffer == NULL)
596 return -ENOMEM;
597
598 done = 0;
599 prev_block_size = 0;
600 may_continue = 1000;
601 while (may_continue > 0) {
602 u32 block_size;
603
604 block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
605 if (block_size & 1) {
606 block_size &= ~1;
607 may_continue--;
608 } else {
609 done += prev_block_size;
610 length -= prev_block_size;
611 }
612
613 if (block_size > 1024 || block_size > length) {
614 rc = -EOVERFLOW;
615 break;
616 }
617
618 if (length == 0) {
619 rc = 0;
620 break;
621 }
622
623 if (block_size == 0) {
624 rc = -EPROTO;
625 may_continue--;
626 udelay(1);
627 continue;
628 }
629
630 prev_block_size = block_size;
631 memcpy(buffer, data + done, block_size);
632
633 rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
634 if (rc)
635 break;
636 }
637
638 if (!rc && length != 0)
639 rc = -EREMOTEIO;
640
641 kfree(buffer);
642
643 return rc;
644}
645
c2c357ce 646static int mwl8k_load_firmware(struct ieee80211_hw *hw)
a66098da 647{
c2c357ce 648 struct mwl8k_priv *priv = hw->priv;
d1f9e41d 649 const struct firmware *fw = priv->fw_ucode;
c2c357ce
LB		 650 int rc;
651 int loops;
652
653 if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) {
d1f9e41d 654 const struct firmware *helper = priv->fw_helper;
a66098da 655
c2c357ce
LB		 656 if (helper == NULL) {
657 printk(KERN_ERR "%s: helper image needed but none "
658 "given\n", pci_name(priv->pdev));
659 return -EINVAL;
660 }
a66098da 661
c2c357ce 662 rc = mwl8k_load_fw_image(priv, helper->data, helper->size);
a66098da
LB		 663 if (rc) {
664 printk(KERN_ERR "%s: unable to load firmware "
c2c357ce 665 "helper image\n", pci_name(priv->pdev));
a66098da
LB		 666 return rc;
667 }
89b872e2 668 msleep(5);
a66098da 669
c2c357ce 670 rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
a66098da 671 } else {
c2c357ce 672 rc = mwl8k_load_fw_image(priv, fw->data, fw->size);
a66098da
LB		 673 }
674
675 if (rc) {
c2c357ce
LB		 676 printk(KERN_ERR "%s: unable to load firmware image\n",
677 pci_name(priv->pdev));
a66098da
LB		 678 return rc;
679 }
680
89a91f4f 681 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
a66098da 682
89b872e2 683 loops = 500000;
a66098da 684 do {
eae74e65
LB		 685 u32 ready_code;
686
687 ready_code = ioread32(priv->regs + MWL8K_HIU_INT_CODE);
688 if (ready_code == MWL8K_FWAP_READY) {
689 priv->ap_fw = 1;
690 break;
691 } else if (ready_code == MWL8K_FWSTA_READY) {
692 priv->ap_fw = 0;
a66098da 693 break;
eae74e65
LB		 694 }
695
696 cond_resched();
a66098da
LB		 697 udelay(1);
698 } while (--loops);
699
700 return loops ? 0 : -ETIMEDOUT;
701}
702
703
a66098da
LB		 704/* DMA header used by firmware and hardware. */
705struct mwl8k_dma_data {
706 __le16 fwlen;
707 struct ieee80211_hdr wh;
20f09c3d 708 char data[0];
ba2d3587 709} __packed;
a66098da
LB		 710
711/* Routines to add/remove DMA header from skb. */
20f09c3d 712static inline void mwl8k_remove_dma_header(struct sk_buff *skb, __le16 qos)
a66098da 713{
20f09c3d
LB		 714 struct mwl8k_dma_data *tr;
715 int hdrlen;
716
717 tr = (struct mwl8k_dma_data *)skb->data;
718 hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
719
720 if (hdrlen != sizeof(tr->wh)) {
721 if (ieee80211_is_data_qos(tr->wh.frame_control)) {
722 memmove(tr->data - hdrlen, &tr->wh, hdrlen - 2);
723 *((__le16 *)(tr->data - 2)) = qos;
724 } else {
725 memmove(tr->data - hdrlen, &tr->wh, hdrlen);
726 }
a66098da 727 }
20f09c3d
LB		 728
729 if (hdrlen != sizeof(*tr))
730 skb_pull(skb, sizeof(*tr) - hdrlen);
a66098da
LB		 731}
732
252486a1
NS		 733static void
734mwl8k_add_dma_header(struct sk_buff *skb, int tail_pad)
a66098da
LB		 735{
736 struct ieee80211_hdr *wh;
ca009301 737 int hdrlen;
252486a1 738 int reqd_hdrlen;
a66098da
LB		 739 struct mwl8k_dma_data *tr;
740
ca009301
LB		 741 /*
742 * Add a firmware DMA header; the firmware requires that we
743 * present a 2-byte payload length followed by a 4-address
744 * header (without QoS field), followed (optionally) by any
745 * WEP/ExtIV header (but only filled in for CCMP).
746 */
a66098da 747 wh = (struct ieee80211_hdr *)skb->data;
ca009301 748
a66098da 749 hdrlen = ieee80211_hdrlen(wh->frame_control);
252486a1
NS		 750 reqd_hdrlen = sizeof(*tr);
751
752 if (hdrlen != reqd_hdrlen)
753 skb_push(skb, reqd_hdrlen - hdrlen);
a66098da 754
ca009301 755 if (ieee80211_is_data_qos(wh->frame_control))
252486a1 756 hdrlen -= IEEE80211_QOS_CTL_LEN;
a66098da
LB		 757
758 tr = (struct mwl8k_dma_data *)skb->data;
759 if (wh != &tr->wh)
760 memmove(&tr->wh, wh, hdrlen);
ca009301
LB		 761 if (hdrlen != sizeof(tr->wh))
762 memset(((void *)&tr->wh) + hdrlen, 0, sizeof(tr->wh) - hdrlen);
a66098da
LB		 763
764 /*
765 * Firmware length is the length of the fully formed "802.11
766 * payload". That is, everything except for the 802.11 header.
767 * This includes all crypto material including the MIC.
768 */
252486a1 769 tr->fwlen = cpu_to_le16(skb->len - sizeof(*tr) + tail_pad);
a66098da
LB		 770}
771
e53d9b96
NS		 772static void mwl8k_encapsulate_tx_frame(struct sk_buff *skb)
773{
774 struct ieee80211_hdr *wh;
775 struct ieee80211_tx_info *tx_info;
776 struct ieee80211_key_conf *key_conf;
777 int data_pad;
778
779 wh = (struct ieee80211_hdr *)skb->data;
780
781 tx_info = IEEE80211_SKB_CB(skb);
782
783 key_conf = NULL;
784 if (ieee80211_is_data(wh->frame_control))
785 key_conf = tx_info->control.hw_key;
786
787 /*
788 * Make sure the packet header is in the DMA header format (4-address
789 * without QoS), the necessary crypto padding between the header and the
790 * payload has already been provided by mac80211, but it doesn't add tail
791 * padding when HW crypto is enabled.
792 *
793 * We have the following trailer padding requirements:
794 * - WEP: 4 trailer bytes (ICV)
795 * - TKIP: 12 trailer bytes (8 MIC + 4 ICV)
796 * - CCMP: 8 trailer bytes (MIC)
797 */
798 data_pad = 0;
799 if (key_conf != NULL) {
800 switch (key_conf->cipher) {
801 case WLAN_CIPHER_SUITE_WEP40:
802 case WLAN_CIPHER_SUITE_WEP104:
803 data_pad = 4;
804 break;
805 case WLAN_CIPHER_SUITE_TKIP:
806 data_pad = 12;
807 break;
808 case WLAN_CIPHER_SUITE_CCMP:
809 data_pad = 8;
810 break;
811 }
812 }
813 mwl8k_add_dma_header(skb, data_pad);
814}
a66098da
LB		 815
816/*
89a91f4f 817 * Packet reception for 88w8366 AP firmware.
6f6d1e9a 818 */
89a91f4f 819struct mwl8k_rxd_8366_ap {
6f6d1e9a
LB		 820 __le16 pkt_len;
821 __u8 sq2;
822 __u8 rate;
823 __le32 pkt_phys_addr;
824 __le32 next_rxd_phys_addr;
825 __le16 qos_control;
826 __le16 htsig2;
827 __le32 hw_rssi_info;
828 __le32 hw_noise_floor_info;
829 __u8 noise_floor;
830 __u8 pad0[3];
831 __u8 rssi;
832 __u8 rx_status;
833 __u8 channel;
834 __u8 rx_ctrl;
ba2d3587 835} __packed;
6f6d1e9a 836
89a91f4f
LB		 837#define MWL8K_8366_AP_RATE_INFO_MCS_FORMAT 0x80
838#define MWL8K_8366_AP_RATE_INFO_40MHZ 0x40
839#define MWL8K_8366_AP_RATE_INFO_RATEID(x) ((x) & 0x3f)
8e9f33f0 840
89a91f4f 841#define MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST 0x80
6f6d1e9a 842
d9a07d49
NS		 843/* 8366 AP rx_status bits */
844#define MWL8K_8366_AP_RXSTAT_DECRYPT_ERR_MASK 0x80
845#define MWL8K_8366_AP_RXSTAT_GENERAL_DECRYPT_ERR 0xFF
846#define MWL8K_8366_AP_RXSTAT_TKIP_DECRYPT_MIC_ERR 0x02
847#define MWL8K_8366_AP_RXSTAT_WEP_DECRYPT_ICV_ERR 0x04
848#define MWL8K_8366_AP_RXSTAT_TKIP_DECRYPT_ICV_ERR 0x08
849
89a91f4f 850static void mwl8k_rxd_8366_ap_init(void *_rxd, dma_addr_t next_dma_addr)
6f6d1e9a 851{
89a91f4f 852 struct mwl8k_rxd_8366_ap *rxd = _rxd;
6f6d1e9a
LB		 853
854 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
89a91f4f 855 rxd->rx_ctrl = MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST;
6f6d1e9a
LB		 856}
857
89a91f4f 858static void mwl8k_rxd_8366_ap_refill(void *_rxd, dma_addr_t addr, int len)
6f6d1e9a 859{
89a91f4f 860 struct mwl8k_rxd_8366_ap *rxd = _rxd;
6f6d1e9a
LB		 861
862 rxd->pkt_len = cpu_to_le16(len);
863 rxd->pkt_phys_addr = cpu_to_le32(addr);
864 wmb();
865 rxd->rx_ctrl = 0;
866}
867
868static int
89a91f4f 869mwl8k_rxd_8366_ap_process(void *_rxd, struct ieee80211_rx_status *status,
0d462bbb 870 __le16 *qos, s8 *noise)
6f6d1e9a 871{
89a91f4f 872 struct mwl8k_rxd_8366_ap *rxd = _rxd;
6f6d1e9a 873
89a91f4f 874 if (!(rxd->rx_ctrl & MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST))
6f6d1e9a
LB		 875 return -1;
876 rmb();
877
878 memset(status, 0, sizeof(*status));
879
880 status->signal = -rxd->rssi;
0d462bbb 881 *noise = -rxd->noise_floor;
6f6d1e9a 882
89a91f4f 883 if (rxd->rate & MWL8K_8366_AP_RATE_INFO_MCS_FORMAT) {
6f6d1e9a 884 status->flag |= RX_FLAG_HT;
89a91f4f 885 if (rxd->rate & MWL8K_8366_AP_RATE_INFO_40MHZ)
8e9f33f0 886 status->flag |= RX_FLAG_40MHZ;
89a91f4f 887 status->rate_idx = MWL8K_8366_AP_RATE_INFO_RATEID(rxd->rate);
6f6d1e9a
LB		 888 } else {
889 int i;
890
777ad375
LB		 891 for (i = 0; i < ARRAY_SIZE(mwl8k_rates_24); i++) {
892 if (mwl8k_rates_24[i].hw_value == rxd->rate) {
6f6d1e9a
LB		 893 status->rate_idx = i;
894 break;
895 }
896 }
897 }
898
85478344
LB		 899 if (rxd->channel > 14) {
900 status->band = IEEE80211_BAND_5GHZ;
901 if (!(status->flag & RX_FLAG_HT))
902 status->rate_idx -= 5;
903 } else {
904 status->band = IEEE80211_BAND_2GHZ;
905 }
6f6d1e9a
LB		 906 status->freq = ieee80211_channel_to_frequency(rxd->channel);
907
20f09c3d
LB		 908 *qos = rxd->qos_control;
909
d9a07d49
NS		 910 if ((rxd->rx_status != MWL8K_8366_AP_RXSTAT_GENERAL_DECRYPT_ERR) &&
911 (rxd->rx_status & MWL8K_8366_AP_RXSTAT_DECRYPT_ERR_MASK) &&
912 (rxd->rx_status & MWL8K_8366_AP_RXSTAT_TKIP_DECRYPT_MIC_ERR))
913 status->flag |= RX_FLAG_MMIC_ERROR;
914
6f6d1e9a
LB		 915 return le16_to_cpu(rxd->pkt_len);
916}
917
89a91f4f
LB		 918static struct rxd_ops rxd_8366_ap_ops = {
919 .rxd_size = sizeof(struct mwl8k_rxd_8366_ap),
920 .rxd_init = mwl8k_rxd_8366_ap_init,
921 .rxd_refill = mwl8k_rxd_8366_ap_refill,
922 .rxd_process = mwl8k_rxd_8366_ap_process,
6f6d1e9a
LB		 923};
924
925/*
89a91f4f 926 * Packet reception for STA firmware.
a66098da 927 */
89a91f4f 928struct mwl8k_rxd_sta {
a66098da
LB		 929 __le16 pkt_len;
930 __u8 link_quality;
931 __u8 noise_level;
932 __le32 pkt_phys_addr;
45eb400d 933 __le32 next_rxd_phys_addr;
a66098da
LB		 934 __le16 qos_control;
935 __le16 rate_info;
936 __le32 pad0[4];
937 __u8 rssi;
938 __u8 channel;
939 __le16 pad1;
940 __u8 rx_ctrl;
941 __u8 rx_status;
942 __u8 pad2[2];
ba2d3587 943} __packed;
a66098da 944
89a91f4f
LB		 945#define MWL8K_STA_RATE_INFO_SHORTPRE 0x8000
946#define MWL8K_STA_RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3)
947#define MWL8K_STA_RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f)
948#define MWL8K_STA_RATE_INFO_40MHZ 0x0004
949#define MWL8K_STA_RATE_INFO_SHORTGI 0x0002
950#define MWL8K_STA_RATE_INFO_MCS_FORMAT 0x0001
54bc3a0d 951
89a91f4f 952#define MWL8K_STA_RX_CTRL_OWNED_BY_HOST 0x02
d9a07d49
NS		 953#define MWL8K_STA_RX_CTRL_DECRYPT_ERROR 0x04
954/* ICV=0 or MIC=1 */
955#define MWL8K_STA_RX_CTRL_DEC_ERR_TYPE 0x08
956/* Key is uploaded only in failure case */
957#define MWL8K_STA_RX_CTRL_KEY_INDEX 0x30
54bc3a0d 958
89a91f4f 959static void mwl8k_rxd_sta_init(void *_rxd, dma_addr_t next_dma_addr)
54bc3a0d 960{
89a91f4f 961 struct mwl8k_rxd_sta *rxd = _rxd;
54bc3a0d
LB		 962
963 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
89a91f4f 964 rxd->rx_ctrl = MWL8K_STA_RX_CTRL_OWNED_BY_HOST;
54bc3a0d
LB		 965}
966
89a91f4f 967static void mwl8k_rxd_sta_refill(void *_rxd, dma_addr_t addr, int len)
54bc3a0d 968{
89a91f4f 969 struct mwl8k_rxd_sta *rxd = _rxd;
54bc3a0d
LB		 970
971 rxd->pkt_len = cpu_to_le16(len);
972 rxd->pkt_phys_addr = cpu_to_le32(addr);
973 wmb();
974 rxd->rx_ctrl = 0;
975}
976
977static int
89a91f4f 978mwl8k_rxd_sta_process(void *_rxd, struct ieee80211_rx_status *status,
0d462bbb 979 __le16 *qos, s8 *noise)
54bc3a0d 980{
89a91f4f 981 struct mwl8k_rxd_sta *rxd = _rxd;
54bc3a0d
LB		 982 u16 rate_info;
983
89a91f4f 984 if (!(rxd->rx_ctrl & MWL8K_STA_RX_CTRL_OWNED_BY_HOST))
54bc3a0d
LB		 985 return -1;
986 rmb();
987
988 rate_info = le16_to_cpu(rxd->rate_info);
989
990 memset(status, 0, sizeof(*status));
991
992 status->signal = -rxd->rssi;
0d462bbb 993 *noise = -rxd->noise_level;
89a91f4f
LB		 994 status->antenna = MWL8K_STA_RATE_INFO_ANTSELECT(rate_info);
995 status->rate_idx = MWL8K_STA_RATE_INFO_RATEID(rate_info);
54bc3a0d 996
89a91f4f 997 if (rate_info & MWL8K_STA_RATE_INFO_SHORTPRE)
54bc3a0d 998 status->flag |= RX_FLAG_SHORTPRE;
89a91f4f 999 if (rate_info & MWL8K_STA_RATE_INFO_40MHZ)
54bc3a0d 1000 status->flag |= RX_FLAG_40MHZ;
89a91f4f 1001 if (rate_info & MWL8K_STA_RATE_INFO_SHORTGI)
54bc3a0d 1002 status->flag |= RX_FLAG_SHORT_GI;
89a91f4f 1003 if (rate_info & MWL8K_STA_RATE_INFO_MCS_FORMAT)
54bc3a0d
LB		 1004 status->flag |= RX_FLAG_HT;
1005
85478344
LB		 1006 if (rxd->channel > 14) {
1007 status->band = IEEE80211_BAND_5GHZ;
1008 if (!(status->flag & RX_FLAG_HT))
1009 status->rate_idx -= 5;
1010 } else {
1011 status->band = IEEE80211_BAND_2GHZ;
1012 }
54bc3a0d
LB		 1013 status->freq = ieee80211_channel_to_frequency(rxd->channel);
1014
20f09c3d 1015 *qos = rxd->qos_control;
d9a07d49
NS		 1016 if ((rxd->rx_ctrl & MWL8K_STA_RX_CTRL_DECRYPT_ERROR) &&
1017 (rxd->rx_ctrl & MWL8K_STA_RX_CTRL_DEC_ERR_TYPE))
1018 status->flag |= RX_FLAG_MMIC_ERROR;
20f09c3d 1019
54bc3a0d
LB		 1020 return le16_to_cpu(rxd->pkt_len);
1021}
1022
89a91f4f
LB		 1023static struct rxd_ops rxd_sta_ops = {
1024 .rxd_size = sizeof(struct mwl8k_rxd_sta),
1025 .rxd_init = mwl8k_rxd_sta_init,
1026 .rxd_refill = mwl8k_rxd_sta_refill,
1027 .rxd_process = mwl8k_rxd_sta_process,
54bc3a0d
LB		 1028};
1029
1030
a66098da
LB		 1031#define MWL8K_RX_DESCS 256
1032#define MWL8K_RX_MAXSZ 3800
1033
1034static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
1035{
1036 struct mwl8k_priv *priv = hw->priv;
1037 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1038 int size;
1039 int i;
1040
45eb400d
LB		 1041 rxq->rxd_count = 0;
1042 rxq->head = 0;
1043 rxq->tail = 0;
a66098da 1044
54bc3a0d 1045 size = MWL8K_RX_DESCS * priv->rxd_ops->rxd_size;
a66098da 1046
45eb400d
LB		 1047 rxq->rxd = pci_alloc_consistent(priv->pdev, size, &rxq->rxd_dma);
1048 if (rxq->rxd == NULL) {
5db55844 1049 wiphy_err(hw->wiphy, "failed to alloc RX descriptors\n");
a66098da
LB		 1050 return -ENOMEM;
1051 }
45eb400d 1052 memset(rxq->rxd, 0, size);
a66098da 1053
788838eb
LB		 1054 rxq->buf = kmalloc(MWL8K_RX_DESCS * sizeof(*rxq->buf), GFP_KERNEL);
1055 if (rxq->buf == NULL) {
5db55844 1056 wiphy_err(hw->wiphy, "failed to alloc RX skbuff list\n");
45eb400d 1057 pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma);
a66098da
LB		 1058 return -ENOMEM;
1059 }
788838eb 1060 memset(rxq->buf, 0, MWL8K_RX_DESCS * sizeof(*rxq->buf));
a66098da
LB		 1061
1062 for (i = 0; i < MWL8K_RX_DESCS; i++) {
54bc3a0d
LB		 1063 int desc_size;
1064 void *rxd;
a66098da 1065 int nexti;
54bc3a0d
LB		 1066 dma_addr_t next_dma_addr;
1067
1068 desc_size = priv->rxd_ops->rxd_size;
1069 rxd = rxq->rxd + (i * priv->rxd_ops->rxd_size);
a66098da 1070
54bc3a0d
LB		 1071 nexti = i + 1;
1072 if (nexti == MWL8K_RX_DESCS)
1073 nexti = 0;
1074 next_dma_addr = rxq->rxd_dma + (nexti * desc_size);
a66098da 1075
54bc3a0d 1076 priv->rxd_ops->rxd_init(rxd, next_dma_addr);
a66098da
LB		 1077 }
1078
1079 return 0;
1080}
1081
1082static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
1083{
1084 struct mwl8k_priv *priv = hw->priv;
1085 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1086 int refilled;
1087
1088 refilled = 0;
45eb400d 1089 while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) {
a66098da 1090 struct sk_buff *skb;
788838eb 1091 dma_addr_t addr;
a66098da 1092 int rx;
54bc3a0d 1093 void *rxd;
a66098da
LB		 1094
1095 skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
1096 if (skb == NULL)
1097 break;
1098
788838eb
LB		 1099 addr = pci_map_single(priv->pdev, skb->data,
1100 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE);
a66098da 1101
54bc3a0d
LB		 1102 rxq->rxd_count++;
1103 rx = rxq->tail++;
1104 if (rxq->tail == MWL8K_RX_DESCS)
1105 rxq->tail = 0;
788838eb 1106 rxq->buf[rx].skb = skb;
53b1b3e1 1107 dma_unmap_addr_set(&rxq->buf[rx], dma, addr);
54bc3a0d
LB		 1108
1109 rxd = rxq->rxd + (rx * priv->rxd_ops->rxd_size);
1110 priv->rxd_ops->rxd_refill(rxd, addr, MWL8K_RX_MAXSZ);
a66098da
LB		 1111
1112 refilled++;
1113 }
1114
1115 return refilled;
1116}
1117
1118/* Must be called only when the card's reception is completely halted */
1119static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
1120{
1121 struct mwl8k_priv *priv = hw->priv;
1122 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1123 int i;
1124
1125 for (i = 0; i < MWL8K_RX_DESCS; i++) {
788838eb
LB		 1126 if (rxq->buf[i].skb != NULL) {
1127 pci_unmap_single(priv->pdev,
53b1b3e1 1128 dma_unmap_addr(&rxq->buf[i], dma),
788838eb 1129 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
53b1b3e1 1130 dma_unmap_addr_set(&rxq->buf[i], dma, 0);
788838eb
LB		 1131
1132 kfree_skb(rxq->buf[i].skb);
1133 rxq->buf[i].skb = NULL;
a66098da
LB		 1134 }
1135 }
1136
788838eb
LB		 1137 kfree(rxq->buf);
1138 rxq->buf = NULL;
a66098da
LB		 1139
1140 pci_free_consistent(priv->pdev,
54bc3a0d 1141 MWL8K_RX_DESCS * priv->rxd_ops->rxd_size,
45eb400d
LB		 1142 rxq->rxd, rxq->rxd_dma);
1143 rxq->rxd = NULL;
a66098da
LB		 1144}
1145
1146
1147/*
1148 * Scan a list of BSSIDs to process for finalize join.
1149 * Allows for extension to process multiple BSSIDs.
1150 */
1151static inline int
1152mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
1153{
1154 return priv->capture_beacon &&
1155 ieee80211_is_beacon(wh->frame_control) &&
1156 !compare_ether_addr(wh->addr3, priv->capture_bssid);
1157}
1158
3779752d
LB		 1159static inline void mwl8k_save_beacon(struct ieee80211_hw *hw,
1160 struct sk_buff *skb)
a66098da 1161{
3779752d
LB		 1162 struct mwl8k_priv *priv = hw->priv;
1163
a66098da 1164 priv->capture_beacon = false;
d89173f2 1165 memset(priv->capture_bssid, 0, ETH_ALEN);
a66098da
LB		 1166
1167 /*
1168 * Use GFP_ATOMIC as rxq_process is called from
1169 * the primary interrupt handler, memory allocation call
1170 * must not sleep.
1171 */
1172 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
1173 if (priv->beacon_skb != NULL)
3779752d 1174 ieee80211_queue_work(hw, &priv->finalize_join_worker);
a66098da
LB		 1175}
1176
d9a07d49
NS		 1177static inline struct mwl8k_vif *mwl8k_find_vif_bss(struct list_head *vif_list,
1178 u8 *bssid)
1179{
1180 struct mwl8k_vif *mwl8k_vif;
1181
1182 list_for_each_entry(mwl8k_vif,
1183 vif_list, list) {
1184 if (memcmp(bssid, mwl8k_vif->bssid,
1185 ETH_ALEN) == 0)
1186 return mwl8k_vif;
1187 }
1188
1189 return NULL;
1190}
1191
a66098da
LB		 1192static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
1193{
1194 struct mwl8k_priv *priv = hw->priv;
d9a07d49 1195 struct mwl8k_vif *mwl8k_vif = NULL;
a66098da
LB		 1196 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1197 int processed;
1198
1199 processed = 0;
45eb400d 1200 while (rxq->rxd_count && limit--) {
a66098da 1201 struct sk_buff *skb;
54bc3a0d
LB		 1202 void *rxd;
1203 int pkt_len;
a66098da 1204 struct ieee80211_rx_status status;
d9a07d49 1205 struct ieee80211_hdr *wh;
20f09c3d 1206 __le16 qos;
a66098da 1207
788838eb 1208 skb = rxq->buf[rxq->head].skb;
d25f9f13
LB		 1209 if (skb == NULL)
1210 break;
54bc3a0d
LB		 1211
1212 rxd = rxq->rxd + (rxq->head * priv->rxd_ops->rxd_size);
1213
0d462bbb
JL		 1214 pkt_len = priv->rxd_ops->rxd_process(rxd, &status, &qos,
1215 &priv->noise);
54bc3a0d
LB		 1216 if (pkt_len < 0)
1217 break;
1218
788838eb
LB		 1219 rxq->buf[rxq->head].skb = NULL;
1220
1221 pci_unmap_single(priv->pdev,
53b1b3e1 1222 dma_unmap_addr(&rxq->buf[rxq->head], dma),
788838eb 1223 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
53b1b3e1 1224 dma_unmap_addr_set(&rxq->buf[rxq->head], dma, 0);
a66098da 1225
54bc3a0d
LB		 1226 rxq->head++;
1227 if (rxq->head == MWL8K_RX_DESCS)
1228 rxq->head = 0;
1229
45eb400d 1230 rxq->rxd_count--;
a66098da 1231
d9a07d49 1232 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
a66098da 1233
a66098da 1234 /*
c2c357ce
LB		 1235 * Check for a pending join operation. Save a
1236 * copy of the beacon and schedule a tasklet to
1237 * send a FINALIZE_JOIN command to the firmware.
a66098da 1238 */
54bc3a0d 1239 if (mwl8k_capture_bssid(priv, (void *)skb->data))
3779752d 1240 mwl8k_save_beacon(hw, skb);
a66098da 1241
d9a07d49
NS		 1242 if (ieee80211_has_protected(wh->frame_control)) {
1243
1244 /* Check if hw crypto has been enabled for
1245 * this bss. If yes, set the status flags
1246 * accordingly
1247 */
1248 mwl8k_vif = mwl8k_find_vif_bss(&priv->vif_list,
1249 wh->addr1);
1250
1251 if (mwl8k_vif != NULL &&
1252 mwl8k_vif->is_hw_crypto_enabled == true) {
1253 /*
1254 * When MMIC ERROR is encountered
1255 * by the firmware, payload is
1256 * dropped and only 32 bytes of
1257 * mwl8k Firmware header is sent
1258 * to the host.
1259 *
1260 * We need to add four bytes of
1261 * key information. In it
1262 * MAC80211 expects keyidx set to
1263 * 0 for triggering Counter
1264 * Measure of MMIC failure.
1265 */
1266 if (status.flag & RX_FLAG_MMIC_ERROR) {
1267 struct mwl8k_dma_data *tr;
1268 tr = (struct mwl8k_dma_data *)skb->data;
1269 memset((void *)&(tr->data), 0, 4);
1270 pkt_len += 4;
1271 }
1272
1273 if (!ieee80211_is_auth(wh->frame_control))
1274 status.flag |= RX_FLAG_IV_STRIPPED |
1275 RX_FLAG_DECRYPTED |
1276 RX_FLAG_MMIC_STRIPPED;
1277 }
1278 }
1279
1280 skb_put(skb, pkt_len);
1281 mwl8k_remove_dma_header(skb, qos);
f1d58c25
JB		 1282 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
1283 ieee80211_rx_irqsafe(hw, skb);
a66098da
LB		 1284
1285 processed++;
1286 }
1287
1288 return processed;
1289}
1290
1291
1292/*
1293 * Packet transmission.
1294 */
1295
a66098da
LB		 1296#define MWL8K_TXD_STATUS_OK 0x00000001
1297#define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
1298#define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
1299#define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
a66098da 1300#define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
a66098da 1301
e0493a8d
LB		 1302#define MWL8K_QOS_QLEN_UNSPEC 0xff00
1303#define MWL8K_QOS_ACK_POLICY_MASK 0x0060
1304#define MWL8K_QOS_ACK_POLICY_NORMAL 0x0000
1305#define MWL8K_QOS_ACK_POLICY_BLOCKACK 0x0060
1306#define MWL8K_QOS_EOSP 0x0010
1307
a66098da
LB		 1308struct mwl8k_tx_desc {
1309 __le32 status;
1310 __u8 data_rate;
1311 __u8 tx_priority;
1312 __le16 qos_control;
1313 __le32 pkt_phys_addr;
1314 __le16 pkt_len;
d89173f2 1315 __u8 dest_MAC_addr[ETH_ALEN];
45eb400d 1316 __le32 next_txd_phys_addr;
a66098da
LB		 1317 __le32 reserved;
1318 __le16 rate_info;
1319 __u8 peer_id;
a1fe24b0 1320 __u8 tx_frag_cnt;
ba2d3587 1321} __packed;
a66098da
LB		 1322
1323#define MWL8K_TX_DESCS 128
1324
1325static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
1326{
1327 struct mwl8k_priv *priv = hw->priv;
1328 struct mwl8k_tx_queue *txq = priv->txq + index;
1329 int size;
1330 int i;
1331
8ccbc3b8 1332 txq->len = 0;
45eb400d
LB		 1333 txq->head = 0;
1334 txq->tail = 0;
a66098da
LB		 1335
1336 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
1337
45eb400d
LB		 1338 txq->txd = pci_alloc_consistent(priv->pdev, size, &txq->txd_dma);
1339 if (txq->txd == NULL) {
5db55844 1340 wiphy_err(hw->wiphy, "failed to alloc TX descriptors\n");
a66098da
LB		 1341 return -ENOMEM;
1342 }
45eb400d 1343 memset(txq->txd, 0, size);
a66098da 1344
45eb400d
LB		 1345 txq->skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->skb), GFP_KERNEL);
1346 if (txq->skb == NULL) {
5db55844 1347 wiphy_err(hw->wiphy, "failed to alloc TX skbuff list\n");
45eb400d 1348 pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma);
a66098da
LB		 1349 return -ENOMEM;
1350 }
45eb400d 1351 memset(txq->skb, 0, MWL8K_TX_DESCS * sizeof(*txq->skb));
a66098da
LB		 1352
1353 for (i = 0; i < MWL8K_TX_DESCS; i++) {
1354 struct mwl8k_tx_desc *tx_desc;
1355 int nexti;
1356
45eb400d 1357 tx_desc = txq->txd + i;
a66098da
LB		 1358 nexti = (i + 1) % MWL8K_TX_DESCS;
1359
1360 tx_desc->status = 0;
45eb400d
LB		 1361 tx_desc->next_txd_phys_addr =
1362 cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc));
a66098da
LB		 1363 }
1364
1365 return 0;
1366}
1367
1368static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
1369{
1370 iowrite32(MWL8K_H2A_INT_PPA_READY,
1371 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1372 iowrite32(MWL8K_H2A_INT_DUMMY,
1373 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1374 ioread32(priv->regs + MWL8K_HIU_INT_CODE);
1375}
1376
7e1112d3 1377static void mwl8k_dump_tx_rings(struct ieee80211_hw *hw)
a66098da 1378{
7e1112d3
LB		 1379 struct mwl8k_priv *priv = hw->priv;
1380 int i;
1381
1382 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
1383 struct mwl8k_tx_queue *txq = priv->txq + i;
1384 int fw_owned = 0;
1385 int drv_owned = 0;
1386 int unused = 0;
1387 int desc;
1388
a66098da 1389 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
7e1112d3
LB		 1390 struct mwl8k_tx_desc *tx_desc = txq->txd + desc;
1391 u32 status;
a66098da 1392
7e1112d3 1393 status = le32_to_cpu(tx_desc->status);
a66098da 1394 if (status & MWL8K_TXD_STATUS_FW_OWNED)
7e1112d3 1395 fw_owned++;
a66098da 1396 else
7e1112d3 1397 drv_owned++;
a66098da
LB		 1398
1399 if (tx_desc->pkt_len == 0)
7e1112d3 1400 unused++;
a66098da 1401 }
a66098da 1402
c96c31e4
JP		 1403 wiphy_err(hw->wiphy,
1404 "txq[%d] len=%d head=%d tail=%d "
1405 "fw_owned=%d drv_owned=%d unused=%d\n",
1406 i,
1407 txq->len, txq->head, txq->tail,
1408 fw_owned, drv_owned, unused);
7e1112d3 1409 }
a66098da
LB		 1410}
1411
618952a7 1412/*
88de754a 1413 * Must be called with priv->fw_mutex held and tx queues stopped.
618952a7 1414 */
62abd3cf 1415#define MWL8K_TX_WAIT_TIMEOUT_MS 5000
7e1112d3 1416
950d5b01 1417static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
a66098da 1418{
a66098da 1419 struct mwl8k_priv *priv = hw->priv;
88de754a 1420 DECLARE_COMPLETION_ONSTACK(tx_wait);
7e1112d3
LB		 1421 int retry;
1422 int rc;
a66098da
LB		 1423
1424 might_sleep();
1425
7e1112d3
LB		 1426 /*
1427 * The TX queues are stopped at this point, so this test
1428 * doesn't need to take ->tx_lock.
1429 */
1430 if (!priv->pending_tx_pkts)
1431 return 0;
1432
1433 retry = 0;
1434 rc = 0;
1435
a66098da 1436 spin_lock_bh(&priv->tx_lock);
7e1112d3
LB		 1437 priv->tx_wait = &tx_wait;
1438 while (!rc) {
1439 int oldcount;
1440 unsigned long timeout;
a66098da 1441
7e1112d3 1442 oldcount = priv->pending_tx_pkts;
a66098da 1443
7e1112d3 1444 spin_unlock_bh(&priv->tx_lock);
88de754a 1445 timeout = wait_for_completion_timeout(&tx_wait,
7e1112d3 1446 msecs_to_jiffies(MWL8K_TX_WAIT_TIMEOUT_MS));
a66098da 1447 spin_lock_bh(&priv->tx_lock);
7e1112d3
LB		 1448
1449 if (timeout) {
1450 WARN_ON(priv->pending_tx_pkts);
1451 if (retry) {
c96c31e4 1452 wiphy_notice(hw->wiphy, "tx rings drained\n");
7e1112d3
LB		 1453 }
1454 break;
1455 }
1456
1457 if (priv->pending_tx_pkts < oldcount) {
c96c31e4
JP		 1458 wiphy_notice(hw->wiphy,
1459 "waiting for tx rings to drain (%d -> %d pkts)\n",
1460 oldcount, priv->pending_tx_pkts);
7e1112d3
LB		 1461 retry = 1;
1462 continue;
1463 }
1464
a66098da 1465 priv->tx_wait = NULL;
a66098da 1466
c96c31e4
JP		 1467 wiphy_err(hw->wiphy, "tx rings stuck for %d ms\n",
1468 MWL8K_TX_WAIT_TIMEOUT_MS);
7e1112d3
LB		 1469 mwl8k_dump_tx_rings(hw);
1470
1471 rc = -ETIMEDOUT;
a66098da 1472 }
7e1112d3 1473 spin_unlock_bh(&priv->tx_lock);
a66098da 1474
7e1112d3 1475 return rc;
a66098da
LB		 1476}
1477
c23b5a69
LB		 1478#define MWL8K_TXD_SUCCESS(status) \
1479 ((status) & (MWL8K_TXD_STATUS_OK | \
1480 MWL8K_TXD_STATUS_OK_RETRY | \
1481 MWL8K_TXD_STATUS_OK_MORE_RETRY))
a66098da 1482
efb7c49a
LB		 1483static int
1484mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int limit, int force)
a66098da
LB		 1485{
1486 struct mwl8k_priv *priv = hw->priv;
1487 struct mwl8k_tx_queue *txq = priv->txq + index;
efb7c49a 1488 int processed;
a66098da 1489
efb7c49a 1490 processed = 0;
8ccbc3b8 1491 while (txq->len > 0 && limit--) {
a66098da 1492 int tx;
a66098da
LB		 1493 struct mwl8k_tx_desc *tx_desc;
1494 unsigned long addr;
ce9e2e1b 1495 int size;
a66098da
LB		 1496 struct sk_buff *skb;
1497 struct ieee80211_tx_info *info;
1498 u32 status;
1499
45eb400d
LB		 1500 tx = txq->head;
1501 tx_desc = txq->txd + tx;
a66098da
LB		 1502
1503 status = le32_to_cpu(tx_desc->status);
1504
1505 if (status & MWL8K_TXD_STATUS_FW_OWNED) {
1506 if (!force)
1507 break;
1508 tx_desc->status &=
1509 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
1510 }
1511
45eb400d 1512 txq->head = (tx + 1) % MWL8K_TX_DESCS;
8ccbc3b8
KV		 1513 BUG_ON(txq->len == 0);
1514 txq->len--;
a66098da
LB		 1515 priv->pending_tx_pkts--;
1516
1517 addr = le32_to_cpu(tx_desc->pkt_phys_addr);
ce9e2e1b 1518 size = le16_to_cpu(tx_desc->pkt_len);
45eb400d
LB		 1519 skb = txq->skb[tx];
1520 txq->skb[tx] = NULL;
a66098da
LB		 1521
1522 BUG_ON(skb == NULL);
1523 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
1524
20f09c3d 1525 mwl8k_remove_dma_header(skb, tx_desc->qos_control);
a66098da
LB		 1526
1527 /* Mark descriptor as unused */
1528 tx_desc->pkt_phys_addr = 0;
1529 tx_desc->pkt_len = 0;
1530
a66098da
LB		 1531 info = IEEE80211_SKB_CB(skb);
1532 ieee80211_tx_info_clear_status(info);
ce9e2e1b 1533 if (MWL8K_TXD_SUCCESS(status))
a66098da 1534 info->flags |= IEEE80211_TX_STAT_ACK;
a66098da
LB		 1535
1536 ieee80211_tx_status_irqsafe(hw, skb);
1537
efb7c49a 1538 processed++;
a66098da
LB		 1539 }
1540
efb7c49a 1541 if (processed && priv->radio_on && !mutex_is_locked(&priv->fw_mutex))
a66098da 1542 ieee80211_wake_queue(hw, index);
efb7c49a
LB		 1543
1544 return processed;
a66098da
LB		 1545}
1546
1547/* must be called only when the card's transmit is completely halted */
1548static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
1549{
1550 struct mwl8k_priv *priv = hw->priv;
1551 struct mwl8k_tx_queue *txq = priv->txq + index;
1552
efb7c49a 1553 mwl8k_txq_reclaim(hw, index, INT_MAX, 1);
a66098da 1554
45eb400d
LB		 1555 kfree(txq->skb);
1556 txq->skb = NULL;
a66098da
LB		 1557
1558 pci_free_consistent(priv->pdev,
1559 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
45eb400d
LB		 1560 txq->txd, txq->txd_dma);
1561 txq->txd = NULL;
a66098da
LB		 1562}
1563
1564static int
1565mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
1566{
1567 struct mwl8k_priv *priv = hw->priv;
1568 struct ieee80211_tx_info *tx_info;
23b33906 1569 struct mwl8k_vif *mwl8k_vif;
a66098da
LB		 1570 struct ieee80211_hdr *wh;
1571 struct mwl8k_tx_queue *txq;
1572 struct mwl8k_tx_desc *tx;
a66098da 1573 dma_addr_t dma;
23b33906
LB		 1574 u32 txstatus;
1575 u8 txdatarate;
1576 u16 qos;
a66098da 1577
23b33906
LB		 1578 wh = (struct ieee80211_hdr *)skb->data;
1579 if (ieee80211_is_data_qos(wh->frame_control))
1580 qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
1581 else
1582 qos = 0;
a66098da 1583
d9a07d49
NS		 1584 if (priv->ap_fw)
1585 mwl8k_encapsulate_tx_frame(skb);
1586 else
1587 mwl8k_add_dma_header(skb, 0);
1588
23b33906 1589 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
a66098da
LB		 1590
1591 tx_info = IEEE80211_SKB_CB(skb);
1592 mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
a66098da
LB		 1593
1594 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
a66098da 1595 wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
657232b6
LB		 1596 wh->seq_ctrl |= cpu_to_le16(mwl8k_vif->seqno);
1597 mwl8k_vif->seqno += 0x10;
a66098da
LB		 1598 }
1599
23b33906
LB		 1600 /* Setup firmware control bit fields for each frame type. */
1601 txstatus = 0;
1602 txdatarate = 0;
1603 if (ieee80211_is_mgmt(wh->frame_control) ||
1604 ieee80211_is_ctl(wh->frame_control)) {
1605 txdatarate = 0;
e0493a8d 1606 qos |= MWL8K_QOS_QLEN_UNSPEC | MWL8K_QOS_EOSP;
23b33906
LB		 1607 } else if (ieee80211_is_data(wh->frame_control)) {
1608 txdatarate = 1;
1609 if (is_multicast_ether_addr(wh->addr1))
1610 txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
1611
e0493a8d 1612 qos &= ~MWL8K_QOS_ACK_POLICY_MASK;
23b33906 1613 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
e0493a8d 1614 qos |= MWL8K_QOS_ACK_POLICY_BLOCKACK;
23b33906 1615 else
e0493a8d 1616 qos |= MWL8K_QOS_ACK_POLICY_NORMAL;
23b33906 1617 }
a66098da
LB		 1618
1619 dma = pci_map_single(priv->pdev, skb->data,
1620 skb->len, PCI_DMA_TODEVICE);
1621
1622 if (pci_dma_mapping_error(priv->pdev, dma)) {
c96c31e4
JP		 1623 wiphy_debug(hw->wiphy,
1624 "failed to dma map skb, dropping TX frame.\n");
23b33906 1625 dev_kfree_skb(skb);
a66098da
LB		 1626 return NETDEV_TX_OK;
1627 }
1628
23b33906 1629 spin_lock_bh(&priv->tx_lock);
a66098da 1630
23b33906 1631 txq = priv->txq + index;
a66098da 1632
45eb400d
LB		 1633 BUG_ON(txq->skb[txq->tail] != NULL);
1634 txq->skb[txq->tail] = skb;
a66098da 1635
45eb400d 1636 tx = txq->txd + txq->tail;
23b33906
LB		 1637 tx->data_rate = txdatarate;
1638 tx->tx_priority = index;
a66098da 1639 tx->qos_control = cpu_to_le16(qos);
a66098da
LB		 1640 tx->pkt_phys_addr = cpu_to_le32(dma);
1641 tx->pkt_len = cpu_to_le16(skb->len);
23b33906 1642 tx->rate_info = 0;
a680400e
LB		 1643 if (!priv->ap_fw && tx_info->control.sta != NULL)
1644 tx->peer_id = MWL8K_STA(tx_info->control.sta)->peer_id;
1645 else
1646 tx->peer_id = 0;
a66098da 1647 wmb();
23b33906
LB		 1648 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus);
1649
8ccbc3b8 1650 txq->len++;
a66098da 1651 priv->pending_tx_pkts++;
a66098da 1652
45eb400d
LB		 1653 txq->tail++;
1654 if (txq->tail == MWL8K_TX_DESCS)
1655 txq->tail = 0;
23b33906 1656
45eb400d 1657 if (txq->head == txq->tail)
a66098da
LB		 1658 ieee80211_stop_queue(hw, index);
1659
23b33906 1660 mwl8k_tx_start(priv);
a66098da
LB		 1661
1662 spin_unlock_bh(&priv->tx_lock);
1663
1664 return NETDEV_TX_OK;
1665}
1666
1667
618952a7
LB		 1668/*
1669 * Firmware access.
1670 *
1671 * We have the following requirements for issuing firmware commands:
1672 * - Some commands require that the packet transmit path is idle when
1673 * the command is issued. (For simplicity, we'll just quiesce the
1674 * transmit path for every command.)
1675 * - There are certain sequences of commands that need to be issued to
1676 * the hardware sequentially, with no other intervening commands.
1677 *
1678 * This leads to an implementation of a "firmware lock" as a mutex that
1679 * can be taken recursively, and which is taken by both the low-level
1680 * command submission function (mwl8k_post_cmd) as well as any users of
1681 * that function that require issuing of an atomic sequence of commands,
1682 * and quiesces the transmit path whenever it's taken.
1683 */
1684static int mwl8k_fw_lock(struct ieee80211_hw *hw)
1685{
1686 struct mwl8k_priv *priv = hw->priv;
1687
1688 if (priv->fw_mutex_owner != current) {
1689 int rc;
1690
1691 mutex_lock(&priv->fw_mutex);
1692 ieee80211_stop_queues(hw);
1693
1694 rc = mwl8k_tx_wait_empty(hw);
1695 if (rc) {
1696 ieee80211_wake_queues(hw);
1697 mutex_unlock(&priv->fw_mutex);
1698
1699 return rc;
1700 }
1701
1702 priv->fw_mutex_owner = current;
1703 }
1704
1705 priv->fw_mutex_depth++;
1706
1707 return 0;
1708}
1709
1710static void mwl8k_fw_unlock(struct ieee80211_hw *hw)
1711{
1712 struct mwl8k_priv *priv = hw->priv;
1713
1714 if (!--priv->fw_mutex_depth) {
1715 ieee80211_wake_queues(hw);
1716 priv->fw_mutex_owner = NULL;
1717 mutex_unlock(&priv->fw_mutex);
1718 }
1719}
1720
1721
a66098da
LB		 1722/*
1723 * Command processing.
1724 */
1725
0c9cc640
LB		 1726/* Timeout firmware commands after 10s */
1727#define MWL8K_CMD_TIMEOUT_MS 10000
a66098da
LB		 1728
1729static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
1730{
1731 DECLARE_COMPLETION_ONSTACK(cmd_wait);
1732 struct mwl8k_priv *priv = hw->priv;
1733 void __iomem *regs = priv->regs;
1734 dma_addr_t dma_addr;
1735 unsigned int dma_size;
1736 int rc;
a66098da
LB		 1737 unsigned long timeout = 0;
1738 u8 buf[32];
1739
b603742f 1740 cmd->result = (__force __le16) 0xffff;
a66098da
LB		 1741 dma_size = le16_to_cpu(cmd->length);
1742 dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
1743 PCI_DMA_BIDIRECTIONAL);
1744 if (pci_dma_mapping_error(priv->pdev, dma_addr))
1745 return -ENOMEM;
1746
618952a7 1747 rc = mwl8k_fw_lock(hw);
39a1e42e
LB		 1748 if (rc) {
1749 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1750 PCI_DMA_BIDIRECTIONAL);
618952a7 1751 return rc;
39a1e42e 1752 }
a66098da 1753
a66098da
LB		 1754 priv->hostcmd_wait = &cmd_wait;
1755 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
1756 iowrite32(MWL8K_H2A_INT_DOORBELL,
1757 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1758 iowrite32(MWL8K_H2A_INT_DUMMY,
1759 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
a66098da
LB		 1760
1761 timeout = wait_for_completion_timeout(&cmd_wait,
1762 msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
1763
618952a7
LB		 1764 priv->hostcmd_wait = NULL;
1765
1766 mwl8k_fw_unlock(hw);
1767
37055bd4
LB		 1768 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1769 PCI_DMA_BIDIRECTIONAL);
1770
a66098da 1771 if (!timeout) {
5db55844 1772 wiphy_err(hw->wiphy, "Command %s timeout after %u ms\n",
c96c31e4
JP		 1773 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1774 MWL8K_CMD_TIMEOUT_MS);
a66098da
LB		 1775 rc = -ETIMEDOUT;
1776 } else {
0c9cc640
LB		 1777 int ms;
1778
1779 ms = MWL8K_CMD_TIMEOUT_MS - jiffies_to_msecs(timeout);
1780
ce9e2e1b 1781 rc = cmd->result ? -EINVAL : 0;
a66098da 1782 if (rc)
5db55844 1783 wiphy_err(hw->wiphy, "Command %s error 0x%x\n",
c96c31e4
JP		 1784 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1785 le16_to_cpu(cmd->result));
0c9cc640 1786 else if (ms > 2000)
5db55844 1787 wiphy_notice(hw->wiphy, "Command %s took %d ms\n",
c96c31e4
JP		 1788 mwl8k_cmd_name(cmd->code,
1789 buf, sizeof(buf)),
1790 ms);
a66098da
LB		 1791 }
1792
a66098da
LB		 1793 return rc;
1794}
1795
f57ca9c1
LB		 1796static int mwl8k_post_pervif_cmd(struct ieee80211_hw *hw,
1797 struct ieee80211_vif *vif,
1798 struct mwl8k_cmd_pkt *cmd)
1799{
1800 if (vif != NULL)
1801 cmd->macid = MWL8K_VIF(vif)->macid;
1802 return mwl8k_post_cmd(hw, cmd);
1803}
1804
1349ad2f
LB		 1805/*
1806 * Setup code shared between STA and AP firmware images.
1807 */
1808static void mwl8k_setup_2ghz_band(struct ieee80211_hw *hw)
1809{
1810 struct mwl8k_priv *priv = hw->priv;
1811
1812 BUILD_BUG_ON(sizeof(priv->channels_24) != sizeof(mwl8k_channels_24));
1813 memcpy(priv->channels_24, mwl8k_channels_24, sizeof(mwl8k_channels_24));
1814
1815 BUILD_BUG_ON(sizeof(priv->rates_24) != sizeof(mwl8k_rates_24));
1816 memcpy(priv->rates_24, mwl8k_rates_24, sizeof(mwl8k_rates_24));
1817
1818 priv->band_24.band = IEEE80211_BAND_2GHZ;
1819 priv->band_24.channels = priv->channels_24;
1820 priv->band_24.n_channels = ARRAY_SIZE(mwl8k_channels_24);
1821 priv->band_24.bitrates = priv->rates_24;
1822 priv->band_24.n_bitrates = ARRAY_SIZE(mwl8k_rates_24);
1823
1824 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band_24;
1825}
1826
4eae9edd
LB		 1827static void mwl8k_setup_5ghz_band(struct ieee80211_hw *hw)
1828{
1829 struct mwl8k_priv *priv = hw->priv;
1830
1831 BUILD_BUG_ON(sizeof(priv->channels_50) != sizeof(mwl8k_channels_50));
1832 memcpy(priv->channels_50, mwl8k_channels_50, sizeof(mwl8k_channels_50));
1833
1834 BUILD_BUG_ON(sizeof(priv->rates_50) != sizeof(mwl8k_rates_50));
1835 memcpy(priv->rates_50, mwl8k_rates_50, sizeof(mwl8k_rates_50));
1836
1837 priv->band_50.band = IEEE80211_BAND_5GHZ;
1838 priv->band_50.channels = priv->channels_50;
1839 priv->band_50.n_channels = ARRAY_SIZE(mwl8k_channels_50);
1840 priv->band_50.bitrates = priv->rates_50;
1841 priv->band_50.n_bitrates = ARRAY_SIZE(mwl8k_rates_50);
1842
1843 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &priv->band_50;
1844}
1845
a66098da 1846/*
04b147b1 1847 * CMD_GET_HW_SPEC (STA version).
a66098da 1848 */
04b147b1 1849struct mwl8k_cmd_get_hw_spec_sta {
a66098da
LB		 1850 struct mwl8k_cmd_pkt header;
1851 __u8 hw_rev;
1852 __u8 host_interface;
1853 __le16 num_mcaddrs;
d89173f2 1854 __u8 perm_addr[ETH_ALEN];
a66098da
LB		 1855 __le16 region_code;
1856 __le32 fw_rev;
1857 __le32 ps_cookie;
1858 __le32 caps;
1859 __u8 mcs_bitmap[16];
1860 __le32 rx_queue_ptr;
1861 __le32 num_tx_queues;
1862 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1863 __le32 caps2;
1864 __le32 num_tx_desc_per_queue;
45eb400d 1865 __le32 total_rxd;
ba2d3587 1866} __packed;
a66098da 1867
341c9791
LB		 1868#define MWL8K_CAP_MAX_AMSDU 0x20000000
1869#define MWL8K_CAP_GREENFIELD 0x08000000
1870#define MWL8K_CAP_AMPDU 0x04000000
1871#define MWL8K_CAP_RX_STBC 0x01000000
1872#define MWL8K_CAP_TX_STBC 0x00800000
1873#define MWL8K_CAP_SHORTGI_40MHZ 0x00400000
1874#define MWL8K_CAP_SHORTGI_20MHZ 0x00200000
1875#define MWL8K_CAP_RX_ANTENNA_MASK 0x000e0000
1876#define MWL8K_CAP_TX_ANTENNA_MASK 0x0001c000
1877#define MWL8K_CAP_DELAY_BA 0x00003000
1878#define MWL8K_CAP_MIMO 0x00000200
1879#define MWL8K_CAP_40MHZ 0x00000100
06953235
LB		 1880#define MWL8K_CAP_BAND_MASK 0x00000007
1881#define MWL8K_CAP_5GHZ 0x00000004
1882#define MWL8K_CAP_2GHZ4 0x00000001
341c9791 1883
06953235
LB		 1884static void
1885mwl8k_set_ht_caps(struct ieee80211_hw *hw,
1886 struct ieee80211_supported_band *band, u32 cap)
341c9791 1887{
341c9791
LB		 1888 int rx_streams;
1889 int tx_streams;
1890
777ad375 1891 band->ht_cap.ht_supported = 1;
341c9791
LB		 1892
1893 if (cap & MWL8K_CAP_MAX_AMSDU)
777ad375 1894 band->ht_cap.cap |= IEEE80211_HT_CAP_MAX_AMSDU;
341c9791 1895 if (cap & MWL8K_CAP_GREENFIELD)
777ad375 1896 band->ht_cap.cap |= IEEE80211_HT_CAP_GRN_FLD;
341c9791
LB		 1897 if (cap & MWL8K_CAP_AMPDU) {
1898 hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION;
777ad375
LB		 1899 band->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
1900 band->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_NONE;
341c9791
LB		 1901 }
1902 if (cap & MWL8K_CAP_RX_STBC)
777ad375 1903 band->ht_cap.cap |= IEEE80211_HT_CAP_RX_STBC;
341c9791 1904 if (cap & MWL8K_CAP_TX_STBC)
777ad375 1905 band->ht_cap.cap |= IEEE80211_HT_CAP_TX_STBC;
341c9791 1906 if (cap & MWL8K_CAP_SHORTGI_40MHZ)
777ad375 1907 band->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
341c9791 1908 if (cap & MWL8K_CAP_SHORTGI_20MHZ)
777ad375 1909 band->ht_cap.cap |= IEEE80211_HT_CAP_SGI_20;
341c9791 1910 if (cap & MWL8K_CAP_DELAY_BA)
777ad375 1911 band->ht_cap.cap |= IEEE80211_HT_CAP_DELAY_BA;
341c9791 1912 if (cap & MWL8K_CAP_40MHZ)
777ad375 1913 band->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
341c9791
LB		 1914
1915 rx_streams = hweight32(cap & MWL8K_CAP_RX_ANTENNA_MASK);
1916 tx_streams = hweight32(cap & MWL8K_CAP_TX_ANTENNA_MASK);
1917
777ad375 1918 band->ht_cap.mcs.rx_mask[0] = 0xff;
341c9791 1919 if (rx_streams >= 2)
777ad375 1920 band->ht_cap.mcs.rx_mask[1] = 0xff;
341c9791 1921 if (rx_streams >= 3)
777ad375
LB		 1922 band->ht_cap.mcs.rx_mask[2] = 0xff;
1923 band->ht_cap.mcs.rx_mask[4] = 0x01;
1924 band->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
341c9791
LB		 1925
1926 if (rx_streams != tx_streams) {
777ad375
LB		 1927 band->ht_cap.mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
1928 band->ht_cap.mcs.tx_params |= (tx_streams - 1) <<
341c9791
LB		 1929 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
1930 }
1931}
1932
06953235
LB		 1933static void
1934mwl8k_set_caps(struct ieee80211_hw *hw, u32 caps)
1935{
1936 struct mwl8k_priv *priv = hw->priv;
1937
1938 if ((caps & MWL8K_CAP_2GHZ4) || !(caps & MWL8K_CAP_BAND_MASK)) {
1939 mwl8k_setup_2ghz_band(hw);
1940 if (caps & MWL8K_CAP_MIMO)
1941 mwl8k_set_ht_caps(hw, &priv->band_24, caps);
1942 }
1943
1944 if (caps & MWL8K_CAP_5GHZ) {
1945 mwl8k_setup_5ghz_band(hw);
1946 if (caps & MWL8K_CAP_MIMO)
1947 mwl8k_set_ht_caps(hw, &priv->band_50, caps);
1948 }
1949}
1950
04b147b1 1951static int mwl8k_cmd_get_hw_spec_sta(struct ieee80211_hw *hw)
a66098da
LB		 1952{
1953 struct mwl8k_priv *priv = hw->priv;
04b147b1 1954 struct mwl8k_cmd_get_hw_spec_sta *cmd;
a66098da
LB		 1955 int rc;
1956 int i;
1957
1958 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1959 if (cmd == NULL)
1960 return -ENOMEM;
1961
1962 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1963 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1964
1965 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1966 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
45eb400d 1967 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
4ff6432e 1968 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
a66098da 1969 for (i = 0; i < MWL8K_TX_QUEUES; i++)
45eb400d 1970 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
4ff6432e 1971 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
45eb400d 1972 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
a66098da
LB		 1973
1974 rc = mwl8k_post_cmd(hw, &cmd->header);
1975
1976 if (!rc) {
1977 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1978 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
4ff6432e 1979 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
a66098da 1980 priv->hw_rev = cmd->hw_rev;
06953235 1981 mwl8k_set_caps(hw, le32_to_cpu(cmd->caps));
ee0ddf18
LB		 1982 priv->ap_macids_supported = 0x00000000;
1983 priv->sta_macids_supported = 0x00000001;
a66098da
LB		 1984 }
1985
1986 kfree(cmd);
1987 return rc;
1988}
1989
42fba21d
LB		 1990/*
1991 * CMD_GET_HW_SPEC (AP version).
1992 */
1993struct mwl8k_cmd_get_hw_spec_ap {
1994 struct mwl8k_cmd_pkt header;
1995 __u8 hw_rev;
1996 __u8 host_interface;
1997 __le16 num_wcb;
1998 __le16 num_mcaddrs;
1999 __u8 perm_addr[ETH_ALEN];
2000 __le16 region_code;
2001 __le16 num_antenna;
2002 __le32 fw_rev;
2003 __le32 wcbbase0;
2004 __le32 rxwrptr;
2005 __le32 rxrdptr;
2006 __le32 ps_cookie;
2007 __le32 wcbbase1;
2008 __le32 wcbbase2;
2009 __le32 wcbbase3;
952a0e96 2010 __le32 fw_api_version;
ba2d3587 2011} __packed;
42fba21d
LB		 2012
2013static int mwl8k_cmd_get_hw_spec_ap(struct ieee80211_hw *hw)
2014{
2015 struct mwl8k_priv *priv = hw->priv;
2016 struct mwl8k_cmd_get_hw_spec_ap *cmd;
2017 int rc;
952a0e96 2018 u32 api_version;
42fba21d
LB		 2019
2020 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2021 if (cmd == NULL)
2022 return -ENOMEM;
2023
2024 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
2025 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2026
2027 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
2028 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
2029
2030 rc = mwl8k_post_cmd(hw, &cmd->header);
2031
2032 if (!rc) {
2033 int off;
2034
952a0e96
BC		 2035 api_version = le32_to_cpu(cmd->fw_api_version);
2036 if (priv->device_info->fw_api_ap != api_version) {
2037 printk(KERN_ERR "%s: Unsupported fw API version for %s."
2038 " Expected %d got %d.\n", MWL8K_NAME,
2039 priv->device_info->part_name,
2040 priv->device_info->fw_api_ap,
2041 api_version);
2042 rc = -EINVAL;
2043 goto done;
2044 }
42fba21d
LB		 2045 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
2046 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
2047 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
2048 priv->hw_rev = cmd->hw_rev;
1349ad2f 2049 mwl8k_setup_2ghz_band(hw);
ee0ddf18
LB		 2050 priv->ap_macids_supported = 0x000000ff;
2051 priv->sta_macids_supported = 0x00000000;
42fba21d
LB		 2052
2053 off = le32_to_cpu(cmd->wcbbase0) & 0xffff;
b603742f 2054 iowrite32(priv->txq[0].txd_dma, priv->sram + off);
42fba21d
LB		 2055
2056 off = le32_to_cpu(cmd->rxwrptr) & 0xffff;
b603742f 2057 iowrite32(priv->rxq[0].rxd_dma, priv->sram + off);
42fba21d
LB		 2058
2059 off = le32_to_cpu(cmd->rxrdptr) & 0xffff;
b603742f 2060 iowrite32(priv->rxq[0].rxd_dma, priv->sram + off);
42fba21d
LB		 2061
2062 off = le32_to_cpu(cmd->wcbbase1) & 0xffff;
b603742f 2063 iowrite32(priv->txq[1].txd_dma, priv->sram + off);
42fba21d
LB		 2064
2065 off = le32_to_cpu(cmd->wcbbase2) & 0xffff;
b603742f 2066 iowrite32(priv->txq[2].txd_dma, priv->sram + off);
42fba21d
LB		 2067
2068 off = le32_to_cpu(cmd->wcbbase3) & 0xffff;
b603742f 2069 iowrite32(priv->txq[3].txd_dma, priv->sram + off);
42fba21d
LB		 2070 }
2071
952a0e96 2072done:
42fba21d
LB		 2073 kfree(cmd);
2074 return rc;
2075}
2076
2077/*
2078 * CMD_SET_HW_SPEC.
2079 */
2080struct mwl8k_cmd_set_hw_spec {
2081 struct mwl8k_cmd_pkt header;
2082 __u8 hw_rev;
2083 __u8 host_interface;
2084 __le16 num_mcaddrs;
2085 __u8 perm_addr[ETH_ALEN];
2086 __le16 region_code;
2087 __le32 fw_rev;
2088 __le32 ps_cookie;
2089 __le32 caps;
2090 __le32 rx_queue_ptr;
2091 __le32 num_tx_queues;
2092 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
2093 __le32 flags;
2094 __le32 num_tx_desc_per_queue;
2095 __le32 total_rxd;
ba2d3587 2096} __packed;
42fba21d 2097
b64fe619
LB		 2098#define MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT 0x00000080
2099#define MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_PROBERESP 0x00000020
2100#define MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_BEACON 0x00000010
42fba21d
LB		 2101
2102static int mwl8k_cmd_set_hw_spec(struct ieee80211_hw *hw)
2103{
2104 struct mwl8k_priv *priv = hw->priv;
2105 struct mwl8k_cmd_set_hw_spec *cmd;
2106 int rc;
2107 int i;
2108
2109 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2110 if (cmd == NULL)
2111 return -ENOMEM;
2112
2113 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_HW_SPEC);
2114 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2115
2116 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
2117 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
2118 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
2119 for (i = 0; i < MWL8K_TX_QUEUES; i++)
2120 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
b64fe619
LB		 2121 cmd->flags = cpu_to_le32(MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT |
2122 MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_PROBERESP |
2123 MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_BEACON);
42fba21d
LB		 2124 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
2125 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
2126
2127 rc = mwl8k_post_cmd(hw, &cmd->header);
2128 kfree(cmd);
2129
2130 return rc;
2131}
2132
a66098da
LB		 2133/*
2134 * CMD_MAC_MULTICAST_ADR.
2135 */
2136struct mwl8k_cmd_mac_multicast_adr {
2137 struct mwl8k_cmd_pkt header;
2138 __le16 action;
2139 __le16 numaddr;
ce9e2e1b 2140 __u8 addr[0][ETH_ALEN];
a66098da
LB		 2141};
2142
d5e30845
LB		 2143#define MWL8K_ENABLE_RX_DIRECTED 0x0001
2144#define MWL8K_ENABLE_RX_MULTICAST 0x0002
2145#define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004
2146#define MWL8K_ENABLE_RX_BROADCAST 0x0008
ce9e2e1b 2147
e81cd2d6 2148static struct mwl8k_cmd_pkt *
447ced07 2149__mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti,
22bedad3 2150 struct netdev_hw_addr_list *mc_list)
a66098da 2151{
e81cd2d6 2152 struct mwl8k_priv *priv = hw->priv;
a66098da 2153 struct mwl8k_cmd_mac_multicast_adr *cmd;
e81cd2d6 2154 int size;
22bedad3
JP		 2155 int mc_count = 0;
2156
2157 if (mc_list)
2158 mc_count = netdev_hw_addr_list_count(mc_list);
e81cd2d6 2159
447ced07 2160 if (allmulti || mc_count > priv->num_mcaddrs) {
d5e30845
LB		 2161 allmulti = 1;
2162 mc_count = 0;
2163 }
e81cd2d6
LB		 2164
2165 size = sizeof(*cmd) + mc_count * ETH_ALEN;
ce9e2e1b 2166
e81cd2d6 2167 cmd = kzalloc(size, GFP_ATOMIC);
a66098da 2168 if (cmd == NULL)
e81cd2d6 2169 return NULL;
a66098da
LB		 2170
2171 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
2172 cmd->header.length = cpu_to_le16(size);
d5e30845
LB		 2173 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED |
2174 MWL8K_ENABLE_RX_BROADCAST);
2175
2176 if (allmulti) {
2177 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST);
2178 } else if (mc_count) {
22bedad3
JP		 2179 struct netdev_hw_addr *ha;
2180 int i = 0;
d5e30845
LB		 2181
2182 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
2183 cmd->numaddr = cpu_to_le16(mc_count);
22bedad3
JP		 2184 netdev_hw_addr_list_for_each(ha, mc_list) {
2185 memcpy(cmd->addr[i], ha->addr, ETH_ALEN);
a66098da 2186 }
a66098da
LB		 2187 }
2188
e81cd2d6 2189 return &cmd->header;
a66098da
LB		 2190}
2191
2192/*
55489b6e 2193 * CMD_GET_STAT.
a66098da 2194 */
55489b6e 2195struct mwl8k_cmd_get_stat {
a66098da 2196 struct mwl8k_cmd_pkt header;
a66098da 2197 __le32 stats[64];
ba2d3587 2198} __packed;
a66098da
LB		 2199
2200#define MWL8K_STAT_ACK_FAILURE 9
2201#define MWL8K_STAT_RTS_FAILURE 12
2202#define MWL8K_STAT_FCS_ERROR 24
2203#define MWL8K_STAT_RTS_SUCCESS 11
2204
55489b6e
LB		 2205static int mwl8k_cmd_get_stat(struct ieee80211_hw *hw,
2206 struct ieee80211_low_level_stats *stats)
a66098da 2207{
55489b6e 2208 struct mwl8k_cmd_get_stat *cmd;
a66098da
LB		 2209 int rc;
2210
2211 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2212 if (cmd == NULL)
2213 return -ENOMEM;
2214
2215 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
2216 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB		 2217
2218 rc = mwl8k_post_cmd(hw, &cmd->header);
2219 if (!rc) {
2220 stats->dot11ACKFailureCount =
2221 le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
2222 stats->dot11RTSFailureCount =
2223 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
2224 stats->dot11FCSErrorCount =
2225 le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
2226 stats->dot11RTSSuccessCount =
2227 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
2228 }
2229 kfree(cmd);
2230
2231 return rc;
2232}
2233
2234/*
55489b6e 2235 * CMD_RADIO_CONTROL.
a66098da 2236 */
55489b6e 2237struct mwl8k_cmd_radio_control {
a66098da
LB		 2238 struct mwl8k_cmd_pkt header;
2239 __le16 action;
2240 __le16 control;
2241 __le16 radio_on;
ba2d3587 2242} __packed;
a66098da 2243
c46563b7 2244static int
55489b6e 2245mwl8k_cmd_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
a66098da
LB		 2246{
2247 struct mwl8k_priv *priv = hw->priv;
55489b6e 2248 struct mwl8k_cmd_radio_control *cmd;
a66098da
LB		 2249 int rc;
2250
c46563b7 2251 if (enable == priv->radio_on && !force)
a66098da
LB		 2252 return 0;
2253
a66098da
LB		 2254 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2255 if (cmd == NULL)
2256 return -ENOMEM;
2257
2258 cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
2259 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2260 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
68ce3884 2261 cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
a66098da
LB		 2262 cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
2263
2264 rc = mwl8k_post_cmd(hw, &cmd->header);
2265 kfree(cmd);
2266
2267 if (!rc)
c46563b7 2268 priv->radio_on = enable;
a66098da
LB		 2269
2270 return rc;
2271}
2272
55489b6e 2273static int mwl8k_cmd_radio_disable(struct ieee80211_hw *hw)
c46563b7 2274{
55489b6e 2275 return mwl8k_cmd_radio_control(hw, 0, 0);
c46563b7
LB		 2276}
2277
55489b6e 2278static int mwl8k_cmd_radio_enable(struct ieee80211_hw *hw)
c46563b7 2279{
55489b6e 2280 return mwl8k_cmd_radio_control(hw, 1, 0);
c46563b7
LB		 2281}
2282
a66098da
LB		 2283static int
2284mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
2285{
99200a99 2286 struct mwl8k_priv *priv = hw->priv;
a66098da 2287
68ce3884 2288 priv->radio_short_preamble = short_preamble;
a66098da 2289
55489b6e 2290 return mwl8k_cmd_radio_control(hw, 1, 1);
a66098da
LB		 2291}
2292
2293/*
55489b6e 2294 * CMD_RF_TX_POWER.
a66098da 2295 */
41fdf097 2296#define MWL8K_RF_TX_POWER_LEVEL_TOTAL 8
a66098da 2297
55489b6e 2298struct mwl8k_cmd_rf_tx_power {
a66098da
LB		 2299 struct mwl8k_cmd_pkt header;
2300 __le16 action;
2301 __le16 support_level;
2302 __le16 current_level;
2303 __le16 reserved;
41fdf097 2304 __le16 power_level_list[MWL8K_RF_TX_POWER_LEVEL_TOTAL];
ba2d3587 2305} __packed;
a66098da 2306
55489b6e 2307static int mwl8k_cmd_rf_tx_power(struct ieee80211_hw *hw, int dBm)
a66098da 2308{
55489b6e 2309 struct mwl8k_cmd_rf_tx_power *cmd;
a66098da
LB		 2310 int rc;
2311
2312 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2313 if (cmd == NULL)
2314 return -ENOMEM;
2315
2316 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
2317 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2318 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2319 cmd->support_level = cpu_to_le16(dBm);
2320
2321 rc = mwl8k_post_cmd(hw, &cmd->header);
2322 kfree(cmd);
2323
2324 return rc;
2325}
2326
41fdf097
NS		 2327/*
2328 * CMD_TX_POWER.
2329 */
2330#define MWL8K_TX_POWER_LEVEL_TOTAL 12
2331
2332struct mwl8k_cmd_tx_power {
2333 struct mwl8k_cmd_pkt header;
2334 __le16 action;
2335 __le16 band;
2336 __le16 channel;
2337 __le16 bw;
2338 __le16 sub_ch;
2339 __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
2340} __attribute__((packed));
2341
2342static int mwl8k_cmd_tx_power(struct ieee80211_hw *hw,
2343 struct ieee80211_conf *conf,
2344 unsigned short pwr)
2345{
2346 struct ieee80211_channel *channel = conf->channel;
2347 struct mwl8k_cmd_tx_power *cmd;
2348 int rc;
2349 int i;
2350
2351 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2352 if (cmd == NULL)
2353 return -ENOMEM;
2354
2355 cmd->header.code = cpu_to_le16(MWL8K_CMD_TX_POWER);
2356 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2357 cmd->action = cpu_to_le16(MWL8K_CMD_SET_LIST);
2358
2359 if (channel->band == IEEE80211_BAND_2GHZ)
2360 cmd->band = cpu_to_le16(0x1);
2361 else if (channel->band == IEEE80211_BAND_5GHZ)
2362 cmd->band = cpu_to_le16(0x4);
2363
2364 cmd->channel = channel->hw_value;
2365
2366 if (conf->channel_type == NL80211_CHAN_NO_HT ||
2367 conf->channel_type == NL80211_CHAN_HT20) {
2368 cmd->bw = cpu_to_le16(0x2);
2369 } else {
2370 cmd->bw = cpu_to_le16(0x4);
2371 if (conf->channel_type == NL80211_CHAN_HT40MINUS)
2372 cmd->sub_ch = cpu_to_le16(0x3);
2373 else if (conf->channel_type == NL80211_CHAN_HT40PLUS)
2374 cmd->sub_ch = cpu_to_le16(0x1);
2375 }
2376
2377 for (i = 0; i < MWL8K_TX_POWER_LEVEL_TOTAL; i++)
2378 cmd->power_level_list[i] = cpu_to_le16(pwr);
2379
2380 rc = mwl8k_post_cmd(hw, &cmd->header);
2381 kfree(cmd);
2382
2383 return rc;
2384}
2385
08b06347
LB		 2386/*
2387 * CMD_RF_ANTENNA.
2388 */
2389struct mwl8k_cmd_rf_antenna {
2390 struct mwl8k_cmd_pkt header;
2391 __le16 antenna;
2392 __le16 mode;
ba2d3587 2393} __packed;
08b06347
LB		 2394
2395#define MWL8K_RF_ANTENNA_RX 1
2396#define MWL8K_RF_ANTENNA_TX 2
2397
2398static int
2399mwl8k_cmd_rf_antenna(struct ieee80211_hw *hw, int antenna, int mask)
2400{
2401 struct mwl8k_cmd_rf_antenna *cmd;
2402 int rc;
2403
2404 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2405 if (cmd == NULL)
2406 return -ENOMEM;
2407
2408 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_ANTENNA);
2409 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2410 cmd->antenna = cpu_to_le16(antenna);
2411 cmd->mode = cpu_to_le16(mask);
2412
2413 rc = mwl8k_post_cmd(hw, &cmd->header);
2414 kfree(cmd);
2415
2416 return rc;
2417}
2418
b64fe619
LB		 2419/*
2420 * CMD_SET_BEACON.
2421 */
2422struct mwl8k_cmd_set_beacon {
2423 struct mwl8k_cmd_pkt header;
2424 __le16 beacon_len;
2425 __u8 beacon[0];
2426};
2427
aa21d0f6
LB		 2428static int mwl8k_cmd_set_beacon(struct ieee80211_hw *hw,
2429 struct ieee80211_vif *vif, u8 *beacon, int len)
b64fe619
LB		 2430{
2431 struct mwl8k_cmd_set_beacon *cmd;
2432 int rc;
2433
2434 cmd = kzalloc(sizeof(*cmd) + len, GFP_KERNEL);
2435 if (cmd == NULL)
2436 return -ENOMEM;
2437
2438 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_BEACON);
2439 cmd->header.length = cpu_to_le16(sizeof(*cmd) + len);
2440 cmd->beacon_len = cpu_to_le16(len);
2441 memcpy(cmd->beacon, beacon, len);
2442
aa21d0f6 2443 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
b64fe619
LB		 2444 kfree(cmd);
2445
2446 return rc;
2447}
2448
a66098da
LB		 2449/*
2450 * CMD_SET_PRE_SCAN.
2451 */
2452struct mwl8k_cmd_set_pre_scan {
2453 struct mwl8k_cmd_pkt header;
ba2d3587 2454} __packed;
a66098da
LB		 2455
2456static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
2457{
2458 struct mwl8k_cmd_set_pre_scan *cmd;
2459 int rc;
2460
2461 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2462 if (cmd == NULL)
2463 return -ENOMEM;
2464
2465 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
2466 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2467
2468 rc = mwl8k_post_cmd(hw, &cmd->header);
2469 kfree(cmd);
2470
2471 return rc;
2472}
2473
2474/*
2475 * CMD_SET_POST_SCAN.
2476 */
2477struct mwl8k_cmd_set_post_scan {
2478 struct mwl8k_cmd_pkt header;
2479 __le32 isibss;
d89173f2 2480 __u8 bssid[ETH_ALEN];
ba2d3587 2481} __packed;
a66098da
LB		 2482
2483static int
0a11dfc3 2484mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, const __u8 *mac)
a66098da
LB		 2485{
2486 struct mwl8k_cmd_set_post_scan *cmd;
2487 int rc;
2488
2489 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2490 if (cmd == NULL)
2491 return -ENOMEM;
2492
2493 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
2494 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2495 cmd->isibss = 0;
d89173f2 2496 memcpy(cmd->bssid, mac, ETH_ALEN);
a66098da
LB		 2497
2498 rc = mwl8k_post_cmd(hw, &cmd->header);
2499 kfree(cmd);
2500
2501 return rc;
2502}
2503
2504/*
2505 * CMD_SET_RF_CHANNEL.
2506 */
2507struct mwl8k_cmd_set_rf_channel {
2508 struct mwl8k_cmd_pkt header;
2509 __le16 action;
2510 __u8 current_channel;
2511 __le32 channel_flags;
ba2d3587 2512} __packed;
a66098da
LB		 2513
2514static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
610677d2 2515 struct ieee80211_conf *conf)
a66098da 2516{
610677d2 2517 struct ieee80211_channel *channel = conf->channel;
a66098da
LB		 2518 struct mwl8k_cmd_set_rf_channel *cmd;
2519 int rc;
2520
2521 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2522 if (cmd == NULL)
2523 return -ENOMEM;
2524
2525 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
2526 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2527 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2528 cmd->current_channel = channel->hw_value;
610677d2 2529
a66098da 2530 if (channel->band == IEEE80211_BAND_2GHZ)
610677d2 2531 cmd->channel_flags |= cpu_to_le32(0x00000001);
42574ea2
LB		 2532 else if (channel->band == IEEE80211_BAND_5GHZ)
2533 cmd->channel_flags |= cpu_to_le32(0x00000004);
610677d2
LB		 2534
2535 if (conf->channel_type == NL80211_CHAN_NO_HT ||
2536 conf->channel_type == NL80211_CHAN_HT20)
2537 cmd->channel_flags |= cpu_to_le32(0x00000080);
2538 else if (conf->channel_type == NL80211_CHAN_HT40MINUS)
2539 cmd->channel_flags |= cpu_to_le32(0x000001900);
2540 else if (conf->channel_type == NL80211_CHAN_HT40PLUS)
2541 cmd->channel_flags |= cpu_to_le32(0x000000900);
a66098da
LB		 2542
2543 rc = mwl8k_post_cmd(hw, &cmd->header);
2544 kfree(cmd);
2545
2546 return rc;
2547}
2548
2549/*
55489b6e 2550 * CMD_SET_AID.
a66098da 2551 */
55489b6e
LB		 2552#define MWL8K_FRAME_PROT_DISABLED 0x00
2553#define MWL8K_FRAME_PROT_11G 0x07
2554#define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
2555#define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
a66098da 2556
55489b6e
LB		 2557struct mwl8k_cmd_update_set_aid {
2558 struct mwl8k_cmd_pkt header;
2559 __le16 aid;
a66098da 2560
55489b6e
LB		 2561 /* AP's MAC address (BSSID) */
2562 __u8 bssid[ETH_ALEN];
2563 __le16 protection_mode;
2564 __u8 supp_rates[14];
ba2d3587 2565} __packed;
a66098da 2566
c6e96010
LB		 2567static void legacy_rate_mask_to_array(u8 *rates, u32 mask)
2568{
2569 int i;
2570 int j;
2571
2572 /*
2573 * Clear nonstandard rates 4 and 13.
2574 */
2575 mask &= 0x1fef;
2576
2577 for (i = 0, j = 0; i < 14; i++) {
2578 if (mask & (1 << i))
777ad375 2579 rates[j++] = mwl8k_rates_24[i].hw_value;
c6e96010
LB		 2580 }
2581}
2582
55489b6e 2583static int
c6e96010
LB		 2584mwl8k_cmd_set_aid(struct ieee80211_hw *hw,
2585 struct ieee80211_vif *vif, u32 legacy_rate_mask)
a66098da 2586{
55489b6e
LB		 2587 struct mwl8k_cmd_update_set_aid *cmd;
2588 u16 prot_mode;
a66098da
LB		 2589 int rc;
2590
2591 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2592 if (cmd == NULL)
2593 return -ENOMEM;
2594
55489b6e 2595 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
a66098da 2596 cmd->header.length = cpu_to_le16(sizeof(*cmd));
7dc6a7a7 2597 cmd->aid = cpu_to_le16(vif->bss_conf.aid);
0a11dfc3 2598 memcpy(cmd->bssid, vif->bss_conf.bssid, ETH_ALEN);
a66098da 2599
7dc6a7a7 2600 if (vif->bss_conf.use_cts_prot) {
55489b6e
LB		 2601 prot_mode = MWL8K_FRAME_PROT_11G;
2602 } else {
7dc6a7a7 2603 switch (vif->bss_conf.ht_operation_mode &
55489b6e
LB		 2604 IEEE80211_HT_OP_MODE_PROTECTION) {
2605 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
2606 prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
2607 break;
2608 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
2609 prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
2610 break;
2611 default:
2612 prot_mode = MWL8K_FRAME_PROT_DISABLED;
2613 break;
2614 }
2615 }
2616 cmd->protection_mode = cpu_to_le16(prot_mode);
a66098da 2617
c6e96010 2618 legacy_rate_mask_to_array(cmd->supp_rates, legacy_rate_mask);
a66098da
LB		 2619
2620 rc = mwl8k_post_cmd(hw, &cmd->header);
2621 kfree(cmd);
2622
2623 return rc;
2624}
2625
32060e1b 2626/*
55489b6e 2627 * CMD_SET_RATE.
32060e1b 2628 */
55489b6e
LB		 2629struct mwl8k_cmd_set_rate {
2630 struct mwl8k_cmd_pkt header;
2631 __u8 legacy_rates[14];
2632
2633 /* Bitmap for supported MCS codes. */
2634 __u8 mcs_set[16];
2635 __u8 reserved[16];
ba2d3587 2636} __packed;
32060e1b 2637
55489b6e 2638static int
c6e96010 2639mwl8k_cmd_set_rate(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
13935e2c 2640 u32 legacy_rate_mask, u8 *mcs_rates)
32060e1b 2641{
55489b6e 2642 struct mwl8k_cmd_set_rate *cmd;
32060e1b
LB		 2643 int rc;
2644
2645 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2646 if (cmd == NULL)
2647 return -ENOMEM;
2648
55489b6e 2649 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
32060e1b 2650 cmd->header.length = cpu_to_le16(sizeof(*cmd));
c6e96010 2651 legacy_rate_mask_to_array(cmd->legacy_rates, legacy_rate_mask);
13935e2c 2652 memcpy(cmd->mcs_set, mcs_rates, 16);
32060e1b
LB		 2653
2654 rc = mwl8k_post_cmd(hw, &cmd->header);
2655 kfree(cmd);
2656
2657 return rc;
2658}
2659
a66098da 2660/*
55489b6e 2661 * CMD_FINALIZE_JOIN.
a66098da 2662 */
55489b6e
LB		 2663#define MWL8K_FJ_BEACON_MAXLEN 128
2664
2665struct mwl8k_cmd_finalize_join {
a66098da 2666 struct mwl8k_cmd_pkt header;
55489b6e
LB		 2667 __le32 sleep_interval; /* Number of beacon periods to sleep */
2668 __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
ba2d3587 2669} __packed;
a66098da 2670
55489b6e
LB		 2671static int mwl8k_cmd_finalize_join(struct ieee80211_hw *hw, void *frame,
2672 int framelen, int dtim)
a66098da 2673{
55489b6e
LB		 2674 struct mwl8k_cmd_finalize_join *cmd;
2675 struct ieee80211_mgmt *payload = frame;
2676 int payload_len;
a66098da
LB		 2677 int rc;
2678
2679 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2680 if (cmd == NULL)
2681 return -ENOMEM;
2682
55489b6e 2683 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
a66098da 2684 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB		 2685 cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
2686
2687 payload_len = framelen - ieee80211_hdrlen(payload->frame_control);
2688 if (payload_len < 0)
2689 payload_len = 0;
2690 else if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2691 payload_len = MWL8K_FJ_BEACON_MAXLEN;
2692
2693 memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
a66098da
LB		 2694
2695 rc = mwl8k_post_cmd(hw, &cmd->header);
2696 kfree(cmd);
2697
2698 return rc;
2699}
2700
2701/*
55489b6e 2702 * CMD_SET_RTS_THRESHOLD.
a66098da 2703 */
55489b6e 2704struct mwl8k_cmd_set_rts_threshold {
a66098da
LB		 2705 struct mwl8k_cmd_pkt header;
2706 __le16 action;
55489b6e 2707 __le16 threshold;
ba2d3587 2708} __packed;
a66098da 2709
c2c2b12a
LB		 2710static int
2711mwl8k_cmd_set_rts_threshold(struct ieee80211_hw *hw, int rts_thresh)
a66098da 2712{
55489b6e 2713 struct mwl8k_cmd_set_rts_threshold *cmd;
a66098da
LB		 2714 int rc;
2715
2716 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2717 if (cmd == NULL)
2718 return -ENOMEM;
2719
55489b6e 2720 cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
a66098da 2721 cmd->header.length = cpu_to_le16(sizeof(*cmd));
c2c2b12a
LB		 2722 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2723 cmd->threshold = cpu_to_le16(rts_thresh);
a66098da
LB		 2724
2725 rc = mwl8k_post_cmd(hw, &cmd->header);
2726 kfree(cmd);
2727
a66098da
LB		 2728 return rc;
2729}
2730
2731/*
55489b6e 2732 * CMD_SET_SLOT.
a66098da 2733 */
55489b6e 2734struct mwl8k_cmd_set_slot {
a66098da
LB		 2735 struct mwl8k_cmd_pkt header;
2736 __le16 action;
55489b6e 2737 __u8 short_slot;
ba2d3587 2738} __packed;
a66098da 2739
55489b6e 2740static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time)
a66098da 2741{
55489b6e 2742 struct mwl8k_cmd_set_slot *cmd;
a66098da
LB		 2743 int rc;
2744
2745 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2746 if (cmd == NULL)
2747 return -ENOMEM;
2748
55489b6e 2749 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
a66098da 2750 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB		 2751 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2752 cmd->short_slot = short_slot_time;
a66098da
LB		 2753
2754 rc = mwl8k_post_cmd(hw, &cmd->header);
2755 kfree(cmd);
2756
2757 return rc;
2758}
2759
2760/*
2761 * CMD_SET_EDCA_PARAMS.
2762 */
2763struct mwl8k_cmd_set_edca_params {
2764 struct mwl8k_cmd_pkt header;
2765
2766 /* See MWL8K_SET_EDCA_XXX below */
2767 __le16 action;
2768
2769 /* TX opportunity in units of 32 us */
2770 __le16 txop;
2771
2e484c89
LB		 2772 union {
2773 struct {
2774 /* Log exponent of max contention period: 0...15 */
2775 __le32 log_cw_max;
2776
2777 /* Log exponent of min contention period: 0...15 */
2778 __le32 log_cw_min;
2779
2780 /* Adaptive interframe spacing in units of 32us */
2781 __u8 aifs;
2782
2783 /* TX queue to configure */
2784 __u8 txq;
2785 } ap;
2786 struct {
2787 /* Log exponent of max contention period: 0...15 */
2788 __u8 log_cw_max;
a66098da 2789
2e484c89
LB		 2790 /* Log exponent of min contention period: 0...15 */
2791 __u8 log_cw_min;
a66098da 2792
2e484c89
LB		 2793 /* Adaptive interframe spacing in units of 32us */
2794 __u8 aifs;
a66098da 2795
2e484c89
LB		 2796 /* TX queue to configure */
2797 __u8 txq;
2798 } sta;
2799 };
ba2d3587 2800} __packed;
a66098da 2801
a66098da
LB		 2802#define MWL8K_SET_EDCA_CW 0x01
2803#define MWL8K_SET_EDCA_TXOP 0x02
2804#define MWL8K_SET_EDCA_AIFS 0x04
2805
2806#define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
2807 MWL8K_SET_EDCA_TXOP | \
2808 MWL8K_SET_EDCA_AIFS)
2809
2810static int
55489b6e
LB		 2811mwl8k_cmd_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
2812 __u16 cw_min, __u16 cw_max,
2813 __u8 aifs, __u16 txop)
a66098da 2814{
2e484c89 2815 struct mwl8k_priv *priv = hw->priv;
a66098da 2816 struct mwl8k_cmd_set_edca_params *cmd;
a66098da
LB		 2817 int rc;
2818
2819 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2820 if (cmd == NULL)
2821 return -ENOMEM;
2822
a66098da
LB		 2823 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
2824 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB		 2825 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
2826 cmd->txop = cpu_to_le16(txop);
2e484c89
LB		 2827 if (priv->ap_fw) {
2828 cmd->ap.log_cw_max = cpu_to_le32(ilog2(cw_max + 1));
2829 cmd->ap.log_cw_min = cpu_to_le32(ilog2(cw_min + 1));
2830 cmd->ap.aifs = aifs;
2831 cmd->ap.txq = qnum;
2832 } else {
2833 cmd->sta.log_cw_max = (u8)ilog2(cw_max + 1);
2834 cmd->sta.log_cw_min = (u8)ilog2(cw_min + 1);
2835 cmd->sta.aifs = aifs;
2836 cmd->sta.txq = qnum;
2837 }
a66098da
LB		 2838
2839 rc = mwl8k_post_cmd(hw, &cmd->header);
2840 kfree(cmd);
2841
2842 return rc;
2843}
2844
2845/*
55489b6e 2846 * CMD_SET_WMM_MODE.
a66098da 2847 */
55489b6e 2848struct mwl8k_cmd_set_wmm_mode {
a66098da 2849 struct mwl8k_cmd_pkt header;
55489b6e 2850 __le16 action;
ba2d3587 2851} __packed;
a66098da 2852
55489b6e 2853static int mwl8k_cmd_set_wmm_mode(struct ieee80211_hw *hw, bool enable)
a66098da 2854{
55489b6e
LB		 2855 struct mwl8k_priv *priv = hw->priv;
2856 struct mwl8k_cmd_set_wmm_mode *cmd;
a66098da
LB		 2857 int rc;
2858
a66098da
LB		 2859 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2860 if (cmd == NULL)
2861 return -ENOMEM;
2862
55489b6e 2863 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
a66098da 2864 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e 2865 cmd->action = cpu_to_le16(!!enable);
a66098da
LB		 2866
2867 rc = mwl8k_post_cmd(hw, &cmd->header);
2868 kfree(cmd);
16cec43d 2869
55489b6e
LB		 2870 if (!rc)
2871 priv->wmm_enabled = enable;
a66098da
LB		 2872
2873 return rc;
2874}
2875
2876/*
55489b6e 2877 * CMD_MIMO_CONFIG.
a66098da 2878 */
55489b6e
LB		 2879struct mwl8k_cmd_mimo_config {
2880 struct mwl8k_cmd_pkt header;
2881 __le32 action;
2882 __u8 rx_antenna_map;
2883 __u8 tx_antenna_map;
ba2d3587 2884} __packed;
a66098da 2885
55489b6e 2886static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
a66098da 2887{
55489b6e 2888 struct mwl8k_cmd_mimo_config *cmd;
a66098da
LB		 2889 int rc;
2890
2891 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2892 if (cmd == NULL)
2893 return -ENOMEM;
2894
55489b6e 2895 cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
a66098da 2896 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB		 2897 cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
2898 cmd->rx_antenna_map = rx;
2899 cmd->tx_antenna_map = tx;
a66098da
LB		 2900
2901 rc = mwl8k_post_cmd(hw, &cmd->header);
2902 kfree(cmd);
2903
2904 return rc;
2905}
2906
2907/*
b71ed2c6 2908 * CMD_USE_FIXED_RATE (STA version).
a66098da 2909 */
b71ed2c6
LB		 2910struct mwl8k_cmd_use_fixed_rate_sta {
2911 struct mwl8k_cmd_pkt header;
2912 __le32 action;
2913 __le32 allow_rate_drop;
2914 __le32 num_rates;
2915 struct {
2916 __le32 is_ht_rate;
2917 __le32 enable_retry;
2918 __le32 rate;
2919 __le32 retry_count;
2920 } rate_entry[8];
2921 __le32 rate_type;
2922 __le32 reserved1;
2923 __le32 reserved2;
ba2d3587 2924} __packed;
a66098da 2925
b71ed2c6
LB		 2926#define MWL8K_USE_AUTO_RATE 0x0002
2927#define MWL8K_UCAST_RATE 0
a66098da 2928
b71ed2c6 2929static int mwl8k_cmd_use_fixed_rate_sta(struct ieee80211_hw *hw)
a66098da 2930{
b71ed2c6 2931 struct mwl8k_cmd_use_fixed_rate_sta *cmd;
a66098da
LB		 2932 int rc;
2933
2934 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2935 if (cmd == NULL)
2936 return -ENOMEM;
2937
2938 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
2939 cmd->header.length = cpu_to_le16(sizeof(*cmd));
b71ed2c6
LB		 2940 cmd->action = cpu_to_le32(MWL8K_USE_AUTO_RATE);
2941 cmd->rate_type = cpu_to_le32(MWL8K_UCAST_RATE);
a66098da
LB		 2942
2943 rc = mwl8k_post_cmd(hw, &cmd->header);
2944 kfree(cmd);
2945
2946 return rc;
2947}
2948
088aab8b
LB		 2949/*
2950 * CMD_USE_FIXED_RATE (AP version).
2951 */
2952struct mwl8k_cmd_use_fixed_rate_ap {
2953 struct mwl8k_cmd_pkt header;
2954 __le32 action;
2955 __le32 allow_rate_drop;
2956 __le32 num_rates;
2957 struct mwl8k_rate_entry_ap {
2958 __le32 is_ht_rate;
2959 __le32 enable_retry;
2960 __le32 rate;
2961 __le32 retry_count;
2962 } rate_entry[4];
2963 u8 multicast_rate;
2964 u8 multicast_rate_type;
2965 u8 management_rate;
ba2d3587 2966} __packed;
088aab8b
LB		 2967
2968static int
2969mwl8k_cmd_use_fixed_rate_ap(struct ieee80211_hw *hw, int mcast, int mgmt)
2970{
2971 struct mwl8k_cmd_use_fixed_rate_ap *cmd;
2972 int rc;
2973
2974 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2975 if (cmd == NULL)
2976 return -ENOMEM;
2977
2978 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
2979 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2980 cmd->action = cpu_to_le32(MWL8K_USE_AUTO_RATE);
2981 cmd->multicast_rate = mcast;
2982 cmd->management_rate = mgmt;
2983
2984 rc = mwl8k_post_cmd(hw, &cmd->header);
2985 kfree(cmd);
2986
2987 return rc;
2988}
2989
55489b6e
LB		 2990/*
2991 * CMD_ENABLE_SNIFFER.
2992 */
2993struct mwl8k_cmd_enable_sniffer {
2994 struct mwl8k_cmd_pkt header;
2995 __le32 action;
ba2d3587 2996} __packed;
55489b6e
LB		 2997
2998static int mwl8k_cmd_enable_sniffer(struct ieee80211_hw *hw, bool enable)
2999{
3000 struct mwl8k_cmd_enable_sniffer *cmd;
3001 int rc;
3002
3003 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3004 if (cmd == NULL)
3005 return -ENOMEM;
3006
3007 cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
3008 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3009 cmd->action = cpu_to_le32(!!enable);
3010
3011 rc = mwl8k_post_cmd(hw, &cmd->header);
3012 kfree(cmd);
3013
3014 return rc;
3015}
3016
3017/*
3018 * CMD_SET_MAC_ADDR.
3019 */
3020struct mwl8k_cmd_set_mac_addr {
3021 struct mwl8k_cmd_pkt header;
3022 union {
3023 struct {
3024 __le16 mac_type;
3025 __u8 mac_addr[ETH_ALEN];
3026 } mbss;
3027 __u8 mac_addr[ETH_ALEN];
3028 };
ba2d3587 3029} __packed;
55489b6e 3030
ee0ddf18
LB		 3031#define MWL8K_MAC_TYPE_PRIMARY_CLIENT 0
3032#define MWL8K_MAC_TYPE_SECONDARY_CLIENT 1
3033#define MWL8K_MAC_TYPE_PRIMARY_AP 2
3034#define MWL8K_MAC_TYPE_SECONDARY_AP 3
a9e00b15 3035
aa21d0f6
LB		 3036static int mwl8k_cmd_set_mac_addr(struct ieee80211_hw *hw,
3037 struct ieee80211_vif *vif, u8 *mac)
55489b6e
LB		 3038{
3039 struct mwl8k_priv *priv = hw->priv;
ee0ddf18 3040 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
55489b6e 3041 struct mwl8k_cmd_set_mac_addr *cmd;
ee0ddf18 3042 int mac_type;
55489b6e
LB		 3043 int rc;
3044
ee0ddf18
LB		 3045 mac_type = MWL8K_MAC_TYPE_PRIMARY_AP;
3046 if (vif != NULL && vif->type == NL80211_IFTYPE_STATION) {
3047 if (mwl8k_vif->macid + 1 == ffs(priv->sta_macids_supported))
3048 mac_type = MWL8K_MAC_TYPE_PRIMARY_CLIENT;
3049 else
3050 mac_type = MWL8K_MAC_TYPE_SECONDARY_CLIENT;
3051 } else if (vif != NULL && vif->type == NL80211_IFTYPE_AP) {
3052 if (mwl8k_vif->macid + 1 == ffs(priv->ap_macids_supported))
3053 mac_type = MWL8K_MAC_TYPE_PRIMARY_AP;
3054 else
3055 mac_type = MWL8K_MAC_TYPE_SECONDARY_AP;
3056 }
3057
55489b6e
LB		 3058 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3059 if (cmd == NULL)
3060 return -ENOMEM;
3061
3062 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR);
3063 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3064 if (priv->ap_fw) {
ee0ddf18 3065 cmd->mbss.mac_type = cpu_to_le16(mac_type);
55489b6e
LB		 3066 memcpy(cmd->mbss.mac_addr, mac, ETH_ALEN);
3067 } else {
3068 memcpy(cmd->mac_addr, mac, ETH_ALEN);
3069 }
3070
aa21d0f6 3071 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
55489b6e
LB		 3072 kfree(cmd);
3073
3074 return rc;
3075}
3076
3077/*
3078 * CMD_SET_RATEADAPT_MODE.
3079 */
3080struct mwl8k_cmd_set_rate_adapt_mode {
3081 struct mwl8k_cmd_pkt header;
3082 __le16 action;
3083 __le16 mode;
ba2d3587 3084} __packed;
55489b6e
LB		 3085
3086static int mwl8k_cmd_set_rateadapt_mode(struct ieee80211_hw *hw, __u16 mode)
3087{
3088 struct mwl8k_cmd_set_rate_adapt_mode *cmd;
3089 int rc;
3090
3091 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3092 if (cmd == NULL)
3093 return -ENOMEM;
3094
3095 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
3096 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3097 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
3098 cmd->mode = cpu_to_le16(mode);
3099
3100 rc = mwl8k_post_cmd(hw, &cmd->header);
3101 kfree(cmd);
3102
3103 return rc;
3104}
3105
b64fe619
LB		 3106/*
3107 * CMD_BSS_START.
3108 */
3109struct mwl8k_cmd_bss_start {
3110 struct mwl8k_cmd_pkt header;
3111 __le32 enable;
ba2d3587 3112} __packed;
b64fe619 3113
aa21d0f6
LB		 3114static int mwl8k_cmd_bss_start(struct ieee80211_hw *hw,
3115 struct ieee80211_vif *vif, int enable)
b64fe619
LB		 3116{
3117 struct mwl8k_cmd_bss_start *cmd;
3118 int rc;
3119
3120 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3121 if (cmd == NULL)
3122 return -ENOMEM;
3123
3124 cmd->header.code = cpu_to_le16(MWL8K_CMD_BSS_START);
3125 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3126 cmd->enable = cpu_to_le32(enable);
3127
aa21d0f6 3128 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
b64fe619
LB		 3129 kfree(cmd);
3130
3131 return rc;
3132}
3133
3f5610ff
LB		 3134/*
3135 * CMD_SET_NEW_STN.
3136 */
3137struct mwl8k_cmd_set_new_stn {
3138 struct mwl8k_cmd_pkt header;
3139 __le16 aid;
3140 __u8 mac_addr[6];
3141 __le16 stn_id;
3142 __le16 action;
3143 __le16 rsvd;
3144 __le32 legacy_rates;
3145 __u8 ht_rates[4];
3146 __le16 cap_info;
3147 __le16 ht_capabilities_info;
3148 __u8 mac_ht_param_info;
3149 __u8 rev;
3150 __u8 control_channel;
3151 __u8 add_channel;
3152 __le16 op_mode;
3153 __le16 stbc;
3154 __u8 add_qos_info;
3155 __u8 is_qos_sta;
3156 __le32 fw_sta_ptr;
ba2d3587 3157} __packed;
3f5610ff
LB		 3158
3159#define MWL8K_STA_ACTION_ADD 0
3160#define MWL8K_STA_ACTION_REMOVE 2
3161
3162static int mwl8k_cmd_set_new_stn_add(struct ieee80211_hw *hw,
3163 struct ieee80211_vif *vif,
3164 struct ieee80211_sta *sta)
3165{
3166 struct mwl8k_cmd_set_new_stn *cmd;
8707d026 3167 u32 rates;
3f5610ff
LB		 3168 int rc;
3169
3170 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3171 if (cmd == NULL)
3172 return -ENOMEM;
3173
3174 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
3175 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3176 cmd->aid = cpu_to_le16(sta->aid);
3177 memcpy(cmd->mac_addr, sta->addr, ETH_ALEN);
3178 cmd->stn_id = cpu_to_le16(sta->aid);
3179 cmd->action = cpu_to_le16(MWL8K_STA_ACTION_ADD);
8707d026
LB		 3180 if (hw->conf.channel->band == IEEE80211_BAND_2GHZ)
3181 rates = sta->supp_rates[IEEE80211_BAND_2GHZ];
3182 else
3183 rates = sta->supp_rates[IEEE80211_BAND_5GHZ] << 5;
3184 cmd->legacy_rates = cpu_to_le32(rates);
3f5610ff
LB		 3185 if (sta->ht_cap.ht_supported) {
3186 cmd->ht_rates[0] = sta->ht_cap.mcs.rx_mask[0];
3187 cmd->ht_rates[1] = sta->ht_cap.mcs.rx_mask[1];
3188 cmd->ht_rates[2] = sta->ht_cap.mcs.rx_mask[2];
3189 cmd->ht_rates[3] = sta->ht_cap.mcs.rx_mask[3];
3190 cmd->ht_capabilities_info = cpu_to_le16(sta->ht_cap.cap);
3191 cmd->mac_ht_param_info = (sta->ht_cap.ampdu_factor & 3) |
3192 ((sta->ht_cap.ampdu_density & 7) << 2);
3193 cmd->is_qos_sta = 1;
3194 }
3195
aa21d0f6 3196 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
3f5610ff
LB		 3197 kfree(cmd);
3198
3199 return rc;
3200}
3201
b64fe619
LB		 3202static int mwl8k_cmd_set_new_stn_add_self(struct ieee80211_hw *hw,
3203 struct ieee80211_vif *vif)
3204{
3205 struct mwl8k_cmd_set_new_stn *cmd;
3206 int rc;
3207
3208 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3209 if (cmd == NULL)
3210 return -ENOMEM;
3211
3212 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
3213 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3214 memcpy(cmd->mac_addr, vif->addr, ETH_ALEN);
3215
aa21d0f6 3216 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
b64fe619
LB		 3217 kfree(cmd);
3218
3219 return rc;
3220}
3221
3f5610ff
LB		 3222static int mwl8k_cmd_set_new_stn_del(struct ieee80211_hw *hw,
3223 struct ieee80211_vif *vif, u8 *addr)
3224{
3225 struct mwl8k_cmd_set_new_stn *cmd;
3226 int rc;
3227
3228 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3229 if (cmd == NULL)
3230 return -ENOMEM;
3231
3232 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
3233 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3234 memcpy(cmd->mac_addr, addr, ETH_ALEN);
3235 cmd->action = cpu_to_le16(MWL8K_STA_ACTION_REMOVE);
3236
aa21d0f6 3237 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
3f5610ff
LB		 3238 kfree(cmd);
3239
3240 return rc;
3241}
3242
55489b6e
LB		 3243/*
3244 * CMD_UPDATE_STADB.
3245 */
25d81b1e
LB		 3246struct ewc_ht_info {
3247 __le16 control1;
3248 __le16 control2;
3249 __le16 control3;
ba2d3587 3250} __packed;
25d81b1e
LB		 3251
3252struct peer_capability_info {
3253 /* Peer type - AP vs. STA. */
3254 __u8 peer_type;
3255
3256 /* Basic 802.11 capabilities from assoc resp. */
3257 __le16 basic_caps;
3258
3259 /* Set if peer supports 802.11n high throughput (HT). */
3260 __u8 ht_support;
3261
3262 /* Valid if HT is supported. */
3263 __le16 ht_caps;
3264 __u8 extended_ht_caps;
3265 struct ewc_ht_info ewc_info;
3266
3267 /* Legacy rate table. Intersection of our rates and peer rates. */
3268 __u8 legacy_rates[12];
3269
3270 /* HT rate table. Intersection of our rates and peer rates. */
3271 __u8 ht_rates[16];
3272 __u8 pad[16];
3273
3274 /* If set, interoperability mode, no proprietary extensions. */
3275 __u8 interop;
3276 __u8 pad2;
3277 __u8 station_id;
3278 __le16 amsdu_enabled;
ba2d3587 3279} __packed;
25d81b1e 3280
55489b6e
LB		 3281struct mwl8k_cmd_update_stadb {
3282 struct mwl8k_cmd_pkt header;
3283
3284 /* See STADB_ACTION_TYPE */
3285 __le32 action;
3286
3287 /* Peer MAC address */
3288 __u8 peer_addr[ETH_ALEN];
3289
3290 __le32 reserved;
3291
3292 /* Peer info - valid during add/update. */
3293 struct peer_capability_info peer_info;
ba2d3587 3294} __packed;
55489b6e 3295
a680400e
LB		 3296#define MWL8K_STA_DB_MODIFY_ENTRY 1
3297#define MWL8K_STA_DB_DEL_ENTRY 2
3298
3299/* Peer Entry flags - used to define the type of the peer node */
3300#define MWL8K_PEER_TYPE_ACCESSPOINT 2
3301
3302static int mwl8k_cmd_update_stadb_add(struct ieee80211_hw *hw,
c6e96010 3303 struct ieee80211_vif *vif,
13935e2c 3304 struct ieee80211_sta *sta)
55489b6e 3305{
55489b6e 3306 struct mwl8k_cmd_update_stadb *cmd;
a680400e 3307 struct peer_capability_info *p;
8707d026 3308 u32 rates;
55489b6e
LB		 3309 int rc;
3310
3311 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3312 if (cmd == NULL)
3313 return -ENOMEM;
3314
3315 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
3316 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a680400e 3317 cmd->action = cpu_to_le32(MWL8K_STA_DB_MODIFY_ENTRY);
13935e2c 3318 memcpy(cmd->peer_addr, sta->addr, ETH_ALEN);
55489b6e 3319
a680400e
LB		 3320 p = &cmd->peer_info;
3321 p->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
3322 p->basic_caps = cpu_to_le16(vif->bss_conf.assoc_capability);
13935e2c 3323 p->ht_support = sta->ht_cap.ht_supported;
b603742f 3324 p->ht_caps = cpu_to_le16(sta->ht_cap.cap);
13935e2c
LB		 3325 p->extended_ht_caps = (sta->ht_cap.ampdu_factor & 3) |
3326 ((sta->ht_cap.ampdu_density & 7) << 2);
8707d026
LB		 3327 if (hw->conf.channel->band == IEEE80211_BAND_2GHZ)
3328 rates = sta->supp_rates[IEEE80211_BAND_2GHZ];
3329 else
3330 rates = sta->supp_rates[IEEE80211_BAND_5GHZ] << 5;
3331 legacy_rate_mask_to_array(p->legacy_rates, rates);
13935e2c 3332 memcpy(p->ht_rates, sta->ht_cap.mcs.rx_mask, 16);
a680400e
LB		 3333 p->interop = 1;
3334 p->amsdu_enabled = 0;
3335
3336 rc = mwl8k_post_cmd(hw, &cmd->header);
3337 kfree(cmd);
3338
3339 return rc ? rc : p->station_id;
3340}
3341
3342static int mwl8k_cmd_update_stadb_del(struct ieee80211_hw *hw,
3343 struct ieee80211_vif *vif, u8 *addr)
3344{
3345 struct mwl8k_cmd_update_stadb *cmd;
3346 int rc;
3347
3348 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3349 if (cmd == NULL)
3350 return -ENOMEM;
3351
3352 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
3353 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3354 cmd->action = cpu_to_le32(MWL8K_STA_DB_DEL_ENTRY);
bbfd9128 3355 memcpy(cmd->peer_addr, addr, ETH_ALEN);
55489b6e 3356
a680400e 3357 rc = mwl8k_post_cmd(hw, &cmd->header);
55489b6e
LB		 3358 kfree(cmd);
3359
3360 return rc;
3361}
3362
a66098da
LB		 3363
3364/*
3365 * Interrupt handling.
3366 */
3367static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
3368{
3369 struct ieee80211_hw *hw = dev_id;
3370 struct mwl8k_priv *priv = hw->priv;
3371 u32 status;
3372
3373 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
a66098da
LB		 3374 if (!status)
3375 return IRQ_NONE;
3376
1e9f9de3
LB		 3377 if (status & MWL8K_A2H_INT_TX_DONE) {
3378 status &= ~MWL8K_A2H_INT_TX_DONE;
3379 tasklet_schedule(&priv->poll_tx_task);
3380 }
3381
a66098da 3382 if (status & MWL8K_A2H_INT_RX_READY) {
67e2eb27
LB		 3383 status &= ~MWL8K_A2H_INT_RX_READY;
3384 tasklet_schedule(&priv->poll_rx_task);
a66098da
LB		 3385 }
3386
67e2eb27
LB		 3387 if (status)
3388 iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
3389
a66098da 3390 if (status & MWL8K_A2H_INT_OPC_DONE) {
618952a7 3391 if (priv->hostcmd_wait != NULL)
a66098da 3392 complete(priv->hostcmd_wait);
a66098da
LB		 3393 }
3394
3395 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
618952a7 3396 if (!mutex_is_locked(&priv->fw_mutex) &&
88de754a 3397 priv->radio_on && priv->pending_tx_pkts)
618952a7 3398 mwl8k_tx_start(priv);
a66098da
LB		 3399 }
3400
3401 return IRQ_HANDLED;
3402}
3403
1e9f9de3
LB		 3404static void mwl8k_tx_poll(unsigned long data)
3405{
3406 struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
3407 struct mwl8k_priv *priv = hw->priv;
3408 int limit;
3409 int i;
3410
3411 limit = 32;
3412
3413 spin_lock_bh(&priv->tx_lock);
3414
3415 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3416 limit -= mwl8k_txq_reclaim(hw, i, limit, 0);
3417
3418 if (!priv->pending_tx_pkts && priv->tx_wait != NULL) {
3419 complete(priv->tx_wait);
3420 priv->tx_wait = NULL;
3421 }
3422
3423 spin_unlock_bh(&priv->tx_lock);
3424
3425 if (limit) {
3426 writel(~MWL8K_A2H_INT_TX_DONE,
3427 priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
3428 } else {
3429 tasklet_schedule(&priv->poll_tx_task);
3430 }
3431}
3432
67e2eb27
LB		 3433static void mwl8k_rx_poll(unsigned long data)
3434{
3435 struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
3436 struct mwl8k_priv *priv = hw->priv;
3437 int limit;
3438
3439 limit = 32;
3440 limit -= rxq_process(hw, 0, limit);
3441 limit -= rxq_refill(hw, 0, limit);
3442
3443 if (limit) {
3444 writel(~MWL8K_A2H_INT_RX_READY,
3445 priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
3446 } else {
3447 tasklet_schedule(&priv->poll_rx_task);
3448 }
3449}
3450
a66098da
LB		 3451
3452/*
3453 * Core driver operations.
3454 */
3455static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
3456{
3457 struct mwl8k_priv *priv = hw->priv;
3458 int index = skb_get_queue_mapping(skb);
3459 int rc;
3460
9189c100 3461 if (!priv->radio_on) {
c96c31e4
JP		 3462 wiphy_debug(hw->wiphy,
3463 "dropped TX frame since radio disabled\n");
a66098da
LB		 3464 dev_kfree_skb(skb);
3465 return NETDEV_TX_OK;
3466 }
3467
3468 rc = mwl8k_txq_xmit(hw, index, skb);
3469
3470 return rc;
3471}
3472
a66098da
LB		 3473static int mwl8k_start(struct ieee80211_hw *hw)
3474{
a66098da
LB		 3475 struct mwl8k_priv *priv = hw->priv;
3476 int rc;
3477
a0607fd3 3478 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
a66098da
LB		 3479 IRQF_SHARED, MWL8K_NAME, hw);
3480 if (rc) {
5db55844 3481 wiphy_err(hw->wiphy, "failed to register IRQ handler\n");
2ec610cb 3482 return -EIO;
a66098da
LB		 3483 }
3484
67e2eb27 3485 /* Enable TX reclaim and RX tasklets. */
1e9f9de3 3486 tasklet_enable(&priv->poll_tx_task);
67e2eb27 3487 tasklet_enable(&priv->poll_rx_task);
2ec610cb 3488
a66098da 3489 /* Enable interrupts */
c23b5a69 3490 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da 3491
2ec610cb
LB		 3492 rc = mwl8k_fw_lock(hw);
3493 if (!rc) {
55489b6e 3494 rc = mwl8k_cmd_radio_enable(hw);
a66098da 3495
5e4cf166
LB		 3496 if (!priv->ap_fw) {
3497 if (!rc)
55489b6e 3498 rc = mwl8k_cmd_enable_sniffer(hw, 0);
a66098da 3499
5e4cf166
LB		 3500 if (!rc)
3501 rc = mwl8k_cmd_set_pre_scan(hw);
3502
3503 if (!rc)
3504 rc = mwl8k_cmd_set_post_scan(hw,
3505 "\x00\x00\x00\x00\x00\x00");
3506 }
2ec610cb
LB		 3507
3508 if (!rc)
55489b6e 3509 rc = mwl8k_cmd_set_rateadapt_mode(hw, 0);
a66098da 3510
2ec610cb 3511 if (!rc)
55489b6e 3512 rc = mwl8k_cmd_set_wmm_mode(hw, 0);
a66098da 3513
2ec610cb
LB		 3514 mwl8k_fw_unlock(hw);
3515 }
3516
3517 if (rc) {
3518 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3519 free_irq(priv->pdev->irq, hw);
1e9f9de3 3520 tasklet_disable(&priv->poll_tx_task);
67e2eb27 3521 tasklet_disable(&priv->poll_rx_task);
2ec610cb 3522 }
a66098da
LB		 3523
3524 return rc;
3525}
3526
a66098da
LB		 3527static void mwl8k_stop(struct ieee80211_hw *hw)
3528{
a66098da
LB		 3529 struct mwl8k_priv *priv = hw->priv;
3530 int i;
3531
55489b6e 3532 mwl8k_cmd_radio_disable(hw);
a66098da
LB		 3533
3534 ieee80211_stop_queues(hw);
3535
a66098da 3536 /* Disable interrupts */
a66098da 3537 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3538 free_irq(priv->pdev->irq, hw);
3539
3540 /* Stop finalize join worker */
3541 cancel_work_sync(&priv->finalize_join_worker);
3542 if (priv->beacon_skb != NULL)
3543 dev_kfree_skb(priv->beacon_skb);
3544
67e2eb27 3545 /* Stop TX reclaim and RX tasklets. */
1e9f9de3 3546 tasklet_disable(&priv->poll_tx_task);
67e2eb27 3547 tasklet_disable(&priv->poll_rx_task);
a66098da 3548
a66098da
LB		 3549 /* Return all skbs to mac80211 */
3550 for (i = 0; i < MWL8K_TX_QUEUES; i++)
efb7c49a 3551 mwl8k_txq_reclaim(hw, i, INT_MAX, 1);
a66098da
LB		 3552}
3553
0863ade8
BC		 3554static int mwl8k_reload_firmware(struct ieee80211_hw *hw, char *fw_image);
3555
a66098da 3556static int mwl8k_add_interface(struct ieee80211_hw *hw,
f5bb87cf 3557 struct ieee80211_vif *vif)
a66098da
LB		 3558{
3559 struct mwl8k_priv *priv = hw->priv;
3560 struct mwl8k_vif *mwl8k_vif;
ee0ddf18 3561 u32 macids_supported;
0863ade8
BC		 3562 int macid, rc;
3563 struct mwl8k_device_info *di;
a66098da 3564
a43c49a8
LB		 3565 /*
3566 * Reject interface creation if sniffer mode is active, as
3567 * STA operation is mutually exclusive with hardware sniffer
b64fe619 3568 * mode. (Sniffer mode is only used on STA firmware.)
a43c49a8
LB		 3569 */
3570 if (priv->sniffer_enabled) {
c96c31e4
JP		 3571 wiphy_info(hw->wiphy,
3572 "unable to create STA interface because sniffer mode is enabled\n");
a43c49a8
LB		 3573 return -EINVAL;
3574 }
3575
0863ade8 3576 di = priv->device_info;
ee0ddf18
LB		 3577 switch (vif->type) {
3578 case NL80211_IFTYPE_AP:
0863ade8
BC		 3579 if (!priv->ap_fw && di->fw_image_ap) {
3580 /* we must load the ap fw to meet this request */
3581 if (!list_empty(&priv->vif_list))
3582 return -EBUSY;
3583 rc = mwl8k_reload_firmware(hw, di->fw_image_ap);
3584 if (rc)
3585 return rc;
3586 }
ee0ddf18
LB		 3587 macids_supported = priv->ap_macids_supported;
3588 break;
3589 case NL80211_IFTYPE_STATION:
0863ade8
BC		 3590 if (priv->ap_fw && di->fw_image_sta) {
3591 /* we must load the sta fw to meet this request */
3592 if (!list_empty(&priv->vif_list))
3593 return -EBUSY;
3594 rc = mwl8k_reload_firmware(hw, di->fw_image_sta);
3595 if (rc)
3596 return rc;
3597 }
ee0ddf18
LB		 3598 macids_supported = priv->sta_macids_supported;
3599 break;
3600 default:
3601 return -EINVAL;
3602 }
3603
3604 macid = ffs(macids_supported & ~priv->macids_used);
3605 if (!macid--)
3606 return -EBUSY;
3607
f5bb87cf 3608 /* Setup driver private area. */
1ed32e4f 3609 mwl8k_vif = MWL8K_VIF(vif);
a66098da 3610 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
f5bb87cf 3611 mwl8k_vif->vif = vif;
ee0ddf18 3612 mwl8k_vif->macid = macid;
a66098da 3613 mwl8k_vif->seqno = 0;
d9a07d49
NS		 3614 memcpy(mwl8k_vif->bssid, vif->addr, ETH_ALEN);
3615 mwl8k_vif->is_hw_crypto_enabled = false;
a66098da 3616
aa21d0f6
LB		 3617 /* Set the mac address. */
3618 mwl8k_cmd_set_mac_addr(hw, vif, vif->addr);
3619
3620 if (priv->ap_fw)
3621 mwl8k_cmd_set_new_stn_add_self(hw, vif);
3622
ee0ddf18 3623 priv->macids_used |= 1 << mwl8k_vif->macid;
f5bb87cf 3624 list_add_tail(&mwl8k_vif->list, &priv->vif_list);
a66098da
LB		 3625
3626 return 0;
3627}
3628
3629static void mwl8k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 3630 struct ieee80211_vif *vif)
a66098da
LB		 3631{
3632 struct mwl8k_priv *priv = hw->priv;
f5bb87cf 3633 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
a66098da 3634
b64fe619
LB		 3635 if (priv->ap_fw)
3636 mwl8k_cmd_set_new_stn_del(hw, vif, vif->addr);
3637
aa21d0f6 3638 mwl8k_cmd_set_mac_addr(hw, vif, "\x00\x00\x00\x00\x00\x00");
32060e1b 3639
ee0ddf18 3640 priv->macids_used &= ~(1 << mwl8k_vif->macid);
f5bb87cf 3641 list_del(&mwl8k_vif->list);
a66098da
LB		 3642}
3643
ee03a932 3644static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
a66098da 3645{
a66098da
LB		 3646 struct ieee80211_conf *conf = &hw->conf;
3647 struct mwl8k_priv *priv = hw->priv;
ee03a932 3648 int rc;
a66098da 3649
7595d67a 3650 if (conf->flags & IEEE80211_CONF_IDLE) {
55489b6e 3651 mwl8k_cmd_radio_disable(hw);
ee03a932 3652 return 0;
7595d67a
LB		 3653 }
3654
ee03a932
LB		 3655 rc = mwl8k_fw_lock(hw);
3656 if (rc)
3657 return rc;
a66098da 3658
55489b6e 3659 rc = mwl8k_cmd_radio_enable(hw);
ee03a932
LB		 3660 if (rc)
3661 goto out;
a66098da 3662
610677d2 3663 rc = mwl8k_cmd_set_rf_channel(hw, conf);
ee03a932
LB		 3664 if (rc)
3665 goto out;
3666
a66098da
LB		 3667 if (conf->power_level > 18)
3668 conf->power_level = 18;
a66098da 3669
08b06347 3670 if (priv->ap_fw) {
41fdf097
NS		 3671 rc = mwl8k_cmd_tx_power(hw, conf, conf->power_level);
3672 if (rc)
3673 goto out;
3674
08b06347
LB		 3675 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_RX, 0x7);
3676 if (!rc)
3677 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_TX, 0x7);
3678 } else {
41fdf097
NS		 3679 rc = mwl8k_cmd_rf_tx_power(hw, conf->power_level);
3680 if (rc)
3681 goto out;
08b06347
LB		 3682 rc = mwl8k_cmd_mimo_config(hw, 0x7, 0x7);
3683 }
a66098da 3684
ee03a932
LB		 3685out:
3686 mwl8k_fw_unlock(hw);
a66098da 3687
ee03a932 3688 return rc;
a66098da
LB		 3689}
3690
b64fe619
LB		 3691static void
3692mwl8k_bss_info_changed_sta(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3693 struct ieee80211_bss_conf *info, u32 changed)
a66098da 3694{
a66098da 3695 struct mwl8k_priv *priv = hw->priv;
c3cbbe8a 3696 u32 ap_legacy_rates;
13935e2c 3697 u8 ap_mcs_rates[16];
3a980d0a
LB		 3698 int rc;
3699
c3cbbe8a 3700 if (mwl8k_fw_lock(hw))
3a980d0a 3701 return;
a66098da 3702
c3cbbe8a
LB		 3703 /*
3704 * No need to capture a beacon if we're no longer associated.
3705 */
3706 if ((changed & BSS_CHANGED_ASSOC) && !vif->bss_conf.assoc)
3707 priv->capture_beacon = false;
3a980d0a 3708
c3cbbe8a 3709 /*
13935e2c 3710 * Get the AP's legacy and MCS rates.
c3cbbe8a 3711 */
7dc6a7a7 3712 if (vif->bss_conf.assoc) {
c6e96010 3713 struct ieee80211_sta *ap;
c97470dd 3714
c6e96010 3715 rcu_read_lock();
c6e96010 3716
c3cbbe8a
LB		 3717 ap = ieee80211_find_sta(vif, vif->bss_conf.bssid);
3718 if (ap == NULL) {
3719 rcu_read_unlock();
c6e96010 3720 goto out;
c3cbbe8a
LB		 3721 }
3722
8707d026
LB		 3723 if (hw->conf.channel->band == IEEE80211_BAND_2GHZ) {
3724 ap_legacy_rates = ap->supp_rates[IEEE80211_BAND_2GHZ];
3725 } else {
3726 ap_legacy_rates =
3727 ap->supp_rates[IEEE80211_BAND_5GHZ] << 5;
3728 }
13935e2c 3729 memcpy(ap_mcs_rates, ap->ht_cap.mcs.rx_mask, 16);
c3cbbe8a
LB		 3730
3731 rcu_read_unlock();
3732 }
c6e96010 3733
c3cbbe8a 3734 if ((changed & BSS_CHANGED_ASSOC) && vif->bss_conf.assoc) {
13935e2c 3735 rc = mwl8k_cmd_set_rate(hw, vif, ap_legacy_rates, ap_mcs_rates);
3a980d0a
LB		 3736 if (rc)
3737 goto out;
a66098da 3738
b71ed2c6 3739 rc = mwl8k_cmd_use_fixed_rate_sta(hw);
3a980d0a
LB		 3740 if (rc)
3741 goto out;
c3cbbe8a 3742 }
a66098da 3743
c3cbbe8a 3744 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
7dc6a7a7
LB		 3745 rc = mwl8k_set_radio_preamble(hw,
3746 vif->bss_conf.use_short_preamble);
3a980d0a
LB		 3747 if (rc)
3748 goto out;
c3cbbe8a 3749 }
a66098da 3750
c3cbbe8a 3751 if (changed & BSS_CHANGED_ERP_SLOT) {
7dc6a7a7 3752 rc = mwl8k_cmd_set_slot(hw, vif->bss_conf.use_short_slot);
3a980d0a
LB		 3753 if (rc)
3754 goto out;
c3cbbe8a 3755 }
a66098da 3756
c97470dd
LB		 3757 if (vif->bss_conf.assoc &&
3758 (changed & (BSS_CHANGED_ASSOC | BSS_CHANGED_ERP_CTS_PROT |
3759 BSS_CHANGED_HT))) {
c3cbbe8a 3760 rc = mwl8k_cmd_set_aid(hw, vif, ap_legacy_rates);
3a980d0a
LB		 3761 if (rc)
3762 goto out;
c3cbbe8a 3763 }
a66098da 3764
c3cbbe8a
LB		 3765 if (vif->bss_conf.assoc &&
3766 (changed & (BSS_CHANGED_ASSOC | BSS_CHANGED_BEACON_INT))) {
a66098da
LB		 3767 /*
3768 * Finalize the join. Tell rx handler to process
3769 * next beacon from our BSSID.
3770 */
0a11dfc3 3771 memcpy(priv->capture_bssid, vif->bss_conf.bssid, ETH_ALEN);
a66098da 3772 priv->capture_beacon = true;
a66098da
LB		 3773 }
3774
3a980d0a
LB		 3775out:
3776 mwl8k_fw_unlock(hw);
a66098da
LB		 3777}
3778
b64fe619
LB		 3779static void
3780mwl8k_bss_info_changed_ap(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3781 struct ieee80211_bss_conf *info, u32 changed)
3782{
3783 int rc;
3784
3785 if (mwl8k_fw_lock(hw))
3786 return;
3787
3788 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
3789 rc = mwl8k_set_radio_preamble(hw,
3790 vif->bss_conf.use_short_preamble);
3791 if (rc)
3792 goto out;
3793 }
3794
3795 if (changed & BSS_CHANGED_BASIC_RATES) {
3796 int idx;
3797 int rate;
3798
3799 /*
3800 * Use lowest supported basic rate for multicasts
3801 * and management frames (such as probe responses --
3802 * beacons will always go out at 1 Mb/s).
3803 */
3804 idx = ffs(vif->bss_conf.basic_rates);
8707d026
LB		 3805 if (idx)
3806 idx--;
3807
3808 if (hw->conf.channel->band == IEEE80211_BAND_2GHZ)
3809 rate = mwl8k_rates_24[idx].hw_value;
3810 else
3811 rate = mwl8k_rates_50[idx].hw_value;
b64fe619
LB		 3812
3813 mwl8k_cmd_use_fixed_rate_ap(hw, rate, rate);
3814 }
3815
3816 if (changed & (BSS_CHANGED_BEACON_INT | BSS_CHANGED_BEACON)) {
3817 struct sk_buff *skb;
3818
3819 skb = ieee80211_beacon_get(hw, vif);
3820 if (skb != NULL) {
aa21d0f6 3821 mwl8k_cmd_set_beacon(hw, vif, skb->data, skb->len);
b64fe619
LB		 3822 kfree_skb(skb);
3823 }
3824 }
3825
3826 if (changed & BSS_CHANGED_BEACON_ENABLED)
aa21d0f6 3827 mwl8k_cmd_bss_start(hw, vif, info->enable_beacon);
b64fe619
LB		 3828
3829out:
3830 mwl8k_fw_unlock(hw);
3831}
3832
3833static void
3834mwl8k_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3835 struct ieee80211_bss_conf *info, u32 changed)
3836{
3837 struct mwl8k_priv *priv = hw->priv;
3838
3839 if (!priv->ap_fw)
3840 mwl8k_bss_info_changed_sta(hw, vif, info, changed);
3841 else
3842 mwl8k_bss_info_changed_ap(hw, vif, info, changed);
3843}
3844
e81cd2d6 3845static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
22bedad3 3846 struct netdev_hw_addr_list *mc_list)
e81cd2d6
LB		 3847{
3848 struct mwl8k_cmd_pkt *cmd;
3849
447ced07
LB		 3850 /*
3851 * Synthesize and return a command packet that programs the
3852 * hardware multicast address filter. At this point we don't
3853 * know whether FIF_ALLMULTI is being requested, but if it is,
3854 * we'll end up throwing this packet away and creating a new
3855 * one in mwl8k_configure_filter().
3856 */
22bedad3 3857 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_list);
e81cd2d6
LB		 3858
3859 return (unsigned long)cmd;
3860}
3861
a43c49a8
LB		 3862static int
3863mwl8k_configure_filter_sniffer(struct ieee80211_hw *hw,
3864 unsigned int changed_flags,
3865 unsigned int *total_flags)
3866{
3867 struct mwl8k_priv *priv = hw->priv;
3868
3869 /*
3870 * Hardware sniffer mode is mutually exclusive with STA
3871 * operation, so refuse to enable sniffer mode if a STA
3872 * interface is active.
3873 */
f5bb87cf 3874 if (!list_empty(&priv->vif_list)) {
a43c49a8 3875 if (net_ratelimit())
c96c31e4
JP		 3876 wiphy_info(hw->wiphy,
3877 "not enabling sniffer mode because STA interface is active\n");
a43c49a8
LB		 3878 return 0;
3879 }
3880
3881 if (!priv->sniffer_enabled) {
55489b6e 3882 if (mwl8k_cmd_enable_sniffer(hw, 1))
a43c49a8
LB		 3883 return 0;
3884 priv->sniffer_enabled = true;
3885 }
3886
3887 *total_flags &= FIF_PROMISC_IN_BSS | FIF_ALLMULTI |
3888 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL |
3889 FIF_OTHER_BSS;
3890
3891 return 1;
3892}
3893
f5bb87cf
LB		 3894static struct mwl8k_vif *mwl8k_first_vif(struct mwl8k_priv *priv)
3895{
3896 if (!list_empty(&priv->vif_list))
3897 return list_entry(priv->vif_list.next, struct mwl8k_vif, list);
3898
3899 return NULL;
3900}
3901
e6935ea1
LB		 3902static void mwl8k_configure_filter(struct ieee80211_hw *hw,
3903 unsigned int changed_flags,
3904 unsigned int *total_flags,
3905 u64 multicast)
3906{
3907 struct mwl8k_priv *priv = hw->priv;
a43c49a8
LB		 3908 struct mwl8k_cmd_pkt *cmd = (void *)(unsigned long)multicast;
3909
c0adae2c
LB		 3910 /*
3911 * AP firmware doesn't allow fine-grained control over
3912 * the receive filter.
3913 */
3914 if (priv->ap_fw) {
3915 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
3916 kfree(cmd);
3917 return;
3918 }
3919
a43c49a8
LB		 3920 /*
3921 * Enable hardware sniffer mode if FIF_CONTROL or
3922 * FIF_OTHER_BSS is requested.
3923 */
3924 if (*total_flags & (FIF_CONTROL | FIF_OTHER_BSS) &&
3925 mwl8k_configure_filter_sniffer(hw, changed_flags, total_flags)) {
3926 kfree(cmd);
3927 return;
3928 }
a66098da 3929
e6935ea1 3930 /* Clear unsupported feature flags */
447ced07 3931 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
a66098da 3932
90852f7a
LB		 3933 if (mwl8k_fw_lock(hw)) {
3934 kfree(cmd);
e6935ea1 3935 return;
90852f7a 3936 }
a66098da 3937
a43c49a8 3938 if (priv->sniffer_enabled) {
55489b6e 3939 mwl8k_cmd_enable_sniffer(hw, 0);
a43c49a8
LB		 3940 priv->sniffer_enabled = false;
3941 }
3942
e6935ea1 3943 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
77165d88
LB		 3944 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
3945 /*
3946 * Disable the BSS filter.
3947 */
e6935ea1 3948 mwl8k_cmd_set_pre_scan(hw);
77165d88 3949 } else {
f5bb87cf 3950 struct mwl8k_vif *mwl8k_vif;
0a11dfc3 3951 const u8 *bssid;
a94cc97e 3952
77165d88
LB		 3953 /*
3954 * Enable the BSS filter.
3955 *
3956 * If there is an active STA interface, use that
3957 * interface's BSSID, otherwise use a dummy one
3958 * (where the OUI part needs to be nonzero for
3959 * the BSSID to be accepted by POST_SCAN).
3960 */
f5bb87cf
LB		 3961 mwl8k_vif = mwl8k_first_vif(priv);
3962 if (mwl8k_vif != NULL)
3963 bssid = mwl8k_vif->vif->bss_conf.bssid;
3964 else
3965 bssid = "\x01\x00\x00\x00\x00\x00";
a94cc97e 3966
e6935ea1 3967 mwl8k_cmd_set_post_scan(hw, bssid);
a66098da
LB		 3968 }
3969 }
3970
447ced07
LB		 3971 /*
3972 * If FIF_ALLMULTI is being requested, throw away the command
3973 * packet that ->prepare_multicast() built and replace it with
3974 * a command packet that enables reception of all multicast
3975 * packets.
3976 */
3977 if (*total_flags & FIF_ALLMULTI) {
3978 kfree(cmd);
22bedad3 3979 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, NULL);
447ced07
LB		 3980 }
3981
3982 if (cmd != NULL) {
3983 mwl8k_post_cmd(hw, cmd);
3984 kfree(cmd);
e6935ea1 3985 }
a66098da 3986
e6935ea1 3987 mwl8k_fw_unlock(hw);
a66098da
LB		 3988}
3989
a66098da
LB		 3990static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
3991{
c2c2b12a 3992 return mwl8k_cmd_set_rts_threshold(hw, value);
a66098da
LB		 3993}
3994
4a6967b8
JB		 3995static int mwl8k_sta_remove(struct ieee80211_hw *hw,
3996 struct ieee80211_vif *vif,
3997 struct ieee80211_sta *sta)
3f5610ff
LB		 3998{
3999 struct mwl8k_priv *priv = hw->priv;
4000
4a6967b8
JB		 4001 if (priv->ap_fw)
4002 return mwl8k_cmd_set_new_stn_del(hw, vif, sta->addr);
4003 else
4004 return mwl8k_cmd_update_stadb_del(hw, vif, sta->addr);
bbfd9128
LB		 4005}
4006
4a6967b8
JB		 4007static int mwl8k_sta_add(struct ieee80211_hw *hw,
4008 struct ieee80211_vif *vif,
4009 struct ieee80211_sta *sta)
bbfd9128
LB		 4010{
4011 struct mwl8k_priv *priv = hw->priv;
4a6967b8 4012 int ret;
bbfd9128 4013
4a6967b8
JB		 4014 if (!priv->ap_fw) {
4015 ret = mwl8k_cmd_update_stadb_add(hw, vif, sta);
4016 if (ret >= 0) {
4017 MWL8K_STA(sta)->peer_id = ret;
4018 return 0;
4019 }
bbfd9128 4020
d9a07d49
NS		 4021 } else {
4022 ret = mwl8k_cmd_set_new_stn_add(hw, vif, sta);
4a6967b8 4023 return ret;
bbfd9128 4024 }
4a6967b8 4025
d9a07d49
NS		 4026 for (i = 0; i < NUM_WEP_KEYS; i++) {
4027 key = IEEE80211_KEY_CONF(mwl8k_vif->wep_key_conf[i].key);
4028 if (mwl8k_vif->wep_key_conf[i].enabled)
4029 mwl8k_set_key(hw, SET_KEY, vif, sta, key);
4030 }
4a6967b8 4031 return mwl8k_cmd_set_new_stn_add(hw, vif, sta);
bbfd9128
LB		 4032}
4033
a66098da
LB		 4034static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue,
4035 const struct ieee80211_tx_queue_params *params)
4036{
3e4f542c 4037 struct mwl8k_priv *priv = hw->priv;
a66098da 4038 int rc;
a66098da 4039
3e4f542c
LB		 4040 rc = mwl8k_fw_lock(hw);
4041 if (!rc) {
0863ade8
BC		 4042 BUG_ON(queue > MWL8K_TX_QUEUES - 1);
4043 memcpy(&priv->wmm_params[queue], params, sizeof(*params));
4044
3e4f542c 4045 if (!priv->wmm_enabled)
55489b6e 4046 rc = mwl8k_cmd_set_wmm_mode(hw, 1);
a66098da 4047
3e4f542c 4048 if (!rc)
55489b6e
LB		 4049 rc = mwl8k_cmd_set_edca_params(hw, queue,
4050 params->cw_min,
4051 params->cw_max,
4052 params->aifs,
4053 params->txop);
3e4f542c
LB		 4054
4055 mwl8k_fw_unlock(hw);
a66098da 4056 }
3e4f542c 4057
a66098da
LB		 4058 return rc;
4059}
4060
a66098da
LB		 4061static int mwl8k_get_stats(struct ieee80211_hw *hw,
4062 struct ieee80211_low_level_stats *stats)
4063{
55489b6e 4064 return mwl8k_cmd_get_stat(hw, stats);
a66098da
LB		 4065}
4066
0d462bbb
JL		 4067static int mwl8k_get_survey(struct ieee80211_hw *hw, int idx,
4068 struct survey_info *survey)
4069{
4070 struct mwl8k_priv *priv = hw->priv;
4071 struct ieee80211_conf *conf = &hw->conf;
4072
4073 if (idx != 0)
4074 return -ENOENT;
4075
4076 survey->channel = conf->channel;
4077 survey->filled = SURVEY_INFO_NOISE_DBM;
4078 survey->noise = priv->noise;
4079
4080 return 0;
4081}
4082
a2292d83
LB		 4083static int
4084mwl8k_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4085 enum ieee80211_ampdu_mlme_action action,
4086 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
4087{
4088 switch (action) {
4089 case IEEE80211_AMPDU_RX_START:
4090 case IEEE80211_AMPDU_RX_STOP:
4091 if (!(hw->flags & IEEE80211_HW_AMPDU_AGGREGATION))
4092 return -ENOTSUPP;
4093 return 0;
4094 default:
4095 return -ENOTSUPP;
4096 }
4097}
4098
a66098da
LB		 4099static const struct ieee80211_ops mwl8k_ops = {
4100 .tx = mwl8k_tx,
4101 .start = mwl8k_start,
4102 .stop = mwl8k_stop,
4103 .add_interface = mwl8k_add_interface,
4104 .remove_interface = mwl8k_remove_interface,
4105 .config = mwl8k_config,
a66098da 4106 .bss_info_changed = mwl8k_bss_info_changed,
3ac64bee 4107 .prepare_multicast = mwl8k_prepare_multicast,
a66098da
LB		 4108 .configure_filter = mwl8k_configure_filter,
4109 .set_rts_threshold = mwl8k_set_rts_threshold,
4a6967b8
JB		 4110 .sta_add = mwl8k_sta_add,
4111 .sta_remove = mwl8k_sta_remove,
a66098da 4112 .conf_tx = mwl8k_conf_tx,
a66098da 4113 .get_stats = mwl8k_get_stats,
0d462bbb 4114 .get_survey = mwl8k_get_survey,
a2292d83 4115 .ampdu_action = mwl8k_ampdu_action,
a66098da
LB		 4116};
4117
a66098da
LB		 4118static void mwl8k_finalize_join_worker(struct work_struct *work)
4119{
4120 struct mwl8k_priv *priv =
4121 container_of(work, struct mwl8k_priv, finalize_join_worker);
4122 struct sk_buff *skb = priv->beacon_skb;
56007a02
JB		 4123 struct ieee80211_mgmt *mgmt = (void *)skb->data;
4124 int len = skb->len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
4125 const u8 *tim = cfg80211_find_ie(WLAN_EID_TIM,
4126 mgmt->u.beacon.variable, len);
4127 int dtim_period = 1;
4128
4129 if (tim && tim[1] >= 2)
4130 dtim_period = tim[3];
a66098da 4131
56007a02 4132 mwl8k_cmd_finalize_join(priv->hw, skb->data, skb->len, dtim_period);
a66098da 4133
f5bb87cf 4134 dev_kfree_skb(skb);
a66098da
LB		 4135 priv->beacon_skb = NULL;
4136}
4137
bcb628d5 4138enum {
9e1b17ea
LB		 4139 MWL8363 = 0,
4140 MWL8687,
bcb628d5 4141 MWL8366,
6f6d1e9a
LB		 4142};
4143
952a0e96
BC		 4144#define MWL8K_8366_AP_FW_API 1
4145#define _MWL8K_8366_AP_FW(api) "mwl8k/fmimage_8366_ap-" #api ".fw"
4146#define MWL8K_8366_AP_FW(api) _MWL8K_8366_AP_FW(api)
4147
bcb628d5 4148static struct mwl8k_device_info mwl8k_info_tbl[] __devinitdata = {
9e1b17ea
LB		 4149 [MWL8363] = {
4150 .part_name = "88w8363",
4151 .helper_image = "mwl8k/helper_8363.fw",
0863ade8 4152 .fw_image_sta = "mwl8k/fmimage_8363.fw",
9e1b17ea 4153 },
49eb691c 4154 [MWL8687] = {
bcb628d5
JL		 4155 .part_name = "88w8687",
4156 .helper_image = "mwl8k/helper_8687.fw",
0863ade8 4157 .fw_image_sta = "mwl8k/fmimage_8687.fw",
bcb628d5 4158 },
49eb691c 4159 [MWL8366] = {
bcb628d5
JL		 4160 .part_name = "88w8366",
4161 .helper_image = "mwl8k/helper_8366.fw",
0863ade8 4162 .fw_image_sta = "mwl8k/fmimage_8366.fw",
952a0e96
BC		 4163 .fw_image_ap = MWL8K_8366_AP_FW(MWL8K_8366_AP_FW_API),
4164 .fw_api_ap = MWL8K_8366_AP_FW_API,
89a91f4f 4165 .ap_rxd_ops = &rxd_8366_ap_ops,
bcb628d5 4166 },
45a390dd
LB		 4167};
4168
c92d4ede
LB		 4169MODULE_FIRMWARE("mwl8k/helper_8363.fw");
4170MODULE_FIRMWARE("mwl8k/fmimage_8363.fw");
4171MODULE_FIRMWARE("mwl8k/helper_8687.fw");
4172MODULE_FIRMWARE("mwl8k/fmimage_8687.fw");
4173MODULE_FIRMWARE("mwl8k/helper_8366.fw");
4174MODULE_FIRMWARE("mwl8k/fmimage_8366.fw");
952a0e96 4175MODULE_FIRMWARE(MWL8K_8366_AP_FW(MWL8K_8366_AP_FW_API));
c92d4ede 4176
45a390dd 4177static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = {
e5868ba1 4178 { PCI_VDEVICE(MARVELL, 0x2a0a), .driver_data = MWL8363, },
9e1b17ea
LB		 4179 { PCI_VDEVICE(MARVELL, 0x2a0c), .driver_data = MWL8363, },
4180 { PCI_VDEVICE(MARVELL, 0x2a24), .driver_data = MWL8363, },
bcb628d5
JL		 4181 { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = MWL8687, },
4182 { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = MWL8687, },
4183 { PCI_VDEVICE(MARVELL, 0x2a40), .driver_data = MWL8366, },
ca66527c 4184 { PCI_VDEVICE(MARVELL, 0x2a43), .driver_data = MWL8366, },
bcb628d5 4185 { },
45a390dd
LB		 4186};
4187MODULE_DEVICE_TABLE(pci, mwl8k_pci_id_table);
4188
99020471
BC		 4189static int mwl8k_request_alt_fw(struct mwl8k_priv *priv)
4190{
4191 int rc;
4192 printk(KERN_ERR "%s: Error requesting preferred fw %s.\n"
4193 "Trying alternative firmware %s\n", pci_name(priv->pdev),
4194 priv->fw_pref, priv->fw_alt);
4195 rc = mwl8k_request_fw(priv, priv->fw_alt, &priv->fw_ucode, true);
4196 if (rc) {
4197 printk(KERN_ERR "%s: Error requesting alt fw %s\n",
4198 pci_name(priv->pdev), priv->fw_alt);
4199 return rc;
4200 }
4201 return 0;
4202}
4203
4204static int mwl8k_firmware_load_success(struct mwl8k_priv *priv);
4205static void mwl8k_fw_state_machine(const struct firmware *fw, void *context)
4206{
4207 struct mwl8k_priv *priv = context;
4208 struct mwl8k_device_info *di = priv->device_info;
4209 int rc;
4210
4211 switch (priv->fw_state) {
4212 case FW_STATE_INIT:
4213 if (!fw) {
4214 printk(KERN_ERR "%s: Error requesting helper fw %s\n",
4215 pci_name(priv->pdev), di->helper_image);
4216 goto fail;
4217 }
4218 priv->fw_helper = fw;
4219 rc = mwl8k_request_fw(priv, priv->fw_pref, &priv->fw_ucode,
4220 true);
4221 if (rc && priv->fw_alt) {
4222 rc = mwl8k_request_alt_fw(priv);
4223 if (rc)
4224 goto fail;
4225 priv->fw_state = FW_STATE_LOADING_ALT;
4226 } else if (rc)
4227 goto fail;
4228 else
4229 priv->fw_state = FW_STATE_LOADING_PREF;
4230 break;
4231
4232 case FW_STATE_LOADING_PREF:
4233 if (!fw) {
4234 if (priv->fw_alt) {
4235 rc = mwl8k_request_alt_fw(priv);
4236 if (rc)
4237 goto fail;
4238 priv->fw_state = FW_STATE_LOADING_ALT;
4239 } else
4240 goto fail;
4241 } else {
4242 priv->fw_ucode = fw;
4243 rc = mwl8k_firmware_load_success(priv);
4244 if (rc)
4245 goto fail;
4246 else
4247 complete(&priv->firmware_loading_complete);
4248 }
4249 break;
4250
4251 case FW_STATE_LOADING_ALT:
4252 if (!fw) {
4253 printk(KERN_ERR "%s: Error requesting alt fw %s\n",
4254 pci_name(priv->pdev), di->helper_image);
4255 goto fail;
4256 }
4257 priv->fw_ucode = fw;
4258 rc = mwl8k_firmware_load_success(priv);
4259 if (rc)
4260 goto fail;
4261 else
4262 complete(&priv->firmware_loading_complete);
4263 break;
4264
4265 default:
4266 printk(KERN_ERR "%s: Unexpected firmware loading state: %d\n",
4267 MWL8K_NAME, priv->fw_state);
4268 BUG_ON(1);
4269 }
4270
4271 return;
4272
4273fail:
4274 priv->fw_state = FW_STATE_ERROR;
4275 complete(&priv->firmware_loading_complete);
4276 device_release_driver(&priv->pdev->dev);
4277 mwl8k_release_firmware(priv);
4278}
4279
4280static int mwl8k_init_firmware(struct ieee80211_hw *hw, char *fw_image,
4281 bool nowait)
a66098da 4282{
3cc7772c 4283 struct mwl8k_priv *priv = hw->priv;
a66098da 4284 int rc;
be695fc4
LB		 4285
4286 /* Reset firmware and hardware */
4287 mwl8k_hw_reset(priv);
4288
4289 /* Ask userland hotplug daemon for the device firmware */
99020471 4290 rc = mwl8k_request_firmware(priv, fw_image, nowait);
be695fc4 4291 if (rc) {
5db55844 4292 wiphy_err(hw->wiphy, "Firmware files not found\n");
3cc7772c 4293 return rc;
be695fc4
LB		 4294 }
4295
99020471
BC		 4296 if (nowait)
4297 return rc;
4298
be695fc4
LB		 4299 /* Load firmware into hardware */
4300 rc = mwl8k_load_firmware(hw);
3cc7772c 4301 if (rc)
5db55844 4302 wiphy_err(hw->wiphy, "Cannot start firmware\n");
be695fc4
LB		 4303
4304 /* Reclaim memory once firmware is successfully loaded */
4305 mwl8k_release_firmware(priv);
4306
3cc7772c
BC		 4307 return rc;
4308}
4309
4310/* initialize hw after successfully loading a firmware image */
4311static int mwl8k_probe_hw(struct ieee80211_hw *hw)
4312{
4313 struct mwl8k_priv *priv = hw->priv;
4314 int rc = 0;
4315 int i;
be695fc4 4316
91942230 4317 if (priv->ap_fw) {
89a91f4f 4318 priv->rxd_ops = priv->device_info->ap_rxd_ops;
91942230 4319 if (priv->rxd_ops == NULL) {
c96c31e4
JP		 4320 wiphy_err(hw->wiphy,
4321 "Driver does not have AP firmware image support for this hardware\n");
91942230
LB		 4322 goto err_stop_firmware;
4323 }
4324 } else {
89a91f4f 4325 priv->rxd_ops = &rxd_sta_ops;
91942230 4326 }
be695fc4
LB		 4327
4328 priv->sniffer_enabled = false;
4329 priv->wmm_enabled = false;
4330 priv->pending_tx_pkts = 0;
4331
a66098da
LB		 4332 rc = mwl8k_rxq_init(hw, 0);
4333 if (rc)
3cc7772c 4334 goto err_stop_firmware;
a66098da
LB		 4335 rxq_refill(hw, 0, INT_MAX);
4336
a66098da
LB		 4337 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
4338 rc = mwl8k_txq_init(hw, i);
4339 if (rc)
4340 goto err_free_queues;
4341 }
4342
4343 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
c23b5a69 4344 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
67e2eb27 4345 iowrite32(MWL8K_A2H_INT_TX_DONE | MWL8K_A2H_INT_RX_READY,
1e9f9de3 4346 priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
a66098da
LB		 4347 iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
4348
a0607fd3 4349 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
a66098da
LB		 4350 IRQF_SHARED, MWL8K_NAME, hw);
4351 if (rc) {
5db55844 4352 wiphy_err(hw->wiphy, "failed to register IRQ handler\n");
a66098da
LB		 4353 goto err_free_queues;
4354 }
4355
a66098da
LB		 4356 /*
4357 * Temporarily enable interrupts. Initial firmware host
c2c2b12a 4358 * commands use interrupts and avoid polling. Disable
a66098da
LB		 4359 * interrupts when done.
4360 */
c23b5a69 4361 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 4362
4363 /* Get config data, mac addrs etc */
42fba21d
LB		 4364 if (priv->ap_fw) {
4365 rc = mwl8k_cmd_get_hw_spec_ap(hw);
4366 if (!rc)
4367 rc = mwl8k_cmd_set_hw_spec(hw);
4368 } else {
4369 rc = mwl8k_cmd_get_hw_spec_sta(hw);
4370 }
a66098da 4371 if (rc) {
5db55844 4372 wiphy_err(hw->wiphy, "Cannot initialise firmware\n");
be695fc4 4373 goto err_free_irq;
a66098da
LB		 4374 }
4375
4376 /* Turn radio off */
55489b6e 4377 rc = mwl8k_cmd_radio_disable(hw);
a66098da 4378 if (rc) {
5db55844 4379 wiphy_err(hw->wiphy, "Cannot disable\n");
be695fc4 4380 goto err_free_irq;
a66098da
LB		 4381 }
4382
32060e1b 4383 /* Clear MAC address */
aa21d0f6 4384 rc = mwl8k_cmd_set_mac_addr(hw, NULL, "\x00\x00\x00\x00\x00\x00");
32060e1b 4385 if (rc) {
5db55844 4386 wiphy_err(hw->wiphy, "Cannot clear MAC address\n");
be695fc4 4387 goto err_free_irq;
32060e1b
LB		 4388 }
4389
a66098da 4390 /* Disable interrupts */
a66098da 4391 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 4392 free_irq(priv->pdev->irq, hw);
4393
c96c31e4
JP		 4394 wiphy_info(hw->wiphy, "%s v%d, %pm, %s firmware %u.%u.%u.%u\n",
4395 priv->device_info->part_name,
4396 priv->hw_rev, hw->wiphy->perm_addr,
4397 priv->ap_fw ? "AP" : "STA",
4398 (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff,
4399 (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff);
a66098da
LB		 4400
4401 return 0;
4402
a66098da 4403err_free_irq:
a66098da 4404 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 4405 free_irq(priv->pdev->irq, hw);
4406
4407err_free_queues:
4408 for (i = 0; i < MWL8K_TX_QUEUES; i++)
4409 mwl8k_txq_deinit(hw, i);
4410 mwl8k_rxq_deinit(hw, 0);
4411
3cc7772c
BC		 4412err_stop_firmware:
4413 mwl8k_hw_reset(priv);
4414
4415 return rc;
4416}
4417
4418/*
4419 * invoke mwl8k_reload_firmware to change the firmware image after the device
4420 * has already been registered
4421 */
4422static int mwl8k_reload_firmware(struct ieee80211_hw *hw, char *fw_image)
4423{
4424 int i, rc = 0;
4425 struct mwl8k_priv *priv = hw->priv;
4426
4427 mwl8k_stop(hw);
4428 mwl8k_rxq_deinit(hw, 0);
4429
4430 for (i = 0; i < MWL8K_TX_QUEUES; i++)
4431 mwl8k_txq_deinit(hw, i);
4432
99020471 4433 rc = mwl8k_init_firmware(hw, fw_image, false);
3cc7772c
BC		 4434 if (rc)
4435 goto fail;
4436
4437 rc = mwl8k_probe_hw(hw);
4438 if (rc)
4439 goto fail;
4440
4441 rc = mwl8k_start(hw);
4442 if (rc)
4443 goto fail;
4444
4445 rc = mwl8k_config(hw, ~0);
4446 if (rc)
4447 goto fail;
4448
4449 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
4450 rc = mwl8k_conf_tx(hw, i, &priv->wmm_params[i]);
4451 if (rc)
4452 goto fail;
4453 }
4454
4455 return rc;
4456
4457fail:
4458 printk(KERN_WARNING "mwl8k: Failed to reload firmware image.\n");
4459 return rc;
4460}
4461
4462static int mwl8k_firmware_load_success(struct mwl8k_priv *priv)
4463{
4464 struct ieee80211_hw *hw = priv->hw;
4465 int i, rc;
4466
99020471
BC		 4467 rc = mwl8k_load_firmware(hw);
4468 mwl8k_release_firmware(priv);
4469 if (rc) {
4470 wiphy_err(hw->wiphy, "Cannot start firmware\n");
4471 return rc;
4472 }
4473
3cc7772c
BC		 4474 /*
4475 * Extra headroom is the size of the required DMA header
4476 * minus the size of the smallest 802.11 frame (CTS frame).
4477 */
4478 hw->extra_tx_headroom =
4479 sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
4480
4481 hw->channel_change_time = 10;
4482
4483 hw->queues = MWL8K_TX_QUEUES;
4484
4485 /* Set rssi values to dBm */
4486 hw->flags |= IEEE80211_HW_SIGNAL_DBM;
4487 hw->vif_data_size = sizeof(struct mwl8k_vif);
4488 hw->sta_data_size = sizeof(struct mwl8k_sta);
4489
4490 priv->macids_used = 0;
4491 INIT_LIST_HEAD(&priv->vif_list);
4492
4493 /* Set default radio state and preamble */
4494 priv->radio_on = 0;
4495 priv->radio_short_preamble = 0;
4496
4497 /* Finalize join worker */
4498 INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
4499
4500 /* TX reclaim and RX tasklets. */
4501 tasklet_init(&priv->poll_tx_task, mwl8k_tx_poll, (unsigned long)hw);
4502 tasklet_disable(&priv->poll_tx_task);
4503 tasklet_init(&priv->poll_rx_task, mwl8k_rx_poll, (unsigned long)hw);
4504 tasklet_disable(&priv->poll_rx_task);
4505
4506 /* Power management cookie */
4507 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
4508 if (priv->cookie == NULL)
4509 return -ENOMEM;
4510
4511 mutex_init(&priv->fw_mutex);
4512 priv->fw_mutex_owner = NULL;
4513 priv->fw_mutex_depth = 0;
4514 priv->hostcmd_wait = NULL;
4515
4516 spin_lock_init(&priv->tx_lock);
4517
4518 priv->tx_wait = NULL;
4519
4520 rc = mwl8k_probe_hw(hw);
4521 if (rc)
4522 goto err_free_cookie;
4523
4524 hw->wiphy->interface_modes = 0;
4525 if (priv->ap_macids_supported || priv->device_info->fw_image_ap)
4526 hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_AP);
4527 if (priv->sta_macids_supported || priv->device_info->fw_image_sta)
4528 hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_STATION);
4529
4530 rc = ieee80211_register_hw(hw);
4531 if (rc) {
4532 wiphy_err(hw->wiphy, "Cannot register device\n");
4533 goto err_unprobe_hw;
4534 }
4535
4536 return 0;
4537
4538err_unprobe_hw:
4539 for (i = 0; i < MWL8K_TX_QUEUES; i++)
4540 mwl8k_txq_deinit(hw, i);
4541 mwl8k_rxq_deinit(hw, 0);
4542
be695fc4 4543err_free_cookie:
a66098da
LB		 4544 if (priv->cookie != NULL)
4545 pci_free_consistent(priv->pdev, 4,
4546 priv->cookie, priv->cookie_dma);
4547
3cc7772c
BC		 4548 return rc;
4549}
4550static int __devinit mwl8k_probe(struct pci_dev *pdev,
4551 const struct pci_device_id *id)
4552{
4553 static int printed_version;
4554 struct ieee80211_hw *hw;
4555 struct mwl8k_priv *priv;
0863ade8 4556 struct mwl8k_device_info *di;
3cc7772c
BC		 4557 int rc;
4558
4559 if (!printed_version) {
4560 printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
4561 printed_version = 1;
4562 }
4563
4564
4565 rc = pci_enable_device(pdev);
4566 if (rc) {
4567 printk(KERN_ERR "%s: Cannot enable new PCI device\n",
4568 MWL8K_NAME);
4569 return rc;
4570 }
4571
4572 rc = pci_request_regions(pdev, MWL8K_NAME);
4573 if (rc) {
4574 printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
4575 MWL8K_NAME);
4576 goto err_disable_device;
4577 }
4578
4579 pci_set_master(pdev);
4580
4581
4582 hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
4583 if (hw == NULL) {
4584 printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
4585 rc = -ENOMEM;
4586 goto err_free_reg;
4587 }
4588
4589 SET_IEEE80211_DEV(hw, &pdev->dev);
4590 pci_set_drvdata(pdev, hw);
4591
4592 priv = hw->priv;
4593 priv->hw = hw;
4594 priv->pdev = pdev;
4595 priv->device_info = &mwl8k_info_tbl[id->driver_data];
4596
4597
4598 priv->sram = pci_iomap(pdev, 0, 0x10000);
4599 if (priv->sram == NULL) {
4600 wiphy_err(hw->wiphy, "Cannot map device SRAM\n");
4601 goto err_iounmap;
4602 }
4603
4604 /*
4605 * If BAR0 is a 32 bit BAR, the register BAR will be BAR1.
4606 * If BAR0 is a 64 bit BAR, the register BAR will be BAR2.
4607 */
4608 priv->regs = pci_iomap(pdev, 1, 0x10000);
4609 if (priv->regs == NULL) {
4610 priv->regs = pci_iomap(pdev, 2, 0x10000);
4611 if (priv->regs == NULL) {
4612 wiphy_err(hw->wiphy, "Cannot map device registers\n");
4613 goto err_iounmap;
4614 }
4615 }
4616
0863ade8 4617 /*
99020471
BC		 4618 * Choose the initial fw image depending on user input. If a second
4619 * image is available, make it the alternative image that will be
4620 * loaded if the first one fails.
0863ade8 4621 */
99020471 4622 init_completion(&priv->firmware_loading_complete);
0863ade8 4623 di = priv->device_info;
99020471
BC		 4624 if (ap_mode_default && di->fw_image_ap) {
4625 priv->fw_pref = di->fw_image_ap;
4626 priv->fw_alt = di->fw_image_sta;
4627 } else if (!ap_mode_default && di->fw_image_sta) {
4628 priv->fw_pref = di->fw_image_sta;
4629 priv->fw_alt = di->fw_image_ap;
4630 } else if (ap_mode_default && !di->fw_image_ap && di->fw_image_sta) {
0863ade8 4631 printk(KERN_WARNING "AP fw is unavailable. Using STA fw.");
99020471 4632 priv->fw_pref = di->fw_image_sta;
0863ade8
BC		 4633 } else if (!ap_mode_default && !di->fw_image_sta && di->fw_image_ap) {
4634 printk(KERN_WARNING "STA fw is unavailable. Using AP fw.");
99020471
BC		 4635 priv->fw_pref = di->fw_image_ap;
4636 }
4637 rc = mwl8k_init_firmware(hw, priv->fw_pref, true);
3cc7772c
BC		 4638 if (rc)
4639 goto err_stop_firmware;
99020471 4640 return rc;
3cc7772c 4641
be695fc4
LB		 4642err_stop_firmware:
4643 mwl8k_hw_reset(priv);
be695fc4
LB		 4644
4645err_iounmap:
a66098da
LB		 4646 if (priv->regs != NULL)
4647 pci_iounmap(pdev, priv->regs);
4648
5b9482dd
LB		 4649 if (priv->sram != NULL)
4650 pci_iounmap(pdev, priv->sram);
4651
a66098da
LB		 4652 pci_set_drvdata(pdev, NULL);
4653 ieee80211_free_hw(hw);
4654
4655err_free_reg:
4656 pci_release_regions(pdev);
3db95e50
LB		 4657
4658err_disable_device:
a66098da
LB		 4659 pci_disable_device(pdev);
4660
4661 return rc;
4662}
4663
230f7af0 4664static void __devexit mwl8k_shutdown(struct pci_dev *pdev)
a66098da
LB		 4665{
4666 printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__);
4667}
4668
230f7af0 4669static void __devexit mwl8k_remove(struct pci_dev *pdev)
a66098da
LB		 4670{
4671 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
4672 struct mwl8k_priv *priv;
4673 int i;
4674
4675 if (hw == NULL)
4676 return;
4677 priv = hw->priv;
4678
99020471
BC		 4679 wait_for_completion(&priv->firmware_loading_complete);
4680
4681 if (priv->fw_state == FW_STATE_ERROR) {
4682 mwl8k_hw_reset(priv);
4683 goto unmap;
4684 }
4685
a66098da
LB		 4686 ieee80211_stop_queues(hw);
4687
60aa569f
LB		 4688 ieee80211_unregister_hw(hw);
4689
67e2eb27 4690 /* Remove TX reclaim and RX tasklets. */
1e9f9de3 4691 tasklet_kill(&priv->poll_tx_task);
67e2eb27 4692 tasklet_kill(&priv->poll_rx_task);
a66098da 4693
a66098da
LB		 4694 /* Stop hardware */
4695 mwl8k_hw_reset(priv);
4696
4697 /* Return all skbs to mac80211 */
4698 for (i = 0; i < MWL8K_TX_QUEUES; i++)
efb7c49a 4699 mwl8k_txq_reclaim(hw, i, INT_MAX, 1);
a66098da 4700
a66098da
LB		 4701 for (i = 0; i < MWL8K_TX_QUEUES; i++)
4702 mwl8k_txq_deinit(hw, i);
4703
4704 mwl8k_rxq_deinit(hw, 0);
4705
c2c357ce 4706 pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma);
a66098da 4707
99020471 4708unmap:
a66098da 4709 pci_iounmap(pdev, priv->regs);
5b9482dd 4710 pci_iounmap(pdev, priv->sram);
a66098da
LB		 4711 pci_set_drvdata(pdev, NULL);
4712 ieee80211_free_hw(hw);
4713 pci_release_regions(pdev);
4714 pci_disable_device(pdev);
4715}
4716
4717static struct pci_driver mwl8k_driver = {
4718 .name = MWL8K_NAME,
45a390dd 4719 .id_table = mwl8k_pci_id_table,
a66098da
LB		 4720 .probe = mwl8k_probe,
4721 .remove = __devexit_p(mwl8k_remove),
4722 .shutdown = __devexit_p(mwl8k_shutdown),
4723};
4724
4725static int __init mwl8k_init(void)
4726{
4727 return pci_register_driver(&mwl8k_driver);
4728}
4729
4730static void __exit mwl8k_exit(void)
4731{
4732 pci_unregister_driver(&mwl8k_driver);
4733}
4734
4735module_init(mwl8k_init);
4736module_exit(mwl8k_exit);
c2c357ce
LB		 4737
4738MODULE_DESCRIPTION(MWL8K_DESC);
4739MODULE_VERSION(MWL8K_VERSION);
4740MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
4741MODULE_LICENSE("GPL");
Linux kernel - Deliverables
This page took 0.703969 seconds and 5 git commands to generate.