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ipw2100: use pci_zalloc_consistent
[deliverable/linux.git] / drivers / net / wireless / mwl8k.c
CommitLineData
a66098da 1/*
ce9e2e1b
LB		 2 * drivers/net/wireless/mwl8k.c
3 * Driver for Marvell TOPDOG 802.11 Wireless cards
a66098da 4 *
a5fb297d 5 * Copyright (C) 2008, 2009, 2010 Marvell Semiconductor Inc.
a66098da
LB		 6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
a6b7a407 12#include <linux/interrupt.h>
a66098da
LB		 13#include <linux/module.h>
14#include <linux/kernel.h>
3d76e82c 15#include <linux/sched.h>
a66098da
LB		 16#include <linux/spinlock.h>
17#include <linux/list.h>
18#include <linux/pci.h>
19#include <linux/delay.h>
20#include <linux/completion.h>
21#include <linux/etherdevice.h>
5a0e3ad6 22#include <linux/slab.h>
a66098da
LB		 23#include <net/mac80211.h>
24#include <linux/moduleparam.h>
25#include <linux/firmware.h>
26#include <linux/workqueue.h>
27
28#define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
29#define MWL8K_NAME KBUILD_MODNAME
00e8e692 30#define MWL8K_VERSION "0.13"
a66098da 31
0863ade8 32/* Module parameters */
eb939922 33static bool ap_mode_default;
0863ade8
BC		 34module_param(ap_mode_default, bool, 0);
35MODULE_PARM_DESC(ap_mode_default,
36 "Set to 1 to make ap mode the default instead of sta mode");
37
a66098da
LB		 38/* Register definitions */
39#define MWL8K_HIU_GEN_PTR 0x00000c10
ce9e2e1b
LB		 40#define MWL8K_MODE_STA 0x0000005a
41#define MWL8K_MODE_AP 0x000000a5
a66098da 42#define MWL8K_HIU_INT_CODE 0x00000c14
ce9e2e1b
LB		 43#define MWL8K_FWSTA_READY 0xf0f1f2f4
44#define MWL8K_FWAP_READY 0xf1f2f4a5
45#define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
a66098da
LB		 46#define MWL8K_HIU_SCRATCH 0x00000c40
47
48/* Host->device communications */
49#define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
50#define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
51#define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
52#define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
53#define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
ce9e2e1b
LB		 54#define MWL8K_H2A_INT_DUMMY (1 << 20)
55#define MWL8K_H2A_INT_RESET (1 << 15)
56#define MWL8K_H2A_INT_DOORBELL (1 << 1)
57#define MWL8K_H2A_INT_PPA_READY (1 << 0)
a66098da
LB		 58
59/* Device->host communications */
60#define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
61#define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
62#define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
63#define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
64#define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
ce9e2e1b 65#define MWL8K_A2H_INT_DUMMY (1 << 20)
3aefc37e 66#define MWL8K_A2H_INT_BA_WATCHDOG (1 << 14)
ce9e2e1b
LB		 67#define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
68#define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
69#define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
70#define MWL8K_A2H_INT_RADIO_ON (1 << 6)
71#define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
72#define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
73#define MWL8K_A2H_INT_OPC_DONE (1 << 2)
74#define MWL8K_A2H_INT_RX_READY (1 << 1)
75#define MWL8K_A2H_INT_TX_DONE (1 << 0)
a66098da 76
566875db
PN		 77/* HW micro second timer register
78 * located at offset 0xA600. This
79 * will be used to timestamp tx
80 * packets.
81 */
82
83#define MWL8K_HW_TIMER_REGISTER 0x0000a600
4c924f42
YAP		 84#define BBU_RXRDY_CNT_REG 0x0000a860
85#define NOK_CCA_CNT_REG 0x0000a6a0
86#define BBU_AVG_NOISE_VAL 0x67
566875db 87
a66098da
LB		 88#define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
89 MWL8K_A2H_INT_CHNL_SWITCHED | \
90 MWL8K_A2H_INT_QUEUE_EMPTY | \
91 MWL8K_A2H_INT_RADAR_DETECT | \
92 MWL8K_A2H_INT_RADIO_ON | \
93 MWL8K_A2H_INT_RADIO_OFF | \
94 MWL8K_A2H_INT_MAC_EVENT | \
95 MWL8K_A2H_INT_OPC_DONE | \
96 MWL8K_A2H_INT_RX_READY | \
3aefc37e
NS		 97 MWL8K_A2H_INT_TX_DONE | \
98 MWL8K_A2H_INT_BA_WATCHDOG)
a66098da 99
a66098da 100#define MWL8K_RX_QUEUES 1
e600707b 101#define MWL8K_TX_WMM_QUEUES 4
8a7a578c 102#define MWL8K_MAX_AMPDU_QUEUES 8
e600707b
BC		 103#define MWL8K_MAX_TX_QUEUES (MWL8K_TX_WMM_QUEUES + MWL8K_MAX_AMPDU_QUEUES)
104#define mwl8k_tx_queues(priv) (MWL8K_TX_WMM_QUEUES + (priv)->num_ampdu_queues)
a66098da 105
7fb978b7
YAP		 106/* txpriorities are mapped with hw queues.
107 * Each hw queue has a txpriority.
108 */
109#define TOTAL_HW_TX_QUEUES 8
110
111/* Each HW queue can have one AMPDU stream.
112 * But, because one of the hw queue is reserved,
113 * maximum AMPDU queues that can be created are
114 * one short of total tx queues.
115 */
116#define MWL8K_NUM_AMPDU_STREAMS (TOTAL_HW_TX_QUEUES - 1)
117
031eb464
YAP		 118#define MWL8K_NUM_CHANS 18
119
54bc3a0d
LB		 120struct rxd_ops {
121 int rxd_size;
122 void (*rxd_init)(void *rxd, dma_addr_t next_dma_addr);
123 void (*rxd_refill)(void *rxd, dma_addr_t addr, int len);
20f09c3d 124 int (*rxd_process)(void *rxd, struct ieee80211_rx_status *status,
0d462bbb 125 __le16 *qos, s8 *noise);
54bc3a0d
LB		 126};
127
45a390dd 128struct mwl8k_device_info {
a74b295e
LB		 129 char *part_name;
130 char *helper_image;
0863ade8
BC		 131 char *fw_image_sta;
132 char *fw_image_ap;
89a91f4f 133 struct rxd_ops *ap_rxd_ops;
952a0e96 134 u32 fw_api_ap;
45a390dd
LB		 135};
136
a66098da 137struct mwl8k_rx_queue {
45eb400d 138 int rxd_count;
a66098da
LB		 139
140 /* hw receives here */
45eb400d 141 int head;
a66098da
LB		 142
143 /* refill descs here */
45eb400d 144 int tail;
a66098da 145
54bc3a0d 146 void *rxd;
45eb400d 147 dma_addr_t rxd_dma;
788838eb
LB		 148 struct {
149 struct sk_buff *skb;
53b1b3e1 150 DEFINE_DMA_UNMAP_ADDR(dma);
788838eb 151 } *buf;
a66098da
LB		 152};
153
a66098da
LB		 154struct mwl8k_tx_queue {
155 /* hw transmits here */
45eb400d 156 int head;
a66098da
LB		 157
158 /* sw appends here */
45eb400d 159 int tail;
a66098da 160
8ccbc3b8 161 unsigned int len;
45eb400d
LB		 162 struct mwl8k_tx_desc *txd;
163 dma_addr_t txd_dma;
164 struct sk_buff **skb;
a66098da
LB		 165};
166
ac109fd0
BC		 167enum {
168 AMPDU_NO_STREAM,
169 AMPDU_STREAM_NEW,
170 AMPDU_STREAM_IN_PROGRESS,
171 AMPDU_STREAM_ACTIVE,
172};
173
5faa1aff
NS		 174struct mwl8k_ampdu_stream {
175 struct ieee80211_sta *sta;
176 u8 tid;
177 u8 state;
178 u8 idx;
5faa1aff
NS		 179};
180
a66098da 181struct mwl8k_priv {
a66098da 182 struct ieee80211_hw *hw;
a66098da 183 struct pci_dev *pdev;
bf3ca7f7 184 int irq;
a66098da 185
45a390dd
LB		 186 struct mwl8k_device_info *device_info;
187
be695fc4
LB		 188 void __iomem *sram;
189 void __iomem *regs;
190
191 /* firmware */
d1f9e41d
BC		 192 const struct firmware *fw_helper;
193 const struct firmware *fw_ucode;
a66098da 194
be695fc4
LB		 195 /* hardware/firmware parameters */
196 bool ap_fw;
197 struct rxd_ops *rxd_ops;
777ad375
LB		 198 struct ieee80211_supported_band band_24;
199 struct ieee80211_channel channels_24[14];
3f524559 200 struct ieee80211_rate rates_24[13];
4eae9edd
LB		 201 struct ieee80211_supported_band band_50;
202 struct ieee80211_channel channels_50[4];
3f524559 203 struct ieee80211_rate rates_50[8];
ee0ddf18
LB		 204 u32 ap_macids_supported;
205 u32 sta_macids_supported;
be695fc4 206
8a7a578c
BC		 207 /* Ampdu stream information */
208 u8 num_ampdu_queues;
ac109fd0
BC		 209 spinlock_t stream_lock;
210 struct mwl8k_ampdu_stream ampdu[MWL8K_MAX_AMPDU_QUEUES];
3aefc37e 211 struct work_struct watchdog_ba_handle;
8a7a578c 212
618952a7
LB		 213 /* firmware access */
214 struct mutex fw_mutex;
215 struct task_struct *fw_mutex_owner;
6b6accc3 216 struct task_struct *hw_restart_owner;
618952a7 217 int fw_mutex_depth;
618952a7
LB		 218 struct completion *hostcmd_wait;
219
c27a54d3
YAP		 220 atomic_t watchdog_event_pending;
221
a66098da
LB		 222 /* lock held over TX and TX reap */
223 spinlock_t tx_lock;
a66098da 224
88de754a
LB		 225 /* TX quiesce completion, protected by fw_mutex and tx_lock */
226 struct completion *tx_wait;
227
f5bb87cf 228 /* List of interfaces. */
ee0ddf18 229 u32 macids_used;
f5bb87cf 230 struct list_head vif_list;
a66098da 231
a66098da
LB		 232 /* power management status cookie from firmware */
233 u32 *cookie;
234 dma_addr_t cookie_dma;
235
236 u16 num_mcaddrs;
a66098da 237 u8 hw_rev;
2aa7b01f 238 u32 fw_rev;
c3f251a3 239 u32 caps;
a66098da
LB		 240
241 /*
242 * Running count of TX packets in flight, to avoid
243 * iterating over the transmit rings each time.
244 */
245 int pending_tx_pkts;
246
247 struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
e600707b
BC		 248 struct mwl8k_tx_queue txq[MWL8K_MAX_TX_QUEUES];
249 u32 txq_offset[MWL8K_MAX_TX_QUEUES];
a66098da 250
c46563b7 251 bool radio_on;
68ce3884 252 bool radio_short_preamble;
a43c49a8 253 bool sniffer_enabled;
0439b1f5 254 bool wmm_enabled;
a66098da 255
a66098da
LB		 256 /* XXX need to convert this to handle multiple interfaces */
257 bool capture_beacon;
d89173f2 258 u8 capture_bssid[ETH_ALEN];
a66098da
LB		 259 struct sk_buff *beacon_skb;
260
261 /*
262 * This FJ worker has to be global as it is scheduled from the
263 * RX handler. At this point we don't know which interface it
264 * belongs to until the list of bssids waiting to complete join
265 * is checked.
266 */
267 struct work_struct finalize_join_worker;
268
1e9f9de3
LB		 269 /* Tasklet to perform TX reclaim. */
270 struct tasklet_struct poll_tx_task;
67e2eb27
LB		 271
272 /* Tasklet to perform RX. */
273 struct tasklet_struct poll_rx_task;
0d462bbb
JL		 274
275 /* Most recently reported noise in dBm */
276 s8 noise;
0863ade8
BC		 277
278 /*
279 * preserve the queue configurations so they can be restored if/when
280 * the firmware image is swapped.
281 */
e600707b 282 struct ieee80211_tx_queue_params wmm_params[MWL8K_TX_WMM_QUEUES];
99020471 283
6b6accc3
YAP		 284 /* To perform the task of reloading the firmware */
285 struct work_struct fw_reload;
286 bool hw_restart_in_progress;
287
99020471
BC		 288 /* async firmware loading state */
289 unsigned fw_state;
290 char *fw_pref;
291 char *fw_alt;
98929824 292 bool is_8764;
99020471 293 struct completion firmware_loading_complete;
e882efc9
YAP		 294
295 /* bitmap of running BSSes */
296 u32 running_bsses;
4c924f42
YAP		 297
298 /* ACS related */
299 bool sw_scan_start;
031eb464
YAP		 300 struct ieee80211_channel *acs_chan;
301 unsigned long channel_time;
302 struct survey_info survey[MWL8K_NUM_CHANS];
a66098da
LB		 303};
304
e53d9b96
NS		 305#define MAX_WEP_KEY_LEN 13
306#define NUM_WEP_KEYS 4
307
a66098da
LB		 308/* Per interface specific private data */
309struct mwl8k_vif {
f5bb87cf
LB		 310 struct list_head list;
311 struct ieee80211_vif *vif;
312
f57ca9c1
LB		 313 /* Firmware macid for this vif. */
314 int macid;
315
c2c2b12a 316 /* Non AMPDU sequence number assigned by driver. */
a680400e 317 u16 seqno;
e53d9b96
NS		 318
319 /* Saved WEP keys */
320 struct {
321 u8 enabled;
322 u8 key[sizeof(struct ieee80211_key_conf) + MAX_WEP_KEY_LEN];
323 } wep_key_conf[NUM_WEP_KEYS];
d9a07d49
NS		 324
325 /* BSSID */
326 u8 bssid[ETH_ALEN];
327
328 /* A flag to indicate is HW crypto is enabled for this bssid */
329 bool is_hw_crypto_enabled;
a66098da 330};
a94cc97e 331#define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
fcdc403c 332#define IEEE80211_KEY_CONF(_u8) ((struct ieee80211_key_conf *)(_u8))
a66098da 333
d0805c1c
BC		 334struct tx_traffic_info {
335 u32 start_time;
336 u32 pkts;
337};
338
339#define MWL8K_MAX_TID 8
a680400e
LB		 340struct mwl8k_sta {
341 /* Index into station database. Returned by UPDATE_STADB. */
342 u8 peer_id;
17033543 343 u8 is_ampdu_allowed;
d0805c1c 344 struct tx_traffic_info tx_stats[MWL8K_MAX_TID];
a680400e
LB		 345};
346#define MWL8K_STA(_sta) ((struct mwl8k_sta *)&((_sta)->drv_priv))
347
777ad375 348static const struct ieee80211_channel mwl8k_channels_24[] = {
d786f67e
JG		 349 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2412, .hw_value = 1, },
350 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2417, .hw_value = 2, },
351 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2422, .hw_value = 3, },
352 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2427, .hw_value = 4, },
353 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2432, .hw_value = 5, },
354 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2437, .hw_value = 6, },
355 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2442, .hw_value = 7, },
356 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2447, .hw_value = 8, },
357 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2452, .hw_value = 9, },
358 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2457, .hw_value = 10, },
359 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2462, .hw_value = 11, },
360 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2467, .hw_value = 12, },
361 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2472, .hw_value = 13, },
362 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2484, .hw_value = 14, },
a66098da
LB		 363};
364
777ad375 365static const struct ieee80211_rate mwl8k_rates_24[] = {
a66098da
LB		 366 { .bitrate = 10, .hw_value = 2, },
367 { .bitrate = 20, .hw_value = 4, },
368 { .bitrate = 55, .hw_value = 11, },
5dfd3e2c
LB		 369 { .bitrate = 110, .hw_value = 22, },
370 { .bitrate = 220, .hw_value = 44, },
a66098da
LB		 371 { .bitrate = 60, .hw_value = 12, },
372 { .bitrate = 90, .hw_value = 18, },
a66098da
LB		 373 { .bitrate = 120, .hw_value = 24, },
374 { .bitrate = 180, .hw_value = 36, },
375 { .bitrate = 240, .hw_value = 48, },
376 { .bitrate = 360, .hw_value = 72, },
377 { .bitrate = 480, .hw_value = 96, },
378 { .bitrate = 540, .hw_value = 108, },
140eb5e2
LB		 379};
380
4eae9edd 381static const struct ieee80211_channel mwl8k_channels_50[] = {
d786f67e
JG		 382 { .band = IEEE80211_BAND_5GHZ, .center_freq = 5180, .hw_value = 36, },
383 { .band = IEEE80211_BAND_5GHZ, .center_freq = 5200, .hw_value = 40, },
384 { .band = IEEE80211_BAND_5GHZ, .center_freq = 5220, .hw_value = 44, },
385 { .band = IEEE80211_BAND_5GHZ, .center_freq = 5240, .hw_value = 48, },
4eae9edd
LB		 386};
387
388static const struct ieee80211_rate mwl8k_rates_50[] = {
389 { .bitrate = 60, .hw_value = 12, },
390 { .bitrate = 90, .hw_value = 18, },
391 { .bitrate = 120, .hw_value = 24, },
392 { .bitrate = 180, .hw_value = 36, },
393 { .bitrate = 240, .hw_value = 48, },
394 { .bitrate = 360, .hw_value = 72, },
395 { .bitrate = 480, .hw_value = 96, },
396 { .bitrate = 540, .hw_value = 108, },
4eae9edd
LB		 397};
398
a66098da 399/* Set or get info from Firmware */
a66098da 400#define MWL8K_CMD_GET 0x0000
41fdf097
NS		 401#define MWL8K_CMD_SET 0x0001
402#define MWL8K_CMD_SET_LIST 0x0002
a66098da
LB		 403
404/* Firmware command codes */
405#define MWL8K_CMD_CODE_DNLD 0x0001
406#define MWL8K_CMD_GET_HW_SPEC 0x0003
42fba21d 407#define MWL8K_CMD_SET_HW_SPEC 0x0004
a66098da
LB		 408#define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
409#define MWL8K_CMD_GET_STAT 0x0014
c3015313 410#define MWL8K_CMD_BBP_REG_ACCESS 0x001a
ff45fc60
LB		 411#define MWL8K_CMD_RADIO_CONTROL 0x001c
412#define MWL8K_CMD_RF_TX_POWER 0x001e
41fdf097 413#define MWL8K_CMD_TX_POWER 0x001f
08b06347 414#define MWL8K_CMD_RF_ANTENNA 0x0020
aa21d0f6 415#define MWL8K_CMD_SET_BEACON 0x0100 /* per-vif */
a66098da
LB		 416#define MWL8K_CMD_SET_PRE_SCAN 0x0107
417#define MWL8K_CMD_SET_POST_SCAN 0x0108
ff45fc60
LB		 418#define MWL8K_CMD_SET_RF_CHANNEL 0x010a
419#define MWL8K_CMD_SET_AID 0x010d
420#define MWL8K_CMD_SET_RATE 0x0110
421#define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
422#define MWL8K_CMD_RTS_THRESHOLD 0x0113
a66098da 423#define MWL8K_CMD_SET_SLOT 0x0114
ff45fc60
LB		 424#define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
425#define MWL8K_CMD_SET_WMM_MODE 0x0123
a66098da 426#define MWL8K_CMD_MIMO_CONFIG 0x0125
ff45fc60 427#define MWL8K_CMD_USE_FIXED_RATE 0x0126
a66098da 428#define MWL8K_CMD_ENABLE_SNIFFER 0x0150
aa21d0f6 429#define MWL8K_CMD_SET_MAC_ADDR 0x0202 /* per-vif */
a66098da 430#define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
3aefc37e 431#define MWL8K_CMD_GET_WATCHDOG_BITMAP 0x0205
197a4e4e 432#define MWL8K_CMD_DEL_MAC_ADDR 0x0206 /* per-vif */
aa21d0f6
LB		 433#define MWL8K_CMD_BSS_START 0x1100 /* per-vif */
434#define MWL8K_CMD_SET_NEW_STN 0x1111 /* per-vif */
fcdc403c 435#define MWL8K_CMD_UPDATE_ENCRYPTION 0x1122 /* per-vif */
ff45fc60 436#define MWL8K_CMD_UPDATE_STADB 0x1123
5faa1aff 437#define MWL8K_CMD_BASTREAM 0x1125
a66098da 438
b603742f 439static const char *mwl8k_cmd_name(__le16 cmd, char *buf, int bufsize)
a66098da 440{
b603742f
JL		 441 u16 command = le16_to_cpu(cmd);
442
a66098da
LB		 443#define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
444 snprintf(buf, bufsize, "%s", #x);\
445 return buf;\
446 } while (0)
b603742f 447 switch (command & ~0x8000) {
a66098da
LB		 448 MWL8K_CMDNAME(CODE_DNLD);
449 MWL8K_CMDNAME(GET_HW_SPEC);
42fba21d 450 MWL8K_CMDNAME(SET_HW_SPEC);
a66098da
LB		 451 MWL8K_CMDNAME(MAC_MULTICAST_ADR);
452 MWL8K_CMDNAME(GET_STAT);
453 MWL8K_CMDNAME(RADIO_CONTROL);
454 MWL8K_CMDNAME(RF_TX_POWER);
41fdf097 455 MWL8K_CMDNAME(TX_POWER);
08b06347 456 MWL8K_CMDNAME(RF_ANTENNA);
b64fe619 457 MWL8K_CMDNAME(SET_BEACON);
a66098da
LB		 458 MWL8K_CMDNAME(SET_PRE_SCAN);
459 MWL8K_CMDNAME(SET_POST_SCAN);
460 MWL8K_CMDNAME(SET_RF_CHANNEL);
ff45fc60
LB		 461 MWL8K_CMDNAME(SET_AID);
462 MWL8K_CMDNAME(SET_RATE);
463 MWL8K_CMDNAME(SET_FINALIZE_JOIN);
464 MWL8K_CMDNAME(RTS_THRESHOLD);
a66098da 465 MWL8K_CMDNAME(SET_SLOT);
ff45fc60
LB		 466 MWL8K_CMDNAME(SET_EDCA_PARAMS);
467 MWL8K_CMDNAME(SET_WMM_MODE);
a66098da 468 MWL8K_CMDNAME(MIMO_CONFIG);
ff45fc60 469 MWL8K_CMDNAME(USE_FIXED_RATE);
a66098da 470 MWL8K_CMDNAME(ENABLE_SNIFFER);
32060e1b 471 MWL8K_CMDNAME(SET_MAC_ADDR);
a66098da 472 MWL8K_CMDNAME(SET_RATEADAPT_MODE);
b64fe619 473 MWL8K_CMDNAME(BSS_START);
3f5610ff 474 MWL8K_CMDNAME(SET_NEW_STN);
fcdc403c 475 MWL8K_CMDNAME(UPDATE_ENCRYPTION);
ff45fc60 476 MWL8K_CMDNAME(UPDATE_STADB);
5faa1aff 477 MWL8K_CMDNAME(BASTREAM);
3aefc37e 478 MWL8K_CMDNAME(GET_WATCHDOG_BITMAP);
a66098da
LB		 479 default:
480 snprintf(buf, bufsize, "0x%x", cmd);
481 }
482#undef MWL8K_CMDNAME
483
484 return buf;
485}
486
487/* Hardware and firmware reset */
488static void mwl8k_hw_reset(struct mwl8k_priv *priv)
489{
490 iowrite32(MWL8K_H2A_INT_RESET,
491 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
492 iowrite32(MWL8K_H2A_INT_RESET,
493 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
494 msleep(20);
495}
496
497/* Release fw image */
d1f9e41d 498static void mwl8k_release_fw(const struct firmware **fw)
a66098da
LB		 499{
500 if (*fw == NULL)
501 return;
502 release_firmware(*fw);
503 *fw = NULL;
504}
505
506static void mwl8k_release_firmware(struct mwl8k_priv *priv)
507{
22be40d9
LB		 508 mwl8k_release_fw(&priv->fw_ucode);
509 mwl8k_release_fw(&priv->fw_helper);
a66098da
LB		 510}
511
99020471
BC		 512/* states for asynchronous f/w loading */
513static void mwl8k_fw_state_machine(const struct firmware *fw, void *context);
514enum {
515 FW_STATE_INIT = 0,
516 FW_STATE_LOADING_PREF,
517 FW_STATE_LOADING_ALT,
518 FW_STATE_ERROR,
519};
520
a66098da
LB		 521/* Request fw image */
522static int mwl8k_request_fw(struct mwl8k_priv *priv,
d1f9e41d 523 const char *fname, const struct firmware **fw,
99020471 524 bool nowait)
a66098da
LB		 525{
526 /* release current image */
527 if (*fw != NULL)
528 mwl8k_release_fw(fw);
529
99020471
BC		 530 if (nowait)
531 return request_firmware_nowait(THIS_MODULE, 1, fname,
532 &priv->pdev->dev, GFP_KERNEL,
533 priv, mwl8k_fw_state_machine);
534 else
d1f9e41d 535 return request_firmware(fw, fname, &priv->pdev->dev);
a66098da
LB		 536}
537
99020471
BC		 538static int mwl8k_request_firmware(struct mwl8k_priv *priv, char *fw_image,
539 bool nowait)
a66098da 540{
a74b295e 541 struct mwl8k_device_info *di = priv->device_info;
a66098da
LB		 542 int rc;
543
a74b295e 544 if (di->helper_image != NULL) {
99020471
BC		 545 if (nowait)
546 rc = mwl8k_request_fw(priv, di->helper_image,
547 &priv->fw_helper, true);
548 else
549 rc = mwl8k_request_fw(priv, di->helper_image,
550 &priv->fw_helper, false);
551 if (rc)
552 printk(KERN_ERR "%s: Error requesting helper fw %s\n",
553 pci_name(priv->pdev), di->helper_image);
554
555 if (rc || nowait)
a74b295e 556 return rc;
a66098da
LB		 557 }
558
99020471
BC		 559 if (nowait) {
560 /*
561 * if we get here, no helper image is needed. Skip the
562 * FW_STATE_INIT state.
563 */
564 priv->fw_state = FW_STATE_LOADING_PREF;
565 rc = mwl8k_request_fw(priv, fw_image,
566 &priv->fw_ucode,
567 true);
568 } else
569 rc = mwl8k_request_fw(priv, fw_image,
570 &priv->fw_ucode, false);
a66098da 571 if (rc) {
c2c357ce 572 printk(KERN_ERR "%s: Error requesting firmware file %s\n",
0863ade8 573 pci_name(priv->pdev), fw_image);
22be40d9 574 mwl8k_release_fw(&priv->fw_helper);
a66098da
LB		 575 return rc;
576 }
577
578 return 0;
579}
580
581struct mwl8k_cmd_pkt {
582 __le16 code;
583 __le16 length;
f57ca9c1
LB		 584 __u8 seq_num;
585 __u8 macid;
a66098da
LB		 586 __le16 result;
587 char payload[0];
ba2d3587 588} __packed;
a66098da
LB		 589
590/*
591 * Firmware loading.
592 */
593static int
594mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
595{
596 void __iomem *regs = priv->regs;
597 dma_addr_t dma_addr;
a66098da
LB		 598 int loops;
599
600 dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
601 if (pci_dma_mapping_error(priv->pdev, dma_addr))
602 return -ENOMEM;
603
604 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
605 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
606 iowrite32(MWL8K_H2A_INT_DOORBELL,
607 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
608 iowrite32(MWL8K_H2A_INT_DUMMY,
609 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
610
a66098da
LB		 611 loops = 1000;
612 do {
613 u32 int_code;
98929824
NS		 614 if (priv->is_8764) {
615 int_code = ioread32(regs +
616 MWL8K_HIU_H2A_INTERRUPT_STATUS);
617 if (int_code == 0)
618 break;
619 } else {
620 int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
621 if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
622 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
623 break;
624 }
a66098da 625 }
3d76e82c 626 cond_resched();
a66098da
LB		 627 udelay(1);
628 } while (--loops);
629
630 pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
631
d4b70570 632 return loops ? 0 : -ETIMEDOUT;
a66098da
LB		 633}
634
635static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
636 const u8 *data, size_t length)
637{
638 struct mwl8k_cmd_pkt *cmd;
639 int done;
640 int rc = 0;
641
642 cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
643 if (cmd == NULL)
644 return -ENOMEM;
645
646 cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
647 cmd->seq_num = 0;
f57ca9c1 648 cmd->macid = 0;
a66098da
LB		 649 cmd->result = 0;
650
651 done = 0;
652 while (length) {
653 int block_size = length > 256 ? 256 : length;
654
655 memcpy(cmd->payload, data + done, block_size);
656 cmd->length = cpu_to_le16(block_size);
657
658 rc = mwl8k_send_fw_load_cmd(priv, cmd,
659 sizeof(*cmd) + block_size);
660 if (rc)
661 break;
662
663 done += block_size;
664 length -= block_size;
665 }
666
667 if (!rc) {
668 cmd->length = 0;
669 rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
670 }
671
672 kfree(cmd);
673
674 return rc;
675}
676
677static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
678 const u8 *data, size_t length)
679{
680 unsigned char *buffer;
681 int may_continue, rc = 0;
682 u32 done, prev_block_size;
683
684 buffer = kmalloc(1024, GFP_KERNEL);
685 if (buffer == NULL)
686 return -ENOMEM;
687
688 done = 0;
689 prev_block_size = 0;
690 may_continue = 1000;
691 while (may_continue > 0) {
692 u32 block_size;
693
694 block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
695 if (block_size & 1) {
696 block_size &= ~1;
697 may_continue--;
698 } else {
699 done += prev_block_size;
700 length -= prev_block_size;
701 }
702
703 if (block_size > 1024 || block_size > length) {
704 rc = -EOVERFLOW;
705 break;
706 }
707
708 if (length == 0) {
709 rc = 0;
710 break;
711 }
712
713 if (block_size == 0) {
714 rc = -EPROTO;
715 may_continue--;
716 udelay(1);
717 continue;
718 }
719
720 prev_block_size = block_size;
721 memcpy(buffer, data + done, block_size);
722
723 rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
724 if (rc)
725 break;
726 }
727
728 if (!rc && length != 0)
729 rc = -EREMOTEIO;
730
731 kfree(buffer);
732
733 return rc;
734}
735
c2c357ce 736static int mwl8k_load_firmware(struct ieee80211_hw *hw)
a66098da 737{
c2c357ce 738 struct mwl8k_priv *priv = hw->priv;
d1f9e41d 739 const struct firmware *fw = priv->fw_ucode;
c2c357ce
LB		 740 int rc;
741 int loops;
742
98929824 743 if (!memcmp(fw->data, "\x01\x00\x00\x00", 4) && !priv->is_8764) {
d1f9e41d 744 const struct firmware *helper = priv->fw_helper;
a66098da 745
c2c357ce
LB		 746 if (helper == NULL) {
747 printk(KERN_ERR "%s: helper image needed but none "
748 "given\n", pci_name(priv->pdev));
749 return -EINVAL;
750 }
a66098da 751
c2c357ce 752 rc = mwl8k_load_fw_image(priv, helper->data, helper->size);
a66098da
LB		 753 if (rc) {
754 printk(KERN_ERR "%s: unable to load firmware "
c2c357ce 755 "helper image\n", pci_name(priv->pdev));
a66098da
LB		 756 return rc;
757 }
ba30c4a5 758 msleep(20);
a66098da 759
c2c357ce 760 rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
a66098da 761 } else {
98929824
NS		 762 if (priv->is_8764)
763 rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
764 else
765 rc = mwl8k_load_fw_image(priv, fw->data, fw->size);
a66098da
LB		 766 }
767
768 if (rc) {
c2c357ce
LB		 769 printk(KERN_ERR "%s: unable to load firmware image\n",
770 pci_name(priv->pdev));
a66098da
LB		 771 return rc;
772 }
773
89a91f4f 774 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
a66098da 775
89b872e2 776 loops = 500000;
a66098da 777 do {
eae74e65
LB		 778 u32 ready_code;
779
780 ready_code = ioread32(priv->regs + MWL8K_HIU_INT_CODE);
781 if (ready_code == MWL8K_FWAP_READY) {
3db1cd5c 782 priv->ap_fw = true;
eae74e65
LB		 783 break;
784 } else if (ready_code == MWL8K_FWSTA_READY) {
3db1cd5c 785 priv->ap_fw = false;
a66098da 786 break;
eae74e65
LB		 787 }
788
789 cond_resched();
a66098da
LB		 790 udelay(1);
791 } while (--loops);
792
793 return loops ? 0 : -ETIMEDOUT;
794}
795
796
a66098da
LB		 797/* DMA header used by firmware and hardware. */
798struct mwl8k_dma_data {
799 __le16 fwlen;
800 struct ieee80211_hdr wh;
20f09c3d 801 char data[0];
ba2d3587 802} __packed;
a66098da
LB		 803
804/* Routines to add/remove DMA header from skb. */
20f09c3d 805static inline void mwl8k_remove_dma_header(struct sk_buff *skb, __le16 qos)
a66098da 806{
20f09c3d
LB		 807 struct mwl8k_dma_data *tr;
808 int hdrlen;
809
810 tr = (struct mwl8k_dma_data *)skb->data;
811 hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
812
813 if (hdrlen != sizeof(tr->wh)) {
814 if (ieee80211_is_data_qos(tr->wh.frame_control)) {
815 memmove(tr->data - hdrlen, &tr->wh, hdrlen - 2);
816 *((__le16 *)(tr->data - 2)) = qos;
817 } else {
818 memmove(tr->data - hdrlen, &tr->wh, hdrlen);
819 }
a66098da 820 }
20f09c3d
LB		 821
822 if (hdrlen != sizeof(*tr))
823 skb_pull(skb, sizeof(*tr) - hdrlen);
a66098da
LB		 824}
825
ff776cec
YAP		 826#define REDUCED_TX_HEADROOM 8
827
252486a1 828static void
e4eefec7
YAP		 829mwl8k_add_dma_header(struct mwl8k_priv *priv, struct sk_buff *skb,
830 int head_pad, int tail_pad)
a66098da
LB		 831{
832 struct ieee80211_hdr *wh;
ca009301 833 int hdrlen;
252486a1 834 int reqd_hdrlen;
a66098da
LB		 835 struct mwl8k_dma_data *tr;
836
ca009301
LB		 837 /*
838 * Add a firmware DMA header; the firmware requires that we
839 * present a 2-byte payload length followed by a 4-address
840 * header (without QoS field), followed (optionally) by any
841 * WEP/ExtIV header (but only filled in for CCMP).
842 */
a66098da 843 wh = (struct ieee80211_hdr *)skb->data;
ca009301 844
a66098da 845 hdrlen = ieee80211_hdrlen(wh->frame_control);
ff776cec
YAP		 846
847 /*
848 * Check if skb_resize is required because of
849 * tx_headroom adjustment.
850 */
851 if (priv->ap_fw && (hdrlen < (sizeof(struct ieee80211_cts)
852 + REDUCED_TX_HEADROOM))) {
853 if (pskb_expand_head(skb, REDUCED_TX_HEADROOM, 0, GFP_ATOMIC)) {
854
855 wiphy_err(priv->hw->wiphy,
856 "Failed to reallocate TX buffer\n");
857 return;
858 }
859 skb->truesize += REDUCED_TX_HEADROOM;
860 }
861
e4eefec7 862 reqd_hdrlen = sizeof(*tr) + head_pad;
252486a1
NS		 863
864 if (hdrlen != reqd_hdrlen)
865 skb_push(skb, reqd_hdrlen - hdrlen);
a66098da 866
ca009301 867 if (ieee80211_is_data_qos(wh->frame_control))
252486a1 868 hdrlen -= IEEE80211_QOS_CTL_LEN;
a66098da
LB		 869
870 tr = (struct mwl8k_dma_data *)skb->data;
871 if (wh != &tr->wh)
872 memmove(&tr->wh, wh, hdrlen);
ca009301
LB		 873 if (hdrlen != sizeof(tr->wh))
874 memset(((void *)&tr->wh) + hdrlen, 0, sizeof(tr->wh) - hdrlen);
a66098da
LB		 875
876 /*
877 * Firmware length is the length of the fully formed "802.11
878 * payload". That is, everything except for the 802.11 header.
879 * This includes all crypto material including the MIC.
880 */
252486a1 881 tr->fwlen = cpu_to_le16(skb->len - sizeof(*tr) + tail_pad);
a66098da
LB		 882}
883
ff776cec
YAP		 884static void mwl8k_encapsulate_tx_frame(struct mwl8k_priv *priv,
885 struct sk_buff *skb)
e53d9b96
NS		 886{
887 struct ieee80211_hdr *wh;
888 struct ieee80211_tx_info *tx_info;
889 struct ieee80211_key_conf *key_conf;
890 int data_pad;
e4eefec7 891 int head_pad = 0;
e53d9b96
NS		 892
893 wh = (struct ieee80211_hdr *)skb->data;
894
895 tx_info = IEEE80211_SKB_CB(skb);
896
897 key_conf = NULL;
898 if (ieee80211_is_data(wh->frame_control))
899 key_conf = tx_info->control.hw_key;
900
901 /*
902 * Make sure the packet header is in the DMA header format (4-address
e4eefec7 903 * without QoS), and add head & tail padding when HW crypto is enabled.
e53d9b96
NS		 904 *
905 * We have the following trailer padding requirements:
906 * - WEP: 4 trailer bytes (ICV)
907 * - TKIP: 12 trailer bytes (8 MIC + 4 ICV)
908 * - CCMP: 8 trailer bytes (MIC)
909 */
910 data_pad = 0;
911 if (key_conf != NULL) {
e4eefec7 912 head_pad = key_conf->iv_len;
e53d9b96
NS		 913 switch (key_conf->cipher) {
914 case WLAN_CIPHER_SUITE_WEP40:
915 case WLAN_CIPHER_SUITE_WEP104:
916 data_pad = 4;
917 break;
918 case WLAN_CIPHER_SUITE_TKIP:
919 data_pad = 12;
920 break;
921 case WLAN_CIPHER_SUITE_CCMP:
922 data_pad = 8;
923 break;
924 }
925 }
e4eefec7 926 mwl8k_add_dma_header(priv, skb, head_pad, data_pad);
e53d9b96 927}
a66098da
LB		 928
929/*
d926dc7d 930 * Packet reception for 88w8366/88w8764 AP firmware.
6f6d1e9a 931 */
d926dc7d 932struct mwl8k_rxd_ap {
6f6d1e9a
LB		 933 __le16 pkt_len;
934 __u8 sq2;
935 __u8 rate;
936 __le32 pkt_phys_addr;
937 __le32 next_rxd_phys_addr;
938 __le16 qos_control;
939 __le16 htsig2;
940 __le32 hw_rssi_info;
941 __le32 hw_noise_floor_info;
942 __u8 noise_floor;
943 __u8 pad0[3];
944 __u8 rssi;
945 __u8 rx_status;
946 __u8 channel;
947 __u8 rx_ctrl;
ba2d3587 948} __packed;
6f6d1e9a 949
d926dc7d
NS		 950#define MWL8K_AP_RATE_INFO_MCS_FORMAT 0x80
951#define MWL8K_AP_RATE_INFO_40MHZ 0x40
952#define MWL8K_AP_RATE_INFO_RATEID(x) ((x) & 0x3f)
8e9f33f0 953
d926dc7d 954#define MWL8K_AP_RX_CTRL_OWNED_BY_HOST 0x80
6f6d1e9a 955
d926dc7d
NS		 956/* 8366/8764 AP rx_status bits */
957#define MWL8K_AP_RXSTAT_DECRYPT_ERR_MASK 0x80
958#define MWL8K_AP_RXSTAT_GENERAL_DECRYPT_ERR 0xFF
959#define MWL8K_AP_RXSTAT_TKIP_DECRYPT_MIC_ERR 0x02
960#define MWL8K_AP_RXSTAT_WEP_DECRYPT_ICV_ERR 0x04
961#define MWL8K_AP_RXSTAT_TKIP_DECRYPT_ICV_ERR 0x08
d9a07d49 962
d926dc7d 963static void mwl8k_rxd_ap_init(void *_rxd, dma_addr_t next_dma_addr)
6f6d1e9a 964{
d926dc7d 965 struct mwl8k_rxd_ap *rxd = _rxd;
6f6d1e9a
LB		 966
967 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
d926dc7d 968 rxd->rx_ctrl = MWL8K_AP_RX_CTRL_OWNED_BY_HOST;
6f6d1e9a
LB		 969}
970
d926dc7d 971static void mwl8k_rxd_ap_refill(void *_rxd, dma_addr_t addr, int len)
6f6d1e9a 972{
d926dc7d 973 struct mwl8k_rxd_ap *rxd = _rxd;
6f6d1e9a
LB		 974
975 rxd->pkt_len = cpu_to_le16(len);
976 rxd->pkt_phys_addr = cpu_to_le32(addr);
977 wmb();
978 rxd->rx_ctrl = 0;
979}
980
981static int
d926dc7d
NS		 982mwl8k_rxd_ap_process(void *_rxd, struct ieee80211_rx_status *status,
983 __le16 *qos, s8 *noise)
6f6d1e9a 984{
d926dc7d 985 struct mwl8k_rxd_ap *rxd = _rxd;
6f6d1e9a 986
d926dc7d 987 if (!(rxd->rx_ctrl & MWL8K_AP_RX_CTRL_OWNED_BY_HOST))
6f6d1e9a
LB		 988 return -1;
989 rmb();
990
991 memset(status, 0, sizeof(*status));
992
993 status->signal = -rxd->rssi;
0d462bbb 994 *noise = -rxd->noise_floor;
6f6d1e9a 995
d926dc7d 996 if (rxd->rate & MWL8K_AP_RATE_INFO_MCS_FORMAT) {
6f6d1e9a 997 status->flag |= RX_FLAG_HT;
d926dc7d 998 if (rxd->rate & MWL8K_AP_RATE_INFO_40MHZ)
8e9f33f0 999 status->flag |= RX_FLAG_40MHZ;
d926dc7d 1000 status->rate_idx = MWL8K_AP_RATE_INFO_RATEID(rxd->rate);
6f6d1e9a
LB		 1001 } else {
1002 int i;
1003
777ad375
LB		 1004 for (i = 0; i < ARRAY_SIZE(mwl8k_rates_24); i++) {
1005 if (mwl8k_rates_24[i].hw_value == rxd->rate) {
6f6d1e9a
LB		 1006 status->rate_idx = i;
1007 break;
1008 }
1009 }
1010 }
1011
85478344
LB		 1012 if (rxd->channel > 14) {
1013 status->band = IEEE80211_BAND_5GHZ;
1014 if (!(status->flag & RX_FLAG_HT))
1015 status->rate_idx -= 5;
1016 } else {
1017 status->band = IEEE80211_BAND_2GHZ;
1018 }
59eb21a6
BR		 1019 status->freq = ieee80211_channel_to_frequency(rxd->channel,
1020 status->band);
6f6d1e9a 1021
20f09c3d
LB		 1022 *qos = rxd->qos_control;
1023
d926dc7d
NS		 1024 if ((rxd->rx_status != MWL8K_AP_RXSTAT_GENERAL_DECRYPT_ERR) &&
1025 (rxd->rx_status & MWL8K_AP_RXSTAT_DECRYPT_ERR_MASK) &&
1026 (rxd->rx_status & MWL8K_AP_RXSTAT_TKIP_DECRYPT_MIC_ERR))
d9a07d49
NS		 1027 status->flag |= RX_FLAG_MMIC_ERROR;
1028
6f6d1e9a
LB		 1029 return le16_to_cpu(rxd->pkt_len);
1030}
1031
d926dc7d
NS		 1032static struct rxd_ops rxd_ap_ops = {
1033 .rxd_size = sizeof(struct mwl8k_rxd_ap),
1034 .rxd_init = mwl8k_rxd_ap_init,
1035 .rxd_refill = mwl8k_rxd_ap_refill,
1036 .rxd_process = mwl8k_rxd_ap_process,
6f6d1e9a
LB		 1037};
1038
1039/*
89a91f4f 1040 * Packet reception for STA firmware.
a66098da 1041 */
89a91f4f 1042struct mwl8k_rxd_sta {
a66098da
LB		 1043 __le16 pkt_len;
1044 __u8 link_quality;
1045 __u8 noise_level;
1046 __le32 pkt_phys_addr;
45eb400d 1047 __le32 next_rxd_phys_addr;
a66098da
LB		 1048 __le16 qos_control;
1049 __le16 rate_info;
1050 __le32 pad0[4];
1051 __u8 rssi;
1052 __u8 channel;
1053 __le16 pad1;
1054 __u8 rx_ctrl;
1055 __u8 rx_status;
1056 __u8 pad2[2];
ba2d3587 1057} __packed;
a66098da 1058
89a91f4f
LB		 1059#define MWL8K_STA_RATE_INFO_SHORTPRE 0x8000
1060#define MWL8K_STA_RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3)
1061#define MWL8K_STA_RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f)
1062#define MWL8K_STA_RATE_INFO_40MHZ 0x0004
1063#define MWL8K_STA_RATE_INFO_SHORTGI 0x0002
1064#define MWL8K_STA_RATE_INFO_MCS_FORMAT 0x0001
54bc3a0d 1065
89a91f4f 1066#define MWL8K_STA_RX_CTRL_OWNED_BY_HOST 0x02
d9a07d49
NS		 1067#define MWL8K_STA_RX_CTRL_DECRYPT_ERROR 0x04
1068/* ICV=0 or MIC=1 */
1069#define MWL8K_STA_RX_CTRL_DEC_ERR_TYPE 0x08
1070/* Key is uploaded only in failure case */
1071#define MWL8K_STA_RX_CTRL_KEY_INDEX 0x30
54bc3a0d 1072
89a91f4f 1073static void mwl8k_rxd_sta_init(void *_rxd, dma_addr_t next_dma_addr)
54bc3a0d 1074{
89a91f4f 1075 struct mwl8k_rxd_sta *rxd = _rxd;
54bc3a0d
LB		 1076
1077 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
89a91f4f 1078 rxd->rx_ctrl = MWL8K_STA_RX_CTRL_OWNED_BY_HOST;
54bc3a0d
LB		 1079}
1080
89a91f4f 1081static void mwl8k_rxd_sta_refill(void *_rxd, dma_addr_t addr, int len)
54bc3a0d 1082{
89a91f4f 1083 struct mwl8k_rxd_sta *rxd = _rxd;
54bc3a0d
LB		 1084
1085 rxd->pkt_len = cpu_to_le16(len);
1086 rxd->pkt_phys_addr = cpu_to_le32(addr);
1087 wmb();
1088 rxd->rx_ctrl = 0;
1089}
1090
1091static int
89a91f4f 1092mwl8k_rxd_sta_process(void *_rxd, struct ieee80211_rx_status *status,
0d462bbb 1093 __le16 *qos, s8 *noise)
54bc3a0d 1094{
89a91f4f 1095 struct mwl8k_rxd_sta *rxd = _rxd;
54bc3a0d
LB		 1096 u16 rate_info;
1097
89a91f4f 1098 if (!(rxd->rx_ctrl & MWL8K_STA_RX_CTRL_OWNED_BY_HOST))
54bc3a0d
LB		 1099 return -1;
1100 rmb();
1101
1102 rate_info = le16_to_cpu(rxd->rate_info);
1103
1104 memset(status, 0, sizeof(*status));
1105
1106 status->signal = -rxd->rssi;
0d462bbb 1107 *noise = -rxd->noise_level;
89a91f4f
LB		 1108 status->antenna = MWL8K_STA_RATE_INFO_ANTSELECT(rate_info);
1109 status->rate_idx = MWL8K_STA_RATE_INFO_RATEID(rate_info);
54bc3a0d 1110
89a91f4f 1111 if (rate_info & MWL8K_STA_RATE_INFO_SHORTPRE)
54bc3a0d 1112 status->flag |= RX_FLAG_SHORTPRE;
89a91f4f 1113 if (rate_info & MWL8K_STA_RATE_INFO_40MHZ)
54bc3a0d 1114 status->flag |= RX_FLAG_40MHZ;
89a91f4f 1115 if (rate_info & MWL8K_STA_RATE_INFO_SHORTGI)
54bc3a0d 1116 status->flag |= RX_FLAG_SHORT_GI;
89a91f4f 1117 if (rate_info & MWL8K_STA_RATE_INFO_MCS_FORMAT)
54bc3a0d
LB		 1118 status->flag |= RX_FLAG_HT;
1119
85478344
LB		 1120 if (rxd->channel > 14) {
1121 status->band = IEEE80211_BAND_5GHZ;
1122 if (!(status->flag & RX_FLAG_HT))
1123 status->rate_idx -= 5;
1124 } else {
1125 status->band = IEEE80211_BAND_2GHZ;
1126 }
59eb21a6
BR		 1127 status->freq = ieee80211_channel_to_frequency(rxd->channel,
1128 status->band);
54bc3a0d 1129
20f09c3d 1130 *qos = rxd->qos_control;
d9a07d49
NS		 1131 if ((rxd->rx_ctrl & MWL8K_STA_RX_CTRL_DECRYPT_ERROR) &&
1132 (rxd->rx_ctrl & MWL8K_STA_RX_CTRL_DEC_ERR_TYPE))
1133 status->flag |= RX_FLAG_MMIC_ERROR;
20f09c3d 1134
54bc3a0d
LB		 1135 return le16_to_cpu(rxd->pkt_len);
1136}
1137
89a91f4f
LB		 1138static struct rxd_ops rxd_sta_ops = {
1139 .rxd_size = sizeof(struct mwl8k_rxd_sta),
1140 .rxd_init = mwl8k_rxd_sta_init,
1141 .rxd_refill = mwl8k_rxd_sta_refill,
1142 .rxd_process = mwl8k_rxd_sta_process,
54bc3a0d
LB		 1143};
1144
1145
a66098da
LB		 1146#define MWL8K_RX_DESCS 256
1147#define MWL8K_RX_MAXSZ 3800
1148
1149static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
1150{
1151 struct mwl8k_priv *priv = hw->priv;
1152 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1153 int size;
1154 int i;
1155
45eb400d
LB		 1156 rxq->rxd_count = 0;
1157 rxq->head = 0;
1158 rxq->tail = 0;
a66098da 1159
54bc3a0d 1160 size = MWL8K_RX_DESCS * priv->rxd_ops->rxd_size;
a66098da 1161
45eb400d
LB		 1162 rxq->rxd = pci_alloc_consistent(priv->pdev, size, &rxq->rxd_dma);
1163 if (rxq->rxd == NULL) {
5db55844 1164 wiphy_err(hw->wiphy, "failed to alloc RX descriptors\n");
a66098da
LB		 1165 return -ENOMEM;
1166 }
45eb400d 1167 memset(rxq->rxd, 0, size);
a66098da 1168
b9ede5f1 1169 rxq->buf = kcalloc(MWL8K_RX_DESCS, sizeof(*rxq->buf), GFP_KERNEL);
788838eb 1170 if (rxq->buf == NULL) {
45eb400d 1171 pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma);
a66098da
LB		 1172 return -ENOMEM;
1173 }
a66098da
LB		 1174
1175 for (i = 0; i < MWL8K_RX_DESCS; i++) {
54bc3a0d
LB		 1176 int desc_size;
1177 void *rxd;
a66098da 1178 int nexti;
54bc3a0d
LB		 1179 dma_addr_t next_dma_addr;
1180
1181 desc_size = priv->rxd_ops->rxd_size;
1182 rxd = rxq->rxd + (i * priv->rxd_ops->rxd_size);
a66098da 1183
54bc3a0d
LB		 1184 nexti = i + 1;
1185 if (nexti == MWL8K_RX_DESCS)
1186 nexti = 0;
1187 next_dma_addr = rxq->rxd_dma + (nexti * desc_size);
a66098da 1188
54bc3a0d 1189 priv->rxd_ops->rxd_init(rxd, next_dma_addr);
a66098da
LB		 1190 }
1191
1192 return 0;
1193}
1194
1195static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
1196{
1197 struct mwl8k_priv *priv = hw->priv;
1198 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1199 int refilled;
1200
1201 refilled = 0;
45eb400d 1202 while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) {
a66098da 1203 struct sk_buff *skb;
788838eb 1204 dma_addr_t addr;
a66098da 1205 int rx;
54bc3a0d 1206 void *rxd;
a66098da
LB		 1207
1208 skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
1209 if (skb == NULL)
1210 break;
1211
788838eb
LB		 1212 addr = pci_map_single(priv->pdev, skb->data,
1213 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE);
a66098da 1214
54bc3a0d
LB		 1215 rxq->rxd_count++;
1216 rx = rxq->tail++;
1217 if (rxq->tail == MWL8K_RX_DESCS)
1218 rxq->tail = 0;
788838eb 1219 rxq->buf[rx].skb = skb;
53b1b3e1 1220 dma_unmap_addr_set(&rxq->buf[rx], dma, addr);
54bc3a0d
LB		 1221
1222 rxd = rxq->rxd + (rx * priv->rxd_ops->rxd_size);
1223 priv->rxd_ops->rxd_refill(rxd, addr, MWL8K_RX_MAXSZ);
a66098da
LB		 1224
1225 refilled++;
1226 }
1227
1228 return refilled;
1229}
1230
1231/* Must be called only when the card's reception is completely halted */
1232static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
1233{
1234 struct mwl8k_priv *priv = hw->priv;
1235 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1236 int i;
1237
73b46320
BC		 1238 if (rxq->rxd == NULL)
1239 return;
1240
a66098da 1241 for (i = 0; i < MWL8K_RX_DESCS; i++) {
788838eb
LB		 1242 if (rxq->buf[i].skb != NULL) {
1243 pci_unmap_single(priv->pdev,
53b1b3e1 1244 dma_unmap_addr(&rxq->buf[i], dma),
788838eb 1245 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
53b1b3e1 1246 dma_unmap_addr_set(&rxq->buf[i], dma, 0);
788838eb
LB		 1247
1248 kfree_skb(rxq->buf[i].skb);
1249 rxq->buf[i].skb = NULL;
a66098da
LB		 1250 }
1251 }
1252
788838eb
LB		 1253 kfree(rxq->buf);
1254 rxq->buf = NULL;
a66098da
LB		 1255
1256 pci_free_consistent(priv->pdev,
54bc3a0d 1257 MWL8K_RX_DESCS * priv->rxd_ops->rxd_size,
45eb400d
LB		 1258 rxq->rxd, rxq->rxd_dma);
1259 rxq->rxd = NULL;
a66098da
LB		 1260}
1261
1262
1263/*
1264 * Scan a list of BSSIDs to process for finalize join.
1265 * Allows for extension to process multiple BSSIDs.
1266 */
1267static inline int
1268mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
1269{
1270 return priv->capture_beacon &&
1271 ieee80211_is_beacon(wh->frame_control) &&
3f9a79b5 1272 ether_addr_equal_64bits(wh->addr3, priv->capture_bssid);
a66098da
LB		 1273}
1274
3779752d
LB		 1275static inline void mwl8k_save_beacon(struct ieee80211_hw *hw,
1276 struct sk_buff *skb)
a66098da 1277{
3779752d
LB		 1278 struct mwl8k_priv *priv = hw->priv;
1279
a66098da 1280 priv->capture_beacon = false;
d89173f2 1281 memset(priv->capture_bssid, 0, ETH_ALEN);
a66098da
LB		 1282
1283 /*
1284 * Use GFP_ATOMIC as rxq_process is called from
1285 * the primary interrupt handler, memory allocation call
1286 * must not sleep.
1287 */
1288 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
1289 if (priv->beacon_skb != NULL)
3779752d 1290 ieee80211_queue_work(hw, &priv->finalize_join_worker);
a66098da
LB		 1291}
1292
d9a07d49
NS		 1293static inline struct mwl8k_vif *mwl8k_find_vif_bss(struct list_head *vif_list,
1294 u8 *bssid)
1295{
1296 struct mwl8k_vif *mwl8k_vif;
1297
1298 list_for_each_entry(mwl8k_vif,
1299 vif_list, list) {
1300 if (memcmp(bssid, mwl8k_vif->bssid,
1301 ETH_ALEN) == 0)
1302 return mwl8k_vif;
1303 }
1304
1305 return NULL;
1306}
1307
a66098da
LB		 1308static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
1309{
1310 struct mwl8k_priv *priv = hw->priv;
d9a07d49 1311 struct mwl8k_vif *mwl8k_vif = NULL;
a66098da
LB		 1312 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1313 int processed;
1314
1315 processed = 0;
45eb400d 1316 while (rxq->rxd_count && limit--) {
a66098da 1317 struct sk_buff *skb;
54bc3a0d
LB		 1318 void *rxd;
1319 int pkt_len;
a66098da 1320 struct ieee80211_rx_status status;
d9a07d49 1321 struct ieee80211_hdr *wh;
20f09c3d 1322 __le16 qos;
a66098da 1323
788838eb 1324 skb = rxq->buf[rxq->head].skb;
d25f9f13
LB		 1325 if (skb == NULL)
1326 break;
54bc3a0d
LB		 1327
1328 rxd = rxq->rxd + (rxq->head * priv->rxd_ops->rxd_size);
1329
0d462bbb
JL		 1330 pkt_len = priv->rxd_ops->rxd_process(rxd, &status, &qos,
1331 &priv->noise);
54bc3a0d
LB		 1332 if (pkt_len < 0)
1333 break;
1334
788838eb
LB		 1335 rxq->buf[rxq->head].skb = NULL;
1336
1337 pci_unmap_single(priv->pdev,
53b1b3e1 1338 dma_unmap_addr(&rxq->buf[rxq->head], dma),
788838eb 1339 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
53b1b3e1 1340 dma_unmap_addr_set(&rxq->buf[rxq->head], dma, 0);
a66098da 1341
54bc3a0d
LB		 1342 rxq->head++;
1343 if (rxq->head == MWL8K_RX_DESCS)
1344 rxq->head = 0;
1345
45eb400d 1346 rxq->rxd_count--;
a66098da 1347
d9a07d49 1348 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
a66098da 1349
a66098da 1350 /*
c2c357ce
LB		 1351 * Check for a pending join operation. Save a
1352 * copy of the beacon and schedule a tasklet to
1353 * send a FINALIZE_JOIN command to the firmware.
a66098da 1354 */
54bc3a0d 1355 if (mwl8k_capture_bssid(priv, (void *)skb->data))
3779752d 1356 mwl8k_save_beacon(hw, skb);
a66098da 1357
d9a07d49
NS		 1358 if (ieee80211_has_protected(wh->frame_control)) {
1359
1360 /* Check if hw crypto has been enabled for
1361 * this bss. If yes, set the status flags
1362 * accordingly
1363 */
1364 mwl8k_vif = mwl8k_find_vif_bss(&priv->vif_list,
1365 wh->addr1);
1366
1367 if (mwl8k_vif != NULL &&
23677ce3 1368 mwl8k_vif->is_hw_crypto_enabled) {
d9a07d49
NS		 1369 /*
1370 * When MMIC ERROR is encountered
1371 * by the firmware, payload is
1372 * dropped and only 32 bytes of
1373 * mwl8k Firmware header is sent
1374 * to the host.
1375 *
1376 * We need to add four bytes of
1377 * key information. In it
1378 * MAC80211 expects keyidx set to
1379 * 0 for triggering Counter
1380 * Measure of MMIC failure.
1381 */
1382 if (status.flag & RX_FLAG_MMIC_ERROR) {
1383 struct mwl8k_dma_data *tr;
1384 tr = (struct mwl8k_dma_data *)skb->data;
1385 memset((void *)&(tr->data), 0, 4);
1386 pkt_len += 4;
1387 }
1388
1389 if (!ieee80211_is_auth(wh->frame_control))
1390 status.flag |= RX_FLAG_IV_STRIPPED |
1391 RX_FLAG_DECRYPTED |
1392 RX_FLAG_MMIC_STRIPPED;
1393 }
1394 }
1395
1396 skb_put(skb, pkt_len);
1397 mwl8k_remove_dma_header(skb, qos);
f1d58c25
JB		 1398 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
1399 ieee80211_rx_irqsafe(hw, skb);
a66098da
LB		 1400
1401 processed++;
1402 }
1403
1404 return processed;
1405}
1406
1407
1408/*
1409 * Packet transmission.
1410 */
1411
a66098da
LB		 1412#define MWL8K_TXD_STATUS_OK 0x00000001
1413#define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
1414#define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
1415#define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
a66098da 1416#define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
a66098da 1417
e0493a8d
LB		 1418#define MWL8K_QOS_QLEN_UNSPEC 0xff00
1419#define MWL8K_QOS_ACK_POLICY_MASK 0x0060
1420#define MWL8K_QOS_ACK_POLICY_NORMAL 0x0000
1421#define MWL8K_QOS_ACK_POLICY_BLOCKACK 0x0060
1422#define MWL8K_QOS_EOSP 0x0010
1423
a66098da
LB		 1424struct mwl8k_tx_desc {
1425 __le32 status;
1426 __u8 data_rate;
1427 __u8 tx_priority;
1428 __le16 qos_control;
1429 __le32 pkt_phys_addr;
1430 __le16 pkt_len;
d89173f2 1431 __u8 dest_MAC_addr[ETH_ALEN];
45eb400d 1432 __le32 next_txd_phys_addr;
8a7a578c 1433 __le32 timestamp;
a66098da
LB		 1434 __le16 rate_info;
1435 __u8 peer_id;
a1fe24b0 1436 __u8 tx_frag_cnt;
ba2d3587 1437} __packed;
a66098da
LB		 1438
1439#define MWL8K_TX_DESCS 128
1440
1441static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
1442{
1443 struct mwl8k_priv *priv = hw->priv;
1444 struct mwl8k_tx_queue *txq = priv->txq + index;
1445 int size;
1446 int i;
1447
8ccbc3b8 1448 txq->len = 0;
45eb400d
LB		 1449 txq->head = 0;
1450 txq->tail = 0;
a66098da
LB		 1451
1452 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
1453
45eb400d
LB		 1454 txq->txd = pci_alloc_consistent(priv->pdev, size, &txq->txd_dma);
1455 if (txq->txd == NULL) {
5db55844 1456 wiphy_err(hw->wiphy, "failed to alloc TX descriptors\n");
a66098da
LB		 1457 return -ENOMEM;
1458 }
45eb400d 1459 memset(txq->txd, 0, size);
a66098da 1460
b9ede5f1 1461 txq->skb = kcalloc(MWL8K_TX_DESCS, sizeof(*txq->skb), GFP_KERNEL);
45eb400d 1462 if (txq->skb == NULL) {
45eb400d 1463 pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma);
a66098da
LB		 1464 return -ENOMEM;
1465 }
a66098da
LB		 1466
1467 for (i = 0; i < MWL8K_TX_DESCS; i++) {
1468 struct mwl8k_tx_desc *tx_desc;
1469 int nexti;
1470
45eb400d 1471 tx_desc = txq->txd + i;
a66098da
LB		 1472 nexti = (i + 1) % MWL8K_TX_DESCS;
1473
1474 tx_desc->status = 0;
45eb400d
LB		 1475 tx_desc->next_txd_phys_addr =
1476 cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc));
a66098da
LB		 1477 }
1478
1479 return 0;
1480}
1481
1482static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
1483{
1484 iowrite32(MWL8K_H2A_INT_PPA_READY,
1485 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1486 iowrite32(MWL8K_H2A_INT_DUMMY,
1487 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1488 ioread32(priv->regs + MWL8K_HIU_INT_CODE);
1489}
1490
7e1112d3 1491static void mwl8k_dump_tx_rings(struct ieee80211_hw *hw)
a66098da 1492{
7e1112d3
LB		 1493 struct mwl8k_priv *priv = hw->priv;
1494 int i;
1495
e600707b 1496 for (i = 0; i < mwl8k_tx_queues(priv); i++) {
7e1112d3
LB		 1497 struct mwl8k_tx_queue *txq = priv->txq + i;
1498 int fw_owned = 0;
1499 int drv_owned = 0;
1500 int unused = 0;
1501 int desc;
1502
a66098da 1503 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
7e1112d3
LB		 1504 struct mwl8k_tx_desc *tx_desc = txq->txd + desc;
1505 u32 status;
a66098da 1506
7e1112d3 1507 status = le32_to_cpu(tx_desc->status);
a66098da 1508 if (status & MWL8K_TXD_STATUS_FW_OWNED)
7e1112d3 1509 fw_owned++;
a66098da 1510 else
7e1112d3 1511 drv_owned++;
a66098da
LB		 1512
1513 if (tx_desc->pkt_len == 0)
7e1112d3 1514 unused++;
a66098da 1515 }
a66098da 1516
c96c31e4
JP		 1517 wiphy_err(hw->wiphy,
1518 "txq[%d] len=%d head=%d tail=%d "
1519 "fw_owned=%d drv_owned=%d unused=%d\n",
1520 i,
1521 txq->len, txq->head, txq->tail,
1522 fw_owned, drv_owned, unused);
7e1112d3 1523 }
a66098da
LB		 1524}
1525
618952a7 1526/*
88de754a 1527 * Must be called with priv->fw_mutex held and tx queues stopped.
618952a7 1528 */
62abd3cf 1529#define MWL8K_TX_WAIT_TIMEOUT_MS 5000
7e1112d3 1530
950d5b01 1531static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
a66098da 1532{
a66098da 1533 struct mwl8k_priv *priv = hw->priv;
88de754a 1534 DECLARE_COMPLETION_ONSTACK(tx_wait);
7e1112d3
LB		 1535 int retry;
1536 int rc;
a66098da
LB		 1537
1538 might_sleep();
1539
6b6accc3
YAP		 1540 /* Since fw restart is in progress, allow only the firmware
1541 * commands from the restart code and block the other
1542 * commands since they are going to fail in any case since
1543 * the firmware has crashed
1544 */
1545 if (priv->hw_restart_in_progress) {
1546 if (priv->hw_restart_owner == current)
1547 return 0;
1548 else
1549 return -EBUSY;
1550 }
1551
c27a54d3
YAP		 1552 if (atomic_read(&priv->watchdog_event_pending))
1553 return 0;
1554
7e1112d3
LB		 1555 /*
1556 * The TX queues are stopped at this point, so this test
1557 * doesn't need to take ->tx_lock.
1558 */
1559 if (!priv->pending_tx_pkts)
1560 return 0;
1561
bbf71a8f 1562 retry = 1;
7e1112d3
LB		 1563 rc = 0;
1564
a66098da 1565 spin_lock_bh(&priv->tx_lock);
7e1112d3
LB		 1566 priv->tx_wait = &tx_wait;
1567 while (!rc) {
1568 int oldcount;
1569 unsigned long timeout;
a66098da 1570
7e1112d3 1571 oldcount = priv->pending_tx_pkts;
a66098da 1572
7e1112d3 1573 spin_unlock_bh(&priv->tx_lock);
88de754a 1574 timeout = wait_for_completion_timeout(&tx_wait,
7e1112d3 1575 msecs_to_jiffies(MWL8K_TX_WAIT_TIMEOUT_MS));
c27a54d3
YAP		 1576
1577 if (atomic_read(&priv->watchdog_event_pending)) {
1578 spin_lock_bh(&priv->tx_lock);
1579 priv->tx_wait = NULL;
1580 spin_unlock_bh(&priv->tx_lock);
1581 return 0;
1582 }
1583
a66098da 1584 spin_lock_bh(&priv->tx_lock);
7e1112d3 1585
bbf71a8f 1586 if (timeout || !priv->pending_tx_pkts) {
7e1112d3 1587 WARN_ON(priv->pending_tx_pkts);
ba30c4a5 1588 if (retry)
c96c31e4 1589 wiphy_notice(hw->wiphy, "tx rings drained\n");
7e1112d3
LB		 1590 break;
1591 }
1592
bbf71a8f
NS		 1593 if (retry) {
1594 mwl8k_tx_start(priv);
1595 retry = 0;
1596 continue;
1597 }
1598
7e1112d3 1599 if (priv->pending_tx_pkts < oldcount) {
c96c31e4
JP		 1600 wiphy_notice(hw->wiphy,
1601 "waiting for tx rings to drain (%d -> %d pkts)\n",
1602 oldcount, priv->pending_tx_pkts);
7e1112d3
LB		 1603 retry = 1;
1604 continue;
1605 }
1606
a66098da 1607 priv->tx_wait = NULL;
a66098da 1608
c96c31e4
JP		 1609 wiphy_err(hw->wiphy, "tx rings stuck for %d ms\n",
1610 MWL8K_TX_WAIT_TIMEOUT_MS);
7e1112d3 1611 mwl8k_dump_tx_rings(hw);
6b6accc3
YAP		 1612 priv->hw_restart_in_progress = true;
1613 ieee80211_queue_work(hw, &priv->fw_reload);
7e1112d3
LB		 1614
1615 rc = -ETIMEDOUT;
a66098da 1616 }
9b0b11fb 1617 priv->tx_wait = NULL;
7e1112d3 1618 spin_unlock_bh(&priv->tx_lock);
a66098da 1619
7e1112d3 1620 return rc;
a66098da
LB		 1621}
1622
c23b5a69
LB		 1623#define MWL8K_TXD_SUCCESS(status) \
1624 ((status) & (MWL8K_TXD_STATUS_OK | \
1625 MWL8K_TXD_STATUS_OK_RETRY | \
1626 MWL8K_TXD_STATUS_OK_MORE_RETRY))
a66098da 1627
a0e7c6cf
NS		 1628static int mwl8k_tid_queue_mapping(u8 tid)
1629{
1630 BUG_ON(tid > 7);
1631
1632 switch (tid) {
1633 case 0:
1634 case 3:
1635 return IEEE80211_AC_BE;
a0e7c6cf
NS		 1636 case 1:
1637 case 2:
1638 return IEEE80211_AC_BK;
a0e7c6cf
NS		 1639 case 4:
1640 case 5:
1641 return IEEE80211_AC_VI;
a0e7c6cf
NS		 1642 case 6:
1643 case 7:
1644 return IEEE80211_AC_VO;
a0e7c6cf
NS		 1645 default:
1646 return -1;
a0e7c6cf
NS		 1647 }
1648}
1649
17033543
NS		 1650/* The firmware will fill in the rate information
1651 * for each packet that gets queued in the hardware
49adc5ce 1652 * and these macros will interpret that info.
17033543
NS		 1653 */
1654
49adc5ce
JL		 1655#define RI_FORMAT(a) (a & 0x0001)
1656#define RI_RATE_ID_MCS(a) ((a & 0x01f8) >> 3)
17033543 1657
efb7c49a
LB		 1658static int
1659mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int limit, int force)
a66098da
LB		 1660{
1661 struct mwl8k_priv *priv = hw->priv;
1662 struct mwl8k_tx_queue *txq = priv->txq + index;
efb7c49a 1663 int processed;
a66098da 1664
efb7c49a 1665 processed = 0;
8ccbc3b8 1666 while (txq->len > 0 && limit--) {
a66098da 1667 int tx;
a66098da
LB		 1668 struct mwl8k_tx_desc *tx_desc;
1669 unsigned long addr;
ce9e2e1b 1670 int size;
a66098da
LB		 1671 struct sk_buff *skb;
1672 struct ieee80211_tx_info *info;
1673 u32 status;
17033543
NS		 1674 struct ieee80211_sta *sta;
1675 struct mwl8k_sta *sta_info = NULL;
1676 u16 rate_info;
17033543 1677 struct ieee80211_hdr *wh;
a66098da 1678
45eb400d
LB		 1679 tx = txq->head;
1680 tx_desc = txq->txd + tx;
a66098da
LB		 1681
1682 status = le32_to_cpu(tx_desc->status);
1683
1684 if (status & MWL8K_TXD_STATUS_FW_OWNED) {
1685 if (!force)
1686 break;
1687 tx_desc->status &=
1688 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
1689 }
1690
45eb400d 1691 txq->head = (tx + 1) % MWL8K_TX_DESCS;
8ccbc3b8
KV		 1692 BUG_ON(txq->len == 0);
1693 txq->len--;
a66098da
LB		 1694 priv->pending_tx_pkts--;
1695
1696 addr = le32_to_cpu(tx_desc->pkt_phys_addr);
ce9e2e1b 1697 size = le16_to_cpu(tx_desc->pkt_len);
45eb400d
LB		 1698 skb = txq->skb[tx];
1699 txq->skb[tx] = NULL;
a66098da
LB		 1700
1701 BUG_ON(skb == NULL);
1702 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
1703
20f09c3d 1704 mwl8k_remove_dma_header(skb, tx_desc->qos_control);
a66098da 1705
17033543
NS		 1706 wh = (struct ieee80211_hdr *) skb->data;
1707
a66098da
LB		 1708 /* Mark descriptor as unused */
1709 tx_desc->pkt_phys_addr = 0;
1710 tx_desc->pkt_len = 0;
1711
a66098da 1712 info = IEEE80211_SKB_CB(skb);
17033543 1713 if (ieee80211_is_data(wh->frame_control)) {
89e11801
TH		 1714 rcu_read_lock();
1715 sta = ieee80211_find_sta_by_ifaddr(hw, wh->addr1,
1716 wh->addr2);
17033543
NS		 1717 if (sta) {
1718 sta_info = MWL8K_STA(sta);
1719 BUG_ON(sta_info == NULL);
1720 rate_info = le16_to_cpu(tx_desc->rate_info);
17033543
NS		 1721 /* If rate is < 6.5 Mpbs for an ht station
1722 * do not form an ampdu. If the station is a
1723 * legacy station (format = 0), do not form an
1724 * ampdu
1725 */
49adc5ce
JL		 1726 if (RI_RATE_ID_MCS(rate_info) < 1 ||
1727 RI_FORMAT(rate_info) == 0) {
17033543
NS		 1728 sta_info->is_ampdu_allowed = false;
1729 } else {
1730 sta_info->is_ampdu_allowed = true;
1731 }
1732 }
89e11801 1733 rcu_read_unlock();
17033543
NS		 1734 }
1735
a66098da 1736 ieee80211_tx_info_clear_status(info);
0bf22c37
NS		 1737
1738 /* Rate control is happening in the firmware.
1739 * Ensure no tx rate is being reported.
1740 */
ba30c4a5
YAP		 1741 info->status.rates[0].idx = -1;
1742 info->status.rates[0].count = 1;
0bf22c37 1743
ce9e2e1b 1744 if (MWL8K_TXD_SUCCESS(status))
a66098da 1745 info->flags |= IEEE80211_TX_STAT_ACK;
a66098da
LB		 1746
1747 ieee80211_tx_status_irqsafe(hw, skb);
1748
efb7c49a 1749 processed++;
a66098da
LB		 1750 }
1751
efb7c49a 1752 return processed;
a66098da
LB		 1753}
1754
1755/* must be called only when the card's transmit is completely halted */
1756static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
1757{
1758 struct mwl8k_priv *priv = hw->priv;
1759 struct mwl8k_tx_queue *txq = priv->txq + index;
1760
73b46320
BC		 1761 if (txq->txd == NULL)
1762 return;
1763
efb7c49a 1764 mwl8k_txq_reclaim(hw, index, INT_MAX, 1);
a66098da 1765
45eb400d
LB		 1766 kfree(txq->skb);
1767 txq->skb = NULL;
a66098da
LB		 1768
1769 pci_free_consistent(priv->pdev,
1770 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
45eb400d
LB		 1771 txq->txd, txq->txd_dma);
1772 txq->txd = NULL;
a66098da
LB		 1773}
1774
ac109fd0 1775/* caller must hold priv->stream_lock when calling the stream functions */
ba30c4a5 1776static struct mwl8k_ampdu_stream *
ac109fd0
BC		 1777mwl8k_add_stream(struct ieee80211_hw *hw, struct ieee80211_sta *sta, u8 tid)
1778{
1779 struct mwl8k_ampdu_stream *stream;
1780 struct mwl8k_priv *priv = hw->priv;
1781 int i;
1782
7fb978b7 1783 for (i = 0; i < MWL8K_NUM_AMPDU_STREAMS; i++) {
ac109fd0
BC		 1784 stream = &priv->ampdu[i];
1785 if (stream->state == AMPDU_NO_STREAM) {
1786 stream->sta = sta;
1787 stream->state = AMPDU_STREAM_NEW;
1788 stream->tid = tid;
1789 stream->idx = i;
ac109fd0
BC		 1790 wiphy_debug(hw->wiphy, "Added a new stream for %pM %d",
1791 sta->addr, tid);
1792 return stream;
1793 }
1794 }
1795 return NULL;
1796}
1797
1798static int
1799mwl8k_start_stream(struct ieee80211_hw *hw, struct mwl8k_ampdu_stream *stream)
1800{
1801 int ret;
1802
1803 /* if the stream has already been started, don't start it again */
1804 if (stream->state != AMPDU_STREAM_NEW)
1805 return 0;
1806 ret = ieee80211_start_tx_ba_session(stream->sta, stream->tid, 0);
1807 if (ret)
1808 wiphy_debug(hw->wiphy, "Failed to start stream for %pM %d: "
1809 "%d\n", stream->sta->addr, stream->tid, ret);
1810 else
1811 wiphy_debug(hw->wiphy, "Started stream for %pM %d\n",
1812 stream->sta->addr, stream->tid);
1813 return ret;
1814}
1815
1816static void
1817mwl8k_remove_stream(struct ieee80211_hw *hw, struct mwl8k_ampdu_stream *stream)
1818{
1819 wiphy_debug(hw->wiphy, "Remove stream for %pM %d\n", stream->sta->addr,
1820 stream->tid);
1821 memset(stream, 0, sizeof(*stream));
1822}
1823
1824static struct mwl8k_ampdu_stream *
1825mwl8k_lookup_stream(struct ieee80211_hw *hw, u8 *addr, u8 tid)
1826{
1827 struct mwl8k_priv *priv = hw->priv;
1828 int i;
1829
7fb978b7 1830 for (i = 0; i < MWL8K_NUM_AMPDU_STREAMS; i++) {
ac109fd0
BC		 1831 struct mwl8k_ampdu_stream *stream;
1832 stream = &priv->ampdu[i];
1833 if (stream->state == AMPDU_NO_STREAM)
1834 continue;
1835 if (!memcmp(stream->sta->addr, addr, ETH_ALEN) &&
1836 stream->tid == tid)
1837 return stream;
1838 }
1839 return NULL;
1840}
1841
d0805c1c
BC		 1842#define MWL8K_AMPDU_PACKET_THRESHOLD 64
1843static inline bool mwl8k_ampdu_allowed(struct ieee80211_sta *sta, u8 tid)
1844{
1845 struct mwl8k_sta *sta_info = MWL8K_STA(sta);
1846 struct tx_traffic_info *tx_stats;
1847
1848 BUG_ON(tid >= MWL8K_MAX_TID);
1849 tx_stats = &sta_info->tx_stats[tid];
1850
1851 return sta_info->is_ampdu_allowed &&
1852 tx_stats->pkts > MWL8K_AMPDU_PACKET_THRESHOLD;
1853}
1854
1855static inline void mwl8k_tx_count_packet(struct ieee80211_sta *sta, u8 tid)
1856{
1857 struct mwl8k_sta *sta_info = MWL8K_STA(sta);
1858 struct tx_traffic_info *tx_stats;
1859
1860 BUG_ON(tid >= MWL8K_MAX_TID);
1861 tx_stats = &sta_info->tx_stats[tid];
1862
1863 if (tx_stats->start_time == 0)
1864 tx_stats->start_time = jiffies;
1865
1866 /* reset the packet count after each second elapses. If the number of
1867 * packets ever exceeds the ampdu_min_traffic threshold, we will allow
1868 * an ampdu stream to be started.
1869 */
1870 if (jiffies - tx_stats->start_time > HZ) {
1871 tx_stats->pkts = 0;
1872 tx_stats->start_time = 0;
1873 } else
1874 tx_stats->pkts++;
1875}
1876
7fb978b7
YAP		 1877/* The hardware ampdu queues start from 5.
1878 * txpriorities for ampdu queues are
1879 * 5 6 7 0 1 2 3 4 ie., queue 5 is highest
1880 * and queue 3 is lowest (queue 4 is reserved)
1881 */
1882#define BA_QUEUE 5
1883
7bb45683 1884static void
36323f81
TH		 1885mwl8k_txq_xmit(struct ieee80211_hw *hw,
1886 int index,
1887 struct ieee80211_sta *sta,
1888 struct sk_buff *skb)
a66098da
LB		 1889{
1890 struct mwl8k_priv *priv = hw->priv;
1891 struct ieee80211_tx_info *tx_info;
23b33906 1892 struct mwl8k_vif *mwl8k_vif;
a66098da
LB		 1893 struct ieee80211_hdr *wh;
1894 struct mwl8k_tx_queue *txq;
1895 struct mwl8k_tx_desc *tx;
a66098da 1896 dma_addr_t dma;
23b33906
LB		 1897 u32 txstatus;
1898 u8 txdatarate;
1899 u16 qos;
65f3ddcd
NS		 1900 int txpriority;
1901 u8 tid = 0;
1902 struct mwl8k_ampdu_stream *stream = NULL;
1903 bool start_ba_session = false;
3a769888 1904 bool mgmtframe = false;
a0e7c6cf 1905 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
e1f4d69b 1906 bool eapol_frame = false;
a66098da 1907
23b33906
LB		 1908 wh = (struct ieee80211_hdr *)skb->data;
1909 if (ieee80211_is_data_qos(wh->frame_control))
1910 qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
1911 else
1912 qos = 0;
a66098da 1913
e1f4d69b
NS		 1914 if (skb->protocol == cpu_to_be16(ETH_P_PAE))
1915 eapol_frame = true;
1916
3a769888
NS		 1917 if (ieee80211_is_mgmt(wh->frame_control))
1918 mgmtframe = true;
1919
d9a07d49 1920 if (priv->ap_fw)
ff776cec 1921 mwl8k_encapsulate_tx_frame(priv, skb);
d9a07d49 1922 else
e4eefec7 1923 mwl8k_add_dma_header(priv, skb, 0, 0);
d9a07d49 1924
23b33906 1925 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
a66098da
LB		 1926
1927 tx_info = IEEE80211_SKB_CB(skb);
1928 mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
a66098da
LB		 1929
1930 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
a66098da 1931 wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
657232b6
LB		 1932 wh->seq_ctrl |= cpu_to_le16(mwl8k_vif->seqno);
1933 mwl8k_vif->seqno += 0x10;
a66098da
LB		 1934 }
1935
23b33906
LB		 1936 /* Setup firmware control bit fields for each frame type. */
1937 txstatus = 0;
1938 txdatarate = 0;
1939 if (ieee80211_is_mgmt(wh->frame_control) ||
1940 ieee80211_is_ctl(wh->frame_control)) {
1941 txdatarate = 0;
e0493a8d 1942 qos |= MWL8K_QOS_QLEN_UNSPEC | MWL8K_QOS_EOSP;
23b33906
LB		 1943 } else if (ieee80211_is_data(wh->frame_control)) {
1944 txdatarate = 1;
1945 if (is_multicast_ether_addr(wh->addr1))
1946 txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
1947
e0493a8d 1948 qos &= ~MWL8K_QOS_ACK_POLICY_MASK;
23b33906 1949 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
e0493a8d 1950 qos |= MWL8K_QOS_ACK_POLICY_BLOCKACK;
23b33906 1951 else
e0493a8d 1952 qos |= MWL8K_QOS_ACK_POLICY_NORMAL;
23b33906 1953 }
a66098da 1954
a0e7c6cf
NS		 1955 /* Queue ADDBA request in the respective data queue. While setting up
1956 * the ampdu stream, mac80211 queues further packets for that
1957 * particular ra/tid pair. However, packets piled up in the hardware
1958 * for that ra/tid pair will still go out. ADDBA request and the
1959 * related data packets going out from different queues asynchronously
1960 * will cause a shift in the receiver window which might result in
1961 * ampdu packets getting dropped at the receiver after the stream has
1962 * been setup.
1963 */
1964 if (unlikely(ieee80211_is_action(wh->frame_control) &&
1965 mgmt->u.action.category == WLAN_CATEGORY_BACK &&
1966 mgmt->u.action.u.addba_req.action_code == WLAN_ACTION_ADDBA_REQ &&
1967 priv->ap_fw)) {
1968 u16 capab = le16_to_cpu(mgmt->u.action.u.addba_req.capab);
1969 tid = (capab & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2;
1970 index = mwl8k_tid_queue_mapping(tid);
1971 }
1972
65f3ddcd
NS		 1973 txpriority = index;
1974
e1f4d69b
NS		 1975 if (priv->ap_fw && sta && sta->ht_cap.ht_supported && !eapol_frame &&
1976 ieee80211_is_data_qos(wh->frame_control)) {
65f3ddcd 1977 tid = qos & 0xf;
d0805c1c 1978 mwl8k_tx_count_packet(sta, tid);
65f3ddcd
NS		 1979 spin_lock(&priv->stream_lock);
1980 stream = mwl8k_lookup_stream(hw, sta->addr, tid);
1981 if (stream != NULL) {
1982 if (stream->state == AMPDU_STREAM_ACTIVE) {
5f2a1494 1983 WARN_ON(!(qos & MWL8K_QOS_ACK_POLICY_BLOCKACK));
7fb978b7
YAP		 1984 txpriority = (BA_QUEUE + stream->idx) %
1985 TOTAL_HW_TX_QUEUES;
1986 if (stream->idx <= 1)
1987 index = stream->idx +
1988 MWL8K_TX_WMM_QUEUES;
1989
65f3ddcd
NS		 1990 } else if (stream->state == AMPDU_STREAM_NEW) {
1991 /* We get here if the driver sends us packets
1992 * after we've initiated a stream, but before
1993 * our ampdu_action routine has been called
1994 * with IEEE80211_AMPDU_TX_START to get the SSN
1995 * for the ADDBA request. So this packet can
1996 * go out with no risk of sequence number
1997 * mismatch. No special handling is required.
1998 */
1999 } else {
2000 /* Drop packets that would go out after the
2001 * ADDBA request was sent but before the ADDBA
2002 * response is received. If we don't do this,
2003 * the recipient would probably receive it
2004 * after the ADDBA request with SSN 0. This
2005 * will cause the recipient's BA receive window
2006 * to shift, which would cause the subsequent
2007 * packets in the BA stream to be discarded.
2008 * mac80211 queues our packets for us in this
2009 * case, so this is really just a safety check.
2010 */
2011 wiphy_warn(hw->wiphy,
2012 "Cannot send packet while ADDBA "
2013 "dialog is underway.\n");
2014 spin_unlock(&priv->stream_lock);
2015 dev_kfree_skb(skb);
2016 return;
2017 }
2018 } else {
2019 /* Defer calling mwl8k_start_stream so that the current
2020 * skb can go out before the ADDBA request. This
2021 * prevents sequence number mismatch at the recepient
2022 * as described above.
2023 */
d0805c1c 2024 if (mwl8k_ampdu_allowed(sta, tid)) {
17033543
NS		 2025 stream = mwl8k_add_stream(hw, sta, tid);
2026 if (stream != NULL)
2027 start_ba_session = true;
2028 }
65f3ddcd
NS		 2029 }
2030 spin_unlock(&priv->stream_lock);
5f2a1494
YAP		 2031 } else {
2032 qos &= ~MWL8K_QOS_ACK_POLICY_MASK;
2033 qos |= MWL8K_QOS_ACK_POLICY_NORMAL;
65f3ddcd
NS		 2034 }
2035
a66098da
LB		 2036 dma = pci_map_single(priv->pdev, skb->data,
2037 skb->len, PCI_DMA_TODEVICE);
2038
2039 if (pci_dma_mapping_error(priv->pdev, dma)) {
c96c31e4
JP		 2040 wiphy_debug(hw->wiphy,
2041 "failed to dma map skb, dropping TX frame.\n");
65f3ddcd
NS		 2042 if (start_ba_session) {
2043 spin_lock(&priv->stream_lock);
2044 mwl8k_remove_stream(hw, stream);
2045 spin_unlock(&priv->stream_lock);
2046 }
23b33906 2047 dev_kfree_skb(skb);
7bb45683 2048 return;
a66098da
LB		 2049 }
2050
23b33906 2051 spin_lock_bh(&priv->tx_lock);
a66098da 2052
23b33906 2053 txq = priv->txq + index;
a66098da 2054
3a769888
NS		 2055 /* Mgmt frames that go out frequently are probe
2056 * responses. Other mgmt frames got out relatively
2057 * infrequently. Hence reserve 2 buffers so that
2058 * other mgmt frames do not get dropped due to an
2059 * already queued probe response in one of the
2060 * reserved buffers.
2061 */
2062
2063 if (txq->len >= MWL8K_TX_DESCS - 2) {
23677ce3 2064 if (!mgmtframe || txq->len == MWL8K_TX_DESCS) {
3a769888
NS		 2065 if (start_ba_session) {
2066 spin_lock(&priv->stream_lock);
2067 mwl8k_remove_stream(hw, stream);
2068 spin_unlock(&priv->stream_lock);
2069 }
bbf71a8f 2070 mwl8k_tx_start(priv);
3a769888 2071 spin_unlock_bh(&priv->tx_lock);
ff7aa96f
NS		 2072 pci_unmap_single(priv->pdev, dma, skb->len,
2073 PCI_DMA_TODEVICE);
3a769888
NS		 2074 dev_kfree_skb(skb);
2075 return;
3a7dbc3b 2076 }
65f3ddcd
NS		 2077 }
2078
45eb400d
LB		 2079 BUG_ON(txq->skb[txq->tail] != NULL);
2080 txq->skb[txq->tail] = skb;
a66098da 2081
45eb400d 2082 tx = txq->txd + txq->tail;
23b33906 2083 tx->data_rate = txdatarate;
65f3ddcd 2084 tx->tx_priority = txpriority;
a66098da 2085 tx->qos_control = cpu_to_le16(qos);
a66098da
LB		 2086 tx->pkt_phys_addr = cpu_to_le32(dma);
2087 tx->pkt_len = cpu_to_le16(skb->len);
23b33906 2088 tx->rate_info = 0;
36323f81
TH		 2089 if (!priv->ap_fw && sta != NULL)
2090 tx->peer_id = MWL8K_STA(sta)->peer_id;
a680400e
LB		 2091 else
2092 tx->peer_id = 0;
566875db 2093
e1f4d69b 2094 if (priv->ap_fw && ieee80211_is_data(wh->frame_control) && !eapol_frame)
566875db
PN		 2095 tx->timestamp = cpu_to_le32(ioread32(priv->regs +
2096 MWL8K_HW_TIMER_REGISTER));
b8d9e572
NS		 2097 else
2098 tx->timestamp = 0;
566875db 2099
a66098da 2100 wmb();
23b33906
LB		 2101 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus);
2102
8ccbc3b8 2103 txq->len++;
a66098da 2104 priv->pending_tx_pkts++;
a66098da 2105
45eb400d
LB		 2106 txq->tail++;
2107 if (txq->tail == MWL8K_TX_DESCS)
2108 txq->tail = 0;
23b33906 2109
23b33906 2110 mwl8k_tx_start(priv);
a66098da
LB		 2111
2112 spin_unlock_bh(&priv->tx_lock);
65f3ddcd
NS		 2113
2114 /* Initiate the ampdu session here */
2115 if (start_ba_session) {
2116 spin_lock(&priv->stream_lock);
2117 if (mwl8k_start_stream(hw, stream))
2118 mwl8k_remove_stream(hw, stream);
2119 spin_unlock(&priv->stream_lock);
2120 }
a66098da
LB		 2121}
2122
2123
618952a7
LB		 2124/*
2125 * Firmware access.
2126 *
2127 * We have the following requirements for issuing firmware commands:
2128 * - Some commands require that the packet transmit path is idle when
2129 * the command is issued. (For simplicity, we'll just quiesce the
2130 * transmit path for every command.)
2131 * - There are certain sequences of commands that need to be issued to
2132 * the hardware sequentially, with no other intervening commands.
2133 *
2134 * This leads to an implementation of a "firmware lock" as a mutex that
2135 * can be taken recursively, and which is taken by both the low-level
2136 * command submission function (mwl8k_post_cmd) as well as any users of
2137 * that function that require issuing of an atomic sequence of commands,
2138 * and quiesces the transmit path whenever it's taken.
2139 */
2140static int mwl8k_fw_lock(struct ieee80211_hw *hw)
2141{
2142 struct mwl8k_priv *priv = hw->priv;
2143
2144 if (priv->fw_mutex_owner != current) {
2145 int rc;
2146
2147 mutex_lock(&priv->fw_mutex);
2148 ieee80211_stop_queues(hw);
2149
2150 rc = mwl8k_tx_wait_empty(hw);
2151 if (rc) {
6b6accc3
YAP		 2152 if (!priv->hw_restart_in_progress)
2153 ieee80211_wake_queues(hw);
2154
618952a7
LB		 2155 mutex_unlock(&priv->fw_mutex);
2156
2157 return rc;
2158 }
2159
2160 priv->fw_mutex_owner = current;
2161 }
2162
2163 priv->fw_mutex_depth++;
2164
2165 return 0;
2166}
2167
2168static void mwl8k_fw_unlock(struct ieee80211_hw *hw)
2169{
2170 struct mwl8k_priv *priv = hw->priv;
2171
2172 if (!--priv->fw_mutex_depth) {
6b6accc3
YAP		 2173 if (!priv->hw_restart_in_progress)
2174 ieee80211_wake_queues(hw);
2175
618952a7
LB		 2176 priv->fw_mutex_owner = NULL;
2177 mutex_unlock(&priv->fw_mutex);
2178 }
2179}
2180
e882efc9
YAP		 2181static void mwl8k_enable_bsses(struct ieee80211_hw *hw, bool enable,
2182 u32 bitmap);
618952a7 2183
a66098da
LB		 2184/*
2185 * Command processing.
2186 */
2187
0c9cc640
LB		 2188/* Timeout firmware commands after 10s */
2189#define MWL8K_CMD_TIMEOUT_MS 10000
a66098da
LB		 2190
2191static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
2192{
2193 DECLARE_COMPLETION_ONSTACK(cmd_wait);
2194 struct mwl8k_priv *priv = hw->priv;
2195 void __iomem *regs = priv->regs;
2196 dma_addr_t dma_addr;
2197 unsigned int dma_size;
2198 int rc;
a66098da
LB		 2199 unsigned long timeout = 0;
2200 u8 buf[32];
e882efc9
YAP		 2201 u32 bitmap = 0;
2202
2203 wiphy_dbg(hw->wiphy, "Posting %s [%d]\n",
2204 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)), cmd->macid);
2205
2206 /* Before posting firmware commands that could change the hardware
2207 * characteristics, make sure that all BSSes are stopped temporary.
2208 * Enable these stopped BSSes after completion of the commands
2209 */
2210
2211 rc = mwl8k_fw_lock(hw);
2212 if (rc)
2213 return rc;
2214
2215 if (priv->ap_fw && priv->running_bsses) {
2216 switch (le16_to_cpu(cmd->code)) {
2217 case MWL8K_CMD_SET_RF_CHANNEL:
2218 case MWL8K_CMD_RADIO_CONTROL:
2219 case MWL8K_CMD_RF_TX_POWER:
2220 case MWL8K_CMD_TX_POWER:
2221 case MWL8K_CMD_RF_ANTENNA:
2222 case MWL8K_CMD_RTS_THRESHOLD:
2223 case MWL8K_CMD_MIMO_CONFIG:
2224 bitmap = priv->running_bsses;
2225 mwl8k_enable_bsses(hw, false, bitmap);
2226 break;
2227 }
2228 }
a66098da 2229
b603742f 2230 cmd->result = (__force __le16) 0xffff;
a66098da
LB		 2231 dma_size = le16_to_cpu(cmd->length);
2232 dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
2233 PCI_DMA_BIDIRECTIONAL);
2234 if (pci_dma_mapping_error(priv->pdev, dma_addr))
2235 return -ENOMEM;
2236
a66098da
LB		 2237 priv->hostcmd_wait = &cmd_wait;
2238 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
2239 iowrite32(MWL8K_H2A_INT_DOORBELL,
2240 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
2241 iowrite32(MWL8K_H2A_INT_DUMMY,
2242 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
a66098da
LB		 2243
2244 timeout = wait_for_completion_timeout(&cmd_wait,
2245 msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
2246
618952a7
LB		 2247 priv->hostcmd_wait = NULL;
2248
618952a7 2249
37055bd4
LB		 2250 pci_unmap_single(priv->pdev, dma_addr, dma_size,
2251 PCI_DMA_BIDIRECTIONAL);
2252
a66098da 2253 if (!timeout) {
5db55844 2254 wiphy_err(hw->wiphy, "Command %s timeout after %u ms\n",
c96c31e4
JP		 2255 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
2256 MWL8K_CMD_TIMEOUT_MS);
a66098da
LB		 2257 rc = -ETIMEDOUT;
2258 } else {
0c9cc640
LB		 2259 int ms;
2260
2261 ms = MWL8K_CMD_TIMEOUT_MS - jiffies_to_msecs(timeout);
2262
ce9e2e1b 2263 rc = cmd->result ? -EINVAL : 0;
a66098da 2264 if (rc)
5db55844 2265 wiphy_err(hw->wiphy, "Command %s error 0x%x\n",
c96c31e4
JP		 2266 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
2267 le16_to_cpu(cmd->result));
0c9cc640 2268 else if (ms > 2000)
5db55844 2269 wiphy_notice(hw->wiphy, "Command %s took %d ms\n",
c96c31e4
JP		 2270 mwl8k_cmd_name(cmd->code,
2271 buf, sizeof(buf)),
2272 ms);
a66098da
LB		 2273 }
2274
e882efc9
YAP		 2275 if (bitmap)
2276 mwl8k_enable_bsses(hw, true, bitmap);
2277
2278 mwl8k_fw_unlock(hw);
2279
a66098da
LB		 2280 return rc;
2281}
2282
f57ca9c1
LB		 2283static int mwl8k_post_pervif_cmd(struct ieee80211_hw *hw,
2284 struct ieee80211_vif *vif,
2285 struct mwl8k_cmd_pkt *cmd)
2286{
2287 if (vif != NULL)
2288 cmd->macid = MWL8K_VIF(vif)->macid;
2289 return mwl8k_post_cmd(hw, cmd);
2290}
2291
1349ad2f
LB		 2292/*
2293 * Setup code shared between STA and AP firmware images.
2294 */
2295static void mwl8k_setup_2ghz_band(struct ieee80211_hw *hw)
2296{
2297 struct mwl8k_priv *priv = hw->priv;
2298
2299 BUILD_BUG_ON(sizeof(priv->channels_24) != sizeof(mwl8k_channels_24));
2300 memcpy(priv->channels_24, mwl8k_channels_24, sizeof(mwl8k_channels_24));
2301
2302 BUILD_BUG_ON(sizeof(priv->rates_24) != sizeof(mwl8k_rates_24));
2303 memcpy(priv->rates_24, mwl8k_rates_24, sizeof(mwl8k_rates_24));
2304
2305 priv->band_24.band = IEEE80211_BAND_2GHZ;
2306 priv->band_24.channels = priv->channels_24;
2307 priv->band_24.n_channels = ARRAY_SIZE(mwl8k_channels_24);
2308 priv->band_24.bitrates = priv->rates_24;
2309 priv->band_24.n_bitrates = ARRAY_SIZE(mwl8k_rates_24);
2310
2311 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band_24;
2312}
2313
4eae9edd
LB		 2314static void mwl8k_setup_5ghz_band(struct ieee80211_hw *hw)
2315{
2316 struct mwl8k_priv *priv = hw->priv;
2317
2318 BUILD_BUG_ON(sizeof(priv->channels_50) != sizeof(mwl8k_channels_50));
2319 memcpy(priv->channels_50, mwl8k_channels_50, sizeof(mwl8k_channels_50));
2320
2321 BUILD_BUG_ON(sizeof(priv->rates_50) != sizeof(mwl8k_rates_50));
2322 memcpy(priv->rates_50, mwl8k_rates_50, sizeof(mwl8k_rates_50));
2323
2324 priv->band_50.band = IEEE80211_BAND_5GHZ;
2325 priv->band_50.channels = priv->channels_50;
2326 priv->band_50.n_channels = ARRAY_SIZE(mwl8k_channels_50);
2327 priv->band_50.bitrates = priv->rates_50;
2328 priv->band_50.n_bitrates = ARRAY_SIZE(mwl8k_rates_50);
2329
2330 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &priv->band_50;
2331}
2332
a66098da 2333/*
04b147b1 2334 * CMD_GET_HW_SPEC (STA version).
a66098da 2335 */
04b147b1 2336struct mwl8k_cmd_get_hw_spec_sta {
a66098da
LB		 2337 struct mwl8k_cmd_pkt header;
2338 __u8 hw_rev;
2339 __u8 host_interface;
2340 __le16 num_mcaddrs;
d89173f2 2341 __u8 perm_addr[ETH_ALEN];
a66098da
LB		 2342 __le16 region_code;
2343 __le32 fw_rev;
2344 __le32 ps_cookie;
2345 __le32 caps;
2346 __u8 mcs_bitmap[16];
2347 __le32 rx_queue_ptr;
2348 __le32 num_tx_queues;
e600707b 2349 __le32 tx_queue_ptrs[MWL8K_TX_WMM_QUEUES];
a66098da
LB		 2350 __le32 caps2;
2351 __le32 num_tx_desc_per_queue;
45eb400d 2352 __le32 total_rxd;
ba2d3587 2353} __packed;
a66098da 2354
341c9791
LB		 2355#define MWL8K_CAP_MAX_AMSDU 0x20000000
2356#define MWL8K_CAP_GREENFIELD 0x08000000
2357#define MWL8K_CAP_AMPDU 0x04000000
2358#define MWL8K_CAP_RX_STBC 0x01000000
2359#define MWL8K_CAP_TX_STBC 0x00800000
2360#define MWL8K_CAP_SHORTGI_40MHZ 0x00400000
2361#define MWL8K_CAP_SHORTGI_20MHZ 0x00200000
2362#define MWL8K_CAP_RX_ANTENNA_MASK 0x000e0000
2363#define MWL8K_CAP_TX_ANTENNA_MASK 0x0001c000
2364#define MWL8K_CAP_DELAY_BA 0x00003000
2365#define MWL8K_CAP_MIMO 0x00000200
2366#define MWL8K_CAP_40MHZ 0x00000100
06953235
LB		 2367#define MWL8K_CAP_BAND_MASK 0x00000007
2368#define MWL8K_CAP_5GHZ 0x00000004
2369#define MWL8K_CAP_2GHZ4 0x00000001
341c9791 2370
06953235
LB		 2371static void
2372mwl8k_set_ht_caps(struct ieee80211_hw *hw,
2373 struct ieee80211_supported_band *band, u32 cap)
341c9791 2374{
341c9791
LB		 2375 int rx_streams;
2376 int tx_streams;
2377
777ad375 2378 band->ht_cap.ht_supported = 1;
341c9791
LB		 2379
2380 if (cap & MWL8K_CAP_MAX_AMSDU)
777ad375 2381 band->ht_cap.cap |= IEEE80211_HT_CAP_MAX_AMSDU;
341c9791 2382 if (cap & MWL8K_CAP_GREENFIELD)
777ad375 2383 band->ht_cap.cap |= IEEE80211_HT_CAP_GRN_FLD;
341c9791
LB		 2384 if (cap & MWL8K_CAP_AMPDU) {
2385 hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION;
777ad375
LB		 2386 band->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
2387 band->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_NONE;
341c9791
LB		 2388 }
2389 if (cap & MWL8K_CAP_RX_STBC)
777ad375 2390 band->ht_cap.cap |= IEEE80211_HT_CAP_RX_STBC;
341c9791 2391 if (cap & MWL8K_CAP_TX_STBC)
777ad375 2392 band->ht_cap.cap |= IEEE80211_HT_CAP_TX_STBC;
341c9791 2393 if (cap & MWL8K_CAP_SHORTGI_40MHZ)
777ad375 2394 band->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
341c9791 2395 if (cap & MWL8K_CAP_SHORTGI_20MHZ)
777ad375 2396 band->ht_cap.cap |= IEEE80211_HT_CAP_SGI_20;
341c9791 2397 if (cap & MWL8K_CAP_DELAY_BA)
777ad375 2398 band->ht_cap.cap |= IEEE80211_HT_CAP_DELAY_BA;
341c9791 2399 if (cap & MWL8K_CAP_40MHZ)
777ad375 2400 band->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
341c9791
LB		 2401
2402 rx_streams = hweight32(cap & MWL8K_CAP_RX_ANTENNA_MASK);
2403 tx_streams = hweight32(cap & MWL8K_CAP_TX_ANTENNA_MASK);
2404
777ad375 2405 band->ht_cap.mcs.rx_mask[0] = 0xff;
341c9791 2406 if (rx_streams >= 2)
777ad375 2407 band->ht_cap.mcs.rx_mask[1] = 0xff;
341c9791 2408 if (rx_streams >= 3)
777ad375
LB		 2409 band->ht_cap.mcs.rx_mask[2] = 0xff;
2410 band->ht_cap.mcs.rx_mask[4] = 0x01;
2411 band->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
341c9791
LB		 2412
2413 if (rx_streams != tx_streams) {
777ad375
LB		 2414 band->ht_cap.mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
2415 band->ht_cap.mcs.tx_params |= (tx_streams - 1) <<
341c9791
LB		 2416 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
2417 }
2418}
2419
06953235
LB		 2420static void
2421mwl8k_set_caps(struct ieee80211_hw *hw, u32 caps)
2422{
2423 struct mwl8k_priv *priv = hw->priv;
2424
c3f251a3
JG		 2425 if (priv->caps)
2426 return;
2427
06953235
LB		 2428 if ((caps & MWL8K_CAP_2GHZ4) || !(caps & MWL8K_CAP_BAND_MASK)) {
2429 mwl8k_setup_2ghz_band(hw);
2430 if (caps & MWL8K_CAP_MIMO)
2431 mwl8k_set_ht_caps(hw, &priv->band_24, caps);
2432 }
2433
2434 if (caps & MWL8K_CAP_5GHZ) {
2435 mwl8k_setup_5ghz_band(hw);
2436 if (caps & MWL8K_CAP_MIMO)
2437 mwl8k_set_ht_caps(hw, &priv->band_50, caps);
2438 }
c3f251a3
JG		 2439
2440 priv->caps = caps;
06953235
LB		 2441}
2442
04b147b1 2443static int mwl8k_cmd_get_hw_spec_sta(struct ieee80211_hw *hw)
a66098da
LB		 2444{
2445 struct mwl8k_priv *priv = hw->priv;
04b147b1 2446 struct mwl8k_cmd_get_hw_spec_sta *cmd;
a66098da
LB		 2447 int rc;
2448 int i;
2449
2450 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2451 if (cmd == NULL)
2452 return -ENOMEM;
2453
2454 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
2455 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2456
2457 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
2458 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
45eb400d 2459 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
e600707b
BC		 2460 cmd->num_tx_queues = cpu_to_le32(mwl8k_tx_queues(priv));
2461 for (i = 0; i < mwl8k_tx_queues(priv); i++)
45eb400d 2462 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
4ff6432e 2463 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
45eb400d 2464 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
a66098da
LB		 2465
2466 rc = mwl8k_post_cmd(hw, &cmd->header);
2467
2468 if (!rc) {
2469 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
2470 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
4ff6432e 2471 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
a66098da 2472 priv->hw_rev = cmd->hw_rev;
06953235 2473 mwl8k_set_caps(hw, le32_to_cpu(cmd->caps));
ee0ddf18
LB		 2474 priv->ap_macids_supported = 0x00000000;
2475 priv->sta_macids_supported = 0x00000001;
a66098da
LB		 2476 }
2477
2478 kfree(cmd);
2479 return rc;
2480}
2481
42fba21d
LB		 2482/*
2483 * CMD_GET_HW_SPEC (AP version).
2484 */
2485struct mwl8k_cmd_get_hw_spec_ap {
2486 struct mwl8k_cmd_pkt header;
2487 __u8 hw_rev;
2488 __u8 host_interface;
2489 __le16 num_wcb;
2490 __le16 num_mcaddrs;
2491 __u8 perm_addr[ETH_ALEN];
2492 __le16 region_code;
2493 __le16 num_antenna;
2494 __le32 fw_rev;
2495 __le32 wcbbase0;
2496 __le32 rxwrptr;
2497 __le32 rxrdptr;
2498 __le32 ps_cookie;
2499 __le32 wcbbase1;
2500 __le32 wcbbase2;
2501 __le32 wcbbase3;
952a0e96 2502 __le32 fw_api_version;
8a7a578c
BC		 2503 __le32 caps;
2504 __le32 num_of_ampdu_queues;
2505 __le32 wcbbase_ampdu[MWL8K_MAX_AMPDU_QUEUES];
ba2d3587 2506} __packed;
42fba21d
LB		 2507
2508static int mwl8k_cmd_get_hw_spec_ap(struct ieee80211_hw *hw)
2509{
2510 struct mwl8k_priv *priv = hw->priv;
2511 struct mwl8k_cmd_get_hw_spec_ap *cmd;
8a7a578c 2512 int rc, i;
952a0e96 2513 u32 api_version;
42fba21d
LB		 2514
2515 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2516 if (cmd == NULL)
2517 return -ENOMEM;
2518
2519 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
2520 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2521
2522 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
2523 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
2524
2525 rc = mwl8k_post_cmd(hw, &cmd->header);
2526
2527 if (!rc) {
2528 int off;
2529
952a0e96
BC		 2530 api_version = le32_to_cpu(cmd->fw_api_version);
2531 if (priv->device_info->fw_api_ap != api_version) {
2532 printk(KERN_ERR "%s: Unsupported fw API version for %s."
2533 " Expected %d got %d.\n", MWL8K_NAME,
2534 priv->device_info->part_name,
2535 priv->device_info->fw_api_ap,
2536 api_version);
2537 rc = -EINVAL;
2538 goto done;
2539 }
42fba21d
LB		 2540 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
2541 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
2542 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
2543 priv->hw_rev = cmd->hw_rev;
8a7a578c 2544 mwl8k_set_caps(hw, le32_to_cpu(cmd->caps));
ee0ddf18 2545 priv->ap_macids_supported = 0x000000ff;
d59c1cfd 2546 priv->sta_macids_supported = 0x00000100;
8a7a578c
BC		 2547 priv->num_ampdu_queues = le32_to_cpu(cmd->num_of_ampdu_queues);
2548 if (priv->num_ampdu_queues > MWL8K_MAX_AMPDU_QUEUES) {
2549 wiphy_warn(hw->wiphy, "fw reported %d ampdu queues"
2550 " but we only support %d.\n",
2551 priv->num_ampdu_queues,
2552 MWL8K_MAX_AMPDU_QUEUES);
2553 priv->num_ampdu_queues = MWL8K_MAX_AMPDU_QUEUES;
2554 }
42fba21d 2555 off = le32_to_cpu(cmd->rxwrptr) & 0xffff;
b603742f 2556 iowrite32(priv->rxq[0].rxd_dma, priv->sram + off);
42fba21d
LB		 2557
2558 off = le32_to_cpu(cmd->rxrdptr) & 0xffff;
b603742f 2559 iowrite32(priv->rxq[0].rxd_dma, priv->sram + off);
42fba21d 2560
73b46320
BC		 2561 priv->txq_offset[0] = le32_to_cpu(cmd->wcbbase0) & 0xffff;
2562 priv->txq_offset[1] = le32_to_cpu(cmd->wcbbase1) & 0xffff;
2563 priv->txq_offset[2] = le32_to_cpu(cmd->wcbbase2) & 0xffff;
2564 priv->txq_offset[3] = le32_to_cpu(cmd->wcbbase3) & 0xffff;
8a7a578c
BC		 2565
2566 for (i = 0; i < priv->num_ampdu_queues; i++)
e600707b 2567 priv->txq_offset[i + MWL8K_TX_WMM_QUEUES] =
8a7a578c 2568 le32_to_cpu(cmd->wcbbase_ampdu[i]) & 0xffff;
42fba21d
LB		 2569 }
2570
952a0e96 2571done:
42fba21d
LB		 2572 kfree(cmd);
2573 return rc;
2574}
2575
2576/*
2577 * CMD_SET_HW_SPEC.
2578 */
2579struct mwl8k_cmd_set_hw_spec {
2580 struct mwl8k_cmd_pkt header;
2581 __u8 hw_rev;
2582 __u8 host_interface;
2583 __le16 num_mcaddrs;
2584 __u8 perm_addr[ETH_ALEN];
2585 __le16 region_code;
2586 __le32 fw_rev;
2587 __le32 ps_cookie;
2588 __le32 caps;
2589 __le32 rx_queue_ptr;
2590 __le32 num_tx_queues;
e600707b 2591 __le32 tx_queue_ptrs[MWL8K_MAX_TX_QUEUES];
42fba21d
LB		 2592 __le32 flags;
2593 __le32 num_tx_desc_per_queue;
2594 __le32 total_rxd;
ba2d3587 2595} __packed;
42fba21d 2596
8a7a578c
BC		 2597/* If enabled, MWL8K_SET_HW_SPEC_FLAG_ENABLE_LIFE_TIME_EXPIRY will cause
2598 * packets to expire 500 ms after the timestamp in the tx descriptor. That is,
2599 * the packets that are queued for more than 500ms, will be dropped in the
2600 * hardware. This helps minimizing the issues caused due to head-of-line
2601 * blocking where a slow client can hog the bandwidth and affect traffic to a
2602 * faster client.
2603 */
2604#define MWL8K_SET_HW_SPEC_FLAG_ENABLE_LIFE_TIME_EXPIRY 0x00000400
3373b28e 2605#define MWL8K_SET_HW_SPEC_FLAG_GENERATE_CCMP_HDR 0x00000200
b64fe619
LB		 2606#define MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT 0x00000080
2607#define MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_PROBERESP 0x00000020
2608#define MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_BEACON 0x00000010
42fba21d
LB		 2609
2610static int mwl8k_cmd_set_hw_spec(struct ieee80211_hw *hw)
2611{
2612 struct mwl8k_priv *priv = hw->priv;
2613 struct mwl8k_cmd_set_hw_spec *cmd;
2614 int rc;
2615 int i;
2616
2617 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2618 if (cmd == NULL)
2619 return -ENOMEM;
2620
2621 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_HW_SPEC);
2622 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2623
2624 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
2625 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
e600707b 2626 cmd->num_tx_queues = cpu_to_le32(mwl8k_tx_queues(priv));
85c9205c
NS		 2627
2628 /*
2629 * Mac80211 stack has Q0 as highest priority and Q3 as lowest in
2630 * that order. Firmware has Q3 as highest priority and Q0 as lowest
2631 * in that order. Map Q3 of mac80211 to Q0 of firmware so that the
2632 * priority is interpreted the right way in firmware.
2633 */
e600707b
BC		 2634 for (i = 0; i < mwl8k_tx_queues(priv); i++) {
2635 int j = mwl8k_tx_queues(priv) - 1 - i;
85c9205c
NS		 2636 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[j].txd_dma);
2637 }
2638
b64fe619
LB		 2639 cmd->flags = cpu_to_le32(MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT |
2640 MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_PROBERESP |
31d291a7 2641 MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_BEACON |
3373b28e
NS		 2642 MWL8K_SET_HW_SPEC_FLAG_ENABLE_LIFE_TIME_EXPIRY |
2643 MWL8K_SET_HW_SPEC_FLAG_GENERATE_CCMP_HDR);
42fba21d
LB		 2644 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
2645 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
2646
2647 rc = mwl8k_post_cmd(hw, &cmd->header);
2648 kfree(cmd);
2649
2650 return rc;
2651}
2652
a66098da
LB		 2653/*
2654 * CMD_MAC_MULTICAST_ADR.
2655 */
2656struct mwl8k_cmd_mac_multicast_adr {
2657 struct mwl8k_cmd_pkt header;
2658 __le16 action;
2659 __le16 numaddr;
ce9e2e1b 2660 __u8 addr[0][ETH_ALEN];
a66098da
LB		 2661};
2662
d5e30845
LB		 2663#define MWL8K_ENABLE_RX_DIRECTED 0x0001
2664#define MWL8K_ENABLE_RX_MULTICAST 0x0002
2665#define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004
2666#define MWL8K_ENABLE_RX_BROADCAST 0x0008
ce9e2e1b 2667
e81cd2d6 2668static struct mwl8k_cmd_pkt *
447ced07 2669__mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti,
22bedad3 2670 struct netdev_hw_addr_list *mc_list)
a66098da 2671{
e81cd2d6 2672 struct mwl8k_priv *priv = hw->priv;
a66098da 2673 struct mwl8k_cmd_mac_multicast_adr *cmd;
e81cd2d6 2674 int size;
22bedad3
JP		 2675 int mc_count = 0;
2676
2677 if (mc_list)
2678 mc_count = netdev_hw_addr_list_count(mc_list);
e81cd2d6 2679
447ced07 2680 if (allmulti || mc_count > priv->num_mcaddrs) {
d5e30845
LB		 2681 allmulti = 1;
2682 mc_count = 0;
2683 }
e81cd2d6
LB		 2684
2685 size = sizeof(*cmd) + mc_count * ETH_ALEN;
ce9e2e1b 2686
e81cd2d6 2687 cmd = kzalloc(size, GFP_ATOMIC);
a66098da 2688 if (cmd == NULL)
e81cd2d6 2689 return NULL;
a66098da
LB		 2690
2691 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
2692 cmd->header.length = cpu_to_le16(size);
d5e30845
LB		 2693 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED |
2694 MWL8K_ENABLE_RX_BROADCAST);
2695
2696 if (allmulti) {
2697 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST);
2698 } else if (mc_count) {
22bedad3
JP		 2699 struct netdev_hw_addr *ha;
2700 int i = 0;
d5e30845
LB		 2701
2702 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
2703 cmd->numaddr = cpu_to_le16(mc_count);
22bedad3
JP		 2704 netdev_hw_addr_list_for_each(ha, mc_list) {
2705 memcpy(cmd->addr[i], ha->addr, ETH_ALEN);
a66098da 2706 }
a66098da
LB		 2707 }
2708
e81cd2d6 2709 return &cmd->header;
a66098da
LB		 2710}
2711
2712/*
55489b6e 2713 * CMD_GET_STAT.
a66098da 2714 */
55489b6e 2715struct mwl8k_cmd_get_stat {
a66098da 2716 struct mwl8k_cmd_pkt header;
a66098da 2717 __le32 stats[64];
ba2d3587 2718} __packed;
a66098da
LB		 2719
2720#define MWL8K_STAT_ACK_FAILURE 9
2721#define MWL8K_STAT_RTS_FAILURE 12
2722#define MWL8K_STAT_FCS_ERROR 24
2723#define MWL8K_STAT_RTS_SUCCESS 11
2724
55489b6e
LB		 2725static int mwl8k_cmd_get_stat(struct ieee80211_hw *hw,
2726 struct ieee80211_low_level_stats *stats)
a66098da 2727{
55489b6e 2728 struct mwl8k_cmd_get_stat *cmd;
a66098da
LB		 2729 int rc;
2730
2731 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2732 if (cmd == NULL)
2733 return -ENOMEM;
2734
2735 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
2736 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB		 2737
2738 rc = mwl8k_post_cmd(hw, &cmd->header);
2739 if (!rc) {
2740 stats->dot11ACKFailureCount =
2741 le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
2742 stats->dot11RTSFailureCount =
2743 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
2744 stats->dot11FCSErrorCount =
2745 le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
2746 stats->dot11RTSSuccessCount =
2747 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
2748 }
2749 kfree(cmd);
2750
2751 return rc;
2752}
2753
2754/*
55489b6e 2755 * CMD_RADIO_CONTROL.
a66098da 2756 */
55489b6e 2757struct mwl8k_cmd_radio_control {
a66098da
LB		 2758 struct mwl8k_cmd_pkt header;
2759 __le16 action;
2760 __le16 control;
2761 __le16 radio_on;
ba2d3587 2762} __packed;
a66098da 2763
c46563b7 2764static int
55489b6e 2765mwl8k_cmd_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
a66098da
LB		 2766{
2767 struct mwl8k_priv *priv = hw->priv;
55489b6e 2768 struct mwl8k_cmd_radio_control *cmd;
a66098da
LB		 2769 int rc;
2770
c46563b7 2771 if (enable == priv->radio_on && !force)
a66098da
LB		 2772 return 0;
2773
a66098da
LB		 2774 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2775 if (cmd == NULL)
2776 return -ENOMEM;
2777
2778 cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
2779 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2780 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
68ce3884 2781 cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
a66098da
LB		 2782 cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
2783
2784 rc = mwl8k_post_cmd(hw, &cmd->header);
2785 kfree(cmd);
2786
2787 if (!rc)
c46563b7 2788 priv->radio_on = enable;
a66098da
LB		 2789
2790 return rc;
2791}
2792
55489b6e 2793static int mwl8k_cmd_radio_disable(struct ieee80211_hw *hw)
c46563b7 2794{
55489b6e 2795 return mwl8k_cmd_radio_control(hw, 0, 0);
c46563b7
LB		 2796}
2797
55489b6e 2798static int mwl8k_cmd_radio_enable(struct ieee80211_hw *hw)
c46563b7 2799{
55489b6e 2800 return mwl8k_cmd_radio_control(hw, 1, 0);
c46563b7
LB		 2801}
2802
a66098da
LB		 2803static int
2804mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
2805{
99200a99 2806 struct mwl8k_priv *priv = hw->priv;
a66098da 2807
68ce3884 2808 priv->radio_short_preamble = short_preamble;
a66098da 2809
55489b6e 2810 return mwl8k_cmd_radio_control(hw, 1, 1);
a66098da
LB		 2811}
2812
2813/*
55489b6e 2814 * CMD_RF_TX_POWER.
a66098da 2815 */
41fdf097 2816#define MWL8K_RF_TX_POWER_LEVEL_TOTAL 8
a66098da 2817
55489b6e 2818struct mwl8k_cmd_rf_tx_power {
a66098da
LB		 2819 struct mwl8k_cmd_pkt header;
2820 __le16 action;
2821 __le16 support_level;
2822 __le16 current_level;
2823 __le16 reserved;
41fdf097 2824 __le16 power_level_list[MWL8K_RF_TX_POWER_LEVEL_TOTAL];
ba2d3587 2825} __packed;
a66098da 2826
55489b6e 2827static int mwl8k_cmd_rf_tx_power(struct ieee80211_hw *hw, int dBm)
a66098da 2828{
55489b6e 2829 struct mwl8k_cmd_rf_tx_power *cmd;
a66098da
LB		 2830 int rc;
2831
2832 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2833 if (cmd == NULL)
2834 return -ENOMEM;
2835
2836 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
2837 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2838 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2839 cmd->support_level = cpu_to_le16(dBm);
2840
2841 rc = mwl8k_post_cmd(hw, &cmd->header);
2842 kfree(cmd);
2843
2844 return rc;
2845}
2846
41fdf097
NS		 2847/*
2848 * CMD_TX_POWER.
2849 */
2850#define MWL8K_TX_POWER_LEVEL_TOTAL 12
2851
2852struct mwl8k_cmd_tx_power {
2853 struct mwl8k_cmd_pkt header;
2854 __le16 action;
2855 __le16 band;
2856 __le16 channel;
2857 __le16 bw;
2858 __le16 sub_ch;
2859 __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
ba30c4a5 2860} __packed;
41fdf097
NS		 2861
2862static int mwl8k_cmd_tx_power(struct ieee80211_hw *hw,
2863 struct ieee80211_conf *conf,
2864 unsigned short pwr)
2865{
675a0b04
KB		 2866 struct ieee80211_channel *channel = conf->chandef.chan;
2867 enum nl80211_channel_type channel_type =
2868 cfg80211_get_chandef_type(&conf->chandef);
41fdf097
NS		 2869 struct mwl8k_cmd_tx_power *cmd;
2870 int rc;
2871 int i;
2872
2873 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2874 if (cmd == NULL)
2875 return -ENOMEM;
2876
2877 cmd->header.code = cpu_to_le16(MWL8K_CMD_TX_POWER);
2878 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2879 cmd->action = cpu_to_le16(MWL8K_CMD_SET_LIST);
2880
2881 if (channel->band == IEEE80211_BAND_2GHZ)
2882 cmd->band = cpu_to_le16(0x1);
2883 else if (channel->band == IEEE80211_BAND_5GHZ)
2884 cmd->band = cpu_to_le16(0x4);
2885
604c4ef1 2886 cmd->channel = cpu_to_le16(channel->hw_value);
41fdf097 2887
675a0b04
KB		 2888 if (channel_type == NL80211_CHAN_NO_HT ||
2889 channel_type == NL80211_CHAN_HT20) {
41fdf097
NS		 2890 cmd->bw = cpu_to_le16(0x2);
2891 } else {
2892 cmd->bw = cpu_to_le16(0x4);
675a0b04 2893 if (channel_type == NL80211_CHAN_HT40MINUS)
41fdf097 2894 cmd->sub_ch = cpu_to_le16(0x3);
675a0b04 2895 else if (channel_type == NL80211_CHAN_HT40PLUS)
41fdf097
NS		 2896 cmd->sub_ch = cpu_to_le16(0x1);
2897 }
2898
2899 for (i = 0; i < MWL8K_TX_POWER_LEVEL_TOTAL; i++)
2900 cmd->power_level_list[i] = cpu_to_le16(pwr);
2901
2902 rc = mwl8k_post_cmd(hw, &cmd->header);
2903 kfree(cmd);
2904
2905 return rc;
2906}
2907
08b06347
LB		 2908/*
2909 * CMD_RF_ANTENNA.
2910 */
2911struct mwl8k_cmd_rf_antenna {
2912 struct mwl8k_cmd_pkt header;
2913 __le16 antenna;
2914 __le16 mode;
ba2d3587 2915} __packed;
08b06347
LB		 2916
2917#define MWL8K_RF_ANTENNA_RX 1
2918#define MWL8K_RF_ANTENNA_TX 2
2919
2920static int
2921mwl8k_cmd_rf_antenna(struct ieee80211_hw *hw, int antenna, int mask)
2922{
2923 struct mwl8k_cmd_rf_antenna *cmd;
2924 int rc;
2925
2926 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2927 if (cmd == NULL)
2928 return -ENOMEM;
2929
2930 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_ANTENNA);
2931 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2932 cmd->antenna = cpu_to_le16(antenna);
2933 cmd->mode = cpu_to_le16(mask);
2934
2935 rc = mwl8k_post_cmd(hw, &cmd->header);
2936 kfree(cmd);
2937
2938 return rc;
2939}
2940
b64fe619
LB		 2941/*
2942 * CMD_SET_BEACON.
2943 */
2944struct mwl8k_cmd_set_beacon {
2945 struct mwl8k_cmd_pkt header;
2946 __le16 beacon_len;
2947 __u8 beacon[0];
2948};
2949
aa21d0f6
LB		 2950static int mwl8k_cmd_set_beacon(struct ieee80211_hw *hw,
2951 struct ieee80211_vif *vif, u8 *beacon, int len)
b64fe619
LB		 2952{
2953 struct mwl8k_cmd_set_beacon *cmd;
2954 int rc;
2955
2956 cmd = kzalloc(sizeof(*cmd) + len, GFP_KERNEL);
2957 if (cmd == NULL)
2958 return -ENOMEM;
2959
2960 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_BEACON);
2961 cmd->header.length = cpu_to_le16(sizeof(*cmd) + len);
2962 cmd->beacon_len = cpu_to_le16(len);
2963 memcpy(cmd->beacon, beacon, len);
2964
aa21d0f6 2965 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
b64fe619
LB		 2966 kfree(cmd);
2967
2968 return rc;
2969}
2970
a66098da
LB		 2971/*
2972 * CMD_SET_PRE_SCAN.
2973 */
2974struct mwl8k_cmd_set_pre_scan {
2975 struct mwl8k_cmd_pkt header;
ba2d3587 2976} __packed;
a66098da
LB		 2977
2978static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
2979{
2980 struct mwl8k_cmd_set_pre_scan *cmd;
2981 int rc;
2982
2983 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2984 if (cmd == NULL)
2985 return -ENOMEM;
2986
2987 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
2988 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2989
2990 rc = mwl8k_post_cmd(hw, &cmd->header);
2991 kfree(cmd);
2992
2993 return rc;
2994}
2995
c3015313
YAP		 2996/*
2997 * CMD_BBP_REG_ACCESS.
2998 */
2999struct mwl8k_cmd_bbp_reg_access {
3000 struct mwl8k_cmd_pkt header;
3001 __le16 action;
3002 __le16 offset;
3003 u8 value;
3004 u8 rsrv[3];
3005} __packed;
3006
3007static int
3008mwl8k_cmd_bbp_reg_access(struct ieee80211_hw *hw,
3009 u16 action,
3010 u16 offset,
3011 u8 *value)
3012{
3013 struct mwl8k_cmd_bbp_reg_access *cmd;
3014 int rc;
3015
3016 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3017 if (cmd == NULL)
3018 return -ENOMEM;
3019
3020 cmd->header.code = cpu_to_le16(MWL8K_CMD_BBP_REG_ACCESS);
3021 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3022 cmd->action = cpu_to_le16(action);
3023 cmd->offset = cpu_to_le16(offset);
3024
3025 rc = mwl8k_post_cmd(hw, &cmd->header);
3026
3027 if (!rc)
3028 *value = cmd->value;
3029 else
3030 *value = 0;
3031
3032 kfree(cmd);
3033
3034 return rc;
3035}
3036
a66098da
LB		 3037/*
3038 * CMD_SET_POST_SCAN.
3039 */
3040struct mwl8k_cmd_set_post_scan {
3041 struct mwl8k_cmd_pkt header;
3042 __le32 isibss;
d89173f2 3043 __u8 bssid[ETH_ALEN];
ba2d3587 3044} __packed;
a66098da
LB		 3045
3046static int
0a11dfc3 3047mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, const __u8 *mac)
a66098da
LB		 3048{
3049 struct mwl8k_cmd_set_post_scan *cmd;
3050 int rc;
3051
3052 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3053 if (cmd == NULL)
3054 return -ENOMEM;
3055
3056 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
3057 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3058 cmd->isibss = 0;
d89173f2 3059 memcpy(cmd->bssid, mac, ETH_ALEN);
a66098da
LB		 3060
3061 rc = mwl8k_post_cmd(hw, &cmd->header);
3062 kfree(cmd);
3063
3064 return rc;
3065}
3066
031eb464
YAP		 3067static int freq_to_idx(struct mwl8k_priv *priv, int freq)
3068{
3069 struct ieee80211_supported_band *sband;
3070 int band, ch, idx = 0;
3071
3072 for (band = IEEE80211_BAND_2GHZ; band < IEEE80211_NUM_BANDS; band++) {
3073 sband = priv->hw->wiphy->bands[band];
3074 if (!sband)
3075 continue;
3076
3077 for (ch = 0; ch < sband->n_channels; ch++, idx++)
3078 if (sband->channels[ch].center_freq == freq)
3079 goto exit;
3080 }
3081
3082exit:
3083 return idx;
3084}
3085
c7c361ef
YAP		 3086static void mwl8k_update_survey(struct mwl8k_priv *priv,
3087 struct ieee80211_channel *channel)
031eb464
YAP		 3088{
3089 u32 cca_cnt, rx_rdy;
3090 s8 nf = 0, idx;
3091 struct survey_info *survey;
3092
3093 idx = freq_to_idx(priv, priv->acs_chan->center_freq);
3094 if (idx >= MWL8K_NUM_CHANS) {
3095 wiphy_err(priv->hw->wiphy, "Failed to update survey\n");
3096 return;
3097 }
3098
3099 survey = &priv->survey[idx];
3100
aa0bee1f 3101 cca_cnt = ioread32(priv->regs + NOK_CCA_CNT_REG);
031eb464
YAP		 3102 cca_cnt /= 1000; /* uSecs to mSecs */
3103 survey->channel_time_busy = (u64) cca_cnt;
3104
aa0bee1f 3105 rx_rdy = ioread32(priv->regs + BBU_RXRDY_CNT_REG);
031eb464
YAP		 3106 rx_rdy /= 1000; /* uSecs to mSecs */
3107 survey->channel_time_rx = (u64) rx_rdy;
3108
3109 priv->channel_time = jiffies - priv->channel_time;
3110 survey->channel_time = jiffies_to_msecs(priv->channel_time);
3111
3112 survey->channel = channel;
3113
3114 mwl8k_cmd_bbp_reg_access(priv->hw, 0, BBU_AVG_NOISE_VAL, &nf);
3115
3116 /* Make sure sign is negative else ACS at hostapd fails */
3117 survey->noise = nf * -1;
3118
3119 survey->filled = SURVEY_INFO_NOISE_DBM |
3120 SURVEY_INFO_CHANNEL_TIME |
3121 SURVEY_INFO_CHANNEL_TIME_BUSY |
3122 SURVEY_INFO_CHANNEL_TIME_RX;
3123}
3124
a66098da
LB		 3125/*
3126 * CMD_SET_RF_CHANNEL.
3127 */
3128struct mwl8k_cmd_set_rf_channel {
3129 struct mwl8k_cmd_pkt header;
3130 __le16 action;
3131 __u8 current_channel;
3132 __le32 channel_flags;
ba2d3587 3133} __packed;
a66098da
LB		 3134
3135static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
610677d2 3136 struct ieee80211_conf *conf)
a66098da 3137{
675a0b04
KB		 3138 struct ieee80211_channel *channel = conf->chandef.chan;
3139 enum nl80211_channel_type channel_type =
3140 cfg80211_get_chandef_type(&conf->chandef);
a66098da 3141 struct mwl8k_cmd_set_rf_channel *cmd;
031eb464 3142 struct mwl8k_priv *priv = hw->priv;
a66098da
LB		 3143 int rc;
3144
3145 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3146 if (cmd == NULL)
3147 return -ENOMEM;
3148
3149 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
3150 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3151 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
3152 cmd->current_channel = channel->hw_value;
610677d2 3153
a66098da 3154 if (channel->band == IEEE80211_BAND_2GHZ)
610677d2 3155 cmd->channel_flags |= cpu_to_le32(0x00000001);
42574ea2
LB		 3156 else if (channel->band == IEEE80211_BAND_5GHZ)
3157 cmd->channel_flags |= cpu_to_le32(0x00000004);
610677d2 3158
031eb464
YAP		 3159 if (!priv->sw_scan_start) {
3160 if (channel_type == NL80211_CHAN_NO_HT ||
3161 channel_type == NL80211_CHAN_HT20)
3162 cmd->channel_flags |= cpu_to_le32(0x00000080);
3163 else if (channel_type == NL80211_CHAN_HT40MINUS)
3164 cmd->channel_flags |= cpu_to_le32(0x000001900);
3165 else if (channel_type == NL80211_CHAN_HT40PLUS)
3166 cmd->channel_flags |= cpu_to_le32(0x000000900);
3167 } else {
610677d2 3168 cmd->channel_flags |= cpu_to_le32(0x00000080);
031eb464
YAP		 3169 }
3170
3171 if (priv->sw_scan_start) {
3172 /* Store current channel stats
3173 * before switching to newer one.
3174 * This will be processed only for AP fw.
3175 */
3176 if (priv->channel_time != 0)
3177 mwl8k_update_survey(priv, priv->acs_chan);
3178
3179 priv->channel_time = jiffies;
3180 priv->acs_chan = channel;
3181 }
a66098da
LB		 3182
3183 rc = mwl8k_post_cmd(hw, &cmd->header);
3184 kfree(cmd);
3185
3186 return rc;
3187}
3188
3189/*
55489b6e 3190 * CMD_SET_AID.
a66098da 3191 */
55489b6e
LB		 3192#define MWL8K_FRAME_PROT_DISABLED 0x00
3193#define MWL8K_FRAME_PROT_11G 0x07
3194#define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
3195#define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
a66098da 3196
55489b6e
LB		 3197struct mwl8k_cmd_update_set_aid {
3198 struct mwl8k_cmd_pkt header;
3199 __le16 aid;
a66098da 3200
55489b6e
LB		 3201 /* AP's MAC address (BSSID) */
3202 __u8 bssid[ETH_ALEN];
3203 __le16 protection_mode;
3204 __u8 supp_rates[14];
ba2d3587 3205} __packed;
a66098da 3206
c6e96010
LB		 3207static void legacy_rate_mask_to_array(u8 *rates, u32 mask)
3208{
3209 int i;
3210 int j;
3211
3212 /*
3f524559 3213 * Clear nonstandard rate 4.
c6e96010
LB		 3214 */
3215 mask &= 0x1fef;
3216
3f524559 3217 for (i = 0, j = 0; i < 13; i++) {
c6e96010 3218 if (mask & (1 << i))
777ad375 3219 rates[j++] = mwl8k_rates_24[i].hw_value;
c6e96010
LB		 3220 }
3221}
3222
55489b6e 3223static int
c6e96010
LB		 3224mwl8k_cmd_set_aid(struct ieee80211_hw *hw,
3225 struct ieee80211_vif *vif, u32 legacy_rate_mask)
a66098da 3226{
55489b6e
LB		 3227 struct mwl8k_cmd_update_set_aid *cmd;
3228 u16 prot_mode;
a66098da
LB		 3229 int rc;
3230
3231 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3232 if (cmd == NULL)
3233 return -ENOMEM;
3234
55489b6e 3235 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
a66098da 3236 cmd->header.length = cpu_to_le16(sizeof(*cmd));
7dc6a7a7 3237 cmd->aid = cpu_to_le16(vif->bss_conf.aid);
0a11dfc3 3238 memcpy(cmd->bssid, vif->bss_conf.bssid, ETH_ALEN);
a66098da 3239
7dc6a7a7 3240 if (vif->bss_conf.use_cts_prot) {
55489b6e
LB		 3241 prot_mode = MWL8K_FRAME_PROT_11G;
3242 } else {
7dc6a7a7 3243 switch (vif->bss_conf.ht_operation_mode &
55489b6e
LB		 3244 IEEE80211_HT_OP_MODE_PROTECTION) {
3245 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
3246 prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
3247 break;
3248 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
3249 prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
3250 break;
3251 default:
3252 prot_mode = MWL8K_FRAME_PROT_DISABLED;
3253 break;
3254 }
3255 }
3256 cmd->protection_mode = cpu_to_le16(prot_mode);
a66098da 3257
c6e96010 3258 legacy_rate_mask_to_array(cmd->supp_rates, legacy_rate_mask);
a66098da
LB		 3259
3260 rc = mwl8k_post_cmd(hw, &cmd->header);
3261 kfree(cmd);
3262
3263 return rc;
3264}
3265
32060e1b 3266/*
55489b6e 3267 * CMD_SET_RATE.
32060e1b 3268 */
55489b6e
LB		 3269struct mwl8k_cmd_set_rate {
3270 struct mwl8k_cmd_pkt header;
3271 __u8 legacy_rates[14];
3272
3273 /* Bitmap for supported MCS codes. */
3274 __u8 mcs_set[16];
3275 __u8 reserved[16];
ba2d3587 3276} __packed;
32060e1b 3277
55489b6e 3278static int
c6e96010 3279mwl8k_cmd_set_rate(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
13935e2c 3280 u32 legacy_rate_mask, u8 *mcs_rates)
32060e1b 3281{
55489b6e 3282 struct mwl8k_cmd_set_rate *cmd;
32060e1b
LB		 3283 int rc;
3284
3285 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3286 if (cmd == NULL)
3287 return -ENOMEM;
3288
55489b6e 3289 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
32060e1b 3290 cmd->header.length = cpu_to_le16(sizeof(*cmd));
c6e96010 3291 legacy_rate_mask_to_array(cmd->legacy_rates, legacy_rate_mask);
13935e2c 3292 memcpy(cmd->mcs_set, mcs_rates, 16);
32060e1b
LB		 3293
3294 rc = mwl8k_post_cmd(hw, &cmd->header);
3295 kfree(cmd);
3296
3297 return rc;
3298}
3299
a66098da 3300/*
55489b6e 3301 * CMD_FINALIZE_JOIN.
a66098da 3302 */
55489b6e
LB		 3303#define MWL8K_FJ_BEACON_MAXLEN 128
3304
3305struct mwl8k_cmd_finalize_join {
a66098da 3306 struct mwl8k_cmd_pkt header;
55489b6e
LB		 3307 __le32 sleep_interval; /* Number of beacon periods to sleep */
3308 __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
ba2d3587 3309} __packed;
a66098da 3310
55489b6e
LB		 3311static int mwl8k_cmd_finalize_join(struct ieee80211_hw *hw, void *frame,
3312 int framelen, int dtim)
a66098da 3313{
55489b6e
LB		 3314 struct mwl8k_cmd_finalize_join *cmd;
3315 struct ieee80211_mgmt *payload = frame;
3316 int payload_len;
a66098da
LB		 3317 int rc;
3318
3319 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3320 if (cmd == NULL)
3321 return -ENOMEM;
3322
55489b6e 3323 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
a66098da 3324 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB		 3325 cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
3326
3327 payload_len = framelen - ieee80211_hdrlen(payload->frame_control);
3328 if (payload_len < 0)
3329 payload_len = 0;
3330 else if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
3331 payload_len = MWL8K_FJ_BEACON_MAXLEN;
3332
3333 memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
a66098da
LB		 3334
3335 rc = mwl8k_post_cmd(hw, &cmd->header);
3336 kfree(cmd);
3337
3338 return rc;
3339}
3340
3341/*
55489b6e 3342 * CMD_SET_RTS_THRESHOLD.
a66098da 3343 */
55489b6e 3344struct mwl8k_cmd_set_rts_threshold {
a66098da
LB		 3345 struct mwl8k_cmd_pkt header;
3346 __le16 action;
55489b6e 3347 __le16 threshold;
ba2d3587 3348} __packed;
a66098da 3349
c2c2b12a
LB		 3350static int
3351mwl8k_cmd_set_rts_threshold(struct ieee80211_hw *hw, int rts_thresh)
a66098da 3352{
55489b6e 3353 struct mwl8k_cmd_set_rts_threshold *cmd;
a66098da
LB		 3354 int rc;
3355
3356 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3357 if (cmd == NULL)
3358 return -ENOMEM;
3359
55489b6e 3360 cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
a66098da 3361 cmd->header.length = cpu_to_le16(sizeof(*cmd));
c2c2b12a
LB		 3362 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
3363 cmd->threshold = cpu_to_le16(rts_thresh);
a66098da
LB		 3364
3365 rc = mwl8k_post_cmd(hw, &cmd->header);
3366 kfree(cmd);
3367
a66098da
LB		 3368 return rc;
3369}
3370
3371/*
55489b6e 3372 * CMD_SET_SLOT.
a66098da 3373 */
55489b6e 3374struct mwl8k_cmd_set_slot {
a66098da
LB		 3375 struct mwl8k_cmd_pkt header;
3376 __le16 action;
55489b6e 3377 __u8 short_slot;
ba2d3587 3378} __packed;
a66098da 3379
55489b6e 3380static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time)
a66098da 3381{
55489b6e 3382 struct mwl8k_cmd_set_slot *cmd;
a66098da
LB		 3383 int rc;
3384
3385 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3386 if (cmd == NULL)
3387 return -ENOMEM;
3388
55489b6e 3389 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
a66098da 3390 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB		 3391 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
3392 cmd->short_slot = short_slot_time;
a66098da
LB		 3393
3394 rc = mwl8k_post_cmd(hw, &cmd->header);
3395 kfree(cmd);
3396
3397 return rc;
3398}
3399
3400/*
3401 * CMD_SET_EDCA_PARAMS.
3402 */
3403struct mwl8k_cmd_set_edca_params {
3404 struct mwl8k_cmd_pkt header;
3405
3406 /* See MWL8K_SET_EDCA_XXX below */
3407 __le16 action;
3408
3409 /* TX opportunity in units of 32 us */
3410 __le16 txop;
3411
2e484c89
LB		 3412 union {
3413 struct {
3414 /* Log exponent of max contention period: 0...15 */
3415 __le32 log_cw_max;
3416
3417 /* Log exponent of min contention period: 0...15 */
3418 __le32 log_cw_min;
3419
3420 /* Adaptive interframe spacing in units of 32us */
3421 __u8 aifs;
3422
3423 /* TX queue to configure */
3424 __u8 txq;
3425 } ap;
3426 struct {
3427 /* Log exponent of max contention period: 0...15 */
3428 __u8 log_cw_max;
a66098da 3429
2e484c89
LB		 3430 /* Log exponent of min contention period: 0...15 */
3431 __u8 log_cw_min;
a66098da 3432
2e484c89
LB		 3433 /* Adaptive interframe spacing in units of 32us */
3434 __u8 aifs;
a66098da 3435
2e484c89
LB		 3436 /* TX queue to configure */
3437 __u8 txq;
3438 } sta;
3439 };
ba2d3587 3440} __packed;
a66098da 3441
a66098da
LB		 3442#define MWL8K_SET_EDCA_CW 0x01
3443#define MWL8K_SET_EDCA_TXOP 0x02
3444#define MWL8K_SET_EDCA_AIFS 0x04
3445
3446#define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
3447 MWL8K_SET_EDCA_TXOP | \
3448 MWL8K_SET_EDCA_AIFS)
3449
3450static int
55489b6e
LB		 3451mwl8k_cmd_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
3452 __u16 cw_min, __u16 cw_max,
3453 __u8 aifs, __u16 txop)
a66098da 3454{
2e484c89 3455 struct mwl8k_priv *priv = hw->priv;
a66098da 3456 struct mwl8k_cmd_set_edca_params *cmd;
a66098da
LB		 3457 int rc;
3458
3459 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3460 if (cmd == NULL)
3461 return -ENOMEM;
3462
a66098da
LB		 3463 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
3464 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB		 3465 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
3466 cmd->txop = cpu_to_le16(txop);
2e484c89
LB		 3467 if (priv->ap_fw) {
3468 cmd->ap.log_cw_max = cpu_to_le32(ilog2(cw_max + 1));
3469 cmd->ap.log_cw_min = cpu_to_le32(ilog2(cw_min + 1));
3470 cmd->ap.aifs = aifs;
3471 cmd->ap.txq = qnum;
3472 } else {
3473 cmd->sta.log_cw_max = (u8)ilog2(cw_max + 1);
3474 cmd->sta.log_cw_min = (u8)ilog2(cw_min + 1);
3475 cmd->sta.aifs = aifs;
3476 cmd->sta.txq = qnum;
3477 }
a66098da
LB		 3478
3479 rc = mwl8k_post_cmd(hw, &cmd->header);
3480 kfree(cmd);
3481
3482 return rc;
3483}
3484
3485/*
55489b6e 3486 * CMD_SET_WMM_MODE.
a66098da 3487 */
55489b6e 3488struct mwl8k_cmd_set_wmm_mode {
a66098da 3489 struct mwl8k_cmd_pkt header;
55489b6e 3490 __le16 action;
ba2d3587 3491} __packed;
a66098da 3492
55489b6e 3493static int mwl8k_cmd_set_wmm_mode(struct ieee80211_hw *hw, bool enable)
a66098da 3494{
55489b6e
LB		 3495 struct mwl8k_priv *priv = hw->priv;
3496 struct mwl8k_cmd_set_wmm_mode *cmd;
a66098da
LB		 3497 int rc;
3498
a66098da
LB		 3499 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3500 if (cmd == NULL)
3501 return -ENOMEM;
3502
55489b6e 3503 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
a66098da 3504 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e 3505 cmd->action = cpu_to_le16(!!enable);
a66098da
LB		 3506
3507 rc = mwl8k_post_cmd(hw, &cmd->header);
3508 kfree(cmd);
16cec43d 3509
55489b6e
LB		 3510 if (!rc)
3511 priv->wmm_enabled = enable;
a66098da
LB		 3512
3513 return rc;
3514}
3515
3516/*
55489b6e 3517 * CMD_MIMO_CONFIG.
a66098da 3518 */
55489b6e
LB		 3519struct mwl8k_cmd_mimo_config {
3520 struct mwl8k_cmd_pkt header;
3521 __le32 action;
3522 __u8 rx_antenna_map;
3523 __u8 tx_antenna_map;
ba2d3587 3524} __packed;
a66098da 3525
55489b6e 3526static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
a66098da 3527{
55489b6e 3528 struct mwl8k_cmd_mimo_config *cmd;
a66098da
LB		 3529 int rc;
3530
3531 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3532 if (cmd == NULL)
3533 return -ENOMEM;
3534
55489b6e 3535 cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
a66098da 3536 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB		 3537 cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
3538 cmd->rx_antenna_map = rx;
3539 cmd->tx_antenna_map = tx;
a66098da
LB		 3540
3541 rc = mwl8k_post_cmd(hw, &cmd->header);
3542 kfree(cmd);
3543
3544 return rc;
3545}
3546
3547/*
b71ed2c6 3548 * CMD_USE_FIXED_RATE (STA version).
a66098da 3549 */
b71ed2c6
LB		 3550struct mwl8k_cmd_use_fixed_rate_sta {
3551 struct mwl8k_cmd_pkt header;
3552 __le32 action;
3553 __le32 allow_rate_drop;
3554 __le32 num_rates;
3555 struct {
3556 __le32 is_ht_rate;
3557 __le32 enable_retry;
3558 __le32 rate;
3559 __le32 retry_count;
3560 } rate_entry[8];
3561 __le32 rate_type;
3562 __le32 reserved1;
3563 __le32 reserved2;
ba2d3587 3564} __packed;
a66098da 3565
b71ed2c6
LB		 3566#define MWL8K_USE_AUTO_RATE 0x0002
3567#define MWL8K_UCAST_RATE 0
a66098da 3568
b71ed2c6 3569static int mwl8k_cmd_use_fixed_rate_sta(struct ieee80211_hw *hw)
a66098da 3570{
b71ed2c6 3571 struct mwl8k_cmd_use_fixed_rate_sta *cmd;
a66098da
LB		 3572 int rc;
3573
3574 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3575 if (cmd == NULL)
3576 return -ENOMEM;
3577
3578 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
3579 cmd->header.length = cpu_to_le16(sizeof(*cmd));
b71ed2c6
LB		 3580 cmd->action = cpu_to_le32(MWL8K_USE_AUTO_RATE);
3581 cmd->rate_type = cpu_to_le32(MWL8K_UCAST_RATE);
a66098da
LB		 3582
3583 rc = mwl8k_post_cmd(hw, &cmd->header);
3584 kfree(cmd);
3585
3586 return rc;
3587}
3588
088aab8b
LB		 3589/*
3590 * CMD_USE_FIXED_RATE (AP version).
3591 */
3592struct mwl8k_cmd_use_fixed_rate_ap {
3593 struct mwl8k_cmd_pkt header;
3594 __le32 action;
3595 __le32 allow_rate_drop;
3596 __le32 num_rates;
3597 struct mwl8k_rate_entry_ap {
3598 __le32 is_ht_rate;
3599 __le32 enable_retry;
3600 __le32 rate;
3601 __le32 retry_count;
3602 } rate_entry[4];
3603 u8 multicast_rate;
3604 u8 multicast_rate_type;
3605 u8 management_rate;
ba2d3587 3606} __packed;
088aab8b
LB		 3607
3608static int
3609mwl8k_cmd_use_fixed_rate_ap(struct ieee80211_hw *hw, int mcast, int mgmt)
3610{
3611 struct mwl8k_cmd_use_fixed_rate_ap *cmd;
3612 int rc;
3613
3614 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3615 if (cmd == NULL)
3616 return -ENOMEM;
3617
3618 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
3619 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3620 cmd->action = cpu_to_le32(MWL8K_USE_AUTO_RATE);
3621 cmd->multicast_rate = mcast;
3622 cmd->management_rate = mgmt;
3623
3624 rc = mwl8k_post_cmd(hw, &cmd->header);
3625 kfree(cmd);
3626
3627 return rc;
3628}
3629
55489b6e
LB		 3630/*
3631 * CMD_ENABLE_SNIFFER.
3632 */
3633struct mwl8k_cmd_enable_sniffer {
3634 struct mwl8k_cmd_pkt header;
3635 __le32 action;
ba2d3587 3636} __packed;
55489b6e
LB		 3637
3638static int mwl8k_cmd_enable_sniffer(struct ieee80211_hw *hw, bool enable)
3639{
3640 struct mwl8k_cmd_enable_sniffer *cmd;
3641 int rc;
3642
3643 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3644 if (cmd == NULL)
3645 return -ENOMEM;
3646
3647 cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
3648 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3649 cmd->action = cpu_to_le32(!!enable);
3650
3651 rc = mwl8k_post_cmd(hw, &cmd->header);
3652 kfree(cmd);
3653
3654 return rc;
3655}
3656
197a4e4e 3657struct mwl8k_cmd_update_mac_addr {
55489b6e
LB		 3658 struct mwl8k_cmd_pkt header;
3659 union {
3660 struct {
3661 __le16 mac_type;
3662 __u8 mac_addr[ETH_ALEN];
3663 } mbss;
3664 __u8 mac_addr[ETH_ALEN];
3665 };
ba2d3587 3666} __packed;
55489b6e 3667
ee0ddf18
LB		 3668#define MWL8K_MAC_TYPE_PRIMARY_CLIENT 0
3669#define MWL8K_MAC_TYPE_SECONDARY_CLIENT 1
3670#define MWL8K_MAC_TYPE_PRIMARY_AP 2
3671#define MWL8K_MAC_TYPE_SECONDARY_AP 3
a9e00b15 3672
197a4e4e
YAP		 3673static int mwl8k_cmd_update_mac_addr(struct ieee80211_hw *hw,
3674 struct ieee80211_vif *vif, u8 *mac, bool set)
55489b6e
LB		 3675{
3676 struct mwl8k_priv *priv = hw->priv;
ee0ddf18 3677 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
197a4e4e 3678 struct mwl8k_cmd_update_mac_addr *cmd;
ee0ddf18 3679 int mac_type;
55489b6e
LB		 3680 int rc;
3681
ee0ddf18
LB		 3682 mac_type = MWL8K_MAC_TYPE_PRIMARY_AP;
3683 if (vif != NULL && vif->type == NL80211_IFTYPE_STATION) {
3684 if (mwl8k_vif->macid + 1 == ffs(priv->sta_macids_supported))
af458831
YAP		 3685 if (priv->ap_fw)
3686 mac_type = MWL8K_MAC_TYPE_SECONDARY_CLIENT;
3687 else
3688 mac_type = MWL8K_MAC_TYPE_PRIMARY_CLIENT;
ee0ddf18
LB		 3689 else
3690 mac_type = MWL8K_MAC_TYPE_SECONDARY_CLIENT;
3691 } else if (vif != NULL && vif->type == NL80211_IFTYPE_AP) {
3692 if (mwl8k_vif->macid + 1 == ffs(priv->ap_macids_supported))
3693 mac_type = MWL8K_MAC_TYPE_PRIMARY_AP;
3694 else
3695 mac_type = MWL8K_MAC_TYPE_SECONDARY_AP;
3696 }
3697
55489b6e
LB		 3698 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3699 if (cmd == NULL)
3700 return -ENOMEM;
3701
197a4e4e
YAP		 3702 if (set)
3703 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR);
3704 else
3705 cmd->header.code = cpu_to_le16(MWL8K_CMD_DEL_MAC_ADDR);
3706
55489b6e
LB		 3707 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3708 if (priv->ap_fw) {
ee0ddf18 3709 cmd->mbss.mac_type = cpu_to_le16(mac_type);
55489b6e
LB		 3710 memcpy(cmd->mbss.mac_addr, mac, ETH_ALEN);
3711 } else {
3712 memcpy(cmd->mac_addr, mac, ETH_ALEN);
3713 }
3714
aa21d0f6 3715 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
55489b6e
LB		 3716 kfree(cmd);
3717
3718 return rc;
3719}
3720
197a4e4e
YAP		 3721/*
3722 * MWL8K_CMD_SET_MAC_ADDR.
3723 */
3724static inline int mwl8k_cmd_set_mac_addr(struct ieee80211_hw *hw,
3725 struct ieee80211_vif *vif, u8 *mac)
3726{
3727 return mwl8k_cmd_update_mac_addr(hw, vif, mac, true);
3728}
3729
3730/*
3731 * MWL8K_CMD_DEL_MAC_ADDR.
3732 */
3733static inline int mwl8k_cmd_del_mac_addr(struct ieee80211_hw *hw,
3734 struct ieee80211_vif *vif, u8 *mac)
3735{
3736 return mwl8k_cmd_update_mac_addr(hw, vif, mac, false);
3737}
3738
55489b6e
LB		 3739/*
3740 * CMD_SET_RATEADAPT_MODE.
3741 */
3742struct mwl8k_cmd_set_rate_adapt_mode {
3743 struct mwl8k_cmd_pkt header;
3744 __le16 action;
3745 __le16 mode;
ba2d3587 3746} __packed;
55489b6e
LB		 3747
3748static int mwl8k_cmd_set_rateadapt_mode(struct ieee80211_hw *hw, __u16 mode)
3749{
3750 struct mwl8k_cmd_set_rate_adapt_mode *cmd;
3751 int rc;
3752
3753 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3754 if (cmd == NULL)
3755 return -ENOMEM;
3756
3757 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
3758 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3759 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
3760 cmd->mode = cpu_to_le16(mode);
3761
3762 rc = mwl8k_post_cmd(hw, &cmd->header);
3763 kfree(cmd);
3764
3765 return rc;
3766}
3767
3aefc37e
NS		 3768/*
3769 * CMD_GET_WATCHDOG_BITMAP.
3770 */
3771struct mwl8k_cmd_get_watchdog_bitmap {
3772 struct mwl8k_cmd_pkt header;
3773 u8 bitmap;
3774} __packed;
3775
3776static int mwl8k_cmd_get_watchdog_bitmap(struct ieee80211_hw *hw, u8 *bitmap)
3777{
3778 struct mwl8k_cmd_get_watchdog_bitmap *cmd;
3779 int rc;
3780
3781 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3782 if (cmd == NULL)
3783 return -ENOMEM;
3784
3785 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_WATCHDOG_BITMAP);
3786 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3787
3788 rc = mwl8k_post_cmd(hw, &cmd->header);
3789 if (!rc)
3790 *bitmap = cmd->bitmap;
3791
3792 kfree(cmd);
3793
3794 return rc;
3795}
3796
cfacba12
YAP		 3797#define MWL8K_WMM_QUEUE_NUMBER 3
3798
3799static void mwl8k_destroy_ba(struct ieee80211_hw *hw,
3800 u8 idx);
3801
3aefc37e
NS		 3802static void mwl8k_watchdog_ba_events(struct work_struct *work)
3803{
3804 int rc;
3805 u8 bitmap = 0, stream_index;
3806 struct mwl8k_ampdu_stream *streams;
3807 struct mwl8k_priv *priv =
3808 container_of(work, struct mwl8k_priv, watchdog_ba_handle);
cfacba12
YAP		 3809 struct ieee80211_hw *hw = priv->hw;
3810 int i;
3811 u32 status = 0;
3812
3813 mwl8k_fw_lock(hw);
3aefc37e
NS		 3814
3815 rc = mwl8k_cmd_get_watchdog_bitmap(priv->hw, &bitmap);
3816 if (rc)
cfacba12 3817 goto done;
3aefc37e 3818
cfacba12 3819 spin_lock(&priv->stream_lock);
3aefc37e
NS		 3820
3821 /* the bitmap is the hw queue number. Map it to the ampdu queue. */
cfacba12
YAP		 3822 for (i = 0; i < TOTAL_HW_TX_QUEUES; i++) {
3823 if (bitmap & (1 << i)) {
3824 stream_index = (i + MWL8K_WMM_QUEUE_NUMBER) %
3825 TOTAL_HW_TX_QUEUES;
3826 streams = &priv->ampdu[stream_index];
3827 if (streams->state == AMPDU_STREAM_ACTIVE) {
3828 ieee80211_stop_tx_ba_session(streams->sta,
3829 streams->tid);
3830 spin_unlock(&priv->stream_lock);
3831 mwl8k_destroy_ba(hw, stream_index);
3832 spin_lock(&priv->stream_lock);
3833 }
3834 }
3835 }
3aefc37e 3836
cfacba12
YAP		 3837 spin_unlock(&priv->stream_lock);
3838done:
c27a54d3 3839 atomic_dec(&priv->watchdog_event_pending);
cfacba12
YAP		 3840 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
3841 iowrite32((status | MWL8K_A2H_INT_BA_WATCHDOG),
3842 priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
3843 mwl8k_fw_unlock(hw);
3aefc37e
NS		 3844 return;
3845}
3846
3847
b64fe619
LB		 3848/*
3849 * CMD_BSS_START.
3850 */
3851struct mwl8k_cmd_bss_start {
3852 struct mwl8k_cmd_pkt header;
3853 __le32 enable;
ba2d3587 3854} __packed;
b64fe619 3855
aa21d0f6
LB		 3856static int mwl8k_cmd_bss_start(struct ieee80211_hw *hw,
3857 struct ieee80211_vif *vif, int enable)
b64fe619
LB		 3858{
3859 struct mwl8k_cmd_bss_start *cmd;
e882efc9
YAP		 3860 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
3861 struct mwl8k_priv *priv = hw->priv;
b64fe619
LB		 3862 int rc;
3863
e882efc9
YAP		 3864 if (enable && (priv->running_bsses & (1 << mwl8k_vif->macid)))
3865 return 0;
3866
3867 if (!enable && !(priv->running_bsses & (1 << mwl8k_vif->macid)))
3868 return 0;
3869
b64fe619
LB		 3870 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3871 if (cmd == NULL)
3872 return -ENOMEM;
3873
3874 cmd->header.code = cpu_to_le16(MWL8K_CMD_BSS_START);
3875 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3876 cmd->enable = cpu_to_le32(enable);
3877
aa21d0f6 3878 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
b64fe619
LB		 3879 kfree(cmd);
3880
e882efc9
YAP		 3881 if (!rc) {
3882 if (enable)
3883 priv->running_bsses |= (1 << mwl8k_vif->macid);
3884 else
3885 priv->running_bsses &= ~(1 << mwl8k_vif->macid);
3886 }
b64fe619
LB		 3887 return rc;
3888}
3889
e882efc9
YAP		 3890static void mwl8k_enable_bsses(struct ieee80211_hw *hw, bool enable, u32 bitmap)
3891{
3892 struct mwl8k_priv *priv = hw->priv;
3893 struct mwl8k_vif *mwl8k_vif, *tmp_vif;
3894 struct ieee80211_vif *vif;
3895
3896 list_for_each_entry_safe(mwl8k_vif, tmp_vif, &priv->vif_list, list) {
3897 vif = mwl8k_vif->vif;
3898
3899 if (!(bitmap & (1 << mwl8k_vif->macid)))
3900 continue;
3901
3902 if (vif->type == NL80211_IFTYPE_AP)
3903 mwl8k_cmd_bss_start(hw, vif, enable);
3904 }
3905}
5faa1aff
NS		 3906/*
3907 * CMD_BASTREAM.
3908 */
3909
3910/*
3911 * UPSTREAM is tx direction
3912 */
3913#define BASTREAM_FLAG_DIRECTION_UPSTREAM 0x00
3914#define BASTREAM_FLAG_IMMEDIATE_TYPE 0x01
3915
ba30c4a5 3916enum ba_stream_action_type {
5faa1aff
NS		 3917 MWL8K_BA_CREATE,
3918 MWL8K_BA_UPDATE,
3919 MWL8K_BA_DESTROY,
3920 MWL8K_BA_FLUSH,
3921 MWL8K_BA_CHECK,
ba30c4a5 3922};
5faa1aff
NS		 3923
3924
3925struct mwl8k_create_ba_stream {
3926 __le32 flags;
3927 __le32 idle_thrs;
3928 __le32 bar_thrs;
3929 __le32 window_size;
3930 u8 peer_mac_addr[6];
3931 u8 dialog_token;
3932 u8 tid;
3933 u8 queue_id;
3934 u8 param_info;
3935 __le32 ba_context;
3936 u8 reset_seq_no_flag;
3937 __le16 curr_seq_no;
3938 u8 sta_src_mac_addr[6];
3939} __packed;
3940
3941struct mwl8k_destroy_ba_stream {
3942 __le32 flags;
3943 __le32 ba_context;
3944} __packed;
3945
3946struct mwl8k_cmd_bastream {
3947 struct mwl8k_cmd_pkt header;
3948 __le32 action;
3949 union {
3950 struct mwl8k_create_ba_stream create_params;
3951 struct mwl8k_destroy_ba_stream destroy_params;
3952 };
3953} __packed;
3954
3955static int
f95275c4
YAP		 3956mwl8k_check_ba(struct ieee80211_hw *hw, struct mwl8k_ampdu_stream *stream,
3957 struct ieee80211_vif *vif)
5faa1aff
NS		 3958{
3959 struct mwl8k_cmd_bastream *cmd;
3960 int rc;
3961
3962 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3963 if (cmd == NULL)
3964 return -ENOMEM;
3965
3966 cmd->header.code = cpu_to_le16(MWL8K_CMD_BASTREAM);
3967 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3968
3969 cmd->action = cpu_to_le32(MWL8K_BA_CHECK);
3970
3971 cmd->create_params.queue_id = stream->idx;
3972 memcpy(&cmd->create_params.peer_mac_addr[0], stream->sta->addr,
3973 ETH_ALEN);
3974 cmd->create_params.tid = stream->tid;
3975
3976 cmd->create_params.flags =
3977 cpu_to_le32(BASTREAM_FLAG_IMMEDIATE_TYPE) |
3978 cpu_to_le32(BASTREAM_FLAG_DIRECTION_UPSTREAM);
3979
f95275c4 3980 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
5faa1aff
NS		 3981
3982 kfree(cmd);
3983
3984 return rc;
3985}
3986
3987static int
3988mwl8k_create_ba(struct ieee80211_hw *hw, struct mwl8k_ampdu_stream *stream,
f95275c4 3989 u8 buf_size, struct ieee80211_vif *vif)
5faa1aff
NS		 3990{
3991 struct mwl8k_cmd_bastream *cmd;
3992 int rc;
3993
3994 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3995 if (cmd == NULL)
3996 return -ENOMEM;
3997
3998
3999 cmd->header.code = cpu_to_le16(MWL8K_CMD_BASTREAM);
4000 cmd->header.length = cpu_to_le16(sizeof(*cmd));
4001
4002 cmd->action = cpu_to_le32(MWL8K_BA_CREATE);
4003
4004 cmd->create_params.bar_thrs = cpu_to_le32((u32)buf_size);
4005 cmd->create_params.window_size = cpu_to_le32((u32)buf_size);
4006 cmd->create_params.queue_id = stream->idx;
4007
4008 memcpy(cmd->create_params.peer_mac_addr, stream->sta->addr, ETH_ALEN);
4009 cmd->create_params.tid = stream->tid;
4010 cmd->create_params.curr_seq_no = cpu_to_le16(0);
4011 cmd->create_params.reset_seq_no_flag = 1;
4012
4013 cmd->create_params.param_info =
4014 (stream->sta->ht_cap.ampdu_factor &
4015 IEEE80211_HT_AMPDU_PARM_FACTOR) |
4016 ((stream->sta->ht_cap.ampdu_density << 2) &
4017 IEEE80211_HT_AMPDU_PARM_DENSITY);
4018
4019 cmd->create_params.flags =
4020 cpu_to_le32(BASTREAM_FLAG_IMMEDIATE_TYPE |
4021 BASTREAM_FLAG_DIRECTION_UPSTREAM);
4022
f95275c4 4023 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
5faa1aff
NS		 4024
4025 wiphy_debug(hw->wiphy, "Created a BA stream for %pM : tid %d\n",
4026 stream->sta->addr, stream->tid);
4027 kfree(cmd);
4028
4029 return rc;
4030}
4031
4032static void mwl8k_destroy_ba(struct ieee80211_hw *hw,
07f6dda1 4033 u8 idx)
5faa1aff
NS		 4034{
4035 struct mwl8k_cmd_bastream *cmd;
4036
4037 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
4038 if (cmd == NULL)
4039 return;
4040
4041 cmd->header.code = cpu_to_le16(MWL8K_CMD_BASTREAM);
4042 cmd->header.length = cpu_to_le16(sizeof(*cmd));
4043 cmd->action = cpu_to_le32(MWL8K_BA_DESTROY);
4044
07f6dda1 4045 cmd->destroy_params.ba_context = cpu_to_le32(idx);
5faa1aff
NS		 4046 mwl8k_post_cmd(hw, &cmd->header);
4047
07f6dda1 4048 wiphy_debug(hw->wiphy, "Deleted BA stream index %d\n", idx);
5faa1aff
NS		 4049
4050 kfree(cmd);
4051}
4052
3f5610ff
LB		 4053/*
4054 * CMD_SET_NEW_STN.
4055 */
4056struct mwl8k_cmd_set_new_stn {
4057 struct mwl8k_cmd_pkt header;
4058 __le16 aid;
4059 __u8 mac_addr[6];
4060 __le16 stn_id;
4061 __le16 action;
4062 __le16 rsvd;
4063 __le32 legacy_rates;
4064 __u8 ht_rates[4];
4065 __le16 cap_info;
4066 __le16 ht_capabilities_info;
4067 __u8 mac_ht_param_info;
4068 __u8 rev;
4069 __u8 control_channel;
4070 __u8 add_channel;
4071 __le16 op_mode;
4072 __le16 stbc;
4073 __u8 add_qos_info;
4074 __u8 is_qos_sta;
4075 __le32 fw_sta_ptr;
ba2d3587 4076} __packed;
3f5610ff
LB		 4077
4078#define MWL8K_STA_ACTION_ADD 0
4079#define MWL8K_STA_ACTION_REMOVE 2
4080
4081static int mwl8k_cmd_set_new_stn_add(struct ieee80211_hw *hw,
4082 struct ieee80211_vif *vif,
4083 struct ieee80211_sta *sta)
4084{
4085 struct mwl8k_cmd_set_new_stn *cmd;
8707d026 4086 u32 rates;
3f5610ff
LB		 4087 int rc;
4088
4089 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
4090 if (cmd == NULL)
4091 return -ENOMEM;
4092
4093 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
4094 cmd->header.length = cpu_to_le16(sizeof(*cmd));
4095 cmd->aid = cpu_to_le16(sta->aid);
4096 memcpy(cmd->mac_addr, sta->addr, ETH_ALEN);
4097 cmd->stn_id = cpu_to_le16(sta->aid);
4098 cmd->action = cpu_to_le16(MWL8K_STA_ACTION_ADD);
675a0b04 4099 if (hw->conf.chandef.chan->band == IEEE80211_BAND_2GHZ)
8707d026
LB		 4100 rates = sta->supp_rates[IEEE80211_BAND_2GHZ];
4101 else
4102 rates = sta->supp_rates[IEEE80211_BAND_5GHZ] << 5;
4103 cmd->legacy_rates = cpu_to_le32(rates);
3f5610ff
LB		 4104 if (sta->ht_cap.ht_supported) {
4105 cmd->ht_rates[0] = sta->ht_cap.mcs.rx_mask[0];
4106 cmd->ht_rates[1] = sta->ht_cap.mcs.rx_mask[1];
4107 cmd->ht_rates[2] = sta->ht_cap.mcs.rx_mask[2];
4108 cmd->ht_rates[3] = sta->ht_cap.mcs.rx_mask[3];
4109 cmd->ht_capabilities_info = cpu_to_le16(sta->ht_cap.cap);
4110 cmd->mac_ht_param_info = (sta->ht_cap.ampdu_factor & 3) |
4111 ((sta->ht_cap.ampdu_density & 7) << 2);
4112 cmd->is_qos_sta = 1;
4113 }
4114
aa21d0f6 4115 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
3f5610ff
LB		 4116 kfree(cmd);
4117
4118 return rc;
4119}
4120
b64fe619
LB		 4121static int mwl8k_cmd_set_new_stn_add_self(struct ieee80211_hw *hw,
4122 struct ieee80211_vif *vif)
4123{
4124 struct mwl8k_cmd_set_new_stn *cmd;
4125 int rc;
4126
4127 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
4128 if (cmd == NULL)
4129 return -ENOMEM;
4130
4131 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
4132 cmd->header.length = cpu_to_le16(sizeof(*cmd));
4133 memcpy(cmd->mac_addr, vif->addr, ETH_ALEN);
4134
aa21d0f6 4135 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
b64fe619
LB		 4136 kfree(cmd);
4137
4138 return rc;
4139}
4140
3f5610ff
LB		 4141static int mwl8k_cmd_set_new_stn_del(struct ieee80211_hw *hw,
4142 struct ieee80211_vif *vif, u8 *addr)
4143{
4144 struct mwl8k_cmd_set_new_stn *cmd;
0dd13a48
YAP		 4145 struct mwl8k_priv *priv = hw->priv;
4146 int rc, i;
4147 u8 idx;
4148
4149 spin_lock(&priv->stream_lock);
4150 /* Destroy any active ampdu streams for this sta */
4151 for (i = 0; i < MWL8K_NUM_AMPDU_STREAMS; i++) {
4152 struct mwl8k_ampdu_stream *s;
4153 s = &priv->ampdu[i];
4154 if (s->state != AMPDU_NO_STREAM) {
4155 if (memcmp(s->sta->addr, addr, ETH_ALEN) == 0) {
4156 if (s->state == AMPDU_STREAM_ACTIVE) {
4157 idx = s->idx;
4158 spin_unlock(&priv->stream_lock);
4159 mwl8k_destroy_ba(hw, idx);
4160 spin_lock(&priv->stream_lock);
4161 } else if (s->state == AMPDU_STREAM_NEW) {
4162 mwl8k_remove_stream(hw, s);
4163 }
4164 }
4165 }
4166 }
4167
4168 spin_unlock(&priv->stream_lock);
3f5610ff
LB		 4169
4170 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
4171 if (cmd == NULL)
4172 return -ENOMEM;
4173
4174 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
4175 cmd->header.length = cpu_to_le16(sizeof(*cmd));
4176 memcpy(cmd->mac_addr, addr, ETH_ALEN);
4177 cmd->action = cpu_to_le16(MWL8K_STA_ACTION_REMOVE);
4178
aa21d0f6 4179 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
3f5610ff
LB		 4180 kfree(cmd);
4181
4182 return rc;
4183}
4184
fcdc403c
NS		 4185/*
4186 * CMD_UPDATE_ENCRYPTION.
4187 */
4188
4189#define MAX_ENCR_KEY_LENGTH 16
4190#define MIC_KEY_LENGTH 8
4191
4192struct mwl8k_cmd_update_encryption {
4193 struct mwl8k_cmd_pkt header;
4194
4195 __le32 action;
4196 __le32 reserved;
4197 __u8 mac_addr[6];
4198 __u8 encr_type;
4199
ba30c4a5 4200} __packed;
fcdc403c
NS		 4201
4202struct mwl8k_cmd_set_key {
4203 struct mwl8k_cmd_pkt header;
4204
4205 __le32 action;
4206 __le32 reserved;
4207 __le16 length;
4208 __le16 key_type_id;
4209 __le32 key_info;
4210 __le32 key_id;
4211 __le16 key_len;
4212 __u8 key_material[MAX_ENCR_KEY_LENGTH];
4213 __u8 tkip_tx_mic_key[MIC_KEY_LENGTH];
4214 __u8 tkip_rx_mic_key[MIC_KEY_LENGTH];
4215 __le16 tkip_rsc_low;
4216 __le32 tkip_rsc_high;
4217 __le16 tkip_tsc_low;
4218 __le32 tkip_tsc_high;
4219 __u8 mac_addr[6];
ba30c4a5 4220} __packed;
fcdc403c
NS		 4221
4222enum {
4223 MWL8K_ENCR_ENABLE,
4224 MWL8K_ENCR_SET_KEY,
4225 MWL8K_ENCR_REMOVE_KEY,
4226 MWL8K_ENCR_SET_GROUP_KEY,
4227};
4228
4229#define MWL8K_UPDATE_ENCRYPTION_TYPE_WEP 0
4230#define MWL8K_UPDATE_ENCRYPTION_TYPE_DISABLE 1
4231#define MWL8K_UPDATE_ENCRYPTION_TYPE_TKIP 4
4232#define MWL8K_UPDATE_ENCRYPTION_TYPE_MIXED 7
4233#define MWL8K_UPDATE_ENCRYPTION_TYPE_AES 8
4234
4235enum {
4236 MWL8K_ALG_WEP,
4237 MWL8K_ALG_TKIP,
4238 MWL8K_ALG_CCMP,
4239};
4240
4241#define MWL8K_KEY_FLAG_TXGROUPKEY 0x00000004
4242#define MWL8K_KEY_FLAG_PAIRWISE 0x00000008
4243#define MWL8K_KEY_FLAG_TSC_VALID 0x00000040
4244#define MWL8K_KEY_FLAG_WEP_TXKEY 0x01000000
4245#define MWL8K_KEY_FLAG_MICKEY_VALID 0x02000000
4246
4247static int mwl8k_cmd_update_encryption_enable(struct ieee80211_hw *hw,
4248 struct ieee80211_vif *vif,
4249 u8 *addr,
4250 u8 encr_type)
4251{
4252 struct mwl8k_cmd_update_encryption *cmd;
4253 int rc;
4254
4255 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
4256 if (cmd == NULL)
4257 return -ENOMEM;
4258
4259 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_ENCRYPTION);
4260 cmd->header.length = cpu_to_le16(sizeof(*cmd));
4261 cmd->action = cpu_to_le32(MWL8K_ENCR_ENABLE);
4262 memcpy(cmd->mac_addr, addr, ETH_ALEN);
4263 cmd->encr_type = encr_type;
4264
4265 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
4266 kfree(cmd);
4267
4268 return rc;
4269}
4270
4271static int mwl8k_encryption_set_cmd_info(struct mwl8k_cmd_set_key *cmd,
4272 u8 *addr,
4273 struct ieee80211_key_conf *key)
4274{
4275 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_ENCRYPTION);
4276 cmd->header.length = cpu_to_le16(sizeof(*cmd));
4277 cmd->length = cpu_to_le16(sizeof(*cmd) -
4278 offsetof(struct mwl8k_cmd_set_key, length));
4279 cmd->key_id = cpu_to_le32(key->keyidx);
4280 cmd->key_len = cpu_to_le16(key->keylen);
4281 memcpy(cmd->mac_addr, addr, ETH_ALEN);
4282
4283 switch (key->cipher) {
4284 case WLAN_CIPHER_SUITE_WEP40:
4285 case WLAN_CIPHER_SUITE_WEP104:
4286 cmd->key_type_id = cpu_to_le16(MWL8K_ALG_WEP);
4287 if (key->keyidx == 0)
4288 cmd->key_info = cpu_to_le32(MWL8K_KEY_FLAG_WEP_TXKEY);
4289
4290 break;
4291 case WLAN_CIPHER_SUITE_TKIP:
4292 cmd->key_type_id = cpu_to_le16(MWL8K_ALG_TKIP);
4293 cmd->key_info = (key->flags & IEEE80211_KEY_FLAG_PAIRWISE)
4294 ? cpu_to_le32(MWL8K_KEY_FLAG_PAIRWISE)
4295 : cpu_to_le32(MWL8K_KEY_FLAG_TXGROUPKEY);
4296 cmd->key_info |= cpu_to_le32(MWL8K_KEY_FLAG_MICKEY_VALID
4297 | MWL8K_KEY_FLAG_TSC_VALID);
4298 break;
4299 case WLAN_CIPHER_SUITE_CCMP:
4300 cmd->key_type_id = cpu_to_le16(MWL8K_ALG_CCMP);
4301 cmd->key_info = (key->flags & IEEE80211_KEY_FLAG_PAIRWISE)
4302 ? cpu_to_le32(MWL8K_KEY_FLAG_PAIRWISE)
4303 : cpu_to_le32(MWL8K_KEY_FLAG_TXGROUPKEY);
4304 break;
4305 default:
4306 return -ENOTSUPP;
4307 }
4308
4309 return 0;
4310}
4311
4312static int mwl8k_cmd_encryption_set_key(struct ieee80211_hw *hw,
4313 struct ieee80211_vif *vif,
4314 u8 *addr,
4315 struct ieee80211_key_conf *key)
4316{
4317 struct mwl8k_cmd_set_key *cmd;
4318 int rc;
4319 int keymlen;
4320 u32 action;
4321 u8 idx;
4322 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
4323
4324 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
4325 if (cmd == NULL)
4326 return -ENOMEM;
4327
4328 rc = mwl8k_encryption_set_cmd_info(cmd, addr, key);
4329 if (rc < 0)
4330 goto done;
4331
4332 idx = key->keyidx;
4333
4334 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE)
4335 action = MWL8K_ENCR_SET_KEY;
4336 else
4337 action = MWL8K_ENCR_SET_GROUP_KEY;
4338
4339 switch (key->cipher) {
4340 case WLAN_CIPHER_SUITE_WEP40:
4341 case WLAN_CIPHER_SUITE_WEP104:
4342 if (!mwl8k_vif->wep_key_conf[idx].enabled) {
4343 memcpy(mwl8k_vif->wep_key_conf[idx].key, key,
4344 sizeof(*key) + key->keylen);
4345 mwl8k_vif->wep_key_conf[idx].enabled = 1;
4346 }
4347
9b571e24 4348 keymlen = key->keylen;
fcdc403c
NS		 4349 action = MWL8K_ENCR_SET_KEY;
4350 break;
4351 case WLAN_CIPHER_SUITE_TKIP:
4352 keymlen = MAX_ENCR_KEY_LENGTH + 2 * MIC_KEY_LENGTH;
4353 break;
4354 case WLAN_CIPHER_SUITE_CCMP:
4355 keymlen = key->keylen;
4356 break;
4357 default:
4358 rc = -ENOTSUPP;
4359 goto done;
4360 }
4361
4362 memcpy(cmd->key_material, key->key, keymlen);
4363 cmd->action = cpu_to_le32(action);
4364
4365 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
4366done:
4367 kfree(cmd);
4368
4369 return rc;
4370}
4371
4372static int mwl8k_cmd_encryption_remove_key(struct ieee80211_hw *hw,
4373 struct ieee80211_vif *vif,
4374 u8 *addr,
4375 struct ieee80211_key_conf *key)
4376{
4377 struct mwl8k_cmd_set_key *cmd;
4378 int rc;
4379 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
4380
4381 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
4382 if (cmd == NULL)
4383 return -ENOMEM;
4384
4385 rc = mwl8k_encryption_set_cmd_info(cmd, addr, key);
4386 if (rc < 0)
4387 goto done;
4388
4389 if (key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
d981e059 4390 key->cipher == WLAN_CIPHER_SUITE_WEP104)
fcdc403c
NS		 4391 mwl8k_vif->wep_key_conf[key->keyidx].enabled = 0;
4392
4393 cmd->action = cpu_to_le32(MWL8K_ENCR_REMOVE_KEY);
4394
4395 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
4396done:
4397 kfree(cmd);
4398
4399 return rc;
4400}
4401
4402static int mwl8k_set_key(struct ieee80211_hw *hw,
4403 enum set_key_cmd cmd_param,
4404 struct ieee80211_vif *vif,
4405 struct ieee80211_sta *sta,
4406 struct ieee80211_key_conf *key)
4407{
4408 int rc = 0;
4409 u8 encr_type;
4410 u8 *addr;
4411 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
751930cb 4412 struct mwl8k_priv *priv = hw->priv;
fcdc403c 4413
751930cb 4414 if (vif->type == NL80211_IFTYPE_STATION && !priv->ap_fw)
fcdc403c
NS		 4415 return -EOPNOTSUPP;
4416
4417 if (sta == NULL)
ff7e9f99 4418 addr = vif->addr;
fcdc403c
NS		 4419 else
4420 addr = sta->addr;
4421
4422 if (cmd_param == SET_KEY) {
fcdc403c
NS		 4423 rc = mwl8k_cmd_encryption_set_key(hw, vif, addr, key);
4424 if (rc)
4425 goto out;
4426
4427 if ((key->cipher == WLAN_CIPHER_SUITE_WEP40)
4428 || (key->cipher == WLAN_CIPHER_SUITE_WEP104))
4429 encr_type = MWL8K_UPDATE_ENCRYPTION_TYPE_WEP;
4430 else
4431 encr_type = MWL8K_UPDATE_ENCRYPTION_TYPE_MIXED;
4432
4433 rc = mwl8k_cmd_update_encryption_enable(hw, vif, addr,
4434 encr_type);
4435 if (rc)
4436 goto out;
4437
4438 mwl8k_vif->is_hw_crypto_enabled = true;
4439
4440 } else {
4441 rc = mwl8k_cmd_encryption_remove_key(hw, vif, addr, key);
4442
4443 if (rc)
4444 goto out;
fcdc403c
NS		 4445 }
4446out:
4447 return rc;
4448}
4449
55489b6e
LB		 4450/*
4451 * CMD_UPDATE_STADB.
4452 */
25d81b1e
LB		 4453struct ewc_ht_info {
4454 __le16 control1;
4455 __le16 control2;
4456 __le16 control3;
ba2d3587 4457} __packed;
25d81b1e
LB		 4458
4459struct peer_capability_info {
4460 /* Peer type - AP vs. STA. */
4461 __u8 peer_type;
4462
4463 /* Basic 802.11 capabilities from assoc resp. */
4464 __le16 basic_caps;
4465
4466 /* Set if peer supports 802.11n high throughput (HT). */
4467 __u8 ht_support;
4468
4469 /* Valid if HT is supported. */
4470 __le16 ht_caps;
4471 __u8 extended_ht_caps;
4472 struct ewc_ht_info ewc_info;
4473
4474 /* Legacy rate table. Intersection of our rates and peer rates. */
4475 __u8 legacy_rates[12];
4476
4477 /* HT rate table. Intersection of our rates and peer rates. */
4478 __u8 ht_rates[16];
4479 __u8 pad[16];
4480
4481 /* If set, interoperability mode, no proprietary extensions. */
4482 __u8 interop;
4483 __u8 pad2;
4484 __u8 station_id;
4485 __le16 amsdu_enabled;
ba2d3587 4486} __packed;
25d81b1e 4487
55489b6e
LB		 4488struct mwl8k_cmd_update_stadb {
4489 struct mwl8k_cmd_pkt header;
4490
4491 /* See STADB_ACTION_TYPE */
4492 __le32 action;
4493
4494 /* Peer MAC address */
4495 __u8 peer_addr[ETH_ALEN];
4496
4497 __le32 reserved;
4498
4499 /* Peer info - valid during add/update. */
4500 struct peer_capability_info peer_info;
ba2d3587 4501} __packed;
55489b6e 4502
a680400e
LB		 4503#define MWL8K_STA_DB_MODIFY_ENTRY 1
4504#define MWL8K_STA_DB_DEL_ENTRY 2
4505
4506/* Peer Entry flags - used to define the type of the peer node */
4507#define MWL8K_PEER_TYPE_ACCESSPOINT 2
4508
4509static int mwl8k_cmd_update_stadb_add(struct ieee80211_hw *hw,
c6e96010 4510 struct ieee80211_vif *vif,
13935e2c 4511 struct ieee80211_sta *sta)
55489b6e 4512{
55489b6e 4513 struct mwl8k_cmd_update_stadb *cmd;
a680400e 4514 struct peer_capability_info *p;
8707d026 4515 u32 rates;
55489b6e
LB		 4516 int rc;
4517
4518 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
4519 if (cmd == NULL)
4520 return -ENOMEM;
4521
4522 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
4523 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a680400e 4524 cmd->action = cpu_to_le32(MWL8K_STA_DB_MODIFY_ENTRY);
13935e2c 4525 memcpy(cmd->peer_addr, sta->addr, ETH_ALEN);
55489b6e 4526
a680400e
LB		 4527 p = &cmd->peer_info;
4528 p->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
4529 p->basic_caps = cpu_to_le16(vif->bss_conf.assoc_capability);
13935e2c 4530 p->ht_support = sta->ht_cap.ht_supported;
b603742f 4531 p->ht_caps = cpu_to_le16(sta->ht_cap.cap);
13935e2c
LB		 4532 p->extended_ht_caps = (sta->ht_cap.ampdu_factor & 3) |
4533 ((sta->ht_cap.ampdu_density & 7) << 2);
675a0b04 4534 if (hw->conf.chandef.chan->band == IEEE80211_BAND_2GHZ)
8707d026
LB		 4535 rates = sta->supp_rates[IEEE80211_BAND_2GHZ];
4536 else
4537 rates = sta->supp_rates[IEEE80211_BAND_5GHZ] << 5;
4538 legacy_rate_mask_to_array(p->legacy_rates, rates);
13935e2c 4539 memcpy(p->ht_rates, sta->ht_cap.mcs.rx_mask, 16);
a680400e
LB		 4540 p->interop = 1;
4541 p->amsdu_enabled = 0;
4542
4543 rc = mwl8k_post_cmd(hw, &cmd->header);
c4f74d35
NZ		 4544 if (!rc)
4545 rc = p->station_id;
a680400e
LB		 4546 kfree(cmd);
4547
c4f74d35 4548 return rc;
a680400e
LB		 4549}
4550
4551static int mwl8k_cmd_update_stadb_del(struct ieee80211_hw *hw,
4552 struct ieee80211_vif *vif, u8 *addr)
4553{
4554 struct mwl8k_cmd_update_stadb *cmd;
4555 int rc;
4556
4557 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
4558 if (cmd == NULL)
4559 return -ENOMEM;
4560
4561 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
4562 cmd->header.length = cpu_to_le16(sizeof(*cmd));
4563 cmd->action = cpu_to_le32(MWL8K_STA_DB_DEL_ENTRY);
bbfd9128 4564 memcpy(cmd->peer_addr, addr, ETH_ALEN);
55489b6e 4565
a680400e 4566 rc = mwl8k_post_cmd(hw, &cmd->header);
55489b6e
LB		 4567 kfree(cmd);
4568
4569 return rc;
4570}
4571
a66098da
LB		 4572
4573/*
4574 * Interrupt handling.
4575 */
4576static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
4577{
4578 struct ieee80211_hw *hw = dev_id;
4579 struct mwl8k_priv *priv = hw->priv;
4580 u32 status;
4581
4582 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
a66098da
LB		 4583 if (!status)
4584 return IRQ_NONE;
4585
1e9f9de3
LB		 4586 if (status & MWL8K_A2H_INT_TX_DONE) {
4587 status &= ~MWL8K_A2H_INT_TX_DONE;
4588 tasklet_schedule(&priv->poll_tx_task);
4589 }
4590
a66098da 4591 if (status & MWL8K_A2H_INT_RX_READY) {
67e2eb27
LB		 4592 status &= ~MWL8K_A2H_INT_RX_READY;
4593 tasklet_schedule(&priv->poll_rx_task);
a66098da
LB		 4594 }
4595
3aefc37e 4596 if (status & MWL8K_A2H_INT_BA_WATCHDOG) {
c27a54d3
YAP		 4597 iowrite32(~MWL8K_A2H_INT_BA_WATCHDOG,
4598 priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
4599
4600 atomic_inc(&priv->watchdog_event_pending);
3aefc37e
NS		 4601 status &= ~MWL8K_A2H_INT_BA_WATCHDOG;
4602 ieee80211_queue_work(hw, &priv->watchdog_ba_handle);
4603 }
4604
67e2eb27
LB		 4605 if (status)
4606 iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
4607
a66098da 4608 if (status & MWL8K_A2H_INT_OPC_DONE) {
618952a7 4609 if (priv->hostcmd_wait != NULL)
a66098da 4610 complete(priv->hostcmd_wait);
a66098da
LB		 4611 }
4612
4613 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
618952a7 4614 if (!mutex_is_locked(&priv->fw_mutex) &&
88de754a 4615 priv->radio_on && priv->pending_tx_pkts)
618952a7 4616 mwl8k_tx_start(priv);
a66098da
LB		 4617 }
4618
4619 return IRQ_HANDLED;
4620}
4621
1e9f9de3
LB		 4622static void mwl8k_tx_poll(unsigned long data)
4623{
4624 struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
4625 struct mwl8k_priv *priv = hw->priv;
4626 int limit;
4627 int i;
4628
4629 limit = 32;
4630
4631 spin_lock_bh(&priv->tx_lock);
4632
e600707b 4633 for (i = 0; i < mwl8k_tx_queues(priv); i++)
1e9f9de3
LB		 4634 limit -= mwl8k_txq_reclaim(hw, i, limit, 0);
4635
4636 if (!priv->pending_tx_pkts && priv->tx_wait != NULL) {
4637 complete(priv->tx_wait);
4638 priv->tx_wait = NULL;
4639 }
4640
4641 spin_unlock_bh(&priv->tx_lock);
4642
4643 if (limit) {
4644 writel(~MWL8K_A2H_INT_TX_DONE,
4645 priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
4646 } else {
4647 tasklet_schedule(&priv->poll_tx_task);
4648 }
4649}
4650
67e2eb27
LB		 4651static void mwl8k_rx_poll(unsigned long data)
4652{
4653 struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
4654 struct mwl8k_priv *priv = hw->priv;
4655 int limit;
4656
4657 limit = 32;
4658 limit -= rxq_process(hw, 0, limit);
4659 limit -= rxq_refill(hw, 0, limit);
4660
4661 if (limit) {
4662 writel(~MWL8K_A2H_INT_RX_READY,
4663 priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
4664 } else {
4665 tasklet_schedule(&priv->poll_rx_task);
4666 }
4667}
4668
a66098da
LB		 4669
4670/*
4671 * Core driver operations.
4672 */
36323f81
TH		 4673static void mwl8k_tx(struct ieee80211_hw *hw,
4674 struct ieee80211_tx_control *control,
4675 struct sk_buff *skb)
a66098da
LB		 4676{
4677 struct mwl8k_priv *priv = hw->priv;
4678 int index = skb_get_queue_mapping(skb);
a66098da 4679
9189c100 4680 if (!priv->radio_on) {
c96c31e4
JP		 4681 wiphy_debug(hw->wiphy,
4682 "dropped TX frame since radio disabled\n");
a66098da 4683 dev_kfree_skb(skb);
7bb45683 4684 return;
a66098da
LB		 4685 }
4686
36323f81 4687 mwl8k_txq_xmit(hw, index, control->sta, skb);
a66098da
LB		 4688}
4689
a66098da
LB		 4690static int mwl8k_start(struct ieee80211_hw *hw)
4691{
a66098da
LB		 4692 struct mwl8k_priv *priv = hw->priv;
4693 int rc;
4694
a0607fd3 4695 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
a66098da
LB		 4696 IRQF_SHARED, MWL8K_NAME, hw);
4697 if (rc) {
bf3ca7f7 4698 priv->irq = -1;
5db55844 4699 wiphy_err(hw->wiphy, "failed to register IRQ handler\n");
2ec610cb 4700 return -EIO;
a66098da 4701 }
bf3ca7f7 4702 priv->irq = priv->pdev->irq;
a66098da 4703
67e2eb27 4704 /* Enable TX reclaim and RX tasklets. */
1e9f9de3 4705 tasklet_enable(&priv->poll_tx_task);
67e2eb27 4706 tasklet_enable(&priv->poll_rx_task);
2ec610cb 4707
a66098da 4708 /* Enable interrupts */
c23b5a69 4709 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
12488e01
NS		 4710 iowrite32(MWL8K_A2H_EVENTS,
4711 priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
a66098da 4712
2ec610cb
LB		 4713 rc = mwl8k_fw_lock(hw);
4714 if (!rc) {
55489b6e 4715 rc = mwl8k_cmd_radio_enable(hw);
a66098da 4716
5e4cf166
LB		 4717 if (!priv->ap_fw) {
4718 if (!rc)
55489b6e 4719 rc = mwl8k_cmd_enable_sniffer(hw, 0);
a66098da 4720
5e4cf166
LB		 4721 if (!rc)
4722 rc = mwl8k_cmd_set_pre_scan(hw);
4723
4724 if (!rc)
4725 rc = mwl8k_cmd_set_post_scan(hw,
4726 "\x00\x00\x00\x00\x00\x00");
4727 }
2ec610cb
LB		 4728
4729 if (!rc)
55489b6e 4730 rc = mwl8k_cmd_set_rateadapt_mode(hw, 0);
a66098da 4731
2ec610cb 4732 if (!rc)
55489b6e 4733 rc = mwl8k_cmd_set_wmm_mode(hw, 0);
a66098da 4734
2ec610cb
LB		 4735 mwl8k_fw_unlock(hw);
4736 }
4737
4738 if (rc) {
4739 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
4740 free_irq(priv->pdev->irq, hw);
bf3ca7f7 4741 priv->irq = -1;
1e9f9de3 4742 tasklet_disable(&priv->poll_tx_task);
67e2eb27 4743 tasklet_disable(&priv->poll_rx_task);
4850b6d3
NS		 4744 } else {
4745 ieee80211_wake_queues(hw);
2ec610cb 4746 }
a66098da
LB		 4747
4748 return rc;
4749}
4750
a66098da
LB		 4751static void mwl8k_stop(struct ieee80211_hw *hw)
4752{
a66098da
LB		 4753 struct mwl8k_priv *priv = hw->priv;
4754 int i;
4755
6b6accc3
YAP		 4756 if (!priv->hw_restart_in_progress)
4757 mwl8k_cmd_radio_disable(hw);
a66098da
LB		 4758
4759 ieee80211_stop_queues(hw);
4760
a66098da 4761 /* Disable interrupts */
a66098da 4762 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
bf3ca7f7
BC		 4763 if (priv->irq != -1) {
4764 free_irq(priv->pdev->irq, hw);
4765 priv->irq = -1;
4766 }
a66098da
LB		 4767
4768 /* Stop finalize join worker */
4769 cancel_work_sync(&priv->finalize_join_worker);
3aefc37e 4770 cancel_work_sync(&priv->watchdog_ba_handle);
a66098da
LB		 4771 if (priv->beacon_skb != NULL)
4772 dev_kfree_skb(priv->beacon_skb);
4773
67e2eb27 4774 /* Stop TX reclaim and RX tasklets. */
1e9f9de3 4775 tasklet_disable(&priv->poll_tx_task);
67e2eb27 4776 tasklet_disable(&priv->poll_rx_task);
a66098da 4777
a66098da 4778 /* Return all skbs to mac80211 */
e600707b 4779 for (i = 0; i < mwl8k_tx_queues(priv); i++)
efb7c49a 4780 mwl8k_txq_reclaim(hw, i, INT_MAX, 1);
a66098da
LB		 4781}
4782
0863ade8
BC		 4783static int mwl8k_reload_firmware(struct ieee80211_hw *hw, char *fw_image);
4784
a66098da 4785static int mwl8k_add_interface(struct ieee80211_hw *hw,
f5bb87cf 4786 struct ieee80211_vif *vif)
a66098da
LB		 4787{
4788 struct mwl8k_priv *priv = hw->priv;
4789 struct mwl8k_vif *mwl8k_vif;
ee0ddf18 4790 u32 macids_supported;
0863ade8
BC		 4791 int macid, rc;
4792 struct mwl8k_device_info *di;
a66098da 4793
a43c49a8
LB		 4794 /*
4795 * Reject interface creation if sniffer mode is active, as
4796 * STA operation is mutually exclusive with hardware sniffer
b64fe619 4797 * mode. (Sniffer mode is only used on STA firmware.)
a43c49a8
LB		 4798 */
4799 if (priv->sniffer_enabled) {
c96c31e4
JP		 4800 wiphy_info(hw->wiphy,
4801 "unable to create STA interface because sniffer mode is enabled\n");
a43c49a8
LB		 4802 return -EINVAL;
4803 }
4804
0863ade8 4805 di = priv->device_info;
ee0ddf18
LB		 4806 switch (vif->type) {
4807 case NL80211_IFTYPE_AP:
0863ade8
BC		 4808 if (!priv->ap_fw && di->fw_image_ap) {
4809 /* we must load the ap fw to meet this request */
4810 if (!list_empty(&priv->vif_list))
4811 return -EBUSY;
4812 rc = mwl8k_reload_firmware(hw, di->fw_image_ap);
4813 if (rc)
4814 return rc;
4815 }
ee0ddf18
LB		 4816 macids_supported = priv->ap_macids_supported;
4817 break;
4818 case NL80211_IFTYPE_STATION:
0863ade8 4819 if (priv->ap_fw && di->fw_image_sta) {
d59c1cfd
YAP		 4820 if (!list_empty(&priv->vif_list)) {
4821 wiphy_warn(hw->wiphy, "AP interface is running.\n"
4822 "Adding STA interface for WDS");
4823 } else {
4824 /* we must load the sta fw to
4825 * meet this request.
4826 */
4827 rc = mwl8k_reload_firmware(hw,
4828 di->fw_image_sta);
4829 if (rc)
4830 return rc;
4831 }
0863ade8 4832 }
ee0ddf18
LB		 4833 macids_supported = priv->sta_macids_supported;
4834 break;
4835 default:
4836 return -EINVAL;
4837 }
4838
4839 macid = ffs(macids_supported & ~priv->macids_used);
4840 if (!macid--)
4841 return -EBUSY;
4842
f5bb87cf 4843 /* Setup driver private area. */
1ed32e4f 4844 mwl8k_vif = MWL8K_VIF(vif);
a66098da 4845 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
f5bb87cf 4846 mwl8k_vif->vif = vif;
ee0ddf18 4847 mwl8k_vif->macid = macid;
a66098da 4848 mwl8k_vif->seqno = 0;
d9a07d49
NS		 4849 memcpy(mwl8k_vif->bssid, vif->addr, ETH_ALEN);
4850 mwl8k_vif->is_hw_crypto_enabled = false;
a66098da 4851
aa21d0f6
LB		 4852 /* Set the mac address. */
4853 mwl8k_cmd_set_mac_addr(hw, vif, vif->addr);
4854
d994a1c8 4855 if (vif->type == NL80211_IFTYPE_AP)
aa21d0f6
LB		 4856 mwl8k_cmd_set_new_stn_add_self(hw, vif);
4857
ee0ddf18 4858 priv->macids_used |= 1 << mwl8k_vif->macid;
f5bb87cf 4859 list_add_tail(&mwl8k_vif->list, &priv->vif_list);
a66098da
LB		 4860
4861 return 0;
4862}
4863
6b6accc3
YAP		 4864static void mwl8k_remove_vif(struct mwl8k_priv *priv, struct mwl8k_vif *vif)
4865{
4866 /* Has ieee80211_restart_hw re-added the removed interfaces? */
4867 if (!priv->macids_used)
4868 return;
4869
4870 priv->macids_used &= ~(1 << vif->macid);
4871 list_del(&vif->list);
4872}
4873
a66098da 4874static void mwl8k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 4875 struct ieee80211_vif *vif)
a66098da
LB		 4876{
4877 struct mwl8k_priv *priv = hw->priv;
f5bb87cf 4878 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
a66098da 4879
d994a1c8 4880 if (vif->type == NL80211_IFTYPE_AP)
b64fe619
LB		 4881 mwl8k_cmd_set_new_stn_del(hw, vif, vif->addr);
4882
197a4e4e 4883 mwl8k_cmd_del_mac_addr(hw, vif, vif->addr);
32060e1b 4884
6b6accc3
YAP		 4885 mwl8k_remove_vif(priv, mwl8k_vif);
4886}
4887
4888static void mwl8k_hw_restart_work(struct work_struct *work)
4889{
4890 struct mwl8k_priv *priv =
4891 container_of(work, struct mwl8k_priv, fw_reload);
4892 struct ieee80211_hw *hw = priv->hw;
4893 struct mwl8k_device_info *di;
4894 int rc;
4895
4896 /* If some command is waiting for a response, clear it */
4897 if (priv->hostcmd_wait != NULL) {
4898 complete(priv->hostcmd_wait);
4899 priv->hostcmd_wait = NULL;
4900 }
4901
4902 priv->hw_restart_owner = current;
4903 di = priv->device_info;
4904 mwl8k_fw_lock(hw);
4905
4906 if (priv->ap_fw)
4907 rc = mwl8k_reload_firmware(hw, di->fw_image_ap);
4908 else
4909 rc = mwl8k_reload_firmware(hw, di->fw_image_sta);
4910
4911 if (rc)
4912 goto fail;
4913
4914 priv->hw_restart_owner = NULL;
4915 priv->hw_restart_in_progress = false;
4916
4917 /*
4918 * This unlock will wake up the queues and
4919 * also opens the command path for other
4920 * commands
4921 */
4922 mwl8k_fw_unlock(hw);
4923
4924 ieee80211_restart_hw(hw);
4925
4926 wiphy_err(hw->wiphy, "Firmware restarted successfully\n");
4927
4928 return;
4929fail:
4930 mwl8k_fw_unlock(hw);
4931
4932 wiphy_err(hw->wiphy, "Firmware restart failed\n");
a66098da
LB		 4933}
4934
ee03a932 4935static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
a66098da 4936{
a66098da
LB		 4937 struct ieee80211_conf *conf = &hw->conf;
4938 struct mwl8k_priv *priv = hw->priv;
ee03a932 4939 int rc;
a66098da 4940
ee03a932
LB		 4941 rc = mwl8k_fw_lock(hw);
4942 if (rc)
4943 return rc;
a66098da 4944
fe21bb02
JG		 4945 if (conf->flags & IEEE80211_CONF_IDLE)
4946 rc = mwl8k_cmd_radio_disable(hw);
4947 else
4948 rc = mwl8k_cmd_radio_enable(hw);
ee03a932
LB		 4949 if (rc)
4950 goto out;
a66098da 4951
0f4316b9
YAP		 4952 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
4953 rc = mwl8k_cmd_set_rf_channel(hw, conf);
4954 if (rc)
4955 goto out;
4956 }
ee03a932 4957
a66098da
LB		 4958 if (conf->power_level > 18)
4959 conf->power_level = 18;
a66098da 4960
08b06347 4961 if (priv->ap_fw) {
03217087
NS		 4962
4963 if (conf->flags & IEEE80211_CONF_CHANGE_POWER) {
4964 rc = mwl8k_cmd_tx_power(hw, conf, conf->power_level);
4965 if (rc)
4966 goto out;
4967 }
41fdf097 4968
da62b761 4969
08b06347 4970 } else {
41fdf097
NS		 4971 rc = mwl8k_cmd_rf_tx_power(hw, conf->power_level);
4972 if (rc)
4973 goto out;
08b06347
LB		 4974 rc = mwl8k_cmd_mimo_config(hw, 0x7, 0x7);
4975 }
a66098da 4976
ee03a932
LB		 4977out:
4978 mwl8k_fw_unlock(hw);
a66098da 4979
ee03a932 4980 return rc;
a66098da
LB		 4981}
4982
b64fe619
LB		 4983static void
4984mwl8k_bss_info_changed_sta(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4985 struct ieee80211_bss_conf *info, u32 changed)
a66098da 4986{
a66098da 4987 struct mwl8k_priv *priv = hw->priv;
ba30c4a5 4988 u32 ap_legacy_rates = 0;
13935e2c 4989 u8 ap_mcs_rates[16];
3a980d0a
LB		 4990 int rc;
4991
c3cbbe8a 4992 if (mwl8k_fw_lock(hw))
3a980d0a 4993 return;
a66098da 4994
c3cbbe8a
LB		 4995 /*
4996 * No need to capture a beacon if we're no longer associated.
4997 */
4998 if ((changed & BSS_CHANGED_ASSOC) && !vif->bss_conf.assoc)
4999 priv->capture_beacon = false;
3a980d0a 5000
c3cbbe8a 5001 /*
13935e2c 5002 * Get the AP's legacy and MCS rates.
c3cbbe8a 5003 */
7dc6a7a7 5004 if (vif->bss_conf.assoc) {
c6e96010 5005 struct ieee80211_sta *ap;
c97470dd 5006
c6e96010 5007 rcu_read_lock();
c6e96010 5008
c3cbbe8a
LB		 5009 ap = ieee80211_find_sta(vif, vif->bss_conf.bssid);
5010 if (ap == NULL) {
5011 rcu_read_unlock();
c6e96010 5012 goto out;
c3cbbe8a
LB		 5013 }
5014
675a0b04 5015 if (hw->conf.chandef.chan->band == IEEE80211_BAND_2GHZ) {
8707d026
LB		 5016 ap_legacy_rates = ap->supp_rates[IEEE80211_BAND_2GHZ];
5017 } else {
5018 ap_legacy_rates =
5019 ap->supp_rates[IEEE80211_BAND_5GHZ] << 5;
5020 }
13935e2c 5021 memcpy(ap_mcs_rates, ap->ht_cap.mcs.rx_mask, 16);
c3cbbe8a
LB		 5022
5023 rcu_read_unlock();
5024 }
c6e96010 5025
dcee7438
YAP		 5026 if ((changed & BSS_CHANGED_ASSOC) && vif->bss_conf.assoc &&
5027 !priv->ap_fw) {
13935e2c 5028 rc = mwl8k_cmd_set_rate(hw, vif, ap_legacy_rates, ap_mcs_rates);
3a980d0a
LB		 5029 if (rc)
5030 goto out;
a66098da 5031
b71ed2c6 5032 rc = mwl8k_cmd_use_fixed_rate_sta(hw);
3a980d0a
LB		 5033 if (rc)
5034 goto out;
dcee7438
YAP		 5035 } else {
5036 if ((changed & BSS_CHANGED_ASSOC) && vif->bss_conf.assoc &&
5037 priv->ap_fw) {
5038 int idx;
5039 int rate;
5040
5041 /* Use AP firmware specific rate command.
5042 */
5043 idx = ffs(vif->bss_conf.basic_rates);
5044 if (idx)
5045 idx--;
5046
675a0b04 5047 if (hw->conf.chandef.chan->band == IEEE80211_BAND_2GHZ)
dcee7438
YAP		 5048 rate = mwl8k_rates_24[idx].hw_value;
5049 else
5050 rate = mwl8k_rates_50[idx].hw_value;
5051
5052 mwl8k_cmd_use_fixed_rate_ap(hw, rate, rate);
5053 }
c3cbbe8a 5054 }
a66098da 5055
c3cbbe8a 5056 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
7dc6a7a7
LB		 5057 rc = mwl8k_set_radio_preamble(hw,
5058 vif->bss_conf.use_short_preamble);
3a980d0a
LB		 5059 if (rc)
5060 goto out;
c3cbbe8a 5061 }
a66098da 5062
dcee7438 5063 if ((changed & BSS_CHANGED_ERP_SLOT) && !priv->ap_fw) {
7dc6a7a7 5064 rc = mwl8k_cmd_set_slot(hw, vif->bss_conf.use_short_slot);
3a980d0a
LB		 5065 if (rc)
5066 goto out;
c3cbbe8a 5067 }
a66098da 5068
dcee7438 5069 if (vif->bss_conf.assoc && !priv->ap_fw &&
c97470dd
LB		 5070 (changed & (BSS_CHANGED_ASSOC | BSS_CHANGED_ERP_CTS_PROT |
5071 BSS_CHANGED_HT))) {
c3cbbe8a 5072 rc = mwl8k_cmd_set_aid(hw, vif, ap_legacy_rates);
3a980d0a
LB		 5073 if (rc)
5074 goto out;
c3cbbe8a 5075 }
a66098da 5076
c3cbbe8a
LB		 5077 if (vif->bss_conf.assoc &&
5078 (changed & (BSS_CHANGED_ASSOC | BSS_CHANGED_BEACON_INT))) {
a66098da
LB		 5079 /*
5080 * Finalize the join. Tell rx handler to process
5081 * next beacon from our BSSID.
5082 */
0a11dfc3 5083 memcpy(priv->capture_bssid, vif->bss_conf.bssid, ETH_ALEN);
a66098da 5084 priv->capture_beacon = true;
a66098da
LB		 5085 }
5086
3a980d0a
LB		 5087out:
5088 mwl8k_fw_unlock(hw);
a66098da
LB		 5089}
5090
b64fe619
LB		 5091static void
5092mwl8k_bss_info_changed_ap(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5093 struct ieee80211_bss_conf *info, u32 changed)
5094{
5095 int rc;
5096
5097 if (mwl8k_fw_lock(hw))
5098 return;
5099
5100 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
5101 rc = mwl8k_set_radio_preamble(hw,
5102 vif->bss_conf.use_short_preamble);
5103 if (rc)
5104 goto out;
5105 }
5106
5107 if (changed & BSS_CHANGED_BASIC_RATES) {
5108 int idx;
5109 int rate;
5110
5111 /*
5112 * Use lowest supported basic rate for multicasts
5113 * and management frames (such as probe responses --
5114 * beacons will always go out at 1 Mb/s).
5115 */
5116 idx = ffs(vif->bss_conf.basic_rates);
8707d026
LB		 5117 if (idx)
5118 idx--;
5119
675a0b04 5120 if (hw->conf.chandef.chan->band == IEEE80211_BAND_2GHZ)
8707d026
LB		 5121 rate = mwl8k_rates_24[idx].hw_value;
5122 else
5123 rate = mwl8k_rates_50[idx].hw_value;
b64fe619
LB		 5124
5125 mwl8k_cmd_use_fixed_rate_ap(hw, rate, rate);
5126 }
5127
5128 if (changed & (BSS_CHANGED_BEACON_INT | BSS_CHANGED_BEACON)) {
5129 struct sk_buff *skb;
5130
5131 skb = ieee80211_beacon_get(hw, vif);
5132 if (skb != NULL) {
aa21d0f6 5133 mwl8k_cmd_set_beacon(hw, vif, skb->data, skb->len);
b64fe619
LB		 5134 kfree_skb(skb);
5135 }
5136 }
5137
5138 if (changed & BSS_CHANGED_BEACON_ENABLED)
aa21d0f6 5139 mwl8k_cmd_bss_start(hw, vif, info->enable_beacon);
b64fe619
LB		 5140
5141out:
5142 mwl8k_fw_unlock(hw);
5143}
5144
5145static void
5146mwl8k_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5147 struct ieee80211_bss_conf *info, u32 changed)
5148{
41bf9119 5149 if (vif->type == NL80211_IFTYPE_STATION)
b64fe619 5150 mwl8k_bss_info_changed_sta(hw, vif, info, changed);
41bf9119 5151 if (vif->type == NL80211_IFTYPE_AP)
b64fe619
LB		 5152 mwl8k_bss_info_changed_ap(hw, vif, info, changed);
5153}
5154
e81cd2d6 5155static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
22bedad3 5156 struct netdev_hw_addr_list *mc_list)
e81cd2d6
LB		 5157{
5158 struct mwl8k_cmd_pkt *cmd;
5159
447ced07
LB		 5160 /*
5161 * Synthesize and return a command packet that programs the
5162 * hardware multicast address filter. At this point we don't
5163 * know whether FIF_ALLMULTI is being requested, but if it is,
5164 * we'll end up throwing this packet away and creating a new
5165 * one in mwl8k_configure_filter().
5166 */
22bedad3 5167 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_list);
e81cd2d6
LB		 5168
5169 return (unsigned long)cmd;
5170}
5171
a43c49a8
LB		 5172static int
5173mwl8k_configure_filter_sniffer(struct ieee80211_hw *hw,
5174 unsigned int changed_flags,
5175 unsigned int *total_flags)
5176{
5177 struct mwl8k_priv *priv = hw->priv;
5178
5179 /*
5180 * Hardware sniffer mode is mutually exclusive with STA
5181 * operation, so refuse to enable sniffer mode if a STA
5182 * interface is active.
5183 */
f5bb87cf 5184 if (!list_empty(&priv->vif_list)) {
a43c49a8 5185 if (net_ratelimit())
c96c31e4
JP		 5186 wiphy_info(hw->wiphy,
5187 "not enabling sniffer mode because STA interface is active\n");
a43c49a8
LB		 5188 return 0;
5189 }
5190
5191 if (!priv->sniffer_enabled) {
55489b6e 5192 if (mwl8k_cmd_enable_sniffer(hw, 1))
a43c49a8
LB		 5193 return 0;
5194 priv->sniffer_enabled = true;
5195 }
5196
5197 *total_flags &= FIF_PROMISC_IN_BSS | FIF_ALLMULTI |
5198 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL |
5199 FIF_OTHER_BSS;
5200
5201 return 1;
5202}
5203
f5bb87cf
LB		 5204static struct mwl8k_vif *mwl8k_first_vif(struct mwl8k_priv *priv)
5205{
5206 if (!list_empty(&priv->vif_list))
5207 return list_entry(priv->vif_list.next, struct mwl8k_vif, list);
5208
5209 return NULL;
5210}
5211
e6935ea1
LB		 5212static void mwl8k_configure_filter(struct ieee80211_hw *hw,
5213 unsigned int changed_flags,
5214 unsigned int *total_flags,
5215 u64 multicast)
5216{
5217 struct mwl8k_priv *priv = hw->priv;
a43c49a8
LB		 5218 struct mwl8k_cmd_pkt *cmd = (void *)(unsigned long)multicast;
5219
c0adae2c
LB		 5220 /*
5221 * AP firmware doesn't allow fine-grained control over
5222 * the receive filter.
5223 */
5224 if (priv->ap_fw) {
5225 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
5226 kfree(cmd);
5227 return;
5228 }
5229
a43c49a8
LB		 5230 /*
5231 * Enable hardware sniffer mode if FIF_CONTROL or
5232 * FIF_OTHER_BSS is requested.
5233 */
5234 if (*total_flags & (FIF_CONTROL | FIF_OTHER_BSS) &&
5235 mwl8k_configure_filter_sniffer(hw, changed_flags, total_flags)) {
5236 kfree(cmd);
5237 return;
5238 }
a66098da 5239
e6935ea1 5240 /* Clear unsupported feature flags */
447ced07 5241 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
a66098da 5242
90852f7a
LB		 5243 if (mwl8k_fw_lock(hw)) {
5244 kfree(cmd);
e6935ea1 5245 return;
90852f7a 5246 }
a66098da 5247
a43c49a8 5248 if (priv->sniffer_enabled) {
55489b6e 5249 mwl8k_cmd_enable_sniffer(hw, 0);
a43c49a8
LB		 5250 priv->sniffer_enabled = false;
5251 }
5252
e6935ea1 5253 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
77165d88
LB		 5254 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
5255 /*
5256 * Disable the BSS filter.
5257 */
e6935ea1 5258 mwl8k_cmd_set_pre_scan(hw);
77165d88 5259 } else {
f5bb87cf 5260 struct mwl8k_vif *mwl8k_vif;
0a11dfc3 5261 const u8 *bssid;
a94cc97e 5262
77165d88
LB		 5263 /*
5264 * Enable the BSS filter.
5265 *
5266 * If there is an active STA interface, use that
5267 * interface's BSSID, otherwise use a dummy one
5268 * (where the OUI part needs to be nonzero for
5269 * the BSSID to be accepted by POST_SCAN).
5270 */
f5bb87cf
LB		 5271 mwl8k_vif = mwl8k_first_vif(priv);
5272 if (mwl8k_vif != NULL)
5273 bssid = mwl8k_vif->vif->bss_conf.bssid;
5274 else
5275 bssid = "\x01\x00\x00\x00\x00\x00";
a94cc97e 5276
e6935ea1 5277 mwl8k_cmd_set_post_scan(hw, bssid);
a66098da
LB		 5278 }
5279 }
5280
447ced07
LB		 5281 /*
5282 * If FIF_ALLMULTI is being requested, throw away the command
5283 * packet that ->prepare_multicast() built and replace it with
5284 * a command packet that enables reception of all multicast
5285 * packets.
5286 */
5287 if (*total_flags & FIF_ALLMULTI) {
5288 kfree(cmd);
22bedad3 5289 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, NULL);
447ced07
LB		 5290 }
5291
5292 if (cmd != NULL) {
5293 mwl8k_post_cmd(hw, cmd);
5294 kfree(cmd);
e6935ea1 5295 }
a66098da 5296
e6935ea1 5297 mwl8k_fw_unlock(hw);
a66098da
LB		 5298}
5299
a66098da
LB		 5300static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
5301{
c2c2b12a 5302 return mwl8k_cmd_set_rts_threshold(hw, value);
a66098da
LB		 5303}
5304
4a6967b8
JB		 5305static int mwl8k_sta_remove(struct ieee80211_hw *hw,
5306 struct ieee80211_vif *vif,
5307 struct ieee80211_sta *sta)
3f5610ff
LB		 5308{
5309 struct mwl8k_priv *priv = hw->priv;
5310
4a6967b8
JB		 5311 if (priv->ap_fw)
5312 return mwl8k_cmd_set_new_stn_del(hw, vif, sta->addr);
5313 else
5314 return mwl8k_cmd_update_stadb_del(hw, vif, sta->addr);
bbfd9128
LB		 5315}
5316
4a6967b8
JB		 5317static int mwl8k_sta_add(struct ieee80211_hw *hw,
5318 struct ieee80211_vif *vif,
5319 struct ieee80211_sta *sta)
bbfd9128
LB		 5320{
5321 struct mwl8k_priv *priv = hw->priv;
4a6967b8 5322 int ret;
fcdc403c
NS		 5323 int i;
5324 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
5325 struct ieee80211_key_conf *key;
bbfd9128 5326
4a6967b8
JB		 5327 if (!priv->ap_fw) {
5328 ret = mwl8k_cmd_update_stadb_add(hw, vif, sta);
5329 if (ret >= 0) {
5330 MWL8K_STA(sta)->peer_id = ret;
17033543
NS		 5331 if (sta->ht_cap.ht_supported)
5332 MWL8K_STA(sta)->is_ampdu_allowed = true;
fcdc403c 5333 ret = 0;
4a6967b8 5334 }
bbfd9128 5335
d9a07d49
NS		 5336 } else {
5337 ret = mwl8k_cmd_set_new_stn_add(hw, vif, sta);
bbfd9128 5338 }
4a6967b8 5339
d9a07d49
NS		 5340 for (i = 0; i < NUM_WEP_KEYS; i++) {
5341 key = IEEE80211_KEY_CONF(mwl8k_vif->wep_key_conf[i].key);
5342 if (mwl8k_vif->wep_key_conf[i].enabled)
5343 mwl8k_set_key(hw, SET_KEY, vif, sta, key);
5344 }
fcdc403c 5345 return ret;
bbfd9128
LB		 5346}
5347
8a3a3c85
EP		 5348static int mwl8k_conf_tx(struct ieee80211_hw *hw,
5349 struct ieee80211_vif *vif, u16 queue,
a66098da
LB		 5350 const struct ieee80211_tx_queue_params *params)
5351{
3e4f542c 5352 struct mwl8k_priv *priv = hw->priv;
a66098da 5353 int rc;
a66098da 5354
3e4f542c
LB		 5355 rc = mwl8k_fw_lock(hw);
5356 if (!rc) {
e600707b 5357 BUG_ON(queue > MWL8K_TX_WMM_QUEUES - 1);
0863ade8
BC		 5358 memcpy(&priv->wmm_params[queue], params, sizeof(*params));
5359
3e4f542c 5360 if (!priv->wmm_enabled)
55489b6e 5361 rc = mwl8k_cmd_set_wmm_mode(hw, 1);
a66098da 5362
85c9205c 5363 if (!rc) {
e600707b 5364 int q = MWL8K_TX_WMM_QUEUES - 1 - queue;
85c9205c 5365 rc = mwl8k_cmd_set_edca_params(hw, q,
55489b6e
LB		 5366 params->cw_min,
5367 params->cw_max,
5368 params->aifs,
5369 params->txop);
85c9205c 5370 }
3e4f542c
LB		 5371
5372 mwl8k_fw_unlock(hw);
a66098da 5373 }
3e4f542c 5374
a66098da
LB		 5375 return rc;
5376}
5377
a66098da
LB		 5378static int mwl8k_get_stats(struct ieee80211_hw *hw,
5379 struct ieee80211_low_level_stats *stats)
5380{
55489b6e 5381 return mwl8k_cmd_get_stat(hw, stats);
a66098da
LB		 5382}
5383
0d462bbb
JL		 5384static int mwl8k_get_survey(struct ieee80211_hw *hw, int idx,
5385 struct survey_info *survey)
5386{
5387 struct mwl8k_priv *priv = hw->priv;
5388 struct ieee80211_conf *conf = &hw->conf;
031eb464
YAP		 5389 struct ieee80211_supported_band *sband;
5390
5391 if (priv->ap_fw) {
5392 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
5393
5394 if (sband && idx >= sband->n_channels) {
5395 idx -= sband->n_channels;
5396 sband = NULL;
5397 }
5398
5399 if (!sband)
5400 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
5401
5402 if (!sband || idx >= sband->n_channels)
5403 return -ENOENT;
5404
5405 memcpy(survey, &priv->survey[idx], sizeof(*survey));
5406 survey->channel = &sband->channels[idx];
5407
5408 return 0;
5409 }
0d462bbb
JL		 5410
5411 if (idx != 0)
5412 return -ENOENT;
5413
675a0b04 5414 survey->channel = conf->chandef.chan;
0d462bbb
JL		 5415 survey->filled = SURVEY_INFO_NOISE_DBM;
5416 survey->noise = priv->noise;
5417
5418 return 0;
5419}
5420
65f3ddcd
NS		 5421#define MAX_AMPDU_ATTEMPTS 5
5422
a2292d83
LB		 5423static int
5424mwl8k_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5425 enum ieee80211_ampdu_mlme_action action,
0b01f030
JB		 5426 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
5427 u8 buf_size)
a2292d83 5428{
65f3ddcd
NS		 5429
5430 int i, rc = 0;
5431 struct mwl8k_priv *priv = hw->priv;
5432 struct mwl8k_ampdu_stream *stream;
07f6dda1 5433 u8 *addr = sta->addr, idx;
fd712f5f 5434 struct mwl8k_sta *sta_info = MWL8K_STA(sta);
65f3ddcd
NS		 5435
5436 if (!(hw->flags & IEEE80211_HW_AMPDU_AGGREGATION))
5437 return -ENOTSUPP;
5438
5439 spin_lock(&priv->stream_lock);
5440 stream = mwl8k_lookup_stream(hw, addr, tid);
5441
a2292d83
LB		 5442 switch (action) {
5443 case IEEE80211_AMPDU_RX_START:
5444 case IEEE80211_AMPDU_RX_STOP:
65f3ddcd
NS		 5445 break;
5446 case IEEE80211_AMPDU_TX_START:
5447 /* By the time we get here the hw queues may contain outgoing
5448 * packets for this RA/TID that are not part of this BA
5449 * session. The hw will assign sequence numbers to these
5450 * packets as they go out. So if we query the hw for its next
5451 * sequence number and use that for the SSN here, it may end up
5452 * being wrong, which will lead to sequence number mismatch at
5453 * the recipient. To avoid this, we reset the sequence number
5454 * to O for the first MPDU in this BA stream.
5455 */
5456 *ssn = 0;
5457 if (stream == NULL) {
5458 /* This means that somebody outside this driver called
5459 * ieee80211_start_tx_ba_session. This is unexpected
5460 * because we do our own rate control. Just warn and
5461 * move on.
5462 */
5463 wiphy_warn(hw->wiphy, "Unexpected call to %s. "
5464 "Proceeding anyway.\n", __func__);
5465 stream = mwl8k_add_stream(hw, sta, tid);
5466 }
5467 if (stream == NULL) {
5468 wiphy_debug(hw->wiphy, "no free AMPDU streams\n");
5469 rc = -EBUSY;
5470 break;
5471 }
5472 stream->state = AMPDU_STREAM_IN_PROGRESS;
5473
5474 /* Release the lock before we do the time consuming stuff */
5475 spin_unlock(&priv->stream_lock);
5476 for (i = 0; i < MAX_AMPDU_ATTEMPTS; i++) {
fd712f5f
YAP		 5477
5478 /* Check if link is still valid */
5479 if (!sta_info->is_ampdu_allowed) {
5480 spin_lock(&priv->stream_lock);
5481 mwl8k_remove_stream(hw, stream);
5482 spin_unlock(&priv->stream_lock);
5483 return -EBUSY;
5484 }
5485
f95275c4 5486 rc = mwl8k_check_ba(hw, stream, vif);
65f3ddcd 5487
6b6accc3
YAP		 5488 /* If HW restart is in progress mwl8k_post_cmd will
5489 * return -EBUSY. Avoid retrying mwl8k_check_ba in
5490 * such cases
5491 */
5492 if (!rc || rc == -EBUSY)
65f3ddcd
NS		 5493 break;
5494 /*
5495 * HW queues take time to be flushed, give them
5496 * sufficient time
5497 */
5498
5499 msleep(1000);
5500 }
5501 spin_lock(&priv->stream_lock);
5502 if (rc) {
5503 wiphy_err(hw->wiphy, "Stream for tid %d busy after %d"
5504 " attempts\n", tid, MAX_AMPDU_ATTEMPTS);
5505 mwl8k_remove_stream(hw, stream);
5506 rc = -EBUSY;
5507 break;
5508 }
5509 ieee80211_start_tx_ba_cb_irqsafe(vif, addr, tid);
5510 break;
18b559d5
JB		 5511 case IEEE80211_AMPDU_TX_STOP_CONT:
5512 case IEEE80211_AMPDU_TX_STOP_FLUSH:
5513 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
eca107ff
YAP		 5514 if (stream) {
5515 if (stream->state == AMPDU_STREAM_ACTIVE) {
07f6dda1 5516 idx = stream->idx;
eca107ff 5517 spin_unlock(&priv->stream_lock);
07f6dda1 5518 mwl8k_destroy_ba(hw, idx);
eca107ff
YAP		 5519 spin_lock(&priv->stream_lock);
5520 }
5521 mwl8k_remove_stream(hw, stream);
65f3ddcd 5522 }
65f3ddcd
NS		 5523 ieee80211_stop_tx_ba_cb_irqsafe(vif, addr, tid);
5524 break;
5525 case IEEE80211_AMPDU_TX_OPERATIONAL:
5526 BUG_ON(stream == NULL);
5527 BUG_ON(stream->state != AMPDU_STREAM_IN_PROGRESS);
5528 spin_unlock(&priv->stream_lock);
f95275c4 5529 rc = mwl8k_create_ba(hw, stream, buf_size, vif);
65f3ddcd
NS		 5530 spin_lock(&priv->stream_lock);
5531 if (!rc)
5532 stream->state = AMPDU_STREAM_ACTIVE;
5533 else {
07f6dda1 5534 idx = stream->idx;
65f3ddcd 5535 spin_unlock(&priv->stream_lock);
07f6dda1 5536 mwl8k_destroy_ba(hw, idx);
65f3ddcd
NS		 5537 spin_lock(&priv->stream_lock);
5538 wiphy_debug(hw->wiphy,
5539 "Failed adding stream for sta %pM tid %d\n",
5540 addr, tid);
5541 mwl8k_remove_stream(hw, stream);
5542 }
5543 break;
5544
a2292d83 5545 default:
65f3ddcd 5546 rc = -ENOTSUPP;
a2292d83 5547 }
65f3ddcd
NS		 5548
5549 spin_unlock(&priv->stream_lock);
5550 return rc;
a2292d83
LB		 5551}
5552
4c924f42
YAP		 5553static void mwl8k_sw_scan_start(struct ieee80211_hw *hw)
5554{
5555 struct mwl8k_priv *priv = hw->priv;
5556 u8 tmp;
5557
5558 if (!priv->ap_fw)
5559 return;
5560
5561 /* clear all stats */
031eb464 5562 priv->channel_time = 0;
4c924f42
YAP		 5563 ioread32(priv->regs + BBU_RXRDY_CNT_REG);
5564 ioread32(priv->regs + NOK_CCA_CNT_REG);
5565 mwl8k_cmd_bbp_reg_access(priv->hw, 0, BBU_AVG_NOISE_VAL, &tmp);
5566
5567 priv->sw_scan_start = true;
5568}
5569
5570static void mwl8k_sw_scan_complete(struct ieee80211_hw *hw)
5571{
5572 struct mwl8k_priv *priv = hw->priv;
5573 u8 tmp;
5574
5575 if (!priv->ap_fw)
5576 return;
5577
5578 priv->sw_scan_start = false;
5579
5580 /* clear all stats */
031eb464 5581 priv->channel_time = 0;
4c924f42
YAP		 5582 ioread32(priv->regs + BBU_RXRDY_CNT_REG);
5583 ioread32(priv->regs + NOK_CCA_CNT_REG);
5584 mwl8k_cmd_bbp_reg_access(priv->hw, 0, BBU_AVG_NOISE_VAL, &tmp);
5585}
5586
a66098da
LB		 5587static const struct ieee80211_ops mwl8k_ops = {
5588 .tx = mwl8k_tx,
5589 .start = mwl8k_start,
5590 .stop = mwl8k_stop,
5591 .add_interface = mwl8k_add_interface,
5592 .remove_interface = mwl8k_remove_interface,
5593 .config = mwl8k_config,
a66098da 5594 .bss_info_changed = mwl8k_bss_info_changed,
3ac64bee 5595 .prepare_multicast = mwl8k_prepare_multicast,
a66098da 5596 .configure_filter = mwl8k_configure_filter,
fcdc403c 5597 .set_key = mwl8k_set_key,
a66098da 5598 .set_rts_threshold = mwl8k_set_rts_threshold,
4a6967b8
JB		 5599 .sta_add = mwl8k_sta_add,
5600 .sta_remove = mwl8k_sta_remove,
a66098da 5601 .conf_tx = mwl8k_conf_tx,
a66098da 5602 .get_stats = mwl8k_get_stats,
0d462bbb 5603 .get_survey = mwl8k_get_survey,
a2292d83 5604 .ampdu_action = mwl8k_ampdu_action,
4c924f42
YAP		 5605 .sw_scan_start = mwl8k_sw_scan_start,
5606 .sw_scan_complete = mwl8k_sw_scan_complete,
a66098da
LB		 5607};
5608
a66098da
LB		 5609static void mwl8k_finalize_join_worker(struct work_struct *work)
5610{
5611 struct mwl8k_priv *priv =
5612 container_of(work, struct mwl8k_priv, finalize_join_worker);
5613 struct sk_buff *skb = priv->beacon_skb;
56007a02
JB		 5614 struct ieee80211_mgmt *mgmt = (void *)skb->data;
5615 int len = skb->len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
5616 const u8 *tim = cfg80211_find_ie(WLAN_EID_TIM,
5617 mgmt->u.beacon.variable, len);
5618 int dtim_period = 1;
5619
5620 if (tim && tim[1] >= 2)
5621 dtim_period = tim[3];
a66098da 5622
56007a02 5623 mwl8k_cmd_finalize_join(priv->hw, skb->data, skb->len, dtim_period);
a66098da 5624
f5bb87cf 5625 dev_kfree_skb(skb);
a66098da
LB		 5626 priv->beacon_skb = NULL;
5627}
5628
bcb628d5 5629enum {
9e1b17ea
LB		 5630 MWL8363 = 0,
5631 MWL8687,
bcb628d5 5632 MWL8366,
d926dc7d 5633 MWL8764,
6f6d1e9a
LB		 5634};
5635
c2f2e202 5636#define MWL8K_8366_AP_FW_API 3
952a0e96
BC		 5637#define _MWL8K_8366_AP_FW(api) "mwl8k/fmimage_8366_ap-" #api ".fw"
5638#define MWL8K_8366_AP_FW(api) _MWL8K_8366_AP_FW(api)
5639
d926dc7d
NS		 5640#define MWL8K_8764_AP_FW_API 1
5641#define _MWL8K_8764_AP_FW(api) "mwl8k/fmimage_8764_ap-" #api ".fw"
5642#define MWL8K_8764_AP_FW(api) _MWL8K_8764_AP_FW(api)
5643
8dee5eef 5644static struct mwl8k_device_info mwl8k_info_tbl[] = {
9e1b17ea
LB		 5645 [MWL8363] = {
5646 .part_name = "88w8363",
5647 .helper_image = "mwl8k/helper_8363.fw",
0863ade8 5648 .fw_image_sta = "mwl8k/fmimage_8363.fw",
9e1b17ea 5649 },
49eb691c 5650 [MWL8687] = {
bcb628d5
JL		 5651 .part_name = "88w8687",
5652 .helper_image = "mwl8k/helper_8687.fw",
0863ade8 5653 .fw_image_sta = "mwl8k/fmimage_8687.fw",
bcb628d5 5654 },
49eb691c 5655 [MWL8366] = {
bcb628d5
JL		 5656 .part_name = "88w8366",
5657 .helper_image = "mwl8k/helper_8366.fw",
0863ade8 5658 .fw_image_sta = "mwl8k/fmimage_8366.fw",
952a0e96
BC		 5659 .fw_image_ap = MWL8K_8366_AP_FW(MWL8K_8366_AP_FW_API),
5660 .fw_api_ap = MWL8K_8366_AP_FW_API,
d926dc7d
NS		 5661 .ap_rxd_ops = &rxd_ap_ops,
5662 },
5663 [MWL8764] = {
5664 .part_name = "88w8764",
5665 .fw_image_ap = MWL8K_8764_AP_FW(MWL8K_8764_AP_FW_API),
5666 .fw_api_ap = MWL8K_8764_AP_FW_API,
5667 .ap_rxd_ops = &rxd_ap_ops,
bcb628d5 5668 },
45a390dd
LB		 5669};
5670
c92d4ede
LB		 5671MODULE_FIRMWARE("mwl8k/helper_8363.fw");
5672MODULE_FIRMWARE("mwl8k/fmimage_8363.fw");
5673MODULE_FIRMWARE("mwl8k/helper_8687.fw");
5674MODULE_FIRMWARE("mwl8k/fmimage_8687.fw");
5675MODULE_FIRMWARE("mwl8k/helper_8366.fw");
5676MODULE_FIRMWARE("mwl8k/fmimage_8366.fw");
952a0e96 5677MODULE_FIRMWARE(MWL8K_8366_AP_FW(MWL8K_8366_AP_FW_API));
c92d4ede 5678
45a390dd 5679static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = {
e5868ba1 5680 { PCI_VDEVICE(MARVELL, 0x2a0a), .driver_data = MWL8363, },
9e1b17ea
LB		 5681 { PCI_VDEVICE(MARVELL, 0x2a0c), .driver_data = MWL8363, },
5682 { PCI_VDEVICE(MARVELL, 0x2a24), .driver_data = MWL8363, },
bcb628d5
JL		 5683 { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = MWL8687, },
5684 { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = MWL8687, },
5685 { PCI_VDEVICE(MARVELL, 0x2a40), .driver_data = MWL8366, },
fc5bc165
JG		 5686 { PCI_VDEVICE(MARVELL, 0x2a41), .driver_data = MWL8366, },
5687 { PCI_VDEVICE(MARVELL, 0x2a42), .driver_data = MWL8366, },
ca66527c 5688 { PCI_VDEVICE(MARVELL, 0x2a43), .driver_data = MWL8366, },
d926dc7d 5689 { PCI_VDEVICE(MARVELL, 0x2b36), .driver_data = MWL8764, },
bcb628d5 5690 { },
45a390dd
LB		 5691};
5692MODULE_DEVICE_TABLE(pci, mwl8k_pci_id_table);
5693
99020471
BC		 5694static int mwl8k_request_alt_fw(struct mwl8k_priv *priv)
5695{
5696 int rc;
5697 printk(KERN_ERR "%s: Error requesting preferred fw %s.\n"
5698 "Trying alternative firmware %s\n", pci_name(priv->pdev),
5699 priv->fw_pref, priv->fw_alt);
5700 rc = mwl8k_request_fw(priv, priv->fw_alt, &priv->fw_ucode, true);
5701 if (rc) {
5702 printk(KERN_ERR "%s: Error requesting alt fw %s\n",
5703 pci_name(priv->pdev), priv->fw_alt);
5704 return rc;
5705 }
5706 return 0;
5707}
5708
5709static int mwl8k_firmware_load_success(struct mwl8k_priv *priv);
5710static void mwl8k_fw_state_machine(const struct firmware *fw, void *context)
5711{
5712 struct mwl8k_priv *priv = context;
5713 struct mwl8k_device_info *di = priv->device_info;
5714 int rc;
5715
5716 switch (priv->fw_state) {
5717 case FW_STATE_INIT:
5718 if (!fw) {
5719 printk(KERN_ERR "%s: Error requesting helper fw %s\n",
5720 pci_name(priv->pdev), di->helper_image);
5721 goto fail;
5722 }
5723 priv->fw_helper = fw;
5724 rc = mwl8k_request_fw(priv, priv->fw_pref, &priv->fw_ucode,
5725 true);
5726 if (rc && priv->fw_alt) {
5727 rc = mwl8k_request_alt_fw(priv);
5728 if (rc)
5729 goto fail;
5730 priv->fw_state = FW_STATE_LOADING_ALT;
5731 } else if (rc)
5732 goto fail;
5733 else
5734 priv->fw_state = FW_STATE_LOADING_PREF;
5735 break;
5736
5737 case FW_STATE_LOADING_PREF:
5738 if (!fw) {
5739 if (priv->fw_alt) {
5740 rc = mwl8k_request_alt_fw(priv);
5741 if (rc)
5742 goto fail;
5743 priv->fw_state = FW_STATE_LOADING_ALT;
5744 } else
5745 goto fail;
5746 } else {
5747 priv->fw_ucode = fw;
5748 rc = mwl8k_firmware_load_success(priv);
5749 if (rc)
5750 goto fail;
5751 else
5752 complete(&priv->firmware_loading_complete);
5753 }
5754 break;
5755
5756 case FW_STATE_LOADING_ALT:
5757 if (!fw) {
5758 printk(KERN_ERR "%s: Error requesting alt fw %s\n",
5759 pci_name(priv->pdev), di->helper_image);
5760 goto fail;
5761 }
5762 priv->fw_ucode = fw;
5763 rc = mwl8k_firmware_load_success(priv);
5764 if (rc)
5765 goto fail;
5766 else
5767 complete(&priv->firmware_loading_complete);
5768 break;
5769
5770 default:
5771 printk(KERN_ERR "%s: Unexpected firmware loading state: %d\n",
5772 MWL8K_NAME, priv->fw_state);
5773 BUG_ON(1);
5774 }
5775
5776 return;
5777
5778fail:
5779 priv->fw_state = FW_STATE_ERROR;
5780 complete(&priv->firmware_loading_complete);
5781 device_release_driver(&priv->pdev->dev);
5782 mwl8k_release_firmware(priv);
5783}
5784
6b6accc3 5785#define MAX_RESTART_ATTEMPTS 1
99020471
BC		 5786static int mwl8k_init_firmware(struct ieee80211_hw *hw, char *fw_image,
5787 bool nowait)
a66098da 5788{
3cc7772c 5789 struct mwl8k_priv *priv = hw->priv;
a66098da 5790 int rc;
6b6accc3 5791 int count = MAX_RESTART_ATTEMPTS;
be695fc4 5792
6b6accc3 5793retry:
be695fc4
LB		 5794 /* Reset firmware and hardware */
5795 mwl8k_hw_reset(priv);
5796
5797 /* Ask userland hotplug daemon for the device firmware */
99020471 5798 rc = mwl8k_request_firmware(priv, fw_image, nowait);
be695fc4 5799 if (rc) {
5db55844 5800 wiphy_err(hw->wiphy, "Firmware files not found\n");
3cc7772c 5801 return rc;
be695fc4
LB		 5802 }
5803
99020471
BC		 5804 if (nowait)
5805 return rc;
5806
be695fc4
LB		 5807 /* Load firmware into hardware */
5808 rc = mwl8k_load_firmware(hw);
3cc7772c 5809 if (rc)
5db55844 5810 wiphy_err(hw->wiphy, "Cannot start firmware\n");
be695fc4
LB		 5811
5812 /* Reclaim memory once firmware is successfully loaded */
5813 mwl8k_release_firmware(priv);
5814
6b6accc3
YAP		 5815 if (rc && count) {
5816 /* FW did not start successfully;
5817 * lets try one more time
5818 */
5819 count--;
5820 wiphy_err(hw->wiphy, "Trying to reload the firmware again\n");
5821 msleep(20);
5822 goto retry;
5823 }
5824
3cc7772c
BC		 5825 return rc;
5826}
5827
73b46320
BC		 5828static int mwl8k_init_txqs(struct ieee80211_hw *hw)
5829{
5830 struct mwl8k_priv *priv = hw->priv;
5831 int rc = 0;
5832 int i;
5833
e600707b 5834 for (i = 0; i < mwl8k_tx_queues(priv); i++) {
73b46320
BC		 5835 rc = mwl8k_txq_init(hw, i);
5836 if (rc)
5837 break;
5838 if (priv->ap_fw)
5839 iowrite32(priv->txq[i].txd_dma,
5840 priv->sram + priv->txq_offset[i]);
5841 }
5842 return rc;
5843}
5844
3cc7772c
BC		 5845/* initialize hw after successfully loading a firmware image */
5846static int mwl8k_probe_hw(struct ieee80211_hw *hw)
5847{
5848 struct mwl8k_priv *priv = hw->priv;
5849 int rc = 0;
5850 int i;
be695fc4 5851
91942230 5852 if (priv->ap_fw) {
89a91f4f 5853 priv->rxd_ops = priv->device_info->ap_rxd_ops;
91942230 5854 if (priv->rxd_ops == NULL) {
c96c31e4
JP		 5855 wiphy_err(hw->wiphy,
5856 "Driver does not have AP firmware image support for this hardware\n");
a2ca8ecb 5857 rc = -ENOENT;
91942230
LB		 5858 goto err_stop_firmware;
5859 }
5860 } else {
89a91f4f 5861 priv->rxd_ops = &rxd_sta_ops;
91942230 5862 }
be695fc4
LB		 5863
5864 priv->sniffer_enabled = false;
5865 priv->wmm_enabled = false;
5866 priv->pending_tx_pkts = 0;
c27a54d3 5867 atomic_set(&priv->watchdog_event_pending, 0);
be695fc4 5868
a66098da
LB		 5869 rc = mwl8k_rxq_init(hw, 0);
5870 if (rc)
3cc7772c 5871 goto err_stop_firmware;
a66098da
LB		 5872 rxq_refill(hw, 0, INT_MAX);
5873
73b46320
BC		 5874 /* For the sta firmware, we need to know the dma addresses of tx queues
5875 * before sending MWL8K_CMD_GET_HW_SPEC. So we must initialize them
5876 * prior to issuing this command. But for the AP case, we learn the
5877 * total number of queues from the result CMD_GET_HW_SPEC, so for this
5878 * case we must initialize the tx queues after.
5879 */
8a7a578c 5880 priv->num_ampdu_queues = 0;
73b46320
BC		 5881 if (!priv->ap_fw) {
5882 rc = mwl8k_init_txqs(hw);
a66098da
LB		 5883 if (rc)
5884 goto err_free_queues;
5885 }
5886
5887 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
c23b5a69 5888 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3aefc37e
NS		 5889 iowrite32(MWL8K_A2H_INT_TX_DONE|MWL8K_A2H_INT_RX_READY|
5890 MWL8K_A2H_INT_BA_WATCHDOG,
1e9f9de3 5891 priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
12488e01
NS		 5892 iowrite32(MWL8K_A2H_INT_OPC_DONE,
5893 priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
a66098da 5894
a0607fd3 5895 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
a66098da
LB		 5896 IRQF_SHARED, MWL8K_NAME, hw);
5897 if (rc) {
5db55844 5898 wiphy_err(hw->wiphy, "failed to register IRQ handler\n");
a66098da
LB		 5899 goto err_free_queues;
5900 }
5901
6b6accc3
YAP		 5902 /*
5903 * When hw restart is requested,
5904 * mac80211 will take care of clearing
5905 * the ampdu streams, so do not clear
5906 * the ampdu state here
5907 */
5908 if (!priv->hw_restart_in_progress)
5909 memset(priv->ampdu, 0, sizeof(priv->ampdu));
ac109fd0 5910
a66098da
LB		 5911 /*
5912 * Temporarily enable interrupts. Initial firmware host
c2c2b12a 5913 * commands use interrupts and avoid polling. Disable
a66098da
LB		 5914 * interrupts when done.
5915 */
c23b5a69 5916 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 5917
5918 /* Get config data, mac addrs etc */
42fba21d
LB		 5919 if (priv->ap_fw) {
5920 rc = mwl8k_cmd_get_hw_spec_ap(hw);
73b46320
BC		 5921 if (!rc)
5922 rc = mwl8k_init_txqs(hw);
42fba21d
LB		 5923 if (!rc)
5924 rc = mwl8k_cmd_set_hw_spec(hw);
5925 } else {
5926 rc = mwl8k_cmd_get_hw_spec_sta(hw);
5927 }
a66098da 5928 if (rc) {
5db55844 5929 wiphy_err(hw->wiphy, "Cannot initialise firmware\n");
be695fc4 5930 goto err_free_irq;
a66098da
LB		 5931 }
5932
5933 /* Turn radio off */
55489b6e 5934 rc = mwl8k_cmd_radio_disable(hw);
a66098da 5935 if (rc) {
5db55844 5936 wiphy_err(hw->wiphy, "Cannot disable\n");
be695fc4 5937 goto err_free_irq;
a66098da
LB		 5938 }
5939
32060e1b 5940 /* Clear MAC address */
aa21d0f6 5941 rc = mwl8k_cmd_set_mac_addr(hw, NULL, "\x00\x00\x00\x00\x00\x00");
32060e1b 5942 if (rc) {
5db55844 5943 wiphy_err(hw->wiphy, "Cannot clear MAC address\n");
be695fc4 5944 goto err_free_irq;
32060e1b
LB		 5945 }
5946
a246ac38
YAP		 5947 /* Configure Antennas */
5948 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_RX, 0x3);
5949 if (rc)
5950 wiphy_warn(hw->wiphy, "failed to set # of RX antennas");
5951 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_TX, 0x7);
5952 if (rc)
5953 wiphy_warn(hw->wiphy, "failed to set # of TX antennas");
5954
5955
a66098da 5956 /* Disable interrupts */
a66098da 5957 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 5958 free_irq(priv->pdev->irq, hw);
5959
c96c31e4
JP		 5960 wiphy_info(hw->wiphy, "%s v%d, %pm, %s firmware %u.%u.%u.%u\n",
5961 priv->device_info->part_name,
5962 priv->hw_rev, hw->wiphy->perm_addr,
5963 priv->ap_fw ? "AP" : "STA",
5964 (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff,
5965 (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff);
a66098da
LB		 5966
5967 return 0;
5968
a66098da 5969err_free_irq:
a66098da 5970 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 5971 free_irq(priv->pdev->irq, hw);
5972
5973err_free_queues:
e600707b 5974 for (i = 0; i < mwl8k_tx_queues(priv); i++)
a66098da
LB		 5975 mwl8k_txq_deinit(hw, i);
5976 mwl8k_rxq_deinit(hw, 0);
5977
3cc7772c
BC		 5978err_stop_firmware:
5979 mwl8k_hw_reset(priv);
5980
5981 return rc;
5982}
5983
5984/*
5985 * invoke mwl8k_reload_firmware to change the firmware image after the device
5986 * has already been registered
5987 */
5988static int mwl8k_reload_firmware(struct ieee80211_hw *hw, char *fw_image)
5989{
5990 int i, rc = 0;
5991 struct mwl8k_priv *priv = hw->priv;
6b6accc3 5992 struct mwl8k_vif *vif, *tmp_vif;
3cc7772c
BC		 5993
5994 mwl8k_stop(hw);
5995 mwl8k_rxq_deinit(hw, 0);
5996
6b6accc3
YAP		 5997 /*
5998 * All the existing interfaces are re-added by the ieee80211_reconfig;
5999 * which means driver should remove existing interfaces before calling
6000 * ieee80211_restart_hw
6001 */
6002 if (priv->hw_restart_in_progress)
6003 list_for_each_entry_safe(vif, tmp_vif, &priv->vif_list, list)
6004 mwl8k_remove_vif(priv, vif);
6005
e600707b 6006 for (i = 0; i < mwl8k_tx_queues(priv); i++)
3cc7772c
BC		 6007 mwl8k_txq_deinit(hw, i);
6008
99020471 6009 rc = mwl8k_init_firmware(hw, fw_image, false);
3cc7772c
BC		 6010 if (rc)
6011 goto fail;
6012
6013 rc = mwl8k_probe_hw(hw);
6014 if (rc)
6015 goto fail;
6016
6b6accc3
YAP		 6017 if (priv->hw_restart_in_progress)
6018 return rc;
6019
3cc7772c
BC		 6020 rc = mwl8k_start(hw);
6021 if (rc)
6022 goto fail;
6023
6024 rc = mwl8k_config(hw, ~0);
6025 if (rc)
6026 goto fail;
6027
e600707b 6028 for (i = 0; i < MWL8K_TX_WMM_QUEUES; i++) {
8a3a3c85 6029 rc = mwl8k_conf_tx(hw, NULL, i, &priv->wmm_params[i]);
3cc7772c
BC		 6030 if (rc)
6031 goto fail;
6032 }
6033
6034 return rc;
6035
6036fail:
6037 printk(KERN_WARNING "mwl8k: Failed to reload firmware image.\n");
6038 return rc;
6039}
6040
5d377fca
YAP		 6041static const struct ieee80211_iface_limit ap_if_limits[] = {
6042 { .max = 8, .types = BIT(NL80211_IFTYPE_AP) },
2acdaa7a 6043 { .max = 1, .types = BIT(NL80211_IFTYPE_STATION) },
5d377fca
YAP		 6044};
6045
6046static const struct ieee80211_iface_combination ap_if_comb = {
6047 .limits = ap_if_limits,
6048 .n_limits = ARRAY_SIZE(ap_if_limits),
6049 .max_interfaces = 8,
6050 .num_different_channels = 1,
6051};
6052
6053
3cc7772c
BC		 6054static int mwl8k_firmware_load_success(struct mwl8k_priv *priv)
6055{
6056 struct ieee80211_hw *hw = priv->hw;
6057 int i, rc;
6058
99020471
BC		 6059 rc = mwl8k_load_firmware(hw);
6060 mwl8k_release_firmware(priv);
6061 if (rc) {
6062 wiphy_err(hw->wiphy, "Cannot start firmware\n");
6063 return rc;
6064 }
6065
3cc7772c
BC		 6066 /*
6067 * Extra headroom is the size of the required DMA header
6068 * minus the size of the smallest 802.11 frame (CTS frame).
6069 */
6070 hw->extra_tx_headroom =
6071 sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
6072
ff776cec
YAP		 6073 hw->extra_tx_headroom -= priv->ap_fw ? REDUCED_TX_HEADROOM : 0;
6074
e600707b 6075 hw->queues = MWL8K_TX_WMM_QUEUES;
3cc7772c
BC		 6076
6077 /* Set rssi values to dBm */
0bf22c37 6078 hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_HAS_RATE_CONTROL;
2a36a0ec
YAP		 6079
6080 /*
6081 * Ask mac80211 to not to trigger PS mode
6082 * based on PM bit of incoming frames.
6083 */
6084 if (priv->ap_fw)
6085 hw->flags |= IEEE80211_HW_AP_LINK_PS;
6086
3cc7772c
BC		 6087 hw->vif_data_size = sizeof(struct mwl8k_vif);
6088 hw->sta_data_size = sizeof(struct mwl8k_sta);
6089
6090 priv->macids_used = 0;
6091 INIT_LIST_HEAD(&priv->vif_list);
6092
6093 /* Set default radio state and preamble */
3db1cd5c
RR		 6094 priv->radio_on = false;
6095 priv->radio_short_preamble = false;
3cc7772c
BC		 6096
6097 /* Finalize join worker */
6098 INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
3aefc37e
NS		 6099 /* Handle watchdog ba events */
6100 INIT_WORK(&priv->watchdog_ba_handle, mwl8k_watchdog_ba_events);
6b6accc3
YAP		 6101 /* To reload the firmware if it crashes */
6102 INIT_WORK(&priv->fw_reload, mwl8k_hw_restart_work);
3cc7772c
BC		 6103
6104 /* TX reclaim and RX tasklets. */
6105 tasklet_init(&priv->poll_tx_task, mwl8k_tx_poll, (unsigned long)hw);
6106 tasklet_disable(&priv->poll_tx_task);
6107 tasklet_init(&priv->poll_rx_task, mwl8k_rx_poll, (unsigned long)hw);
6108 tasklet_disable(&priv->poll_rx_task);
6109
6110 /* Power management cookie */
6111 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
6112 if (priv->cookie == NULL)
6113 return -ENOMEM;
6114
6115 mutex_init(&priv->fw_mutex);
6116 priv->fw_mutex_owner = NULL;
6117 priv->fw_mutex_depth = 0;
6118 priv->hostcmd_wait = NULL;
6119
6120 spin_lock_init(&priv->tx_lock);
6121
ac109fd0
BC		 6122 spin_lock_init(&priv->stream_lock);
6123
3cc7772c
BC		 6124 priv->tx_wait = NULL;
6125
6126 rc = mwl8k_probe_hw(hw);
6127 if (rc)
6128 goto err_free_cookie;
6129
6130 hw->wiphy->interface_modes = 0;
5d377fca
YAP		 6131
6132 if (priv->ap_macids_supported || priv->device_info->fw_image_ap) {
3cc7772c 6133 hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_AP);
2acdaa7a 6134 hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_STATION);
5d377fca
YAP		 6135 hw->wiphy->iface_combinations = &ap_if_comb;
6136 hw->wiphy->n_iface_combinations = 1;
6137 }
6138
3cc7772c
BC		 6139 if (priv->sta_macids_supported || priv->device_info->fw_image_sta)
6140 hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_STATION);
6141
6142 rc = ieee80211_register_hw(hw);
6143 if (rc) {
6144 wiphy_err(hw->wiphy, "Cannot register device\n");
6145 goto err_unprobe_hw;
6146 }
6147
6148 return 0;
6149
6150err_unprobe_hw:
e600707b 6151 for (i = 0; i < mwl8k_tx_queues(priv); i++)
3cc7772c
BC		 6152 mwl8k_txq_deinit(hw, i);
6153 mwl8k_rxq_deinit(hw, 0);
6154
be695fc4 6155err_free_cookie:
a66098da
LB		 6156 if (priv->cookie != NULL)
6157 pci_free_consistent(priv->pdev, 4,
6158 priv->cookie, priv->cookie_dma);
6159
3cc7772c
BC		 6160 return rc;
6161}
8dee5eef 6162static int mwl8k_probe(struct pci_dev *pdev,
3cc7772c
BC		 6163 const struct pci_device_id *id)
6164{
6165 static int printed_version;
6166 struct ieee80211_hw *hw;
6167 struct mwl8k_priv *priv;
0863ade8 6168 struct mwl8k_device_info *di;
3cc7772c
BC		 6169 int rc;
6170
6171 if (!printed_version) {
6172 printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
6173 printed_version = 1;
6174 }
6175
6176
6177 rc = pci_enable_device(pdev);
6178 if (rc) {
6179 printk(KERN_ERR "%s: Cannot enable new PCI device\n",
6180 MWL8K_NAME);
6181 return rc;
6182 }
6183
6184 rc = pci_request_regions(pdev, MWL8K_NAME);
6185 if (rc) {
6186 printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
6187 MWL8K_NAME);
6188 goto err_disable_device;
6189 }
6190
6191 pci_set_master(pdev);
6192
6193
6194 hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
6195 if (hw == NULL) {
6196 printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
6197 rc = -ENOMEM;
6198 goto err_free_reg;
6199 }
6200
6201 SET_IEEE80211_DEV(hw, &pdev->dev);
6202 pci_set_drvdata(pdev, hw);
6203
6204 priv = hw->priv;
6205 priv->hw = hw;
6206 priv->pdev = pdev;
6207 priv->device_info = &mwl8k_info_tbl[id->driver_data];
6208
98929824
NS		 6209 if (id->driver_data == MWL8764)
6210 priv->is_8764 = true;
3cc7772c
BC		 6211
6212 priv->sram = pci_iomap(pdev, 0, 0x10000);
6213 if (priv->sram == NULL) {
6214 wiphy_err(hw->wiphy, "Cannot map device SRAM\n");
a2ca8ecb 6215 rc = -EIO;
3cc7772c
BC		 6216 goto err_iounmap;
6217 }
6218
6219 /*
6220 * If BAR0 is a 32 bit BAR, the register BAR will be BAR1.
6221 * If BAR0 is a 64 bit BAR, the register BAR will be BAR2.
6222 */
6223 priv->regs = pci_iomap(pdev, 1, 0x10000);
6224 if (priv->regs == NULL) {
6225 priv->regs = pci_iomap(pdev, 2, 0x10000);
6226 if (priv->regs == NULL) {
6227 wiphy_err(hw->wiphy, "Cannot map device registers\n");
a2ca8ecb 6228 rc = -EIO;
3cc7772c
BC		 6229 goto err_iounmap;
6230 }
6231 }
6232
0863ade8 6233 /*
99020471
BC		 6234 * Choose the initial fw image depending on user input. If a second
6235 * image is available, make it the alternative image that will be
6236 * loaded if the first one fails.
0863ade8 6237 */
99020471 6238 init_completion(&priv->firmware_loading_complete);
0863ade8 6239 di = priv->device_info;
99020471
BC		 6240 if (ap_mode_default && di->fw_image_ap) {
6241 priv->fw_pref = di->fw_image_ap;
6242 priv->fw_alt = di->fw_image_sta;
6243 } else if (!ap_mode_default && di->fw_image_sta) {
6244 priv->fw_pref = di->fw_image_sta;
6245 priv->fw_alt = di->fw_image_ap;
6246 } else if (ap_mode_default && !di->fw_image_ap && di->fw_image_sta) {
0863ade8 6247 printk(KERN_WARNING "AP fw is unavailable. Using STA fw.");
99020471 6248 priv->fw_pref = di->fw_image_sta;
0863ade8
BC		 6249 } else if (!ap_mode_default && !di->fw_image_sta && di->fw_image_ap) {
6250 printk(KERN_WARNING "STA fw is unavailable. Using AP fw.");
99020471
BC		 6251 priv->fw_pref = di->fw_image_ap;
6252 }
6253 rc = mwl8k_init_firmware(hw, priv->fw_pref, true);
3cc7772c
BC		 6254 if (rc)
6255 goto err_stop_firmware;
6b6accc3
YAP		 6256
6257 priv->hw_restart_in_progress = false;
6258
e882efc9
YAP		 6259 priv->running_bsses = 0;
6260
99020471 6261 return rc;
3cc7772c 6262
be695fc4
LB		 6263err_stop_firmware:
6264 mwl8k_hw_reset(priv);
be695fc4
LB		 6265
6266err_iounmap:
a66098da
LB		 6267 if (priv->regs != NULL)
6268 pci_iounmap(pdev, priv->regs);
6269
5b9482dd
LB		 6270 if (priv->sram != NULL)
6271 pci_iounmap(pdev, priv->sram);
6272
a66098da
LB		 6273 ieee80211_free_hw(hw);
6274
6275err_free_reg:
6276 pci_release_regions(pdev);
3db95e50
LB		 6277
6278err_disable_device:
a66098da
LB		 6279 pci_disable_device(pdev);
6280
6281 return rc;
6282}
6283
8dee5eef 6284static void mwl8k_remove(struct pci_dev *pdev)
a66098da
LB		 6285{
6286 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
6287 struct mwl8k_priv *priv;
6288 int i;
6289
6290 if (hw == NULL)
6291 return;
6292 priv = hw->priv;
6293
99020471
BC		 6294 wait_for_completion(&priv->firmware_loading_complete);
6295
6296 if (priv->fw_state == FW_STATE_ERROR) {
6297 mwl8k_hw_reset(priv);
6298 goto unmap;
6299 }
6300
a66098da
LB		 6301 ieee80211_stop_queues(hw);
6302
60aa569f
LB		 6303 ieee80211_unregister_hw(hw);
6304
67e2eb27 6305 /* Remove TX reclaim and RX tasklets. */
1e9f9de3 6306 tasklet_kill(&priv->poll_tx_task);
67e2eb27 6307 tasklet_kill(&priv->poll_rx_task);
a66098da 6308
a66098da
LB		 6309 /* Stop hardware */
6310 mwl8k_hw_reset(priv);
6311
6312 /* Return all skbs to mac80211 */
e600707b 6313 for (i = 0; i < mwl8k_tx_queues(priv); i++)
efb7c49a 6314 mwl8k_txq_reclaim(hw, i, INT_MAX, 1);
a66098da 6315
e600707b 6316 for (i = 0; i < mwl8k_tx_queues(priv); i++)
a66098da
LB		 6317 mwl8k_txq_deinit(hw, i);
6318
6319 mwl8k_rxq_deinit(hw, 0);
6320
c2c357ce 6321 pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma);
a66098da 6322
99020471 6323unmap:
a66098da 6324 pci_iounmap(pdev, priv->regs);
5b9482dd 6325 pci_iounmap(pdev, priv->sram);
a66098da
LB		 6326 ieee80211_free_hw(hw);
6327 pci_release_regions(pdev);
6328 pci_disable_device(pdev);
6329}
6330
6331static struct pci_driver mwl8k_driver = {
6332 .name = MWL8K_NAME,
45a390dd 6333 .id_table = mwl8k_pci_id_table,
a66098da 6334 .probe = mwl8k_probe,
8dee5eef 6335 .remove = mwl8k_remove,
a66098da
LB		 6336};
6337
5b0a3b7e 6338module_pci_driver(mwl8k_driver);
c2c357ce
LB		 6339
6340MODULE_DESCRIPTION(MWL8K_DESC);
6341MODULE_VERSION(MWL8K_VERSION);
6342MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
6343MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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