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mwl8k: sort firmware command list by opcode, and trim unused commands
[deliverable/linux.git] / drivers / net / wireless / mwl8k.c
CommitLineData
a66098da
LB		 1/*
2 * drivers/net/wireless/mwl8k.c driver for Marvell TOPDOG 802.11 Wireless cards
3 *
4 * Copyright (C) 2008 Marvell Semiconductor Inc.
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/init.h>
12#include <linux/module.h>
13#include <linux/kernel.h>
14#include <linux/spinlock.h>
15#include <linux/list.h>
16#include <linux/pci.h>
17#include <linux/delay.h>
18#include <linux/completion.h>
19#include <linux/etherdevice.h>
20#include <net/mac80211.h>
21#include <linux/moduleparam.h>
22#include <linux/firmware.h>
23#include <linux/workqueue.h>
24
25#define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
26#define MWL8K_NAME KBUILD_MODNAME
27#define MWL8K_VERSION "0.9.1"
28
29MODULE_DESCRIPTION(MWL8K_DESC);
30MODULE_VERSION(MWL8K_VERSION);
31MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
32MODULE_LICENSE("GPL");
33
34static DEFINE_PCI_DEVICE_TABLE(mwl8k_table) = {
35 { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = 8687, },
36 { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = 8687, },
37 { }
38};
39MODULE_DEVICE_TABLE(pci, mwl8k_table);
40
a66098da
LB		 41/* Register definitions */
42#define MWL8K_HIU_GEN_PTR 0x00000c10
43#define MWL8K_MODE_STA 0x0000005a
44#define MWL8K_MODE_AP 0x000000a5
45#define MWL8K_HIU_INT_CODE 0x00000c14
46#define MWL8K_FWSTA_READY 0xf0f1f2f4
47#define MWL8K_FWAP_READY 0xf1f2f4a5
48#define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
49#define MWL8K_HIU_SCRATCH 0x00000c40
50
51/* Host->device communications */
52#define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
53#define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
54#define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
55#define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
56#define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
57#define MWL8K_H2A_INT_DUMMY (1 << 20)
58#define MWL8K_H2A_INT_RESET (1 << 15)
a66098da
LB		 59#define MWL8K_H2A_INT_DOORBELL (1 << 1)
60#define MWL8K_H2A_INT_PPA_READY (1 << 0)
61
62/* Device->host communications */
63#define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
64#define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
65#define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
66#define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
67#define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
68#define MWL8K_A2H_INT_DUMMY (1 << 20)
69#define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
70#define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
71#define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
72#define MWL8K_A2H_INT_RADIO_ON (1 << 6)
73#define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
74#define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
75#define MWL8K_A2H_INT_OPC_DONE (1 << 2)
76#define MWL8K_A2H_INT_RX_READY (1 << 1)
77#define MWL8K_A2H_INT_TX_DONE (1 << 0)
78
79#define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
80 MWL8K_A2H_INT_CHNL_SWITCHED | \
81 MWL8K_A2H_INT_QUEUE_EMPTY | \
82 MWL8K_A2H_INT_RADAR_DETECT | \
83 MWL8K_A2H_INT_RADIO_ON | \
84 MWL8K_A2H_INT_RADIO_OFF | \
85 MWL8K_A2H_INT_MAC_EVENT | \
86 MWL8K_A2H_INT_OPC_DONE | \
87 MWL8K_A2H_INT_RX_READY | \
88 MWL8K_A2H_INT_TX_DONE)
89
90/* WME stream classes */
91#define WME_AC_BE 0 /* best effort */
92#define WME_AC_BK 1 /* background */
93#define WME_AC_VI 2 /* video */
94#define WME_AC_VO 3 /* voice */
95
96#define MWL8K_RX_QUEUES 1
97#define MWL8K_TX_QUEUES 4
98
99struct mwl8k_rx_queue {
100 int rx_desc_count;
101
102 /* hw receives here */
103 int rx_head;
104
105 /* refill descs here */
106 int rx_tail;
107
108 struct mwl8k_rx_desc *rx_desc_area;
109 dma_addr_t rx_desc_dma;
110 struct sk_buff **rx_skb;
111};
112
113struct mwl8k_skb {
114 /*
115 * The DMA engine requires a modification to the payload.
116 * If the skbuff is shared/cloned, it needs to be unshared.
117 * This method is used to ensure the stack always gets back
118 * the skbuff it sent for transmission.
119 */
120 struct sk_buff *clone;
121 struct sk_buff *skb;
122};
123
124struct mwl8k_tx_queue {
125 /* hw transmits here */
126 int tx_head;
127
128 /* sw appends here */
129 int tx_tail;
130
131 struct ieee80211_tx_queue_stats tx_stats;
132 struct mwl8k_tx_desc *tx_desc_area;
133 dma_addr_t tx_desc_dma;
134 struct mwl8k_skb *tx_skb;
135};
136
137/* Pointers to the firmware data and meta information about it. */
138struct mwl8k_firmware {
139 /* Microcode */
140 struct firmware *ucode;
141
142 /* Boot helper code */
143 struct firmware *helper;
144};
145
146struct mwl8k_priv {
147 void __iomem *regs;
148 struct ieee80211_hw *hw;
149
150 struct pci_dev *pdev;
151 u8 name[16];
152 /* firmware access lock */
153 spinlock_t fw_lock;
154
155 /* firmware files and meta data */
156 struct mwl8k_firmware fw;
157 u32 part_num;
158
159 /* lock held over TX and TX reap */
160 spinlock_t tx_lock;
a66098da
LB		 161
162 struct ieee80211_vif *vif;
a66098da
LB		 163
164 struct ieee80211_channel *current_channel;
165
166 /* power management status cookie from firmware */
167 u32 *cookie;
168 dma_addr_t cookie_dma;
169
170 u16 num_mcaddrs;
a66098da
LB		 171 u8 hw_rev;
172 __le32 fw_rev;
a66098da
LB		 173
174 /*
175 * Running count of TX packets in flight, to avoid
176 * iterating over the transmit rings each time.
177 */
178 int pending_tx_pkts;
179
180 struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
181 struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES];
182
183 /* PHY parameters */
184 struct ieee80211_supported_band band;
185 struct ieee80211_channel channels[14];
186 struct ieee80211_rate rates[12];
187
188 /* RF preamble: Short, Long or Auto */
189 u8 radio_preamble;
190 u8 radio_state;
191
192 /* WMM MODE 1 for enabled; 0 for disabled */
193 bool wmm_mode;
194
195 /* Set if PHY config is in progress */
196 bool inconfig;
197
198 /* XXX need to convert this to handle multiple interfaces */
199 bool capture_beacon;
d89173f2 200 u8 capture_bssid[ETH_ALEN];
a66098da
LB		 201 struct sk_buff *beacon_skb;
202
203 /*
204 * This FJ worker has to be global as it is scheduled from the
205 * RX handler. At this point we don't know which interface it
206 * belongs to until the list of bssids waiting to complete join
207 * is checked.
208 */
209 struct work_struct finalize_join_worker;
210
211 /* Tasklet to reclaim TX descriptors and buffers after tx */
212 struct tasklet_struct tx_reclaim_task;
213
214 /* Work thread to serialize configuration requests */
215 struct workqueue_struct *config_wq;
216 struct completion *hostcmd_wait;
217 struct completion *tx_wait;
218};
219
220/* Per interface specific private data */
221struct mwl8k_vif {
a66098da
LB		 222 /* backpointer to parent config block */
223 struct mwl8k_priv *priv;
224
225 /* BSS config of AP or IBSS from mac80211*/
226 struct ieee80211_bss_conf bss_info;
227
228 /* BSSID of AP or IBSS */
d89173f2
LB		 229 u8 bssid[ETH_ALEN];
230 u8 mac_addr[ETH_ALEN];
a66098da
LB		 231
232 /*
233 * Subset of supported legacy rates.
234 * Intersection of AP and STA supported rates.
235 */
236 struct ieee80211_rate legacy_rates[12];
237
238 /* number of supported legacy rates */
239 u8 legacy_nrates;
240
a66098da
LB		 241 /* Index into station database.Returned by update_sta_db call */
242 u8 peer_id;
243
244 /* Non AMPDU sequence number assigned by driver */
245 u16 seqno;
a66098da
LB		 246};
247
a94cc97e 248#define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
a66098da
LB		 249
250static const struct ieee80211_channel mwl8k_channels[] = {
251 { .center_freq = 2412, .hw_value = 1, },
252 { .center_freq = 2417, .hw_value = 2, },
253 { .center_freq = 2422, .hw_value = 3, },
254 { .center_freq = 2427, .hw_value = 4, },
255 { .center_freq = 2432, .hw_value = 5, },
256 { .center_freq = 2437, .hw_value = 6, },
257 { .center_freq = 2442, .hw_value = 7, },
258 { .center_freq = 2447, .hw_value = 8, },
259 { .center_freq = 2452, .hw_value = 9, },
260 { .center_freq = 2457, .hw_value = 10, },
261 { .center_freq = 2462, .hw_value = 11, },
262};
263
264static const struct ieee80211_rate mwl8k_rates[] = {
265 { .bitrate = 10, .hw_value = 2, },
266 { .bitrate = 20, .hw_value = 4, },
267 { .bitrate = 55, .hw_value = 11, },
268 { .bitrate = 60, .hw_value = 12, },
269 { .bitrate = 90, .hw_value = 18, },
270 { .bitrate = 110, .hw_value = 22, },
271 { .bitrate = 120, .hw_value = 24, },
272 { .bitrate = 180, .hw_value = 36, },
273 { .bitrate = 240, .hw_value = 48, },
274 { .bitrate = 360, .hw_value = 72, },
275 { .bitrate = 480, .hw_value = 96, },
276 { .bitrate = 540, .hw_value = 108, },
277};
278
279/* Radio settings */
280#define MWL8K_RADIO_FORCE 0x2
281#define MWL8K_RADIO_ENABLE 0x1
282#define MWL8K_RADIO_DISABLE 0x0
283#define MWL8K_RADIO_AUTO_PREAMBLE 0x0005
284#define MWL8K_RADIO_SHORT_PREAMBLE 0x0003
285#define MWL8K_RADIO_LONG_PREAMBLE 0x0001
286
287/* WMM */
288#define MWL8K_WMM_ENABLE 1
289#define MWL8K_WMM_DISABLE 0
290
291#define MWL8K_RADIO_DEFAULT_PREAMBLE MWL8K_RADIO_LONG_PREAMBLE
292
293/* Slot time */
294
295/* Short Slot: 9us slot time */
296#define MWL8K_SHORT_SLOTTIME 1
297
298/* Long slot: 20us slot time */
299#define MWL8K_LONG_SLOTTIME 0
300
301/* Set or get info from Firmware */
302#define MWL8K_CMD_SET 0x0001
303#define MWL8K_CMD_GET 0x0000
304
305/* Firmware command codes */
306#define MWL8K_CMD_CODE_DNLD 0x0001
307#define MWL8K_CMD_GET_HW_SPEC 0x0003
308#define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
309#define MWL8K_CMD_GET_STAT 0x0014
ff45fc60
LB		 310#define MWL8K_CMD_RADIO_CONTROL 0x001c
311#define MWL8K_CMD_RF_TX_POWER 0x001e
a66098da
LB		 312#define MWL8K_CMD_SET_PRE_SCAN 0x0107
313#define MWL8K_CMD_SET_POST_SCAN 0x0108
ff45fc60
LB		 314#define MWL8K_CMD_SET_RF_CHANNEL 0x010a
315#define MWL8K_CMD_SET_AID 0x010d
316#define MWL8K_CMD_SET_RATE 0x0110
317#define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
318#define MWL8K_CMD_RTS_THRESHOLD 0x0113
a66098da 319#define MWL8K_CMD_SET_SLOT 0x0114
ff45fc60
LB		 320#define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
321#define MWL8K_CMD_SET_WMM_MODE 0x0123
a66098da 322#define MWL8K_CMD_MIMO_CONFIG 0x0125
ff45fc60 323#define MWL8K_CMD_USE_FIXED_RATE 0x0126
a66098da 324#define MWL8K_CMD_ENABLE_SNIFFER 0x0150
a66098da 325#define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
ff45fc60 326#define MWL8K_CMD_UPDATE_STADB 0x1123
a66098da
LB		 327
328static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize)
329{
330#define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
331 snprintf(buf, bufsize, "%s", #x);\
332 return buf;\
333 } while (0)
334 switch (cmd & (~0x8000)) {
335 MWL8K_CMDNAME(CODE_DNLD);
336 MWL8K_CMDNAME(GET_HW_SPEC);
337 MWL8K_CMDNAME(MAC_MULTICAST_ADR);
338 MWL8K_CMDNAME(GET_STAT);
339 MWL8K_CMDNAME(RADIO_CONTROL);
340 MWL8K_CMDNAME(RF_TX_POWER);
341 MWL8K_CMDNAME(SET_PRE_SCAN);
342 MWL8K_CMDNAME(SET_POST_SCAN);
343 MWL8K_CMDNAME(SET_RF_CHANNEL);
ff45fc60
LB		 344 MWL8K_CMDNAME(SET_AID);
345 MWL8K_CMDNAME(SET_RATE);
346 MWL8K_CMDNAME(SET_FINALIZE_JOIN);
347 MWL8K_CMDNAME(RTS_THRESHOLD);
a66098da 348 MWL8K_CMDNAME(SET_SLOT);
ff45fc60
LB		 349 MWL8K_CMDNAME(SET_EDCA_PARAMS);
350 MWL8K_CMDNAME(SET_WMM_MODE);
a66098da 351 MWL8K_CMDNAME(MIMO_CONFIG);
ff45fc60 352 MWL8K_CMDNAME(USE_FIXED_RATE);
a66098da 353 MWL8K_CMDNAME(ENABLE_SNIFFER);
a66098da 354 MWL8K_CMDNAME(SET_RATEADAPT_MODE);
ff45fc60 355 MWL8K_CMDNAME(UPDATE_STADB);
a66098da
LB		 356 default:
357 snprintf(buf, bufsize, "0x%x", cmd);
358 }
359#undef MWL8K_CMDNAME
360
361 return buf;
362}
363
364/* Hardware and firmware reset */
365static void mwl8k_hw_reset(struct mwl8k_priv *priv)
366{
367 iowrite32(MWL8K_H2A_INT_RESET,
368 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
369 iowrite32(MWL8K_H2A_INT_RESET,
370 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
371 msleep(20);
372}
373
374/* Release fw image */
375static void mwl8k_release_fw(struct firmware **fw)
376{
377 if (*fw == NULL)
378 return;
379 release_firmware(*fw);
380 *fw = NULL;
381}
382
383static void mwl8k_release_firmware(struct mwl8k_priv *priv)
384{
385 mwl8k_release_fw(&priv->fw.ucode);
386 mwl8k_release_fw(&priv->fw.helper);
387}
388
389/* Request fw image */
390static int mwl8k_request_fw(struct mwl8k_priv *priv,
391 const char *fname, struct firmware **fw)
392{
393 /* release current image */
394 if (*fw != NULL)
395 mwl8k_release_fw(fw);
396
397 return request_firmware((const struct firmware **)fw,
398 fname, &priv->pdev->dev);
399}
400
401static int mwl8k_request_firmware(struct mwl8k_priv *priv, u32 part_num)
402{
403 u8 filename[64];
404 int rc;
405
406 priv->part_num = part_num;
407
408 snprintf(filename, sizeof(filename),
409 "mwl8k/helper_%u.fw", priv->part_num);
410
411 rc = mwl8k_request_fw(priv, filename, &priv->fw.helper);
412 if (rc) {
413 printk(KERN_ERR
414 "%s Error requesting helper firmware file %s\n",
415 pci_name(priv->pdev), filename);
416 return rc;
417 }
418
419 snprintf(filename, sizeof(filename),
420 "mwl8k/fmimage_%u.fw", priv->part_num);
421
422 rc = mwl8k_request_fw(priv, filename, &priv->fw.ucode);
423 if (rc) {
424 printk(KERN_ERR "%s Error requesting firmware file %s\n",
425 pci_name(priv->pdev), filename);
426 mwl8k_release_fw(&priv->fw.helper);
427 return rc;
428 }
429
430 return 0;
431}
432
433struct mwl8k_cmd_pkt {
434 __le16 code;
435 __le16 length;
436 __le16 seq_num;
437 __le16 result;
438 char payload[0];
439} __attribute__((packed));
440
441/*
442 * Firmware loading.
443 */
444static int
445mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
446{
447 void __iomem *regs = priv->regs;
448 dma_addr_t dma_addr;
449 int rc;
450 int loops;
451
452 dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
453 if (pci_dma_mapping_error(priv->pdev, dma_addr))
454 return -ENOMEM;
455
456 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
457 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
458 iowrite32(MWL8K_H2A_INT_DOORBELL,
459 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
460 iowrite32(MWL8K_H2A_INT_DUMMY,
461 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
462
463 rc = -ETIMEDOUT;
464 loops = 1000;
465 do {
466 u32 int_code;
467
468 int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
469 if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
470 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
471 rc = 0;
472 break;
473 }
474
475 udelay(1);
476 } while (--loops);
477
478 pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
479
480 /*
481 * Clear 'command done' interrupt bit.
482 */
483 loops = 1000;
484 do {
485 u32 status;
486
487 status = ioread32(priv->regs +
488 MWL8K_HIU_A2H_INTERRUPT_STATUS);
489 if (status & MWL8K_A2H_INT_OPC_DONE) {
490 iowrite32(~MWL8K_A2H_INT_OPC_DONE,
491 priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
492 ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
493 break;
494 }
495
496 udelay(1);
497 } while (--loops);
498
499 return rc;
500}
501
502static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
503 const u8 *data, size_t length)
504{
505 struct mwl8k_cmd_pkt *cmd;
506 int done;
507 int rc = 0;
508
509 cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
510 if (cmd == NULL)
511 return -ENOMEM;
512
513 cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
514 cmd->seq_num = 0;
515 cmd->result = 0;
516
517 done = 0;
518 while (length) {
519 int block_size = length > 256 ? 256 : length;
520
521 memcpy(cmd->payload, data + done, block_size);
522 cmd->length = cpu_to_le16(block_size);
523
524 rc = mwl8k_send_fw_load_cmd(priv, cmd,
525 sizeof(*cmd) + block_size);
526 if (rc)
527 break;
528
529 done += block_size;
530 length -= block_size;
531 }
532
533 if (!rc) {
534 cmd->length = 0;
535 rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
536 }
537
538 kfree(cmd);
539
540 return rc;
541}
542
543static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
544 const u8 *data, size_t length)
545{
546 unsigned char *buffer;
547 int may_continue, rc = 0;
548 u32 done, prev_block_size;
549
550 buffer = kmalloc(1024, GFP_KERNEL);
551 if (buffer == NULL)
552 return -ENOMEM;
553
554 done = 0;
555 prev_block_size = 0;
556 may_continue = 1000;
557 while (may_continue > 0) {
558 u32 block_size;
559
560 block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
561 if (block_size & 1) {
562 block_size &= ~1;
563 may_continue--;
564 } else {
565 done += prev_block_size;
566 length -= prev_block_size;
567 }
568
569 if (block_size > 1024 || block_size > length) {
570 rc = -EOVERFLOW;
571 break;
572 }
573
574 if (length == 0) {
575 rc = 0;
576 break;
577 }
578
579 if (block_size == 0) {
580 rc = -EPROTO;
581 may_continue--;
582 udelay(1);
583 continue;
584 }
585
586 prev_block_size = block_size;
587 memcpy(buffer, data + done, block_size);
588
589 rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
590 if (rc)
591 break;
592 }
593
594 if (!rc && length != 0)
595 rc = -EREMOTEIO;
596
597 kfree(buffer);
598
599 return rc;
600}
601
602static int mwl8k_load_firmware(struct mwl8k_priv *priv)
603{
604 int loops, rc;
605
606 const u8 *ucode = priv->fw.ucode->data;
607 size_t ucode_len = priv->fw.ucode->size;
608 const u8 *helper = priv->fw.helper->data;
609 size_t helper_len = priv->fw.helper->size;
610
611 if (!memcmp(ucode, "\x01\x00\x00\x00", 4)) {
612 rc = mwl8k_load_fw_image(priv, helper, helper_len);
613 if (rc) {
614 printk(KERN_ERR "%s: unable to load firmware "
615 "helper image\n", pci_name(priv->pdev));
616 return rc;
617 }
618 msleep(1);
619
620 rc = mwl8k_feed_fw_image(priv, ucode, ucode_len);
621 } else {
622 rc = mwl8k_load_fw_image(priv, ucode, ucode_len);
623 }
624
625 if (rc) {
626 printk(KERN_ERR "%s: unable to load firmware data\n",
627 pci_name(priv->pdev));
628 return rc;
629 }
630
631 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
632 msleep(1);
633
634 loops = 200000;
635 do {
636 if (ioread32(priv->regs + MWL8K_HIU_INT_CODE)
637 == MWL8K_FWSTA_READY)
638 break;
639 udelay(1);
640 } while (--loops);
641
642 return loops ? 0 : -ETIMEDOUT;
643}
644
645
646/*
647 * Defines shared between transmission and reception.
648 */
649/* HT control fields for firmware */
650struct ewc_ht_info {
651 __le16 control1;
652 __le16 control2;
653 __le16 control3;
654} __attribute__((packed));
655
656/* Firmware Station database operations */
657#define MWL8K_STA_DB_ADD_ENTRY 0
658#define MWL8K_STA_DB_MODIFY_ENTRY 1
659#define MWL8K_STA_DB_DEL_ENTRY 2
660#define MWL8K_STA_DB_FLUSH 3
661
662/* Peer Entry flags - used to define the type of the peer node */
663#define MWL8K_PEER_TYPE_ACCESSPOINT 2
a66098da
LB		 664
665#define MWL8K_IEEE_LEGACY_DATA_RATES 12
666#define MWL8K_MCS_BITMAP_SIZE 16
a66098da
LB		 667
668struct peer_capability_info {
669 /* Peer type - AP vs. STA. */
670 __u8 peer_type;
671
672 /* Basic 802.11 capabilities from assoc resp. */
673 __le16 basic_caps;
674
675 /* Set if peer supports 802.11n high throughput (HT). */
676 __u8 ht_support;
677
678 /* Valid if HT is supported. */
679 __le16 ht_caps;
680 __u8 extended_ht_caps;
681 struct ewc_ht_info ewc_info;
682
683 /* Legacy rate table. Intersection of our rates and peer rates. */
684 __u8 legacy_rates[MWL8K_IEEE_LEGACY_DATA_RATES];
685
686 /* HT rate table. Intersection of our rates and peer rates. */
687 __u8 ht_rates[MWL8K_MCS_BITMAP_SIZE];
c23b5a69 688 __u8 pad[16];
a66098da
LB		 689
690 /* If set, interoperability mode, no proprietary extensions. */
691 __u8 interop;
692 __u8 pad2;
693 __u8 station_id;
694 __le16 amsdu_enabled;
695} __attribute__((packed));
696
697/* Inline functions to manipulate QoS field in data descriptor. */
a66098da
LB		 698static inline u16 mwl8k_qos_setbit_eosp(u16 qos)
699{
700 u16 val_mask = 1 << 4;
701
702 /* End of Service Period Bit 4 */
703 return qos | val_mask;
704}
705
706static inline u16 mwl8k_qos_setbit_ack(u16 qos, u8 ack_policy)
707{
708 u16 val_mask = 0x3;
709 u8 shift = 5;
710 u16 qos_mask = ~(val_mask << shift);
711
712 /* Ack Policy Bit 5-6 */
713 return (qos & qos_mask) | ((ack_policy & val_mask) << shift);
714}
715
716static inline u16 mwl8k_qos_setbit_amsdu(u16 qos)
717{
718 u16 val_mask = 1 << 7;
719
720 /* AMSDU present Bit 7 */
721 return qos | val_mask;
722}
723
724static inline u16 mwl8k_qos_setbit_qlen(u16 qos, u8 len)
725{
726 u16 val_mask = 0xff;
727 u8 shift = 8;
728 u16 qos_mask = ~(val_mask << shift);
729
730 /* Queue Length Bits 8-15 */
731 return (qos & qos_mask) | ((len & val_mask) << shift);
732}
733
734/* DMA header used by firmware and hardware. */
735struct mwl8k_dma_data {
736 __le16 fwlen;
737 struct ieee80211_hdr wh;
738} __attribute__((packed));
739
740/* Routines to add/remove DMA header from skb. */
741static inline int mwl8k_remove_dma_header(struct sk_buff *skb)
742{
743 struct mwl8k_dma_data *tr = (struct mwl8k_dma_data *)(skb->data);
744 void *dst, *src = &tr->wh;
745 __le16 fc = tr->wh.frame_control;
746 int hdrlen = ieee80211_hdrlen(fc);
747 u16 space = sizeof(struct mwl8k_dma_data) - hdrlen;
748
749 dst = (void *)tr + space;
750 if (dst != src) {
751 memmove(dst, src, hdrlen);
752 skb_pull(skb, space);
753 }
754
755 return 0;
756}
757
758static inline struct sk_buff *mwl8k_add_dma_header(struct sk_buff *skb)
759{
760 struct ieee80211_hdr *wh;
761 u32 hdrlen, pktlen;
762 struct mwl8k_dma_data *tr;
763
764 wh = (struct ieee80211_hdr *)skb->data;
765 hdrlen = ieee80211_hdrlen(wh->frame_control);
766 pktlen = skb->len;
767
768 /*
769 * Copy up/down the 802.11 header; the firmware requires
770 * we present a 2-byte payload length followed by a
771 * 4-address header (w/o QoS), followed (optionally) by
772 * any WEP/ExtIV header (but only filled in for CCMP).
773 */
774 if (hdrlen != sizeof(struct mwl8k_dma_data))
775 skb_push(skb, sizeof(struct mwl8k_dma_data) - hdrlen);
776
777 tr = (struct mwl8k_dma_data *)skb->data;
778 if (wh != &tr->wh)
779 memmove(&tr->wh, wh, hdrlen);
780
781 /* Clear addr4 */
d89173f2 782 memset(tr->wh.addr4, 0, ETH_ALEN);
a66098da
LB		 783
784 /*
785 * Firmware length is the length of the fully formed "802.11
786 * payload". That is, everything except for the 802.11 header.
787 * This includes all crypto material including the MIC.
788 */
789 tr->fwlen = cpu_to_le16(pktlen - hdrlen);
790
791 return skb;
792}
793
794
795/*
796 * Packet reception.
797 */
a66098da 798#define MWL8K_RX_CTRL_OWNED_BY_HOST 0x02
a66098da
LB		 799
800struct mwl8k_rx_desc {
801 __le16 pkt_len;
802 __u8 link_quality;
803 __u8 noise_level;
804 __le32 pkt_phys_addr;
805 __le32 next_rx_desc_phys_addr;
806 __le16 qos_control;
807 __le16 rate_info;
808 __le32 pad0[4];
809 __u8 rssi;
810 __u8 channel;
811 __le16 pad1;
812 __u8 rx_ctrl;
813 __u8 rx_status;
814 __u8 pad2[2];
815} __attribute__((packed));
816
817#define MWL8K_RX_DESCS 256
818#define MWL8K_RX_MAXSZ 3800
819
820static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
821{
822 struct mwl8k_priv *priv = hw->priv;
823 struct mwl8k_rx_queue *rxq = priv->rxq + index;
824 int size;
825 int i;
826
827 rxq->rx_desc_count = 0;
828 rxq->rx_head = 0;
829 rxq->rx_tail = 0;
830
831 size = MWL8K_RX_DESCS * sizeof(struct mwl8k_rx_desc);
832
833 rxq->rx_desc_area =
834 pci_alloc_consistent(priv->pdev, size, &rxq->rx_desc_dma);
835 if (rxq->rx_desc_area == NULL) {
836 printk(KERN_ERR "%s: failed to alloc RX descriptors\n",
837 priv->name);
838 return -ENOMEM;
839 }
840 memset(rxq->rx_desc_area, 0, size);
841
842 rxq->rx_skb = kmalloc(MWL8K_RX_DESCS *
843 sizeof(*rxq->rx_skb), GFP_KERNEL);
844 if (rxq->rx_skb == NULL) {
845 printk(KERN_ERR "%s: failed to alloc RX skbuff list\n",
846 priv->name);
847 pci_free_consistent(priv->pdev, size,
848 rxq->rx_desc_area, rxq->rx_desc_dma);
849 return -ENOMEM;
850 }
851 memset(rxq->rx_skb, 0, MWL8K_RX_DESCS * sizeof(*rxq->rx_skb));
852
853 for (i = 0; i < MWL8K_RX_DESCS; i++) {
854 struct mwl8k_rx_desc *rx_desc;
855 int nexti;
856
857 rx_desc = rxq->rx_desc_area + i;
858 nexti = (i + 1) % MWL8K_RX_DESCS;
859
860 rx_desc->next_rx_desc_phys_addr =
861 cpu_to_le32(rxq->rx_desc_dma
862 + nexti * sizeof(*rx_desc));
c491bf12 863 rx_desc->rx_ctrl = MWL8K_RX_CTRL_OWNED_BY_HOST;
a66098da
LB		 864 }
865
866 return 0;
867}
868
869static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
870{
871 struct mwl8k_priv *priv = hw->priv;
872 struct mwl8k_rx_queue *rxq = priv->rxq + index;
873 int refilled;
874
875 refilled = 0;
876 while (rxq->rx_desc_count < MWL8K_RX_DESCS && limit--) {
877 struct sk_buff *skb;
878 int rx;
879
880 skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
881 if (skb == NULL)
882 break;
883
884 rxq->rx_desc_count++;
885
886 rx = rxq->rx_tail;
887 rxq->rx_tail = (rx + 1) % MWL8K_RX_DESCS;
888
889 rxq->rx_desc_area[rx].pkt_phys_addr =
890 cpu_to_le32(pci_map_single(priv->pdev, skb->data,
891 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE));
892
893 rxq->rx_desc_area[rx].pkt_len = cpu_to_le16(MWL8K_RX_MAXSZ);
894 rxq->rx_skb[rx] = skb;
895 wmb();
896 rxq->rx_desc_area[rx].rx_ctrl = 0;
897
898 refilled++;
899 }
900
901 return refilled;
902}
903
904/* Must be called only when the card's reception is completely halted */
905static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
906{
907 struct mwl8k_priv *priv = hw->priv;
908 struct mwl8k_rx_queue *rxq = priv->rxq + index;
909 int i;
910
911 for (i = 0; i < MWL8K_RX_DESCS; i++) {
912 if (rxq->rx_skb[i] != NULL) {
913 unsigned long addr;
914
915 addr = le32_to_cpu(rxq->rx_desc_area[i].pkt_phys_addr);
916 pci_unmap_single(priv->pdev, addr, MWL8K_RX_MAXSZ,
917 PCI_DMA_FROMDEVICE);
918 kfree_skb(rxq->rx_skb[i]);
919 rxq->rx_skb[i] = NULL;
920 }
921 }
922
923 kfree(rxq->rx_skb);
924 rxq->rx_skb = NULL;
925
926 pci_free_consistent(priv->pdev,
927 MWL8K_RX_DESCS * sizeof(struct mwl8k_rx_desc),
928 rxq->rx_desc_area, rxq->rx_desc_dma);
929 rxq->rx_desc_area = NULL;
930}
931
932
933/*
934 * Scan a list of BSSIDs to process for finalize join.
935 * Allows for extension to process multiple BSSIDs.
936 */
937static inline int
938mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
939{
940 return priv->capture_beacon &&
941 ieee80211_is_beacon(wh->frame_control) &&
942 !compare_ether_addr(wh->addr3, priv->capture_bssid);
943}
944
945static inline void mwl8k_save_beacon(struct mwl8k_priv *priv,
946 struct sk_buff *skb)
947{
948 priv->capture_beacon = false;
d89173f2 949 memset(priv->capture_bssid, 0, ETH_ALEN);
a66098da
LB		 950
951 /*
952 * Use GFP_ATOMIC as rxq_process is called from
953 * the primary interrupt handler, memory allocation call
954 * must not sleep.
955 */
956 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
957 if (priv->beacon_skb != NULL)
958 queue_work(priv->config_wq,
959 &priv->finalize_join_worker);
960}
961
962static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
963{
964 struct mwl8k_priv *priv = hw->priv;
965 struct mwl8k_rx_queue *rxq = priv->rxq + index;
966 int processed;
967
968 processed = 0;
969 while (rxq->rx_desc_count && limit--) {
970 struct mwl8k_rx_desc *rx_desc;
971 struct sk_buff *skb;
972 struct ieee80211_rx_status status;
973 unsigned long addr;
974 struct ieee80211_hdr *wh;
975
976 rx_desc = rxq->rx_desc_area + rxq->rx_head;
977 if (!(rx_desc->rx_ctrl & MWL8K_RX_CTRL_OWNED_BY_HOST))
978 break;
979 rmb();
980
981 skb = rxq->rx_skb[rxq->rx_head];
d25f9f13
LB		 982 if (skb == NULL)
983 break;
a66098da
LB		 984 rxq->rx_skb[rxq->rx_head] = NULL;
985
986 rxq->rx_head = (rxq->rx_head + 1) % MWL8K_RX_DESCS;
987 rxq->rx_desc_count--;
988
989 addr = le32_to_cpu(rx_desc->pkt_phys_addr);
990 pci_unmap_single(priv->pdev, addr,
991 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
992
993 skb_put(skb, le16_to_cpu(rx_desc->pkt_len));
994 if (mwl8k_remove_dma_header(skb)) {
995 dev_kfree_skb(skb);
996 continue;
997 }
998
999 wh = (struct ieee80211_hdr *)skb->data;
1000
1001 /*
1002 * Check for pending join operation. save a copy of
1003 * the beacon and schedule a tasklet to send finalize
1004 * join command to the firmware.
1005 */
1006 if (mwl8k_capture_bssid(priv, wh))
1007 mwl8k_save_beacon(priv, skb);
1008
1009 memset(&status, 0, sizeof(status));
1010 status.mactime = 0;
1011 status.signal = -rx_desc->rssi;
1012 status.noise = -rx_desc->noise_level;
1013 status.qual = rx_desc->link_quality;
1014 status.antenna = 1;
1015 status.rate_idx = 1;
1016 status.flag = 0;
1017 status.band = IEEE80211_BAND_2GHZ;
1018 status.freq = ieee80211_channel_to_frequency(rx_desc->channel);
f1d58c25
JB		 1019 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
1020 ieee80211_rx_irqsafe(hw, skb);
a66098da
LB		 1021
1022 processed++;
1023 }
1024
1025 return processed;
1026}
1027
1028
1029/*
1030 * Packet transmission.
1031 */
1032
1033/* Transmit queue assignment. */
1034enum {
1035 MWL8K_WME_AC_BK = 0, /* background access */
1036 MWL8K_WME_AC_BE = 1, /* best effort access */
1037 MWL8K_WME_AC_VI = 2, /* video access */
1038 MWL8K_WME_AC_VO = 3, /* voice access */
1039};
1040
1041/* Transmit packet ACK policy */
1042#define MWL8K_TXD_ACK_POLICY_NORMAL 0
a66098da
LB		 1043#define MWL8K_TXD_ACK_POLICY_BLOCKACK 3
1044
1045#define GET_TXQ(_ac) (\
1046 ((_ac) == WME_AC_VO) ? MWL8K_WME_AC_VO : \
1047 ((_ac) == WME_AC_VI) ? MWL8K_WME_AC_VI : \
1048 ((_ac) == WME_AC_BK) ? MWL8K_WME_AC_BK : \
1049 MWL8K_WME_AC_BE)
1050
a66098da
LB		 1051#define MWL8K_TXD_STATUS_OK 0x00000001
1052#define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
1053#define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
1054#define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
a66098da 1055#define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
a66098da
LB		 1056
1057struct mwl8k_tx_desc {
1058 __le32 status;
1059 __u8 data_rate;
1060 __u8 tx_priority;
1061 __le16 qos_control;
1062 __le32 pkt_phys_addr;
1063 __le16 pkt_len;
d89173f2 1064 __u8 dest_MAC_addr[ETH_ALEN];
a66098da
LB		 1065 __le32 next_tx_desc_phys_addr;
1066 __le32 reserved;
1067 __le16 rate_info;
1068 __u8 peer_id;
1069 __u8 tx_frag_cnt;
1070} __attribute__((packed));
1071
1072#define MWL8K_TX_DESCS 128
1073
1074static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
1075{
1076 struct mwl8k_priv *priv = hw->priv;
1077 struct mwl8k_tx_queue *txq = priv->txq + index;
1078 int size;
1079 int i;
1080
1081 memset(&txq->tx_stats, 0,
1082 sizeof(struct ieee80211_tx_queue_stats));
1083 txq->tx_stats.limit = MWL8K_TX_DESCS;
1084 txq->tx_head = 0;
1085 txq->tx_tail = 0;
1086
1087 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
1088
1089 txq->tx_desc_area =
1090 pci_alloc_consistent(priv->pdev, size, &txq->tx_desc_dma);
1091 if (txq->tx_desc_area == NULL) {
1092 printk(KERN_ERR "%s: failed to alloc TX descriptors\n",
1093 priv->name);
1094 return -ENOMEM;
1095 }
1096 memset(txq->tx_desc_area, 0, size);
1097
1098 txq->tx_skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->tx_skb),
1099 GFP_KERNEL);
1100 if (txq->tx_skb == NULL) {
1101 printk(KERN_ERR "%s: failed to alloc TX skbuff list\n",
1102 priv->name);
1103 pci_free_consistent(priv->pdev, size,
1104 txq->tx_desc_area, txq->tx_desc_dma);
1105 return -ENOMEM;
1106 }
1107 memset(txq->tx_skb, 0, MWL8K_TX_DESCS * sizeof(*txq->tx_skb));
1108
1109 for (i = 0; i < MWL8K_TX_DESCS; i++) {
1110 struct mwl8k_tx_desc *tx_desc;
1111 int nexti;
1112
1113 tx_desc = txq->tx_desc_area + i;
1114 nexti = (i + 1) % MWL8K_TX_DESCS;
1115
1116 tx_desc->status = 0;
1117 tx_desc->next_tx_desc_phys_addr =
1118 cpu_to_le32(txq->tx_desc_dma +
1119 nexti * sizeof(*tx_desc));
1120 }
1121
1122 return 0;
1123}
1124
1125static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
1126{
1127 iowrite32(MWL8K_H2A_INT_PPA_READY,
1128 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1129 iowrite32(MWL8K_H2A_INT_DUMMY,
1130 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1131 ioread32(priv->regs + MWL8K_HIU_INT_CODE);
1132}
1133
1134static inline int mwl8k_txq_busy(struct mwl8k_priv *priv)
1135{
1136 return priv->pending_tx_pkts;
1137}
1138
1139struct mwl8k_txq_info {
1140 u32 fw_owned;
1141 u32 drv_owned;
1142 u32 unused;
1143 u32 len;
1144 u32 head;
1145 u32 tail;
1146};
1147
1148static int mwl8k_scan_tx_ring(struct mwl8k_priv *priv,
1149 struct mwl8k_txq_info txinfo[],
1150 u32 num_queues)
1151{
1152 int count, desc, status;
1153 struct mwl8k_tx_queue *txq;
1154 struct mwl8k_tx_desc *tx_desc;
1155 int ndescs = 0;
1156
1157 memset(txinfo, 0, num_queues * sizeof(struct mwl8k_txq_info));
1158 spin_lock_bh(&priv->tx_lock);
1159 for (count = 0; count < num_queues; count++) {
1160 txq = priv->txq + count;
1161 txinfo[count].len = txq->tx_stats.len;
1162 txinfo[count].head = txq->tx_head;
1163 txinfo[count].tail = txq->tx_tail;
1164 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
1165 tx_desc = txq->tx_desc_area + desc;
1166 status = le32_to_cpu(tx_desc->status);
1167
1168 if (status & MWL8K_TXD_STATUS_FW_OWNED)
1169 txinfo[count].fw_owned++;
1170 else
1171 txinfo[count].drv_owned++;
1172
1173 if (tx_desc->pkt_len == 0)
1174 txinfo[count].unused++;
1175 }
1176 }
1177 spin_unlock_bh(&priv->tx_lock);
1178
1179 return ndescs;
1180}
1181
1182static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw, u32 delay_ms)
1183{
1184 u32 count = 0;
1185 unsigned long timeout = 0;
1186 struct mwl8k_priv *priv = hw->priv;
1187 DECLARE_COMPLETION_ONSTACK(cmd_wait);
1188
1189 might_sleep();
1190
1191 if (priv->tx_wait != NULL)
1192 printk(KERN_ERR "WARNING Previous TXWaitEmpty instance\n");
1193
1194 spin_lock_bh(&priv->tx_lock);
1195 count = mwl8k_txq_busy(priv);
1196 if (count) {
1197 priv->tx_wait = &cmd_wait;
1198 if (priv->radio_state)
1199 mwl8k_tx_start(priv);
1200 }
1201 spin_unlock_bh(&priv->tx_lock);
1202
1203 if (count) {
1204 struct mwl8k_txq_info txinfo[4];
1205 int index;
1206 int newcount;
1207
1208 timeout = wait_for_completion_timeout(&cmd_wait,
1209 msecs_to_jiffies(delay_ms));
1210 if (timeout)
1211 return 0;
1212
1213 spin_lock_bh(&priv->tx_lock);
1214 priv->tx_wait = NULL;
1215 newcount = mwl8k_txq_busy(priv);
1216 spin_unlock_bh(&priv->tx_lock);
1217
1218 printk(KERN_ERR "%s(%u) TIMEDOUT:%ums Pend:%u-->%u\n",
1219 __func__, __LINE__, delay_ms, count, newcount);
1220
1221 mwl8k_scan_tx_ring(priv, txinfo, 4);
1222 for (index = 0 ; index < 4; index++)
1223 printk(KERN_ERR
1224 "TXQ:%u L:%u H:%u T:%u FW:%u DRV:%u U:%u\n",
1225 index,
1226 txinfo[index].len,
1227 txinfo[index].head,
1228 txinfo[index].tail,
1229 txinfo[index].fw_owned,
1230 txinfo[index].drv_owned,
1231 txinfo[index].unused);
1232 return -ETIMEDOUT;
1233 }
1234
1235 return 0;
1236}
1237
c23b5a69
LB		 1238#define MWL8K_TXD_SUCCESS(status) \
1239 ((status) & (MWL8K_TXD_STATUS_OK | \
1240 MWL8K_TXD_STATUS_OK_RETRY | \
1241 MWL8K_TXD_STATUS_OK_MORE_RETRY))
a66098da
LB		 1242
1243static void mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int force)
1244{
1245 struct mwl8k_priv *priv = hw->priv;
1246 struct mwl8k_tx_queue *txq = priv->txq + index;
1247 int wake = 0;
1248
1249 while (txq->tx_stats.len > 0) {
1250 int tx;
1251 int rc;
1252 struct mwl8k_tx_desc *tx_desc;
1253 unsigned long addr;
1254 size_t size;
1255 struct sk_buff *skb;
1256 struct ieee80211_tx_info *info;
1257 u32 status;
1258
1259 rc = 0;
1260 tx = txq->tx_head;
1261 tx_desc = txq->tx_desc_area + tx;
1262
1263 status = le32_to_cpu(tx_desc->status);
1264
1265 if (status & MWL8K_TXD_STATUS_FW_OWNED) {
1266 if (!force)
1267 break;
1268 tx_desc->status &=
1269 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
1270 }
1271
1272 txq->tx_head = (tx + 1) % MWL8K_TX_DESCS;
1273 BUG_ON(txq->tx_stats.len == 0);
1274 txq->tx_stats.len--;
1275 priv->pending_tx_pkts--;
1276
1277 addr = le32_to_cpu(tx_desc->pkt_phys_addr);
1278 size = (u32)(le16_to_cpu(tx_desc->pkt_len));
1279 skb = txq->tx_skb[tx].skb;
1280 txq->tx_skb[tx].skb = NULL;
1281
1282 BUG_ON(skb == NULL);
1283 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
1284
1285 rc = mwl8k_remove_dma_header(skb);
1286
1287 /* Mark descriptor as unused */
1288 tx_desc->pkt_phys_addr = 0;
1289 tx_desc->pkt_len = 0;
1290
1291 if (txq->tx_skb[tx].clone) {
1292 /* Replace with original skb
1293 * before returning to stack
1294 * as buffer has been cloned
1295 */
1296 dev_kfree_skb(skb);
1297 skb = txq->tx_skb[tx].clone;
1298 txq->tx_skb[tx].clone = NULL;
1299 }
1300
1301 if (rc) {
1302 /* Something has gone wrong here.
1303 * Failed to remove DMA header.
1304 * Print error message and drop packet.
1305 */
1306 printk(KERN_ERR "%s: Error removing DMA header from "
1307 "tx skb 0x%p.\n", priv->name, skb);
1308
1309 dev_kfree_skb(skb);
1310 continue;
1311 }
1312
1313 info = IEEE80211_SKB_CB(skb);
1314 ieee80211_tx_info_clear_status(info);
1315
1316 /* Convert firmware status stuff into tx_status */
1317 if (MWL8K_TXD_SUCCESS(status)) {
1318 /* Transmit OK */
1319 info->flags |= IEEE80211_TX_STAT_ACK;
1320 }
1321
1322 ieee80211_tx_status_irqsafe(hw, skb);
1323
1324 wake = !priv->inconfig && priv->radio_state;
1325 }
1326
1327 if (wake)
1328 ieee80211_wake_queue(hw, index);
1329}
1330
1331/* must be called only when the card's transmit is completely halted */
1332static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
1333{
1334 struct mwl8k_priv *priv = hw->priv;
1335 struct mwl8k_tx_queue *txq = priv->txq + index;
1336
1337 mwl8k_txq_reclaim(hw, index, 1);
1338
1339 kfree(txq->tx_skb);
1340 txq->tx_skb = NULL;
1341
1342 pci_free_consistent(priv->pdev,
1343 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
1344 txq->tx_desc_area, txq->tx_desc_dma);
1345 txq->tx_desc_area = NULL;
1346}
1347
1348static int
1349mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
1350{
1351 struct mwl8k_priv *priv = hw->priv;
1352 struct ieee80211_tx_info *tx_info;
1353 struct ieee80211_hdr *wh;
1354 struct mwl8k_tx_queue *txq;
1355 struct mwl8k_tx_desc *tx;
1356 struct mwl8k_dma_data *tr;
1357 struct mwl8k_vif *mwl8k_vif;
1358 struct sk_buff *org_skb = skb;
1359 dma_addr_t dma;
1360 u16 qos = 0;
1361 bool qosframe = false, ampduframe = false;
1362 bool mcframe = false, eapolframe = false;
1363 bool amsduframe = false;
1364 __le16 fc;
1365
1366 txq = priv->txq + index;
1367 tx = txq->tx_desc_area + txq->tx_tail;
1368
1369 BUG_ON(txq->tx_skb[txq->tx_tail].skb != NULL);
1370
1371 /*
1372 * Append HW DMA header to start of packet. Drop packet if
1373 * there is not enough space or a failure to unshare/unclone
1374 * the skb.
1375 */
1376 skb = mwl8k_add_dma_header(skb);
1377
1378 if (skb == NULL) {
1379 printk(KERN_DEBUG "%s: failed to prepend HW DMA "
1380 "header, dropping TX frame.\n", priv->name);
1381 dev_kfree_skb(org_skb);
1382 return NETDEV_TX_OK;
1383 }
1384
1385 tx_info = IEEE80211_SKB_CB(skb);
1386 mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
1387 tr = (struct mwl8k_dma_data *)skb->data;
1388 wh = &tr->wh;
1389 fc = wh->frame_control;
1390 qosframe = ieee80211_is_data_qos(fc);
1391 mcframe = is_multicast_ether_addr(wh->addr1);
1392 ampduframe = !!(tx_info->flags & IEEE80211_TX_CTL_AMPDU);
1393
1394 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1395 u16 seqno = mwl8k_vif->seqno;
1396 wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1397 wh->seq_ctrl |= cpu_to_le16(seqno << 4);
1398 mwl8k_vif->seqno = seqno++ % 4096;
1399 }
1400
1401 if (qosframe)
1402 qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
1403
1404 dma = pci_map_single(priv->pdev, skb->data,
1405 skb->len, PCI_DMA_TODEVICE);
1406
1407 if (pci_dma_mapping_error(priv->pdev, dma)) {
1408 printk(KERN_DEBUG "%s: failed to dma map skb, "
1409 "dropping TX frame.\n", priv->name);
1410
1411 if (org_skb != NULL)
1412 dev_kfree_skb(org_skb);
1413 if (skb != NULL)
1414 dev_kfree_skb(skb);
1415 return NETDEV_TX_OK;
1416 }
1417
1418 /* Set desc header, cpu bit order. */
1419 tx->status = 0;
1420 tx->data_rate = 0;
1421 tx->tx_priority = index;
1422 tx->qos_control = 0;
1423 tx->rate_info = 0;
1424 tx->peer_id = mwl8k_vif->peer_id;
1425
1426 amsduframe = !!(qos & IEEE80211_QOS_CONTROL_A_MSDU_PRESENT);
1427
1428 /* Setup firmware control bit fields for each frame type. */
1429 if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc)) {
1430 tx->data_rate = 0;
1431 qos = mwl8k_qos_setbit_eosp(qos);
1432 /* Set Queue size to unspecified */
1433 qos = mwl8k_qos_setbit_qlen(qos, 0xff);
1434 } else if (ieee80211_is_data(fc)) {
1435 tx->data_rate = 1;
1436 if (mcframe)
1437 tx->status |= MWL8K_TXD_STATUS_MULTICAST_TX;
1438
1439 /*
1440 * Tell firmware to not send EAPOL pkts in an
1441 * aggregate. Verify against mac80211 tx path. If
1442 * stack turns off AMPDU for an EAPOL frame this
1443 * check will be removed.
1444 */
1445 if (eapolframe) {
1446 qos = mwl8k_qos_setbit_ack(qos,
1447 MWL8K_TXD_ACK_POLICY_NORMAL);
1448 } else {
1449 /* Send pkt in an aggregate if AMPDU frame. */
1450 if (ampduframe)
1451 qos = mwl8k_qos_setbit_ack(qos,
1452 MWL8K_TXD_ACK_POLICY_BLOCKACK);
1453 else
1454 qos = mwl8k_qos_setbit_ack(qos,
1455 MWL8K_TXD_ACK_POLICY_NORMAL);
1456
1457 if (amsduframe)
1458 qos = mwl8k_qos_setbit_amsdu(qos);
1459 }
1460 }
1461
1462 /* Convert to little endian */
1463 tx->qos_control = cpu_to_le16(qos);
1464 tx->status = cpu_to_le32(tx->status);
1465 tx->pkt_phys_addr = cpu_to_le32(dma);
1466 tx->pkt_len = cpu_to_le16(skb->len);
1467
1468 txq->tx_skb[txq->tx_tail].skb = skb;
1469 txq->tx_skb[txq->tx_tail].clone =
1470 skb == org_skb ? NULL : org_skb;
1471
1472 spin_lock_bh(&priv->tx_lock);
1473
1474 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_OK |
1475 MWL8K_TXD_STATUS_FW_OWNED);
1476 wmb();
1477 txq->tx_stats.len++;
1478 priv->pending_tx_pkts++;
1479 txq->tx_stats.count++;
1480 txq->tx_tail++;
1481
1482 if (txq->tx_tail == MWL8K_TX_DESCS)
1483 txq->tx_tail = 0;
1484 if (txq->tx_head == txq->tx_tail)
1485 ieee80211_stop_queue(hw, index);
1486
1487 if (priv->inconfig) {
1488 /*
1489 * Silently queue packet when we are in the middle of
1490 * a config cycle. Notify firmware only if we are
1491 * waiting for TXQs to empty. If a packet is sent
1492 * before .config() is complete, perhaps it is better
1493 * to drop the packet, as the channel is being changed
1494 * and the packet will end up on the wrong channel.
1495 */
1496 printk(KERN_ERR "%s(): WARNING TX activity while "
1497 "in config\n", __func__);
1498
1499 if (priv->tx_wait != NULL)
1500 mwl8k_tx_start(priv);
1501 } else
1502 mwl8k_tx_start(priv);
1503
1504 spin_unlock_bh(&priv->tx_lock);
1505
1506 return NETDEV_TX_OK;
1507}
1508
1509
1510/*
1511 * Command processing.
1512 */
1513
1514/* Timeout firmware commands after 2000ms */
1515#define MWL8K_CMD_TIMEOUT_MS 2000
1516
1517static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
1518{
1519 DECLARE_COMPLETION_ONSTACK(cmd_wait);
1520 struct mwl8k_priv *priv = hw->priv;
1521 void __iomem *regs = priv->regs;
1522 dma_addr_t dma_addr;
1523 unsigned int dma_size;
1524 int rc;
1525 u16 __iomem *result;
1526 unsigned long timeout = 0;
1527 u8 buf[32];
1528
1529 cmd->result = 0xFFFF;
1530 dma_size = le16_to_cpu(cmd->length);
1531 dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
1532 PCI_DMA_BIDIRECTIONAL);
1533 if (pci_dma_mapping_error(priv->pdev, dma_addr))
1534 return -ENOMEM;
1535
1536 if (priv->hostcmd_wait != NULL)
1537 printk(KERN_ERR "WARNING host command in progress\n");
1538
1539 spin_lock_irq(&priv->fw_lock);
1540 priv->hostcmd_wait = &cmd_wait;
1541 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
1542 iowrite32(MWL8K_H2A_INT_DOORBELL,
1543 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1544 iowrite32(MWL8K_H2A_INT_DUMMY,
1545 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1546 spin_unlock_irq(&priv->fw_lock);
1547
1548 timeout = wait_for_completion_timeout(&cmd_wait,
1549 msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
1550
37055bd4
LB		 1551 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1552 PCI_DMA_BIDIRECTIONAL);
1553
a66098da
LB		 1554 result = &cmd->result;
1555 if (!timeout) {
1556 spin_lock_irq(&priv->fw_lock);
1557 priv->hostcmd_wait = NULL;
1558 spin_unlock_irq(&priv->fw_lock);
1559 printk(KERN_ERR "%s: Command %s timeout after %u ms\n",
1560 priv->name,
1561 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1562 MWL8K_CMD_TIMEOUT_MS);
1563 rc = -ETIMEDOUT;
1564 } else {
1565 rc = *result ? -EINVAL : 0;
1566 if (rc)
1567 printk(KERN_ERR "%s: Command %s error 0x%x\n",
1568 priv->name,
1569 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1570 *result);
1571 }
1572
a66098da
LB		 1573 return rc;
1574}
1575
1576/*
1577 * GET_HW_SPEC.
1578 */
1579struct mwl8k_cmd_get_hw_spec {
1580 struct mwl8k_cmd_pkt header;
1581 __u8 hw_rev;
1582 __u8 host_interface;
1583 __le16 num_mcaddrs;
d89173f2 1584 __u8 perm_addr[ETH_ALEN];
a66098da
LB		 1585 __le16 region_code;
1586 __le32 fw_rev;
1587 __le32 ps_cookie;
1588 __le32 caps;
1589 __u8 mcs_bitmap[16];
1590 __le32 rx_queue_ptr;
1591 __le32 num_tx_queues;
1592 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1593 __le32 caps2;
1594 __le32 num_tx_desc_per_queue;
1595 __le32 total_rx_desc;
1596} __attribute__((packed));
1597
1598static int mwl8k_cmd_get_hw_spec(struct ieee80211_hw *hw)
1599{
1600 struct mwl8k_priv *priv = hw->priv;
1601 struct mwl8k_cmd_get_hw_spec *cmd;
1602 int rc;
1603 int i;
1604
1605 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1606 if (cmd == NULL)
1607 return -ENOMEM;
1608
1609 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1610 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1611
1612 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1613 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1614 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rx_desc_dma);
4ff6432e 1615 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
a66098da
LB		 1616 for (i = 0; i < MWL8K_TX_QUEUES; i++)
1617 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].tx_desc_dma);
4ff6432e
LB		 1618 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
1619 cmd->total_rx_desc = cpu_to_le32(MWL8K_RX_DESCS);
a66098da
LB		 1620
1621 rc = mwl8k_post_cmd(hw, &cmd->header);
1622
1623 if (!rc) {
1624 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1625 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
4ff6432e 1626 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
a66098da 1627 priv->hw_rev = cmd->hw_rev;
a66098da
LB		 1628 }
1629
1630 kfree(cmd);
1631 return rc;
1632}
1633
1634/*
1635 * CMD_MAC_MULTICAST_ADR.
1636 */
1637struct mwl8k_cmd_mac_multicast_adr {
1638 struct mwl8k_cmd_pkt header;
1639 __le16 action;
1640 __le16 numaddr;
d89173f2 1641 __u8 addr[1][ETH_ALEN];
a66098da
LB		 1642};
1643
1644#define MWL8K_ENABLE_RX_MULTICAST 0x000F
1645static int mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw,
1646 int mc_count,
1647 struct dev_addr_list *mclist)
1648{
1649 struct mwl8k_cmd_mac_multicast_adr *cmd;
1650 int index = 0;
1651 int rc;
d89173f2 1652 int size = sizeof(*cmd) + ((mc_count - 1) * ETH_ALEN);
a66098da
LB		 1653 cmd = kzalloc(size, GFP_KERNEL);
1654 if (cmd == NULL)
1655 return -ENOMEM;
1656
1657 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
1658 cmd->header.length = cpu_to_le16(size);
1659 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
1660 cmd->numaddr = cpu_to_le16(mc_count);
1661 while ((index < mc_count) && mclist) {
d89173f2 1662 if (mclist->da_addrlen != ETH_ALEN) {
a66098da
LB		 1663 rc = -EINVAL;
1664 goto mwl8k_cmd_mac_multicast_adr_exit;
1665 }
d89173f2 1666 memcpy(cmd->addr[index], mclist->da_addr, ETH_ALEN);
a66098da
LB		 1667 index++;
1668 mclist = mclist->next;
1669 }
1670
1671 rc = mwl8k_post_cmd(hw, &cmd->header);
1672
1673mwl8k_cmd_mac_multicast_adr_exit:
1674 kfree(cmd);
1675 return rc;
1676}
1677
1678/*
1679 * CMD_802_11_GET_STAT.
1680 */
1681struct mwl8k_cmd_802_11_get_stat {
1682 struct mwl8k_cmd_pkt header;
1683 __le16 action;
1684 __le32 stats[64];
1685} __attribute__((packed));
1686
1687#define MWL8K_STAT_ACK_FAILURE 9
1688#define MWL8K_STAT_RTS_FAILURE 12
1689#define MWL8K_STAT_FCS_ERROR 24
1690#define MWL8K_STAT_RTS_SUCCESS 11
1691
1692static int mwl8k_cmd_802_11_get_stat(struct ieee80211_hw *hw,
1693 struct ieee80211_low_level_stats *stats)
1694{
1695 struct mwl8k_cmd_802_11_get_stat *cmd;
1696 int rc;
1697
1698 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1699 if (cmd == NULL)
1700 return -ENOMEM;
1701
1702 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
1703 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1704 cmd->action = cpu_to_le16(MWL8K_CMD_GET);
1705
1706 rc = mwl8k_post_cmd(hw, &cmd->header);
1707 if (!rc) {
1708 stats->dot11ACKFailureCount =
1709 le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
1710 stats->dot11RTSFailureCount =
1711 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
1712 stats->dot11FCSErrorCount =
1713 le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
1714 stats->dot11RTSSuccessCount =
1715 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
1716 }
1717 kfree(cmd);
1718
1719 return rc;
1720}
1721
1722/*
1723 * CMD_802_11_RADIO_CONTROL.
1724 */
1725struct mwl8k_cmd_802_11_radio_control {
1726 struct mwl8k_cmd_pkt header;
1727 __le16 action;
1728 __le16 control;
1729 __le16 radio_on;
1730} __attribute__((packed));
1731
1732static int mwl8k_cmd_802_11_radio_control(struct ieee80211_hw *hw, int enable)
1733{
1734 struct mwl8k_priv *priv = hw->priv;
1735 struct mwl8k_cmd_802_11_radio_control *cmd;
1736 int rc;
1737
1738 if (((enable & MWL8K_RADIO_ENABLE) == priv->radio_state) &&
1739 !(enable & MWL8K_RADIO_FORCE))
1740 return 0;
1741
1742 enable &= MWL8K_RADIO_ENABLE;
1743
1744 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1745 if (cmd == NULL)
1746 return -ENOMEM;
1747
1748 cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
1749 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1750 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1751 cmd->control = cpu_to_le16(priv->radio_preamble);
1752 cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
1753
1754 rc = mwl8k_post_cmd(hw, &cmd->header);
1755 kfree(cmd);
1756
1757 if (!rc)
1758 priv->radio_state = enable;
1759
1760 return rc;
1761}
1762
1763static int
1764mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
1765{
1766 struct mwl8k_priv *priv;
1767
1768 if (hw == NULL || hw->priv == NULL)
1769 return -EINVAL;
1770 priv = hw->priv;
1771
1772 priv->radio_preamble = (short_preamble ?
1773 MWL8K_RADIO_SHORT_PREAMBLE :
1774 MWL8K_RADIO_LONG_PREAMBLE);
1775
1776 return mwl8k_cmd_802_11_radio_control(hw,
1777 MWL8K_RADIO_ENABLE | MWL8K_RADIO_FORCE);
1778}
1779
1780/*
1781 * CMD_802_11_RF_TX_POWER.
1782 */
1783#define MWL8K_TX_POWER_LEVEL_TOTAL 8
1784
1785struct mwl8k_cmd_802_11_rf_tx_power {
1786 struct mwl8k_cmd_pkt header;
1787 __le16 action;
1788 __le16 support_level;
1789 __le16 current_level;
1790 __le16 reserved;
1791 __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
1792} __attribute__((packed));
1793
1794static int mwl8k_cmd_802_11_rf_tx_power(struct ieee80211_hw *hw, int dBm)
1795{
1796 struct mwl8k_cmd_802_11_rf_tx_power *cmd;
1797 int rc;
1798
1799 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1800 if (cmd == NULL)
1801 return -ENOMEM;
1802
1803 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
1804 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1805 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1806 cmd->support_level = cpu_to_le16(dBm);
1807
1808 rc = mwl8k_post_cmd(hw, &cmd->header);
1809 kfree(cmd);
1810
1811 return rc;
1812}
1813
1814/*
1815 * CMD_SET_PRE_SCAN.
1816 */
1817struct mwl8k_cmd_set_pre_scan {
1818 struct mwl8k_cmd_pkt header;
1819} __attribute__((packed));
1820
1821static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
1822{
1823 struct mwl8k_cmd_set_pre_scan *cmd;
1824 int rc;
1825
1826 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1827 if (cmd == NULL)
1828 return -ENOMEM;
1829
1830 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
1831 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1832
1833 rc = mwl8k_post_cmd(hw, &cmd->header);
1834 kfree(cmd);
1835
1836 return rc;
1837}
1838
1839/*
1840 * CMD_SET_POST_SCAN.
1841 */
1842struct mwl8k_cmd_set_post_scan {
1843 struct mwl8k_cmd_pkt header;
1844 __le32 isibss;
d89173f2 1845 __u8 bssid[ETH_ALEN];
a66098da
LB		 1846} __attribute__((packed));
1847
1848static int
d89173f2 1849mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, __u8 mac[ETH_ALEN])
a66098da
LB		 1850{
1851 struct mwl8k_cmd_set_post_scan *cmd;
1852 int rc;
1853
1854 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1855 if (cmd == NULL)
1856 return -ENOMEM;
1857
1858 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
1859 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1860 cmd->isibss = 0;
d89173f2 1861 memcpy(cmd->bssid, mac, ETH_ALEN);
a66098da
LB		 1862
1863 rc = mwl8k_post_cmd(hw, &cmd->header);
1864 kfree(cmd);
1865
1866 return rc;
1867}
1868
1869/*
1870 * CMD_SET_RF_CHANNEL.
1871 */
1872struct mwl8k_cmd_set_rf_channel {
1873 struct mwl8k_cmd_pkt header;
1874 __le16 action;
1875 __u8 current_channel;
1876 __le32 channel_flags;
1877} __attribute__((packed));
1878
1879static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
1880 struct ieee80211_channel *channel)
1881{
1882 struct mwl8k_cmd_set_rf_channel *cmd;
1883 int rc;
1884
1885 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1886 if (cmd == NULL)
1887 return -ENOMEM;
1888
1889 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
1890 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1891 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1892 cmd->current_channel = channel->hw_value;
1893 if (channel->band == IEEE80211_BAND_2GHZ)
1894 cmd->channel_flags = cpu_to_le32(0x00000081);
1895 else
1896 cmd->channel_flags = cpu_to_le32(0x00000000);
1897
1898 rc = mwl8k_post_cmd(hw, &cmd->header);
1899 kfree(cmd);
1900
1901 return rc;
1902}
1903
1904/*
1905 * CMD_SET_SLOT.
1906 */
1907struct mwl8k_cmd_set_slot {
1908 struct mwl8k_cmd_pkt header;
1909 __le16 action;
1910 __u8 short_slot;
1911} __attribute__((packed));
1912
1913static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, int slot_time)
1914{
1915 struct mwl8k_cmd_set_slot *cmd;
1916 int rc;
1917
1918 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1919 if (cmd == NULL)
1920 return -ENOMEM;
1921
1922 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
1923 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1924 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1925 cmd->short_slot = slot_time == MWL8K_SHORT_SLOTTIME ? 1 : 0;
1926
1927 rc = mwl8k_post_cmd(hw, &cmd->header);
1928 kfree(cmd);
1929
1930 return rc;
1931}
1932
1933/*
1934 * CMD_MIMO_CONFIG.
1935 */
1936struct mwl8k_cmd_mimo_config {
1937 struct mwl8k_cmd_pkt header;
1938 __le32 action;
1939 __u8 rx_antenna_map;
1940 __u8 tx_antenna_map;
1941} __attribute__((packed));
1942
1943static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
1944{
1945 struct mwl8k_cmd_mimo_config *cmd;
1946 int rc;
1947
1948 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1949 if (cmd == NULL)
1950 return -ENOMEM;
1951
1952 cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
1953 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1954 cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
1955 cmd->rx_antenna_map = rx;
1956 cmd->tx_antenna_map = tx;
1957
1958 rc = mwl8k_post_cmd(hw, &cmd->header);
1959 kfree(cmd);
1960
1961 return rc;
1962}
1963
1964/*
1965 * CMD_ENABLE_SNIFFER.
1966 */
1967struct mwl8k_cmd_enable_sniffer {
1968 struct mwl8k_cmd_pkt header;
1969 __le32 action;
1970} __attribute__((packed));
1971
1972static int mwl8k_enable_sniffer(struct ieee80211_hw *hw, bool enable)
1973{
1974 struct mwl8k_cmd_enable_sniffer *cmd;
1975 int rc;
1976
1977 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1978 if (cmd == NULL)
1979 return -ENOMEM;
1980
1981 cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
1982 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1983 cmd->action = enable ? cpu_to_le32((u32)MWL8K_CMD_SET) : 0;
1984
1985 rc = mwl8k_post_cmd(hw, &cmd->header);
1986 kfree(cmd);
1987
1988 return rc;
1989}
1990
1991/*
1992 * CMD_SET_RATE_ADAPT_MODE.
1993 */
1994struct mwl8k_cmd_set_rate_adapt_mode {
1995 struct mwl8k_cmd_pkt header;
1996 __le16 action;
1997 __le16 mode;
1998} __attribute__((packed));
1999
2000static int mwl8k_cmd_setrateadaptmode(struct ieee80211_hw *hw, __u16 mode)
2001{
2002 struct mwl8k_cmd_set_rate_adapt_mode *cmd;
2003 int rc;
2004
2005 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2006 if (cmd == NULL)
2007 return -ENOMEM;
2008
2009 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
2010 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2011 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2012 cmd->mode = cpu_to_le16(mode);
2013
2014 rc = mwl8k_post_cmd(hw, &cmd->header);
2015 kfree(cmd);
2016
2017 return rc;
2018}
2019
2020/*
2021 * CMD_SET_WMM_MODE.
2022 */
2023struct mwl8k_cmd_set_wmm {
2024 struct mwl8k_cmd_pkt header;
2025 __le16 action;
2026} __attribute__((packed));
2027
2028static int mwl8k_set_wmm(struct ieee80211_hw *hw, bool enable)
2029{
2030 struct mwl8k_priv *priv = hw->priv;
2031 struct mwl8k_cmd_set_wmm *cmd;
2032 int rc;
2033
2034 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2035 if (cmd == NULL)
2036 return -ENOMEM;
2037
2038 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
2039 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2040 cmd->action = enable ? cpu_to_le16(MWL8K_CMD_SET) : 0;
2041
2042 rc = mwl8k_post_cmd(hw, &cmd->header);
2043 kfree(cmd);
2044
2045 if (!rc)
2046 priv->wmm_mode = enable;
2047
2048 return rc;
2049}
2050
2051/*
2052 * CMD_SET_RTS_THRESHOLD.
2053 */
2054struct mwl8k_cmd_rts_threshold {
2055 struct mwl8k_cmd_pkt header;
2056 __le16 action;
2057 __le16 threshold;
2058} __attribute__((packed));
2059
2060static int mwl8k_rts_threshold(struct ieee80211_hw *hw,
2061 u16 action, u16 *threshold)
2062{
2063 struct mwl8k_cmd_rts_threshold *cmd;
2064 int rc;
2065
2066 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2067 if (cmd == NULL)
2068 return -ENOMEM;
2069
2070 cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
2071 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2072 cmd->action = cpu_to_le16(action);
2073 cmd->threshold = cpu_to_le16(*threshold);
2074
2075 rc = mwl8k_post_cmd(hw, &cmd->header);
2076 kfree(cmd);
2077
2078 return rc;
2079}
2080
2081/*
2082 * CMD_SET_EDCA_PARAMS.
2083 */
2084struct mwl8k_cmd_set_edca_params {
2085 struct mwl8k_cmd_pkt header;
2086
2087 /* See MWL8K_SET_EDCA_XXX below */
2088 __le16 action;
2089
2090 /* TX opportunity in units of 32 us */
2091 __le16 txop;
2092
2093 /* Log exponent of max contention period: 0...15*/
2094 __u8 log_cw_max;
2095
2096 /* Log exponent of min contention period: 0...15 */
2097 __u8 log_cw_min;
2098
2099 /* Adaptive interframe spacing in units of 32us */
2100 __u8 aifs;
2101
2102 /* TX queue to configure */
2103 __u8 txq;
2104} __attribute__((packed));
2105
a66098da
LB		 2106#define MWL8K_SET_EDCA_CW 0x01
2107#define MWL8K_SET_EDCA_TXOP 0x02
2108#define MWL8K_SET_EDCA_AIFS 0x04
2109
2110#define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
2111 MWL8K_SET_EDCA_TXOP | \
2112 MWL8K_SET_EDCA_AIFS)
2113
2114static int
2115mwl8k_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
2116 __u16 cw_min, __u16 cw_max,
2117 __u8 aifs, __u16 txop)
2118{
2119 struct mwl8k_cmd_set_edca_params *cmd;
2120 u32 log_cw_min, log_cw_max;
2121 int rc;
2122
2123 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2124 if (cmd == NULL)
2125 return -ENOMEM;
2126
2127 log_cw_min = ilog2(cw_min+1);
2128 log_cw_max = ilog2(cw_max+1);
2129 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
2130 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2131
2132 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
2133 cmd->txop = cpu_to_le16(txop);
2134 cmd->log_cw_max = (u8)log_cw_max;
2135 cmd->log_cw_min = (u8)log_cw_min;
2136 cmd->aifs = aifs;
2137 cmd->txq = qnum;
2138
2139 rc = mwl8k_post_cmd(hw, &cmd->header);
2140 kfree(cmd);
2141
2142 return rc;
2143}
2144
2145/*
2146 * CMD_FINALIZE_JOIN.
2147 */
2148
2149/* FJ beacon buffer size is compiled into the firmware. */
2150#define MWL8K_FJ_BEACON_MAXLEN 128
2151
2152struct mwl8k_cmd_finalize_join {
2153 struct mwl8k_cmd_pkt header;
2154 __le32 sleep_interval; /* Number of beacon periods to sleep */
2155 __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
2156} __attribute__((packed));
2157
2158static int mwl8k_finalize_join(struct ieee80211_hw *hw, void *frame,
2159 __u16 framelen, __u16 dtim)
2160{
2161 struct mwl8k_cmd_finalize_join *cmd;
2162 struct ieee80211_mgmt *payload = frame;
2163 u16 hdrlen;
2164 u32 payload_len;
2165 int rc;
2166
2167 if (frame == NULL)
2168 return -EINVAL;
2169
2170 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2171 if (cmd == NULL)
2172 return -ENOMEM;
2173
2174 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
2175 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2176
2177 if (dtim)
2178 cmd->sleep_interval = cpu_to_le32(dtim);
2179 else
2180 cmd->sleep_interval = cpu_to_le32(1);
2181
2182 hdrlen = ieee80211_hdrlen(payload->frame_control);
2183
2184 payload_len = framelen > hdrlen ? framelen - hdrlen : 0;
2185
2186 /* XXX TBD Might just have to abort and return an error */
2187 if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2188 printk(KERN_ERR "%s(): WARNING: Incomplete beacon "
2189 "sent to firmware. Sz=%u MAX=%u\n", __func__,
2190 payload_len, MWL8K_FJ_BEACON_MAXLEN);
2191
2192 payload_len = payload_len > MWL8K_FJ_BEACON_MAXLEN ?
2193 MWL8K_FJ_BEACON_MAXLEN : payload_len;
2194
2195 if (payload && payload_len)
2196 memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
2197
2198 rc = mwl8k_post_cmd(hw, &cmd->header);
2199 kfree(cmd);
2200 return rc;
2201}
2202
2203/*
2204 * CMD_UPDATE_STADB.
2205 */
2206struct mwl8k_cmd_update_sta_db {
2207 struct mwl8k_cmd_pkt header;
2208
2209 /* See STADB_ACTION_TYPE */
2210 __le32 action;
2211
2212 /* Peer MAC address */
d89173f2 2213 __u8 peer_addr[ETH_ALEN];
a66098da
LB		 2214
2215 __le32 reserved;
2216
2217 /* Peer info - valid during add/update. */
2218 struct peer_capability_info peer_info;
2219} __attribute__((packed));
2220
2221static int mwl8k_cmd_update_sta_db(struct ieee80211_hw *hw,
2222 struct ieee80211_vif *vif, __u32 action)
2223{
2224 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2225 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2226 struct mwl8k_cmd_update_sta_db *cmd;
2227 struct peer_capability_info *peer_info;
2228 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
a66098da
LB		 2229 int rc;
2230 __u8 count, *rates;
2231
2232 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2233 if (cmd == NULL)
2234 return -ENOMEM;
2235
2236 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
2237 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2238
2239 cmd->action = cpu_to_le32(action);
2240 peer_info = &cmd->peer_info;
d89173f2 2241 memcpy(cmd->peer_addr, mv_vif->bssid, ETH_ALEN);
a66098da
LB		 2242
2243 switch (action) {
2244 case MWL8K_STA_DB_ADD_ENTRY:
2245 case MWL8K_STA_DB_MODIFY_ENTRY:
2246 /* Build peer_info block */
2247 peer_info->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
2248 peer_info->basic_caps = cpu_to_le16(info->assoc_capability);
2249 peer_info->interop = 1;
2250 peer_info->amsdu_enabled = 0;
2251
2252 rates = peer_info->legacy_rates;
2253 for (count = 0 ; count < mv_vif->legacy_nrates; count++)
2254 rates[count] = bitrates[count].hw_value;
2255
2256 rc = mwl8k_post_cmd(hw, &cmd->header);
2257 if (rc == 0)
2258 mv_vif->peer_id = peer_info->station_id;
2259
2260 break;
2261
2262 case MWL8K_STA_DB_DEL_ENTRY:
2263 case MWL8K_STA_DB_FLUSH:
2264 default:
2265 rc = mwl8k_post_cmd(hw, &cmd->header);
2266 if (rc == 0)
2267 mv_vif->peer_id = 0;
2268 break;
2269 }
2270 kfree(cmd);
2271
2272 return rc;
2273}
2274
2275/*
2276 * CMD_SET_AID.
2277 */
a66098da
LB		 2278#define MWL8K_RATE_INDEX_MAX_ARRAY 14
2279
2280#define MWL8K_FRAME_PROT_DISABLED 0x00
2281#define MWL8K_FRAME_PROT_11G 0x07
2282#define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
2283#define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
a66098da
LB		 2284
2285struct mwl8k_cmd_update_set_aid {
2286 struct mwl8k_cmd_pkt header;
2287 __le16 aid;
2288
2289 /* AP's MAC address (BSSID) */
d89173f2 2290 __u8 bssid[ETH_ALEN];
a66098da
LB		 2291 __le16 protection_mode;
2292 __u8 supp_rates[MWL8K_RATE_INDEX_MAX_ARRAY];
2293} __attribute__((packed));
2294
2295static int mwl8k_cmd_set_aid(struct ieee80211_hw *hw,
2296 struct ieee80211_vif *vif)
2297{
2298 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2299 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2300 struct mwl8k_cmd_update_set_aid *cmd;
2301 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
2302 int count;
2303 u16 prot_mode;
2304 int rc;
2305
2306 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2307 if (cmd == NULL)
2308 return -ENOMEM;
2309
2310 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
2311 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2312 cmd->aid = cpu_to_le16(info->aid);
2313
d89173f2 2314 memcpy(cmd->bssid, mv_vif->bssid, ETH_ALEN);
a66098da
LB		 2315
2316 prot_mode = MWL8K_FRAME_PROT_DISABLED;
2317
2318 if (info->use_cts_prot) {
2319 prot_mode = MWL8K_FRAME_PROT_11G;
2320 } else {
9ed6bcce 2321 switch (info->ht_operation_mode &
a66098da
LB		 2322 IEEE80211_HT_OP_MODE_PROTECTION) {
2323 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
2324 prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
2325 break;
2326 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
2327 prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
2328 break;
2329 default:
2330 prot_mode = MWL8K_FRAME_PROT_DISABLED;
2331 break;
2332 }
2333 }
2334
2335 cmd->protection_mode = cpu_to_le16(prot_mode);
2336
2337 for (count = 0; count < mv_vif->legacy_nrates; count++)
2338 cmd->supp_rates[count] = bitrates[count].hw_value;
2339
2340 rc = mwl8k_post_cmd(hw, &cmd->header);
2341 kfree(cmd);
2342
2343 return rc;
2344}
2345
2346/*
2347 * CMD_SET_RATE.
2348 */
2349struct mwl8k_cmd_update_rateset {
2350 struct mwl8k_cmd_pkt header;
2351 __u8 legacy_rates[MWL8K_RATE_INDEX_MAX_ARRAY];
2352
2353 /* Bitmap for supported MCS codes. */
2354 __u8 mcs_set[MWL8K_IEEE_LEGACY_DATA_RATES];
2355 __u8 reserved[MWL8K_IEEE_LEGACY_DATA_RATES];
2356} __attribute__((packed));
2357
2358static int mwl8k_update_rateset(struct ieee80211_hw *hw,
2359 struct ieee80211_vif *vif)
2360{
2361 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2362 struct mwl8k_cmd_update_rateset *cmd;
2363 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
2364 int count;
2365 int rc;
2366
2367 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2368 if (cmd == NULL)
2369 return -ENOMEM;
2370
2371 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
2372 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2373
2374 for (count = 0; count < mv_vif->legacy_nrates; count++)
2375 cmd->legacy_rates[count] = bitrates[count].hw_value;
2376
2377 rc = mwl8k_post_cmd(hw, &cmd->header);
2378 kfree(cmd);
2379
2380 return rc;
2381}
2382
2383/*
2384 * CMD_USE_FIXED_RATE.
2385 */
2386#define MWL8K_RATE_TABLE_SIZE 8
2387#define MWL8K_UCAST_RATE 0
a66098da
LB		 2388#define MWL8K_USE_AUTO_RATE 0x0002
2389
2390struct mwl8k_rate_entry {
2391 /* Set to 1 if HT rate, 0 if legacy. */
2392 __le32 is_ht_rate;
2393
2394 /* Set to 1 to use retry_count field. */
2395 __le32 enable_retry;
2396
2397 /* Specified legacy rate or MCS. */
2398 __le32 rate;
2399
2400 /* Number of allowed retries. */
2401 __le32 retry_count;
2402} __attribute__((packed));
2403
2404struct mwl8k_rate_table {
2405 /* 1 to allow specified rate and below */
2406 __le32 allow_rate_drop;
2407 __le32 num_rates;
2408 struct mwl8k_rate_entry rate_entry[MWL8K_RATE_TABLE_SIZE];
2409} __attribute__((packed));
2410
2411struct mwl8k_cmd_use_fixed_rate {
2412 struct mwl8k_cmd_pkt header;
2413 __le32 action;
2414 struct mwl8k_rate_table rate_table;
2415
2416 /* Unicast, Broadcast or Multicast */
2417 __le32 rate_type;
2418 __le32 reserved1;
2419 __le32 reserved2;
2420} __attribute__((packed));
2421
2422static int mwl8k_cmd_use_fixed_rate(struct ieee80211_hw *hw,
2423 u32 action, u32 rate_type, struct mwl8k_rate_table *rate_table)
2424{
2425 struct mwl8k_cmd_use_fixed_rate *cmd;
2426 int count;
2427 int rc;
2428
2429 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2430 if (cmd == NULL)
2431 return -ENOMEM;
2432
2433 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
2434 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2435
2436 cmd->action = cpu_to_le32(action);
2437 cmd->rate_type = cpu_to_le32(rate_type);
2438
2439 if (rate_table != NULL) {
2440 /* Copy over each field manually so
2441 * that bitflipping can be done
2442 */
2443 cmd->rate_table.allow_rate_drop =
2444 cpu_to_le32(rate_table->allow_rate_drop);
2445 cmd->rate_table.num_rates =
2446 cpu_to_le32(rate_table->num_rates);
2447
2448 for (count = 0; count < rate_table->num_rates; count++) {
2449 struct mwl8k_rate_entry *dst =
2450 &cmd->rate_table.rate_entry[count];
2451 struct mwl8k_rate_entry *src =
2452 &rate_table->rate_entry[count];
2453
2454 dst->is_ht_rate = cpu_to_le32(src->is_ht_rate);
2455 dst->enable_retry = cpu_to_le32(src->enable_retry);
2456 dst->rate = cpu_to_le32(src->rate);
2457 dst->retry_count = cpu_to_le32(src->retry_count);
2458 }
2459 }
2460
2461 rc = mwl8k_post_cmd(hw, &cmd->header);
2462 kfree(cmd);
2463
2464 return rc;
2465}
2466
2467
2468/*
2469 * Interrupt handling.
2470 */
2471static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
2472{
2473 struct ieee80211_hw *hw = dev_id;
2474 struct mwl8k_priv *priv = hw->priv;
2475 u32 status;
2476
2477 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2478 iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2479
a66098da
LB		 2480 if (!status)
2481 return IRQ_NONE;
2482
2483 if (status & MWL8K_A2H_INT_TX_DONE)
2484 tasklet_schedule(&priv->tx_reclaim_task);
2485
2486 if (status & MWL8K_A2H_INT_RX_READY) {
2487 while (rxq_process(hw, 0, 1))
2488 rxq_refill(hw, 0, 1);
2489 }
2490
2491 if (status & MWL8K_A2H_INT_OPC_DONE) {
2492 if (priv->hostcmd_wait != NULL) {
2493 complete(priv->hostcmd_wait);
2494 priv->hostcmd_wait = NULL;
2495 }
2496 }
2497
2498 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
2499 if (!priv->inconfig &&
2500 priv->radio_state &&
2501 mwl8k_txq_busy(priv))
2502 mwl8k_tx_start(priv);
2503 }
2504
2505 return IRQ_HANDLED;
2506}
2507
2508
2509/*
2510 * Core driver operations.
2511 */
2512static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2513{
2514 struct mwl8k_priv *priv = hw->priv;
2515 int index = skb_get_queue_mapping(skb);
2516 int rc;
2517
2518 if (priv->current_channel == NULL) {
2519 printk(KERN_DEBUG "%s: dropped TX frame since radio "
2520 "disabled\n", priv->name);
2521 dev_kfree_skb(skb);
2522 return NETDEV_TX_OK;
2523 }
2524
2525 rc = mwl8k_txq_xmit(hw, index, skb);
2526
2527 return rc;
2528}
2529
2530struct mwl8k_work_struct {
2531 /* Initialized by mwl8k_queue_work(). */
2532 struct work_struct wt;
2533
2534 /* Required field passed in to mwl8k_queue_work(). */
2535 struct ieee80211_hw *hw;
2536
2537 /* Required field passed in to mwl8k_queue_work(). */
2538 int (*wfunc)(struct work_struct *w);
2539
2540 /* Initialized by mwl8k_queue_work(). */
2541 struct completion *cmd_wait;
2542
2543 /* Result code. */
2544 int rc;
2545
2546 /*
2547 * Optional field. Refer to explanation of MWL8K_WQ_XXX_XXX
2548 * flags for explanation. Defaults to MWL8K_WQ_DEFAULT_OPTIONS.
2549 */
2550 u32 options;
2551
2552 /* Optional field. Defaults to MWL8K_CONFIG_TIMEOUT_MS. */
2553 unsigned long timeout_ms;
2554
2555 /* Optional field. Defaults to MWL8K_WQ_TXWAIT_ATTEMPTS. */
2556 u32 txwait_attempts;
2557
2558 /* Optional field. Defaults to MWL8K_TXWAIT_MS. */
2559 u32 tx_timeout_ms;
2560 u32 step;
2561};
2562
2563/* Flags controlling behavior of config queue requests */
2564
2565/* Caller spins while waiting for completion. */
2566#define MWL8K_WQ_SPIN 0x00000001
2567
2568/* Wait for TX queues to empty before proceeding with configuration. */
2569#define MWL8K_WQ_TX_WAIT_EMPTY 0x00000002
2570
2571/* Queue request and return immediately. */
2572#define MWL8K_WQ_POST_REQUEST 0x00000004
2573
2574/*
2575 * Caller sleeps and waits for task complete notification.
2576 * Do not use in atomic context.
2577 */
2578#define MWL8K_WQ_SLEEP 0x00000008
2579
2580/* Free work struct when task is done. */
2581#define MWL8K_WQ_FREE_WORKSTRUCT 0x00000010
2582
2583/*
2584 * Config request is queued and returns to caller imediately. Use
2585 * this in atomic context. Work struct is freed by mwl8k_queue_work()
2586 * when this flag is set.
2587 */
2588#define MWL8K_WQ_QUEUE_ONLY (MWL8K_WQ_POST_REQUEST | \
2589 MWL8K_WQ_FREE_WORKSTRUCT)
2590
2591/* Default work queue behavior is to sleep and wait for tx completion. */
2592#define MWL8K_WQ_DEFAULT_OPTIONS (MWL8K_WQ_SLEEP | MWL8K_WQ_TX_WAIT_EMPTY)
2593
2594/*
2595 * Default config request timeout. Add adjustments to make sure the
2596 * config thread waits long enough for both tx wait and cmd wait before
2597 * timing out.
2598 */
2599
2600/* Time to wait for all TXQs to drain. TX Doorbell is pressed each time. */
2601#define MWL8K_TXWAIT_TIMEOUT_MS 1000
2602
2603/* Default number of TX wait attempts. */
2604#define MWL8K_WQ_TXWAIT_ATTEMPTS 4
2605
2606/* Total time to wait for TXQ to drain. */
2607#define MWL8K_TXWAIT_MS (MWL8K_TXWAIT_TIMEOUT_MS * \
2608 MWL8K_WQ_TXWAIT_ATTEMPTS)
2609
2610/* Scheduling slop. */
2611#define MWL8K_OS_SCHEDULE_OVERHEAD_MS 200
2612
2613#define MWL8K_CONFIG_TIMEOUT_MS (MWL8K_CMD_TIMEOUT_MS + \
2614 MWL8K_TXWAIT_MS + \
2615 MWL8K_OS_SCHEDULE_OVERHEAD_MS)
2616
2617static void mwl8k_config_thread(struct work_struct *wt)
2618{
2619 struct mwl8k_work_struct *worker = (struct mwl8k_work_struct *)wt;
2620 struct ieee80211_hw *hw = worker->hw;
2621 struct mwl8k_priv *priv = hw->priv;
2622 int rc = 0;
2623
2624 spin_lock_irq(&priv->tx_lock);
2625 priv->inconfig = true;
2626 spin_unlock_irq(&priv->tx_lock);
2627
2628 ieee80211_stop_queues(hw);
2629
2630 /*
2631 * Wait for host queues to drain before doing PHY
2632 * reconfiguration. This avoids interrupting any in-flight
2633 * DMA transfers to the hardware.
2634 */
2635 if (worker->options & MWL8K_WQ_TX_WAIT_EMPTY) {
2636 u32 timeout;
2637 u32 time_remaining;
2638 u32 iter;
2639 u32 tx_wait_attempts = worker->txwait_attempts;
2640
2641 time_remaining = worker->tx_timeout_ms;
2642 if (!tx_wait_attempts)
2643 tx_wait_attempts = 1;
2644
2645 timeout = worker->tx_timeout_ms/tx_wait_attempts;
2646 if (!timeout)
2647 timeout = 1;
2648
2649 iter = tx_wait_attempts;
2650 do {
2651 int wait_time;
2652
2653 if (time_remaining > timeout) {
2654 time_remaining -= timeout;
2655 wait_time = timeout;
2656 } else
2657 wait_time = time_remaining;
2658
2659 if (!wait_time)
2660 wait_time = 1;
2661
2662 rc = mwl8k_tx_wait_empty(hw, wait_time);
2663 if (rc)
2664 printk(KERN_ERR "%s() txwait timeout=%ums "
2665 "Retry:%u/%u\n", __func__, timeout,
2666 tx_wait_attempts - iter + 1,
2667 tx_wait_attempts);
2668
2669 } while (rc && --iter);
2670
2671 rc = iter ? 0 : -ETIMEDOUT;
2672 }
2673 if (!rc)
2674 rc = worker->wfunc(wt);
2675
2676 spin_lock_irq(&priv->tx_lock);
2677 priv->inconfig = false;
2678 if (priv->pending_tx_pkts && priv->radio_state)
2679 mwl8k_tx_start(priv);
2680 spin_unlock_irq(&priv->tx_lock);
2681 ieee80211_wake_queues(hw);
2682
2683 worker->rc = rc;
2684 if (worker->options & MWL8K_WQ_SLEEP)
2685 complete(worker->cmd_wait);
2686
2687 if (worker->options & MWL8K_WQ_FREE_WORKSTRUCT)
2688 kfree(wt);
2689}
2690
2691static int mwl8k_queue_work(struct ieee80211_hw *hw,
2692 struct mwl8k_work_struct *worker,
2693 struct workqueue_struct *wqueue,
2694 int (*wfunc)(struct work_struct *w))
2695{
2696 unsigned long timeout = 0;
2697 int rc = 0;
2698
2699 DECLARE_COMPLETION_ONSTACK(cmd_wait);
2700
2701 if (!worker->timeout_ms)
2702 worker->timeout_ms = MWL8K_CONFIG_TIMEOUT_MS;
2703
2704 if (!worker->options)
2705 worker->options = MWL8K_WQ_DEFAULT_OPTIONS;
2706
2707 if (!worker->txwait_attempts)
2708 worker->txwait_attempts = MWL8K_WQ_TXWAIT_ATTEMPTS;
2709
2710 if (!worker->tx_timeout_ms)
2711 worker->tx_timeout_ms = MWL8K_TXWAIT_MS;
2712
2713 worker->hw = hw;
2714 worker->cmd_wait = &cmd_wait;
2715 worker->rc = 1;
2716 worker->wfunc = wfunc;
2717
2718 INIT_WORK(&worker->wt, mwl8k_config_thread);
2719 queue_work(wqueue, &worker->wt);
2720
2721 if (worker->options & MWL8K_WQ_POST_REQUEST) {
2722 rc = 0;
2723 } else {
2724 if (worker->options & MWL8K_WQ_SPIN) {
2725 timeout = worker->timeout_ms;
2726 while (timeout && (worker->rc > 0)) {
2727 mdelay(1);
2728 timeout--;
2729 }
2730 } else if (worker->options & MWL8K_WQ_SLEEP)
2731 timeout = wait_for_completion_timeout(&cmd_wait,
2732 msecs_to_jiffies(worker->timeout_ms));
2733
2734 if (timeout)
2735 rc = worker->rc;
2736 else {
2737 cancel_work_sync(&worker->wt);
2738 rc = -ETIMEDOUT;
2739 }
2740 }
2741
2742 return rc;
2743}
2744
2745struct mwl8k_start_worker {
2746 struct mwl8k_work_struct header;
2747};
2748
2749static int mwl8k_start_wt(struct work_struct *wt)
2750{
2751 struct mwl8k_start_worker *worker = (struct mwl8k_start_worker *)wt;
2752 struct ieee80211_hw *hw = worker->header.hw;
2753 struct mwl8k_priv *priv = hw->priv;
2754 int rc = 0;
2755
2756 if (priv->vif != NULL) {
2757 rc = -EIO;
2758 goto mwl8k_start_exit;
2759 }
2760
2761 /* Turn on radio */
2762 if (mwl8k_cmd_802_11_radio_control(hw, MWL8K_RADIO_ENABLE)) {
2763 rc = -EIO;
2764 goto mwl8k_start_exit;
2765 }
2766
2767 /* Purge TX/RX HW queues */
2768 if (mwl8k_cmd_set_pre_scan(hw)) {
2769 rc = -EIO;
2770 goto mwl8k_start_exit;
2771 }
2772
2773 if (mwl8k_cmd_set_post_scan(hw, "\x00\x00\x00\x00\x00\x00")) {
2774 rc = -EIO;
2775 goto mwl8k_start_exit;
2776 }
2777
2778 /* Enable firmware rate adaptation */
2779 if (mwl8k_cmd_setrateadaptmode(hw, 0)) {
2780 rc = -EIO;
2781 goto mwl8k_start_exit;
2782 }
2783
2784 /* Disable WMM. WMM gets enabled when stack sends WMM parms */
2785 if (mwl8k_set_wmm(hw, MWL8K_WMM_DISABLE)) {
2786 rc = -EIO;
2787 goto mwl8k_start_exit;
2788 }
2789
2790 /* Disable sniffer mode */
2791 if (mwl8k_enable_sniffer(hw, 0))
2792 rc = -EIO;
2793
2794mwl8k_start_exit:
2795 return rc;
2796}
2797
2798static int mwl8k_start(struct ieee80211_hw *hw)
2799{
2800 struct mwl8k_start_worker *worker;
2801 struct mwl8k_priv *priv = hw->priv;
2802 int rc;
2803
2804 /* Enable tx reclaim tasklet */
2805 tasklet_enable(&priv->tx_reclaim_task);
2806
2807 rc = request_irq(priv->pdev->irq, &mwl8k_interrupt,
2808 IRQF_SHARED, MWL8K_NAME, hw);
2809 if (rc) {
2810 printk(KERN_ERR "%s: failed to register IRQ handler\n",
2811 priv->name);
2812 rc = -EIO;
2813 goto mwl8k_start_disable_tasklet;
2814 }
2815
2816 /* Enable interrupts */
c23b5a69 2817 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 2818
2819 worker = kzalloc(sizeof(*worker), GFP_KERNEL);
2820 if (worker == NULL) {
2821 rc = -ENOMEM;
2822 goto mwl8k_start_disable_irq;
2823 }
2824
2825 rc = mwl8k_queue_work(hw, &worker->header,
2826 priv->config_wq, mwl8k_start_wt);
2827 kfree(worker);
2828 if (!rc)
2829 return rc;
2830
2831 if (rc == -ETIMEDOUT)
2832 printk(KERN_ERR "%s() timed out\n", __func__);
2833
2834 rc = -EIO;
2835
2836mwl8k_start_disable_irq:
2837 spin_lock_irq(&priv->tx_lock);
2838 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2839 spin_unlock_irq(&priv->tx_lock);
2840 free_irq(priv->pdev->irq, hw);
2841
2842mwl8k_start_disable_tasklet:
2843 tasklet_disable(&priv->tx_reclaim_task);
2844
2845 return rc;
2846}
2847
2848struct mwl8k_stop_worker {
2849 struct mwl8k_work_struct header;
2850};
2851
2852static int mwl8k_stop_wt(struct work_struct *wt)
2853{
2854 struct mwl8k_stop_worker *worker = (struct mwl8k_stop_worker *)wt;
2855 struct ieee80211_hw *hw = worker->header.hw;
2856 int rc;
2857
2858 rc = mwl8k_cmd_802_11_radio_control(hw, MWL8K_RADIO_DISABLE);
2859
2860 return rc;
2861}
2862
2863static void mwl8k_stop(struct ieee80211_hw *hw)
2864{
2865 int rc;
2866 struct mwl8k_stop_worker *worker;
2867 struct mwl8k_priv *priv = hw->priv;
2868 int i;
2869
2870 if (priv->vif != NULL)
2871 return;
2872
2873 ieee80211_stop_queues(hw);
2874
2875 worker = kzalloc(sizeof(*worker), GFP_KERNEL);
2876 if (worker == NULL)
2877 return;
2878
2879 rc = mwl8k_queue_work(hw, &worker->header,
2880 priv->config_wq, mwl8k_stop_wt);
2881 kfree(worker);
2882 if (rc == -ETIMEDOUT)
2883 printk(KERN_ERR "%s() timed out\n", __func__);
2884
2885 /* Disable interrupts */
2886 spin_lock_irq(&priv->tx_lock);
2887 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2888 spin_unlock_irq(&priv->tx_lock);
2889 free_irq(priv->pdev->irq, hw);
2890
2891 /* Stop finalize join worker */
2892 cancel_work_sync(&priv->finalize_join_worker);
2893 if (priv->beacon_skb != NULL)
2894 dev_kfree_skb(priv->beacon_skb);
2895
2896 /* Stop tx reclaim tasklet */
2897 tasklet_disable(&priv->tx_reclaim_task);
2898
2899 /* Stop config thread */
2900 flush_workqueue(priv->config_wq);
2901
2902 /* Return all skbs to mac80211 */
2903 for (i = 0; i < MWL8K_TX_QUEUES; i++)
2904 mwl8k_txq_reclaim(hw, i, 1);
2905}
2906
2907static int mwl8k_add_interface(struct ieee80211_hw *hw,
2908 struct ieee80211_if_init_conf *conf)
2909{
2910 struct mwl8k_priv *priv = hw->priv;
2911 struct mwl8k_vif *mwl8k_vif;
2912
2913 /*
2914 * We only support one active interface at a time.
2915 */
2916 if (priv->vif != NULL)
2917 return -EBUSY;
2918
2919 /*
2920 * We only support managed interfaces for now.
2921 */
2922 if (conf->type != NL80211_IFTYPE_STATION &&
2923 conf->type != NL80211_IFTYPE_MONITOR)
2924 return -EINVAL;
2925
2926 /* Clean out driver private area */
2927 mwl8k_vif = MWL8K_VIF(conf->vif);
2928 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
2929
2930 /* Save the mac address */
d89173f2 2931 memcpy(mwl8k_vif->mac_addr, conf->mac_addr, ETH_ALEN);
a66098da
LB		 2932
2933 /* Back pointer to parent config block */
2934 mwl8k_vif->priv = priv;
2935
2936 /* Setup initial PHY parameters */
2937 memcpy(mwl8k_vif->legacy_rates ,
2938 priv->rates, sizeof(mwl8k_vif->legacy_rates));
2939 mwl8k_vif->legacy_nrates = ARRAY_SIZE(priv->rates);
2940
2941 /* Set Initial sequence number to zero */
2942 mwl8k_vif->seqno = 0;
2943
2944 priv->vif = conf->vif;
2945 priv->current_channel = NULL;
2946
2947 return 0;
2948}
2949
2950static void mwl8k_remove_interface(struct ieee80211_hw *hw,
2951 struct ieee80211_if_init_conf *conf)
2952{
2953 struct mwl8k_priv *priv = hw->priv;
2954
2955 if (priv->vif == NULL)
2956 return;
2957
2958 priv->vif = NULL;
2959}
2960
2961struct mwl8k_config_worker {
2962 struct mwl8k_work_struct header;
2963 u32 changed;
2964};
2965
2966static int mwl8k_config_wt(struct work_struct *wt)
2967{
2968 struct mwl8k_config_worker *worker =
2969 (struct mwl8k_config_worker *)wt;
2970 struct ieee80211_hw *hw = worker->header.hw;
2971 struct ieee80211_conf *conf = &hw->conf;
2972 struct mwl8k_priv *priv = hw->priv;
2973 int rc = 0;
2974
a66098da
LB		 2975 if (mwl8k_cmd_802_11_radio_control(hw, MWL8K_RADIO_ENABLE)) {
2976 rc = -EINVAL;
2977 goto mwl8k_config_exit;
2978 }
2979
2980 priv->current_channel = conf->channel;
2981
2982 if (mwl8k_cmd_set_rf_channel(hw, conf->channel)) {
2983 rc = -EINVAL;
2984 goto mwl8k_config_exit;
2985 }
2986
2987 if (conf->power_level > 18)
2988 conf->power_level = 18;
2989 if (mwl8k_cmd_802_11_rf_tx_power(hw, conf->power_level)) {
2990 rc = -EINVAL;
2991 goto mwl8k_config_exit;
2992 }
2993
2994 if (mwl8k_cmd_mimo_config(hw, 0x7, 0x7))
2995 rc = -EINVAL;
2996
2997mwl8k_config_exit:
2998 return rc;
2999}
3000
3001static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
3002{
3003 int rc = 0;
3004 struct mwl8k_config_worker *worker;
3005 struct mwl8k_priv *priv = hw->priv;
3006
3007 worker = kzalloc(sizeof(*worker), GFP_KERNEL);
3008 if (worker == NULL)
3009 return -ENOMEM;
3010
3011 worker->changed = changed;
3012 rc = mwl8k_queue_work(hw, &worker->header,
3013 priv->config_wq, mwl8k_config_wt);
3014 if (rc == -ETIMEDOUT) {
3015 printk(KERN_ERR "%s() timed out.\n", __func__);
3016 rc = -EINVAL;
3017 }
3018
3019 kfree(worker);
3020
3021 /*
3022 * mac80211 will crash on anything other than -EINVAL on
3023 * error. Looks like wireless extensions which calls mac80211
3024 * may be the actual culprit...
3025 */
3026 return rc ? -EINVAL : 0;
3027}
3028
a66098da
LB		 3029struct mwl8k_bss_info_changed_worker {
3030 struct mwl8k_work_struct header;
3031 struct ieee80211_vif *vif;
3032 struct ieee80211_bss_conf *info;
3033 u32 changed;
3034};
3035
3036static int mwl8k_bss_info_changed_wt(struct work_struct *wt)
3037{
3038 struct mwl8k_bss_info_changed_worker *worker =
3039 (struct mwl8k_bss_info_changed_worker *)wt;
3040 struct ieee80211_hw *hw = worker->header.hw;
3041 struct ieee80211_vif *vif = worker->vif;
3042 struct ieee80211_bss_conf *info = worker->info;
3043 u32 changed;
3044 int rc;
3045
3046 struct mwl8k_priv *priv = hw->priv;
3047 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
3048
3049 changed = worker->changed;
3050 priv->capture_beacon = false;
3051
3052 if (info->assoc) {
3053 memcpy(&mwl8k_vif->bss_info, info,
3054 sizeof(struct ieee80211_bss_conf));
3055
3056 /* Install rates */
3057 if (mwl8k_update_rateset(hw, vif))
3058 goto mwl8k_bss_info_changed_exit;
3059
3060 /* Turn on rate adaptation */
3061 if (mwl8k_cmd_use_fixed_rate(hw, MWL8K_USE_AUTO_RATE,
3062 MWL8K_UCAST_RATE, NULL))
3063 goto mwl8k_bss_info_changed_exit;
3064
3065 /* Set radio preamble */
3066 if (mwl8k_set_radio_preamble(hw,
3067 info->use_short_preamble))
3068 goto mwl8k_bss_info_changed_exit;
3069
3070 /* Set slot time */
3071 if (mwl8k_cmd_set_slot(hw, info->use_short_slot ?
3072 MWL8K_SHORT_SLOTTIME : MWL8K_LONG_SLOTTIME))
3073 goto mwl8k_bss_info_changed_exit;
3074
3075 /* Update peer rate info */
3076 if (mwl8k_cmd_update_sta_db(hw, vif,
3077 MWL8K_STA_DB_MODIFY_ENTRY))
3078 goto mwl8k_bss_info_changed_exit;
3079
3080 /* Set AID */
3081 if (mwl8k_cmd_set_aid(hw, vif))
3082 goto mwl8k_bss_info_changed_exit;
3083
3084 /*
3085 * Finalize the join. Tell rx handler to process
3086 * next beacon from our BSSID.
3087 */
d89173f2 3088 memcpy(priv->capture_bssid, mwl8k_vif->bssid, ETH_ALEN);
a66098da
LB		 3089 priv->capture_beacon = true;
3090 } else {
3091 mwl8k_cmd_update_sta_db(hw, vif, MWL8K_STA_DB_DEL_ENTRY);
3092 memset(&mwl8k_vif->bss_info, 0,
3093 sizeof(struct ieee80211_bss_conf));
d89173f2 3094 memset(mwl8k_vif->bssid, 0, ETH_ALEN);
a66098da
LB		 3095 }
3096
3097mwl8k_bss_info_changed_exit:
3098 rc = 0;
3099 return rc;
3100}
3101
3102static void mwl8k_bss_info_changed(struct ieee80211_hw *hw,
3103 struct ieee80211_vif *vif,
3104 struct ieee80211_bss_conf *info,
3105 u32 changed)
3106{
3107 struct mwl8k_bss_info_changed_worker *worker;
3108 struct mwl8k_priv *priv = hw->priv;
2d0ddec5 3109 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
a66098da
LB		 3110 int rc;
3111
2d0ddec5 3112 if (changed & BSS_CHANGED_BSSID)
d89173f2 3113 memcpy(mv_vif->bssid, info->bssid, ETH_ALEN);
2d0ddec5 3114
a66098da
LB		 3115 if ((changed & BSS_CHANGED_ASSOC) == 0)
3116 return;
3117
3118 worker = kzalloc(sizeof(*worker), GFP_KERNEL);
3119 if (worker == NULL)
3120 return;
3121
3122 worker->vif = vif;
3123 worker->info = info;
3124 worker->changed = changed;
3125 rc = mwl8k_queue_work(hw, &worker->header,
3126 priv->config_wq,
3127 mwl8k_bss_info_changed_wt);
3128 kfree(worker);
3129 if (rc == -ETIMEDOUT)
3130 printk(KERN_ERR "%s() timed out\n", __func__);
3131}
3132
3133struct mwl8k_configure_filter_worker {
3134 struct mwl8k_work_struct header;
3135 unsigned int changed_flags;
3136 unsigned int *total_flags;
3137 int mc_count;
3138 struct dev_addr_list *mclist;
3139};
3140
3141#define MWL8K_SUPPORTED_IF_FLAGS FIF_BCN_PRBRESP_PROMISC
3142
3143static int mwl8k_configure_filter_wt(struct work_struct *wt)
3144{
3145 struct mwl8k_configure_filter_worker *worker =
3146 (struct mwl8k_configure_filter_worker *)wt;
3147
3148 struct ieee80211_hw *hw = worker->header.hw;
3149 unsigned int changed_flags = worker->changed_flags;
3150 unsigned int *total_flags = worker->total_flags;
3151 int mc_count = worker->mc_count;
3152 struct dev_addr_list *mclist = worker->mclist;
3153
3154 struct mwl8k_priv *priv = hw->priv;
a66098da
LB		 3155 int rc = 0;
3156
3157 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
3158 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
3159 rc = mwl8k_cmd_set_pre_scan(hw);
3160 else {
a94cc97e
LB		 3161 u8 *bssid;
3162
3163 bssid = "\x00\x00\x00\x00\x00\x00";
3164 if (priv->vif != NULL)
3165 bssid = MWL8K_VIF(priv->vif)->bssid;
3166
3167 rc = mwl8k_cmd_set_post_scan(hw, bssid);
a66098da
LB		 3168 }
3169 }
3170
3171 if (rc)
3172 goto mwl8k_configure_filter_exit;
3173 if (mc_count) {
3174 mc_count = mc_count < priv->num_mcaddrs ?
3175 mc_count : priv->num_mcaddrs;
3176 rc = mwl8k_cmd_mac_multicast_adr(hw, mc_count, mclist);
3177 if (rc)
3178 printk(KERN_ERR
3179 "%s()Error setting multicast addresses\n",
3180 __func__);
3181 }
3182
3183mwl8k_configure_filter_exit:
3184 return rc;
3185}
3186
3ac64bee
JB		 3187static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
3188 int mc_count, struct dev_addr_list *mclist)
3189{
3190 struct mwl8k_configure_filter_worker *worker;
3191
3192 worker = kzalloc(sizeof(*worker), GFP_ATOMIC);
3193
3194 if (!worker)
3195 return 0;
3196
3197 /*
3198 * XXX: This is _HORRIBLY_ broken!!
3199 *
3200 * No locking, the mclist pointer might be invalid as soon as this
3201 * function returns, something in the list might be invalidated
3202 * once we get to the worker, etc...
3203 */
3204 worker->mc_count = mc_count;
3205 worker->mclist = mclist;
3206
3207 return (u64)worker;
3208}
3209
a66098da
LB		 3210static void mwl8k_configure_filter(struct ieee80211_hw *hw,
3211 unsigned int changed_flags,
3212 unsigned int *total_flags,
3ac64bee 3213 u64 multicast)
a66098da
LB		 3214{
3215
3ac64bee 3216 struct mwl8k_configure_filter_worker *worker = (void *)multicast;
a66098da
LB		 3217 struct mwl8k_priv *priv = hw->priv;
3218
3219 /* Clear unsupported feature flags */
3220 *total_flags &= MWL8K_SUPPORTED_IF_FLAGS;
3221
3ac64bee 3222 if (!(changed_flags & MWL8K_SUPPORTED_IF_FLAGS))
a66098da
LB		 3223 return;
3224
a66098da
LB		 3225 if (worker == NULL)
3226 return;
3227
3228 worker->header.options = MWL8K_WQ_QUEUE_ONLY | MWL8K_WQ_TX_WAIT_EMPTY;
3229 worker->changed_flags = changed_flags;
3230 worker->total_flags = total_flags;
a66098da
LB		 3231
3232 mwl8k_queue_work(hw, &worker->header, priv->config_wq,
3233 mwl8k_configure_filter_wt);
3234}
3235
3236struct mwl8k_set_rts_threshold_worker {
3237 struct mwl8k_work_struct header;
3238 u32 value;
3239};
3240
3241static int mwl8k_set_rts_threshold_wt(struct work_struct *wt)
3242{
3243 struct mwl8k_set_rts_threshold_worker *worker =
3244 (struct mwl8k_set_rts_threshold_worker *)wt;
3245
3246 struct ieee80211_hw *hw = worker->header.hw;
3247 u16 threshold = (u16)(worker->value);
3248 int rc;
3249
3250 rc = mwl8k_rts_threshold(hw, MWL8K_CMD_SET, &threshold);
3251
3252 return rc;
3253}
3254
3255static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
3256{
3257 int rc;
3258 struct mwl8k_set_rts_threshold_worker *worker;
3259 struct mwl8k_priv *priv = hw->priv;
3260
3261 worker = kzalloc(sizeof(*worker), GFP_KERNEL);
3262 if (worker == NULL)
3263 return -ENOMEM;
3264
3265 worker->value = value;
3266
3267 rc = mwl8k_queue_work(hw, &worker->header,
3268 priv->config_wq,
3269 mwl8k_set_rts_threshold_wt);
3270 kfree(worker);
3271
3272 if (rc == -ETIMEDOUT) {
3273 printk(KERN_ERR "%s() timed out\n", __func__);
3274 rc = -EINVAL;
3275 }
3276
3277 return rc;
3278}
3279
3280struct mwl8k_conf_tx_worker {
3281 struct mwl8k_work_struct header;
3282 u16 queue;
3283 const struct ieee80211_tx_queue_params *params;
3284};
3285
3286static int mwl8k_conf_tx_wt(struct work_struct *wt)
3287{
3288 struct mwl8k_conf_tx_worker *worker =
3289 (struct mwl8k_conf_tx_worker *)wt;
3290
3291 struct ieee80211_hw *hw = worker->header.hw;
3292 u16 queue = worker->queue;
3293 const struct ieee80211_tx_queue_params *params = worker->params;
3294
3295 struct mwl8k_priv *priv = hw->priv;
3296 int rc = 0;
3297
3298 if (priv->wmm_mode == MWL8K_WMM_DISABLE)
3299 if (mwl8k_set_wmm(hw, MWL8K_WMM_ENABLE)) {
3300 rc = -EINVAL;
3301 goto mwl8k_conf_tx_exit;
3302 }
3303
3304 if (mwl8k_set_edca_params(hw, GET_TXQ(queue), params->cw_min,
3305 params->cw_max, params->aifs, params->txop))
3306 rc = -EINVAL;
3307mwl8k_conf_tx_exit:
3308 return rc;
3309}
3310
3311static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue,
3312 const struct ieee80211_tx_queue_params *params)
3313{
3314 int rc;
3315 struct mwl8k_conf_tx_worker *worker;
3316 struct mwl8k_priv *priv = hw->priv;
3317
3318 worker = kzalloc(sizeof(*worker), GFP_KERNEL);
3319 if (worker == NULL)
3320 return -ENOMEM;
3321
3322 worker->queue = queue;
3323 worker->params = params;
3324 rc = mwl8k_queue_work(hw, &worker->header,
3325 priv->config_wq, mwl8k_conf_tx_wt);
3326 kfree(worker);
3327 if (rc == -ETIMEDOUT) {
3328 printk(KERN_ERR "%s() timed out\n", __func__);
3329 rc = -EINVAL;
3330 }
3331 return rc;
3332}
3333
3334static int mwl8k_get_tx_stats(struct ieee80211_hw *hw,
3335 struct ieee80211_tx_queue_stats *stats)
3336{
3337 struct mwl8k_priv *priv = hw->priv;
3338 struct mwl8k_tx_queue *txq;
3339 int index;
3340
3341 spin_lock_bh(&priv->tx_lock);
3342 for (index = 0; index < MWL8K_TX_QUEUES; index++) {
3343 txq = priv->txq + index;
3344 memcpy(&stats[index], &txq->tx_stats,
3345 sizeof(struct ieee80211_tx_queue_stats));
3346 }
3347 spin_unlock_bh(&priv->tx_lock);
3348 return 0;
3349}
3350
3351struct mwl8k_get_stats_worker {
3352 struct mwl8k_work_struct header;
3353 struct ieee80211_low_level_stats *stats;
3354};
3355
3356static int mwl8k_get_stats_wt(struct work_struct *wt)
3357{
3358 struct mwl8k_get_stats_worker *worker =
3359 (struct mwl8k_get_stats_worker *)wt;
3360
3361 return mwl8k_cmd_802_11_get_stat(worker->header.hw, worker->stats);
3362}
3363
3364static int mwl8k_get_stats(struct ieee80211_hw *hw,
3365 struct ieee80211_low_level_stats *stats)
3366{
3367 int rc;
3368 struct mwl8k_get_stats_worker *worker;
3369 struct mwl8k_priv *priv = hw->priv;
3370
3371 worker = kzalloc(sizeof(*worker), GFP_KERNEL);
3372 if (worker == NULL)
3373 return -ENOMEM;
3374
3375 worker->stats = stats;
3376 rc = mwl8k_queue_work(hw, &worker->header,
3377 priv->config_wq, mwl8k_get_stats_wt);
3378
3379 kfree(worker);
3380 if (rc == -ETIMEDOUT) {
3381 printk(KERN_ERR "%s() timed out\n", __func__);
3382 rc = -EINVAL;
3383 }
3384
3385 return rc;
3386}
3387
3388static const struct ieee80211_ops mwl8k_ops = {
3389 .tx = mwl8k_tx,
3390 .start = mwl8k_start,
3391 .stop = mwl8k_stop,
3392 .add_interface = mwl8k_add_interface,
3393 .remove_interface = mwl8k_remove_interface,
3394 .config = mwl8k_config,
a66098da 3395 .bss_info_changed = mwl8k_bss_info_changed,
3ac64bee 3396 .prepare_multicast = mwl8k_prepare_multicast,
a66098da
LB		 3397 .configure_filter = mwl8k_configure_filter,
3398 .set_rts_threshold = mwl8k_set_rts_threshold,
3399 .conf_tx = mwl8k_conf_tx,
3400 .get_tx_stats = mwl8k_get_tx_stats,
3401 .get_stats = mwl8k_get_stats,
3402};
3403
3404static void mwl8k_tx_reclaim_handler(unsigned long data)
3405{
3406 int i;
3407 struct ieee80211_hw *hw = (struct ieee80211_hw *) data;
3408 struct mwl8k_priv *priv = hw->priv;
3409
3410 spin_lock_bh(&priv->tx_lock);
3411 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3412 mwl8k_txq_reclaim(hw, i, 0);
3413
3414 if (priv->tx_wait != NULL) {
3415 int count = mwl8k_txq_busy(priv);
3416 if (count == 0) {
3417 complete(priv->tx_wait);
3418 priv->tx_wait = NULL;
3419 }
3420 }
3421 spin_unlock_bh(&priv->tx_lock);
3422}
3423
3424static void mwl8k_finalize_join_worker(struct work_struct *work)
3425{
3426 struct mwl8k_priv *priv =
3427 container_of(work, struct mwl8k_priv, finalize_join_worker);
3428 struct sk_buff *skb = priv->beacon_skb;
3429 u8 dtim = (MWL8K_VIF(priv->vif))->bss_info.dtim_period;
3430
3431 mwl8k_finalize_join(priv->hw, skb->data, skb->len, dtim);
3432 dev_kfree_skb(skb);
3433
3434 priv->beacon_skb = NULL;
3435}
3436
3437static int __devinit mwl8k_probe(struct pci_dev *pdev,
3438 const struct pci_device_id *id)
3439{
3440 struct ieee80211_hw *hw;
3441 struct mwl8k_priv *priv;
a66098da
LB		 3442 int rc;
3443 int i;
3444 u8 *fw;
3445
3446 rc = pci_enable_device(pdev);
3447 if (rc) {
3448 printk(KERN_ERR "%s: Cannot enable new PCI device\n",
3449 MWL8K_NAME);
3450 return rc;
3451 }
3452
3453 rc = pci_request_regions(pdev, MWL8K_NAME);
3454 if (rc) {
3455 printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
3456 MWL8K_NAME);
3457 return rc;
3458 }
3459
3460 pci_set_master(pdev);
3461
3462 hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
3463 if (hw == NULL) {
3464 printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
3465 rc = -ENOMEM;
3466 goto err_free_reg;
3467 }
3468
3469 priv = hw->priv;
3470 priv->hw = hw;
3471 priv->pdev = pdev;
3472 priv->hostcmd_wait = NULL;
3473 priv->tx_wait = NULL;
3474 priv->inconfig = false;
a66098da
LB		 3475 priv->wmm_mode = false;
3476 priv->pending_tx_pkts = 0;
3477 strncpy(priv->name, MWL8K_NAME, sizeof(priv->name));
3478
3479 spin_lock_init(&priv->fw_lock);
3480
3481 SET_IEEE80211_DEV(hw, &pdev->dev);
3482 pci_set_drvdata(pdev, hw);
3483
3484 priv->regs = pci_iomap(pdev, 1, 0x10000);
3485 if (priv->regs == NULL) {
3486 printk(KERN_ERR "%s: Cannot map device memory\n", priv->name);
3487 goto err_iounmap;
3488 }
3489
3490 memcpy(priv->channels, mwl8k_channels, sizeof(mwl8k_channels));
3491 priv->band.band = IEEE80211_BAND_2GHZ;
3492 priv->band.channels = priv->channels;
3493 priv->band.n_channels = ARRAY_SIZE(mwl8k_channels);
3494 priv->band.bitrates = priv->rates;
3495 priv->band.n_bitrates = ARRAY_SIZE(mwl8k_rates);
3496 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
3497
3498 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(mwl8k_rates));
3499 memcpy(priv->rates, mwl8k_rates, sizeof(mwl8k_rates));
3500
3501 /*
3502 * Extra headroom is the size of the required DMA header
3503 * minus the size of the smallest 802.11 frame (CTS frame).
3504 */
3505 hw->extra_tx_headroom =
3506 sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
3507
3508 hw->channel_change_time = 10;
3509
3510 hw->queues = MWL8K_TX_QUEUES;
3511
3512 hw->wiphy->interface_modes =
3513 BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_MONITOR);
3514
3515 /* Set rssi and noise values to dBm */
3516 hw->flags |= (IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM);
3517 hw->vif_data_size = sizeof(struct mwl8k_vif);
3518 priv->vif = NULL;
3519
3520 /* Set default radio state and preamble */
3521 priv->radio_preamble = MWL8K_RADIO_DEFAULT_PREAMBLE;
3522 priv->radio_state = MWL8K_RADIO_DISABLE;
3523
3524 /* Finalize join worker */
3525 INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
3526
3527 /* TX reclaim tasklet */
3528 tasklet_init(&priv->tx_reclaim_task,
3529 mwl8k_tx_reclaim_handler, (unsigned long)hw);
3530 tasklet_disable(&priv->tx_reclaim_task);
3531
3532 /* Config workthread */
3533 priv->config_wq = create_singlethread_workqueue("mwl8k_config");
3534 if (priv->config_wq == NULL)
3535 goto err_iounmap;
3536
3537 /* Power management cookie */
3538 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
3539 if (priv->cookie == NULL)
3540 goto err_iounmap;
3541
3542 rc = mwl8k_rxq_init(hw, 0);
3543 if (rc)
3544 goto err_iounmap;
3545 rxq_refill(hw, 0, INT_MAX);
3546
3547 spin_lock_init(&priv->tx_lock);
3548
3549 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
3550 rc = mwl8k_txq_init(hw, i);
3551 if (rc)
3552 goto err_free_queues;
3553 }
3554
3555 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
c23b5a69 3556 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3557 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
3558 iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
3559
3560 rc = request_irq(priv->pdev->irq, &mwl8k_interrupt,
3561 IRQF_SHARED, MWL8K_NAME, hw);
3562 if (rc) {
3563 printk(KERN_ERR "%s: failed to register IRQ handler\n",
3564 priv->name);
3565 goto err_free_queues;
3566 }
3567
3568 /* Reset firmware and hardware */
3569 mwl8k_hw_reset(priv);
3570
3571 /* Ask userland hotplug daemon for the device firmware */
3572 rc = mwl8k_request_firmware(priv, (u32)id->driver_data);
3573 if (rc) {
3574 printk(KERN_ERR "%s: Firmware files not found\n", priv->name);
3575 goto err_free_irq;
3576 }
3577
3578 /* Load firmware into hardware */
3579 rc = mwl8k_load_firmware(priv);
3580 if (rc) {
3581 printk(KERN_ERR "%s: Cannot start firmware\n", priv->name);
3582 goto err_stop_firmware;
3583 }
3584
3585 /* Reclaim memory once firmware is successfully loaded */
3586 mwl8k_release_firmware(priv);
3587
3588 /*
3589 * Temporarily enable interrupts. Initial firmware host
3590 * commands use interrupts and avoids polling. Disable
3591 * interrupts when done.
3592 */
c23b5a69 3593 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3594
3595 /* Get config data, mac addrs etc */
3596 rc = mwl8k_cmd_get_hw_spec(hw);
3597 if (rc) {
3598 printk(KERN_ERR "%s: Cannot initialise firmware\n", priv->name);
3599 goto err_stop_firmware;
3600 }
3601
3602 /* Turn radio off */
3603 rc = mwl8k_cmd_802_11_radio_control(hw, MWL8K_RADIO_DISABLE);
3604 if (rc) {
3605 printk(KERN_ERR "%s: Cannot disable\n", priv->name);
3606 goto err_stop_firmware;
3607 }
3608
3609 /* Disable interrupts */
3610 spin_lock_irq(&priv->tx_lock);
3611 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3612 spin_unlock_irq(&priv->tx_lock);
3613 free_irq(priv->pdev->irq, hw);
3614
3615 rc = ieee80211_register_hw(hw);
3616 if (rc) {
3617 printk(KERN_ERR "%s: Cannot register device\n", priv->name);
3618 goto err_stop_firmware;
3619 }
3620
3621 fw = (u8 *)&priv->fw_rev;
3622 printk(KERN_INFO "%s: 88W%u %s\n", priv->name, priv->part_num,
3623 MWL8K_DESC);
3624 printk(KERN_INFO "%s: Driver Ver:%s Firmware Ver:%u.%u.%u.%u\n",
3625 priv->name, MWL8K_VERSION, fw[3], fw[2], fw[1], fw[0]);
e91d8334
JB		 3626 printk(KERN_INFO "%s: MAC Address: %pM\n", priv->name,
3627 hw->wiphy->perm_addr);
a66098da
LB		 3628
3629 return 0;
3630
3631err_stop_firmware:
3632 mwl8k_hw_reset(priv);
3633 mwl8k_release_firmware(priv);
3634
3635err_free_irq:
3636 spin_lock_irq(&priv->tx_lock);
3637 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3638 spin_unlock_irq(&priv->tx_lock);
3639 free_irq(priv->pdev->irq, hw);
3640
3641err_free_queues:
3642 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3643 mwl8k_txq_deinit(hw, i);
3644 mwl8k_rxq_deinit(hw, 0);
3645
3646err_iounmap:
3647 if (priv->cookie != NULL)
3648 pci_free_consistent(priv->pdev, 4,
3649 priv->cookie, priv->cookie_dma);
3650
3651 if (priv->regs != NULL)
3652 pci_iounmap(pdev, priv->regs);
3653
3654 if (priv->config_wq != NULL)
3655 destroy_workqueue(priv->config_wq);
3656
3657 pci_set_drvdata(pdev, NULL);
3658 ieee80211_free_hw(hw);
3659
3660err_free_reg:
3661 pci_release_regions(pdev);
3662 pci_disable_device(pdev);
3663
3664 return rc;
3665}
3666
230f7af0 3667static void __devexit mwl8k_shutdown(struct pci_dev *pdev)
a66098da
LB		 3668{
3669 printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__);
3670}
3671
230f7af0 3672static void __devexit mwl8k_remove(struct pci_dev *pdev)
a66098da
LB		 3673{
3674 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
3675 struct mwl8k_priv *priv;
3676 int i;
3677
3678 if (hw == NULL)
3679 return;
3680 priv = hw->priv;
3681
3682 ieee80211_stop_queues(hw);
3683
60aa569f
LB		 3684 ieee80211_unregister_hw(hw);
3685
a66098da
LB		 3686 /* Remove tx reclaim tasklet */
3687 tasklet_kill(&priv->tx_reclaim_task);
3688
3689 /* Stop config thread */
3690 destroy_workqueue(priv->config_wq);
3691
3692 /* Stop hardware */
3693 mwl8k_hw_reset(priv);
3694
3695 /* Return all skbs to mac80211 */
3696 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3697 mwl8k_txq_reclaim(hw, i, 1);
3698
a66098da
LB		 3699 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3700 mwl8k_txq_deinit(hw, i);
3701
3702 mwl8k_rxq_deinit(hw, 0);
3703
3704 pci_free_consistent(priv->pdev, 4,
3705 priv->cookie, priv->cookie_dma);
3706
3707 pci_iounmap(pdev, priv->regs);
3708 pci_set_drvdata(pdev, NULL);
3709 ieee80211_free_hw(hw);
3710 pci_release_regions(pdev);
3711 pci_disable_device(pdev);
3712}
3713
3714static struct pci_driver mwl8k_driver = {
3715 .name = MWL8K_NAME,
3716 .id_table = mwl8k_table,
3717 .probe = mwl8k_probe,
3718 .remove = __devexit_p(mwl8k_remove),
3719 .shutdown = __devexit_p(mwl8k_shutdown),
3720};
3721
3722static int __init mwl8k_init(void)
3723{
3724 return pci_register_driver(&mwl8k_driver);
3725}
3726
3727static void __exit mwl8k_exit(void)
3728{
3729 pci_unregister_driver(&mwl8k_driver);
3730}
3731
3732module_init(mwl8k_init);
3733module_exit(mwl8k_exit);
Linux kernel - Deliverables
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