[deliverable/linux.git] / drivers / net / wireless / p54 / p54spi.c

/*
 * Copyright (C) 2008 Christian Lamparter <chunkeey@web.de>
 * Copyright 2008       Johannes Berg <johannes@sipsolutions.net>
 *
 * This driver is a port from stlc45xx:
 *	Copyright (C) 2008 Nokia Corporation and/or its subsidiary(-ies).
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 */

#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/firmware.h>
#include <linux/delay.h>
#include <linux/irq.h>
#include <linux/spi/spi.h>
#include <linux/etherdevice.h>
#include <linux/gpio.h>

#include "p54spi.h"
#include "p54spi_eeprom.h"
#include "p54.h"

#include "p54common.h"

MODULE_FIRMWARE("3826.arm");
MODULE_ALIAS("stlc45xx");

/*
 * gpios should be handled in board files and provided via platform data,
 * but because it's currently impossible for p54spi to have a header file
 * in include/linux, let's use module paramaters for now
 */

static int p54spi_gpio_power = 97;
module_param(p54spi_gpio_power, int, 0444);
MODULE_PARM_DESC(p54spi_gpio_power, "gpio number for power line");

static int p54spi_gpio_irq = 87;
module_param(p54spi_gpio_irq, int, 0444);
MODULE_PARM_DESC(p54spi_gpio_irq, "gpio number for irq line");

static void p54spi_spi_read(struct p54s_priv *priv, u8 address,
			      void *buf, size_t len)
{
	struct spi_transfer t[2];
	struct spi_message m;
	__le16 addr;

	/* We first push the address */
	addr = cpu_to_le16(address << 8 | SPI_ADRS_READ_BIT_15);

	spi_message_init(&m);
	memset(t, 0, sizeof(t));

	t[0].tx_buf = &addr;
	t[0].len = sizeof(addr);
	spi_message_add_tail(&t[0], &m);

	t[1].rx_buf = buf;
	t[1].len = len;
	spi_message_add_tail(&t[1], &m);

	spi_sync(priv->spi, &m);
}


static void p54spi_spi_write(struct p54s_priv *priv, u8 address,
			     const void *buf, size_t len)
{
	struct spi_transfer t[3];
	struct spi_message m;
	__le16 addr;

	/* We first push the address */
	addr = cpu_to_le16(address << 8);

	spi_message_init(&m);
	memset(t, 0, sizeof(t));

	t[0].tx_buf = &addr;
	t[0].len = sizeof(addr);
	spi_message_add_tail(&t[0], &m);

	t[1].tx_buf = buf;
	t[1].len = len & ~1;
	spi_message_add_tail(&t[1], &m);

	if (len % 2) {
		__le16 last_word;
		last_word = cpu_to_le16(((u8 *)buf)[len - 1]);

		t[2].tx_buf = &last_word;
		t[2].len = sizeof(last_word);
		spi_message_add_tail(&t[2], &m);
	}

	spi_sync(priv->spi, &m);
}

static u16 p54spi_read16(struct p54s_priv *priv, u8 addr)
{
	__le16 val;

	p54spi_spi_read(priv, addr, &val, sizeof(val));

	return le16_to_cpu(val);
}

static u32 p54spi_read32(struct p54s_priv *priv, u8 addr)
{
	__le32 val;

	p54spi_spi_read(priv, addr, &val, sizeof(val));

	return le32_to_cpu(val);
}

static inline void p54spi_write16(struct p54s_priv *priv, u8 addr, __le16 val)
{
	p54spi_spi_write(priv, addr, &val, sizeof(val));
}

static inline void p54spi_write32(struct p54s_priv *priv, u8 addr, __le32 val)
{
	p54spi_spi_write(priv, addr, &val, sizeof(val));
}

struct p54spi_spi_reg {
	u16 address;		/* __le16 ? */
	u16 length;
	char *name;
};

static const struct p54spi_spi_reg p54spi_registers_array[] =
{
	{ SPI_ADRS_ARM_INTERRUPTS,	32, "ARM_INT     " },
	{ SPI_ADRS_ARM_INT_EN,		32, "ARM_INT_ENA " },
	{ SPI_ADRS_HOST_INTERRUPTS,	32, "HOST_INT    " },
	{ SPI_ADRS_HOST_INT_EN,		32, "HOST_INT_ENA" },
	{ SPI_ADRS_HOST_INT_ACK,	32, "HOST_INT_ACK" },
	{ SPI_ADRS_GEN_PURP_1,		32, "GP1_COMM    " },
	{ SPI_ADRS_GEN_PURP_2,		32, "GP2_COMM    " },
	{ SPI_ADRS_DEV_CTRL_STAT,	32, "DEV_CTRL_STA" },
	{ SPI_ADRS_DMA_DATA,		16, "DMA_DATA    " },
	{ SPI_ADRS_DMA_WRITE_CTRL,	16, "DMA_WR_CTRL " },
	{ SPI_ADRS_DMA_WRITE_LEN,	16, "DMA_WR_LEN  " },
	{ SPI_ADRS_DMA_WRITE_BASE,	32, "DMA_WR_BASE " },
	{ SPI_ADRS_DMA_READ_CTRL,	16, "DMA_RD_CTRL " },
	{ SPI_ADRS_DMA_READ_LEN,	16, "DMA_RD_LEN  " },
	{ SPI_ADRS_DMA_WRITE_BASE,	32, "DMA_RD_BASE " }
};

static int p54spi_wait_bit(struct p54s_priv *priv, u16 reg, __le32 bits)
{
	int i;

	for (i = 0; i < 2000; i++) {
		__le32 buffer = p54spi_read32(priv, reg);
		if ((buffer & bits) == bits)
			return 1;
	}
	return 0;
}

static int p54spi_spi_write_dma(struct p54s_priv *priv, __le32 base,
				const void *buf, size_t len)
{
	if (!p54spi_wait_bit(priv, SPI_ADRS_DMA_WRITE_CTRL,
			     cpu_to_le32(HOST_ALLOWED))) {
		dev_err(&priv->spi->dev, "spi_write_dma not allowed "
			"to DMA write.\n");
		return -EAGAIN;
	}

	p54spi_write16(priv, SPI_ADRS_DMA_WRITE_CTRL,
		       cpu_to_le16(SPI_DMA_WRITE_CTRL_ENABLE));

	p54spi_write16(priv, SPI_ADRS_DMA_WRITE_LEN, cpu_to_le16(len));
	p54spi_write32(priv, SPI_ADRS_DMA_WRITE_BASE, base);
	p54spi_spi_write(priv, SPI_ADRS_DMA_DATA, buf, len);
	return 0;
}

static int p54spi_request_firmware(struct ieee80211_hw *dev)
{
	struct p54s_priv *priv = dev->priv;
	int ret;

	/* FIXME: should driver use it's own struct device? */
	ret = request_firmware(&priv->firmware, "3826.arm", &priv->spi->dev);

	if (ret < 0) {
		dev_err(&priv->spi->dev, "request_firmware() failed: %d", ret);
		return ret;
	}

	ret = p54_parse_firmware(dev, priv->firmware);
	if (ret) {
		release_firmware(priv->firmware);
		return ret;
	}

	return 0;
}

static int p54spi_request_eeprom(struct ieee80211_hw *dev)
{
	struct p54s_priv *priv = dev->priv;
	const struct firmware *eeprom;
	int ret;

	/*
	 * allow users to customize their eeprom.
	 */

	ret = request_firmware(&eeprom, "3826.eeprom", &priv->spi->dev);
	if (ret < 0) {
		dev_info(&priv->spi->dev, "loading default eeprom...\n");
		ret = p54_parse_eeprom(dev, (void *) p54spi_eeprom,
				       sizeof(p54spi_eeprom));
	} else {
		dev_info(&priv->spi->dev, "loading user eeprom...\n");
		ret = p54_parse_eeprom(dev, (void *) eeprom->data,
				       (int)eeprom->size);
		release_firmware(eeprom);
	}
	return ret;
}

static int p54spi_upload_firmware(struct ieee80211_hw *dev)
{
	struct p54s_priv *priv = dev->priv;
	unsigned long fw_len, _fw_len;
	unsigned int offset = 0;
	int err = 0;
	u8 *fw;

	fw_len = priv->firmware->size;
	fw = kmemdup(priv->firmware->data, fw_len, GFP_KERNEL);
	if (!fw)
		return -ENOMEM;

	/* stop the device */
	p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
		       SPI_CTRL_STAT_HOST_OVERRIDE | SPI_CTRL_STAT_HOST_RESET |
		       SPI_CTRL_STAT_START_HALTED));

	msleep(TARGET_BOOT_SLEEP);

	p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
		       SPI_CTRL_STAT_HOST_OVERRIDE |
		       SPI_CTRL_STAT_START_HALTED));

	msleep(TARGET_BOOT_SLEEP);

	while (fw_len > 0) {
		_fw_len = min_t(long, fw_len, SPI_MAX_PACKET_SIZE);

		err = p54spi_spi_write_dma(priv, cpu_to_le32(
					   ISL38XX_DEV_FIRMWARE_ADDR + offset),
					   (fw + offset), _fw_len);
		if (err < 0)
			goto out;

		fw_len -= _fw_len;
		offset += _fw_len;
	}

	BUG_ON(fw_len != 0);

	/* enable host interrupts */
	p54spi_write32(priv, SPI_ADRS_HOST_INT_EN,
		       cpu_to_le32(SPI_HOST_INTS_DEFAULT));

	/* boot the device */
	p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
		       SPI_CTRL_STAT_HOST_OVERRIDE | SPI_CTRL_STAT_HOST_RESET |
		       SPI_CTRL_STAT_RAM_BOOT));

	msleep(TARGET_BOOT_SLEEP);

	p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
		       SPI_CTRL_STAT_HOST_OVERRIDE | SPI_CTRL_STAT_RAM_BOOT));
	msleep(TARGET_BOOT_SLEEP);

out:
	kfree(fw);
	return err;
}

static void p54spi_power_off(struct p54s_priv *priv)
{
	disable_irq(gpio_to_irq(p54spi_gpio_irq));
	gpio_set_value(p54spi_gpio_power, 0);
}

static void p54spi_power_on(struct p54s_priv *priv)
{
	gpio_set_value(p54spi_gpio_power, 1);
	enable_irq(gpio_to_irq(p54spi_gpio_irq));

	/*
	 * need to wait a while before device can be accessed, the lenght
	 * is just a guess
	 */
	msleep(10);
}

static inline void p54spi_int_ack(struct p54s_priv *priv, u32 val)
{
	p54spi_write32(priv, SPI_ADRS_HOST_INT_ACK, cpu_to_le32(val));
}

static int p54spi_wakeup(struct p54s_priv *priv)
{
	/* wake the chip */
	p54spi_write32(priv, SPI_ADRS_ARM_INTERRUPTS,
		       cpu_to_le32(SPI_TARGET_INT_WAKEUP));

	/* And wait for the READY interrupt */
	if (!p54spi_wait_bit(priv, SPI_ADRS_HOST_INTERRUPTS,
			     cpu_to_le32(SPI_HOST_INT_READY))) {
		dev_err(&priv->spi->dev, "INT_READY timeout\n");
		return -EBUSY;
	}

	p54spi_int_ack(priv, SPI_HOST_INT_READY);
	return 0;
}

static inline void p54spi_sleep(struct p54s_priv *priv)
{
	p54spi_write32(priv, SPI_ADRS_ARM_INTERRUPTS,
		       cpu_to_le32(SPI_TARGET_INT_SLEEP));
}

static void p54spi_int_ready(struct p54s_priv *priv)
{
	p54spi_write32(priv, SPI_ADRS_HOST_INT_EN, cpu_to_le32(
		       SPI_HOST_INT_UPDATE | SPI_HOST_INT_SW_UPDATE));

	switch (priv->fw_state) {
	case FW_STATE_BOOTING:
		priv->fw_state = FW_STATE_READY;
		complete(&priv->fw_comp);
		break;
	case FW_STATE_RESETTING:
		priv->fw_state = FW_STATE_READY;
		/* TODO: reinitialize state */
		break;
	default:
		break;
	}
}

static int p54spi_rx(struct p54s_priv *priv)
{
	struct sk_buff *skb;
	u16 len;

	if (p54spi_wakeup(priv) < 0)
		return -EBUSY;

	/* dummy read to flush SPI DMA controller bug */
	p54spi_read16(priv, SPI_ADRS_GEN_PURP_1);

	len = p54spi_read16(priv, SPI_ADRS_DMA_DATA);

	if (len == 0) {
		dev_err(&priv->spi->dev, "rx request of zero bytes");
		return 0;
	}


	/* Firmware may insert up to 4 padding bytes after the lmac header,
	 * but it does not amend the size of SPI data transfer.
	 * Such packets has correct data size in header, thus referencing
	 * past the end of allocated skb. Reserve extra 4 bytes for this case */
	skb = dev_alloc_skb(len + 4);
	if (!skb) {
		dev_err(&priv->spi->dev, "could not alloc skb");
		return 0;
	}

	p54spi_spi_read(priv, SPI_ADRS_DMA_DATA, skb_put(skb, len), len);
	p54spi_sleep(priv);
	/* Put additional bytes to compensate for the possible
	 * alignment-caused truncation */
	skb_put(skb, 4);

	if (p54_rx(priv->hw, skb) == 0)
		dev_kfree_skb(skb);

	return 0;
}


static irqreturn_t p54spi_interrupt(int irq, void *config)
{
	struct spi_device *spi = config;
	struct p54s_priv *priv = dev_get_drvdata(&spi->dev);

	queue_work(priv->hw->workqueue, &priv->work);

	return IRQ_HANDLED;
}

static int p54spi_tx_frame(struct p54s_priv *priv, struct sk_buff *skb)
{
	struct p54_hdr *hdr = (struct p54_hdr *) skb->data;
	int ret = 0;

	if (p54spi_wakeup(priv) < 0)
		return -EBUSY;

	ret = p54spi_spi_write_dma(priv, hdr->req_id, skb->data, skb->len);
	if (ret < 0)
		goto out;

	if (!p54spi_wait_bit(priv, SPI_ADRS_HOST_INTERRUPTS,
			     cpu_to_le32(SPI_HOST_INT_WR_READY))) {
		dev_err(&priv->spi->dev, "WR_READY timeout\n");
		ret = -EAGAIN;
		goto out;
	}

	p54spi_int_ack(priv, SPI_HOST_INT_WR_READY);

	if (FREE_AFTER_TX(skb))
		p54_free_skb(priv->hw, skb);
out:
	p54spi_sleep(priv);
	return ret;
}

static int p54spi_wq_tx(struct p54s_priv *priv)
{
	struct p54s_tx_info *entry;
	struct sk_buff *skb;
	struct ieee80211_tx_info *info;
	struct p54_tx_info *minfo;
	struct p54s_tx_info *dinfo;
	unsigned long flags;
	int ret = 0;

	spin_lock_irqsave(&priv->tx_lock, flags);

	while (!list_empty(&priv->tx_pending)) {
		entry = list_entry(priv->tx_pending.next,
				   struct p54s_tx_info, tx_list);

		list_del_init(&entry->tx_list);

		spin_unlock_irqrestore(&priv->tx_lock, flags);

		dinfo = container_of((void *) entry, struct p54s_tx_info,
				     tx_list);
		minfo = container_of((void *) dinfo, struct p54_tx_info,
				     data);
		info = container_of((void *) minfo, struct ieee80211_tx_info,
				    rate_driver_data);
		skb = container_of((void *) info, struct sk_buff, cb);

		ret = p54spi_tx_frame(priv, skb);

		if (ret < 0) {
			p54_free_skb(priv->hw, skb);
			return ret;
		}

		spin_lock_irqsave(&priv->tx_lock, flags);
	}
	spin_unlock_irqrestore(&priv->tx_lock, flags);
	return ret;
}

static void p54spi_op_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
{
	struct p54s_priv *priv = dev->priv;
	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
	struct p54_tx_info *mi = (struct p54_tx_info *) info->rate_driver_data;
	struct p54s_tx_info *di = (struct p54s_tx_info *) mi->data;
	unsigned long flags;

	BUILD_BUG_ON(sizeof(*di) > sizeof((mi->data)));

	spin_lock_irqsave(&priv->tx_lock, flags);
	list_add_tail(&di->tx_list, &priv->tx_pending);
	spin_unlock_irqrestore(&priv->tx_lock, flags);

	queue_work(priv->hw->workqueue, &priv->work);
}

static void p54spi_work(struct work_struct *work)
{
	struct p54s_priv *priv = container_of(work, struct p54s_priv, work);
	u32 ints;
	int ret;

	mutex_lock(&priv->mutex);

	if (priv->fw_state == FW_STATE_OFF &&
	    priv->fw_state == FW_STATE_RESET)
		goto out;

	ints = p54spi_read32(priv, SPI_ADRS_HOST_INTERRUPTS);

	if (ints & SPI_HOST_INT_READY) {
		p54spi_int_ready(priv);
		p54spi_int_ack(priv, SPI_HOST_INT_READY);
	}

	if (priv->fw_state != FW_STATE_READY)
		goto out;

	if (ints & SPI_HOST_INT_UPDATE) {
		p54spi_int_ack(priv, SPI_HOST_INT_UPDATE);
		ret = p54spi_rx(priv);
		if (ret < 0)
			goto out;
	}
	if (ints & SPI_HOST_INT_SW_UPDATE) {
		p54spi_int_ack(priv, SPI_HOST_INT_SW_UPDATE);
		ret = p54spi_rx(priv);
		if (ret < 0)
			goto out;
	}

	ret = p54spi_wq_tx(priv);
out:
	mutex_unlock(&priv->mutex);
}

static int p54spi_op_start(struct ieee80211_hw *dev)
{
	struct p54s_priv *priv = dev->priv;
	unsigned long timeout;
	int ret = 0;

	if (mutex_lock_interruptible(&priv->mutex)) {
		ret = -EINTR;
		goto out;
	}

	priv->fw_state = FW_STATE_BOOTING;

	p54spi_power_on(priv);

	ret = p54spi_upload_firmware(dev);
	if (ret < 0) {
		p54spi_power_off(priv);
		goto out_unlock;
	}

	mutex_unlock(&priv->mutex);

	timeout = msecs_to_jiffies(2000);
	timeout = wait_for_completion_interruptible_timeout(&priv->fw_comp,
							    timeout);
	if (!timeout) {
		dev_err(&priv->spi->dev, "firmware boot failed");
		p54spi_power_off(priv);
		ret = -1;
		goto out;
	}

	if (mutex_lock_interruptible(&priv->mutex)) {
		ret = -EINTR;
		p54spi_power_off(priv);
		goto out;
	}

	WARN_ON(priv->fw_state != FW_STATE_READY);

out_unlock:
	mutex_unlock(&priv->mutex);

out:
	return ret;
}

static void p54spi_op_stop(struct ieee80211_hw *dev)
{
	struct p54s_priv *priv = dev->priv;
	unsigned long flags;

	if (mutex_lock_interruptible(&priv->mutex)) {
		/* FIXME: how to handle this error? */
		return;
	}

	WARN_ON(priv->fw_state != FW_STATE_READY);

	cancel_work_sync(&priv->work);

	p54spi_power_off(priv);
	spin_lock_irqsave(&priv->tx_lock, flags);
	INIT_LIST_HEAD(&priv->tx_pending);
	spin_unlock_irqrestore(&priv->tx_lock, flags);

	priv->fw_state = FW_STATE_OFF;
	mutex_unlock(&priv->mutex);
}

static int __devinit p54spi_probe(struct spi_device *spi)
{
	struct p54s_priv *priv = NULL;
	struct ieee80211_hw *hw;
	int ret = -EINVAL;

	hw = p54_init_common(sizeof(*priv));
	if (!hw) {
		dev_err(&priv->spi->dev, "could not alloc ieee80211_hw");
		return -ENOMEM;
	}

	priv = hw->priv;
	priv->hw = hw;
	dev_set_drvdata(&spi->dev, priv);
	priv->spi = spi;

	spi->bits_per_word = 16;
	spi->max_speed_hz = 24000000;

	ret = spi_setup(spi);
	if (ret < 0) {
		dev_err(&priv->spi->dev, "spi_setup failed");
		goto err_free_common;
	}

	ret = gpio_request(p54spi_gpio_power, "p54spi power");
	if (ret < 0) {
		dev_err(&priv->spi->dev, "power GPIO request failed: %d", ret);
		goto err_free_common;
	}

	ret = gpio_request(p54spi_gpio_irq, "p54spi irq");
	if (ret < 0) {
		dev_err(&priv->spi->dev, "irq GPIO request failed: %d", ret);
		goto err_free_common;
	}

	gpio_direction_output(p54spi_gpio_power, 0);
	gpio_direction_input(p54spi_gpio_irq);

	ret = request_irq(gpio_to_irq(p54spi_gpio_irq),
			  p54spi_interrupt, IRQF_DISABLED, "p54spi",
			  priv->spi);
	if (ret < 0) {
		dev_err(&priv->spi->dev, "request_irq() failed");
		goto err_free_common;
	}

	set_irq_type(gpio_to_irq(p54spi_gpio_irq),
		     IRQ_TYPE_EDGE_RISING);

	disable_irq(gpio_to_irq(p54spi_gpio_irq));

	INIT_WORK(&priv->work, p54spi_work);
	init_completion(&priv->fw_comp);
	INIT_LIST_HEAD(&priv->tx_pending);
	mutex_init(&priv->mutex);
	SET_IEEE80211_DEV(hw, &spi->dev);
	priv->common.open = p54spi_op_start;
	priv->common.stop = p54spi_op_stop;
	priv->common.tx = p54spi_op_tx;

	ret = p54spi_request_firmware(hw);
	if (ret < 0)
		goto err_free_common;

	ret = p54spi_request_eeprom(hw);
	if (ret)
		goto err_free_common;

	ret = p54_register_common(hw, &priv->spi->dev);
	if (ret)
		goto err_free_common;

	return 0;

err_free_common:
	p54_free_common(priv->hw);
	return ret;
}

static int __devexit p54spi_remove(struct spi_device *spi)
{
	struct p54s_priv *priv = dev_get_drvdata(&spi->dev);

	ieee80211_unregister_hw(priv->hw);

	free_irq(gpio_to_irq(p54spi_gpio_irq), spi);

	gpio_free(p54spi_gpio_power);
	gpio_free(p54spi_gpio_irq);
	release_firmware(priv->firmware);

	mutex_destroy(&priv->mutex);

	p54_free_common(priv->hw);
	ieee80211_free_hw(priv->hw);

	return 0;
}


static struct spi_driver p54spi_driver = {
	.driver = {
		/* use cx3110x name because board-n800.c uses that for the
		 * SPI port */
		.name		= "cx3110x",
		.bus		= &spi_bus_type,
		.owner		= THIS_MODULE,
	},

	.probe		= p54spi_probe,
	.remove		= __devexit_p(p54spi_remove),
};

static int __init p54spi_init(void)
{
	int ret;

	ret = spi_register_driver(&p54spi_driver);
	if (ret < 0) {
		printk(KERN_ERR "failed to register SPI driver: %d", ret);
		goto out;
	}

out:
	return ret;
}

static void __exit p54spi_exit(void)
{
	spi_unregister_driver(&p54spi_driver);
}

module_init(p54spi_init);
module_exit(p54spi_exit);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Christian Lamparter <chunkeey@web.de>");
Commit	Line	Data
cd8d3d32 CL	1	/*
	2	* Copyright (C) 2008 Christian Lamparter <chunkeey@web.de>
	3	* Copyright 2008 Johannes Berg <johannes@sipsolutions.net>
	4	*
	5	* This driver is a port from stlc45xx:
	6	* Copyright (C) 2008 Nokia Corporation and/or its subsidiary(-ies).
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License
	10	* version 2 as published by the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope that it will be useful, but
	13	* WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	20	* 02110-1301 USA
	21	*/
	22
	23	#include <linux/module.h>
	24	#include <linux/platform_device.h>
	25	#include <linux/interrupt.h>
	26	#include <linux/firmware.h>
	27	#include <linux/delay.h>
	28	#include <linux/irq.h>
	29	#include <linux/spi/spi.h>
	30	#include <linux/etherdevice.h>
	31	#include <linux/gpio.h>
	32
	33	#include "p54spi.h"
	34	#include "p54spi_eeprom.h"
	35	#include "p54.h"
	36
	37	#include "p54common.h"
	38
	39	MODULE_FIRMWARE("3826.arm");
	40	MODULE_ALIAS("stlc45xx");
	41
a2116993 CL	42	/*
	43	* gpios should be handled in board files and provided via platform data,
	44	* but because it's currently impossible for p54spi to have a header file
	45	* in include/linux, let's use module paramaters for now
	46	*/
	47
	48	static int p54spi_gpio_power = 97;
	49	module_param(p54spi_gpio_power, int, 0444);
	50	MODULE_PARM_DESC(p54spi_gpio_power, "gpio number for power line");
	51
	52	static int p54spi_gpio_irq = 87;
	53	module_param(p54spi_gpio_irq, int, 0444);
	54	MODULE_PARM_DESC(p54spi_gpio_irq, "gpio number for irq line");
	55
cd8d3d32 CL	56	static void p54spi_spi_read(struct p54s_priv *priv, u8 address,
	57	void *buf, size_t len)
	58	{
	59	struct spi_transfer t[2];
	60	struct spi_message m;
	61	__le16 addr;
	62
	63	/* We first push the address */
	64	addr = cpu_to_le16(address << 8 \| SPI_ADRS_READ_BIT_15);
	65
	66	spi_message_init(&m);
	67	memset(t, 0, sizeof(t));
	68
	69	t[0].tx_buf = &addr;
	70	t[0].len = sizeof(addr);
	71	spi_message_add_tail(&t[0], &m);
	72
	73	t[1].rx_buf = buf;
	74	t[1].len = len;
	75	spi_message_add_tail(&t[1], &m);
	76
	77	spi_sync(priv->spi, &m);
	78	}
	79
	80
	81	static void p54spi_spi_write(struct p54s_priv *priv, u8 address,
	82	const void *buf, size_t len)
	83	{
	84	struct spi_transfer t[3];
	85	struct spi_message m;
	86	__le16 addr;
	87
	88	/* We first push the address */
	89	addr = cpu_to_le16(address << 8);
	90
	91	spi_message_init(&m);
	92	memset(t, 0, sizeof(t));
	93
	94	t[0].tx_buf = &addr;
	95	t[0].len = sizeof(addr);
	96	spi_message_add_tail(&t[0], &m);
	97
	98	t[1].tx_buf = buf;
69712e92	99	t[1].len = len & ~1;
cd8d3d32 CL	100	spi_message_add_tail(&t[1], &m);
	101
	102	if (len % 2) {
	103	__le16 last_word;
	104	last_word = cpu_to_le16(((u8 *)buf)[len - 1]);
	105
	106	t[2].tx_buf = &last_word;
	107	t[2].len = sizeof(last_word);
	108	spi_message_add_tail(&t[2], &m);
	109	}
	110
	111	spi_sync(priv->spi, &m);
	112	}
	113
	114	static u16 p54spi_read16(struct p54s_priv *priv, u8 addr)
	115	{
	116	__le16 val;
	117
	118	p54spi_spi_read(priv, addr, &val, sizeof(val));
	119
	120	return le16_to_cpu(val);
	121	}
	122
	123	static u32 p54spi_read32(struct p54s_priv *priv, u8 addr)
	124	{
	125	__le32 val;
	126
	127	p54spi_spi_read(priv, addr, &val, sizeof(val));
	128
	129	return le32_to_cpu(val);
	130	}
	131
	132	static inline void p54spi_write16(struct p54s_priv *priv, u8 addr, __le16 val)
	133	{
	134	p54spi_spi_write(priv, addr, &val, sizeof(val));
	135	}
	136
	137	static inline void p54spi_write32(struct p54s_priv *priv, u8 addr, __le32 val)
	138	{
	139	p54spi_spi_write(priv, addr, &val, sizeof(val));
	140	}
	141
	142	struct p54spi_spi_reg {
	143	u16 address; /* __le16 ? */
	144	u16 length;
	145	char *name;
	146	};
	147
	148	static const struct p54spi_spi_reg p54spi_registers_array[] =
	149	{
	150	{ SPI_ADRS_ARM_INTERRUPTS, 32, "ARM_INT " },
	151	{ SPI_ADRS_ARM_INT_EN, 32, "ARM_INT_ENA " },
	152	{ SPI_ADRS_HOST_INTERRUPTS, 32, "HOST_INT " },
	153	{ SPI_ADRS_HOST_INT_EN, 32, "HOST_INT_ENA" },
	154	{ SPI_ADRS_HOST_INT_ACK, 32, "HOST_INT_ACK" },
	155	{ SPI_ADRS_GEN_PURP_1, 32, "GP1_COMM " },
	156	{ SPI_ADRS_GEN_PURP_2, 32, "GP2_COMM " },
	157	{ SPI_ADRS_DEV_CTRL_STAT, 32, "DEV_CTRL_STA" },
	158	{ SPI_ADRS_DMA_DATA, 16, "DMA_DATA " },
	159	{ SPI_ADRS_DMA_WRITE_CTRL, 16, "DMA_WR_CTRL " },
	160	{ SPI_ADRS_DMA_WRITE_LEN, 16, "DMA_WR_LEN " },
	161	{ SPI_ADRS_DMA_WRITE_BASE, 32, "DMA_WR_BASE " },
	162	{ SPI_ADRS_DMA_READ_CTRL, 16, "DMA_RD_CTRL " },
	163	{ SPI_ADRS_DMA_READ_LEN, 16, "DMA_RD_LEN " },
164	{ SPI_ADRS_DMA_WRITE_BASE, 32, "DMA_RD_BASE " }
165	};
166
167	static int p54spi_wait_bit(struct p54s_priv *priv, u16 reg, __le32 bits)
168	{
169	int i;
cd8d3d32 CL	170
cd8d3d32 CL	171	for (i = 0; i < 2000; i++) {
87cbfd06	172	__le32 buffer = p54spi_read32(priv, reg);
f74d0f5c	173	if ((buffer & bits) == bits)
cd8d3d32	174	return 1;
cd8d3d32 CL	175	}
	176	return 0;
	177	}
	178
4f5cab96 MF	179	static int p54spi_spi_write_dma(struct p54s_priv *priv, __le32 base,
	180	const void *buf, size_t len)
	181	{
87cbfd06 MF	182	if (!p54spi_wait_bit(priv, SPI_ADRS_DMA_WRITE_CTRL,
87cbfd06 MF	183	cpu_to_le32(HOST_ALLOWED))) {
4f5cab96	184	dev_err(&priv->spi->dev, "spi_write_dma not allowed "
87cbfd06	185	"to DMA write.\n");
4f5cab96 MF	186	return -EAGAIN;
	187	}
	188
210dd1bb MF	189	p54spi_write16(priv, SPI_ADRS_DMA_WRITE_CTRL,
	190	cpu_to_le16(SPI_DMA_WRITE_CTRL_ENABLE));
	191
4f5cab96 MF	192	p54spi_write16(priv, SPI_ADRS_DMA_WRITE_LEN, cpu_to_le16(len));
	193	p54spi_write32(priv, SPI_ADRS_DMA_WRITE_BASE, base);
	194	p54spi_spi_write(priv, SPI_ADRS_DMA_DATA, buf, len);
	195	return 0;
	196	}
	197
cd8d3d32 CL	198	static int p54spi_request_firmware(struct ieee80211_hw *dev)
	199	{
	200	struct p54s_priv *priv = dev->priv;
	201	int ret;
	202
	203	/* FIXME: should driver use it's own struct device? */
	204	ret = request_firmware(&priv->firmware, "3826.arm", &priv->spi->dev);
	205
	206	if (ret < 0) {
	207	dev_err(&priv->spi->dev, "request_firmware() failed: %d", ret);
	208	return ret;
	209	}
	210
	211	ret = p54_parse_firmware(dev, priv->firmware);
	212	if (ret) {
	213	release_firmware(priv->firmware);
	214	return ret;
	215	}
	216
	217	return 0;
	218	}
	219
	220	static int p54spi_request_eeprom(struct ieee80211_hw *dev)
	221	{
	222	struct p54s_priv *priv = dev->priv;
	223	const struct firmware *eeprom;
	224	int ret;
	225
	226	/*
	227	* allow users to customize their eeprom.
	228	*/
	229
	230	ret = request_firmware(&eeprom, "3826.eeprom", &priv->spi->dev);
	231	if (ret < 0) {
	232	dev_info(&priv->spi->dev, "loading default eeprom...\n");
	233	ret = p54_parse_eeprom(dev, (void *) p54spi_eeprom,
	234	sizeof(p54spi_eeprom));
	235	} else {
	236	dev_info(&priv->spi->dev, "loading user eeprom...\n");
	237	ret = p54_parse_eeprom(dev, (void *) eeprom->data,
	238	(int)eeprom->size);
	239	release_firmware(eeprom);
	240	}
	241	return ret;
	242	}
	243
	244	static int p54spi_upload_firmware(struct ieee80211_hw *dev)
	245	{
	246	struct p54s_priv *priv = dev->priv;
5e3af1d2 MF	247	unsigned long fw_len, _fw_len;
	248	unsigned int offset = 0;
	249	int err = 0;
	250	u8 *fw;
	251
	252	fw_len = priv->firmware->size;
	253	fw = kmemdup(priv->firmware->data, fw_len, GFP_KERNEL);
	254	if (!fw)
	255	return -ENOMEM;
cd8d3d32 CL	256
	257	/* stop the device */
	258	p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
	259	SPI_CTRL_STAT_HOST_OVERRIDE \| SPI_CTRL_STAT_HOST_RESET \|
	260	SPI_CTRL_STAT_START_HALTED));
	261
	262	msleep(TARGET_BOOT_SLEEP);
	263
	264	p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
	265	SPI_CTRL_STAT_HOST_OVERRIDE \|
	266	SPI_CTRL_STAT_START_HALTED));
	267
	268	msleep(TARGET_BOOT_SLEEP);
	269
cd8d3d32 CL	270	while (fw_len > 0) {
	271	_fw_len = min_t(long, fw_len, SPI_MAX_PACKET_SIZE);
	272
4f5cab96 MF	273	err = p54spi_spi_write_dma(priv, cpu_to_le32(
	274	ISL38XX_DEV_FIRMWARE_ADDR + offset),
	275	(fw + offset), _fw_len);
	276	if (err < 0)
5e3af1d2	277	goto out;
cd8d3d32 CL	278
cd8d3d32 CL	279	fw_len -= _fw_len;
5e3af1d2	280	offset += _fw_len;
cd8d3d32 CL	281	}
	282
	283	BUG_ON(fw_len != 0);
	284
	285	/* enable host interrupts */
	286	p54spi_write32(priv, SPI_ADRS_HOST_INT_EN,
	287	cpu_to_le32(SPI_HOST_INTS_DEFAULT));
	288
	289	/* boot the device */
	290	p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
	291	SPI_CTRL_STAT_HOST_OVERRIDE \| SPI_CTRL_STAT_HOST_RESET \|
	292	SPI_CTRL_STAT_RAM_BOOT));
	293
	294	msleep(TARGET_BOOT_SLEEP);
	295
	296	p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
	297	SPI_CTRL_STAT_HOST_OVERRIDE \| SPI_CTRL_STAT_RAM_BOOT));
	298	msleep(TARGET_BOOT_SLEEP);
5e3af1d2 MF	299
	300	out:
	301	kfree(fw);
	302	return err;
cd8d3d32 CL	303	}
	304
	305	static void p54spi_power_off(struct p54s_priv *priv)
	306	{
a2116993 CL	307	disable_irq(gpio_to_irq(p54spi_gpio_irq));
a2116993 CL	308	gpio_set_value(p54spi_gpio_power, 0);
cd8d3d32 CL	309	}
	310
	311	static void p54spi_power_on(struct p54s_priv *priv)
	312	{
a2116993 CL	313	gpio_set_value(p54spi_gpio_power, 1);
a2116993 CL	314	enable_irq(gpio_to_irq(p54spi_gpio_irq));
cd8d3d32 CL	315
	316	/*
	317	* need to wait a while before device can be accessed, the lenght
	318	* is just a guess
	319	*/
	320	msleep(10);
	321	}
	322
	323	static inline void p54spi_int_ack(struct p54s_priv *priv, u32 val)
	324	{
	325	p54spi_write32(priv, SPI_ADRS_HOST_INT_ACK, cpu_to_le32(val));
	326	}
	327
465b6353	328	static int p54spi_wakeup(struct p54s_priv *priv)
cd8d3d32	329	{
cd8d3d32 CL	330	/* wake the chip */
	331	p54spi_write32(priv, SPI_ADRS_ARM_INTERRUPTS,
	332	cpu_to_le32(SPI_TARGET_INT_WAKEUP));
	333
	334	/* And wait for the READY interrupt */
87cbfd06 MF	335	if (!p54spi_wait_bit(priv, SPI_ADRS_HOST_INTERRUPTS,
	336	cpu_to_le32(SPI_HOST_INT_READY))) {
	337	dev_err(&priv->spi->dev, "INT_READY timeout\n");
465b6353	338	return -EBUSY;
cd8d3d32 CL	339	}
	340
	341	p54spi_int_ack(priv, SPI_HOST_INT_READY);
465b6353	342	return 0;
cd8d3d32 CL	343	}
	344
	345	static inline void p54spi_sleep(struct p54s_priv *priv)
	346	{
	347	p54spi_write32(priv, SPI_ADRS_ARM_INTERRUPTS,
	348	cpu_to_le32(SPI_TARGET_INT_SLEEP));
	349	}
	350
	351	static void p54spi_int_ready(struct p54s_priv *priv)
	352	{
	353	p54spi_write32(priv, SPI_ADRS_HOST_INT_EN, cpu_to_le32(
	354	SPI_HOST_INT_UPDATE \| SPI_HOST_INT_SW_UPDATE));
	355
	356	switch (priv->fw_state) {
	357	case FW_STATE_BOOTING:
	358	priv->fw_state = FW_STATE_READY;
	359	complete(&priv->fw_comp);
	360	break;
	361	case FW_STATE_RESETTING:
	362	priv->fw_state = FW_STATE_READY;
	363	/* TODO: reinitialize state */
	364	break;
	365	default:
	366	break;
	367	}
	368	}
	369
	370	static int p54spi_rx(struct p54s_priv *priv)
	371	{
	372	struct sk_buff *skb;
	373	u16 len;
	374
465b6353 MF	375	if (p54spi_wakeup(priv) < 0)
465b6353 MF	376	return -EBUSY;
cd8d3d32 CL	377
	378	/* dummy read to flush SPI DMA controller bug */
	379	p54spi_read16(priv, SPI_ADRS_GEN_PURP_1);
	380
	381	len = p54spi_read16(priv, SPI_ADRS_DMA_DATA);
	382
	383	if (len == 0) {
	384	dev_err(&priv->spi->dev, "rx request of zero bytes");
	385	return 0;
	386	}
	387
9f201a87 MF	388
	389	/* Firmware may insert up to 4 padding bytes after the lmac header,
	390	* but it does not amend the size of SPI data transfer.
	391	* Such packets has correct data size in header, thus referencing
	392	* past the end of allocated skb. Reserve extra 4 bytes for this case */
	393	skb = dev_alloc_skb(len + 4);
cd8d3d32 CL	394	if (!skb) {
	395	dev_err(&priv->spi->dev, "could not alloc skb");
	396	return 0;
	397	}
	398
	399	p54spi_spi_read(priv, SPI_ADRS_DMA_DATA, skb_put(skb, len), len);
	400	p54spi_sleep(priv);
9f201a87 MF	401	/* Put additional bytes to compensate for the possible
	402	* alignment-caused truncation */
	403	skb_put(skb, 4);
cd8d3d32 CL	404
	405	if (p54_rx(priv->hw, skb) == 0)
	406	dev_kfree_skb(skb);
	407
	408	return 0;
	409	}
	410
	411
	412	static irqreturn_t p54spi_interrupt(int irq, void *config)
	413	{
	414	struct spi_device *spi = config;
	415	struct p54s_priv *priv = dev_get_drvdata(&spi->dev);
	416
	417	queue_work(priv->hw->workqueue, &priv->work);
	418
	419	return IRQ_HANDLED;
	420	}
	421
	422	static int p54spi_tx_frame(struct p54s_priv priv, struct sk_buff skb)
	423	{
	424	struct p54_hdr hdr = (struct p54_hdr ) skb->data;
cd8d3d32	425	int ret = 0;
cd8d3d32	426
465b6353 MF	427	if (p54spi_wakeup(priv) < 0)
465b6353 MF	428	return -EBUSY;
cd8d3d32	429
4f5cab96 MF	430	ret = p54spi_spi_write_dma(priv, hdr->req_id, skb->data, skb->len);
	431	if (ret < 0)
	432	goto out;
cd8d3d32	433
87cbfd06 MF	434	if (!p54spi_wait_bit(priv, SPI_ADRS_HOST_INTERRUPTS,
	435	cpu_to_le32(SPI_HOST_INT_WR_READY))) {
	436	dev_err(&priv->spi->dev, "WR_READY timeout\n");
6edf534a	437	ret = -EAGAIN;
87cbfd06	438	goto out;
cd8d3d32 CL	439	}
	440
	441	p54spi_int_ack(priv, SPI_HOST_INT_WR_READY);
cd8d3d32	442
cd8d3d32 CL	443	if (FREE_AFTER_TX(skb))
cd8d3d32 CL	444	p54_free_skb(priv->hw, skb);
4f5cab96	445	out:
6edf534a	446	p54spi_sleep(priv);
cd8d3d32 CL	447	return ret;
	448	}
	449
	450	static int p54spi_wq_tx(struct p54s_priv *priv)
	451	{
	452	struct p54s_tx_info *entry;
	453	struct sk_buff *skb;
	454	struct ieee80211_tx_info *info;
	455	struct p54_tx_info *minfo;
	456	struct p54s_tx_info *dinfo;
731c6531	457	unsigned long flags;
cd8d3d32 CL	458	int ret = 0;
cd8d3d32 CL	459
731c6531	460	spin_lock_irqsave(&priv->tx_lock, flags);
cd8d3d32 CL	461
	462	while (!list_empty(&priv->tx_pending)) {
	463	entry = list_entry(priv->tx_pending.next,
	464	struct p54s_tx_info, tx_list);
	465
	466	list_del_init(&entry->tx_list);
	467
731c6531	468	spin_unlock_irqrestore(&priv->tx_lock, flags);
cd8d3d32 CL	469
	470	dinfo = container_of((void *) entry, struct p54s_tx_info,
	471	tx_list);
	472	minfo = container_of((void *) dinfo, struct p54_tx_info,
	473	data);
	474	info = container_of((void *) minfo, struct ieee80211_tx_info,
	475	rate_driver_data);
	476	skb = container_of((void *) info, struct sk_buff, cb);
	477
	478	ret = p54spi_tx_frame(priv, skb);
	479
cd8d3d32 CL	480	if (ret < 0) {
cd8d3d32 CL	481	p54_free_skb(priv->hw, skb);
731c6531	482	return ret;
cd8d3d32	483	}
cd8d3d32	484
731c6531 CL	485	spin_lock_irqsave(&priv->tx_lock, flags);
	486	}
	487	spin_unlock_irqrestore(&priv->tx_lock, flags);
cd8d3d32 CL	488	return ret;
	489	}
	490
	491	static void p54spi_op_tx(struct ieee80211_hw dev, struct sk_buff skb)
	492	{
	493	struct p54s_priv *priv = dev->priv;
	494	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
	495	struct p54_tx_info mi = (struct p54_tx_info ) info->rate_driver_data;
	496	struct p54s_tx_info di = (struct p54s_tx_info ) mi->data;
731c6531	497	unsigned long flags;
cd8d3d32 CL	498
	499	BUILD_BUG_ON(sizeof(*di) > sizeof((mi->data)));
	500
731c6531	501	spin_lock_irqsave(&priv->tx_lock, flags);
cd8d3d32	502	list_add_tail(&di->tx_list, &priv->tx_pending);
731c6531	503	spin_unlock_irqrestore(&priv->tx_lock, flags);
cd8d3d32 CL	504
	505	queue_work(priv->hw->workqueue, &priv->work);
	506	}
	507
	508	static void p54spi_work(struct work_struct *work)
	509	{
	510	struct p54s_priv *priv = container_of(work, struct p54s_priv, work);
	511	u32 ints;
	512	int ret;
	513
	514	mutex_lock(&priv->mutex);
	515
	516	if (priv->fw_state == FW_STATE_OFF &&
	517	priv->fw_state == FW_STATE_RESET)
	518	goto out;
	519
	520	ints = p54spi_read32(priv, SPI_ADRS_HOST_INTERRUPTS);
	521
	522	if (ints & SPI_HOST_INT_READY) {
	523	p54spi_int_ready(priv);
	524	p54spi_int_ack(priv, SPI_HOST_INT_READY);
	525	}
	526
	527	if (priv->fw_state != FW_STATE_READY)
	528	goto out;
	529
	530	if (ints & SPI_HOST_INT_UPDATE) {
	531	p54spi_int_ack(priv, SPI_HOST_INT_UPDATE);
	532	ret = p54spi_rx(priv);
	533	if (ret < 0)
	534	goto out;
	535	}
	536	if (ints & SPI_HOST_INT_SW_UPDATE) {
	537	p54spi_int_ack(priv, SPI_HOST_INT_SW_UPDATE);
	538	ret = p54spi_rx(priv);
	539	if (ret < 0)
	540	goto out;
	541	}
	542
	543	ret = p54spi_wq_tx(priv);
cd8d3d32 CL	544	out:
	545	mutex_unlock(&priv->mutex);
	546	}
	547
	548	static int p54spi_op_start(struct ieee80211_hw *dev)
	549	{
	550	struct p54s_priv *priv = dev->priv;
	551	unsigned long timeout;
	552	int ret = 0;
	553
	554	if (mutex_lock_interruptible(&priv->mutex)) {
	555	ret = -EINTR;
	556	goto out;
	557	}
	558
	559	priv->fw_state = FW_STATE_BOOTING;
	560
	561	p54spi_power_on(priv);
	562
	563	ret = p54spi_upload_firmware(dev);
	564	if (ret < 0) {
	565	p54spi_power_off(priv);
	566	goto out_unlock;
	567	}
	568
	569	mutex_unlock(&priv->mutex);
	570
	571	timeout = msecs_to_jiffies(2000);
	572	timeout = wait_for_completion_interruptible_timeout(&priv->fw_comp,
	573	timeout);
	574	if (!timeout) {
	575	dev_err(&priv->spi->dev, "firmware boot failed");
	576	p54spi_power_off(priv);
	577	ret = -1;
	578	goto out;
	579	}
	580
	581	if (mutex_lock_interruptible(&priv->mutex)) {
	582	ret = -EINTR;
	583	p54spi_power_off(priv);
	584	goto out;
	585	}
	586
	587	WARN_ON(priv->fw_state != FW_STATE_READY);
	588
	589	out_unlock:
	590	mutex_unlock(&priv->mutex);
	591
	592	out:
	593	return ret;
	594	}
	595
	596	static void p54spi_op_stop(struct ieee80211_hw *dev)
	597	{
	598	struct p54s_priv *priv = dev->priv;
731c6531	599	unsigned long flags;
cd8d3d32 CL	600
	601	if (mutex_lock_interruptible(&priv->mutex)) {
	602	/* FIXME: how to handle this error? */
	603	return;
	604	}
	605
	606	WARN_ON(priv->fw_state != FW_STATE_READY);
	607
	608	cancel_work_sync(&priv->work);
	609
	610	p54spi_power_off(priv);
731c6531	611	spin_lock_irqsave(&priv->tx_lock, flags);
cd8d3d32	612	INIT_LIST_HEAD(&priv->tx_pending);
731c6531	613	spin_unlock_irqrestore(&priv->tx_lock, flags);
cd8d3d32 CL	614
	615	priv->fw_state = FW_STATE_OFF;
	616	mutex_unlock(&priv->mutex);
	617	}
	618
	619	static int __devinit p54spi_probe(struct spi_device *spi)
	620	{
	621	struct p54s_priv *priv = NULL;
	622	struct ieee80211_hw *hw;
	623	int ret = -EINVAL;
	624
	625	hw = p54_init_common(sizeof(*priv));
	626	if (!hw) {
	627	dev_err(&priv->spi->dev, "could not alloc ieee80211_hw");
	628	return -ENOMEM;
	629	}
	630
	631	priv = hw->priv;
	632	priv->hw = hw;
	633	dev_set_drvdata(&spi->dev, priv);
	634	priv->spi = spi;
	635
cd8d3d32 CL	636	spi->bits_per_word = 16;
	637	spi->max_speed_hz = 24000000;
	638
	639	ret = spi_setup(spi);
	640	if (ret < 0) {
	641	dev_err(&priv->spi->dev, "spi_setup failed");
	642	goto err_free_common;
	643	}
	644
a2116993	645	ret = gpio_request(p54spi_gpio_power, "p54spi power");
cd8d3d32 CL	646	if (ret < 0) {
	647	dev_err(&priv->spi->dev, "power GPIO request failed: %d", ret);
	648	goto err_free_common;
	649	}
	650
a2116993	651	ret = gpio_request(p54spi_gpio_irq, "p54spi irq");
cd8d3d32 CL	652	if (ret < 0) {
	653	dev_err(&priv->spi->dev, "irq GPIO request failed: %d", ret);
	654	goto err_free_common;
	655	}
	656
a2116993 CL	657	gpio_direction_output(p54spi_gpio_power, 0);
a2116993 CL	658	gpio_direction_input(p54spi_gpio_irq);
cd8d3d32	659
a2116993	660	ret = request_irq(gpio_to_irq(p54spi_gpio_irq),
cd8d3d32 CL	661	p54spi_interrupt, IRQF_DISABLED, "p54spi",
	662	priv->spi);
	663	if (ret < 0) {
	664	dev_err(&priv->spi->dev, "request_irq() failed");
	665	goto err_free_common;
	666	}
	667
a2116993	668	set_irq_type(gpio_to_irq(p54spi_gpio_irq),
cd8d3d32 CL	669	IRQ_TYPE_EDGE_RISING);
cd8d3d32 CL	670
a2116993	671	disable_irq(gpio_to_irq(p54spi_gpio_irq));
cd8d3d32 CL	672
	673	INIT_WORK(&priv->work, p54spi_work);
	674	init_completion(&priv->fw_comp);
	675	INIT_LIST_HEAD(&priv->tx_pending);
	676	mutex_init(&priv->mutex);
	677	SET_IEEE80211_DEV(hw, &spi->dev);
	678	priv->common.open = p54spi_op_start;
	679	priv->common.stop = p54spi_op_stop;
	680	priv->common.tx = p54spi_op_tx;
	681
	682	ret = p54spi_request_firmware(hw);
	683	if (ret < 0)
	684	goto err_free_common;
	685
	686	ret = p54spi_request_eeprom(hw);
	687	if (ret)
	688	goto err_free_common;
	689
2ac71072 CL	690	ret = p54_register_common(hw, &priv->spi->dev);
2ac71072 CL	691	if (ret)
cd8d3d32	692	goto err_free_common;
cd8d3d32	693
cd8d3d32 CL	694	return 0;
	695
	696	err_free_common:
	697	p54_free_common(priv->hw);
	698	return ret;
	699	}
	700
	701	static int __devexit p54spi_remove(struct spi_device *spi)
	702	{
	703	struct p54s_priv *priv = dev_get_drvdata(&spi->dev);
	704
	705	ieee80211_unregister_hw(priv->hw);
	706
a2116993	707	free_irq(gpio_to_irq(p54spi_gpio_irq), spi);
cd8d3d32	708
a2116993 CL	709	gpio_free(p54spi_gpio_power);
a2116993 CL	710	gpio_free(p54spi_gpio_irq);
cd8d3d32 CL	711	release_firmware(priv->firmware);
	712
	713	mutex_destroy(&priv->mutex);
	714
	715	p54_free_common(priv->hw);
	716	ieee80211_free_hw(priv->hw);
	717
	718	return 0;
	719	}
	720
	721
	722	static struct spi_driver p54spi_driver = {
	723	.driver = {
	724	/* use cx3110x name because board-n800.c uses that for the
	725	* SPI port */
	726	.name = "cx3110x",
	727	.bus = &spi_bus_type,
	728	.owner = THIS_MODULE,
	729	},
	730
	731	.probe = p54spi_probe,
	732	.remove = __devexit_p(p54spi_remove),
	733	};
	734
	735	static int __init p54spi_init(void)
	736	{
	737	int ret;
	738
	739	ret = spi_register_driver(&p54spi_driver);
	740	if (ret < 0) {
	741	printk(KERN_ERR "failed to register SPI driver: %d", ret);
	742	goto out;
	743	}
	744
	745	out:
	746	return ret;
	747	}
	748
	749	static void __exit p54spi_exit(void)
	750	{
	751	spi_unregister_driver(&p54spi_driver);
	752	}
	753
	754	module_init(p54spi_init);
	755	module_exit(p54spi_exit);
	756
	757	MODULE_LICENSE("GPL");
	758	MODULE_AUTHOR("Christian Lamparter <chunkeey@web.de>");