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rtl8xxxu: Do LC calibration before IQK calibration
[deliverable/linux.git] / drivers / net / wireless / realtek / rtl8xxxu / rtl8xxxu.c
CommitLineData
26f1fad2
JS		 1/*
2 * RTL8XXXU mac80211 USB driver
3 *
4 * Copyright (c) 2014 - 2015 Jes Sorensen <Jes.Sorensen@redhat.com>
5 *
6 * Portions, notably calibration code:
7 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
8 *
9 * This driver was written as a replacement for the vendor provided
10 * rtl8723au driver. As the Realtek 8xxx chips are very similar in
11 * their programming interface, I have started adding support for
12 * additional 8xxx chips like the 8192cu, 8188cus, etc.
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of version 2 of the GNU General Public License as
16 * published by the Free Software Foundation.
17 *
18 * This program is distributed in the hope that it will be useful, but WITHOUT
19 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 * more details.
22 */
23
24#include <linux/init.h>
25#include <linux/kernel.h>
26#include <linux/sched.h>
27#include <linux/errno.h>
28#include <linux/slab.h>
29#include <linux/module.h>
30#include <linux/spinlock.h>
31#include <linux/list.h>
32#include <linux/usb.h>
33#include <linux/netdevice.h>
34#include <linux/etherdevice.h>
35#include <linux/ethtool.h>
36#include <linux/wireless.h>
37#include <linux/firmware.h>
38#include <linux/moduleparam.h>
39#include <net/mac80211.h>
40#include "rtl8xxxu.h"
41#include "rtl8xxxu_regs.h"
42
43#define DRIVER_NAME "rtl8xxxu"
44
3307d840 45static int rtl8xxxu_debug = RTL8XXXU_DEBUG_EFUSE;
26f1fad2
JS		 46static bool rtl8xxxu_ht40_2g;
47
48MODULE_AUTHOR("Jes Sorensen <Jes.Sorensen@redhat.com>");
49MODULE_DESCRIPTION("RTL8XXXu USB mac80211 Wireless LAN Driver");
50MODULE_LICENSE("GPL");
51MODULE_FIRMWARE("rtlwifi/rtl8723aufw_A.bin");
52MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B.bin");
53MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B_NoBT.bin");
54MODULE_FIRMWARE("rtlwifi/rtl8192cufw_A.bin");
55MODULE_FIRMWARE("rtlwifi/rtl8192cufw_B.bin");
56MODULE_FIRMWARE("rtlwifi/rtl8192cufw_TMSC.bin");
b001e086 57MODULE_FIRMWARE("rtlwifi/rtl8192eu_nic.bin");
35a741fe
JS		 58MODULE_FIRMWARE("rtlwifi/rtl8723bu_nic.bin");
59MODULE_FIRMWARE("rtlwifi/rtl8723bu_bt.bin");
26f1fad2
JS		 60
61module_param_named(debug, rtl8xxxu_debug, int, 0600);
62MODULE_PARM_DESC(debug, "Set debug mask");
63module_param_named(ht40_2g, rtl8xxxu_ht40_2g, bool, 0600);
64MODULE_PARM_DESC(ht40_2g, "Enable HT40 support on the 2.4GHz band");
65
66#define USB_VENDOR_ID_REALTEK 0x0bda
67/* Minimum IEEE80211_MAX_FRAME_LEN */
68#define RTL_RX_BUFFER_SIZE IEEE80211_MAX_FRAME_LEN
69#define RTL8XXXU_RX_URBS 32
70#define RTL8XXXU_RX_URB_PENDING_WATER 8
71#define RTL8XXXU_TX_URBS 64
72#define RTL8XXXU_TX_URB_LOW_WATER 25
73#define RTL8XXXU_TX_URB_HIGH_WATER 32
74
75static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
76 struct rtl8xxxu_rx_urb *rx_urb);
77
78static struct ieee80211_rate rtl8xxxu_rates[] = {
79 { .bitrate = 10, .hw_value = DESC_RATE_1M, .flags = 0 },
80 { .bitrate = 20, .hw_value = DESC_RATE_2M, .flags = 0 },
81 { .bitrate = 55, .hw_value = DESC_RATE_5_5M, .flags = 0 },
82 { .bitrate = 110, .hw_value = DESC_RATE_11M, .flags = 0 },
83 { .bitrate = 60, .hw_value = DESC_RATE_6M, .flags = 0 },
84 { .bitrate = 90, .hw_value = DESC_RATE_9M, .flags = 0 },
85 { .bitrate = 120, .hw_value = DESC_RATE_12M, .flags = 0 },
86 { .bitrate = 180, .hw_value = DESC_RATE_18M, .flags = 0 },
87 { .bitrate = 240, .hw_value = DESC_RATE_24M, .flags = 0 },
88 { .bitrate = 360, .hw_value = DESC_RATE_36M, .flags = 0 },
89 { .bitrate = 480, .hw_value = DESC_RATE_48M, .flags = 0 },
90 { .bitrate = 540, .hw_value = DESC_RATE_54M, .flags = 0 },
91};
92
93static struct ieee80211_channel rtl8xxxu_channels_2g[] = {
94 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2412,
95 .hw_value = 1, .max_power = 30 },
96 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2417,
97 .hw_value = 2, .max_power = 30 },
98 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2422,
99 .hw_value = 3, .max_power = 30 },
100 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2427,
101 .hw_value = 4, .max_power = 30 },
102 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2432,
103 .hw_value = 5, .max_power = 30 },
104 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2437,
105 .hw_value = 6, .max_power = 30 },
106 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2442,
107 .hw_value = 7, .max_power = 30 },
108 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2447,
109 .hw_value = 8, .max_power = 30 },
110 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2452,
111 .hw_value = 9, .max_power = 30 },
112 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2457,
113 .hw_value = 10, .max_power = 30 },
114 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2462,
115 .hw_value = 11, .max_power = 30 },
116 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2467,
117 .hw_value = 12, .max_power = 30 },
118 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2472,
119 .hw_value = 13, .max_power = 30 },
120 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2484,
121 .hw_value = 14, .max_power = 30 }
122};
123
124static struct ieee80211_supported_band rtl8xxxu_supported_band = {
125 .channels = rtl8xxxu_channels_2g,
126 .n_channels = ARRAY_SIZE(rtl8xxxu_channels_2g),
127 .bitrates = rtl8xxxu_rates,
128 .n_bitrates = ARRAY_SIZE(rtl8xxxu_rates),
129};
130
131static struct rtl8xxxu_reg8val rtl8723a_mac_init_table[] = {
132 {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00},
133 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
134 {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00},
135 {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05},
136 {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01},
137 {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f},
138 {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72},
139 {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08},
140 {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
141 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
142 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
143 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
144 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
145 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
146 {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16},
147 {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00},
148 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02},
149 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
150 {0x652, 0x20}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
151 {0x63f, 0x0e}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
152 {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
153 {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff},
154};
155
b7dd8ff9
JS		 156static struct rtl8xxxu_reg8val rtl8723b_mac_init_table[] = {
157 {0x02f, 0x30}, {0x035, 0x00}, {0x039, 0x08}, {0x04e, 0xe0},
158 {0x064, 0x00}, {0x067, 0x20}, {0x428, 0x0a}, {0x429, 0x10},
159 {0x430, 0x00}, {0x431, 0x00},
160 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
161 {0x436, 0x07}, {0x437, 0x08}, {0x43c, 0x04}, {0x43d, 0x05},
162 {0x43e, 0x07}, {0x43f, 0x08}, {0x440, 0x5d}, {0x441, 0x01},
163 {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, {0x446, 0x00},
164 {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xf0}, {0x44a, 0x0f},
165 {0x44b, 0x3e}, {0x44c, 0x10}, {0x44d, 0x00}, {0x44e, 0x00},
166 {0x44f, 0x00}, {0x450, 0x00}, {0x451, 0xf0}, {0x452, 0x0f},
167 {0x453, 0x00}, {0x456, 0x5e}, {0x460, 0x66}, {0x461, 0x66},
168 {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
169 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
170 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
171 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
172 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
173 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
174 {0x516, 0x0a}, {0x525, 0x4f},
175 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55c, 0x50},
176 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
177 {0x620, 0xff}, {0x621, 0xff}, {0x622, 0xff}, {0x623, 0xff},
178 {0x624, 0xff}, {0x625, 0xff}, {0x626, 0xff}, {0x627, 0xff},
179 {0x638, 0x50}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
180 {0x63f, 0x0e}, {0x640, 0x40}, {0x642, 0x40}, {0x643, 0x00},
181 {0x652, 0xc8}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
182 {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
183 {0x70a, 0x65}, {0x70b, 0x87}, {0x765, 0x18}, {0x76e, 0x04},
184 {0xffff, 0xff},
185};
186
26f1fad2
JS		 187static struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table[] = {
188 {0x800, 0x80040000}, {0x804, 0x00000003},
189 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
190 {0x810, 0x10001331}, {0x814, 0x020c3d10},
191 {0x818, 0x02200385}, {0x81c, 0x00000000},
192 {0x820, 0x01000100}, {0x824, 0x00390004},
193 {0x828, 0x00000000}, {0x82c, 0x00000000},
194 {0x830, 0x00000000}, {0x834, 0x00000000},
195 {0x838, 0x00000000}, {0x83c, 0x00000000},
196 {0x840, 0x00010000}, {0x844, 0x00000000},
197 {0x848, 0x00000000}, {0x84c, 0x00000000},
198 {0x850, 0x00000000}, {0x854, 0x00000000},
199 {0x858, 0x569a569a}, {0x85c, 0x001b25a4},
200 {0x860, 0x66f60110}, {0x864, 0x061f0130},
201 {0x868, 0x00000000}, {0x86c, 0x32323200},
202 {0x870, 0x07000760}, {0x874, 0x22004000},
203 {0x878, 0x00000808}, {0x87c, 0x00000000},
204 {0x880, 0xc0083070}, {0x884, 0x000004d5},
205 {0x888, 0x00000000}, {0x88c, 0xccc000c0},
206 {0x890, 0x00000800}, {0x894, 0xfffffffe},
207 {0x898, 0x40302010}, {0x89c, 0x00706050},
208 {0x900, 0x00000000}, {0x904, 0x00000023},
209 {0x908, 0x00000000}, {0x90c, 0x81121111},
210 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
211 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
212 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
213 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
214 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
215 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
216 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
217 {0xa78, 0x00000900},
218 {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
219 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
220 {0xc10, 0x08800000}, {0xc14, 0x40000100},
221 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
222 {0xc20, 0x00000000}, {0xc24, 0x00000000},
223 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
224 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
225 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
226 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
227 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
228 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
229 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
230 {0xc60, 0x00000000}, {0xc64, 0x7112848b},
231 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
232 {0xc70, 0x2c7f000d}, {0xc74, 0x018610db},
233 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
234 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
235 {0xc88, 0x40000100}, {0xc8c, 0x20200000},
236 {0xc90, 0x00121820}, {0xc94, 0x00000000},
237 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
238 {0xca0, 0x00000000}, {0xca4, 0x00000080},
239 {0xca8, 0x00000000}, {0xcac, 0x00000000},
240 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
241 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
242 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
243 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
244 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
245 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
246 {0xce0, 0x00222222}, {0xce4, 0x00000000},
247 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
248 {0xd00, 0x00080740}, {0xd04, 0x00020401},
249 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
250 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
251 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
252 {0xd30, 0x00000000}, {0xd34, 0x80608000},
253 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
254 {0xd40, 0x00000000}, {0xd44, 0x00000000},
255 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
256 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
257 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
258 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
259 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
260 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
261 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
262 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
263 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
264 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
265 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
266 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
267 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
268 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
269 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
270 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
271 {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
272 {0xe68, 0x001b25a4}, {0xe6c, 0x631b25a0},
273 {0xe70, 0x631b25a0}, {0xe74, 0x081b25a0},
274 {0xe78, 0x081b25a0}, {0xe7c, 0x081b25a0},
275 {0xe80, 0x081b25a0}, {0xe84, 0x631b25a0},
276 {0xe88, 0x081b25a0}, {0xe8c, 0x631b25a0},
277 {0xed0, 0x631b25a0}, {0xed4, 0x631b25a0},
278 {0xed8, 0x631b25a0}, {0xedc, 0x001b25a0},
279 {0xee0, 0x001b25a0}, {0xeec, 0x6b1b25a0},
280 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
281 {0xf00, 0x00000300},
282 {0xffff, 0xffffffff},
283};
284
36c32588
JS		 285static struct rtl8xxxu_reg32val rtl8723b_phy_1t_init_table[] = {
286 {0x800, 0x80040000}, {0x804, 0x00000003},
287 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
288 {0x810, 0x10001331}, {0x814, 0x020c3d10},
289 {0x818, 0x02200385}, {0x81c, 0x00000000},
290 {0x820, 0x01000100}, {0x824, 0x00190204},
291 {0x828, 0x00000000}, {0x82c, 0x00000000},
292 {0x830, 0x00000000}, {0x834, 0x00000000},
293 {0x838, 0x00000000}, {0x83c, 0x00000000},
294 {0x840, 0x00010000}, {0x844, 0x00000000},
295 {0x848, 0x00000000}, {0x84c, 0x00000000},
296 {0x850, 0x00000000}, {0x854, 0x00000000},
297 {0x858, 0x569a11a9}, {0x85c, 0x01000014},
298 {0x860, 0x66f60110}, {0x864, 0x061f0649},
299 {0x868, 0x00000000}, {0x86c, 0x27272700},
300 {0x870, 0x07000760}, {0x874, 0x25004000},
301 {0x878, 0x00000808}, {0x87c, 0x00000000},
302 {0x880, 0xb0000c1c}, {0x884, 0x00000001},
303 {0x888, 0x00000000}, {0x88c, 0xccc000c0},
304 {0x890, 0x00000800}, {0x894, 0xfffffffe},
305 {0x898, 0x40302010}, {0x89c, 0x00706050},
306 {0x900, 0x00000000}, {0x904, 0x00000023},
307 {0x908, 0x00000000}, {0x90c, 0x81121111},
308 {0x910, 0x00000002}, {0x914, 0x00000201},
309 {0xa00, 0x00d047c8}, {0xa04, 0x80ff800c},
310 {0xa08, 0x8c838300}, {0xa0c, 0x2e7f120f},
311 {0xa10, 0x9500bb78}, {0xa14, 0x1114d028},
312 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
313 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
314 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
315 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
316 {0xa78, 0x00000900}, {0xa7c, 0x225b0606},
317 {0xa80, 0x21806490}, {0xb2c, 0x00000000},
318 {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
319 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
320 {0xc10, 0x08800000}, {0xc14, 0x40000100},
321 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
322 {0xc20, 0x00000000}, {0xc24, 0x00000000},
323 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
324 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
325 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
326 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
327 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
328 {0xc50, 0x69553420}, {0xc54, 0x43bc0094},
329 {0xc58, 0x00013149}, {0xc5c, 0x00250492},
330 {0xc60, 0x00000000}, {0xc64, 0x7112848b},
331 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
332 {0xc70, 0x2c7f000d}, {0xc74, 0x020610db},
333 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
334 {0xc80, 0x390000e4}, {0xc84, 0x20f60000},
335 {0xc88, 0x40000100}, {0xc8c, 0x20200000},
336 {0xc90, 0x00020e1a}, {0xc94, 0x00000000},
337 {0xc98, 0x00020e1a}, {0xc9c, 0x00007f7f},
338 {0xca0, 0x00000000}, {0xca4, 0x000300a0},
339 {0xca8, 0x00000000}, {0xcac, 0x00000000},
340 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
341 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
342 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
343 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
344 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
345 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
346 {0xce0, 0x00222222}, {0xce4, 0x00000000},
347 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
348 {0xd00, 0x00000740}, {0xd04, 0x40020401},
349 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
350 {0xd10, 0xa0633333}, {0xd14, 0x3333bc53},
351 {0xd18, 0x7a8f5b6f}, {0xd2c, 0xcc979975},
352 {0xd30, 0x00000000}, {0xd34, 0x80608000},
353 {0xd38, 0x00000000}, {0xd3c, 0x00127353},
354 {0xd40, 0x00000000}, {0xd44, 0x00000000},
355 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
356 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
357 {0xd58, 0x00000282}, {0xd5c, 0x30032064},
358 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
359 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
360 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
361 {0xd78, 0x000e3c24}, {0xe00, 0x2d2d2d2d},
362 {0xe04, 0x2d2d2d2d}, {0xe08, 0x0390272d},
363 {0xe10, 0x2d2d2d2d}, {0xe14, 0x2d2d2d2d},
364 {0xe18, 0x2d2d2d2d}, {0xe1c, 0x2d2d2d2d},
365 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
366 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
367 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
368 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
369 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
370 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
371 {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
372 {0xe68, 0x001b2556}, {0xe6c, 0x00c00096},
373 {0xe70, 0x00c00096}, {0xe74, 0x01000056},
374 {0xe78, 0x01000014}, {0xe7c, 0x01000056},
375 {0xe80, 0x01000014}, {0xe84, 0x00c00096},
376 {0xe88, 0x01000056}, {0xe8c, 0x00c00096},
377 {0xed0, 0x00c00096}, {0xed4, 0x00c00096},
378 {0xed8, 0x00c00096}, {0xedc, 0x000000d6},
379 {0xee0, 0x000000d6}, {0xeec, 0x01c00016},
380 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
381 {0xf00, 0x00000300},
382 {0x820, 0x01000100}, {0x800, 0x83040000},
383 {0xffff, 0xffffffff},
384};
385
26f1fad2
JS		 386static struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table[] = {
387 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
388 {0x800, 0x80040002}, {0x804, 0x00000003},
389 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
390 {0x810, 0x10000330}, {0x814, 0x020c3d10},
391 {0x818, 0x02200385}, {0x81c, 0x00000000},
392 {0x820, 0x01000100}, {0x824, 0x00390004},
393 {0x828, 0x01000100}, {0x82c, 0x00390004},
394 {0x830, 0x27272727}, {0x834, 0x27272727},
395 {0x838, 0x27272727}, {0x83c, 0x27272727},
396 {0x840, 0x00010000}, {0x844, 0x00010000},
397 {0x848, 0x27272727}, {0x84c, 0x27272727},
398 {0x850, 0x00000000}, {0x854, 0x00000000},
399 {0x858, 0x569a569a}, {0x85c, 0x0c1b25a4},
400 {0x860, 0x66e60230}, {0x864, 0x061f0130},
401 {0x868, 0x27272727}, {0x86c, 0x2b2b2b27},
402 {0x870, 0x07000700}, {0x874, 0x22184000},
403 {0x878, 0x08080808}, {0x87c, 0x00000000},
404 {0x880, 0xc0083070}, {0x884, 0x000004d5},
405 {0x888, 0x00000000}, {0x88c, 0xcc0000c0},
406 {0x890, 0x00000800}, {0x894, 0xfffffffe},
407 {0x898, 0x40302010}, {0x89c, 0x00706050},
408 {0x900, 0x00000000}, {0x904, 0x00000023},
409 {0x908, 0x00000000}, {0x90c, 0x81121313},
410 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
411 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
412 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
413 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
414 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
415 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
416 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
417 {0xc00, 0x48071d40}, {0xc04, 0x03a05633},
418 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
419 {0xc10, 0x08800000}, {0xc14, 0x40000100},
420 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
421 {0xc20, 0x00000000}, {0xc24, 0x00000000},
422 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
423 {0xc30, 0x69e9ac44}, {0xc34, 0x469652cf},
424 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
425 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
426 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
427 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
428 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
429 {0xc60, 0x00000000}, {0xc64, 0x5116848b},
430 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
431 {0xc70, 0x2c7f000d}, {0xc74, 0x2186115b},
432 {0xc78, 0x0000001f}, {0xc7c, 0x00b99612},
433 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
434 {0xc88, 0x40000100}, {0xc8c, 0xa0e40000},
435 {0xc90, 0x00121820}, {0xc94, 0x00000000},
436 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
437 {0xca0, 0x00000000}, {0xca4, 0x00000080},
438 {0xca8, 0x00000000}, {0xcac, 0x00000000},
439 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
440 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
441 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
442 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
443 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
444 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
445 {0xce0, 0x00222222}, {0xce4, 0x00000000},
446 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
447 {0xd00, 0x00080740}, {0xd04, 0x00020403},
448 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
449 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
450 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
451 {0xd30, 0x00000000}, {0xd34, 0x80608000},
452 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
453 {0xd40, 0x00000000}, {0xd44, 0x00000000},
454 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
455 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
456 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
457 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
458 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
459 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
460 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
461 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
462 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
463 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
464 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
465 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
466 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
467 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
468 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
469 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
470 {0xe5c, 0x28160d05}, {0xe60, 0x00000010},
471 {0xe68, 0x001b25a4}, {0xe6c, 0x63db25a4},
472 {0xe70, 0x63db25a4}, {0xe74, 0x0c1b25a4},
473 {0xe78, 0x0c1b25a4}, {0xe7c, 0x0c1b25a4},
474 {0xe80, 0x0c1b25a4}, {0xe84, 0x63db25a4},
475 {0xe88, 0x0c1b25a4}, {0xe8c, 0x63db25a4},
476 {0xed0, 0x63db25a4}, {0xed4, 0x63db25a4},
477 {0xed8, 0x63db25a4}, {0xedc, 0x001b25a4},
478 {0xee0, 0x001b25a4}, {0xeec, 0x6fdb25a4},
479 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
480 {0xf00, 0x00000300},
481 {0xffff, 0xffffffff},
482};
483
484static struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table[] = {
485 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
486 {0x040, 0x000c0004}, {0x800, 0x80040000},
487 {0x804, 0x00000001}, {0x808, 0x0000fc00},
488 {0x80c, 0x0000000a}, {0x810, 0x10005388},
489 {0x814, 0x020c3d10}, {0x818, 0x02200385},
490 {0x81c, 0x00000000}, {0x820, 0x01000100},
491 {0x824, 0x00390204}, {0x828, 0x00000000},
492 {0x82c, 0x00000000}, {0x830, 0x00000000},
493 {0x834, 0x00000000}, {0x838, 0x00000000},
494 {0x83c, 0x00000000}, {0x840, 0x00010000},
495 {0x844, 0x00000000}, {0x848, 0x00000000},
496 {0x84c, 0x00000000}, {0x850, 0x00000000},
497 {0x854, 0x00000000}, {0x858, 0x569a569a},
498 {0x85c, 0x001b25a4}, {0x860, 0x66e60230},
499 {0x864, 0x061f0130}, {0x868, 0x00000000},
500 {0x86c, 0x20202000}, {0x870, 0x03000300},
501 {0x874, 0x22004000}, {0x878, 0x00000808},
502 {0x87c, 0x00ffc3f1}, {0x880, 0xc0083070},
503 {0x884, 0x000004d5}, {0x888, 0x00000000},
504 {0x88c, 0xccc000c0}, {0x890, 0x00000800},
505 {0x894, 0xfffffffe}, {0x898, 0x40302010},
506 {0x89c, 0x00706050}, {0x900, 0x00000000},
507 {0x904, 0x00000023}, {0x908, 0x00000000},
508 {0x90c, 0x81121111}, {0xa00, 0x00d047c8},
509 {0xa04, 0x80ff000c}, {0xa08, 0x8c838300},
510 {0xa0c, 0x2e68120f}, {0xa10, 0x9500bb78},
511 {0xa14, 0x11144028}, {0xa18, 0x00881117},
512 {0xa1c, 0x89140f00}, {0xa20, 0x15160000},
513 {0xa24, 0x070b0f12}, {0xa28, 0x00000104},
514 {0xa2c, 0x00d30000}, {0xa70, 0x101fbf00},
515 {0xa74, 0x00000007}, {0xc00, 0x48071d40},
516 {0xc04, 0x03a05611}, {0xc08, 0x000000e4},
517 {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000},
518 {0xc14, 0x40000100}, {0xc18, 0x08800000},
519 {0xc1c, 0x40000100}, {0xc20, 0x00000000},
520 {0xc24, 0x00000000}, {0xc28, 0x00000000},
521 {0xc2c, 0x00000000}, {0xc30, 0x69e9ac44},
522 {0xc34, 0x469652cf}, {0xc38, 0x49795994},
523 {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f},
524 {0xc44, 0x000100b7}, {0xc48, 0xec020107},
525 {0xc4c, 0x007f037f}, {0xc50, 0x6954342e},
526 {0xc54, 0x43bc0094}, {0xc58, 0x6954342f},
527 {0xc5c, 0x433c0094}, {0xc60, 0x00000000},
528 {0xc64, 0x5116848b}, {0xc68, 0x47c00bff},
529 {0xc6c, 0x00000036}, {0xc70, 0x2c46000d},
530 {0xc74, 0x018610db}, {0xc78, 0x0000001f},
531 {0xc7c, 0x00b91612}, {0xc80, 0x24000090},
532 {0xc84, 0x20f60000}, {0xc88, 0x24000090},
533 {0xc8c, 0x20200000}, {0xc90, 0x00121820},
534 {0xc94, 0x00000000}, {0xc98, 0x00121820},
535 {0xc9c, 0x00007f7f}, {0xca0, 0x00000000},
536 {0xca4, 0x00000080}, {0xca8, 0x00000000},
537 {0xcac, 0x00000000}, {0xcb0, 0x00000000},
538 {0xcb4, 0x00000000}, {0xcb8, 0x00000000},
539 {0xcbc, 0x28000000}, {0xcc0, 0x00000000},
540 {0xcc4, 0x00000000}, {0xcc8, 0x00000000},
541 {0xccc, 0x00000000}, {0xcd0, 0x00000000},
542 {0xcd4, 0x00000000}, {0xcd8, 0x64b22427},
543 {0xcdc, 0x00766932}, {0xce0, 0x00222222},
544 {0xce4, 0x00000000}, {0xce8, 0x37644302},
545 {0xcec, 0x2f97d40c}, {0xd00, 0x00080740},
546 {0xd04, 0x00020401}, {0xd08, 0x0000907f},
547 {0xd0c, 0x20010201}, {0xd10, 0xa0633333},
548 {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b},
549 {0xd2c, 0xcc979975}, {0xd30, 0x00000000},
550 {0xd34, 0x80608000}, {0xd38, 0x00000000},
551 {0xd3c, 0x00027293}, {0xd40, 0x00000000},
552 {0xd44, 0x00000000}, {0xd48, 0x00000000},
553 {0xd4c, 0x00000000}, {0xd50, 0x6437140a},
554 {0xd54, 0x00000000}, {0xd58, 0x00000000},
555 {0xd5c, 0x30032064}, {0xd60, 0x4653de68},
556 {0xd64, 0x04518a3c}, {0xd68, 0x00002101},
557 {0xd6c, 0x2a201c16}, {0xd70, 0x1812362e},
558 {0xd74, 0x322c2220}, {0xd78, 0x000e3c24},
559 {0xe00, 0x24242424}, {0xe04, 0x24242424},
560 {0xe08, 0x03902024}, {0xe10, 0x24242424},
561 {0xe14, 0x24242424}, {0xe18, 0x24242424},
562 {0xe1c, 0x24242424}, {0xe28, 0x00000000},
563 {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f},
564 {0xe38, 0x02140102}, {0xe3c, 0x681604c2},
565 {0xe40, 0x01007c00}, {0xe44, 0x01004800},
566 {0xe48, 0xfb000000}, {0xe4c, 0x000028d1},
567 {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f},
568 {0xe58, 0x02140102}, {0xe5c, 0x28160d05},
569 {0xe60, 0x00000008}, {0xe68, 0x001b25a4},
570 {0xe6c, 0x631b25a0}, {0xe70, 0x631b25a0},
571 {0xe74, 0x081b25a0}, {0xe78, 0x081b25a0},
572 {0xe7c, 0x081b25a0}, {0xe80, 0x081b25a0},
573 {0xe84, 0x631b25a0}, {0xe88, 0x081b25a0},
574 {0xe8c, 0x631b25a0}, {0xed0, 0x631b25a0},
575 {0xed4, 0x631b25a0}, {0xed8, 0x631b25a0},
576 {0xedc, 0x001b25a0}, {0xee0, 0x001b25a0},
577 {0xeec, 0x6b1b25a0}, {0xee8, 0x31555448},
578 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
579 {0xf00, 0x00000300},
580 {0xffff, 0xffffffff},
581};
582
583static struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table[] = {
584 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
585 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
586 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
587 {0xc78, 0x7a060001}, {0xc78, 0x79070001},
588 {0xc78, 0x78080001}, {0xc78, 0x77090001},
589 {0xc78, 0x760a0001}, {0xc78, 0x750b0001},
590 {0xc78, 0x740c0001}, {0xc78, 0x730d0001},
591 {0xc78, 0x720e0001}, {0xc78, 0x710f0001},
592 {0xc78, 0x70100001}, {0xc78, 0x6f110001},
593 {0xc78, 0x6e120001}, {0xc78, 0x6d130001},
594 {0xc78, 0x6c140001}, {0xc78, 0x6b150001},
595 {0xc78, 0x6a160001}, {0xc78, 0x69170001},
596 {0xc78, 0x68180001}, {0xc78, 0x67190001},
597 {0xc78, 0x661a0001}, {0xc78, 0x651b0001},
598 {0xc78, 0x641c0001}, {0xc78, 0x631d0001},
599 {0xc78, 0x621e0001}, {0xc78, 0x611f0001},
600 {0xc78, 0x60200001}, {0xc78, 0x49210001},
601 {0xc78, 0x48220001}, {0xc78, 0x47230001},
602 {0xc78, 0x46240001}, {0xc78, 0x45250001},
603 {0xc78, 0x44260001}, {0xc78, 0x43270001},
604 {0xc78, 0x42280001}, {0xc78, 0x41290001},
605 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
606 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
607 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
608 {0xc78, 0x21300001}, {0xc78, 0x20310001},
609 {0xc78, 0x06320001}, {0xc78, 0x05330001},
610 {0xc78, 0x04340001}, {0xc78, 0x03350001},
611 {0xc78, 0x02360001}, {0xc78, 0x01370001},
612 {0xc78, 0x00380001}, {0xc78, 0x00390001},
613 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
614 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
615 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
616 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
617 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
618 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
619 {0xc78, 0x7a460001}, {0xc78, 0x79470001},
620 {0xc78, 0x78480001}, {0xc78, 0x77490001},
621 {0xc78, 0x764a0001}, {0xc78, 0x754b0001},
622 {0xc78, 0x744c0001}, {0xc78, 0x734d0001},
623 {0xc78, 0x724e0001}, {0xc78, 0x714f0001},
624 {0xc78, 0x70500001}, {0xc78, 0x6f510001},
625 {0xc78, 0x6e520001}, {0xc78, 0x6d530001},
626 {0xc78, 0x6c540001}, {0xc78, 0x6b550001},
627 {0xc78, 0x6a560001}, {0xc78, 0x69570001},
628 {0xc78, 0x68580001}, {0xc78, 0x67590001},
629 {0xc78, 0x665a0001}, {0xc78, 0x655b0001},
630 {0xc78, 0x645c0001}, {0xc78, 0x635d0001},
631 {0xc78, 0x625e0001}, {0xc78, 0x615f0001},
632 {0xc78, 0x60600001}, {0xc78, 0x49610001},
633 {0xc78, 0x48620001}, {0xc78, 0x47630001},
634 {0xc78, 0x46640001}, {0xc78, 0x45650001},
635 {0xc78, 0x44660001}, {0xc78, 0x43670001},
636 {0xc78, 0x42680001}, {0xc78, 0x41690001},
637 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
638 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
639 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
640 {0xc78, 0x21700001}, {0xc78, 0x20710001},
641 {0xc78, 0x06720001}, {0xc78, 0x05730001},
642 {0xc78, 0x04740001}, {0xc78, 0x03750001},
643 {0xc78, 0x02760001}, {0xc78, 0x01770001},
644 {0xc78, 0x00780001}, {0xc78, 0x00790001},
645 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
646 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
647 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
648 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
649 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
650 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
651 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
652 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
653 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
654 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
655 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
656 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
657 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
658 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
659 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
660 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
661 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
662 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
663 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
664 {0xffff, 0xffffffff}
665};
666
667static struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table[] = {
668 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
669 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
670 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
671 {0xc78, 0x7b060001}, {0xc78, 0x7b070001},
672 {0xc78, 0x7b080001}, {0xc78, 0x7a090001},
673 {0xc78, 0x790a0001}, {0xc78, 0x780b0001},
674 {0xc78, 0x770c0001}, {0xc78, 0x760d0001},
675 {0xc78, 0x750e0001}, {0xc78, 0x740f0001},
676 {0xc78, 0x73100001}, {0xc78, 0x72110001},
677 {0xc78, 0x71120001}, {0xc78, 0x70130001},
678 {0xc78, 0x6f140001}, {0xc78, 0x6e150001},
679 {0xc78, 0x6d160001}, {0xc78, 0x6c170001},
680 {0xc78, 0x6b180001}, {0xc78, 0x6a190001},
681 {0xc78, 0x691a0001}, {0xc78, 0x681b0001},
682 {0xc78, 0x671c0001}, {0xc78, 0x661d0001},
683 {0xc78, 0x651e0001}, {0xc78, 0x641f0001},
684 {0xc78, 0x63200001}, {0xc78, 0x62210001},
685 {0xc78, 0x61220001}, {0xc78, 0x60230001},
686 {0xc78, 0x46240001}, {0xc78, 0x45250001},
687 {0xc78, 0x44260001}, {0xc78, 0x43270001},
688 {0xc78, 0x42280001}, {0xc78, 0x41290001},
689 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
690 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
691 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
692 {0xc78, 0x21300001}, {0xc78, 0x20310001},
693 {0xc78, 0x06320001}, {0xc78, 0x05330001},
694 {0xc78, 0x04340001}, {0xc78, 0x03350001},
695 {0xc78, 0x02360001}, {0xc78, 0x01370001},
696 {0xc78, 0x00380001}, {0xc78, 0x00390001},
697 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
698 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
699 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
700 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
701 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
702 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
703 {0xc78, 0x7b460001}, {0xc78, 0x7b470001},
704 {0xc78, 0x7b480001}, {0xc78, 0x7a490001},
705 {0xc78, 0x794a0001}, {0xc78, 0x784b0001},
706 {0xc78, 0x774c0001}, {0xc78, 0x764d0001},
707 {0xc78, 0x754e0001}, {0xc78, 0x744f0001},
708 {0xc78, 0x73500001}, {0xc78, 0x72510001},
709 {0xc78, 0x71520001}, {0xc78, 0x70530001},
710 {0xc78, 0x6f540001}, {0xc78, 0x6e550001},
711 {0xc78, 0x6d560001}, {0xc78, 0x6c570001},
712 {0xc78, 0x6b580001}, {0xc78, 0x6a590001},
713 {0xc78, 0x695a0001}, {0xc78, 0x685b0001},
714 {0xc78, 0x675c0001}, {0xc78, 0x665d0001},
715 {0xc78, 0x655e0001}, {0xc78, 0x645f0001},
716 {0xc78, 0x63600001}, {0xc78, 0x62610001},
717 {0xc78, 0x61620001}, {0xc78, 0x60630001},
718 {0xc78, 0x46640001}, {0xc78, 0x45650001},
719 {0xc78, 0x44660001}, {0xc78, 0x43670001},
720 {0xc78, 0x42680001}, {0xc78, 0x41690001},
721 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
722 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
723 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
724 {0xc78, 0x21700001}, {0xc78, 0x20710001},
725 {0xc78, 0x06720001}, {0xc78, 0x05730001},
726 {0xc78, 0x04740001}, {0xc78, 0x03750001},
727 {0xc78, 0x02760001}, {0xc78, 0x01770001},
728 {0xc78, 0x00780001}, {0xc78, 0x00790001},
729 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
730 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
731 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
732 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
733 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
734 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
735 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
736 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
737 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
738 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
739 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
740 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
741 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
742 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
743 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
744 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
745 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
746 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
747 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
748 {0xffff, 0xffffffff}
749};
750
b9f498e1
JS		 751static struct rtl8xxxu_reg32val rtl8xxx_agc_8723bu_table[] = {
752 {0xc78, 0xfd000001}, {0xc78, 0xfc010001},
753 {0xc78, 0xfb020001}, {0xc78, 0xfa030001},
754 {0xc78, 0xf9040001}, {0xc78, 0xf8050001},
755 {0xc78, 0xf7060001}, {0xc78, 0xf6070001},
756 {0xc78, 0xf5080001}, {0xc78, 0xf4090001},
757 {0xc78, 0xf30a0001}, {0xc78, 0xf20b0001},
758 {0xc78, 0xf10c0001}, {0xc78, 0xf00d0001},
759 {0xc78, 0xef0e0001}, {0xc78, 0xee0f0001},
760 {0xc78, 0xed100001}, {0xc78, 0xec110001},
761 {0xc78, 0xeb120001}, {0xc78, 0xea130001},
762 {0xc78, 0xe9140001}, {0xc78, 0xe8150001},
763 {0xc78, 0xe7160001}, {0xc78, 0xe6170001},
764 {0xc78, 0xe5180001}, {0xc78, 0xe4190001},
765 {0xc78, 0xe31a0001}, {0xc78, 0xa51b0001},
766 {0xc78, 0xa41c0001}, {0xc78, 0xa31d0001},
767 {0xc78, 0x671e0001}, {0xc78, 0x661f0001},
768 {0xc78, 0x65200001}, {0xc78, 0x64210001},
769 {0xc78, 0x63220001}, {0xc78, 0x4a230001},
770 {0xc78, 0x49240001}, {0xc78, 0x48250001},
771 {0xc78, 0x47260001}, {0xc78, 0x46270001},
772 {0xc78, 0x45280001}, {0xc78, 0x44290001},
773 {0xc78, 0x432a0001}, {0xc78, 0x422b0001},
774 {0xc78, 0x292c0001}, {0xc78, 0x282d0001},
775 {0xc78, 0x272e0001}, {0xc78, 0x262f0001},
776 {0xc78, 0x0a300001}, {0xc78, 0x09310001},
777 {0xc78, 0x08320001}, {0xc78, 0x07330001},
778 {0xc78, 0x06340001}, {0xc78, 0x05350001},
779 {0xc78, 0x04360001}, {0xc78, 0x03370001},
780 {0xc78, 0x02380001}, {0xc78, 0x01390001},
781 {0xc78, 0x013a0001}, {0xc78, 0x013b0001},
782 {0xc78, 0x013c0001}, {0xc78, 0x013d0001},
783 {0xc78, 0x013e0001}, {0xc78, 0x013f0001},
784 {0xc78, 0xfc400001}, {0xc78, 0xfb410001},
785 {0xc78, 0xfa420001}, {0xc78, 0xf9430001},
786 {0xc78, 0xf8440001}, {0xc78, 0xf7450001},
787 {0xc78, 0xf6460001}, {0xc78, 0xf5470001},
788 {0xc78, 0xf4480001}, {0xc78, 0xf3490001},
789 {0xc78, 0xf24a0001}, {0xc78, 0xf14b0001},
790 {0xc78, 0xf04c0001}, {0xc78, 0xef4d0001},
791 {0xc78, 0xee4e0001}, {0xc78, 0xed4f0001},
792 {0xc78, 0xec500001}, {0xc78, 0xeb510001},
793 {0xc78, 0xea520001}, {0xc78, 0xe9530001},
794 {0xc78, 0xe8540001}, {0xc78, 0xe7550001},
795 {0xc78, 0xe6560001}, {0xc78, 0xe5570001},
796 {0xc78, 0xe4580001}, {0xc78, 0xe3590001},
797 {0xc78, 0xa65a0001}, {0xc78, 0xa55b0001},
798 {0xc78, 0xa45c0001}, {0xc78, 0xa35d0001},
799 {0xc78, 0x675e0001}, {0xc78, 0x665f0001},
800 {0xc78, 0x65600001}, {0xc78, 0x64610001},
801 {0xc78, 0x63620001}, {0xc78, 0x62630001},
802 {0xc78, 0x61640001}, {0xc78, 0x48650001},
803 {0xc78, 0x47660001}, {0xc78, 0x46670001},
804 {0xc78, 0x45680001}, {0xc78, 0x44690001},
805 {0xc78, 0x436a0001}, {0xc78, 0x426b0001},
806 {0xc78, 0x286c0001}, {0xc78, 0x276d0001},
807 {0xc78, 0x266e0001}, {0xc78, 0x256f0001},
808 {0xc78, 0x24700001}, {0xc78, 0x09710001},
809 {0xc78, 0x08720001}, {0xc78, 0x07730001},
810 {0xc78, 0x06740001}, {0xc78, 0x05750001},
811 {0xc78, 0x04760001}, {0xc78, 0x03770001},
812 {0xc78, 0x02780001}, {0xc78, 0x01790001},
813 {0xc78, 0x017a0001}, {0xc78, 0x017b0001},
814 {0xc78, 0x017c0001}, {0xc78, 0x017d0001},
815 {0xc78, 0x017e0001}, {0xc78, 0x017f0001},
816 {0xc50, 0x69553422},
817 {0xc50, 0x69553420},
818 {0x824, 0x00390204},
819 {0xffff, 0xffffffff}
820};
821
26f1fad2
JS		 822static struct rtl8xxxu_rfregval rtl8723au_radioa_1t_init_table[] = {
823 {0x00, 0x00030159}, {0x01, 0x00031284},
824 {0x02, 0x00098000}, {0x03, 0x00039c63},
825 {0x04, 0x000210e7}, {0x09, 0x0002044f},
826 {0x0a, 0x0001a3f1}, {0x0b, 0x00014787},
827 {0x0c, 0x000896fe}, {0x0d, 0x0000e02c},
828 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
829 {0x19, 0x00000000}, {0x1a, 0x00030355},
830 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
831 {0x1d, 0x000a1250}, {0x1e, 0x0000024f},
832 {0x1f, 0x00000000}, {0x20, 0x0000b614},
833 {0x21, 0x0006c000}, {0x22, 0x00000000},
834 {0x23, 0x00001558}, {0x24, 0x00000060},
835 {0x25, 0x00000483}, {0x26, 0x0004f000},
836 {0x27, 0x000ec7d9}, {0x28, 0x00057730},
837 {0x29, 0x00004783}, {0x2a, 0x00000001},
838 {0x2b, 0x00021334}, {0x2a, 0x00000000},
839 {0x2b, 0x00000054}, {0x2a, 0x00000001},
840 {0x2b, 0x00000808}, {0x2b, 0x00053333},
841 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
842 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
843 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
844 {0x2b, 0x00000808}, {0x2b, 0x00063333},
845 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
846 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
847 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
848 {0x2b, 0x00000808}, {0x2b, 0x00073333},
849 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
850 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
851 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
852 {0x2b, 0x00000709}, {0x2b, 0x00063333},
853 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
854 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
855 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
856 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
857 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
858 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
859 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
860 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
861 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
862 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
863 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
864 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
865 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
866 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
867 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
868 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
869 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
870 {0x10, 0x0002000f}, {0x11, 0x000203f9},
871 {0x10, 0x0003000f}, {0x11, 0x000ff500},
872 {0x10, 0x00000000}, {0x11, 0x00000000},
873 {0x10, 0x0008000f}, {0x11, 0x0003f100},
874 {0x10, 0x0009000f}, {0x11, 0x00023100},
875 {0x12, 0x00032000}, {0x12, 0x00071000},
876 {0x12, 0x000b0000}, {0x12, 0x000fc000},
877 {0x13, 0x000287b3}, {0x13, 0x000244b7},
878 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
879 {0x13, 0x00018493}, {0x13, 0x0001429b},
880 {0x13, 0x00010299}, {0x13, 0x0000c29c},
881 {0x13, 0x000081a0}, {0x13, 0x000040ac},
882 {0x13, 0x00000020}, {0x14, 0x0001944c},
883 {0x14, 0x00059444}, {0x14, 0x0009944c},
884 {0x14, 0x000d9444}, {0x15, 0x0000f474},
885 {0x15, 0x0004f477}, {0x15, 0x0008f455},
886 {0x15, 0x000cf455}, {0x16, 0x00000339},
887 {0x16, 0x00040339}, {0x16, 0x00080339},
888 {0x16, 0x000c0366}, {0x00, 0x00010159},
889 {0x18, 0x0000f401}, {0xfe, 0x00000000},
890 {0xfe, 0x00000000}, {0x1f, 0x00000003},
891 {0xfe, 0x00000000}, {0xfe, 0x00000000},
892 {0x1e, 0x00000247}, {0x1f, 0x00000000},
893 {0x00, 0x00030159},
894 {0xff, 0xffffffff}
895};
896
22a31d45
JS		 897static struct rtl8xxxu_rfregval rtl8723bu_radioa_1t_init_table[] = {
898 {0x00, 0x00010000}, {0xb0, 0x000dffe0},
899 {0xfe, 0x00000000}, {0xfe, 0x00000000},
900 {0xfe, 0x00000000}, {0xb1, 0x00000018},
901 {0xfe, 0x00000000}, {0xfe, 0x00000000},
902 {0xfe, 0x00000000}, {0xb2, 0x00084c00},
903 {0xb5, 0x0000d2cc}, {0xb6, 0x000925aa},
904 {0xb7, 0x00000010}, {0xb8, 0x0000907f},
905 {0x5c, 0x00000002}, {0x7c, 0x00000002},
906 {0x7e, 0x00000005}, {0x8b, 0x0006fc00},
907 {0xb0, 0x000ff9f0}, {0x1c, 0x000739d2},
908 {0x1e, 0x00000000}, {0xdf, 0x00000780},
909 {0x50, 0x00067435},
910 /*
911 * The 8723bu vendor driver indicates that bit 8 should be set in
912 * 0x51 for package types TFBGA90, TFBGA80, and TFBGA79. However
913 * they never actually check the package type - and just default
914 * to not setting it.
915 */
916 {0x51, 0x0006b04e},
917 {0x52, 0x000007d2}, {0x53, 0x00000000},
918 {0x54, 0x00050400}, {0x55, 0x0004026e},
919 {0xdd, 0x0000004c}, {0x70, 0x00067435},
920 /*
921 * 0x71 has same package type condition as for register 0x51
922 */
923 {0x71, 0x0006b04e},
924 {0x72, 0x000007d2}, {0x73, 0x00000000},
925 {0x74, 0x00050400}, {0x75, 0x0004026e},
926 {0xef, 0x00000100}, {0x34, 0x0000add7},
927 {0x35, 0x00005c00}, {0x34, 0x00009dd4},
928 {0x35, 0x00005000}, {0x34, 0x00008dd1},
929 {0x35, 0x00004400}, {0x34, 0x00007dce},
930 {0x35, 0x00003800}, {0x34, 0x00006cd1},
931 {0x35, 0x00004400}, {0x34, 0x00005cce},
932 {0x35, 0x00003800}, {0x34, 0x000048ce},
933 {0x35, 0x00004400}, {0x34, 0x000034ce},
934 {0x35, 0x00003800}, {0x34, 0x00002451},
935 {0x35, 0x00004400}, {0x34, 0x0000144e},
936 {0x35, 0x00003800}, {0x34, 0x00000051},
937 {0x35, 0x00004400}, {0xef, 0x00000000},
938 {0xef, 0x00000100}, {0xed, 0x00000010},
939 {0x44, 0x0000add7}, {0x44, 0x00009dd4},
940 {0x44, 0x00008dd1}, {0x44, 0x00007dce},
941 {0x44, 0x00006cc1}, {0x44, 0x00005cce},
942 {0x44, 0x000044d1}, {0x44, 0x000034ce},
943 {0x44, 0x00002451}, {0x44, 0x0000144e},
944 {0x44, 0x00000051}, {0xef, 0x00000000},
945 {0xed, 0x00000000}, {0x7f, 0x00020080},
946 {0xef, 0x00002000}, {0x3b, 0x000380ef},
947 {0x3b, 0x000302fe}, {0x3b, 0x00028ce6},
948 {0x3b, 0x000200bc}, {0x3b, 0x000188a5},
949 {0x3b, 0x00010fbc}, {0x3b, 0x00008f71},
950 {0x3b, 0x00000900}, {0xef, 0x00000000},
951 {0xed, 0x00000001}, {0x40, 0x000380ef},
952 {0x40, 0x000302fe}, {0x40, 0x00028ce6},
953 {0x40, 0x000200bc}, {0x40, 0x000188a5},
954 {0x40, 0x00010fbc}, {0x40, 0x00008f71},
955 {0x40, 0x00000900}, {0xed, 0x00000000},
956 {0x82, 0x00080000}, {0x83, 0x00008000},
957 {0x84, 0x00048d80}, {0x85, 0x00068000},
958 {0xa2, 0x00080000}, {0xa3, 0x00008000},
959 {0xa4, 0x00048d80}, {0xa5, 0x00068000},
960 {0xed, 0x00000002}, {0xef, 0x00000002},
961 {0x56, 0x00000032}, {0x76, 0x00000032},
962 {0x01, 0x00000780},
963 {0xff, 0xffffffff}
964};
965
26f1fad2
JS		 966static struct rtl8xxxu_rfregval rtl8192cu_radioa_2t_init_table[] = {
967 {0x00, 0x00030159}, {0x01, 0x00031284},
968 {0x02, 0x00098000}, {0x03, 0x00018c63},
969 {0x04, 0x000210e7}, {0x09, 0x0002044f},
970 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
971 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
972 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
973 {0x19, 0x00000000}, {0x1a, 0x00010255},
974 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
975 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
976 {0x1f, 0x00080001}, {0x20, 0x0000b614},
977 {0x21, 0x0006c000}, {0x22, 0x00000000},
978 {0x23, 0x00001558}, {0x24, 0x00000060},
979 {0x25, 0x00000483}, {0x26, 0x0004f000},
980 {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
981 {0x29, 0x00004783}, {0x2a, 0x00000001},
982 {0x2b, 0x00021334}, {0x2a, 0x00000000},
983 {0x2b, 0x00000054}, {0x2a, 0x00000001},
984 {0x2b, 0x00000808}, {0x2b, 0x00053333},
985 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
986 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
987 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
988 {0x2b, 0x00000808}, {0x2b, 0x00063333},
989 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
990 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
991 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
992 {0x2b, 0x00000808}, {0x2b, 0x00073333},
993 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
994 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
995 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
996 {0x2b, 0x00000709}, {0x2b, 0x00063333},
997 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
998 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
999 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1000 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1001 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1002 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1003 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1004 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1005 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1006 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1007 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1008 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1009 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1010 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1011 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1012 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1013 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1014 {0x10, 0x0002000f}, {0x11, 0x000203f9},
1015 {0x10, 0x0003000f}, {0x11, 0x000ff500},
1016 {0x10, 0x00000000}, {0x11, 0x00000000},
1017 {0x10, 0x0008000f}, {0x11, 0x0003f100},
1018 {0x10, 0x0009000f}, {0x11, 0x00023100},
1019 {0x12, 0x00032000}, {0x12, 0x00071000},
1020 {0x12, 0x000b0000}, {0x12, 0x000fc000},
1021 {0x13, 0x000287b3}, {0x13, 0x000244b7},
1022 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1023 {0x13, 0x00018493}, {0x13, 0x0001429b},
1024 {0x13, 0x00010299}, {0x13, 0x0000c29c},
1025 {0x13, 0x000081a0}, {0x13, 0x000040ac},
1026 {0x13, 0x00000020}, {0x14, 0x0001944c},
1027 {0x14, 0x00059444}, {0x14, 0x0009944c},
1028 {0x14, 0x000d9444}, {0x15, 0x0000f424},
1029 {0x15, 0x0004f424}, {0x15, 0x0008f424},
1030 {0x15, 0x000cf424}, {0x16, 0x000e0330},
1031 {0x16, 0x000a0330}, {0x16, 0x00060330},
1032 {0x16, 0x00020330}, {0x00, 0x00010159},
1033 {0x18, 0x0000f401}, {0xfe, 0x00000000},
1034 {0xfe, 0x00000000}, {0x1f, 0x00080003},
1035 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1036 {0x1e, 0x00044457}, {0x1f, 0x00080000},
1037 {0x00, 0x00030159},
1038 {0xff, 0xffffffff}
1039};
1040
1041static struct rtl8xxxu_rfregval rtl8192cu_radiob_2t_init_table[] = {
1042 {0x00, 0x00030159}, {0x01, 0x00031284},
1043 {0x02, 0x00098000}, {0x03, 0x00018c63},
1044 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1045 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
1046 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
1047 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1048 {0x12, 0x00032000}, {0x12, 0x00071000},
1049 {0x12, 0x000b0000}, {0x12, 0x000fc000},
1050 {0x13, 0x000287af}, {0x13, 0x000244b7},
1051 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1052 {0x13, 0x00018493}, {0x13, 0x00014297},
1053 {0x13, 0x00010295}, {0x13, 0x0000c298},
1054 {0x13, 0x0000819c}, {0x13, 0x000040a8},
1055 {0x13, 0x0000001c}, {0x14, 0x0001944c},
1056 {0x14, 0x00059444}, {0x14, 0x0009944c},
1057 {0x14, 0x000d9444}, {0x15, 0x0000f424},
1058 {0x15, 0x0004f424}, {0x15, 0x0008f424},
1059 {0x15, 0x000cf424}, {0x16, 0x000e0330},
1060 {0x16, 0x000a0330}, {0x16, 0x00060330},
1061 {0x16, 0x00020330},
1062 {0xff, 0xffffffff}
1063};
1064
1065static struct rtl8xxxu_rfregval rtl8192cu_radioa_1t_init_table[] = {
1066 {0x00, 0x00030159}, {0x01, 0x00031284},
1067 {0x02, 0x00098000}, {0x03, 0x00018c63},
1068 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1069 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
1070 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
1071 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1072 {0x19, 0x00000000}, {0x1a, 0x00010255},
1073 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
1074 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
1075 {0x1f, 0x00080001}, {0x20, 0x0000b614},
1076 {0x21, 0x0006c000}, {0x22, 0x00000000},
1077 {0x23, 0x00001558}, {0x24, 0x00000060},
1078 {0x25, 0x00000483}, {0x26, 0x0004f000},
1079 {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
1080 {0x29, 0x00004783}, {0x2a, 0x00000001},
1081 {0x2b, 0x00021334}, {0x2a, 0x00000000},
1082 {0x2b, 0x00000054}, {0x2a, 0x00000001},
1083 {0x2b, 0x00000808}, {0x2b, 0x00053333},
1084 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
1085 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
1086 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
1087 {0x2b, 0x00000808}, {0x2b, 0x00063333},
1088 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
1089 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
1090 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
1091 {0x2b, 0x00000808}, {0x2b, 0x00073333},
1092 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
1093 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
1094 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
1095 {0x2b, 0x00000709}, {0x2b, 0x00063333},
1096 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
1097 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
1098 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1099 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1100 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1101 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1102 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1103 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1104 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1105 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1106 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1107 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1108 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1109 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1110 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1111 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1112 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1113 {0x10, 0x0002000f}, {0x11, 0x000203f9},
1114 {0x10, 0x0003000f}, {0x11, 0x000ff500},
1115 {0x10, 0x00000000}, {0x11, 0x00000000},
1116 {0x10, 0x0008000f}, {0x11, 0x0003f100},
1117 {0x10, 0x0009000f}, {0x11, 0x00023100},
1118 {0x12, 0x00032000}, {0x12, 0x00071000},
1119 {0x12, 0x000b0000}, {0x12, 0x000fc000},
1120 {0x13, 0x000287b3}, {0x13, 0x000244b7},
1121 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1122 {0x13, 0x00018493}, {0x13, 0x0001429b},
1123 {0x13, 0x00010299}, {0x13, 0x0000c29c},
1124 {0x13, 0x000081a0}, {0x13, 0x000040ac},
1125 {0x13, 0x00000020}, {0x14, 0x0001944c},
1126 {0x14, 0x00059444}, {0x14, 0x0009944c},
1127 {0x14, 0x000d9444}, {0x15, 0x0000f405},
1128 {0x15, 0x0004f405}, {0x15, 0x0008f405},
1129 {0x15, 0x000cf405}, {0x16, 0x000e0330},
1130 {0x16, 0x000a0330}, {0x16, 0x00060330},
1131 {0x16, 0x00020330}, {0x00, 0x00010159},
1132 {0x18, 0x0000f401}, {0xfe, 0x00000000},
1133 {0xfe, 0x00000000}, {0x1f, 0x00080003},
1134 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1135 {0x1e, 0x00044457}, {0x1f, 0x00080000},
1136 {0x00, 0x00030159},
1137 {0xff, 0xffffffff}
1138};
1139
1140static struct rtl8xxxu_rfregval rtl8188ru_radioa_1t_highpa_table[] = {
1141 {0x00, 0x00030159}, {0x01, 0x00031284},
1142 {0x02, 0x00098000}, {0x03, 0x00018c63},
1143 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1144 {0x0a, 0x0001adb0}, {0x0b, 0x00054867},
1145 {0x0c, 0x0008992e}, {0x0d, 0x0000e529},
1146 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1147 {0x19, 0x00000000}, {0x1a, 0x00000255},
1148 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
1149 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
1150 {0x1f, 0x00080001}, {0x20, 0x0000b614},
1151 {0x21, 0x0006c000}, {0x22, 0x0000083c},
1152 {0x23, 0x00001558}, {0x24, 0x00000060},
1153 {0x25, 0x00000483}, {0x26, 0x0004f000},
1154 {0x27, 0x000ec7d9}, {0x28, 0x000977c0},
1155 {0x29, 0x00004783}, {0x2a, 0x00000001},
1156 {0x2b, 0x00021334}, {0x2a, 0x00000000},
1157 {0x2b, 0x00000054}, {0x2a, 0x00000001},
1158 {0x2b, 0x00000808}, {0x2b, 0x00053333},
1159 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
1160 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
1161 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
1162 {0x2b, 0x00000808}, {0x2b, 0x00063333},
1163 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
1164 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
1165 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
1166 {0x2b, 0x00000808}, {0x2b, 0x00073333},
1167 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
1168 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
1169 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
1170 {0x2b, 0x00000709}, {0x2b, 0x00063333},
1171 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
1172 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
1173 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1174 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1175 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1176 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1177 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1178 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1179 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1180 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1181 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1182 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1183 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1184 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1185 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1186 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1187 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1188 {0x10, 0x0002000f}, {0x11, 0x000203f9},
1189 {0x10, 0x0003000f}, {0x11, 0x000ff500},
1190 {0x10, 0x00000000}, {0x11, 0x00000000},
1191 {0x10, 0x0008000f}, {0x11, 0x0003f100},
1192 {0x10, 0x0009000f}, {0x11, 0x00023100},
1193 {0x12, 0x000d8000}, {0x12, 0x00090000},
1194 {0x12, 0x00051000}, {0x12, 0x00012000},
1195 {0x13, 0x00028fb4}, {0x13, 0x00024fa8},
1196 {0x13, 0x000207a4}, {0x13, 0x0001c3b0},
1197 {0x13, 0x000183a4}, {0x13, 0x00014398},
1198 {0x13, 0x000101a4}, {0x13, 0x0000c198},
1199 {0x13, 0x000080a4}, {0x13, 0x00004098},
1200 {0x13, 0x00000000}, {0x14, 0x0001944c},
1201 {0x14, 0x00059444}, {0x14, 0x0009944c},
1202 {0x14, 0x000d9444}, {0x15, 0x0000f405},
1203 {0x15, 0x0004f405}, {0x15, 0x0008f405},
1204 {0x15, 0x000cf405}, {0x16, 0x000e0330},
1205 {0x16, 0x000a0330}, {0x16, 0x00060330},
1206 {0x16, 0x00020330}, {0x00, 0x00010159},
1207 {0x18, 0x0000f401}, {0xfe, 0x00000000},
1208 {0xfe, 0x00000000}, {0x1f, 0x00080003},
1209 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1210 {0x1e, 0x00044457}, {0x1f, 0x00080000},
1211 {0x00, 0x00030159},
1212 {0xff, 0xffffffff}
1213};
1214
1215static struct rtl8xxxu_rfregs rtl8xxxu_rfregs[] = {
1216 { /* RF_A */
1217 .hssiparm1 = REG_FPGA0_XA_HSSI_PARM1,
1218 .hssiparm2 = REG_FPGA0_XA_HSSI_PARM2,
1219 .lssiparm = REG_FPGA0_XA_LSSI_PARM,
1220 .hspiread = REG_HSPI_XA_READBACK,
1221 .lssiread = REG_FPGA0_XA_LSSI_READBACK,
1222 .rf_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL,
1223 },
1224 { /* RF_B */
1225 .hssiparm1 = REG_FPGA0_XB_HSSI_PARM1,
1226 .hssiparm2 = REG_FPGA0_XB_HSSI_PARM2,
1227 .lssiparm = REG_FPGA0_XB_LSSI_PARM,
1228 .hspiread = REG_HSPI_XB_READBACK,
1229 .lssiread = REG_FPGA0_XB_LSSI_READBACK,
1230 .rf_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL,
1231 },
1232};
1233
1234static const u32 rtl8723au_iqk_phy_iq_bb_reg[RTL8XXXU_BB_REGS] = {
1235 REG_OFDM0_XA_RX_IQ_IMBALANCE,
1236 REG_OFDM0_XB_RX_IQ_IMBALANCE,
1237 REG_OFDM0_ENERGY_CCA_THRES,
1238 REG_OFDM0_AGCR_SSI_TABLE,
1239 REG_OFDM0_XA_TX_IQ_IMBALANCE,
1240 REG_OFDM0_XB_TX_IQ_IMBALANCE,
1241 REG_OFDM0_XC_TX_AFE,
1242 REG_OFDM0_XD_TX_AFE,
1243 REG_OFDM0_RX_IQ_EXT_ANTA
1244};
1245
1246static u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr)
1247{
1248 struct usb_device *udev = priv->udev;
1249 int len;
1250 u8 data;
1251
1252 mutex_lock(&priv->usb_buf_mutex);
1253 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1254 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1255 addr, 0, &priv->usb_buf.val8, sizeof(u8),
1256 RTW_USB_CONTROL_MSG_TIMEOUT);
1257 data = priv->usb_buf.val8;
1258 mutex_unlock(&priv->usb_buf_mutex);
1259
1260 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1261 dev_info(&udev->dev, "%s(%04x) = 0x%02x, len %i\n",
1262 __func__, addr, data, len);
1263 return data;
1264}
1265
1266static u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr)
1267{
1268 struct usb_device *udev = priv->udev;
1269 int len;
1270 u16 data;
1271
1272 mutex_lock(&priv->usb_buf_mutex);
1273 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1274 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1275 addr, 0, &priv->usb_buf.val16, sizeof(u16),
1276 RTW_USB_CONTROL_MSG_TIMEOUT);
1277 data = le16_to_cpu(priv->usb_buf.val16);
1278 mutex_unlock(&priv->usb_buf_mutex);
1279
1280 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1281 dev_info(&udev->dev, "%s(%04x) = 0x%04x, len %i\n",
1282 __func__, addr, data, len);
1283 return data;
1284}
1285
1286static u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr)
1287{
1288 struct usb_device *udev = priv->udev;
1289 int len;
1290 u32 data;
1291
1292 mutex_lock(&priv->usb_buf_mutex);
1293 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1294 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1295 addr, 0, &priv->usb_buf.val32, sizeof(u32),
1296 RTW_USB_CONTROL_MSG_TIMEOUT);
1297 data = le32_to_cpu(priv->usb_buf.val32);
1298 mutex_unlock(&priv->usb_buf_mutex);
1299
1300 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1301 dev_info(&udev->dev, "%s(%04x) = 0x%08x, len %i\n",
1302 __func__, addr, data, len);
1303 return data;
1304}
1305
1306static int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val)
1307{
1308 struct usb_device *udev = priv->udev;
1309 int ret;
1310
1311 mutex_lock(&priv->usb_buf_mutex);
1312 priv->usb_buf.val8 = val;
1313 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1314 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1315 addr, 0, &priv->usb_buf.val8, sizeof(u8),
1316 RTW_USB_CONTROL_MSG_TIMEOUT);
1317
1318 mutex_unlock(&priv->usb_buf_mutex);
1319
1320 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1321 dev_info(&udev->dev, "%s(%04x) = 0x%02x\n",
1322 __func__, addr, val);
1323 return ret;
1324}
1325
1326static int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val)
1327{
1328 struct usb_device *udev = priv->udev;
1329 int ret;
1330
1331 mutex_lock(&priv->usb_buf_mutex);
1332 priv->usb_buf.val16 = cpu_to_le16(val);
1333 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1334 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1335 addr, 0, &priv->usb_buf.val16, sizeof(u16),
1336 RTW_USB_CONTROL_MSG_TIMEOUT);
1337 mutex_unlock(&priv->usb_buf_mutex);
1338
1339 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1340 dev_info(&udev->dev, "%s(%04x) = 0x%04x\n",
1341 __func__, addr, val);
1342 return ret;
1343}
1344
1345static int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val)
1346{
1347 struct usb_device *udev = priv->udev;
1348 int ret;
1349
1350 mutex_lock(&priv->usb_buf_mutex);
1351 priv->usb_buf.val32 = cpu_to_le32(val);
1352 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1353 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1354 addr, 0, &priv->usb_buf.val32, sizeof(u32),
1355 RTW_USB_CONTROL_MSG_TIMEOUT);
1356 mutex_unlock(&priv->usb_buf_mutex);
1357
1358 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1359 dev_info(&udev->dev, "%s(%04x) = 0x%08x\n",
1360 __func__, addr, val);
1361 return ret;
1362}
1363
1364static int
1365rtl8xxxu_writeN(struct rtl8xxxu_priv *priv, u16 addr, u8 *buf, u16 len)
1366{
1367 struct usb_device *udev = priv->udev;
1368 int blocksize = priv->fops->writeN_block_size;
1369 int ret, i, count, remainder;
1370
1371 count = len / blocksize;
1372 remainder = len % blocksize;
1373
1374 for (i = 0; i < count; i++) {
1375 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1376 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1377 addr, 0, buf, blocksize,
1378 RTW_USB_CONTROL_MSG_TIMEOUT);
1379 if (ret != blocksize)
1380 goto write_error;
1381
1382 addr += blocksize;
1383 buf += blocksize;
1384 }
1385
1386 if (remainder) {
1387 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1388 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1389 addr, 0, buf, remainder,
1390 RTW_USB_CONTROL_MSG_TIMEOUT);
1391 if (ret != remainder)
1392 goto write_error;
1393 }
1394
1395 return len;
1396
1397write_error:
1398 dev_info(&udev->dev,
1399 "%s: Failed to write block at addr: %04x size: %04x\n",
1400 __func__, addr, blocksize);
1401 return -EAGAIN;
1402}
1403
1404static u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv,
1405 enum rtl8xxxu_rfpath path, u8 reg)
1406{
1407 u32 hssia, val32, retval;
1408
1409 hssia = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
1410 if (path != RF_A)
1411 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm2);
1412 else
1413 val32 = hssia;
1414
1415 val32 &= ~FPGA0_HSSI_PARM2_ADDR_MASK;
1416 val32 |= (reg << FPGA0_HSSI_PARM2_ADDR_SHIFT);
1417 val32 |= FPGA0_HSSI_PARM2_EDGE_READ;
1418 hssia &= ~FPGA0_HSSI_PARM2_EDGE_READ;
1419 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
1420
1421 udelay(10);
1422
1423 rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].hssiparm2, val32);
1424 udelay(100);
1425
1426 hssia |= FPGA0_HSSI_PARM2_EDGE_READ;
1427 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
1428 udelay(10);
1429
1430 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm1);
1431 if (val32 & FPGA0_HSSI_PARM1_PI)
1432 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hspiread);
1433 else
1434 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].lssiread);
1435
1436 retval &= 0xfffff;
1437
1438 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_READ)
1439 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
1440 __func__, reg, retval);
1441 return retval;
1442}
1443
22a31d45
JS		 1444/*
1445 * The RTL8723BU driver indicates that registers 0xb2 and 0xb6 can
1446 * have write issues in high temperature conditions. We may have to
1447 * retry writing them.
1448 */
26f1fad2
JS		 1449static int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv,
1450 enum rtl8xxxu_rfpath path, u8 reg, u32 data)
1451{
1452 int ret, retval;
1453 u32 dataaddr;
1454
1455 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_WRITE)
1456 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
1457 __func__, reg, data);
1458
1459 data &= FPGA0_LSSI_PARM_DATA_MASK;
1460 dataaddr = (reg << FPGA0_LSSI_PARM_ADDR_SHIFT) | data;
1461
1462 /* Use XB for path B */
1463 ret = rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].lssiparm, dataaddr);
1464 if (ret != sizeof(dataaddr))
1465 retval = -EIO;
1466 else
1467 retval = 0;
1468
1469 udelay(1);
1470
1471 return retval;
1472}
1473
8da91571
JS		 1474static int rtl8723a_h2c_cmd(struct rtl8xxxu_priv *priv,
1475 struct h2c_cmd *h2c, int len)
26f1fad2
JS		 1476{
1477 struct device *dev = &priv->udev->dev;
1478 int mbox_nr, retry, retval = 0;
1479 int mbox_reg, mbox_ext_reg;
1480 u8 val8;
1481
1482 mutex_lock(&priv->h2c_mutex);
1483
1484 mbox_nr = priv->next_mbox;
1485 mbox_reg = REG_HMBOX_0 + (mbox_nr * 4);
ed35d094
JS		 1486 mbox_ext_reg = priv->fops->mbox_ext_reg +
1487 (mbox_nr * priv->fops->mbox_ext_width);
26f1fad2
JS		 1488
1489 /*
1490 * MBOX ready?
1491 */
1492 retry = 100;
1493 do {
1494 val8 = rtl8xxxu_read8(priv, REG_HMTFR);
1495 if (!(val8 & BIT(mbox_nr)))
1496 break;
1497 } while (retry--);
1498
1499 if (!retry) {
c7a5a190 1500 dev_info(dev, "%s: Mailbox busy\n", __func__);
26f1fad2
JS		 1501 retval = -EBUSY;
1502 goto error;
1503 }
1504
1505 /*
1506 * Need to swap as it's being swapped again by rtl8xxxu_write16/32()
1507 */
8da91571 1508 if (len > sizeof(u32)) {
ed35d094
JS		 1509 if (priv->fops->mbox_ext_width == 4) {
1510 rtl8xxxu_write32(priv, mbox_ext_reg,
1511 le32_to_cpu(h2c->raw_wide.ext));
1512 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1513 dev_info(dev, "H2C_EXT %08x\n",
1514 le32_to_cpu(h2c->raw_wide.ext));
1515 } else {
1516 rtl8xxxu_write16(priv, mbox_ext_reg,
1517 le16_to_cpu(h2c->raw.ext));
1518 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1519 dev_info(dev, "H2C_EXT %04x\n",
1520 le16_to_cpu(h2c->raw.ext));
1521 }
26f1fad2
JS		 1522 }
1523 rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data));
1524 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1525 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data));
1526
1527 priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX;
1528
1529error:
1530 mutex_unlock(&priv->h2c_mutex);
1531 return retval;
1532}
1533
1534static void rtl8723a_enable_rf(struct rtl8xxxu_priv *priv)
1535{
1536 u8 val8;
1537 u32 val32;
1538
1539 val8 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1540 val8 |= BIT(0) | BIT(3);
1541 rtl8xxxu_write8(priv, REG_SPS0_CTRL, val8);
1542
1543 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1544 val32 &= ~(BIT(4) | BIT(5));
1545 val32 |= BIT(3);
1546 if (priv->rf_paths == 2) {
1547 val32 &= ~(BIT(20) | BIT(21));
1548 val32 |= BIT(19);
1549 }
1550 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1551
1552 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1553 val32 &= ~OFDM_RF_PATH_TX_MASK;
1554 if (priv->tx_paths == 2)
1555 val32 |= OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B;
1556 else if (priv->rtlchip == 0x8192c || priv->rtlchip == 0x8191c)
1557 val32 |= OFDM_RF_PATH_TX_B;
1558 else
1559 val32 |= OFDM_RF_PATH_TX_A;
1560 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1561
1562 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1563 val32 &= ~FPGA_RF_MODE_JAPAN;
1564 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1565
1566 if (priv->rf_paths == 2)
1567 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x63db25a0);
1568 else
1569 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x631b25a0);
1570
1571 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x32d95);
1572 if (priv->rf_paths == 2)
1573 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x32d95);
1574
1575 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
1576}
1577
1578static void rtl8723a_disable_rf(struct rtl8xxxu_priv *priv)
1579{
1580 u8 sps0;
1581 u32 val32;
1582
1583 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
1584
1585 sps0 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1586
1587 /* RF RX code for preamble power saving */
1588 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1589 val32 &= ~(BIT(3) | BIT(4) | BIT(5));
1590 if (priv->rf_paths == 2)
1591 val32 &= ~(BIT(19) | BIT(20) | BIT(21));
1592 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1593
1594 /* Disable TX for four paths */
1595 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1596 val32 &= ~OFDM_RF_PATH_TX_MASK;
1597 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1598
1599 /* Enable power saving */
1600 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1601 val32 |= FPGA_RF_MODE_JAPAN;
1602 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1603
1604 /* AFE control register to power down bits [30:22] */
1605 if (priv->rf_paths == 2)
1606 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00db25a0);
1607 else
1608 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x001b25a0);
1609
1610 /* Power down RF module */
1611 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0);
1612 if (priv->rf_paths == 2)
1613 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0);
1614
1615 sps0 &= ~(BIT(0) | BIT(3));
1616 rtl8xxxu_write8(priv, REG_SPS0_CTRL, sps0);
1617}
1618
1619
1620static void rtl8723a_stop_tx_beacon(struct rtl8xxxu_priv *priv)
1621{
1622 u8 val8;
1623
1624 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2);
1625 val8 &= ~BIT(6);
1626 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8);
1627
1628 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x64);
1629 val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2);
1630 val8 &= ~BIT(0);
1631 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8);
1632}
1633
1634
1635/*
1636 * The rtl8723a has 3 channel groups for it's efuse settings. It only
1637 * supports the 2.4GHz band, so channels 1 - 14:
1638 * group 0: channels 1 - 3
1639 * group 1: channels 4 - 9
1640 * group 2: channels 10 - 14
1641 *
1642 * Note: We index from 0 in the code
1643 */
1644static int rtl8723a_channel_to_group(int channel)
1645{
1646 int group;
1647
1648 if (channel < 4)
1649 group = 0;
1650 else if (channel < 10)
1651 group = 1;
1652 else
1653 group = 2;
1654
1655 return group;
1656}
1657
1658static void rtl8723au_config_channel(struct ieee80211_hw *hw)
1659{
1660 struct rtl8xxxu_priv *priv = hw->priv;
1661 u32 val32, rsr;
1662 u8 val8, opmode;
1663 bool ht = true;
1664 int sec_ch_above, channel;
1665 int i;
1666
1667 opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE);
1668 rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
1669 channel = hw->conf.chandef.chan->hw_value;
1670
1671 switch (hw->conf.chandef.width) {
1672 case NL80211_CHAN_WIDTH_20_NOHT:
1673 ht = false;
1674 case NL80211_CHAN_WIDTH_20:
1675 opmode |= BW_OPMODE_20MHZ;
1676 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1677
1678 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1679 val32 &= ~FPGA_RF_MODE;
1680 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1681
1682 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1683 val32 &= ~FPGA_RF_MODE;
1684 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1685
1686 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1687 val32 |= FPGA0_ANALOG2_20MHZ;
1688 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1689 break;
1690 case NL80211_CHAN_WIDTH_40:
1691 if (hw->conf.chandef.center_freq1 >
1692 hw->conf.chandef.chan->center_freq) {
1693 sec_ch_above = 1;
1694 channel += 2;
1695 } else {
1696 sec_ch_above = 0;
1697 channel -= 2;
1698 }
1699
1700 opmode &= ~BW_OPMODE_20MHZ;
1701 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1702 rsr &= ~RSR_RSC_BANDWIDTH_40M;
1703 if (sec_ch_above)
1704 rsr |= RSR_RSC_UPPER_SUB_CHANNEL;
1705 else
1706 rsr |= RSR_RSC_LOWER_SUB_CHANNEL;
1707 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr);
1708
1709 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1710 val32 |= FPGA_RF_MODE;
1711 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1712
1713 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1714 val32 |= FPGA_RF_MODE;
1715 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1716
1717 /*
1718 * Set Control channel to upper or lower. These settings
1719 * are required only for 40MHz
1720 */
1721 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
1722 val32 &= ~CCK0_SIDEBAND;
1723 if (!sec_ch_above)
1724 val32 |= CCK0_SIDEBAND;
1725 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
1726
1727 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
1728 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
1729 if (sec_ch_above)
1730 val32 |= OFDM_LSTF_PRIME_CH_LOW;
1731 else
1732 val32 |= OFDM_LSTF_PRIME_CH_HIGH;
1733 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
1734
1735 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1736 val32 &= ~FPGA0_ANALOG2_20MHZ;
1737 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1738
1739 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1740 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
1741 if (sec_ch_above)
1742 val32 |= FPGA0_PS_UPPER_CHANNEL;
1743 else
1744 val32 |= FPGA0_PS_LOWER_CHANNEL;
1745 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1746 break;
1747
1748 default:
1749 break;
1750 }
1751
1752 for (i = RF_A; i < priv->rf_paths; i++) {
1753 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1754 val32 &= ~MODE_AG_CHANNEL_MASK;
1755 val32 |= channel;
1756 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1757 }
1758
1759 if (ht)
1760 val8 = 0x0e;
1761 else
1762 val8 = 0x0a;
1763
1764 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
1765 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
1766
1767 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
1768 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
1769
1770 for (i = RF_A; i < priv->rf_paths; i++) {
1771 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1772 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40)
1773 val32 &= ~MODE_AG_CHANNEL_20MHZ;
1774 else
1775 val32 |= MODE_AG_CHANNEL_20MHZ;
1776 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1777 }
1778}
1779
1780static void
1781rtl8723a_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
1782{
1783 u8 cck[RTL8723A_MAX_RF_PATHS], ofdm[RTL8723A_MAX_RF_PATHS];
1784 u8 ofdmbase[RTL8723A_MAX_RF_PATHS], mcsbase[RTL8723A_MAX_RF_PATHS];
1785 u32 val32, ofdm_a, ofdm_b, mcs_a, mcs_b;
1786 u8 val8;
1787 int group, i;
1788
1789 group = rtl8723a_channel_to_group(channel);
1790
1791 cck[0] = priv->cck_tx_power_index_A[group];
1792 cck[1] = priv->cck_tx_power_index_B[group];
1793
1794 ofdm[0] = priv->ht40_1s_tx_power_index_A[group];
1795 ofdm[1] = priv->ht40_1s_tx_power_index_B[group];
1796
1797 ofdmbase[0] = ofdm[0] + priv->ofdm_tx_power_index_diff[group].a;
1798 ofdmbase[1] = ofdm[1] + priv->ofdm_tx_power_index_diff[group].b;
1799
1800 mcsbase[0] = ofdm[0];
1801 mcsbase[1] = ofdm[1];
1802 if (!ht40) {
1803 mcsbase[0] += priv->ht20_tx_power_index_diff[group].a;
1804 mcsbase[1] += priv->ht20_tx_power_index_diff[group].b;
1805 }
1806
1807 if (priv->tx_paths > 1) {
1808 if (ofdm[0] > priv->ht40_2s_tx_power_index_diff[group].a)
1809 ofdm[0] -= priv->ht40_2s_tx_power_index_diff[group].a;
1810 if (ofdm[1] > priv->ht40_2s_tx_power_index_diff[group].b)
1811 ofdm[1] -= priv->ht40_2s_tx_power_index_diff[group].b;
1812 }
1813
1814 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
1815 dev_info(&priv->udev->dev,
1816 "%s: Setting TX power CCK A: %02x, "
1817 "CCK B: %02x, OFDM A: %02x, OFDM B: %02x\n",
1818 __func__, cck[0], cck[1], ofdm[0], ofdm[1]);
1819
1820 for (i = 0; i < RTL8723A_MAX_RF_PATHS; i++) {
1821 if (cck[i] > RF6052_MAX_TX_PWR)
1822 cck[i] = RF6052_MAX_TX_PWR;
1823 if (ofdm[i] > RF6052_MAX_TX_PWR)
1824 ofdm[i] = RF6052_MAX_TX_PWR;
1825 }
1826
1827 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
1828 val32 &= 0xffff00ff;
1829 val32 |= (cck[0] << 8);
1830 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
1831
1832 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1833 val32 &= 0xff;
1834 val32 |= ((cck[0] << 8) | (cck[0] << 16) | (cck[0] << 24));
1835 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
1836
1837 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1838 val32 &= 0xffffff00;
1839 val32 |= cck[1];
1840 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
1841
1842 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32);
1843 val32 &= 0xff;
1844 val32 |= ((cck[1] << 8) | (cck[1] << 16) | (cck[1] << 24));
1845 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32);
1846
1847 ofdm_a = ofdmbase[0] | ofdmbase[0] << 8 |
1848 ofdmbase[0] << 16 | ofdmbase[0] << 24;
1849 ofdm_b = ofdmbase[1] | ofdmbase[1] << 8 |
1850 ofdmbase[1] << 16 | ofdmbase[1] << 24;
1851 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm_a);
1852 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06, ofdm_b);
1853
1854 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm_a);
1855 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24, ofdm_b);
1856
1857 mcs_a = mcsbase[0] | mcsbase[0] << 8 |
1858 mcsbase[0] << 16 | mcsbase[0] << 24;
1859 mcs_b = mcsbase[1] | mcsbase[1] << 8 |
1860 mcsbase[1] << 16 | mcsbase[1] << 24;
1861
1862 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs_a);
1863 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00, mcs_b);
1864
1865 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs_a);
1866 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04, mcs_b);
1867
1868 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs_a);
1869 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08, mcs_b);
1870
1871 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs_a);
1872 for (i = 0; i < 3; i++) {
1873 if (i != 2)
1874 val8 = (mcsbase[0] > 8) ? (mcsbase[0] - 8) : 0;
1875 else
1876 val8 = (mcsbase[0] > 6) ? (mcsbase[0] - 6) : 0;
1877 rtl8xxxu_write8(priv, REG_OFDM0_XC_TX_IQ_IMBALANCE + i, val8);
1878 }
1879 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12, mcs_b);
1880 for (i = 0; i < 3; i++) {
1881 if (i != 2)
1882 val8 = (mcsbase[1] > 8) ? (mcsbase[1] - 8) : 0;
1883 else
1884 val8 = (mcsbase[1] > 6) ? (mcsbase[1] - 6) : 0;
1885 rtl8xxxu_write8(priv, REG_OFDM0_XD_TX_IQ_IMBALANCE + i, val8);
1886 }
1887}
1888
1889static void rtl8xxxu_set_linktype(struct rtl8xxxu_priv *priv,
1890 enum nl80211_iftype linktype)
1891{
a26703f3 1892 u8 val8;
26f1fad2 1893
a26703f3 1894 val8 = rtl8xxxu_read8(priv, REG_MSR);
26f1fad2
JS		 1895 val8 &= ~MSR_LINKTYPE_MASK;
1896
1897 switch (linktype) {
1898 case NL80211_IFTYPE_UNSPECIFIED:
1899 val8 |= MSR_LINKTYPE_NONE;
1900 break;
1901 case NL80211_IFTYPE_ADHOC:
1902 val8 |= MSR_LINKTYPE_ADHOC;
1903 break;
1904 case NL80211_IFTYPE_STATION:
1905 val8 |= MSR_LINKTYPE_STATION;
1906 break;
1907 case NL80211_IFTYPE_AP:
1908 val8 |= MSR_LINKTYPE_AP;
1909 break;
1910 default:
1911 goto out;
1912 }
1913
1914 rtl8xxxu_write8(priv, REG_MSR, val8);
1915out:
1916 return;
1917}
1918
1919static void
1920rtl8xxxu_set_retry(struct rtl8xxxu_priv *priv, u16 short_retry, u16 long_retry)
1921{
1922 u16 val16;
1923
1924 val16 = ((short_retry << RETRY_LIMIT_SHORT_SHIFT) &
1925 RETRY_LIMIT_SHORT_MASK) |
1926 ((long_retry << RETRY_LIMIT_LONG_SHIFT) &
1927 RETRY_LIMIT_LONG_MASK);
1928
1929 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
1930}
1931
1932static void
1933rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv *priv, u16 cck, u16 ofdm)
1934{
1935 u16 val16;
1936
1937 val16 = ((cck << SPEC_SIFS_CCK_SHIFT) & SPEC_SIFS_CCK_MASK) |
1938 ((ofdm << SPEC_SIFS_OFDM_SHIFT) & SPEC_SIFS_OFDM_MASK);
1939
1940 rtl8xxxu_write16(priv, REG_SPEC_SIFS, val16);
1941}
1942
1943static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv *priv)
1944{
1945 struct device *dev = &priv->udev->dev;
1946 char *cut;
1947
1948 switch (priv->chip_cut) {
1949 case 0:
1950 cut = "A";
1951 break;
1952 case 1:
1953 cut = "B";
1954 break;
0e5d435a
JS		 1955 case 2:
1956 cut = "C";
1957 break;
1958 case 3:
1959 cut = "D";
1960 break;
1961 case 4:
1962 cut = "E";
1963 break;
26f1fad2
JS		 1964 default:
1965 cut = "unknown";
1966 }
1967
1968 dev_info(dev,
1969 "RTL%s rev %s (%s) %iT%iR, TX queues %i, WiFi=%i, BT=%i, GPS=%i, HI PA=%i\n",
0e5d435a
JS		 1970 priv->chip_name, cut, priv->chip_vendor, priv->tx_paths,
1971 priv->rx_paths, priv->ep_tx_count, priv->has_wifi,
1972 priv->has_bluetooth, priv->has_gps, priv->hi_pa);
26f1fad2
JS		 1973
1974 dev_info(dev, "RTL%s MAC: %pM\n", priv->chip_name, priv->mac_addr);
1975}
1976
1977static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv *priv)
1978{
1979 struct device *dev = &priv->udev->dev;
1980 u32 val32, bonding;
1981 u16 val16;
1982
1983 val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
1984 priv->chip_cut = (val32 & SYS_CFG_CHIP_VERSION_MASK) >>
1985 SYS_CFG_CHIP_VERSION_SHIFT;
1986 if (val32 & SYS_CFG_TRP_VAUX_EN) {
1987 dev_info(dev, "Unsupported test chip\n");
1988 return -ENOTSUPP;
1989 }
1990
1991 if (val32 & SYS_CFG_BT_FUNC) {
35a741fe
JS		 1992 if (priv->chip_cut >= 3) {
1993 sprintf(priv->chip_name, "8723BU");
1994 priv->rtlchip = 0x8723b;
1995 } else {
1996 sprintf(priv->chip_name, "8723AU");
0e28b975 1997 priv->usb_interrupts = 1;
35a741fe
JS		 1998 priv->rtlchip = 0x8723a;
1999 }
2000
26f1fad2
JS		 2001 priv->rf_paths = 1;
2002 priv->rx_paths = 1;
2003 priv->tx_paths = 1;
26f1fad2
JS		 2004
2005 val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL);
2006 if (val32 & MULTI_WIFI_FUNC_EN)
2007 priv->has_wifi = 1;
2008 if (val32 & MULTI_BT_FUNC_EN)
2009 priv->has_bluetooth = 1;
2010 if (val32 & MULTI_GPS_FUNC_EN)
2011 priv->has_gps = 1;
38451998 2012 priv->is_multi_func = 1;
26f1fad2
JS		 2013 } else if (val32 & SYS_CFG_TYPE_ID) {
2014 bonding = rtl8xxxu_read32(priv, REG_HPON_FSM);
2015 bonding &= HPON_FSM_BONDING_MASK;
0e5d435a
JS		 2016 if (priv->chip_cut >= 3) {
2017 if (bonding == HPON_FSM_BONDING_1T2R) {
2018 sprintf(priv->chip_name, "8191EU");
2019 priv->rf_paths = 2;
2020 priv->rx_paths = 2;
2021 priv->tx_paths = 1;
2022 priv->rtlchip = 0x8191e;
2023 } else {
2024 sprintf(priv->chip_name, "8192EU");
2025 priv->rf_paths = 2;
2026 priv->rx_paths = 2;
2027 priv->tx_paths = 2;
2028 priv->rtlchip = 0x8192e;
2029 }
2030 } else if (bonding == HPON_FSM_BONDING_1T2R) {
26f1fad2
JS		 2031 sprintf(priv->chip_name, "8191CU");
2032 priv->rf_paths = 2;
2033 priv->rx_paths = 2;
2034 priv->tx_paths = 1;
0e28b975 2035 priv->usb_interrupts = 1;
26f1fad2
JS		 2036 priv->rtlchip = 0x8191c;
2037 } else {
2038 sprintf(priv->chip_name, "8192CU");
2039 priv->rf_paths = 2;
2040 priv->rx_paths = 2;
2041 priv->tx_paths = 2;
0e28b975 2042 priv->usb_interrupts = 1;
26f1fad2
JS		 2043 priv->rtlchip = 0x8192c;
2044 }
2045 priv->has_wifi = 1;
2046 } else {
2047 sprintf(priv->chip_name, "8188CU");
2048 priv->rf_paths = 1;
2049 priv->rx_paths = 1;
2050 priv->tx_paths = 1;
2051 priv->rtlchip = 0x8188c;
0e28b975 2052 priv->usb_interrupts = 1;
26f1fad2
JS		 2053 priv->has_wifi = 1;
2054 }
2055
0e5d435a
JS		 2056 switch (priv->rtlchip) {
2057 case 0x8188e:
2058 case 0x8192e:
2059 case 0x8723b:
2060 switch (val32 & SYS_CFG_VENDOR_EXT_MASK) {
2061 case SYS_CFG_VENDOR_ID_TSMC:
2062 sprintf(priv->chip_vendor, "TSMC");
2063 break;
2064 case SYS_CFG_VENDOR_ID_SMIC:
2065 sprintf(priv->chip_vendor, "SMIC");
2066 priv->vendor_smic = 1;
2067 break;
2068 case SYS_CFG_VENDOR_ID_UMC:
2069 sprintf(priv->chip_vendor, "UMC");
2070 priv->vendor_umc = 1;
2071 break;
2072 default:
2073 sprintf(priv->chip_vendor, "unknown");
2074 }
2075 break;
2076 default:
2077 if (val32 & SYS_CFG_VENDOR_ID) {
2078 sprintf(priv->chip_vendor, "UMC");
2079 priv->vendor_umc = 1;
2080 } else {
2081 sprintf(priv->chip_vendor, "TSMC");
2082 }
2083 }
26f1fad2
JS		 2084
2085 val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS);
2086 priv->rom_rev = (val32 & GPIO_RF_RL_ID) >> 28;
2087
2088 val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX);
2089 if (val16 & NORMAL_SIE_EP_TX_HIGH_MASK) {
2090 priv->ep_tx_high_queue = 1;
2091 priv->ep_tx_count++;
2092 }
2093
2094 if (val16 & NORMAL_SIE_EP_TX_NORMAL_MASK) {
2095 priv->ep_tx_normal_queue = 1;
2096 priv->ep_tx_count++;
2097 }
2098
2099 if (val16 & NORMAL_SIE_EP_TX_LOW_MASK) {
2100 priv->ep_tx_low_queue = 1;
2101 priv->ep_tx_count++;
2102 }
2103
2104 /*
2105 * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX
2106 */
2107 if (!priv->ep_tx_count) {
2108 switch (priv->nr_out_eps) {
35a741fe 2109 case 4:
26f1fad2
JS		 2110 case 3:
2111 priv->ep_tx_low_queue = 1;
2112 priv->ep_tx_count++;
2113 case 2:
2114 priv->ep_tx_normal_queue = 1;
2115 priv->ep_tx_count++;
2116 case 1:
2117 priv->ep_tx_high_queue = 1;
2118 priv->ep_tx_count++;
2119 break;
2120 default:
2121 dev_info(dev, "Unsupported USB TX end-points\n");
2122 return -ENOTSUPP;
2123 }
2124 }
2125
2126 return 0;
2127}
2128
2129static int rtl8723au_parse_efuse(struct rtl8xxxu_priv *priv)
2130{
d38f1c37
JS		 2131 struct rtl8723au_efuse *efuse = &priv->efuse_wifi.efuse8723;
2132
2133 if (efuse->rtl_id != cpu_to_le16(0x8129))
26f1fad2
JS		 2134 return -EINVAL;
2135
d38f1c37 2136 ether_addr_copy(priv->mac_addr, efuse->mac_addr);
26f1fad2
JS		 2137
2138 memcpy(priv->cck_tx_power_index_A,
d38f1c37 2139 efuse->cck_tx_power_index_A,
26f1fad2
JS		 2140 sizeof(priv->cck_tx_power_index_A));
2141 memcpy(priv->cck_tx_power_index_B,
d38f1c37 2142 efuse->cck_tx_power_index_B,
26f1fad2
JS		 2143 sizeof(priv->cck_tx_power_index_B));
2144
2145 memcpy(priv->ht40_1s_tx_power_index_A,
d38f1c37 2146 efuse->ht40_1s_tx_power_index_A,
26f1fad2
JS		 2147 sizeof(priv->ht40_1s_tx_power_index_A));
2148 memcpy(priv->ht40_1s_tx_power_index_B,
d38f1c37 2149 efuse->ht40_1s_tx_power_index_B,
26f1fad2
JS		 2150 sizeof(priv->ht40_1s_tx_power_index_B));
2151
2152 memcpy(priv->ht20_tx_power_index_diff,
d38f1c37 2153 efuse->ht20_tx_power_index_diff,
26f1fad2
JS		 2154 sizeof(priv->ht20_tx_power_index_diff));
2155 memcpy(priv->ofdm_tx_power_index_diff,
d38f1c37 2156 efuse->ofdm_tx_power_index_diff,
26f1fad2
JS		 2157 sizeof(priv->ofdm_tx_power_index_diff));
2158
2159 memcpy(priv->ht40_max_power_offset,
d38f1c37 2160 efuse->ht40_max_power_offset,
26f1fad2
JS		 2161 sizeof(priv->ht40_max_power_offset));
2162 memcpy(priv->ht20_max_power_offset,
d38f1c37 2163 efuse->ht20_max_power_offset,
26f1fad2
JS		 2164 sizeof(priv->ht20_max_power_offset));
2165
2166 dev_info(&priv->udev->dev, "Vendor: %.7s\n",
d38f1c37 2167 efuse->vendor_name);
26f1fad2 2168 dev_info(&priv->udev->dev, "Product: %.41s\n",
d38f1c37 2169 efuse->device_name);
26f1fad2
JS		 2170 return 0;
2171}
2172
3c836d60
JS		 2173static int rtl8723bu_parse_efuse(struct rtl8xxxu_priv *priv)
2174{
b8ba8602
JS		 2175 struct rtl8723bu_efuse *efuse = &priv->efuse_wifi.efuse8723bu;
2176
2177 if (efuse->rtl_id != cpu_to_le16(0x8129))
3c836d60
JS		 2178 return -EINVAL;
2179
b8ba8602 2180 ether_addr_copy(priv->mac_addr, efuse->mac_addr);
3c836d60 2181
b8ba8602 2182 memcpy(priv->cck_tx_power_index_A, efuse->cck_tx_power_index_A,
3c836d60 2183 sizeof(priv->cck_tx_power_index_A));
b8ba8602 2184 memcpy(priv->cck_tx_power_index_B, efuse->cck_tx_power_index_B,
3c836d60
JS		 2185 sizeof(priv->cck_tx_power_index_B));
2186
b8ba8602 2187 memcpy(priv->ht40_1s_tx_power_index_A, efuse->ht40_1s_tx_power_index_A,
3c836d60 2188 sizeof(priv->ht40_1s_tx_power_index_A));
b8ba8602 2189 memcpy(priv->ht40_1s_tx_power_index_B, efuse->ht40_1s_tx_power_index_B,
3c836d60
JS		 2190 sizeof(priv->ht40_1s_tx_power_index_B));
2191
b8ba8602
JS		 2192 dev_info(&priv->udev->dev, "Vendor: %.7s\n", efuse->vendor_name);
2193 dev_info(&priv->udev->dev, "Product: %.41s\n", efuse->device_name);
3c836d60
JS		 2194
2195 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
2196 int i;
2197 unsigned char *raw = priv->efuse_wifi.raw;
2198
2199 dev_info(&priv->udev->dev,
2200 "%s: dumping efuse (0x%02zx bytes):\n",
2201 __func__, sizeof(struct rtl8723bu_efuse));
2202 for (i = 0; i < sizeof(struct rtl8723bu_efuse); i += 8) {
2203 dev_info(&priv->udev->dev, "%02x: "
2204 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
2205 raw[i], raw[i + 1], raw[i + 2],
2206 raw[i + 3], raw[i + 4], raw[i + 5],
2207 raw[i + 6], raw[i + 7]);
2208 }
2209 }
2210
2211 return 0;
2212}
2213
c0963772
KV		 2214#ifdef CONFIG_RTL8XXXU_UNTESTED
2215
26f1fad2
JS		 2216static int rtl8192cu_parse_efuse(struct rtl8xxxu_priv *priv)
2217{
49594441 2218 struct rtl8192cu_efuse *efuse = &priv->efuse_wifi.efuse8192;
26f1fad2
JS		 2219 int i;
2220
49594441 2221 if (efuse->rtl_id != cpu_to_le16(0x8129))
26f1fad2
JS		 2222 return -EINVAL;
2223
49594441 2224 ether_addr_copy(priv->mac_addr, efuse->mac_addr);
26f1fad2
JS		 2225
2226 memcpy(priv->cck_tx_power_index_A,
49594441 2227 efuse->cck_tx_power_index_A,
26f1fad2
JS		 2228 sizeof(priv->cck_tx_power_index_A));
2229 memcpy(priv->cck_tx_power_index_B,
49594441 2230 efuse->cck_tx_power_index_B,
26f1fad2
JS		 2231 sizeof(priv->cck_tx_power_index_B));
2232
2233 memcpy(priv->ht40_1s_tx_power_index_A,
49594441 2234 efuse->ht40_1s_tx_power_index_A,
26f1fad2
JS		 2235 sizeof(priv->ht40_1s_tx_power_index_A));
2236 memcpy(priv->ht40_1s_tx_power_index_B,
49594441 2237 efuse->ht40_1s_tx_power_index_B,
26f1fad2
JS		 2238 sizeof(priv->ht40_1s_tx_power_index_B));
2239 memcpy(priv->ht40_2s_tx_power_index_diff,
49594441 2240 efuse->ht40_2s_tx_power_index_diff,
26f1fad2
JS		 2241 sizeof(priv->ht40_2s_tx_power_index_diff));
2242
2243 memcpy(priv->ht20_tx_power_index_diff,
49594441 2244 efuse->ht20_tx_power_index_diff,
26f1fad2
JS		 2245 sizeof(priv->ht20_tx_power_index_diff));
2246 memcpy(priv->ofdm_tx_power_index_diff,
49594441 2247 efuse->ofdm_tx_power_index_diff,
26f1fad2
JS		 2248 sizeof(priv->ofdm_tx_power_index_diff));
2249
2250 memcpy(priv->ht40_max_power_offset,
49594441 2251 efuse->ht40_max_power_offset,
26f1fad2
JS		 2252 sizeof(priv->ht40_max_power_offset));
2253 memcpy(priv->ht20_max_power_offset,
49594441 2254 efuse->ht20_max_power_offset,
26f1fad2
JS		 2255 sizeof(priv->ht20_max_power_offset));
2256
2257 dev_info(&priv->udev->dev, "Vendor: %.7s\n",
49594441 2258 efuse->vendor_name);
26f1fad2 2259 dev_info(&priv->udev->dev, "Product: %.20s\n",
49594441 2260 efuse->device_name);
26f1fad2 2261
49594441 2262 if (efuse->rf_regulatory & 0x20) {
26f1fad2
JS		 2263 sprintf(priv->chip_name, "8188RU");
2264 priv->hi_pa = 1;
2265 }
2266
2267 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
2268 unsigned char *raw = priv->efuse_wifi.raw;
2269
2270 dev_info(&priv->udev->dev,
2271 "%s: dumping efuse (0x%02zx bytes):\n",
2272 __func__, sizeof(struct rtl8192cu_efuse));
2273 for (i = 0; i < sizeof(struct rtl8192cu_efuse); i += 8) {
2274 dev_info(&priv->udev->dev, "%02x: "
2275 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
2276 raw[i], raw[i + 1], raw[i + 2],
2277 raw[i + 3], raw[i + 4], raw[i + 5],
2278 raw[i + 6], raw[i + 7]);
2279 }
2280 }
2281 return 0;
2282}
2283
c0963772
KV		 2284#endif
2285
3307d840
JS		 2286static int rtl8192eu_parse_efuse(struct rtl8xxxu_priv *priv)
2287{
b7dda34d 2288 struct rtl8192eu_efuse *efuse = &priv->efuse_wifi.efuse8192eu;
3307d840
JS		 2289 int i;
2290
b7dda34d 2291 if (efuse->rtl_id != cpu_to_le16(0x8129))
3307d840
JS		 2292 return -EINVAL;
2293
b7dda34d 2294 ether_addr_copy(priv->mac_addr, efuse->mac_addr);
3307d840 2295
b7dda34d 2296 memcpy(priv->cck_tx_power_index_A, efuse->cck_tx_power_index_A,
3307d840 2297 sizeof(priv->cck_tx_power_index_A));
b7dda34d 2298 memcpy(priv->cck_tx_power_index_B, efuse->cck_tx_power_index_B,
3307d840
JS		 2299 sizeof(priv->cck_tx_power_index_B));
2300
b7dda34d 2301 memcpy(priv->ht40_1s_tx_power_index_A, efuse->ht40_1s_tx_power_index_A,
3307d840 2302 sizeof(priv->ht40_1s_tx_power_index_A));
b7dda34d 2303 memcpy(priv->ht40_1s_tx_power_index_B, efuse->ht40_1s_tx_power_index_B,
3307d840
JS		 2304 sizeof(priv->ht40_1s_tx_power_index_B));
2305
b7dda34d
JS		 2306 dev_info(&priv->udev->dev, "Vendor: %.7s\n", efuse->vendor_name);
2307 dev_info(&priv->udev->dev, "Product: %.11s\n", efuse->device_name);
2308 dev_info(&priv->udev->dev, "Serial: %.11s\n", efuse->serial);
3307d840
JS		 2309
2310 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
2311 unsigned char *raw = priv->efuse_wifi.raw;
2312
2313 dev_info(&priv->udev->dev,
2314 "%s: dumping efuse (0x%02zx bytes):\n",
2315 __func__, sizeof(struct rtl8192eu_efuse));
2316 for (i = 0; i < sizeof(struct rtl8192eu_efuse); i += 8) {
2317 dev_info(&priv->udev->dev, "%02x: "
2318 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
2319 raw[i], raw[i + 1], raw[i + 2],
2320 raw[i + 3], raw[i + 4], raw[i + 5],
2321 raw[i + 6], raw[i + 7]);
2322 }
2323 }
0e5d435a 2324 return 0;
3307d840
JS		 2325}
2326
26f1fad2
JS		 2327static int
2328rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data)
2329{
2330 int i;
2331 u8 val8;
2332 u32 val32;
2333
2334 /* Write Address */
2335 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 1, offset & 0xff);
2336 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 2);
2337 val8 &= 0xfc;
2338 val8 |= (offset >> 8) & 0x03;
2339 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 2, val8);
2340
2341 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 3);
2342 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 3, val8 & 0x7f);
2343
2344 /* Poll for data read */
2345 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
2346 for (i = 0; i < RTL8XXXU_MAX_REG_POLL; i++) {
2347 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
2348 if (val32 & BIT(31))
2349 break;
2350 }
2351
2352 if (i == RTL8XXXU_MAX_REG_POLL)
2353 return -EIO;
2354
2355 udelay(50);
2356 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
2357
2358 *data = val32 & 0xff;
2359 return 0;
2360}
2361
2362static int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv)
2363{
2364 struct device *dev = &priv->udev->dev;
2365 int i, ret = 0;
2366 u8 val8, word_mask, header, extheader;
2367 u16 val16, efuse_addr, offset;
2368 u32 val32;
2369
2370 val16 = rtl8xxxu_read16(priv, REG_9346CR);
2371 if (val16 & EEPROM_ENABLE)
2372 priv->has_eeprom = 1;
2373 if (val16 & EEPROM_BOOT)
2374 priv->boot_eeprom = 1;
2375
38451998
JS		 2376 if (priv->is_multi_func) {
2377 val32 = rtl8xxxu_read32(priv, REG_EFUSE_TEST);
2378 val32 = (val32 & ~EFUSE_SELECT_MASK) | EFUSE_WIFI_SELECT;
2379 rtl8xxxu_write32(priv, REG_EFUSE_TEST, val32);
2380 }
26f1fad2
JS		 2381
2382 dev_dbg(dev, "Booting from %s\n",
2383 priv->boot_eeprom ? "EEPROM" : "EFUSE");
2384
2385 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_ENABLE);
2386
2387 /* 1.2V Power: From VDDON with Power Cut(0x0000[15]), default valid */
2388 val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
2389 if (!(val16 & SYS_ISO_PWC_EV12V)) {
2390 val16 |= SYS_ISO_PWC_EV12V;
2391 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
2392 }
2393 /* Reset: 0x0000[28], default valid */
2394 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2395 if (!(val16 & SYS_FUNC_ELDR)) {
2396 val16 |= SYS_FUNC_ELDR;
2397 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2398 }
2399
2400 /*
2401 * Clock: Gated(0x0008[5]) 8M(0x0008[1]) clock from ANA, default valid
2402 */
2403 val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR);
2404 if (!(val16 & SYS_CLK_LOADER_ENABLE) || !(val16 & SYS_CLK_ANA8M)) {
2405 val16 |= (SYS_CLK_LOADER_ENABLE | SYS_CLK_ANA8M);
2406 rtl8xxxu_write16(priv, REG_SYS_CLKR, val16);
2407 }
2408
2409 /* Default value is 0xff */
3307d840 2410 memset(priv->efuse_wifi.raw, 0xff, EFUSE_MAP_LEN);
26f1fad2
JS		 2411
2412 efuse_addr = 0;
2413 while (efuse_addr < EFUSE_REAL_CONTENT_LEN_8723A) {
f6c47702
JS		 2414 u16 map_addr;
2415
26f1fad2
JS		 2416 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &header);
2417 if (ret || header == 0xff)
2418 goto exit;
2419
2420 if ((header & 0x1f) == 0x0f) { /* extended header */
2421 offset = (header & 0xe0) >> 5;
2422
2423 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++,
2424 &extheader);
2425 if (ret)
2426 goto exit;
2427 /* All words disabled */
2428 if ((extheader & 0x0f) == 0x0f)
2429 continue;
2430
2431 offset |= ((extheader & 0xf0) >> 1);
2432 word_mask = extheader & 0x0f;
2433 } else {
2434 offset = (header >> 4) & 0x0f;
2435 word_mask = header & 0x0f;
2436 }
2437
f6c47702
JS		 2438 /* Get word enable value from PG header */
2439
2440 /* We have 8 bits to indicate validity */
2441 map_addr = offset * 8;
2442 if (map_addr >= EFUSE_MAP_LEN) {
2443 dev_warn(dev, "%s: Illegal map_addr (%04x), "
2444 "efuse corrupt!\n",
2445 __func__, map_addr);
26f1fad2
JS		 2446 ret = -EINVAL;
2447 goto exit;
2448 }
f6c47702
JS		 2449 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
2450 /* Check word enable condition in the section */
32a39dd4 2451 if (word_mask & BIT(i)) {
f6c47702 2452 map_addr += 2;
32a39dd4
JS		 2453 continue;
2454 }
2455
2456 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);
2457 if (ret)
2458 goto exit;
2459 priv->efuse_wifi.raw[map_addr++] = val8;
2460
2461 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);
2462 if (ret)
2463 goto exit;
2464 priv->efuse_wifi.raw[map_addr++] = val8;
f6c47702 2465 }
26f1fad2
JS		 2466 }
2467
2468exit:
2469 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_DISABLE);
2470
2471 return ret;
2472}
2473
d48fe60e
JS		 2474static void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv)
2475{
2476 u8 val8;
2477 u16 sys_func;
2478
2479 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
53b381c4 2480 val8 &= ~BIT(0);
d48fe60e
JS		 2481 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
2482 sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2483 sys_func &= ~SYS_FUNC_CPU_ENABLE;
2484 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
2485 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
53b381c4 2486 val8 |= BIT(0);
d48fe60e
JS		 2487 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
2488 sys_func |= SYS_FUNC_CPU_ENABLE;
2489 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
2490}
2491
26f1fad2
JS		 2492static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv *priv)
2493{
2494 struct device *dev = &priv->udev->dev;
2495 int ret = 0, i;
2496 u32 val32;
2497
2498 /* Poll checksum report */
2499 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
2500 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2501 if (val32 & MCU_FW_DL_CSUM_REPORT)
2502 break;
2503 }
2504
2505 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
2506 dev_warn(dev, "Firmware checksum poll timed out\n");
2507 ret = -EAGAIN;
2508 goto exit;
2509 }
2510
2511 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2512 val32 |= MCU_FW_DL_READY;
2513 val32 &= ~MCU_WINT_INIT_READY;
2514 rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
2515
d48fe60e
JS		 2516 /*
2517 * Reset the 8051 in order for the firmware to start running,
2518 * otherwise it won't come up on the 8192eu
2519 */
2520 rtl8xxxu_reset_8051(priv);
2521
26f1fad2
JS		 2522 /* Wait for firmware to become ready */
2523 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
2524 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2525 if (val32 & MCU_WINT_INIT_READY)
2526 break;
2527
2528 udelay(100);
2529 }
2530
2531 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
2532 dev_warn(dev, "Firmware failed to start\n");
2533 ret = -EAGAIN;
2534 goto exit;
2535 }
2536
2537exit:
2538 return ret;
2539}
2540
2541static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv *priv)
2542{
2543 int pages, remainder, i, ret;
d48fe60e 2544 u8 val8;
26f1fad2
JS		 2545 u16 val16;
2546 u32 val32;
2547 u8 *fwptr;
2548
2549 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC + 1);
2550 val8 |= 4;
2551 rtl8xxxu_write8(priv, REG_SYS_FUNC + 1, val8);
2552
2553 /* 8051 enable */
2554 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
43154f6f
JS		 2555 val16 |= SYS_FUNC_CPU_ENABLE;
2556 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
26f1fad2 2557
216202ae
JS		 2558 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2559 if (val8 & MCU_FW_RAM_SEL) {
2560 pr_info("do the RAM reset\n");
2561 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
d48fe60e 2562 rtl8xxxu_reset_8051(priv);
216202ae
JS		 2563 }
2564
26f1fad2
JS		 2565 /* MCU firmware download enable */
2566 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
ef1c0499
JS		 2567 val8 |= MCU_FW_DL_ENABLE;
2568 rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
26f1fad2
JS		 2569
2570 /* 8051 reset */
2571 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
ef1c0499
JS		 2572 val32 &= ~BIT(19);
2573 rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
26f1fad2
JS		 2574
2575 /* Reset firmware download checksum */
2576 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
ef1c0499
JS		 2577 val8 |= MCU_FW_DL_CSUM_REPORT;
2578 rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
26f1fad2
JS		 2579
2580 pages = priv->fw_size / RTL_FW_PAGE_SIZE;
2581 remainder = priv->fw_size % RTL_FW_PAGE_SIZE;
2582
2583 fwptr = priv->fw_data->data;
2584
2585 for (i = 0; i < pages; i++) {
2586 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
ef1c0499
JS		 2587 val8 |= i;
2588 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
26f1fad2
JS		 2589
2590 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2591 fwptr, RTL_FW_PAGE_SIZE);
2592 if (ret != RTL_FW_PAGE_SIZE) {
2593 ret = -EAGAIN;
2594 goto fw_abort;
2595 }
2596
2597 fwptr += RTL_FW_PAGE_SIZE;
2598 }
2599
2600 if (remainder) {
2601 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
ef1c0499
JS		 2602 val8 |= i;
2603 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
26f1fad2
JS		 2604 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2605 fwptr, remainder);
2606 if (ret != remainder) {
2607 ret = -EAGAIN;
2608 goto fw_abort;
2609 }
2610 }
2611
2612 ret = 0;
2613fw_abort:
2614 /* MCU firmware download disable */
2615 val16 = rtl8xxxu_read16(priv, REG_MCU_FW_DL);
ef1c0499
JS		 2616 val16 &= ~MCU_FW_DL_ENABLE;
2617 rtl8xxxu_write16(priv, REG_MCU_FW_DL, val16);
26f1fad2
JS		 2618
2619 return ret;
2620}
2621
2622static int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, char *fw_name)
2623{
2624 struct device *dev = &priv->udev->dev;
2625 const struct firmware *fw;
2626 int ret = 0;
2627 u16 signature;
2628
2629 dev_info(dev, "%s: Loading firmware %s\n", DRIVER_NAME, fw_name);
2630 if (request_firmware(&fw, fw_name, &priv->udev->dev)) {
2631 dev_warn(dev, "request_firmware(%s) failed\n", fw_name);
2632 ret = -EAGAIN;
2633 goto exit;
2634 }
2635 if (!fw) {
2636 dev_warn(dev, "Firmware data not available\n");
2637 ret = -EINVAL;
2638 goto exit;
2639 }
2640
2641 priv->fw_data = kmemdup(fw->data, fw->size, GFP_KERNEL);
98e27cbd
TK		 2642 if (!priv->fw_data) {
2643 ret = -ENOMEM;
2644 goto exit;
2645 }
26f1fad2
JS		 2646 priv->fw_size = fw->size - sizeof(struct rtl8xxxu_firmware_header);
2647
2648 signature = le16_to_cpu(priv->fw_data->signature);
2649 switch (signature & 0xfff0) {
0e5d435a 2650 case 0x92e0:
26f1fad2
JS		 2651 case 0x92c0:
2652 case 0x88c0:
35a741fe 2653 case 0x5300:
26f1fad2
JS		 2654 case 0x2300:
2655 break;
2656 default:
2657 ret = -EINVAL;
2658 dev_warn(dev, "%s: Invalid firmware signature: 0x%04x\n",
2659 __func__, signature);
2660 }
2661
2662 dev_info(dev, "Firmware revision %i.%i (signature 0x%04x)\n",
2663 le16_to_cpu(priv->fw_data->major_version),
2664 priv->fw_data->minor_version, signature);
2665
2666exit:
2667 release_firmware(fw);
2668 return ret;
2669}
2670
2671static int rtl8723au_load_firmware(struct rtl8xxxu_priv *priv)
2672{
2673 char *fw_name;
2674 int ret;
2675
2676 switch (priv->chip_cut) {
2677 case 0:
2678 fw_name = "rtlwifi/rtl8723aufw_A.bin";
2679 break;
2680 case 1:
2681 if (priv->enable_bluetooth)
2682 fw_name = "rtlwifi/rtl8723aufw_B.bin";
2683 else
2684 fw_name = "rtlwifi/rtl8723aufw_B_NoBT.bin";
2685
2686 break;
2687 default:
2688 return -EINVAL;
2689 }
2690
2691 ret = rtl8xxxu_load_firmware(priv, fw_name);
2692 return ret;
2693}
2694
35a741fe
JS		 2695static int rtl8723bu_load_firmware(struct rtl8xxxu_priv *priv)
2696{
2697 char *fw_name;
2698 int ret;
2699
2700 if (priv->enable_bluetooth)
2701 fw_name = "rtlwifi/rtl8723bu_bt.bin";
2702 else
2703 fw_name = "rtlwifi/rtl8723bu_nic.bin";
2704
2705 ret = rtl8xxxu_load_firmware(priv, fw_name);
2706 return ret;
2707}
2708
c0963772
KV		 2709#ifdef CONFIG_RTL8XXXU_UNTESTED
2710
26f1fad2
JS		 2711static int rtl8192cu_load_firmware(struct rtl8xxxu_priv *priv)
2712{
2713 char *fw_name;
2714 int ret;
2715
2716 if (!priv->vendor_umc)
2717 fw_name = "rtlwifi/rtl8192cufw_TMSC.bin";
2718 else if (priv->chip_cut || priv->rtlchip == 0x8192c)
2719 fw_name = "rtlwifi/rtl8192cufw_B.bin";
2720 else
2721 fw_name = "rtlwifi/rtl8192cufw_A.bin";
2722
2723 ret = rtl8xxxu_load_firmware(priv, fw_name);
2724
2725 return ret;
2726}
2727
c0963772
KV		 2728#endif
2729
3307d840
JS		 2730static int rtl8192eu_load_firmware(struct rtl8xxxu_priv *priv)
2731{
2732 char *fw_name;
2733 int ret;
2734
0e5d435a 2735 fw_name = "rtlwifi/rtl8192eu_nic.bin";
3307d840
JS		 2736
2737 ret = rtl8xxxu_load_firmware(priv, fw_name);
2738
2739 return ret;
2740}
2741
26f1fad2
JS		 2742static void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv)
2743{
2744 u16 val16;
2745 int i = 100;
2746
2747 /* Inform 8051 to perform reset */
2748 rtl8xxxu_write8(priv, REG_HMTFR + 3, 0x20);
2749
2750 for (i = 100; i > 0; i--) {
2751 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2752
2753 if (!(val16 & SYS_FUNC_CPU_ENABLE)) {
2754 dev_dbg(&priv->udev->dev,
2755 "%s: Firmware self reset success!\n", __func__);
2756 break;
2757 }
2758 udelay(50);
2759 }
2760
2761 if (!i) {
2762 /* Force firmware reset */
2763 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2764 val16 &= ~SYS_FUNC_CPU_ENABLE;
2765 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2766 }
2767}
2768
f0d9f5e9
JS		 2769static void rtl8723bu_phy_init_antenna_selection(struct rtl8xxxu_priv *priv)
2770{
2771 u32 val32;
2772
2773 val32 = rtl8xxxu_read32(priv, 0x64);
2774 val32 &= ~(BIT(20) | BIT(24));
2775 rtl8xxxu_write32(priv, 0x64, val32);
2776
2777 val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG);
2778 val32 &= ~BIT(4);
2779 val32 |= BIT(3);
2780 rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32);
2781
2782 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
2783 val32 &= ~BIT(23);
2784 val32 |= BIT(24);
2785 rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
2786
2787 val32 = rtl8xxxu_read32(priv, 0x0944);
2788 val32 |= (BIT(0) | BIT(1));
2789 rtl8xxxu_write32(priv, 0x0944, val32);
2790
2791 val32 = rtl8xxxu_read32(priv, 0x0930);
2792 val32 &= 0xffffff00;
2793 val32 |= 0x77;
2794 rtl8xxxu_write32(priv, 0x0930, val32);
2795
2796 val32 = rtl8xxxu_read32(priv, REG_PWR_DATA);
2797 val32 |= BIT(11);
2798 rtl8xxxu_write32(priv, REG_PWR_DATA, val32);
2799}
2800
26f1fad2
JS		 2801static int
2802rtl8xxxu_init_mac(struct rtl8xxxu_priv *priv, struct rtl8xxxu_reg8val *array)
2803{
2804 int i, ret;
2805 u16 reg;
2806 u8 val;
2807
2808 for (i = 0; ; i++) {
2809 reg = array[i].reg;
2810 val = array[i].val;
2811
2812 if (reg == 0xffff && val == 0xff)
2813 break;
2814
2815 ret = rtl8xxxu_write8(priv, reg, val);
2816 if (ret != 1) {
2817 dev_warn(&priv->udev->dev,
2818 "Failed to initialize MAC\n");
2819 return -EAGAIN;
2820 }
2821 }
2822
2823 rtl8xxxu_write8(priv, REG_MAX_AGGR_NUM, 0x0a);
2824
2825 return 0;
2826}
2827
2828static int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv,
2829 struct rtl8xxxu_reg32val *array)
2830{
2831 int i, ret;
2832 u16 reg;
2833 u32 val;
2834
2835 for (i = 0; ; i++) {
2836 reg = array[i].reg;
2837 val = array[i].val;
2838
2839 if (reg == 0xffff && val == 0xffffffff)
2840 break;
2841
2842 ret = rtl8xxxu_write32(priv, reg, val);
2843 if (ret != sizeof(val)) {
2844 dev_warn(&priv->udev->dev,
2845 "Failed to initialize PHY\n");
2846 return -EAGAIN;
2847 }
2848 udelay(1);
2849 }
2850
2851 return 0;
2852}
2853
2854/*
2855 * Most of this is black magic retrieved from the old rtl8723au driver
2856 */
2857static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv *priv)
2858{
2859 u8 val8, ldoa15, ldov12d, lpldo, ldohci12;
2860 u32 val32;
2861
2862 /*
2863 * Todo: The vendor driver maintains a table of PHY register
2864 * addresses, which is initialized here. Do we need this?
2865 */
2866
2867 val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);
2868 udelay(2);
2869 val8 |= AFE_PLL_320_ENABLE;
2870 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);
2871 udelay(2);
2872
2873 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL + 1, 0xff);
2874 udelay(2);
2875
2876 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
2877 val8 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB;
2878 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
2879
2880 /* AFE_XTAL_RF_GATE (bit 14) if addressing as 32 bit register */
2881 val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL);
2882 val32 &= ~AFE_XTAL_RF_GATE;
2883 if (priv->has_bluetooth)
2884 val32 &= ~AFE_XTAL_BT_GATE;
2885 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32);
2886
2887 /* 6. 0x1f[7:0] = 0x07 */
2888 val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
2889 rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
2890
2891 if (priv->hi_pa)
2892 rtl8xxxu_init_phy_regs(priv, rtl8188ru_phy_1t_highpa_table);
2893 else if (priv->tx_paths == 2)
2894 rtl8xxxu_init_phy_regs(priv, rtl8192cu_phy_2t_init_table);
36c32588
JS		 2895 else if (priv->rtlchip == 0x8723b)
2896 rtl8xxxu_init_phy_regs(priv, rtl8723b_phy_1t_init_table);
26f1fad2
JS		 2897 else
2898 rtl8xxxu_init_phy_regs(priv, rtl8723a_phy_1t_init_table);
2899
2900
2901 if (priv->rtlchip == 0x8188c && priv->hi_pa &&
2902 priv->vendor_umc && priv->chip_cut == 1)
2903 rtl8xxxu_write8(priv, REG_OFDM0_AGC_PARM1 + 2, 0x50);
2904
2905 if (priv->tx_paths == 1 && priv->rx_paths == 2) {
2906 /*
2907 * For 1T2R boards, patch the registers.
2908 *
2909 * It looks like 8191/2 1T2R boards use path B for TX
2910 */
2911 val32 = rtl8xxxu_read32(priv, REG_FPGA0_TX_INFO);
2912 val32 &= ~(BIT(0) | BIT(1));
2913 val32 |= BIT(1);
2914 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, val32);
2915
2916 val32 = rtl8xxxu_read32(priv, REG_FPGA1_TX_INFO);
2917 val32 &= ~0x300033;
2918 val32 |= 0x200022;
2919 rtl8xxxu_write32(priv, REG_FPGA1_TX_INFO, val32);
2920
2921 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
2922 val32 &= 0xff000000;
2923 val32 |= 0x45000000;
2924 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
2925
2926 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
2927 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK);
2928 val32 |= (OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B |
2929 OFDM_RF_PATH_TX_B);
2930 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
2931
2932 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_PARM1);
2933 val32 &= ~(BIT(4) | BIT(5));
2934 val32 |= BIT(4);
2935 rtl8xxxu_write32(priv, REG_OFDM0_AGC_PARM1, val32);
2936
2937 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_RFON);
2938 val32 &= ~(BIT(27) | BIT(26));
2939 val32 |= BIT(27);
2940 rtl8xxxu_write32(priv, REG_TX_CCK_RFON, val32);
2941
2942 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_BBON);
2943 val32 &= ~(BIT(27) | BIT(26));
2944 val32 |= BIT(27);
2945 rtl8xxxu_write32(priv, REG_TX_CCK_BBON, val32);
2946
2947 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_RFON);
2948 val32 &= ~(BIT(27) | BIT(26));
2949 val32 |= BIT(27);
2950 rtl8xxxu_write32(priv, REG_TX_OFDM_RFON, val32);
2951
2952 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_BBON);
2953 val32 &= ~(BIT(27) | BIT(26));
2954 val32 |= BIT(27);
2955 rtl8xxxu_write32(priv, REG_TX_OFDM_BBON, val32);
2956
2957 val32 = rtl8xxxu_read32(priv, REG_TX_TO_TX);
2958 val32 &= ~(BIT(27) | BIT(26));
2959 val32 |= BIT(27);
2960 rtl8xxxu_write32(priv, REG_TX_TO_TX, val32);
2961 }
2962
b9f498e1
JS		 2963 if (priv->rtlchip == 0x8723b)
2964 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8723bu_table);
2965 else if (priv->hi_pa)
26f1fad2
JS		 2966 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_highpa_table);
2967 else
2968 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_standard_table);
2969
35a741fe 2970 if ((priv->rtlchip == 0x8723a || priv->rtlchip == 0x8723b) &&
26f1fad2
JS		 2971 priv->efuse_wifi.efuse8723.version >= 0x01) {
2972 val32 = rtl8xxxu_read32(priv, REG_MAC_PHY_CTRL);
2973
2974 val8 = priv->efuse_wifi.efuse8723.xtal_k & 0x3f;
2975 val32 &= 0xff000fff;
2976 val32 |= ((val8 | (val8 << 6)) << 12);
2977
2978 rtl8xxxu_write32(priv, REG_MAC_PHY_CTRL, val32);
2979 }
2980
2981 ldoa15 = LDOA15_ENABLE | LDOA15_OBUF;
2982 ldov12d = LDOV12D_ENABLE | BIT(2) | (2 << LDOV12D_VADJ_SHIFT);
2983 ldohci12 = 0x57;
2984 lpldo = 1;
2985 val32 = (lpldo << 24) | (ldohci12 << 16) | (ldov12d << 8) | ldoa15;
2986
2987 rtl8xxxu_write32(priv, REG_LDOA15_CTRL, val32);
2988
2989 return 0;
2990}
2991
2992static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv *priv,
2993 struct rtl8xxxu_rfregval *array,
2994 enum rtl8xxxu_rfpath path)
2995{
2996 int i, ret;
2997 u8 reg;
2998 u32 val;
2999
3000 for (i = 0; ; i++) {
3001 reg = array[i].reg;
3002 val = array[i].val;
3003
3004 if (reg == 0xff && val == 0xffffffff)
3005 break;
3006
3007 switch (reg) {
3008 case 0xfe:
3009 msleep(50);
3010 continue;
3011 case 0xfd:
3012 mdelay(5);
3013 continue;
3014 case 0xfc:
3015 mdelay(1);
3016 continue;
3017 case 0xfb:
3018 udelay(50);
3019 continue;
3020 case 0xfa:
3021 udelay(5);
3022 continue;
3023 case 0xf9:
3024 udelay(1);
3025 continue;
3026 }
3027
26f1fad2
JS		 3028 ret = rtl8xxxu_write_rfreg(priv, path, reg, val);
3029 if (ret) {
3030 dev_warn(&priv->udev->dev,
3031 "Failed to initialize RF\n");
3032 return -EAGAIN;
3033 }
3034 udelay(1);
3035 }
3036
3037 return 0;
3038}
3039
3040static int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv,
3041 struct rtl8xxxu_rfregval *table,
3042 enum rtl8xxxu_rfpath path)
3043{
3044 u32 val32;
3045 u16 val16, rfsi_rfenv;
3046 u16 reg_sw_ctrl, reg_int_oe, reg_hssi_parm2;
3047
3048 switch (path) {
3049 case RF_A:
3050 reg_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL;
3051 reg_int_oe = REG_FPGA0_XA_RF_INT_OE;
3052 reg_hssi_parm2 = REG_FPGA0_XA_HSSI_PARM2;
3053 break;
3054 case RF_B:
3055 reg_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL;
3056 reg_int_oe = REG_FPGA0_XB_RF_INT_OE;
3057 reg_hssi_parm2 = REG_FPGA0_XB_HSSI_PARM2;
3058 break;
3059 default:
3060 dev_err(&priv->udev->dev, "%s:Unsupported RF path %c\n",
3061 __func__, path + 'A');
3062 return -EINVAL;
3063 }
3064 /* For path B, use XB */
3065 rfsi_rfenv = rtl8xxxu_read16(priv, reg_sw_ctrl);
3066 rfsi_rfenv &= FPGA0_RF_RFENV;
3067
3068 /*
3069 * These two we might be able to optimize into one
3070 */
3071 val32 = rtl8xxxu_read32(priv, reg_int_oe);
3072 val32 |= BIT(20); /* 0x10 << 16 */
3073 rtl8xxxu_write32(priv, reg_int_oe, val32);
3074 udelay(1);
3075
3076 val32 = rtl8xxxu_read32(priv, reg_int_oe);
3077 val32 |= BIT(4);
3078 rtl8xxxu_write32(priv, reg_int_oe, val32);
3079 udelay(1);
3080
3081 /*
3082 * These two we might be able to optimize into one
3083 */
3084 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
3085 val32 &= ~FPGA0_HSSI_3WIRE_ADDR_LEN;
3086 rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
3087 udelay(1);
3088
3089 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
3090 val32 &= ~FPGA0_HSSI_3WIRE_DATA_LEN;
3091 rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
3092 udelay(1);
3093
3094 rtl8xxxu_init_rf_regs(priv, table, path);
3095
3096 /* For path B, use XB */
3097 val16 = rtl8xxxu_read16(priv, reg_sw_ctrl);
3098 val16 &= ~FPGA0_RF_RFENV;
3099 val16 |= rfsi_rfenv;
3100 rtl8xxxu_write16(priv, reg_sw_ctrl, val16);
3101
3102 return 0;
3103}
3104
3105static int rtl8xxxu_llt_write(struct rtl8xxxu_priv *priv, u8 address, u8 data)
3106{
3107 int ret = -EBUSY;
3108 int count = 0;
3109 u32 value;
3110
3111 value = LLT_OP_WRITE | address << 8 | data;
3112
3113 rtl8xxxu_write32(priv, REG_LLT_INIT, value);
3114
3115 do {
3116 value = rtl8xxxu_read32(priv, REG_LLT_INIT);
3117 if ((value & LLT_OP_MASK) == LLT_OP_INACTIVE) {
3118 ret = 0;
3119 break;
3120 }
3121 } while (count++ < 20);
3122
3123 return ret;
3124}
3125
3126static int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page)
3127{
3128 int ret;
3129 int i;
3130
3131 for (i = 0; i < last_tx_page; i++) {
3132 ret = rtl8xxxu_llt_write(priv, i, i + 1);
3133 if (ret)
3134 goto exit;
3135 }
3136
3137 ret = rtl8xxxu_llt_write(priv, last_tx_page, 0xff);
3138 if (ret)
3139 goto exit;
3140
3141 /* Mark remaining pages as a ring buffer */
3142 for (i = last_tx_page + 1; i < 0xff; i++) {
3143 ret = rtl8xxxu_llt_write(priv, i, (i + 1));
3144 if (ret)
3145 goto exit;
3146 }
3147
3148 /* Let last entry point to the start entry of ring buffer */
3149 ret = rtl8xxxu_llt_write(priv, 0xff, last_tx_page + 1);
3150 if (ret)
3151 goto exit;
3152
3153exit:
3154 return ret;
3155}
3156
74b99bed
JS		 3157static int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page)
3158{
3159 u32 val32;
3160 int ret = 0;
3161 int i;
3162
3163 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
74b99bed
JS		 3164 val32 |= AUTO_LLT_INIT_LLT;
3165 rtl8xxxu_write32(priv, REG_AUTO_LLT, val32);
3166
3167 for (i = 500; i; i--) {
3168 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
3169 if (!(val32 & AUTO_LLT_INIT_LLT))
3170 break;
3171 usleep_range(2, 4);
3172 }
3173
4de24819 3174 if (!i) {
74b99bed
JS		 3175 ret = -EBUSY;
3176 dev_warn(&priv->udev->dev, "LLT table init failed\n");
3177 }
74b99bed
JS		 3178
3179 return ret;
3180}
3181
26f1fad2
JS		 3182static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv *priv)
3183{
3184 u16 val16, hi, lo;
3185 u16 hiq, mgq, bkq, beq, viq, voq;
3186 int hip, mgp, bkp, bep, vip, vop;
3187 int ret = 0;
3188
3189 switch (priv->ep_tx_count) {
3190 case 1:
3191 if (priv->ep_tx_high_queue) {
3192 hi = TRXDMA_QUEUE_HIGH;
3193 } else if (priv->ep_tx_low_queue) {
3194 hi = TRXDMA_QUEUE_LOW;
3195 } else if (priv->ep_tx_normal_queue) {
3196 hi = TRXDMA_QUEUE_NORMAL;
3197 } else {
3198 hi = 0;
3199 ret = -EINVAL;
3200 }
3201
3202 hiq = hi;
3203 mgq = hi;
3204 bkq = hi;
3205 beq = hi;
3206 viq = hi;
3207 voq = hi;
3208
3209 hip = 0;
3210 mgp = 0;
3211 bkp = 0;
3212 bep = 0;
3213 vip = 0;
3214 vop = 0;
3215 break;
3216 case 2:
3217 if (priv->ep_tx_high_queue && priv->ep_tx_low_queue) {
3218 hi = TRXDMA_QUEUE_HIGH;
3219 lo = TRXDMA_QUEUE_LOW;
3220 } else if (priv->ep_tx_normal_queue && priv->ep_tx_low_queue) {
3221 hi = TRXDMA_QUEUE_NORMAL;
3222 lo = TRXDMA_QUEUE_LOW;
3223 } else if (priv->ep_tx_high_queue && priv->ep_tx_normal_queue) {
3224 hi = TRXDMA_QUEUE_HIGH;
3225 lo = TRXDMA_QUEUE_NORMAL;
3226 } else {
3227 ret = -EINVAL;
3228 hi = 0;
3229 lo = 0;
3230 }
3231
3232 hiq = hi;
3233 mgq = hi;
3234 bkq = lo;
3235 beq = lo;
3236 viq = hi;
3237 voq = hi;
3238
3239 hip = 0;
3240 mgp = 0;
3241 bkp = 1;
3242 bep = 1;
3243 vip = 0;
3244 vop = 0;
3245 break;
3246 case 3:
3247 beq = TRXDMA_QUEUE_LOW;
3248 bkq = TRXDMA_QUEUE_LOW;
3249 viq = TRXDMA_QUEUE_NORMAL;
3250 voq = TRXDMA_QUEUE_HIGH;
3251 mgq = TRXDMA_QUEUE_HIGH;
3252 hiq = TRXDMA_QUEUE_HIGH;
3253
3254 hip = hiq ^ 3;
3255 mgp = mgq ^ 3;
3256 bkp = bkq ^ 3;
3257 bep = beq ^ 3;
3258 vip = viq ^ 3;
3259 vop = viq ^ 3;
3260 break;
3261 default:
3262 ret = -EINVAL;
3263 }
3264
3265 /*
3266 * None of the vendor drivers are configuring the beacon
3267 * queue here .... why?
3268 */
3269 if (!ret) {
3270 val16 = rtl8xxxu_read16(priv, REG_TRXDMA_CTRL);
3271 val16 &= 0x7;
3272 val16 |= (voq << TRXDMA_CTRL_VOQ_SHIFT) |
3273 (viq << TRXDMA_CTRL_VIQ_SHIFT) |
3274 (beq << TRXDMA_CTRL_BEQ_SHIFT) |
3275 (bkq << TRXDMA_CTRL_BKQ_SHIFT) |
3276 (mgq << TRXDMA_CTRL_MGQ_SHIFT) |
3277 (hiq << TRXDMA_CTRL_HIQ_SHIFT);
3278 rtl8xxxu_write16(priv, REG_TRXDMA_CTRL, val16);
3279
3280 priv->pipe_out[TXDESC_QUEUE_VO] =
3281 usb_sndbulkpipe(priv->udev, priv->out_ep[vop]);
3282 priv->pipe_out[TXDESC_QUEUE_VI] =
3283 usb_sndbulkpipe(priv->udev, priv->out_ep[vip]);
3284 priv->pipe_out[TXDESC_QUEUE_BE] =
3285 usb_sndbulkpipe(priv->udev, priv->out_ep[bep]);
3286 priv->pipe_out[TXDESC_QUEUE_BK] =
3287 usb_sndbulkpipe(priv->udev, priv->out_ep[bkp]);
3288 priv->pipe_out[TXDESC_QUEUE_BEACON] =
3289 usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
3290 priv->pipe_out[TXDESC_QUEUE_MGNT] =
3291 usb_sndbulkpipe(priv->udev, priv->out_ep[mgp]);
3292 priv->pipe_out[TXDESC_QUEUE_HIGH] =
3293 usb_sndbulkpipe(priv->udev, priv->out_ep[hip]);
3294 priv->pipe_out[TXDESC_QUEUE_CMD] =
3295 usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
3296 }
3297
3298 return ret;
3299}
3300
3301static void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv,
3302 bool iqk_ok, int result[][8],
3303 int candidate, bool tx_only)
3304{
3305 u32 oldval, x, tx0_a, reg;
3306 int y, tx0_c;
3307 u32 val32;
3308
3309 if (!iqk_ok)
3310 return;
3311
3312 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
3313 oldval = val32 >> 22;
3314
3315 x = result[candidate][0];
3316 if ((x & 0x00000200) != 0)
3317 x = x | 0xfffffc00;
3318 tx0_a = (x * oldval) >> 8;
3319
3320 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
3321 val32 &= ~0x3ff;
3322 val32 |= tx0_a;
3323 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
3324
3325 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3326 val32 &= ~BIT(31);
3327 if ((x * oldval >> 7) & 0x1)
3328 val32 |= BIT(31);
3329 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3330
3331 y = result[candidate][1];
3332 if ((y & 0x00000200) != 0)
3333 y = y | 0xfffffc00;
3334 tx0_c = (y * oldval) >> 8;
3335
3336 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XC_TX_AFE);
3337 val32 &= ~0xf0000000;
3338 val32 |= (((tx0_c & 0x3c0) >> 6) << 28);
3339 rtl8xxxu_write32(priv, REG_OFDM0_XC_TX_AFE, val32);
3340
3341 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
3342 val32 &= ~0x003f0000;
3343 val32 |= ((tx0_c & 0x3f) << 16);
3344 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
3345
3346 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3347 val32 &= ~BIT(29);
3348 if ((y * oldval >> 7) & 0x1)
3349 val32 |= BIT(29);
3350 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3351
3352 if (tx_only) {
3353 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
3354 return;
3355 }
3356
3357 reg = result[candidate][2];
3358
3359 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
3360 val32 &= ~0x3ff;
3361 val32 |= (reg & 0x3ff);
3362 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
3363
3364 reg = result[candidate][3] & 0x3F;
3365
3366 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
3367 val32 &= ~0xfc00;
3368 val32 |= ((reg << 10) & 0xfc00);
3369 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
3370
3371 reg = (result[candidate][3] >> 6) & 0xF;
3372
3373 val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_IQ_EXT_ANTA);
3374 val32 &= ~0xf0000000;
3375 val32 |= (reg << 28);
3376 rtl8xxxu_write32(priv, REG_OFDM0_RX_IQ_EXT_ANTA, val32);
3377}
3378
3379static void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv,
3380 bool iqk_ok, int result[][8],
3381 int candidate, bool tx_only)
3382{
3383 u32 oldval, x, tx1_a, reg;
3384 int y, tx1_c;
3385 u32 val32;
3386
3387 if (!iqk_ok)
3388 return;
3389
3390 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
3391 oldval = val32 >> 22;
3392
3393 x = result[candidate][4];
3394 if ((x & 0x00000200) != 0)
3395 x = x | 0xfffffc00;
3396 tx1_a = (x * oldval) >> 8;
3397
3398 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
3399 val32 &= ~0x3ff;
3400 val32 |= tx1_a;
3401 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
3402
3403 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3404 val32 &= ~BIT(27);
3405 if ((x * oldval >> 7) & 0x1)
3406 val32 |= BIT(27);
3407 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3408
3409 y = result[candidate][5];
3410 if ((y & 0x00000200) != 0)
3411 y = y | 0xfffffc00;
3412 tx1_c = (y * oldval) >> 8;
3413
3414 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XD_TX_AFE);
3415 val32 &= ~0xf0000000;
3416 val32 |= (((tx1_c & 0x3c0) >> 6) << 28);
3417 rtl8xxxu_write32(priv, REG_OFDM0_XD_TX_AFE, val32);
3418
3419 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
3420 val32 &= ~0x003f0000;
3421 val32 |= ((tx1_c & 0x3f) << 16);
3422 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
3423
3424 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3425 val32 &= ~BIT(25);
3426 if ((y * oldval >> 7) & 0x1)
3427 val32 |= BIT(25);
3428 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3429
3430 if (tx_only) {
3431 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
3432 return;
3433 }
3434
3435 reg = result[candidate][6];
3436
3437 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
3438 val32 &= ~0x3ff;
3439 val32 |= (reg & 0x3ff);
3440 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
3441
3442 reg = result[candidate][7] & 0x3f;
3443
3444 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
3445 val32 &= ~0xfc00;
3446 val32 |= ((reg << 10) & 0xfc00);
3447 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
3448
3449 reg = (result[candidate][7] >> 6) & 0xf;
3450
3451 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGCR_SSI_TABLE);
3452 val32 &= ~0x0000f000;
3453 val32 |= (reg << 12);
3454 rtl8xxxu_write32(priv, REG_OFDM0_AGCR_SSI_TABLE, val32);
3455}
3456
3457#define MAX_TOLERANCE 5
3458
3459static bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv,
3460 int result[][8], int c1, int c2)
3461{
3462 u32 i, j, diff, simubitmap, bound = 0;
3463 int candidate[2] = {-1, -1}; /* for path A and path B */
3464 bool retval = true;
3465
3466 if (priv->tx_paths > 1)
3467 bound = 8;
3468 else
3469 bound = 4;
3470
3471 simubitmap = 0;
3472
3473 for (i = 0; i < bound; i++) {
3474 diff = (result[c1][i] > result[c2][i]) ?
3475 (result[c1][i] - result[c2][i]) :
3476 (result[c2][i] - result[c1][i]);
3477 if (diff > MAX_TOLERANCE) {
3478 if ((i == 2 || i == 6) && !simubitmap) {
3479 if (result[c1][i] + result[c1][i + 1] == 0)
3480 candidate[(i / 4)] = c2;
3481 else if (result[c2][i] + result[c2][i + 1] == 0)
3482 candidate[(i / 4)] = c1;
3483 else
3484 simubitmap = simubitmap | (1 << i);
3485 } else {
3486 simubitmap = simubitmap | (1 << i);
3487 }
3488 }
3489 }
3490
3491 if (simubitmap == 0) {
3492 for (i = 0; i < (bound / 4); i++) {
3493 if (candidate[i] >= 0) {
3494 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
3495 result[3][j] = result[candidate[i]][j];
3496 retval = false;
3497 }
3498 }
3499 return retval;
3500 } else if (!(simubitmap & 0x0f)) {
3501 /* path A OK */
3502 for (i = 0; i < 4; i++)
3503 result[3][i] = result[c1][i];
3504 } else if (!(simubitmap & 0xf0) && priv->tx_paths > 1) {
3505 /* path B OK */
3506 for (i = 4; i < 8; i++)
3507 result[3][i] = result[c1][i];
3508 }
3509
3510 return false;
3511}
3512
e1547c53
JS		 3513static bool rtl8723bu_simularity_compare(struct rtl8xxxu_priv *priv,
3514 int result[][8], int c1, int c2)
3515{
3516 u32 i, j, diff, simubitmap, bound = 0;
3517 int candidate[2] = {-1, -1}; /* for path A and path B */
3518 int tmp1, tmp2;
3519 bool retval = true;
3520
3521 if (priv->tx_paths > 1)
3522 bound = 8;
3523 else
3524 bound = 4;
3525
3526 simubitmap = 0;
3527
3528 for (i = 0; i < bound; i++) {
3529 if (i & 1) {
3530 if ((result[c1][i] & 0x00000200))
3531 tmp1 = result[c1][i] | 0xfffffc00;
3532 else
3533 tmp1 = result[c1][i];
3534
3535 if ((result[c2][i]& 0x00000200))
3536 tmp2 = result[c2][i] | 0xfffffc00;
3537 else
3538 tmp2 = result[c2][i];
3539 } else {
3540 tmp1 = result[c1][i];
3541 tmp2 = result[c2][i];
3542 }
3543
3544 diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1);
3545
3546 if (diff > MAX_TOLERANCE) {
3547 if ((i == 2 || i == 6) && !simubitmap) {
3548 if (result[c1][i] + result[c1][i + 1] == 0)
3549 candidate[(i / 4)] = c2;
3550 else if (result[c2][i] + result[c2][i + 1] == 0)
3551 candidate[(i / 4)] = c1;
3552 else
3553 simubitmap = simubitmap | (1 << i);
3554 } else {
3555 simubitmap = simubitmap | (1 << i);
3556 }
3557 }
3558 }
3559
3560 if (simubitmap == 0) {
3561 for (i = 0; i < (bound / 4); i++) {
3562 if (candidate[i] >= 0) {
3563 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
3564 result[3][j] = result[candidate[i]][j];
3565 retval = false;
3566 }
3567 }
3568 return retval;
3569 } else {
3570 if (!(simubitmap & 0x03)) {
3571 /* path A TX OK */
3572 for (i = 0; i < 2; i++)
3573 result[3][i] = result[c1][i];
3574 }
3575
3576 if (!(simubitmap & 0x0c)) {
3577 /* path A RX OK */
3578 for (i = 2; i < 4; i++)
3579 result[3][i] = result[c1][i];
3580 }
3581
3582 if (!(simubitmap & 0x30) && priv->tx_paths > 1) {
3583 /* path B RX OK */
3584 for (i = 4; i < 6; i++)
3585 result[3][i] = result[c1][i];
3586 }
3587
3588 if (!(simubitmap & 0x30) && priv->tx_paths > 1) {
3589 /* path B RX OK */
3590 for (i = 6; i < 8; i++)
3591 result[3][i] = result[c1][i];
3592 }
3593 }
3594
3595 return false;
3596}
3597
26f1fad2
JS		 3598static void
3599rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, const u32 *reg, u32 *backup)
3600{
3601 int i;
3602
3603 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
3604 backup[i] = rtl8xxxu_read8(priv, reg[i]);
3605
3606 backup[i] = rtl8xxxu_read32(priv, reg[i]);
3607}
3608
3609static void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv,
3610 const u32 *reg, u32 *backup)
3611{
3612 int i;
3613
3614 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
3615 rtl8xxxu_write8(priv, reg[i], backup[i]);
3616
3617 rtl8xxxu_write32(priv, reg[i], backup[i]);
3618}
3619
3620static void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
3621 u32 *backup, int count)
3622{
3623 int i;
3624
3625 for (i = 0; i < count; i++)
3626 backup[i] = rtl8xxxu_read32(priv, regs[i]);
3627}
3628
3629static void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
3630 u32 *backup, int count)
3631{
3632 int i;
3633
3634 for (i = 0; i < count; i++)
3635 rtl8xxxu_write32(priv, regs[i], backup[i]);
3636}
3637
3638
3639static void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs,
3640 bool path_a_on)
3641{
3642 u32 path_on;
3643 int i;
3644
26f1fad2 3645 if (priv->tx_paths == 1) {
8634af5e
JS		 3646 path_on = priv->fops->adda_1t_path_on;
3647 rtl8xxxu_write32(priv, regs[0], priv->fops->adda_1t_init);
26f1fad2 3648 } else {
8634af5e
JS		 3649 path_on = path_a_on ? priv->fops->adda_2t_path_on_a :
3650 priv->fops->adda_2t_path_on_b;
3651
26f1fad2
JS		 3652 rtl8xxxu_write32(priv, regs[0], path_on);
3653 }
3654
3655 for (i = 1 ; i < RTL8XXXU_ADDA_REGS ; i++)
3656 rtl8xxxu_write32(priv, regs[i], path_on);
3657}
3658
3659static void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv,
3660 const u32 *regs, u32 *backup)
3661{
3662 int i = 0;
3663
3664 rtl8xxxu_write8(priv, regs[i], 0x3f);
3665
3666 for (i = 1 ; i < (RTL8XXXU_MAC_REGS - 1); i++)
3667 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(3)));
3668
3669 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(5)));
3670}
3671
3672static int rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv *priv)
3673{
3674 u32 reg_eac, reg_e94, reg_e9c, reg_ea4, val32;
3675 int result = 0;
3676
3677 /* path-A IQK setting */
3678 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1f);
3679 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1f);
3680 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140102);
3681
3682 val32 = (priv->rf_paths > 1) ? 0x28160202 :
3683 /*IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202: */
3684 0x28160502;
3685 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val32);
3686
3687 /* path-B IQK setting */
3688 if (priv->rf_paths > 1) {
3689 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x10008c22);
3690 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x10008c22);
3691 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140102);
3692 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160202);
3693 }
3694
3695 /* LO calibration setting */
3696 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x001028d1);
3697
3698 /* One shot, path A LOK & IQK */
3699 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
3700 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
3701
3702 mdelay(1);
3703
3704 /* Check failed */
3705 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3706 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
3707 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
3708 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
3709
3710 if (!(reg_eac & BIT(28)) &&
3711 ((reg_e94 & 0x03ff0000) != 0x01420000) &&
3712 ((reg_e9c & 0x03ff0000) != 0x00420000))
3713 result |= 0x01;
3714 else /* If TX not OK, ignore RX */
3715 goto out;
3716
3717 /* If TX is OK, check whether RX is OK */
3718 if (!(reg_eac & BIT(27)) &&
3719 ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
3720 ((reg_eac & 0x03ff0000) != 0x00360000))
3721 result |= 0x02;
3722 else
3723 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n",
3724 __func__);
3725out:
3726 return result;
3727}
3728
3729static int rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv *priv)
3730{
3731 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
3732 int result = 0;
3733
3734 /* One shot, path B LOK & IQK */
3735 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002);
3736 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000);
3737
3738 mdelay(1);
3739
3740 /* Check failed */
3741 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3742 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3743 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3744 reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
3745 reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
3746
3747 if (!(reg_eac & BIT(31)) &&
3748 ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
3749 ((reg_ebc & 0x03ff0000) != 0x00420000))
3750 result |= 0x01;
3751 else
3752 goto out;
3753
3754 if (!(reg_eac & BIT(30)) &&
3755 (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) &&
3756 (((reg_ecc & 0x03ff0000) >> 16) != 0x36))
3757 result |= 0x02;
3758 else
3759 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
3760 __func__);
3761out:
3762 return result;
3763}
3764
e1547c53
JS		 3765static int rtl8723bu_iqk_path_a(struct rtl8xxxu_priv *priv)
3766{
3767 u32 reg_eac, reg_e94, reg_e9c, path_sel, val32;
3768 int result = 0;
3769
3770 path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
3771
3772 /*
3773 * Leave IQK mode
3774 */
3775 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
3776 val32 &= 0x000000ff;
3777 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
3778
3779 /*
3780 * Enable path A PA in TX IQK mode
3781 */
3782 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
3783 val32 |= 0x80000;
3784 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
3785 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x20000);
3786 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0003f);
3787 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xc7f87);
3788
3789 /*
3790 * Tx IQK setting
3791 */
3792 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
3793 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
3794
3795 /* path-A IQK setting */
3796 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);
3797 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
3798 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
3799 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
3800
3801 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821403ea);
3802 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000);
3803 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000);
3804 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000);
3805
3806 /* LO calibration setting */
3807 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911);
3808
3809 /*
3810 * Enter IQK mode
3811 */
3812 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
3813 val32 &= 0x000000ff;
3814 val32 |= 0x80800000;
3815 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
3816
3817 /*
3818 * The vendor driver indicates the USB module is always using
3819 * S0S1 path 1 for the 8723bu. This may be different for 8192eu
3820 */
3821 if (priv->rf_paths > 1)
3822 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000);
3823 else
3824 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280);
3825
3826 /*
3827 * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu.
3828 * No trace of this in the 8192eu or 8188eu vendor drivers.
3829 */
3830 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800);
3831
3832 /* One shot, path A LOK & IQK */
3833 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
3834 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
3835
3836 mdelay(1);
3837
3838 /* Restore Ant Path */
3839 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel);
3840#ifdef RTL8723BU_BT
3841 /* GNT_BT = 1 */
3842 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800);
3843#endif
3844
3845 /*
3846 * Leave IQK mode
3847 */
3848 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
3849 val32 &= 0x000000ff;
3850 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
3851
3852 /* Check failed */
3853 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3854 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
3855 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
3856
3857 val32 = (reg_e9c >> 16) & 0x3ff;
3858 if (val32 & 0x200)
3859 val32 = 0x400 - val32;
3860
3861 if (!(reg_eac & BIT(28)) &&
3862 ((reg_e94 & 0x03ff0000) != 0x01420000) &&
3863 ((reg_e9c & 0x03ff0000) != 0x00420000) &&
3864 ((reg_e94 & 0x03ff0000) < 0x01100000) &&
3865 ((reg_e94 & 0x03ff0000) > 0x00f00000) &&
3866 val32 < 0xf)
3867 result |= 0x01;
3868 else /* If TX not OK, ignore RX */
3869 goto out;
3870
3871out:
3872 return result;
3873}
3874
3875static int rtl8723bu_rx_iqk_path_a(struct rtl8xxxu_priv *priv)
3876{
3877 u32 reg_ea4, reg_eac, reg_e94, reg_e9c, path_sel, val32;
3878 int result = 0;
3879
3880 path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
3881
3882 /*
3883 * Leave IQK mode
3884 */
3885 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
3886 val32 &= 0x000000ff;
3887 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
3888
3889 /*
3890 * Enable path A PA in TX IQK mode
3891 */
3892 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
3893 val32 |= 0x80000;
3894 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
3895 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
3896 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
3897 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7fb7);
3898
3899 /*
3900 * Tx IQK setting
3901 */
3902 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
3903 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
3904
3905 /* path-A IQK setting */
3906 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);
3907 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
3908 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
3909 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
3910
3911 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160ff0);
3912 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000);
3913 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000);
3914 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000);
3915
3916 /* LO calibration setting */
3917 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911);
3918
3919 /*
3920 * Enter IQK mode
3921 */
3922 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
3923 val32 &= 0x000000ff;
3924 val32 |= 0x80800000;
3925 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
3926
3927 /*
3928 * The vendor driver indicates the USB module is always using
3929 * S0S1 path 1 for the 8723bu. This may be different for 8192eu
3930 */
3931 if (priv->rf_paths > 1)
3932 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000);
3933 else
3934 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280);
3935
3936 /*
3937 * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu.
3938 * No trace of this in the 8192eu or 8188eu vendor drivers.
3939 */
3940 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800);
3941
3942 /* One shot, path A LOK & IQK */
3943 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
3944 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
3945
3946 mdelay(1);
3947
3948 /* Restore Ant Path */
3949 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel);
3950#ifdef RTL8723BU_BT
3951 /* GNT_BT = 1 */
3952 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800);
3953#endif
3954
3955 /*
3956 * Leave IQK mode
3957 */
3958 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
3959 val32 &= 0x000000ff;
3960 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
3961
3962 /* Check failed */
3963 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3964 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
3965 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
3966
3967 val32 = (reg_e9c >> 16) & 0x3ff;
3968 if (val32 & 0x200)
3969 val32 = 0x400 - val32;
3970
3971 if (!(reg_eac & BIT(28)) &&
3972 ((reg_e94 & 0x03ff0000) != 0x01420000) &&
3973 ((reg_e9c & 0x03ff0000) != 0x00420000) &&
3974 ((reg_e94 & 0x03ff0000) < 0x01100000) &&
3975 ((reg_e94 & 0x03ff0000) > 0x00f00000) &&
3976 val32 < 0xf)
3977 result |= 0x01;
3978 else /* If TX not OK, ignore RX */
3979 goto out;
3980
3981 val32 = 0x80007c00 | (reg_e94 &0x3ff0000) |
3982 ((reg_e9c & 0x3ff0000) >> 16);
3983 rtl8xxxu_write32(priv, REG_TX_IQK, val32);
3984
3985 /*
3986 * Modify RX IQK mode
3987 */
3988 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
3989 val32 &= 0x000000ff;
3990 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
3991 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
3992 val32 |= 0x80000;
3993 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
3994 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
3995 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
3996 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7d77);
3997
3998 /*
3999 * PA, PAD setting
4000 */
4001 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0xf80);
4002 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_55, 0x4021f);
4003
4004 /*
4005 * RX IQK setting
4006 */
4007 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
4008
4009 /* path-A IQK setting */
4010 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);
4011 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x18008c1c);
4012 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
4013 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
4014
4015 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82110000);
4016 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x2816001f);
4017 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000);
4018 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000);
4019
4020 /* LO calibration setting */
4021 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a8d1);
4022
4023 /*
4024 * Enter IQK mode
4025 */
4026 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4027 val32 &= 0x000000ff;
4028 val32 |= 0x80800000;
4029 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4030
4031 if (priv->rf_paths > 1)
4032 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000);
4033 else
4034 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280);
4035
4036 /*
4037 * Disable BT
4038 */
4039 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800);
4040
4041 /* One shot, path A LOK & IQK */
4042 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
4043 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
4044
4045 mdelay(1);
4046
4047 /* Restore Ant Path */
4048 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel);
4049#ifdef RTL8723BU_BT
4050 /* GNT_BT = 1 */
4051 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800);
4052#endif
4053
4054 /*
4055 * Leave IQK mode
4056 */
4057 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4058 val32 &= 0x000000ff;
4059 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4060
4061 /* Check failed */
4062 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4063 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
4064
4065 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x780);
4066
4067 val32 = (reg_eac >> 16) & 0x3ff;
4068 if (val32 & 0x200)
4069 val32 = 0x400 - val32;
4070
4071 if (!(reg_eac & BIT(27)) &&
4072 ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
4073 ((reg_eac & 0x03ff0000) != 0x00360000) &&
4074 ((reg_ea4 & 0x03ff0000) < 0x01100000) &&
4075 ((reg_ea4 & 0x03ff0000) > 0x00f00000) &&
4076 val32 < 0xf)
4077 result |= 0x02;
4078 else /* If TX not OK, ignore RX */
4079 goto out;
4080out:
4081 return result;
4082}
4083
4084#ifdef RTL8723BU_PATH_B
4085static int rtl8723bu_iqk_path_b(struct rtl8xxxu_priv *priv)
4086{
4087 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc, path_sel;
4088 int result = 0;
4089
4090 path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
4091
4092 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4093 val32 &= 0x000000ff;
4094 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4095
4096 /* One shot, path B LOK & IQK */
4097 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002);
4098 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000);
4099
4100 mdelay(1);
4101
4102 /* Check failed */
4103 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4104 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
4105 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
4106 reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
4107 reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
4108
4109 if (!(reg_eac & BIT(31)) &&
4110 ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
4111 ((reg_ebc & 0x03ff0000) != 0x00420000))
4112 result |= 0x01;
4113 else
4114 goto out;
4115
4116 if (!(reg_eac & BIT(30)) &&
4117 (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) &&
4118 (((reg_ecc & 0x03ff0000) >> 16) != 0x36))
4119 result |= 0x02;
4120 else
4121 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
4122 __func__);
4123out:
4124 return result;
4125}
4126#endif
4127
26f1fad2
JS		 4128static void rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
4129 int result[][8], int t)
4130{
4131 struct device *dev = &priv->udev->dev;
4132 u32 i, val32;
4133 int path_a_ok, path_b_ok;
4134 int retry = 2;
4135 const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
4136 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
4137 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
4138 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
4139 REG_TX_OFDM_BBON, REG_TX_TO_RX,
4140 REG_TX_TO_TX, REG_RX_CCK,
4141 REG_RX_OFDM, REG_RX_WAIT_RIFS,
4142 REG_RX_TO_RX, REG_STANDBY,
4143 REG_SLEEP, REG_PMPD_ANAEN
4144 };
4145 const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
4146 REG_TXPAUSE, REG_BEACON_CTRL,
4147 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
4148 };
4149 const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
4150 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
4151 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
4152 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
4153 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
4154 };
4155
4156 /*
4157 * Note: IQ calibration must be performed after loading
4158 * PHY_REG.txt , and radio_a, radio_b.txt
4159 */
4160
4161 if (t == 0) {
4162 /* Save ADDA parameters, turn Path A ADDA on */
4163 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
4164 RTL8XXXU_ADDA_REGS);
4165 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
4166 rtl8xxxu_save_regs(priv, iqk_bb_regs,
4167 priv->bb_backup, RTL8XXXU_BB_REGS);
4168 }
4169
4170 rtl8xxxu_path_adda_on(priv, adda_regs, true);
4171
4172 if (t == 0) {
4173 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1);
4174 if (val32 & FPGA0_HSSI_PARM1_PI)
4175 priv->pi_enabled = 1;
4176 }
4177
4178 if (!priv->pi_enabled) {
4179 /* Switch BB to PI mode to do IQ Calibration. */
4180 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100);
4181 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100);
4182 }
4183
4184 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4185 val32 &= ~FPGA_RF_MODE_CCK;
4186 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
4187
4188 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
4189 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
4190 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
4191
4192 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL);
4193 val32 |= (FPGA0_RF_PAPE | (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
4194 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
4195
4196 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE);
4197 val32 &= ~BIT(10);
4198 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32);
4199 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE);
4200 val32 &= ~BIT(10);
4201 rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32);
4202
4203 if (priv->tx_paths > 1) {
4204 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
4205 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 0x00010000);
4206 }
4207
4208 /* MAC settings */
4209 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
4210
4211 /* Page B init */
4212 rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x00080000);
4213
4214 if (priv->tx_paths > 1)
4215 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x00080000);
4216
4217 /* IQ calibration setting */
4218 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
4219 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
4220 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
4221
4222 for (i = 0; i < retry; i++) {
4223 path_a_ok = rtl8xxxu_iqk_path_a(priv);
4224 if (path_a_ok == 0x03) {
4225 val32 = rtl8xxxu_read32(priv,
4226 REG_TX_POWER_BEFORE_IQK_A);
4227 result[t][0] = (val32 >> 16) & 0x3ff;
4228 val32 = rtl8xxxu_read32(priv,
4229 REG_TX_POWER_AFTER_IQK_A);
4230 result[t][1] = (val32 >> 16) & 0x3ff;
4231 val32 = rtl8xxxu_read32(priv,
4232 REG_RX_POWER_BEFORE_IQK_A_2);
4233 result[t][2] = (val32 >> 16) & 0x3ff;
4234 val32 = rtl8xxxu_read32(priv,
4235 REG_RX_POWER_AFTER_IQK_A_2);
4236 result[t][3] = (val32 >> 16) & 0x3ff;
4237 break;
4238 } else if (i == (retry - 1) && path_a_ok == 0x01) {
4239 /* TX IQK OK */
4240 dev_dbg(dev, "%s: Path A IQK Only Tx Success!!\n",
4241 __func__);
4242
4243 val32 = rtl8xxxu_read32(priv,
4244 REG_TX_POWER_BEFORE_IQK_A);
4245 result[t][0] = (val32 >> 16) & 0x3ff;
4246 val32 = rtl8xxxu_read32(priv,
4247 REG_TX_POWER_AFTER_IQK_A);
4248 result[t][1] = (val32 >> 16) & 0x3ff;
4249 }
4250 }
4251
4252 if (!path_a_ok)
4253 dev_dbg(dev, "%s: Path A IQK failed!\n", __func__);
4254
4255 if (priv->tx_paths > 1) {
4256 /*
4257 * Path A into standby
4258 */
4259 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x0);
4260 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
4261 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
4262
4263 /* Turn Path B ADDA on */
4264 rtl8xxxu_path_adda_on(priv, adda_regs, false);
4265
4266 for (i = 0; i < retry; i++) {
4267 path_b_ok = rtl8xxxu_iqk_path_b(priv);
4268 if (path_b_ok == 0x03) {
4269 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
4270 result[t][4] = (val32 >> 16) & 0x3ff;
4271 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
4272 result[t][5] = (val32 >> 16) & 0x3ff;
4273 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
4274 result[t][6] = (val32 >> 16) & 0x3ff;
4275 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
4276 result[t][7] = (val32 >> 16) & 0x3ff;
4277 break;
4278 } else if (i == (retry - 1) && path_b_ok == 0x01) {
4279 /* TX IQK OK */
4280 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
4281 result[t][4] = (val32 >> 16) & 0x3ff;
4282 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
4283 result[t][5] = (val32 >> 16) & 0x3ff;
4284 }
4285 }
4286
4287 if (!path_b_ok)
4288 dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
4289 }
4290
4291 /* Back to BB mode, load original value */
4292 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0);
4293
4294 if (t) {
4295 if (!priv->pi_enabled) {
4296 /*
4297 * Switch back BB to SI mode after finishing
4298 * IQ Calibration
4299 */
4300 val32 = 0x01000000;
4301 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32);
4302 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32);
4303 }
4304
4305 /* Reload ADDA power saving parameters */
4306 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
4307 RTL8XXXU_ADDA_REGS);
4308
4309 /* Reload MAC parameters */
4310 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
4311
4312 /* Reload BB parameters */
4313 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
4314 priv->bb_backup, RTL8XXXU_BB_REGS);
4315
4316 /* Restore RX initial gain */
4317 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3);
4318
4319 if (priv->tx_paths > 1) {
4320 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM,
4321 0x00032ed3);
4322 }
4323
4324 /* Load 0xe30 IQC default value */
4325 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
4326 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
4327 }
4328}
4329
e1547c53
JS		 4330static void rtl8723bu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
4331 int result[][8], int t)
4332{
4333 struct device *dev = &priv->udev->dev;
4334 u32 i, val32;
4335 int path_a_ok /*, path_b_ok */;
4336 int retry = 2;
4337 const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
4338 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
4339 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
4340 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
4341 REG_TX_OFDM_BBON, REG_TX_TO_RX,
4342 REG_TX_TO_TX, REG_RX_CCK,
4343 REG_RX_OFDM, REG_RX_WAIT_RIFS,
4344 REG_RX_TO_RX, REG_STANDBY,
4345 REG_SLEEP, REG_PMPD_ANAEN
4346 };
4347 const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
4348 REG_TXPAUSE, REG_BEACON_CTRL,
4349 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
4350 };
4351 const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
4352 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
4353 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
4354 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
4355 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
4356 };
4357 u8 xa_agc = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1) & 0xff;
4358 u8 xb_agc = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1) & 0xff;
4359
4360 /*
4361 * Note: IQ calibration must be performed after loading
4362 * PHY_REG.txt , and radio_a, radio_b.txt
4363 */
4364
4365 if (t == 0) {
4366 /* Save ADDA parameters, turn Path A ADDA on */
4367 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
4368 RTL8XXXU_ADDA_REGS);
4369 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
4370 rtl8xxxu_save_regs(priv, iqk_bb_regs,
4371 priv->bb_backup, RTL8XXXU_BB_REGS);
4372 }
4373
4374 rtl8xxxu_path_adda_on(priv, adda_regs, true);
4375
4376 /* MAC settings */
4377 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
4378
4379 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
4380 val32 |= 0x0f000000;
4381 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
4382
4383 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
4384 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
4385 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
4386
4387#ifdef RTL8723BU_PATH_B
4388 /* Set RF mode to standby Path B */
4389 if (priv->tx_paths > 1)
4390 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x10000);
4391#endif
4392
4393#if 0
4394 /* Page B init */
4395 rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x0f600000);
4396
4397 if (priv->tx_paths > 1)
4398 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x0f600000);
4399#endif
4400
4401 /*
4402 * RX IQ calibration setting for 8723B D cut large current issue
4403 * when leaving IPS
4404 */
4405 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4406 val32 &= 0x000000ff;
4407 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4408
4409 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
4410 val32 |= 0x80000;
4411 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
4412
4413 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
4414 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
4415 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7fb7);
4416
4417 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED);
4418 val32 |= 0x20;
4419 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32);
4420
4421 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_43, 0x60fbd);
4422
4423 for (i = 0; i < retry; i++) {
4424 path_a_ok = rtl8723bu_iqk_path_a(priv);
4425 if (path_a_ok == 0x01) {
4426 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4427 val32 &= 0x000000ff;
4428 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4429
4430#if 0 /* Only needed in restore case, we may need this when going to suspend */
4431 priv->RFCalibrateInfo.TxLOK[RF_A] =
4432 rtl8xxxu_read_rfreg(priv, RF_A,
4433 RF6052_REG_TXM_IDAC);
4434#endif
4435
4436 val32 = rtl8xxxu_read32(priv,
4437 REG_TX_POWER_BEFORE_IQK_A);
4438 result[t][0] = (val32 >> 16) & 0x3ff;
4439 val32 = rtl8xxxu_read32(priv,
4440 REG_TX_POWER_AFTER_IQK_A);
4441 result[t][1] = (val32 >> 16) & 0x3ff;
4442
4443 break;
4444 }
4445 }
4446
4447 if (!path_a_ok)
4448 dev_dbg(dev, "%s: Path A TX IQK failed!\n", __func__);
4449
4450 for (i = 0; i < retry; i++) {
4451 path_a_ok = rtl8723bu_rx_iqk_path_a(priv);
4452 if (path_a_ok == 0x03) {
4453 val32 = rtl8xxxu_read32(priv,
4454 REG_RX_POWER_BEFORE_IQK_A_2);
4455 result[t][2] = (val32 >> 16) & 0x3ff;
4456 val32 = rtl8xxxu_read32(priv,
4457 REG_RX_POWER_AFTER_IQK_A_2);
4458 result[t][3] = (val32 >> 16) & 0x3ff;
4459
4460 break;
4461 }
4462 }
4463
4464 if (!path_a_ok)
4465 dev_dbg(dev, "%s: Path A RX IQK failed!\n", __func__);
4466
4467 if (priv->tx_paths > 1) {
4468#if 1
4469 dev_warn(dev, "%s: Path B not supported\n", __func__);
4470#else
4471
4472 /*
4473 * Path A into standby
4474 */
4475 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4476 val32 &= 0x000000ff;
4477 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4478 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x10000);
4479
4480 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4481 val32 &= 0x000000ff;
4482 val32 |= 0x80800000;
4483 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4484
4485 /* Turn Path B ADDA on */
4486 rtl8xxxu_path_adda_on(priv, adda_regs, false);
4487
4488 for (i = 0; i < retry; i++) {
4489 path_b_ok = rtl8xxxu_iqk_path_b(priv);
4490 if (path_b_ok == 0x03) {
4491 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
4492 result[t][4] = (val32 >> 16) & 0x3ff;
4493 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
4494 result[t][5] = (val32 >> 16) & 0x3ff;
4495 break;
4496 }
4497 }
4498
4499 if (!path_b_ok)
4500 dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
4501
4502 for (i = 0; i < retry; i++) {
4503 path_b_ok = rtl8723bu_rx_iqk_path_b(priv);
4504 if (path_a_ok == 0x03) {
4505 val32 = rtl8xxxu_read32(priv,
4506 REG_RX_POWER_BEFORE_IQK_B_2);
4507 result[t][6] = (val32 >> 16) & 0x3ff;
4508 val32 = rtl8xxxu_read32(priv,
4509 REG_RX_POWER_AFTER_IQK_B_2);
4510 result[t][7] = (val32 >> 16) & 0x3ff;
4511 break;
4512 }
4513 }
4514
4515 if (!path_b_ok)
4516 dev_dbg(dev, "%s: Path B RX IQK failed!\n", __func__);
4517#endif
4518 }
4519
4520 /* Back to BB mode, load original value */
4521 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4522 val32 &= 0x000000ff;
4523 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4524
4525 if (t) {
4526 /* Reload ADDA power saving parameters */
4527 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
4528 RTL8XXXU_ADDA_REGS);
4529
4530 /* Reload MAC parameters */
4531 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
4532
4533 /* Reload BB parameters */
4534 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
4535 priv->bb_backup, RTL8XXXU_BB_REGS);
4536
4537 /* Restore RX initial gain */
4538 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);
4539 val32 &= 0xffffff00;
4540 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | 0x50);
4541 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | xa_agc);
4542
4543 if (priv->tx_paths > 1) {
4544 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1);
4545 val32 &= 0xffffff00;
4546 rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1,
4547 val32 | 0x50);
4548 rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1,
4549 val32 | xb_agc);
4550 }
4551
4552 /* Load 0xe30 IQC default value */
4553 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
4554 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
4555 }
4556}
4557
c7a5a190
JS		 4558static void rtl8xxxu_prepare_calibrate(struct rtl8xxxu_priv *priv, u8 start)
4559{
4560 struct h2c_cmd h2c;
4561
4562 if (priv->fops->mbox_ext_width < 4)
4563 return;
4564
4565 memset(&h2c, 0, sizeof(struct h2c_cmd));
4566 h2c.bt_wlan_calibration.cmd = H2C_8723B_BT_WLAN_CALIBRATION;
4567 h2c.bt_wlan_calibration.data = start;
4568
4569 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_wlan_calibration));
4570}
4571
e1547c53 4572static void rtl8723au_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
26f1fad2
JS		 4573{
4574 struct device *dev = &priv->udev->dev;
4575 int result[4][8]; /* last is final result */
4576 int i, candidate;
4577 bool path_a_ok, path_b_ok;
4578 u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
4579 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
4580 s32 reg_tmp = 0;
4581 bool simu;
4582
c7a5a190
JS		 4583 rtl8xxxu_prepare_calibrate(priv, 1);
4584
26f1fad2
JS		 4585 memset(result, 0, sizeof(result));
4586 candidate = -1;
4587
4588 path_a_ok = false;
4589 path_b_ok = false;
4590
4591 rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4592
4593 for (i = 0; i < 3; i++) {
4594 rtl8xxxu_phy_iqcalibrate(priv, result, i);
4595
4596 if (i == 1) {
4597 simu = rtl8xxxu_simularity_compare(priv, result, 0, 1);
4598 if (simu) {
4599 candidate = 0;
4600 break;
4601 }
4602 }
4603
4604 if (i == 2) {
4605 simu = rtl8xxxu_simularity_compare(priv, result, 0, 2);
4606 if (simu) {
4607 candidate = 0;
4608 break;
4609 }
4610
4611 simu = rtl8xxxu_simularity_compare(priv, result, 1, 2);
4612 if (simu) {
4613 candidate = 1;
4614 } else {
4615 for (i = 0; i < 8; i++)
4616 reg_tmp += result[3][i];
4617
4618 if (reg_tmp)
4619 candidate = 3;
4620 else
4621 candidate = -1;
4622 }
4623 }
4624 }
4625
4626 for (i = 0; i < 4; i++) {
4627 reg_e94 = result[i][0];
4628 reg_e9c = result[i][1];
4629 reg_ea4 = result[i][2];
4630 reg_eac = result[i][3];
4631 reg_eb4 = result[i][4];
4632 reg_ebc = result[i][5];
4633 reg_ec4 = result[i][6];
4634 reg_ecc = result[i][7];
4635 }
4636
4637 if (candidate >= 0) {
4638 reg_e94 = result[candidate][0];
4639 priv->rege94 = reg_e94;
4640 reg_e9c = result[candidate][1];
4641 priv->rege9c = reg_e9c;
4642 reg_ea4 = result[candidate][2];
4643 reg_eac = result[candidate][3];
4644 reg_eb4 = result[candidate][4];
4645 priv->regeb4 = reg_eb4;
4646 reg_ebc = result[candidate][5];
4647 priv->regebc = reg_ebc;
4648 reg_ec4 = result[candidate][6];
4649 reg_ecc = result[candidate][7];
4650 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
4651 dev_dbg(dev,
4652 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
4653 "ecc=%x\n ", __func__, reg_e94, reg_e9c,
4654 reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
4655 path_a_ok = true;
4656 path_b_ok = true;
4657 } else {
4658 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
4659 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
4660 }
4661
4662 if (reg_e94 && candidate >= 0)
4663 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
4664 candidate, (reg_ea4 == 0));
4665
4666 if (priv->tx_paths > 1 && reg_eb4)
4667 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
4668 candidate, (reg_ec4 == 0));
4669
4670 rtl8xxxu_save_regs(priv, rtl8723au_iqk_phy_iq_bb_reg,
4671 priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
c7a5a190
JS		 4672
4673 rtl8xxxu_prepare_calibrate(priv, 0);
26f1fad2
JS		 4674}
4675
e1547c53
JS		 4676static void rtl8723bu_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
4677{
4678 struct device *dev = &priv->udev->dev;
4679 int result[4][8]; /* last is final result */
4680 int i, candidate;
4681 bool path_a_ok, path_b_ok;
4682 u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
4683 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
4684 u32 val32, bt_control;
4685 s32 reg_tmp = 0;
4686 bool simu;
4687
4688 rtl8xxxu_prepare_calibrate(priv, 1);
4689
4690 memset(result, 0, sizeof(result));
4691 candidate = -1;
4692
4693 path_a_ok = false;
4694 path_b_ok = false;
4695
4696 bt_control = rtl8xxxu_read32(priv, REG_BT_CONTROL_8723BU);
4697
4698 for (i = 0; i < 3; i++) {
4699 rtl8723bu_phy_iqcalibrate(priv, result, i);
4700
4701 if (i == 1) {
4702 simu = rtl8723bu_simularity_compare(priv, result, 0, 1);
4703 if (simu) {
4704 candidate = 0;
4705 break;
4706 }
4707 }
4708
4709 if (i == 2) {
4710 simu = rtl8723bu_simularity_compare(priv, result, 0, 2);
4711 if (simu) {
4712 candidate = 0;
4713 break;
4714 }
4715
4716 simu = rtl8723bu_simularity_compare(priv, result, 1, 2);
4717 if (simu) {
4718 candidate = 1;
4719 } else {
4720 for (i = 0; i < 8; i++)
4721 reg_tmp += result[3][i];
4722
4723 if (reg_tmp)
4724 candidate = 3;
4725 else
4726 candidate = -1;
4727 }
4728 }
4729 }
4730
4731 for (i = 0; i < 4; i++) {
4732 reg_e94 = result[i][0];
4733 reg_e9c = result[i][1];
4734 reg_ea4 = result[i][2];
4735 reg_eac = result[i][3];
4736 reg_eb4 = result[i][4];
4737 reg_ebc = result[i][5];
4738 reg_ec4 = result[i][6];
4739 reg_ecc = result[i][7];
4740 }
4741
4742 if (candidate >= 0) {
4743 reg_e94 = result[candidate][0];
4744 priv->rege94 = reg_e94;
4745 reg_e9c = result[candidate][1];
4746 priv->rege9c = reg_e9c;
4747 reg_ea4 = result[candidate][2];
4748 reg_eac = result[candidate][3];
4749 reg_eb4 = result[candidate][4];
4750 priv->regeb4 = reg_eb4;
4751 reg_ebc = result[candidate][5];
4752 priv->regebc = reg_ebc;
4753 reg_ec4 = result[candidate][6];
4754 reg_ecc = result[candidate][7];
4755 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
4756 dev_dbg(dev,
4757 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
4758 "ecc=%x\n ", __func__, reg_e94, reg_e9c,
4759 reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
4760 path_a_ok = true;
4761 path_b_ok = true;
4762 } else {
4763 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
4764 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
4765 }
4766
4767 if (reg_e94 && candidate >= 0)
4768 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
4769 candidate, (reg_ea4 == 0));
4770
4771 if (priv->tx_paths > 1 && reg_eb4)
4772 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
4773 candidate, (reg_ec4 == 0));
4774
4775 rtl8xxxu_save_regs(priv, rtl8723au_iqk_phy_iq_bb_reg,
4776 priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
4777
4778 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, bt_control);
4779
4780 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
4781 val32 |= 0x80000;
4782 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
4783 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x18000);
4784 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
4785 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xe6177);
4786 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED);
4787 val32 |= 0x20;
4788 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32);
4789 rtl8xxxu_write_rfreg(priv, RF_A, 0x43, 0x300bd);
4790
4791 if (priv->rf_paths > 1) {
4792 dev_dbg(dev, "%s: beware 2T not yet supported\n", __func__);
4793#ifdef RTL8723BU_PATH_B
4794 if (RF_Path == 0x0) //S1
4795 ODM_SetIQCbyRFpath(pDM_Odm, 0);
4796 else //S0
4797 ODM_SetIQCbyRFpath(pDM_Odm, 1);
4798#endif
4799 }
4800 rtl8xxxu_prepare_calibrate(priv, 0);
4801}
4802
26f1fad2
JS		 4803static void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv)
4804{
4805 u32 val32;
4806 u32 rf_amode, rf_bmode = 0, lstf;
4807
4808 /* Check continuous TX and Packet TX */
4809 lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
4810
4811 if (lstf & OFDM_LSTF_MASK) {
4812 /* Disable all continuous TX */
4813 val32 = lstf & ~OFDM_LSTF_MASK;
4814 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
4815
4816 /* Read original RF mode Path A */
4817 rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_AC);
4818
4819 /* Set RF mode to standby Path A */
4820 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC,
4821 (rf_amode & 0x8ffff) | 0x10000);
4822
4823 /* Path-B */
4824 if (priv->tx_paths > 1) {
4825 rf_bmode = rtl8xxxu_read_rfreg(priv, RF_B,
4826 RF6052_REG_AC);
4827
4828 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
4829 (rf_bmode & 0x8ffff) | 0x10000);
4830 }
4831 } else {
4832 /* Deal with Packet TX case */
4833 /* block all queues */
4834 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
4835 }
4836
4837 /* Start LC calibration */
0d698dec
JS		 4838 if (priv->fops->has_s0s1)
4839 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdfbe0);
26f1fad2
JS		 4840 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG);
4841 val32 |= 0x08000;
4842 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32);
4843
4844 msleep(100);
4845
0d698dec
JS		 4846 if (priv->fops->has_s0s1)
4847 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdffe0);
4848
26f1fad2
JS		 4849 /* Restore original parameters */
4850 if (lstf & OFDM_LSTF_MASK) {
4851 /* Path-A */
4852 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf);
4853 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, rf_amode);
4854
4855 /* Path-B */
4856 if (priv->tx_paths > 1)
4857 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
4858 rf_bmode);
4859 } else /* Deal with Packet TX case */
4860 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
4861}
4862
4863static int rtl8xxxu_set_mac(struct rtl8xxxu_priv *priv)
4864{
4865 int i;
4866 u16 reg;
4867
4868 reg = REG_MACID;
4869
4870 for (i = 0; i < ETH_ALEN; i++)
4871 rtl8xxxu_write8(priv, reg + i, priv->mac_addr[i]);
4872
4873 return 0;
4874}
4875
4876static int rtl8xxxu_set_bssid(struct rtl8xxxu_priv *priv, const u8 *bssid)
4877{
4878 int i;
4879 u16 reg;
4880
4881 dev_dbg(&priv->udev->dev, "%s: (%pM)\n", __func__, bssid);
4882
4883 reg = REG_BSSID;
4884
4885 for (i = 0; i < ETH_ALEN; i++)
4886 rtl8xxxu_write8(priv, reg + i, bssid[i]);
4887
4888 return 0;
4889}
4890
4891static void
4892rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv *priv, u8 ampdu_factor)
4893{
4894 u8 vals[4] = { 0x41, 0xa8, 0x72, 0xb9 };
4895 u8 max_agg = 0xf;
4896 int i;
4897
4898 ampdu_factor = 1 << (ampdu_factor + 2);
4899 if (ampdu_factor > max_agg)
4900 ampdu_factor = max_agg;
4901
4902 for (i = 0; i < 4; i++) {
4903 if ((vals[i] & 0xf0) > (ampdu_factor << 4))
4904 vals[i] = (vals[i] & 0x0f) | (ampdu_factor << 4);
4905
4906 if ((vals[i] & 0x0f) > ampdu_factor)
4907 vals[i] = (vals[i] & 0xf0) | ampdu_factor;
4908
4909 rtl8xxxu_write8(priv, REG_AGGLEN_LMT + i, vals[i]);
4910 }
4911}
4912
4913static void rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv *priv, u8 density)
4914{
4915 u8 val8;
4916
4917 val8 = rtl8xxxu_read8(priv, REG_AMPDU_MIN_SPACE);
4918 val8 &= 0xf8;
4919 val8 |= density;
4920 rtl8xxxu_write8(priv, REG_AMPDU_MIN_SPACE, val8);
4921}
4922
4923static int rtl8xxxu_active_to_emu(struct rtl8xxxu_priv *priv)
4924{
4925 u8 val8;
4926 int count, ret;
4927
4928 /* Start of rtl8723AU_card_enable_flow */
4929 /* Act to Cardemu sequence*/
4930 /* Turn off RF */
4931 rtl8xxxu_write8(priv, REG_RF_CTRL, 0);
4932
4933 /* 0x004E[7] = 0, switch DPDT_SEL_P output from register 0x0065[2] */
4934 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
4935 val8 &= ~LEDCFG2_DPDT_SELECT;
4936 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
4937
4938 /* 0x0005[1] = 1 turn off MAC by HW state machine*/
4939 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4940 val8 |= BIT(1);
4941 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4942
4943 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
4944 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4945 if ((val8 & BIT(1)) == 0)
4946 break;
4947 udelay(10);
4948 }
4949
4950 if (!count) {
4951 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",
4952 __func__);
4953 ret = -EBUSY;
4954 goto exit;
4955 }
4956
4957 /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */
4958 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
4959 val8 |= SYS_ISO_ANALOG_IPS;
4960 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
4961
4962 /* 0x0020[0] = 0 disable LDOA12 MACRO block*/
4963 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
4964 val8 &= ~LDOA15_ENABLE;
4965 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
4966
4967exit:
4968 return ret;
4969}
4970
4971static int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv)
4972{
4973 u8 val8;
4974 u8 val32;
4975 int count, ret;
4976
4977 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
4978
4979 /*
4980 * Poll - wait for RX packet to complete
4981 */
4982 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
4983 val32 = rtl8xxxu_read32(priv, 0x5f8);
4984 if (!val32)
4985 break;
4986 udelay(10);
4987 }
4988
4989 if (!count) {
4990 dev_warn(&priv->udev->dev,
4991 "%s: RX poll timed out (0x05f8)\n", __func__);
4992 ret = -EBUSY;
4993 goto exit;
4994 }
4995
4996 /* Disable CCK and OFDM, clock gated */
4997 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
4998 val8 &= ~SYS_FUNC_BBRSTB;
4999 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
5000
5001 udelay(2);
5002
5003 /* Reset baseband */
5004 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
5005 val8 &= ~SYS_FUNC_BB_GLB_RSTN;
5006 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
5007
5008 /* Reset MAC TRX */
5009 val8 = rtl8xxxu_read8(priv, REG_CR);
5010 val8 = CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE;
5011 rtl8xxxu_write8(priv, REG_CR, val8);
5012
5013 /* Reset MAC TRX */
5014 val8 = rtl8xxxu_read8(priv, REG_CR + 1);
5015 val8 &= ~BIT(1); /* CR_SECURITY_ENABLE */
5016 rtl8xxxu_write8(priv, REG_CR + 1, val8);
5017
5018 /* Respond TX OK to scheduler */
5019 val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST);
5020 val8 |= DUAL_TSF_TX_OK;
5021 rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8);
5022
5023exit:
5024 return ret;
5025}
5026
c05a9dbf 5027static void rtl8723a_disabled_to_emu(struct rtl8xxxu_priv *priv)
26f1fad2
JS		 5028{
5029 u8 val8;
5030
5031 /* Clear suspend enable and power down enable*/
5032 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5033 val8 &= ~(BIT(3) | BIT(7));
5034 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5035
5036 /* 0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/
5037 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
5038 val8 &= ~BIT(0);
5039 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
5040
5041 /* 0x04[12:11] = 11 enable WL suspend*/
5042 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5043 val8 &= ~(BIT(3) | BIT(4));
5044 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5045}
5046
c05a9dbf
JS		 5047static void rtl8192e_disabled_to_emu(struct rtl8xxxu_priv *priv)
5048{
5049 u8 val8;
5050
5051 /* Clear suspend enable and power down enable*/
5052 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5053 val8 &= ~(BIT(3) | BIT(4));
5054 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5055}
5056
5057static int rtl8192e_emu_to_active(struct rtl8xxxu_priv *priv)
5058{
5059 u8 val8;
5060 u32 val32;
5061 int count, ret = 0;
5062
5063 /* disable HWPDN 0x04[15]=0*/
5064 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5065 val8 &= ~BIT(7);
5066 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5067
5068 /* disable SW LPS 0x04[10]= 0 */
5069 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5070 val8 &= ~BIT(2);
5071 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5072
5073 /* disable WL suspend*/
5074 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5075 val8 &= ~(BIT(3) | BIT(4));
5076 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5077
5078 /* wait till 0x04[17] = 1 power ready*/
5079 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5080 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5081 if (val32 & BIT(17))
5082 break;
5083
5084 udelay(10);
5085 }
5086
5087 if (!count) {
5088 ret = -EBUSY;
5089 goto exit;
5090 }
5091
5092 /* We should be able to optimize the following three entries into one */
5093
5094 /* release WLON reset 0x04[16]= 1*/
5095 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
5096 val8 |= BIT(0);
5097 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
5098
5099 /* set, then poll until 0 */
5100 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5101 val32 |= APS_FSMCO_MAC_ENABLE;
5102 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5103
5104 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5105 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5106 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
5107 ret = 0;
5108 break;
5109 }
5110 udelay(10);
5111 }
5112
5113 if (!count) {
5114 ret = -EBUSY;
5115 goto exit;
5116 }
5117
5118exit:
5119 return ret;
5120}
5121
5122static int rtl8723a_emu_to_active(struct rtl8xxxu_priv *priv)
26f1fad2
JS		 5123{
5124 u8 val8;
5125 u32 val32;
5126 int count, ret = 0;
5127
5128 /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface*/
5129 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
5130 val8 |= LDOA15_ENABLE;
5131 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
5132
5133 /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
5134 val8 = rtl8xxxu_read8(priv, 0x0067);
5135 val8 &= ~BIT(4);
5136 rtl8xxxu_write8(priv, 0x0067, val8);
5137
5138 mdelay(1);
5139
5140 /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
5141 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
5142 val8 &= ~SYS_ISO_ANALOG_IPS;
5143 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
5144
5145 /* disable SW LPS 0x04[10]= 0 */
5146 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5147 val8 &= ~BIT(2);
5148 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5149
5150 /* wait till 0x04[17] = 1 power ready*/
5151 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5152 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5153 if (val32 & BIT(17))
5154 break;
5155
5156 udelay(10);
5157 }
5158
5159 if (!count) {
5160 ret = -EBUSY;
5161 goto exit;
5162 }
5163
5164 /* We should be able to optimize the following three entries into one */
5165
5166 /* release WLON reset 0x04[16]= 1*/
5167 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
5168 val8 |= BIT(0);
5169 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
5170
5171 /* disable HWPDN 0x04[15]= 0*/
5172 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5173 val8 &= ~BIT(7);
5174 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5175
5176 /* disable WL suspend*/
5177 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5178 val8 &= ~(BIT(3) | BIT(4));
5179 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5180
5181 /* set, then poll until 0 */
5182 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5183 val32 |= APS_FSMCO_MAC_ENABLE;
5184 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5185
5186 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5187 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5188 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
5189 ret = 0;
5190 break;
5191 }
5192 udelay(10);
5193 }
5194
5195 if (!count) {
5196 ret = -EBUSY;
5197 goto exit;
5198 }
5199
5200 /* 0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */
5201 /*
5202 * Note: Vendor driver actually clears this bit, despite the
5203 * documentation claims it's being set!
5204 */
5205 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
5206 val8 |= LEDCFG2_DPDT_SELECT;
5207 val8 &= ~LEDCFG2_DPDT_SELECT;
5208 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
5209
5210exit:
5211 return ret;
5212}
5213
5214static int rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv *priv)
5215{
5216 u8 val8;
5217
5218 /* 0x0007[7:0] = 0x20 SOP option to disable BG/MB */
5219 rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20);
5220
5221 /* 0x04[12:11] = 01 enable WL suspend */
5222 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5223 val8 &= ~BIT(4);
5224 val8 |= BIT(3);
5225 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5226
5227 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5228 val8 |= BIT(7);
5229 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5230
5231 /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */
5232 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
5233 val8 |= BIT(0);
5234 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
5235
5236 return 0;
5237}
5238
5239static int rtl8723au_power_on(struct rtl8xxxu_priv *priv)
5240{
5241 u8 val8;
5242 u16 val16;
5243 u32 val32;
5244 int ret;
5245
5246 /*
5247 * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
5248 */
5249 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
5250
c05a9dbf 5251 rtl8723a_disabled_to_emu(priv);
26f1fad2 5252
c05a9dbf 5253 ret = rtl8723a_emu_to_active(priv);
26f1fad2
JS		 5254 if (ret)
5255 goto exit;
5256
5257 /*
5258 * 0x0004[19] = 1, reset 8051
5259 */
5260 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
5261 val8 |= BIT(3);
5262 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
5263
5264 /*
5265 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
5266 * Set CR bit10 to enable 32k calibration.
5267 */
5268 val16 = rtl8xxxu_read16(priv, REG_CR);
5269 val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
5270 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
5271 CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
5272 CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
5273 CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
5274 rtl8xxxu_write16(priv, REG_CR, val16);
5275
5276 /* For EFuse PG */
5277 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
5278 val32 &= ~(BIT(28) | BIT(29) | BIT(30));
5279 val32 |= (0x06 << 28);
5280 rtl8xxxu_write32(priv, REG_EFUSE_CTRL, val32);
5281exit:
5282 return ret;
5283}
5284
c0963772
KV		 5285#ifdef CONFIG_RTL8XXXU_UNTESTED
5286
26f1fad2
JS		 5287static int rtl8192cu_power_on(struct rtl8xxxu_priv *priv)
5288{
5289 u8 val8;
5290 u16 val16;
5291 u32 val32;
5292 int i;
5293
5294 for (i = 100; i; i--) {
5295 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO);
5296 if (val8 & APS_FSMCO_PFM_ALDN)
5297 break;
5298 }
5299
5300 if (!i) {
5301 pr_info("%s: Poll failed\n", __func__);
5302 return -ENODEV;
5303 }
5304
5305 /*
5306 * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
5307 */
5308 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
5309 rtl8xxxu_write8(priv, REG_SPS0_CTRL, 0x2b);
5310 udelay(100);
5311
5312 val8 = rtl8xxxu_read8(priv, REG_LDOV12D_CTRL);
5313 if (!(val8 & LDOV12D_ENABLE)) {
5314 pr_info("%s: Enabling LDOV12D (%02x)\n", __func__, val8);
5315 val8 |= LDOV12D_ENABLE;
5316 rtl8xxxu_write8(priv, REG_LDOV12D_CTRL, val8);
5317
5318 udelay(100);
5319
5320 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
5321 val8 &= ~SYS_ISO_MD2PP;
5322 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
5323 }
5324
5325 /*
5326 * Auto enable WLAN
5327 */
5328 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
5329 val16 |= APS_FSMCO_MAC_ENABLE;
5330 rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
5331
5332 for (i = 1000; i; i--) {
5333 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
5334 if (!(val16 & APS_FSMCO_MAC_ENABLE))
5335 break;
5336 }
5337 if (!i) {
5338 pr_info("%s: FSMCO_MAC_ENABLE poll failed\n", __func__);
5339 return -EBUSY;
5340 }
5341
5342 /*
5343 * Enable radio, GPIO, LED
5344 */
5345 val16 = APS_FSMCO_HW_SUSPEND | APS_FSMCO_ENABLE_POWERDOWN |
5346 APS_FSMCO_PFM_ALDN;
5347 rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
5348
5349 /*
5350 * Release RF digital isolation
5351 */
5352 val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
5353 val16 &= ~SYS_ISO_DIOR;
5354 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
5355
5356 val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
5357 val8 &= ~APSD_CTRL_OFF;
5358 rtl8xxxu_write8(priv, REG_APSD_CTRL, val8);
5359 for (i = 200; i; i--) {
5360 val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
5361 if (!(val8 & APSD_CTRL_OFF_STATUS))
5362 break;
5363 }
5364
5365 if (!i) {
5366 pr_info("%s: APSD_CTRL poll failed\n", __func__);
5367 return -EBUSY;
5368 }
5369
5370 /*
5371 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
5372 */
5373 val16 = rtl8xxxu_read16(priv, REG_CR);
5374 val16 |= CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
5375 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | CR_PROTOCOL_ENABLE |
5376 CR_SCHEDULE_ENABLE | CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE;
5377 rtl8xxxu_write16(priv, REG_CR, val16);
5378
5379 /*
5380 * Workaround for 8188RU LNA power leakage problem.
5381 */
5382 if (priv->rtlchip == 0x8188c && priv->hi_pa) {
5383 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
5384 val32 &= ~BIT(1);
5385 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
5386 }
5387 return 0;
5388}
5389
c0963772
KV		 5390#endif
5391
c05a9dbf
JS		 5392static int rtl8192eu_power_on(struct rtl8xxxu_priv *priv)
5393{
5394 u16 val16;
5395 u32 val32;
5396 int ret;
5397
5398 ret = 0;
5399
5400 val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
5401 if (val32 & SYS_CFG_SPS_LDO_SEL) {
5402 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0xc3);
5403 } else {
5404 /*
5405 * Raise 1.2V voltage
5406 */
5407 val32 = rtl8xxxu_read32(priv, REG_8192E_LDOV12_CTRL);
5408 val32 &= 0xff0fffff;
5409 val32 |= 0x00500000;
5410 rtl8xxxu_write32(priv, REG_8192E_LDOV12_CTRL, val32);
5411 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0x83);
5412 }
5413
5414 rtl8192e_disabled_to_emu(priv);
5415
5416 ret = rtl8192e_emu_to_active(priv);
5417 if (ret)
5418 goto exit;
5419
5420 rtl8xxxu_write16(priv, REG_CR, 0x0000);
5421
5422 /*
5423 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
5424 * Set CR bit10 to enable 32k calibration.
5425 */
5426 val16 = rtl8xxxu_read16(priv, REG_CR);
5427 val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
5428 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
5429 CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
5430 CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
5431 CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
5432 rtl8xxxu_write16(priv, REG_CR, val16);
5433
5434exit:
5435 return ret;
5436}
5437
26f1fad2
JS		 5438static void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv)
5439{
5440 u8 val8;
5441 u16 val16;
5442 u32 val32;
5443
5444 /*
5445 * Workaround for 8188RU LNA power leakage problem.
5446 */
5447 if (priv->rtlchip == 0x8188c && priv->hi_pa) {
5448 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
5449 val32 |= BIT(1);
5450 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
5451 }
5452
5453 rtl8xxxu_active_to_lps(priv);
5454
5455 /* Turn off RF */
5456 rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00);
5457
5458 /* Reset Firmware if running in RAM */
5459 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
5460 rtl8xxxu_firmware_self_reset(priv);
5461
5462 /* Reset MCU */
5463 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
5464 val16 &= ~SYS_FUNC_CPU_ENABLE;
5465 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
5466
5467 /* Reset MCU ready status */
5468 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
5469
5470 rtl8xxxu_active_to_emu(priv);
5471 rtl8xxxu_emu_to_disabled(priv);
5472
5473 /* Reset MCU IO Wrapper */
5474 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
5475 val8 &= ~BIT(0);
5476 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
5477
5478 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
5479 val8 |= BIT(0);
5480 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
5481
5482 /* RSV_CTRL 0x1C[7:0] = 0x0e lock ISO/CLK/Power control register */
5483 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0e);
5484}
5485
5486static void rtl8xxxu_init_bt(struct rtl8xxxu_priv *priv)
5487{
5488 if (!priv->has_bluetooth)
5489 return;
5490}
5491
5492static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
5493{
5494 struct rtl8xxxu_priv *priv = hw->priv;
5495 struct device *dev = &priv->udev->dev;
5496 struct rtl8xxxu_rfregval *rftable;
5497 bool macpower;
5498 int ret;
5499 u8 val8;
5500 u16 val16;
5501 u32 val32;
5502
5503 /* Check if MAC is already powered on */
5504 val8 = rtl8xxxu_read8(priv, REG_CR);
5505
5506 /*
5507 * Fix 92DU-VC S3 hang with the reason is that secondary mac is not
5508 * initialized. First MAC returns 0xea, second MAC returns 0x00
5509 */
5510 if (val8 == 0xea)
5511 macpower = false;
5512 else
5513 macpower = true;
5514
5515 ret = priv->fops->power_on(priv);
5516 if (ret < 0) {
5517 dev_warn(dev, "%s: Failed power on\n", __func__);
5518 goto exit;
5519 }
5520
07bb46be
JS		 5521 dev_dbg(dev, "%s: macpower %i\n", __func__, macpower);
5522 if (!macpower) {
5523 if (priv->ep_tx_normal_queue)
5524 val8 = TX_PAGE_NUM_NORM_PQ;
5525 else
5526 val8 = 0;
5527
5528 rtl8xxxu_write8(priv, REG_RQPN_NPQ, val8);
5529
5530 val32 = (TX_PAGE_NUM_PUBQ << RQPN_NORM_PQ_SHIFT) | RQPN_LOAD;
5531
5532 if (priv->ep_tx_high_queue)
5533 val32 |= (TX_PAGE_NUM_HI_PQ << RQPN_HI_PQ_SHIFT);
5534 if (priv->ep_tx_low_queue)
5535 val32 |= (TX_PAGE_NUM_LO_PQ << RQPN_LO_PQ_SHIFT);
5536
5537 rtl8xxxu_write32(priv, REG_RQPN, val32);
5538
5539 /*
5540 * Set TX buffer boundary
5541 */
5542 val8 = TX_TOTAL_PAGE_NUM + 1;
5543 rtl8xxxu_write8(priv, REG_TXPKTBUF_BCNQ_BDNY, val8);
5544 rtl8xxxu_write8(priv, REG_TXPKTBUF_MGQ_BDNY, val8);
5545 rtl8xxxu_write8(priv, REG_TXPKTBUF_WMAC_LBK_BF_HD, val8);
5546 rtl8xxxu_write8(priv, REG_TRXFF_BNDY, val8);
5547 rtl8xxxu_write8(priv, REG_TDECTRL + 1, val8);
5548 }
5549
a47b9d47
JS		 5550 ret = rtl8xxxu_download_firmware(priv);
5551 dev_dbg(dev, "%s: download_fiwmare %i\n", __func__, ret);
5552 if (ret)
5553 goto exit;
5554 ret = rtl8xxxu_start_firmware(priv);
5555 dev_dbg(dev, "%s: start_fiwmare %i\n", __func__, ret);
5556 if (ret)
5557 goto exit;
5558
07bb46be
JS		 5559 ret = rtl8xxxu_init_queue_priority(priv);
5560 dev_dbg(dev, "%s: init_queue_priority %i\n", __func__, ret);
5561 if (ret)
5562 goto exit;
5563
26f1fad2
JS		 5564 dev_dbg(dev, "%s: macpower %i\n", __func__, macpower);
5565 if (!macpower) {
74b99bed 5566 ret = priv->fops->llt_init(priv, TX_TOTAL_PAGE_NUM);
26f1fad2
JS		 5567 if (ret) {
5568 dev_warn(dev, "%s: LLT table init failed\n", __func__);
5569 goto exit;
5570 }
5571 }
5572
6431ea00
JS		 5573 /* Fix USB interface interference issue */
5574 if (priv->rtlchip == 0x8723a) {
5575 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
5576 rtl8xxxu_write8(priv, 0xfe41, 0x8d);
5577 rtl8xxxu_write8(priv, 0xfe42, 0x80);
5578 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, 0xfd0320);
5579 } else {
b63d0aac
JS		 5580 val32 = rtl8xxxu_read32(priv, REG_TXDMA_OFFSET_CHK);
5581 val32 |= TXDMA_OFFSET_DROP_DATA_EN;
5582 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, val32);
6431ea00 5583 }
99ad16cb 5584
6431ea00
JS		 5585 /* Solve too many protocol error on USB bus */
5586 /* Can't do this for 8188/8192 UMC A cut parts */
5587 if (priv->rtlchip == 0x8723a ||
5588 ((priv->rtlchip == 0x8192c || priv->rtlchip == 0x8191c ||
5589 priv->rtlchip == 0x8188c) &&
5590 (priv->chip_cut || !priv->vendor_umc))) {
5591 rtl8xxxu_write8(priv, 0xfe40, 0xe6);
5592 rtl8xxxu_write8(priv, 0xfe41, 0x94);
5593 rtl8xxxu_write8(priv, 0xfe42, 0x80);
5594
5595 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
5596 rtl8xxxu_write8(priv, 0xfe41, 0x19);
5597 rtl8xxxu_write8(priv, 0xfe42, 0x80);
5598
5599 rtl8xxxu_write8(priv, 0xfe40, 0xe5);
5600 rtl8xxxu_write8(priv, 0xfe41, 0x91);
5601 rtl8xxxu_write8(priv, 0xfe42, 0x80);
5602
5603 rtl8xxxu_write8(priv, 0xfe40, 0xe2);
5604 rtl8xxxu_write8(priv, 0xfe41, 0x81);
5605 rtl8xxxu_write8(priv, 0xfe42, 0x80);
5606 }
5607
5608 if (priv->rtlchip == 0x8192e || priv->rtlchip == 0x8723b) {
99ad16cb
JS		 5609 rtl8xxxu_write32(priv, REG_HIMR0, 0x00);
5610 rtl8xxxu_write32(priv, REG_HIMR1, 0x00);
b63d0aac
JS		 5611 }
5612
f0d9f5e9
JS		 5613 if (priv->fops->phy_init_antenna_selection)
5614 priv->fops->phy_init_antenna_selection(priv);
5615
b7dd8ff9
JS		 5616 if (priv->rtlchip == 0x8723b)
5617 ret = rtl8xxxu_init_mac(priv, rtl8723b_mac_init_table);
5618 else
5619 ret = rtl8xxxu_init_mac(priv, rtl8723a_mac_init_table);
5620
26f1fad2
JS		 5621 dev_dbg(dev, "%s: init_mac %i\n", __func__, ret);
5622 if (ret)
5623 goto exit;
5624
5625 ret = rtl8xxxu_init_phy_bb(priv);
5626 dev_dbg(dev, "%s: init_phy_bb %i\n", __func__, ret);
5627 if (ret)
5628 goto exit;
5629
5630 switch(priv->rtlchip) {
5631 case 0x8723a:
5632 rftable = rtl8723au_radioa_1t_init_table;
5633 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
5634 break;
22a31d45
JS		 5635 case 0x8723b:
5636 rftable = rtl8723bu_radioa_1t_init_table;
5637 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
5638 break;
26f1fad2
JS		 5639 case 0x8188c:
5640 if (priv->hi_pa)
5641 rftable = rtl8188ru_radioa_1t_highpa_table;
5642 else
5643 rftable = rtl8192cu_radioa_1t_init_table;
5644 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
5645 break;
5646 case 0x8191c:
5647 rftable = rtl8192cu_radioa_1t_init_table;
5648 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
5649 break;
5650 case 0x8192c:
5651 rftable = rtl8192cu_radioa_2t_init_table;
5652 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
5653 if (ret)
5654 break;
5655 rftable = rtl8192cu_radiob_2t_init_table;
5656 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_B);
5657 break;
5658 default:
5659 ret = -EINVAL;
5660 }
5661
5662 if (ret)
5663 goto exit;
5664
5665 /* Reduce 80M spur */
5666 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x0381808d);
5667 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
5668 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff82);
5669 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
5670
5671 /* RFSW Control - clear bit 14 ?? */
5672 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003);
5673 /* 0x07000760 */
5674 val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW |
5675 FPGA0_RF_ANTSWB | FPGA0_RF_PAPE |
5676 ((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB | FPGA0_RF_PAPE) <<
5677 FPGA0_RF_BD_CTRL_SHIFT);
5678 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
5679 /* 0x860[6:5]= 00 - why? - this sets antenna B */
5680 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66F60210);
5681
5682 priv->rf_mode_ag[0] = rtl8xxxu_read_rfreg(priv, RF_A,
5683 RF6052_REG_MODE_AG);
5684
26f1fad2
JS		 5685 /*
5686 * Set RX page boundary
5687 */
5688 rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, 0x27ff);
5689 /*
5690 * Transfer page size is always 128
5691 */
5692 val8 = (PBP_PAGE_SIZE_128 << PBP_PAGE_SIZE_RX_SHIFT) |
5693 (PBP_PAGE_SIZE_128 << PBP_PAGE_SIZE_TX_SHIFT);
5694 rtl8xxxu_write8(priv, REG_PBP, val8);
5695
5696 /*
5697 * Unit in 8 bytes, not obvious what it is used for
5698 */
5699 rtl8xxxu_write8(priv, REG_RX_DRVINFO_SZ, 4);
5700
5701 /*
5702 * Enable all interrupts - not obvious USB needs to do this
5703 */
5704 rtl8xxxu_write32(priv, REG_HISR, 0xffffffff);
5705 rtl8xxxu_write32(priv, REG_HIMR, 0xffffffff);
5706
5707 rtl8xxxu_set_mac(priv);
5708 rtl8xxxu_set_linktype(priv, NL80211_IFTYPE_STATION);
5709
5710 /*
5711 * Configure initial WMAC settings
5712 */
5713 val32 = RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_MCAST | RCR_ACCEPT_BCAST |
26f1fad2
JS		 5714 RCR_ACCEPT_MGMT_FRAME | RCR_HTC_LOC_CTRL |
5715 RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC;
5716 rtl8xxxu_write32(priv, REG_RCR, val32);
5717
5718 /*
5719 * Accept all multicast
5720 */
5721 rtl8xxxu_write32(priv, REG_MAR, 0xffffffff);
5722 rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff);
5723
5724 /*
5725 * Init adaptive controls
5726 */
5727 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
5728 val32 &= ~RESPONSE_RATE_BITMAP_ALL;
5729 val32 |= RESPONSE_RATE_RRSR_CCK_ONLY_1M;
5730 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
5731
5732 /* CCK = 0x0a, OFDM = 0x10 */
5733 rtl8xxxu_set_spec_sifs(priv, 0x10, 0x10);
5734 rtl8xxxu_set_retry(priv, 0x30, 0x30);
5735 rtl8xxxu_set_spec_sifs(priv, 0x0a, 0x10);
5736
5737 /*
5738 * Init EDCA
5739 */
5740 rtl8xxxu_write16(priv, REG_MAC_SPEC_SIFS, 0x100a);
5741
5742 /* Set CCK SIFS */
5743 rtl8xxxu_write16(priv, REG_SIFS_CCK, 0x100a);
5744
5745 /* Set OFDM SIFS */
5746 rtl8xxxu_write16(priv, REG_SIFS_OFDM, 0x100a);
5747
5748 /* TXOP */
5749 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, 0x005ea42b);
5750 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, 0x0000a44f);
5751 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, 0x005ea324);
5752 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, 0x002fa226);
5753
5754 /* Set data auto rate fallback retry count */
5755 rtl8xxxu_write32(priv, REG_DARFRC, 0x00000000);
5756 rtl8xxxu_write32(priv, REG_DARFRC + 4, 0x10080404);
5757 rtl8xxxu_write32(priv, REG_RARFRC, 0x04030201);
5758 rtl8xxxu_write32(priv, REG_RARFRC + 4, 0x08070605);
5759
5760 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL);
5761 val8 |= FWHW_TXQ_CTRL_AMPDU_RETRY;
5762 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, val8);
5763
5764 /* Set ACK timeout */
5765 rtl8xxxu_write8(priv, REG_ACKTO, 0x40);
5766
5767 /*
5768 * Initialize beacon parameters
5769 */
5770 val16 = BEACON_DISABLE_TSF_UPDATE | (BEACON_DISABLE_TSF_UPDATE << 8);
5771 rtl8xxxu_write16(priv, REG_BEACON_CTRL, val16);
5772 rtl8xxxu_write16(priv, REG_TBTT_PROHIBIT, 0x6404);
5773 rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME);
5774 rtl8xxxu_write8(priv, REG_BEACON_DMA_TIME, BEACON_DMA_ATIME_INT_TIME);
5775 rtl8xxxu_write16(priv, REG_BEACON_TCFG, 0x660F);
5776
5777 /*
5778 * Enable CCK and OFDM block
5779 */
5780 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
5781 val32 |= (FPGA_RF_MODE_CCK | FPGA_RF_MODE_OFDM);
5782 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
5783
5784 /*
5785 * Invalidate all CAM entries - bit 30 is undocumented
5786 */
5787 rtl8xxxu_write32(priv, REG_CAM_CMD, CAM_CMD_POLLING | BIT(30));
5788
5789 /*
5790 * Start out with default power levels for channel 6, 20MHz
5791 */
5792 rtl8723a_set_tx_power(priv, 1, false);
5793
5794 /* Let the 8051 take control of antenna setting */
5795 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
5796 val8 |= LEDCFG2_DPDT_SELECT;
5797 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
5798
5799 rtl8xxxu_write8(priv, REG_HWSEQ_CTRL, 0xff);
5800
5801 /* Disable BAR - not sure if this has any effect on USB */
5802 rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff);
5803
5804 rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0);
5805
fa0f2d48
JS		 5806 rtl8723a_phy_lc_calibrate(priv);
5807
e1547c53 5808 priv->fops->phy_iq_calibrate(priv);
26f1fad2
JS		 5809
5810 /*
5811 * This should enable thermal meter
5812 */
5813 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER, 0x60);
5814
26f1fad2
JS		 5815 /* Init BT hw config. */
5816 rtl8xxxu_init_bt(priv);
5817
5818 /*
5819 * Not sure if we really need to save these parameters, but the
5820 * vendor driver does
5821 */
5822 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
5823 if (val32 & FPGA0_HSSI_PARM2_CCK_HIGH_PWR)
5824 priv->path_a_hi_power = 1;
5825
5826 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
5827 priv->path_a_rf_paths = val32 & OFDM_RF_PATH_RX_MASK;
5828
5829 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);
5830 priv->path_a_ig_value = val32 & OFDM0_X_AGC_CORE1_IGI_MASK;
5831
5832 /* Set NAV_UPPER to 30000us */
5833 val8 = ((30000 + NAV_UPPER_UNIT - 1) / NAV_UPPER_UNIT);
5834 rtl8xxxu_write8(priv, REG_NAV_UPPER, val8);
5835
4042e617
JS		 5836 if (priv->rtlchip == 0x8723a) {
5837 /*
5838 * 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test,
5839 * but we need to find root cause.
5840 * This is 8723au only.
5841 */
5842 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
5843 if ((val32 & 0xff000000) != 0x83000000) {
5844 val32 |= FPGA_RF_MODE_CCK;
5845 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
5846 }
26f1fad2
JS		 5847 }
5848
5849 val32 = rtl8xxxu_read32(priv, REG_FWHW_TXQ_CTRL);
5850 val32 |= FWHW_TXQ_CTRL_XMIT_MGMT_ACK;
5851 /* ack for xmit mgmt frames. */
5852 rtl8xxxu_write32(priv, REG_FWHW_TXQ_CTRL, val32);
5853
5854exit:
5855 return ret;
5856}
5857
5858static void rtl8xxxu_disable_device(struct ieee80211_hw *hw)
5859{
5860 struct rtl8xxxu_priv *priv = hw->priv;
5861
5862 rtl8xxxu_power_off(priv);
5863}
5864
5865static void rtl8xxxu_cam_write(struct rtl8xxxu_priv *priv,
5866 struct ieee80211_key_conf *key, const u8 *mac)
5867{
5868 u32 cmd, val32, addr, ctrl;
5869 int j, i, tmp_debug;
5870
5871 tmp_debug = rtl8xxxu_debug;
5872 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_KEY)
5873 rtl8xxxu_debug |= RTL8XXXU_DEBUG_REG_WRITE;
5874
5875 /*
5876 * This is a bit of a hack - the lower bits of the cipher
5877 * suite selector happens to match the cipher index in the CAM
5878 */
5879 addr = key->keyidx << CAM_CMD_KEY_SHIFT;
5880 ctrl = (key->cipher & 0x0f) << 2 | key->keyidx | CAM_WRITE_VALID;
5881
5882 for (j = 5; j >= 0; j--) {
5883 switch (j) {
5884 case 0:
5885 val32 = ctrl | (mac[0] << 16) | (mac[1] << 24);
5886 break;
5887 case 1:
5888 val32 = mac[2] | (mac[3] << 8) |
5889 (mac[4] << 16) | (mac[5] << 24);
5890 break;
5891 default:
5892 i = (j - 2) << 2;
5893 val32 = key->key[i] | (key->key[i + 1] << 8) |
5894 key->key[i + 2] << 16 | key->key[i + 3] << 24;
5895 break;
5896 }
5897
5898 rtl8xxxu_write32(priv, REG_CAM_WRITE, val32);
5899 cmd = CAM_CMD_POLLING | CAM_CMD_WRITE | (addr + j);
5900 rtl8xxxu_write32(priv, REG_CAM_CMD, cmd);
5901 udelay(100);
5902 }
5903
5904 rtl8xxxu_debug = tmp_debug;
5905}
5906
5907static void rtl8xxxu_sw_scan_start(struct ieee80211_hw *hw,
56e4374a 5908 struct ieee80211_vif *vif, const u8 *mac)
26f1fad2
JS		 5909{
5910 struct rtl8xxxu_priv *priv = hw->priv;
5911 u8 val8;
5912
5913 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
5914 val8 |= BEACON_DISABLE_TSF_UPDATE;
5915 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
5916}
5917
5918static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw *hw,
5919 struct ieee80211_vif *vif)
5920{
5921 struct rtl8xxxu_priv *priv = hw->priv;
5922 u8 val8;
5923
5924 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
5925 val8 &= ~BEACON_DISABLE_TSF_UPDATE;
5926 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
5927}
5928
5929static void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv,
5930 u32 ramask, int sgi)
5931{
5932 struct h2c_cmd h2c;
5933
5934 h2c.ramask.cmd = H2C_SET_RATE_MASK;
5935 h2c.ramask.mask_lo = cpu_to_le16(ramask & 0xffff);
5936 h2c.ramask.mask_hi = cpu_to_le16(ramask >> 16);
5937
5938 h2c.ramask.arg = 0x80;
5939 if (sgi)
5940 h2c.ramask.arg |= 0x20;
5941
7ff8c1ae 5942 dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %zi\n",
8da91571
JS		 5943 __func__, ramask, h2c.ramask.arg, sizeof(h2c.ramask));
5944 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.ramask));
26f1fad2
JS		 5945}
5946
5947static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv *priv, u32 rate_cfg)
5948{
5949 u32 val32;
5950 u8 rate_idx = 0;
5951
5952 rate_cfg &= RESPONSE_RATE_BITMAP_ALL;
5953
5954 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
5955 val32 &= ~RESPONSE_RATE_BITMAP_ALL;
5956 val32 |= rate_cfg;
5957 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
5958
5959 dev_dbg(&priv->udev->dev, "%s: rates %08x\n", __func__, rate_cfg);
5960
5961 while (rate_cfg) {
5962 rate_cfg = (rate_cfg >> 1);
5963 rate_idx++;
5964 }
5965 rtl8xxxu_write8(priv, REG_INIRTS_RATE_SEL, rate_idx);
5966}
5967
5968static void
5969rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5970 struct ieee80211_bss_conf *bss_conf, u32 changed)
5971{
5972 struct rtl8xxxu_priv *priv = hw->priv;
5973 struct device *dev = &priv->udev->dev;
5974 struct ieee80211_sta *sta;
5975 u32 val32;
5976 u8 val8;
5977
5978 if (changed & BSS_CHANGED_ASSOC) {
5979 struct h2c_cmd h2c;
5980
5981 dev_dbg(dev, "Changed ASSOC: %i!\n", bss_conf->assoc);
5982
5983 memset(&h2c, 0, sizeof(struct h2c_cmd));
5984 rtl8xxxu_set_linktype(priv, vif->type);
5985
5986 if (bss_conf->assoc) {
5987 u32 ramask;
5988 int sgi = 0;
5989
5990 rcu_read_lock();
5991 sta = ieee80211_find_sta(vif, bss_conf->bssid);
5992 if (!sta) {
5993 dev_info(dev, "%s: ASSOC no sta found\n",
5994 __func__);
5995 rcu_read_unlock();
5996 goto error;
5997 }
5998
5999 if (sta->ht_cap.ht_supported)
6000 dev_info(dev, "%s: HT supported\n", __func__);
6001 if (sta->vht_cap.vht_supported)
6002 dev_info(dev, "%s: VHT supported\n", __func__);
6003
6004 /* TODO: Set bits 28-31 for rate adaptive id */
6005 ramask = (sta->supp_rates[0] & 0xfff) |
6006 sta->ht_cap.mcs.rx_mask[0] << 12 |
6007 sta->ht_cap.mcs.rx_mask[1] << 20;
6008 if (sta->ht_cap.cap &
6009 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))
6010 sgi = 1;
6011 rcu_read_unlock();
6012
6013 rtl8xxxu_update_rate_mask(priv, ramask, sgi);
6014
26f1fad2
JS		 6015 rtl8xxxu_write8(priv, REG_BCN_MAX_ERR, 0xff);
6016
6017 rtl8723a_stop_tx_beacon(priv);
6018
6019 /* joinbss sequence */
6020 rtl8xxxu_write16(priv, REG_BCN_PSR_RPT,
6021 0xc000 | bss_conf->aid);
6022
6023 h2c.joinbss.data = H2C_JOIN_BSS_CONNECT;
6024 } else {
26f1fad2
JS		 6025 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
6026 val8 |= BEACON_DISABLE_TSF_UPDATE;
6027 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
6028
26f1fad2
JS		 6029 h2c.joinbss.data = H2C_JOIN_BSS_DISCONNECT;
6030 }
6031 h2c.joinbss.cmd = H2C_JOIN_BSS_REPORT;
8da91571 6032 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.joinbss));
26f1fad2
JS		 6033 }
6034
6035 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
6036 dev_dbg(dev, "Changed ERP_PREAMBLE: Use short preamble %i\n",
6037 bss_conf->use_short_preamble);
6038 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
6039 if (bss_conf->use_short_preamble)
6040 val32 |= RSR_ACK_SHORT_PREAMBLE;
6041 else
6042 val32 &= ~RSR_ACK_SHORT_PREAMBLE;
6043 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
6044 }
6045
6046 if (changed & BSS_CHANGED_ERP_SLOT) {
6047 dev_dbg(dev, "Changed ERP_SLOT: short_slot_time %i\n",
6048 bss_conf->use_short_slot);
6049
6050 if (bss_conf->use_short_slot)
6051 val8 = 9;
6052 else
6053 val8 = 20;
6054 rtl8xxxu_write8(priv, REG_SLOT, val8);
6055 }
6056
6057 if (changed & BSS_CHANGED_BSSID) {
6058 dev_dbg(dev, "Changed BSSID!\n");
6059 rtl8xxxu_set_bssid(priv, bss_conf->bssid);
6060 }
6061
6062 if (changed & BSS_CHANGED_BASIC_RATES) {
6063 dev_dbg(dev, "Changed BASIC_RATES!\n");
6064 rtl8xxxu_set_basic_rates(priv, bss_conf->basic_rates);
6065 }
6066error:
6067 return;
6068}
6069
6070static u32 rtl8xxxu_80211_to_rtl_queue(u32 queue)
6071{
6072 u32 rtlqueue;
6073
6074 switch (queue) {
6075 case IEEE80211_AC_VO:
6076 rtlqueue = TXDESC_QUEUE_VO;
6077 break;
6078 case IEEE80211_AC_VI:
6079 rtlqueue = TXDESC_QUEUE_VI;
6080 break;
6081 case IEEE80211_AC_BE:
6082 rtlqueue = TXDESC_QUEUE_BE;
6083 break;
6084 case IEEE80211_AC_BK:
6085 rtlqueue = TXDESC_QUEUE_BK;
6086 break;
6087 default:
6088 rtlqueue = TXDESC_QUEUE_BE;
6089 }
6090
6091 return rtlqueue;
6092}
6093
6094static u32 rtl8xxxu_queue_select(struct ieee80211_hw *hw, struct sk_buff *skb)
6095{
6096 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
6097 u32 queue;
6098
6099 if (ieee80211_is_mgmt(hdr->frame_control))
6100 queue = TXDESC_QUEUE_MGNT;
6101 else
6102 queue = rtl8xxxu_80211_to_rtl_queue(skb_get_queue_mapping(skb));
6103
6104 return queue;
6105}
6106
6107static void rtl8xxxu_calc_tx_desc_csum(struct rtl8xxxu_tx_desc *tx_desc)
6108{
6109 __le16 *ptr = (__le16 *)tx_desc;
6110 u16 csum = 0;
6111 int i;
6112
6113 /*
6114 * Clear csum field before calculation, as the csum field is
6115 * in the middle of the struct.
6116 */
6117 tx_desc->csum = cpu_to_le16(0);
6118
6119 for (i = 0; i < (sizeof(struct rtl8xxxu_tx_desc) / sizeof(u16)); i++)
6120 csum = csum ^ le16_to_cpu(ptr[i]);
6121
6122 tx_desc->csum |= cpu_to_le16(csum);
6123}
6124
6125static void rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv *priv)
6126{
6127 struct rtl8xxxu_tx_urb *tx_urb, *tmp;
6128 unsigned long flags;
6129
6130 spin_lock_irqsave(&priv->tx_urb_lock, flags);
6131 list_for_each_entry_safe(tx_urb, tmp, &priv->tx_urb_free_list, list) {
6132 list_del(&tx_urb->list);
6133 priv->tx_urb_free_count--;
6134 usb_free_urb(&tx_urb->urb);
6135 }
6136 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
6137}
6138
6139static struct rtl8xxxu_tx_urb *
6140rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv *priv)
6141{
6142 struct rtl8xxxu_tx_urb *tx_urb;
6143 unsigned long flags;
6144
6145 spin_lock_irqsave(&priv->tx_urb_lock, flags);
6146 tx_urb = list_first_entry_or_null(&priv->tx_urb_free_list,
6147 struct rtl8xxxu_tx_urb, list);
6148 if (tx_urb) {
6149 list_del(&tx_urb->list);
6150 priv->tx_urb_free_count--;
6151 if (priv->tx_urb_free_count < RTL8XXXU_TX_URB_LOW_WATER &&
6152 !priv->tx_stopped) {
6153 priv->tx_stopped = true;
6154 ieee80211_stop_queues(priv->hw);
6155 }
6156 }
6157
6158 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
6159
6160 return tx_urb;
6161}
6162
6163static void rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv *priv,
6164 struct rtl8xxxu_tx_urb *tx_urb)
6165{
6166 unsigned long flags;
6167
6168 INIT_LIST_HEAD(&tx_urb->list);
6169
6170 spin_lock_irqsave(&priv->tx_urb_lock, flags);
6171
6172 list_add(&tx_urb->list, &priv->tx_urb_free_list);
6173 priv->tx_urb_free_count++;
6174 if (priv->tx_urb_free_count > RTL8XXXU_TX_URB_HIGH_WATER &&
6175 priv->tx_stopped) {
6176 priv->tx_stopped = false;
6177 ieee80211_wake_queues(priv->hw);
6178 }
6179
6180 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
6181}
6182
6183static void rtl8xxxu_tx_complete(struct urb *urb)
6184{
6185 struct sk_buff *skb = (struct sk_buff *)urb->context;
6186 struct ieee80211_tx_info *tx_info;
6187 struct ieee80211_hw *hw;
6188 struct rtl8xxxu_tx_urb *tx_urb =
6189 container_of(urb, struct rtl8xxxu_tx_urb, urb);
6190
6191 tx_info = IEEE80211_SKB_CB(skb);
6192 hw = tx_info->rate_driver_data[0];
6193
6194 skb_pull(skb, sizeof(struct rtl8xxxu_tx_desc));
6195
6196 ieee80211_tx_info_clear_status(tx_info);
6197 tx_info->status.rates[0].idx = -1;
6198 tx_info->status.rates[0].count = 0;
6199
6200 if (!urb->status)
6201 tx_info->flags |= IEEE80211_TX_STAT_ACK;
6202
6203 ieee80211_tx_status_irqsafe(hw, skb);
6204
6205 rtl8xxxu_free_tx_urb(hw->priv, tx_urb);
6206}
6207
6208static void rtl8xxxu_dump_action(struct device *dev,
6209 struct ieee80211_hdr *hdr)
6210{
6211 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr;
6212 u16 cap, timeout;
6213
6214 if (!(rtl8xxxu_debug & RTL8XXXU_DEBUG_ACTION))
6215 return;
6216
6217 switch (mgmt->u.action.u.addba_resp.action_code) {
6218 case WLAN_ACTION_ADDBA_RESP:
6219 cap = le16_to_cpu(mgmt->u.action.u.addba_resp.capab);
6220 timeout = le16_to_cpu(mgmt->u.action.u.addba_resp.timeout);
6221 dev_info(dev, "WLAN_ACTION_ADDBA_RESP: "
6222 "timeout %i, tid %02x, buf_size %02x, policy %02x, "
6223 "status %02x\n",
6224 timeout,
6225 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
6226 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
6227 (cap >> 1) & 0x1,
6228 le16_to_cpu(mgmt->u.action.u.addba_resp.status));
6229 break;
6230 case WLAN_ACTION_ADDBA_REQ:
6231 cap = le16_to_cpu(mgmt->u.action.u.addba_req.capab);
6232 timeout = le16_to_cpu(mgmt->u.action.u.addba_req.timeout);
6233 dev_info(dev, "WLAN_ACTION_ADDBA_REQ: "
6234 "timeout %i, tid %02x, buf_size %02x, policy %02x\n",
6235 timeout,
6236 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
6237 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
6238 (cap >> 1) & 0x1);
6239 break;
6240 default:
6241 dev_info(dev, "action frame %02x\n",
6242 mgmt->u.action.u.addba_resp.action_code);
6243 break;
6244 }
6245}
6246
6247static void rtl8xxxu_tx(struct ieee80211_hw *hw,
6248 struct ieee80211_tx_control *control,
6249 struct sk_buff *skb)
6250{
6251 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
6252 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
6253 struct ieee80211_rate *tx_rate = ieee80211_get_tx_rate(hw, tx_info);
6254 struct rtl8xxxu_priv *priv = hw->priv;
6255 struct rtl8xxxu_tx_desc *tx_desc;
6256 struct rtl8xxxu_tx_urb *tx_urb;
6257 struct ieee80211_sta *sta = NULL;
6258 struct ieee80211_vif *vif = tx_info->control.vif;
6259 struct device *dev = &priv->udev->dev;
6260 u32 queue, rate;
6261 u16 pktlen = skb->len;
6262 u16 seq_number;
6263 u16 rate_flag = tx_info->control.rates[0].flags;
6264 int ret;
6265
6266 if (skb_headroom(skb) < sizeof(struct rtl8xxxu_tx_desc)) {
6267 dev_warn(dev,
6268 "%s: Not enough headroom (%i) for tx descriptor\n",
6269 __func__, skb_headroom(skb));
6270 goto error;
6271 }
6272
6273 if (unlikely(skb->len > (65535 - sizeof(struct rtl8xxxu_tx_desc)))) {
6274 dev_warn(dev, "%s: Trying to send over-sized skb (%i)\n",
6275 __func__, skb->len);
6276 goto error;
6277 }
6278
6279 tx_urb = rtl8xxxu_alloc_tx_urb(priv);
6280 if (!tx_urb) {
6281 dev_warn(dev, "%s: Unable to allocate tx urb\n", __func__);
6282 goto error;
6283 }
6284
6285 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX)
6286 dev_info(dev, "%s: TX rate: %d (%d), pkt size %d\n",
6287 __func__, tx_rate->bitrate, tx_rate->hw_value, pktlen);
6288
6289 if (ieee80211_is_action(hdr->frame_control))
6290 rtl8xxxu_dump_action(dev, hdr);
6291
6292 tx_info->rate_driver_data[0] = hw;
6293
6294 if (control && control->sta)
6295 sta = control->sta;
6296
6297 tx_desc = (struct rtl8xxxu_tx_desc *)
6298 skb_push(skb, sizeof(struct rtl8xxxu_tx_desc));
6299
6300 memset(tx_desc, 0, sizeof(struct rtl8xxxu_tx_desc));
6301 tx_desc->pkt_size = cpu_to_le16(pktlen);
6302 tx_desc->pkt_offset = sizeof(struct rtl8xxxu_tx_desc);
6303
6304 tx_desc->txdw0 =
6305 TXDESC_OWN | TXDESC_FIRST_SEGMENT | TXDESC_LAST_SEGMENT;
6306 if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
6307 is_broadcast_ether_addr(ieee80211_get_DA(hdr)))
6308 tx_desc->txdw0 |= TXDESC_BROADMULTICAST;
6309
6310 queue = rtl8xxxu_queue_select(hw, skb);
6311 tx_desc->txdw1 = cpu_to_le32(queue << TXDESC_QUEUE_SHIFT);
6312
6313 if (tx_info->control.hw_key) {
6314 switch (tx_info->control.hw_key->cipher) {
6315 case WLAN_CIPHER_SUITE_WEP40:
6316 case WLAN_CIPHER_SUITE_WEP104:
6317 case WLAN_CIPHER_SUITE_TKIP:
6318 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_RC4);
6319 break;
6320 case WLAN_CIPHER_SUITE_CCMP:
6321 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_AES);
6322 break;
6323 default:
6324 break;
6325 }
6326 }
6327
6328 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
6329 tx_desc->txdw3 = cpu_to_le32((u32)seq_number << TXDESC_SEQ_SHIFT);
6330
6331 if (rate_flag & IEEE80211_TX_RC_MCS)
6332 rate = tx_info->control.rates[0].idx + DESC_RATE_MCS0;
6333 else
6334 rate = tx_rate->hw_value;
6335 tx_desc->txdw5 = cpu_to_le32(rate);
6336
6337 if (ieee80211_is_data(hdr->frame_control))
6338 tx_desc->txdw5 |= cpu_to_le32(0x0001ff00);
6339
6340 /* (tx_info->flags & IEEE80211_TX_CTL_AMPDU) && */
6341 if (ieee80211_is_data_qos(hdr->frame_control) && sta) {
6342 if (sta->ht_cap.ht_supported) {
6343 u32 ampdu, val32;
6344
6345 ampdu = (u32)sta->ht_cap.ampdu_density;
6346 val32 = ampdu << TXDESC_AMPDU_DENSITY_SHIFT;
6347 tx_desc->txdw2 |= cpu_to_le32(val32);
6348 tx_desc->txdw1 |= cpu_to_le32(TXDESC_AGG_ENABLE);
6349 } else
6350 tx_desc->txdw1 |= cpu_to_le32(TXDESC_BK);
6351 } else
6352 tx_desc->txdw1 |= cpu_to_le32(TXDESC_BK);
6353
6354 if (ieee80211_is_data_qos(hdr->frame_control))
6355 tx_desc->txdw4 |= cpu_to_le32(TXDESC_QOS);
6356 if (rate_flag & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ||
6357 (sta && vif && vif->bss_conf.use_short_preamble))
6358 tx_desc->txdw4 |= cpu_to_le32(TXDESC_SHORT_PREAMBLE);
6359 if (rate_flag & IEEE80211_TX_RC_SHORT_GI ||
6360 (ieee80211_is_data_qos(hdr->frame_control) &&
6361 sta && sta->ht_cap.cap &
6362 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))) {
6363 tx_desc->txdw5 |= cpu_to_le32(TXDESC_SHORT_GI);
6364 }
6365 if (ieee80211_is_mgmt(hdr->frame_control)) {
6366 tx_desc->txdw5 = cpu_to_le32(tx_rate->hw_value);
6367 tx_desc->txdw4 |= cpu_to_le32(TXDESC_USE_DRIVER_RATE);
6368 tx_desc->txdw5 |= cpu_to_le32(6 << TXDESC_RETRY_LIMIT_SHIFT);
6369 tx_desc->txdw5 |= cpu_to_le32(TXDESC_RETRY_LIMIT_ENABLE);
6370 }
6371
6372 if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS) {
6373 /* Use RTS rate 24M - does the mac80211 tell us which to use? */
6374 tx_desc->txdw4 |= cpu_to_le32(DESC_RATE_24M);
6375 tx_desc->txdw4 |= cpu_to_le32(TXDESC_RTS_CTS_ENABLE);
6376 tx_desc->txdw4 |= cpu_to_le32(TXDESC_HW_RTS_ENABLE);
6377 }
6378
6379 rtl8xxxu_calc_tx_desc_csum(tx_desc);
6380
6381 usb_fill_bulk_urb(&tx_urb->urb, priv->udev, priv->pipe_out[queue],
6382 skb->data, skb->len, rtl8xxxu_tx_complete, skb);
6383
6384 usb_anchor_urb(&tx_urb->urb, &priv->tx_anchor);
6385 ret = usb_submit_urb(&tx_urb->urb, GFP_ATOMIC);
6386 if (ret) {
6387 usb_unanchor_urb(&tx_urb->urb);
6388 rtl8xxxu_free_tx_urb(priv, tx_urb);
6389 goto error;
6390 }
6391 return;
6392error:
6393 dev_kfree_skb(skb);
6394}
6395
6396static void rtl8xxxu_rx_parse_phystats(struct rtl8xxxu_priv *priv,
6397 struct ieee80211_rx_status *rx_status,
6398 struct rtl8xxxu_rx_desc *rx_desc,
6399 struct rtl8723au_phy_stats *phy_stats)
6400{
6401 if (phy_stats->sgi_en)
6402 rx_status->flag |= RX_FLAG_SHORT_GI;
6403
6404 if (rx_desc->rxmcs < DESC_RATE_6M) {
6405 /*
6406 * Handle PHY stats for CCK rates
6407 */
6408 u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a;
6409
6410 switch (cck_agc_rpt & 0xc0) {
6411 case 0xc0:
6412 rx_status->signal = -46 - (cck_agc_rpt & 0x3e);
6413 break;
6414 case 0x80:
6415 rx_status->signal = -26 - (cck_agc_rpt & 0x3e);
6416 break;
6417 case 0x40:
6418 rx_status->signal = -12 - (cck_agc_rpt & 0x3e);
6419 break;
6420 case 0x00:
6421 rx_status->signal = 16 - (cck_agc_rpt & 0x3e);
6422 break;
6423 }
6424 } else {
6425 rx_status->signal =
6426 (phy_stats->cck_sig_qual_ofdm_pwdb_all >> 1) - 110;
6427 }
6428}
6429
6430static void rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv *priv)
6431{
6432 struct rtl8xxxu_rx_urb *rx_urb, *tmp;
6433 unsigned long flags;
6434
6435 spin_lock_irqsave(&priv->rx_urb_lock, flags);
6436
6437 list_for_each_entry_safe(rx_urb, tmp,
6438 &priv->rx_urb_pending_list, list) {
6439 list_del(&rx_urb->list);
6440 priv->rx_urb_pending_count--;
6441 usb_free_urb(&rx_urb->urb);
6442 }
6443
6444 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
6445}
6446
6447static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv *priv,
6448 struct rtl8xxxu_rx_urb *rx_urb)
6449{
6450 struct sk_buff *skb;
6451 unsigned long flags;
6452 int pending = 0;
6453
6454 spin_lock_irqsave(&priv->rx_urb_lock, flags);
6455
6456 if (!priv->shutdown) {
6457 list_add_tail(&rx_urb->list, &priv->rx_urb_pending_list);
6458 priv->rx_urb_pending_count++;
6459 pending = priv->rx_urb_pending_count;
6460 } else {
6461 skb = (struct sk_buff *)rx_urb->urb.context;
6462 dev_kfree_skb(skb);
6463 usb_free_urb(&rx_urb->urb);
6464 }
6465
6466 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
6467
6468 if (pending > RTL8XXXU_RX_URB_PENDING_WATER)
6469 schedule_work(&priv->rx_urb_wq);
6470}
6471
6472static void rtl8xxxu_rx_urb_work(struct work_struct *work)
6473{
6474 struct rtl8xxxu_priv *priv;
6475 struct rtl8xxxu_rx_urb *rx_urb, *tmp;
6476 struct list_head local;
6477 struct sk_buff *skb;
6478 unsigned long flags;
6479 int ret;
6480
6481 priv = container_of(work, struct rtl8xxxu_priv, rx_urb_wq);
6482 INIT_LIST_HEAD(&local);
6483
6484 spin_lock_irqsave(&priv->rx_urb_lock, flags);
6485
6486 list_splice_init(&priv->rx_urb_pending_list, &local);
6487 priv->rx_urb_pending_count = 0;
6488
6489 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
6490
6491 list_for_each_entry_safe(rx_urb, tmp, &local, list) {
6492 list_del_init(&rx_urb->list);
6493 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
6494 /*
6495 * If out of memory or temporary error, put it back on the
6496 * queue and try again. Otherwise the device is dead/gone
6497 * and we should drop it.
6498 */
6499 switch (ret) {
6500 case 0:
6501 break;
6502 case -ENOMEM:
6503 case -EAGAIN:
6504 rtl8xxxu_queue_rx_urb(priv, rx_urb);
6505 break;
6506 default:
6507 pr_info("failed to requeue urb %i\n", ret);
6508 skb = (struct sk_buff *)rx_urb->urb.context;
6509 dev_kfree_skb(skb);
6510 usb_free_urb(&rx_urb->urb);
6511 }
6512 }
6513}
6514
6515static void rtl8xxxu_rx_complete(struct urb *urb)
6516{
6517 struct rtl8xxxu_rx_urb *rx_urb =
6518 container_of(urb, struct rtl8xxxu_rx_urb, urb);
6519 struct ieee80211_hw *hw = rx_urb->hw;
6520 struct rtl8xxxu_priv *priv = hw->priv;
6521 struct sk_buff *skb = (struct sk_buff *)urb->context;
6522 struct rtl8xxxu_rx_desc *rx_desc = (struct rtl8xxxu_rx_desc *)skb->data;
6523 struct rtl8723au_phy_stats *phy_stats;
6524 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb);
26f1fad2
JS		 6525 struct device *dev = &priv->udev->dev;
6526 __le32 *_rx_desc_le = (__le32 *)skb->data;
6527 u32 *_rx_desc = (u32 *)skb->data;
a9ffa615 6528 int drvinfo_sz, desc_shift, i;
26f1fad2
JS		 6529
6530 for (i = 0; i < (sizeof(struct rtl8xxxu_rx_desc) / sizeof(u32)); i++)
6531 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]);
6532
26f1fad2
JS		 6533 drvinfo_sz = rx_desc->drvinfo_sz * 8;
6534 desc_shift = rx_desc->shift;
6535 skb_put(skb, urb->actual_length);
6536
6537 if (urb->status == 0) {
6538 skb_pull(skb, sizeof(struct rtl8xxxu_rx_desc));
6539 phy_stats = (struct rtl8723au_phy_stats *)skb->data;
6540
6541 skb_pull(skb, drvinfo_sz + desc_shift);
6542
26f1fad2
JS		 6543 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
6544
6545 if (rx_desc->phy_stats)
6546 rtl8xxxu_rx_parse_phystats(priv, rx_status,
6547 rx_desc, phy_stats);
6548
6549 rx_status->freq = hw->conf.chandef.chan->center_freq;
6550 rx_status->band = hw->conf.chandef.chan->band;
6551
6552 rx_status->mactime = le32_to_cpu(rx_desc->tsfl);
6553 rx_status->flag |= RX_FLAG_MACTIME_START;
6554
6555 if (!rx_desc->swdec)
6556 rx_status->flag |= RX_FLAG_DECRYPTED;
6557 if (rx_desc->crc32)
6558 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
6559 if (rx_desc->bw)
6560 rx_status->flag |= RX_FLAG_40MHZ;
6561
6562 if (rx_desc->rxht) {
6563 rx_status->flag |= RX_FLAG_HT;
6564 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
6565 } else {
6566 rx_status->rate_idx = rx_desc->rxmcs;
6567 }
6568
6569 ieee80211_rx_irqsafe(hw, skb);
6570 skb = NULL;
6571 rx_urb->urb.context = NULL;
6572 rtl8xxxu_queue_rx_urb(priv, rx_urb);
6573 } else {
6574 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
6575 goto cleanup;
6576 }
6577 return;
6578
6579cleanup:
6580 usb_free_urb(urb);
6581 dev_kfree_skb(skb);
6582 return;
6583}
6584
6585static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
6586 struct rtl8xxxu_rx_urb *rx_urb)
6587{
6588 struct sk_buff *skb;
6589 int skb_size;
6590 int ret;
6591
6592 skb_size = sizeof(struct rtl8xxxu_rx_desc) + RTL_RX_BUFFER_SIZE;
6593 skb = __netdev_alloc_skb(NULL, skb_size, GFP_KERNEL);
6594 if (!skb)
6595 return -ENOMEM;
6596
6597 memset(skb->data, 0, sizeof(struct rtl8xxxu_rx_desc));
6598 usb_fill_bulk_urb(&rx_urb->urb, priv->udev, priv->pipe_in, skb->data,
6599 skb_size, rtl8xxxu_rx_complete, skb);
6600 usb_anchor_urb(&rx_urb->urb, &priv->rx_anchor);
6601 ret = usb_submit_urb(&rx_urb->urb, GFP_ATOMIC);
6602 if (ret)
6603 usb_unanchor_urb(&rx_urb->urb);
6604 return ret;
6605}
6606
6607static void rtl8xxxu_int_complete(struct urb *urb)
6608{
6609 struct rtl8xxxu_priv *priv = (struct rtl8xxxu_priv *)urb->context;
6610 struct device *dev = &priv->udev->dev;
6611 int ret;
6612
6613 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
6614 if (urb->status == 0) {
6615 usb_anchor_urb(urb, &priv->int_anchor);
6616 ret = usb_submit_urb(urb, GFP_ATOMIC);
6617 if (ret)
6618 usb_unanchor_urb(urb);
6619 } else {
6620 dev_info(dev, "%s: Error %i\n", __func__, urb->status);
6621 }
6622}
6623
6624
6625static int rtl8xxxu_submit_int_urb(struct ieee80211_hw *hw)
6626{
6627 struct rtl8xxxu_priv *priv = hw->priv;
6628 struct urb *urb;
6629 u32 val32;
6630 int ret;
6631
6632 urb = usb_alloc_urb(0, GFP_KERNEL);
6633 if (!urb)
6634 return -ENOMEM;
6635
6636 usb_fill_int_urb(urb, priv->udev, priv->pipe_interrupt,
6637 priv->int_buf, USB_INTR_CONTENT_LENGTH,
6638 rtl8xxxu_int_complete, priv, 1);
6639 usb_anchor_urb(urb, &priv->int_anchor);
6640 ret = usb_submit_urb(urb, GFP_KERNEL);
6641 if (ret) {
6642 usb_unanchor_urb(urb);
6643 goto error;
6644 }
6645
6646 val32 = rtl8xxxu_read32(priv, REG_USB_HIMR);
6647 val32 |= USB_HIMR_CPWM;
6648 rtl8xxxu_write32(priv, REG_USB_HIMR, val32);
6649
6650error:
6651 return ret;
6652}
6653
6654static int rtl8xxxu_add_interface(struct ieee80211_hw *hw,
6655 struct ieee80211_vif *vif)
6656{
6657 struct rtl8xxxu_priv *priv = hw->priv;
6658 int ret;
6659 u8 val8;
6660
6661 switch (vif->type) {
6662 case NL80211_IFTYPE_STATION:
6663 rtl8723a_stop_tx_beacon(priv);
6664
6665 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
6666 val8 |= BEACON_ATIM | BEACON_FUNCTION_ENABLE |
6667 BEACON_DISABLE_TSF_UPDATE;
6668 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
6669 ret = 0;
6670 break;
6671 default:
6672 ret = -EOPNOTSUPP;
6673 }
6674
6675 rtl8xxxu_set_linktype(priv, vif->type);
6676
6677 return ret;
6678}
6679
6680static void rtl8xxxu_remove_interface(struct ieee80211_hw *hw,
6681 struct ieee80211_vif *vif)
6682{
6683 struct rtl8xxxu_priv *priv = hw->priv;
6684
6685 dev_dbg(&priv->udev->dev, "%s\n", __func__);
6686}
6687
6688static int rtl8xxxu_config(struct ieee80211_hw *hw, u32 changed)
6689{
6690 struct rtl8xxxu_priv *priv = hw->priv;
6691 struct device *dev = &priv->udev->dev;
6692 u16 val16;
6693 int ret = 0, channel;
6694 bool ht40;
6695
6696 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
6697 dev_info(dev,
6698 "%s: channel: %i (changed %08x chandef.width %02x)\n",
6699 __func__, hw->conf.chandef.chan->hw_value,
6700 changed, hw->conf.chandef.width);
6701
6702 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) {
6703 val16 = ((hw->conf.long_frame_max_tx_count <<
6704 RETRY_LIMIT_LONG_SHIFT) & RETRY_LIMIT_LONG_MASK) |
6705 ((hw->conf.short_frame_max_tx_count <<
6706 RETRY_LIMIT_SHORT_SHIFT) & RETRY_LIMIT_SHORT_MASK);
6707 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
6708 }
6709
6710 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
6711 switch (hw->conf.chandef.width) {
6712 case NL80211_CHAN_WIDTH_20_NOHT:
6713 case NL80211_CHAN_WIDTH_20:
6714 ht40 = false;
6715 break;
6716 case NL80211_CHAN_WIDTH_40:
6717 ht40 = true;
6718 break;
6719 default:
6720 ret = -ENOTSUPP;
6721 goto exit;
6722 }
6723
6724 channel = hw->conf.chandef.chan->hw_value;
6725
6726 rtl8723a_set_tx_power(priv, channel, ht40);
6727
6728 rtl8723au_config_channel(hw);
6729 }
6730
6731exit:
6732 return ret;
6733}
6734
6735static int rtl8xxxu_conf_tx(struct ieee80211_hw *hw,
6736 struct ieee80211_vif *vif, u16 queue,
6737 const struct ieee80211_tx_queue_params *param)
6738{
6739 struct rtl8xxxu_priv *priv = hw->priv;
6740 struct device *dev = &priv->udev->dev;
6741 u32 val32;
6742 u8 aifs, acm_ctrl, acm_bit;
6743
6744 aifs = param->aifs;
6745
6746 val32 = aifs |
6747 fls(param->cw_min) << EDCA_PARAM_ECW_MIN_SHIFT |
6748 fls(param->cw_max) << EDCA_PARAM_ECW_MAX_SHIFT |
6749 (u32)param->txop << EDCA_PARAM_TXOP_SHIFT;
6750
6751 acm_ctrl = rtl8xxxu_read8(priv, REG_ACM_HW_CTRL);
6752 dev_dbg(dev,
6753 "%s: IEEE80211 queue %02x val %08x, acm %i, acm_ctrl %02x\n",
6754 __func__, queue, val32, param->acm, acm_ctrl);
6755
6756 switch (queue) {
6757 case IEEE80211_AC_VO:
6758 acm_bit = ACM_HW_CTRL_VO;
6759 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, val32);
6760 break;
6761 case IEEE80211_AC_VI:
6762 acm_bit = ACM_HW_CTRL_VI;
6763 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, val32);
6764 break;
6765 case IEEE80211_AC_BE:
6766 acm_bit = ACM_HW_CTRL_BE;
6767 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, val32);
6768 break;
6769 case IEEE80211_AC_BK:
6770 acm_bit = ACM_HW_CTRL_BK;
6771 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, val32);
6772 break;
6773 default:
6774 acm_bit = 0;
6775 break;
6776 }
6777
6778 if (param->acm)
6779 acm_ctrl |= acm_bit;
6780 else
6781 acm_ctrl &= ~acm_bit;
6782 rtl8xxxu_write8(priv, REG_ACM_HW_CTRL, acm_ctrl);
6783
6784 return 0;
6785}
6786
6787static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw,
6788 unsigned int changed_flags,
6789 unsigned int *total_flags, u64 multicast)
6790{
6791 struct rtl8xxxu_priv *priv = hw->priv;
3bed4bfa 6792 u32 rcr = rtl8xxxu_read32(priv, REG_RCR);
26f1fad2
JS		 6793
6794 dev_dbg(&priv->udev->dev, "%s: changed_flags %08x, total_flags %08x\n",
6795 __func__, changed_flags, *total_flags);
6796
3bed4bfa
BR		 6797 /*
6798 * FIF_ALLMULTI ignored as all multicast frames are accepted (REG_MAR)
6799 */
6800
6801 if (*total_flags & FIF_FCSFAIL)
6802 rcr |= RCR_ACCEPT_CRC32;
6803 else
6804 rcr &= ~RCR_ACCEPT_CRC32;
6805
6806 /*
6807 * FIF_PLCPFAIL not supported?
6808 */
6809
6810 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
6811 rcr &= ~RCR_CHECK_BSSID_BEACON;
6812 else
6813 rcr |= RCR_CHECK_BSSID_BEACON;
6814
6815 if (*total_flags & FIF_CONTROL)
6816 rcr |= RCR_ACCEPT_CTRL_FRAME;
6817 else
6818 rcr &= ~RCR_ACCEPT_CTRL_FRAME;
6819
6820 if (*total_flags & FIF_OTHER_BSS) {
6821 rcr |= RCR_ACCEPT_AP;
6822 rcr &= ~RCR_CHECK_BSSID_MATCH;
6823 } else {
6824 rcr &= ~RCR_ACCEPT_AP;
6825 rcr |= RCR_CHECK_BSSID_MATCH;
6826 }
6827
6828 if (*total_flags & FIF_PSPOLL)
6829 rcr |= RCR_ACCEPT_PM;
6830 else
6831 rcr &= ~RCR_ACCEPT_PM;
6832
6833 /*
6834 * FIF_PROBE_REQ ignored as probe requests always seem to be accepted
6835 */
6836
6837 rtl8xxxu_write32(priv, REG_RCR, rcr);
6838
755bda11
JS		 6839 *total_flags &= (FIF_ALLMULTI | FIF_FCSFAIL | FIF_BCN_PRBRESP_PROMISC |
6840 FIF_CONTROL | FIF_OTHER_BSS | FIF_PSPOLL |
6841 FIF_PROBE_REQ);
26f1fad2
JS		 6842}
6843
6844static int rtl8xxxu_set_rts_threshold(struct ieee80211_hw *hw, u32 rts)
6845{
6846 if (rts > 2347)
6847 return -EINVAL;
6848
6849 return 0;
6850}
6851
6852static int rtl8xxxu_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
6853 struct ieee80211_vif *vif,
6854 struct ieee80211_sta *sta,
6855 struct ieee80211_key_conf *key)
6856{
6857 struct rtl8xxxu_priv *priv = hw->priv;
6858 struct device *dev = &priv->udev->dev;
6859 u8 mac_addr[ETH_ALEN];
6860 u8 val8;
6861 u16 val16;
6862 u32 val32;
6863 int retval = -EOPNOTSUPP;
6864
6865 dev_dbg(dev, "%s: cmd %02x, cipher %08x, index %i\n",
6866 __func__, cmd, key->cipher, key->keyidx);
6867
6868 if (vif->type != NL80211_IFTYPE_STATION)
6869 return -EOPNOTSUPP;
6870
6871 if (key->keyidx > 3)
6872 return -EOPNOTSUPP;
6873
6874 switch (key->cipher) {
6875 case WLAN_CIPHER_SUITE_WEP40:
6876 case WLAN_CIPHER_SUITE_WEP104:
6877
6878 break;
6879 case WLAN_CIPHER_SUITE_CCMP:
6880 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
6881 break;
6882 case WLAN_CIPHER_SUITE_TKIP:
6883 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
6884 default:
6885 return -EOPNOTSUPP;
6886 }
6887
6888 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
6889 dev_dbg(dev, "%s: pairwise key\n", __func__);
6890 ether_addr_copy(mac_addr, sta->addr);
6891 } else {
6892 dev_dbg(dev, "%s: group key\n", __func__);
6893 eth_broadcast_addr(mac_addr);
6894 }
6895
6896 val16 = rtl8xxxu_read16(priv, REG_CR);
6897 val16 |= CR_SECURITY_ENABLE;
6898 rtl8xxxu_write16(priv, REG_CR, val16);
6899
6900 val8 = SEC_CFG_TX_SEC_ENABLE | SEC_CFG_TXBC_USE_DEFKEY |
6901 SEC_CFG_RX_SEC_ENABLE | SEC_CFG_RXBC_USE_DEFKEY;
6902 val8 |= SEC_CFG_TX_USE_DEFKEY | SEC_CFG_RX_USE_DEFKEY;
6903 rtl8xxxu_write8(priv, REG_SECURITY_CFG, val8);
6904
6905 switch (cmd) {
6906 case SET_KEY:
6907 key->hw_key_idx = key->keyidx;
6908 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
6909 rtl8xxxu_cam_write(priv, key, mac_addr);
6910 retval = 0;
6911 break;
6912 case DISABLE_KEY:
6913 rtl8xxxu_write32(priv, REG_CAM_WRITE, 0x00000000);
6914 val32 = CAM_CMD_POLLING | CAM_CMD_WRITE |
6915 key->keyidx << CAM_CMD_KEY_SHIFT;
6916 rtl8xxxu_write32(priv, REG_CAM_CMD, val32);
6917 retval = 0;
6918 break;
6919 default:
6920 dev_warn(dev, "%s: Unsupported command %02x\n", __func__, cmd);
6921 }
6922
6923 return retval;
6924}
6925
6926static int
6927rtl8xxxu_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
50ea05ef 6928 struct ieee80211_ampdu_params *params)
26f1fad2
JS		 6929{
6930 struct rtl8xxxu_priv *priv = hw->priv;
6931 struct device *dev = &priv->udev->dev;
6932 u8 ampdu_factor, ampdu_density;
50ea05ef
SS		 6933 struct ieee80211_sta *sta = params->sta;
6934 enum ieee80211_ampdu_mlme_action action = params->action;
26f1fad2
JS		 6935
6936 switch (action) {
6937 case IEEE80211_AMPDU_TX_START:
6938 dev_info(dev, "%s: IEEE80211_AMPDU_TX_START\n", __func__);
6939 ampdu_factor = sta->ht_cap.ampdu_factor;
6940 ampdu_density = sta->ht_cap.ampdu_density;
6941 rtl8xxxu_set_ampdu_factor(priv, ampdu_factor);
6942 rtl8xxxu_set_ampdu_min_space(priv, ampdu_density);
6943 dev_dbg(dev,
6944 "Changed HT: ampdu_factor %02x, ampdu_density %02x\n",
6945 ampdu_factor, ampdu_density);
6946 break;
6947 case IEEE80211_AMPDU_TX_STOP_FLUSH:
6948 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH\n", __func__);
6949 rtl8xxxu_set_ampdu_factor(priv, 0);
6950 rtl8xxxu_set_ampdu_min_space(priv, 0);
6951 break;
6952 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
6953 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH_CONT\n",
6954 __func__);
6955 rtl8xxxu_set_ampdu_factor(priv, 0);
6956 rtl8xxxu_set_ampdu_min_space(priv, 0);
6957 break;
6958 case IEEE80211_AMPDU_RX_START:
6959 dev_info(dev, "%s: IEEE80211_AMPDU_RX_START\n", __func__);
6960 break;
6961 case IEEE80211_AMPDU_RX_STOP:
6962 dev_info(dev, "%s: IEEE80211_AMPDU_RX_STOP\n", __func__);
6963 break;
6964 default:
6965 break;
6966 }
6967 return 0;
6968}
6969
6970static int rtl8xxxu_start(struct ieee80211_hw *hw)
6971{
6972 struct rtl8xxxu_priv *priv = hw->priv;
6973 struct rtl8xxxu_rx_urb *rx_urb;
6974 struct rtl8xxxu_tx_urb *tx_urb;
6975 unsigned long flags;
6976 int ret, i;
6977
6978 ret = 0;
6979
6980 init_usb_anchor(&priv->rx_anchor);
6981 init_usb_anchor(&priv->tx_anchor);
6982 init_usb_anchor(&priv->int_anchor);
6983
6984 rtl8723a_enable_rf(priv);
0e28b975
JS		 6985 if (priv->usb_interrupts) {
6986 ret = rtl8xxxu_submit_int_urb(hw);
6987 if (ret)
6988 goto exit;
6989 }
26f1fad2
JS		 6990
6991 for (i = 0; i < RTL8XXXU_TX_URBS; i++) {
6992 tx_urb = kmalloc(sizeof(struct rtl8xxxu_tx_urb), GFP_KERNEL);
6993 if (!tx_urb) {
6994 if (!i)
6995 ret = -ENOMEM;
6996
6997 goto error_out;
6998 }
6999 usb_init_urb(&tx_urb->urb);
7000 INIT_LIST_HEAD(&tx_urb->list);
7001 tx_urb->hw = hw;
7002 list_add(&tx_urb->list, &priv->tx_urb_free_list);
7003 priv->tx_urb_free_count++;
7004 }
7005
7006 priv->tx_stopped = false;
7007
7008 spin_lock_irqsave(&priv->rx_urb_lock, flags);
7009 priv->shutdown = false;
7010 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
7011
7012 for (i = 0; i < RTL8XXXU_RX_URBS; i++) {
7013 rx_urb = kmalloc(sizeof(struct rtl8xxxu_rx_urb), GFP_KERNEL);
7014 if (!rx_urb) {
7015 if (!i)
7016 ret = -ENOMEM;
7017
7018 goto error_out;
7019 }
7020 usb_init_urb(&rx_urb->urb);
7021 INIT_LIST_HEAD(&rx_urb->list);
7022 rx_urb->hw = hw;
7023
7024 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
7025 }
7026exit:
7027 /*
c85ea115 7028 * Accept all data and mgmt frames
26f1fad2 7029 */
c85ea115 7030 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff);
26f1fad2
JS		 7031 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff);
7032
7033 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, 0x6954341e);
7034
7035 return ret;
7036
7037error_out:
7038 rtl8xxxu_free_tx_resources(priv);
7039 /*
7040 * Disable all data and mgmt frames
7041 */
7042 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
7043 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
7044
7045 return ret;
7046}
7047
7048static void rtl8xxxu_stop(struct ieee80211_hw *hw)
7049{
7050 struct rtl8xxxu_priv *priv = hw->priv;
7051 unsigned long flags;
7052
7053 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
7054
7055 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
7056 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
7057
7058 spin_lock_irqsave(&priv->rx_urb_lock, flags);
7059 priv->shutdown = true;
7060 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
7061
7062 usb_kill_anchored_urbs(&priv->rx_anchor);
7063 usb_kill_anchored_urbs(&priv->tx_anchor);
0e28b975
JS		 7064 if (priv->usb_interrupts)
7065 usb_kill_anchored_urbs(&priv->int_anchor);
26f1fad2
JS		 7066
7067 rtl8723a_disable_rf(priv);
7068
7069 /*
7070 * Disable interrupts
7071 */
0e28b975
JS		 7072 if (priv->usb_interrupts)
7073 rtl8xxxu_write32(priv, REG_USB_HIMR, 0);
26f1fad2
JS		 7074
7075 rtl8xxxu_free_rx_resources(priv);
7076 rtl8xxxu_free_tx_resources(priv);
7077}
7078
7079static const struct ieee80211_ops rtl8xxxu_ops = {
7080 .tx = rtl8xxxu_tx,
7081 .add_interface = rtl8xxxu_add_interface,
7082 .remove_interface = rtl8xxxu_remove_interface,
7083 .config = rtl8xxxu_config,
7084 .conf_tx = rtl8xxxu_conf_tx,
7085 .bss_info_changed = rtl8xxxu_bss_info_changed,
7086 .configure_filter = rtl8xxxu_configure_filter,
7087 .set_rts_threshold = rtl8xxxu_set_rts_threshold,
7088 .start = rtl8xxxu_start,
7089 .stop = rtl8xxxu_stop,
7090 .sw_scan_start = rtl8xxxu_sw_scan_start,
7091 .sw_scan_complete = rtl8xxxu_sw_scan_complete,
7092 .set_key = rtl8xxxu_set_key,
7093 .ampdu_action = rtl8xxxu_ampdu_action,
7094};
7095
7096static int rtl8xxxu_parse_usb(struct rtl8xxxu_priv *priv,
7097 struct usb_interface *interface)
7098{
7099 struct usb_interface_descriptor *interface_desc;
7100 struct usb_host_interface *host_interface;
7101 struct usb_endpoint_descriptor *endpoint;
7102 struct device *dev = &priv->udev->dev;
7103 int i, j = 0, endpoints;
7104 u8 dir, xtype, num;
7105 int ret = 0;
7106
7107 host_interface = &interface->altsetting[0];
7108 interface_desc = &host_interface->desc;
7109 endpoints = interface_desc->bNumEndpoints;
7110
7111 for (i = 0; i < endpoints; i++) {
7112 endpoint = &host_interface->endpoint[i].desc;
7113
7114 dir = endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK;
7115 num = usb_endpoint_num(endpoint);
7116 xtype = usb_endpoint_type(endpoint);
7117 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
7118 dev_dbg(dev,
7119 "%s: endpoint: dir %02x, # %02x, type %02x\n",
7120 __func__, dir, num, xtype);
7121 if (usb_endpoint_dir_in(endpoint) &&
7122 usb_endpoint_xfer_bulk(endpoint)) {
7123 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
7124 dev_dbg(dev, "%s: in endpoint num %i\n",
7125 __func__, num);
7126
7127 if (priv->pipe_in) {
7128 dev_warn(dev,
7129 "%s: Too many IN pipes\n", __func__);
7130 ret = -EINVAL;
7131 goto exit;
7132 }
7133
7134 priv->pipe_in = usb_rcvbulkpipe(priv->udev, num);
7135 }
7136
7137 if (usb_endpoint_dir_in(endpoint) &&
7138 usb_endpoint_xfer_int(endpoint)) {
7139 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
7140 dev_dbg(dev, "%s: interrupt endpoint num %i\n",
7141 __func__, num);
7142
7143 if (priv->pipe_interrupt) {
7144 dev_warn(dev, "%s: Too many INTERRUPT pipes\n",
7145 __func__);
7146 ret = -EINVAL;
7147 goto exit;
7148 }
7149
7150 priv->pipe_interrupt = usb_rcvintpipe(priv->udev, num);
7151 }
7152
7153 if (usb_endpoint_dir_out(endpoint) &&
7154 usb_endpoint_xfer_bulk(endpoint)) {
7155 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
7156 dev_dbg(dev, "%s: out endpoint num %i\n",
7157 __func__, num);
7158 if (j >= RTL8XXXU_OUT_ENDPOINTS) {
7159 dev_warn(dev,
7160 "%s: Too many OUT pipes\n", __func__);
7161 ret = -EINVAL;
7162 goto exit;
7163 }
7164 priv->out_ep[j++] = num;
7165 }
7166 }
7167exit:
7168 priv->nr_out_eps = j;
7169 return ret;
7170}
7171
7172static int rtl8xxxu_probe(struct usb_interface *interface,
7173 const struct usb_device_id *id)
7174{
7175 struct rtl8xxxu_priv *priv;
7176 struct ieee80211_hw *hw;
7177 struct usb_device *udev;
7178 struct ieee80211_supported_band *sband;
7179 int ret = 0;
7180 int untested = 1;
7181
7182 udev = usb_get_dev(interface_to_usbdev(interface));
7183
7184 switch (id->idVendor) {
7185 case USB_VENDOR_ID_REALTEK:
7186 switch(id->idProduct) {
7187 case 0x1724:
7188 case 0x8176:
7189 case 0x8178:
7190 case 0x817f:
7191 untested = 0;
7192 break;
7193 }
7194 break;
7195 case 0x7392:
7196 if (id->idProduct == 0x7811)
7197 untested = 0;
7198 break;
7199 default:
7200 break;
7201 }
7202
7203 if (untested) {
eaa4d14c 7204 rtl8xxxu_debug |= RTL8XXXU_DEBUG_EFUSE;
26f1fad2
JS		 7205 dev_info(&udev->dev,
7206 "This Realtek USB WiFi dongle (0x%04x:0x%04x) is untested!\n",
7207 id->idVendor, id->idProduct);
7208 dev_info(&udev->dev,
7209 "Please report results to Jes.Sorensen@gmail.com\n");
7210 }
7211
7212 hw = ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv), &rtl8xxxu_ops);
7213 if (!hw) {
7214 ret = -ENOMEM;
7215 goto exit;
7216 }
7217
7218 priv = hw->priv;
7219 priv->hw = hw;
7220 priv->udev = udev;
7221 priv->fops = (struct rtl8xxxu_fileops *)id->driver_info;
7222 mutex_init(&priv->usb_buf_mutex);
7223 mutex_init(&priv->h2c_mutex);
7224 INIT_LIST_HEAD(&priv->tx_urb_free_list);
7225 spin_lock_init(&priv->tx_urb_lock);
7226 INIT_LIST_HEAD(&priv->rx_urb_pending_list);
7227 spin_lock_init(&priv->rx_urb_lock);
7228 INIT_WORK(&priv->rx_urb_wq, rtl8xxxu_rx_urb_work);
7229
7230 usb_set_intfdata(interface, hw);
7231
7232 ret = rtl8xxxu_parse_usb(priv, interface);
7233 if (ret)
7234 goto exit;
7235
7236 ret = rtl8xxxu_identify_chip(priv);
7237 if (ret) {
7238 dev_err(&udev->dev, "Fatal - failed to identify chip\n");
7239 goto exit;
7240 }
7241
7242 ret = rtl8xxxu_read_efuse(priv);
7243 if (ret) {
7244 dev_err(&udev->dev, "Fatal - failed to read EFuse\n");
7245 goto exit;
7246 }
7247
7248 ret = priv->fops->parse_efuse(priv);
7249 if (ret) {
7250 dev_err(&udev->dev, "Fatal - failed to parse EFuse\n");
7251 goto exit;
7252 }
7253
7254 rtl8xxxu_print_chipinfo(priv);
7255
7256 ret = priv->fops->load_firmware(priv);
7257 if (ret) {
7258 dev_err(&udev->dev, "Fatal - failed to load firmware\n");
7259 goto exit;
7260 }
7261
7262 ret = rtl8xxxu_init_device(hw);
7263
7264 hw->wiphy->max_scan_ssids = 1;
7265 hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
7266 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
7267 hw->queues = 4;
7268
7269 sband = &rtl8xxxu_supported_band;
7270 sband->ht_cap.ht_supported = true;
7271 sband->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
7272 sband->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
7273 sband->ht_cap.cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40;
7274 memset(&sband->ht_cap.mcs, 0, sizeof(sband->ht_cap.mcs));
7275 sband->ht_cap.mcs.rx_mask[0] = 0xff;
7276 sband->ht_cap.mcs.rx_mask[4] = 0x01;
7277 if (priv->rf_paths > 1) {
7278 sband->ht_cap.mcs.rx_mask[1] = 0xff;
7279 sband->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
7280 }
7281 sband->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
7282 /*
7283 * Some APs will negotiate HT20_40 in a noisy environment leading
7284 * to miserable performance. Rather than defaulting to this, only
7285 * enable it if explicitly requested at module load time.
7286 */
7287 if (rtl8xxxu_ht40_2g) {
7288 dev_info(&udev->dev, "Enabling HT_20_40 on the 2.4GHz band\n");
7289 sband->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
7290 }
7291 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
7292
7293 hw->wiphy->rts_threshold = 2347;
7294
7295 SET_IEEE80211_DEV(priv->hw, &interface->dev);
7296 SET_IEEE80211_PERM_ADDR(hw, priv->mac_addr);
7297
7298 hw->extra_tx_headroom = sizeof(struct rtl8xxxu_tx_desc);
7299 ieee80211_hw_set(hw, SIGNAL_DBM);
7300 /*
7301 * The firmware handles rate control
7302 */
7303 ieee80211_hw_set(hw, HAS_RATE_CONTROL);
7304 ieee80211_hw_set(hw, AMPDU_AGGREGATION);
7305
7306 ret = ieee80211_register_hw(priv->hw);
7307 if (ret) {
7308 dev_err(&udev->dev, "%s: Failed to register: %i\n",
7309 __func__, ret);
7310 goto exit;
7311 }
7312
7313exit:
7314 if (ret < 0)
7315 usb_put_dev(udev);
7316 return ret;
7317}
7318
7319static void rtl8xxxu_disconnect(struct usb_interface *interface)
7320{
7321 struct rtl8xxxu_priv *priv;
7322 struct ieee80211_hw *hw;
7323
7324 hw = usb_get_intfdata(interface);
7325 priv = hw->priv;
7326
7327 rtl8xxxu_disable_device(hw);
7328 usb_set_intfdata(interface, NULL);
7329
7330 dev_info(&priv->udev->dev, "disconnecting\n");
7331
7332 ieee80211_unregister_hw(hw);
7333
7334 kfree(priv->fw_data);
7335 mutex_destroy(&priv->usb_buf_mutex);
7336 mutex_destroy(&priv->h2c_mutex);
7337
7338 usb_put_dev(priv->udev);
7339 ieee80211_free_hw(hw);
7340}
7341
7342static struct rtl8xxxu_fileops rtl8723au_fops = {
7343 .parse_efuse = rtl8723au_parse_efuse,
7344 .load_firmware = rtl8723au_load_firmware,
7345 .power_on = rtl8723au_power_on,
74b99bed 7346 .llt_init = rtl8xxxu_init_llt_table,
e1547c53 7347 .phy_iq_calibrate = rtl8723au_phy_iq_calibrate,
26f1fad2 7348 .writeN_block_size = 1024,
ed35d094
JS		 7349 .mbox_ext_reg = REG_HMBOX_EXT_0,
7350 .mbox_ext_width = 2,
8634af5e
JS		 7351 .adda_1t_init = 0x0b1b25a0,
7352 .adda_1t_path_on = 0x0bdb25a0,
7353 .adda_2t_path_on_a = 0x04db25a4,
7354 .adda_2t_path_on_b = 0x0b1b25a4,
26f1fad2
JS		 7355};
7356
35a741fe 7357static struct rtl8xxxu_fileops rtl8723bu_fops = {
3c836d60 7358 .parse_efuse = rtl8723bu_parse_efuse,
35a741fe
JS		 7359 .load_firmware = rtl8723bu_load_firmware,
7360 .power_on = rtl8723au_power_on,
7361 .llt_init = rtl8xxxu_auto_llt_table,
f0d9f5e9 7362 .phy_init_antenna_selection = rtl8723bu_phy_init_antenna_selection,
e1547c53 7363 .phy_iq_calibrate = rtl8723bu_phy_iq_calibrate,
adfc0124 7364 .writeN_block_size = 1024,
ed35d094
JS		 7365 .mbox_ext_reg = REG_HMBOX_EXT0_8723B,
7366 .mbox_ext_width = 4,
0d698dec 7367 .has_s0s1 = 1,
8634af5e
JS		 7368 .adda_1t_init = 0x01c00014,
7369 .adda_1t_path_on = 0x01c00014,
7370 .adda_2t_path_on_a = 0x01c00014,
7371 .adda_2t_path_on_b = 0x01c00014,
35a741fe
JS		 7372};
7373
c0963772
KV		 7374#ifdef CONFIG_RTL8XXXU_UNTESTED
7375
26f1fad2
JS		 7376static struct rtl8xxxu_fileops rtl8192cu_fops = {
7377 .parse_efuse = rtl8192cu_parse_efuse,
7378 .load_firmware = rtl8192cu_load_firmware,
7379 .power_on = rtl8192cu_power_on,
74b99bed 7380 .llt_init = rtl8xxxu_init_llt_table,
e1547c53 7381 .phy_iq_calibrate = rtl8723au_phy_iq_calibrate,
26f1fad2 7382 .writeN_block_size = 128,
ed35d094
JS		 7383 .mbox_ext_reg = REG_HMBOX_EXT_0,
7384 .mbox_ext_width = 2,
8634af5e
JS		 7385 .adda_1t_init = 0x0b1b25a0,
7386 .adda_1t_path_on = 0x0bdb25a0,
7387 .adda_2t_path_on_a = 0x04db25a4,
7388 .adda_2t_path_on_b = 0x0b1b25a4,
26f1fad2
JS		 7389};
7390
c0963772
KV		 7391#endif
7392
3307d840
JS		 7393static struct rtl8xxxu_fileops rtl8192eu_fops = {
7394 .parse_efuse = rtl8192eu_parse_efuse,
7395 .load_firmware = rtl8192eu_load_firmware,
c05a9dbf 7396 .power_on = rtl8192eu_power_on,
74b99bed 7397 .llt_init = rtl8xxxu_auto_llt_table,
e1547c53 7398 .phy_iq_calibrate = rtl8723bu_phy_iq_calibrate,
c05a9dbf 7399 .writeN_block_size = 128,
ed35d094
JS		 7400 .mbox_ext_reg = REG_HMBOX_EXT0_8723B,
7401 .mbox_ext_width = 4,
0d698dec 7402 .has_s0s1 = 1,
8634af5e
JS		 7403 .adda_1t_init = 0x0fc01616,
7404 .adda_1t_path_on = 0x0fc01616,
7405 .adda_2t_path_on_a = 0x0fc01616,
7406 .adda_2t_path_on_b = 0x0fc01616,
3307d840
JS		 7407};
7408
26f1fad2
JS		 7409static struct usb_device_id dev_table[] = {
7410{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8724, 0xff, 0xff, 0xff),
7411 .driver_info = (unsigned long)&rtl8723au_fops},
7412{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1724, 0xff, 0xff, 0xff),
7413 .driver_info = (unsigned long)&rtl8723au_fops},
7414{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0724, 0xff, 0xff, 0xff),
7415 .driver_info = (unsigned long)&rtl8723au_fops},
3307d840
JS		 7416{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818b, 0xff, 0xff, 0xff),
7417 .driver_info = (unsigned long)&rtl8192eu_fops},
35a741fe
JS		 7418{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xb720, 0xff, 0xff, 0xff),
7419 .driver_info = (unsigned long)&rtl8723bu_fops},
033695bd
KV		 7420#ifdef CONFIG_RTL8XXXU_UNTESTED
7421/* Still supported by rtlwifi */
26f1fad2
JS		 7422{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8176, 0xff, 0xff, 0xff),
7423 .driver_info = (unsigned long)&rtl8192cu_fops},
7424{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8178, 0xff, 0xff, 0xff),
7425 .driver_info = (unsigned long)&rtl8192cu_fops},
7426{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817f, 0xff, 0xff, 0xff),
7427 .driver_info = (unsigned long)&rtl8192cu_fops},
7428/* Tested by Larry Finger */
7429{USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7811, 0xff, 0xff, 0xff),
7430 .driver_info = (unsigned long)&rtl8192cu_fops},
26f1fad2
JS		 7431/* Currently untested 8188 series devices */
7432{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8191, 0xff, 0xff, 0xff),
7433 .driver_info = (unsigned long)&rtl8192cu_fops},
7434{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8170, 0xff, 0xff, 0xff),
7435 .driver_info = (unsigned long)&rtl8192cu_fops},
7436{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8177, 0xff, 0xff, 0xff),
7437 .driver_info = (unsigned long)&rtl8192cu_fops},
7438{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817a, 0xff, 0xff, 0xff),
7439 .driver_info = (unsigned long)&rtl8192cu_fops},
7440{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817b, 0xff, 0xff, 0xff),
7441 .driver_info = (unsigned long)&rtl8192cu_fops},
7442{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817d, 0xff, 0xff, 0xff),
7443 .driver_info = (unsigned long)&rtl8192cu_fops},
7444{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817e, 0xff, 0xff, 0xff),
7445 .driver_info = (unsigned long)&rtl8192cu_fops},
7446{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818a, 0xff, 0xff, 0xff),
7447 .driver_info = (unsigned long)&rtl8192cu_fops},
7448{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff),
7449 .driver_info = (unsigned long)&rtl8192cu_fops},
7450{USB_DEVICE_AND_INTERFACE_INFO(0x1058, 0x0631, 0xff, 0xff, 0xff),
7451 .driver_info = (unsigned long)&rtl8192cu_fops},
7452{USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x094c, 0xff, 0xff, 0xff),
7453 .driver_info = (unsigned long)&rtl8192cu_fops},
7454{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1102, 0xff, 0xff, 0xff),
7455 .driver_info = (unsigned long)&rtl8192cu_fops},
7456{USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff),
7457 .driver_info = (unsigned long)&rtl8192cu_fops},
7458{USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8189, 0xff, 0xff, 0xff),
7459 .driver_info = (unsigned long)&rtl8192cu_fops},
7460{USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9041, 0xff, 0xff, 0xff),
7461 .driver_info = (unsigned long)&rtl8192cu_fops},
7462{USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ba, 0xff, 0xff, 0xff),
7463 .driver_info = (unsigned long)&rtl8192cu_fops},
7464{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1e1e, 0xff, 0xff, 0xff),
7465 .driver_info = (unsigned long)&rtl8192cu_fops},
7466{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x5088, 0xff, 0xff, 0xff),
7467 .driver_info = (unsigned long)&rtl8192cu_fops},
7468{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0052, 0xff, 0xff, 0xff),
7469 .driver_info = (unsigned long)&rtl8192cu_fops},
7470{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x005c, 0xff, 0xff, 0xff),
7471 .driver_info = (unsigned long)&rtl8192cu_fops},
7472{USB_DEVICE_AND_INTERFACE_INFO(0x0eb0, 0x9071, 0xff, 0xff, 0xff),
7473 .driver_info = (unsigned long)&rtl8192cu_fops},
7474{USB_DEVICE_AND_INTERFACE_INFO(0x103c, 0x1629, 0xff, 0xff, 0xff),
7475 .driver_info = (unsigned long)&rtl8192cu_fops},
7476{USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3357, 0xff, 0xff, 0xff),
7477 .driver_info = (unsigned long)&rtl8192cu_fops},
7478{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3308, 0xff, 0xff, 0xff),
7479 .driver_info = (unsigned long)&rtl8192cu_fops},
7480{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330b, 0xff, 0xff, 0xff),
7481 .driver_info = (unsigned long)&rtl8192cu_fops},
7482{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x4902, 0xff, 0xff, 0xff),
7483 .driver_info = (unsigned long)&rtl8192cu_fops},
7484{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2a, 0xff, 0xff, 0xff),
7485 .driver_info = (unsigned long)&rtl8192cu_fops},
7486{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2e, 0xff, 0xff, 0xff),
7487 .driver_info = (unsigned long)&rtl8192cu_fops},
7488{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xed17, 0xff, 0xff, 0xff),
7489 .driver_info = (unsigned long)&rtl8192cu_fops},
7490{USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x648b, 0xff, 0xff, 0xff),
7491 .driver_info = (unsigned long)&rtl8192cu_fops},
7492{USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0090, 0xff, 0xff, 0xff),
7493 .driver_info = (unsigned long)&rtl8192cu_fops},
7494{USB_DEVICE_AND_INTERFACE_INFO(0x4856, 0x0091, 0xff, 0xff, 0xff),
7495 .driver_info = (unsigned long)&rtl8192cu_fops},
7496{USB_DEVICE_AND_INTERFACE_INFO(0xcdab, 0x8010, 0xff, 0xff, 0xff),
7497 .driver_info = (unsigned long)&rtl8192cu_fops},
26f1fad2
JS		 7498{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff7, 0xff, 0xff, 0xff),
7499 .driver_info = (unsigned long)&rtl8192cu_fops},
7500{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff9, 0xff, 0xff, 0xff),
7501 .driver_info = (unsigned long)&rtl8192cu_fops},
7502{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffa, 0xff, 0xff, 0xff),
7503 .driver_info = (unsigned long)&rtl8192cu_fops},
7504{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff8, 0xff, 0xff, 0xff),
7505 .driver_info = (unsigned long)&rtl8192cu_fops},
7506{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffb, 0xff, 0xff, 0xff),
7507 .driver_info = (unsigned long)&rtl8192cu_fops},
7508{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffc, 0xff, 0xff, 0xff),
7509 .driver_info = (unsigned long)&rtl8192cu_fops},
7510{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x1201, 0xff, 0xff, 0xff),
7511 .driver_info = (unsigned long)&rtl8192cu_fops},
7512/* Currently untested 8192 series devices */
7513{USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x0950, 0xff, 0xff, 0xff),
7514 .driver_info = (unsigned long)&rtl8192cu_fops},
7515{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1004, 0xff, 0xff, 0xff),
7516 .driver_info = (unsigned long)&rtl8192cu_fops},
7517{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2102, 0xff, 0xff, 0xff),
7518 .driver_info = (unsigned long)&rtl8192cu_fops},
7519{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2103, 0xff, 0xff, 0xff),
7520 .driver_info = (unsigned long)&rtl8192cu_fops},
7521{USB_DEVICE_AND_INTERFACE_INFO(0x0586, 0x341f, 0xff, 0xff, 0xff),
7522 .driver_info = (unsigned long)&rtl8192cu_fops},
7523{USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe035, 0xff, 0xff, 0xff),
7524 .driver_info = (unsigned long)&rtl8192cu_fops},
7525{USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ab, 0xff, 0xff, 0xff),
7526 .driver_info = (unsigned long)&rtl8192cu_fops},
7527{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0061, 0xff, 0xff, 0xff),
7528 .driver_info = (unsigned long)&rtl8192cu_fops},
7529{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0070, 0xff, 0xff, 0xff),
7530 .driver_info = (unsigned long)&rtl8192cu_fops},
7531{USB_DEVICE_AND_INTERFACE_INFO(0x0789, 0x016d, 0xff, 0xff, 0xff),
7532 .driver_info = (unsigned long)&rtl8192cu_fops},
7533{USB_DEVICE_AND_INTERFACE_INFO(0x07aa, 0x0056, 0xff, 0xff, 0xff),
7534 .driver_info = (unsigned long)&rtl8192cu_fops},
7535{USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8178, 0xff, 0xff, 0xff),
7536 .driver_info = (unsigned long)&rtl8192cu_fops},
7537{USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9021, 0xff, 0xff, 0xff),
7538 .driver_info = (unsigned long)&rtl8192cu_fops},
7539{USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0xf001, 0xff, 0xff, 0xff),
7540 .driver_info = (unsigned long)&rtl8192cu_fops},
7541{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2e2e, 0xff, 0xff, 0xff),
7542 .driver_info = (unsigned long)&rtl8192cu_fops},
7543{USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0019, 0xff, 0xff, 0xff),
7544 .driver_info = (unsigned long)&rtl8192cu_fops},
7545{USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0020, 0xff, 0xff, 0xff),
7546 .driver_info = (unsigned long)&rtl8192cu_fops},
7547{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3307, 0xff, 0xff, 0xff),
7548 .driver_info = (unsigned long)&rtl8192cu_fops},
7549{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3309, 0xff, 0xff, 0xff),
7550 .driver_info = (unsigned long)&rtl8192cu_fops},
7551{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330a, 0xff, 0xff, 0xff),
7552 .driver_info = (unsigned long)&rtl8192cu_fops},
7553{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2b, 0xff, 0xff, 0xff),
7554 .driver_info = (unsigned long)&rtl8192cu_fops},
7555{USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x624d, 0xff, 0xff, 0xff),
7556 .driver_info = (unsigned long)&rtl8192cu_fops},
7557{USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0100, 0xff, 0xff, 0xff),
7558 .driver_info = (unsigned long)&rtl8192cu_fops},
7559{USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0091, 0xff, 0xff, 0xff),
7560 .driver_info = (unsigned long)&rtl8192cu_fops},
7561{USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7822, 0xff, 0xff, 0xff),
7562 .driver_info = (unsigned long)&rtl8192cu_fops},
7563#endif
7564{ }
7565};
7566
7567static struct usb_driver rtl8xxxu_driver = {
7568 .name = DRIVER_NAME,
7569 .probe = rtl8xxxu_probe,
7570 .disconnect = rtl8xxxu_disconnect,
7571 .id_table = dev_table,
7572 .disable_hub_initiated_lpm = 1,
7573};
7574
7575static int __init rtl8xxxu_module_init(void)
7576{
7577 int res;
7578
7579 res = usb_register(&rtl8xxxu_driver);
7580 if (res < 0)
7581 pr_err(DRIVER_NAME ": usb_register() failed (%i)\n", res);
7582
7583 return res;
7584}
7585
7586static void __exit rtl8xxxu_module_exit(void)
7587{
7588 usb_deregister(&rtl8xxxu_driver);
7589}
7590
7591
7592MODULE_DEVICE_TABLE(usb, dev_table);
7593
7594module_init(rtl8xxxu_module_init);
7595module_exit(rtl8xxxu_module_exit);
Linux kernel - Deliverables
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