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b54f78a8 | 1 | /* |
bc8a979e ID |
2 | Copyright (C) 2004 - 2010 Ivo van Doorn <IvDoorn@gmail.com> |
3 | Copyright (C) 2010 Willow Garage <http://www.willowgarage.com> | |
9c9a0d14 GW |
4 | Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com> |
5 | Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org> | |
6 | Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com> | |
7 | Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de> | |
8 | Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com> | |
9 | Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com> | |
10 | Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com> | |
b54f78a8 BZ |
11 | <http://rt2x00.serialmonkey.com> |
12 | ||
13 | This program is free software; you can redistribute it and/or modify | |
14 | it under the terms of the GNU General Public License as published by | |
15 | the Free Software Foundation; either version 2 of the License, or | |
16 | (at your option) any later version. | |
17 | ||
18 | This program is distributed in the hope that it will be useful, | |
19 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | GNU General Public License for more details. | |
22 | ||
23 | You should have received a copy of the GNU General Public License | |
24 | along with this program; if not, write to the | |
25 | Free Software Foundation, Inc., | |
26 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
27 | */ | |
28 | ||
29 | /* | |
30 | Module: rt2800 | |
31 | Abstract: Data structures and registers for the rt2800 modules. | |
32 | Supported chipsets: RT2800E, RT2800ED & RT2800U. | |
33 | */ | |
34 | ||
35 | #ifndef RT2800_H | |
36 | #define RT2800_H | |
37 | ||
38 | /* | |
39 | * RF chip defines. | |
40 | * | |
41 | * RF2820 2.4G 2T3R | |
42 | * RF2850 2.4G/5G 2T3R | |
43 | * RF2720 2.4G 1T2R | |
44 | * RF2750 2.4G/5G 1T2R | |
45 | * RF3020 2.4G 1T1R | |
46 | * RF2020 2.4G B/G | |
47 | * RF3021 2.4G 1T2R | |
48 | * RF3022 2.4G 2T2R | |
8d4ff3f3 RJH |
49 | * RF3052 2.4G/5G 2T2R |
50 | * RF2853 2.4G/5G 3T3R | |
51 | * RF3320 2.4G 1T1R(RT3350/RT3370/RT3390) | |
52 | * RF3322 2.4G 2T2R(RT3352/RT3371/RT3372/RT3391/RT3392) | |
53 | * RF3853 2.4G/5G 3T3R(RT3883/RT3563/RT3573/RT3593/RT3662) | |
60687ba7 | 54 | * RF5390 2.4G 1T1R |
b54f78a8 BZ |
55 | */ |
56 | #define RF2820 0x0001 | |
57 | #define RF2850 0x0002 | |
58 | #define RF2720 0x0003 | |
59 | #define RF2750 0x0004 | |
60 | #define RF3020 0x0005 | |
61 | #define RF2020 0x0006 | |
62 | #define RF3021 0x0007 | |
63 | #define RF3022 0x0008 | |
64 | #define RF3052 0x0009 | |
8d4ff3f3 | 65 | #define RF2853 0x000a |
fab799c3 | 66 | #define RF3320 0x000b |
8d4ff3f3 RJH |
67 | #define RF3322 0x000c |
68 | #define RF3853 0x000d | |
60687ba7 | 69 | #define RF5390 0x5390 |
b54f78a8 BZ |
70 | |
71 | /* | |
8d0c9b65 | 72 | * Chipset revisions. |
b54f78a8 | 73 | */ |
8d0c9b65 GW |
74 | #define REV_RT2860C 0x0100 |
75 | #define REV_RT2860D 0x0101 | |
8d0c9b65 GW |
76 | #define REV_RT2872E 0x0200 |
77 | #define REV_RT3070E 0x0200 | |
78 | #define REV_RT3070F 0x0201 | |
79 | #define REV_RT3071E 0x0211 | |
80 | #define REV_RT3090E 0x0211 | |
81 | #define REV_RT3390E 0x0211 | |
60687ba7 | 82 | #define REV_RT5390F 0x0502 |
b54f78a8 BZ |
83 | |
84 | /* | |
85 | * Signal information. | |
86 | * Default offset is required for RSSI <-> dBm conversion. | |
87 | */ | |
74861922 | 88 | #define DEFAULT_RSSI_OFFSET 120 |
b54f78a8 BZ |
89 | |
90 | /* | |
91 | * Register layout information. | |
92 | */ | |
93 | #define CSR_REG_BASE 0x1000 | |
94 | #define CSR_REG_SIZE 0x0800 | |
95 | #define EEPROM_BASE 0x0000 | |
96 | #define EEPROM_SIZE 0x0110 | |
97 | #define BBP_BASE 0x0000 | |
98 | #define BBP_SIZE 0x0080 | |
99 | #define RF_BASE 0x0004 | |
100 | #define RF_SIZE 0x0010 | |
101 | ||
102 | /* | |
103 | * Number of TX queues. | |
104 | */ | |
105 | #define NUM_TX_QUEUES 4 | |
106 | ||
107 | /* | |
fab799c3 | 108 | * Registers. |
b54f78a8 BZ |
109 | */ |
110 | ||
785c3c06 GW |
111 | /* |
112 | * E2PROM_CSR: PCI EEPROM control register. | |
113 | * RELOAD: Write 1 to reload eeprom content. | |
114 | * TYPE: 0: 93c46, 1:93c66. | |
115 | * LOAD_STATUS: 1:loading, 0:done. | |
116 | */ | |
117 | #define E2PROM_CSR 0x0004 | |
118 | #define E2PROM_CSR_DATA_CLOCK FIELD32(0x00000001) | |
119 | #define E2PROM_CSR_CHIP_SELECT FIELD32(0x00000002) | |
120 | #define E2PROM_CSR_DATA_IN FIELD32(0x00000004) | |
121 | #define E2PROM_CSR_DATA_OUT FIELD32(0x00000008) | |
122 | #define E2PROM_CSR_TYPE FIELD32(0x00000030) | |
123 | #define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040) | |
124 | #define E2PROM_CSR_RELOAD FIELD32(0x00000080) | |
125 | ||
60687ba7 RST |
126 | /* |
127 | * AUX_CTRL: Aux/PCI-E related configuration | |
128 | */ | |
129 | #define AUX_CTRL 0x10c | |
130 | #define AUX_CTRL_WAKE_PCIE_EN FIELD32(0x00000002) | |
131 | #define AUX_CTRL_FORCE_PCIE_CLK FIELD32(0x00000400) | |
132 | ||
fab799c3 GW |
133 | /* |
134 | * OPT_14: Unknown register used by rt3xxx devices. | |
135 | */ | |
136 | #define OPT_14_CSR 0x0114 | |
137 | #define OPT_14_CSR_BIT0 FIELD32(0x00000001) | |
138 | ||
b54f78a8 BZ |
139 | /* |
140 | * INT_SOURCE_CSR: Interrupt source register. | |
141 | * Write one to clear corresponding bit. | |
0bdab171 | 142 | * TX_FIFO_STATUS: FIFO Statistics is full, sw should read TX_STA_FIFO |
b54f78a8 BZ |
143 | */ |
144 | #define INT_SOURCE_CSR 0x0200 | |
145 | #define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001) | |
146 | #define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002) | |
147 | #define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004) | |
148 | #define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008) | |
149 | #define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010) | |
150 | #define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020) | |
151 | #define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040) | |
152 | #define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080) | |
153 | #define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100) | |
154 | #define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200) | |
155 | #define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400) | |
156 | #define INT_SOURCE_CSR_TBTT FIELD32(0x00000800) | |
157 | #define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000) | |
158 | #define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000) | |
159 | #define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000) | |
160 | #define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000) | |
161 | #define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000) | |
162 | #define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000) | |
163 | ||
164 | /* | |
165 | * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF. | |
166 | */ | |
167 | #define INT_MASK_CSR 0x0204 | |
168 | #define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001) | |
169 | #define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002) | |
170 | #define INT_MASK_CSR_RX_DONE FIELD32(0x00000004) | |
171 | #define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008) | |
172 | #define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010) | |
173 | #define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020) | |
174 | #define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040) | |
175 | #define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080) | |
176 | #define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100) | |
177 | #define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200) | |
178 | #define INT_MASK_CSR_RXTX_COHERENT FIELD32(0x00000400) | |
179 | #define INT_MASK_CSR_TBTT FIELD32(0x00000800) | |
180 | #define INT_MASK_CSR_PRE_TBTT FIELD32(0x00001000) | |
181 | #define INT_MASK_CSR_TX_FIFO_STATUS FIELD32(0x00002000) | |
182 | #define INT_MASK_CSR_AUTO_WAKEUP FIELD32(0x00004000) | |
183 | #define INT_MASK_CSR_GPTIMER FIELD32(0x00008000) | |
184 | #define INT_MASK_CSR_RX_COHERENT FIELD32(0x00010000) | |
185 | #define INT_MASK_CSR_TX_COHERENT FIELD32(0x00020000) | |
186 | ||
187 | /* | |
188 | * WPDMA_GLO_CFG | |
189 | */ | |
190 | #define WPDMA_GLO_CFG 0x0208 | |
191 | #define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001) | |
192 | #define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002) | |
193 | #define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004) | |
194 | #define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008) | |
195 | #define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030) | |
196 | #define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040) | |
197 | #define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080) | |
198 | #define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00) | |
199 | #define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000) | |
200 | ||
201 | /* | |
202 | * WPDMA_RST_IDX | |
203 | */ | |
204 | #define WPDMA_RST_IDX 0x020c | |
205 | #define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001) | |
206 | #define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002) | |
207 | #define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004) | |
208 | #define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008) | |
209 | #define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010) | |
210 | #define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020) | |
211 | #define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000) | |
212 | ||
213 | /* | |
214 | * DELAY_INT_CFG | |
215 | */ | |
216 | #define DELAY_INT_CFG 0x0210 | |
217 | #define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff) | |
218 | #define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00) | |
219 | #define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000) | |
220 | #define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000) | |
221 | #define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000) | |
222 | #define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000) | |
223 | ||
224 | /* | |
225 | * WMM_AIFSN_CFG: Aifsn for each EDCA AC | |
f615e9a3 ID |
226 | * AIFSN0: AC_VO |
227 | * AIFSN1: AC_VI | |
228 | * AIFSN2: AC_BE | |
229 | * AIFSN3: AC_BK | |
b54f78a8 BZ |
230 | */ |
231 | #define WMM_AIFSN_CFG 0x0214 | |
232 | #define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f) | |
233 | #define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0) | |
234 | #define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00) | |
235 | #define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000) | |
236 | ||
237 | /* | |
238 | * WMM_CWMIN_CSR: CWmin for each EDCA AC | |
f615e9a3 ID |
239 | * CWMIN0: AC_VO |
240 | * CWMIN1: AC_VI | |
241 | * CWMIN2: AC_BE | |
242 | * CWMIN3: AC_BK | |
b54f78a8 BZ |
243 | */ |
244 | #define WMM_CWMIN_CFG 0x0218 | |
245 | #define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f) | |
246 | #define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0) | |
247 | #define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00) | |
248 | #define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000) | |
249 | ||
250 | /* | |
251 | * WMM_CWMAX_CSR: CWmax for each EDCA AC | |
f615e9a3 ID |
252 | * CWMAX0: AC_VO |
253 | * CWMAX1: AC_VI | |
254 | * CWMAX2: AC_BE | |
255 | * CWMAX3: AC_BK | |
b54f78a8 BZ |
256 | */ |
257 | #define WMM_CWMAX_CFG 0x021c | |
258 | #define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f) | |
259 | #define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0) | |
260 | #define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00) | |
261 | #define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000) | |
262 | ||
263 | /* | |
f615e9a3 ID |
264 | * AC_TXOP0: AC_VO/AC_VI TXOP register |
265 | * AC0TXOP: AC_VO in unit of 32us | |
266 | * AC1TXOP: AC_VI in unit of 32us | |
b54f78a8 BZ |
267 | */ |
268 | #define WMM_TXOP0_CFG 0x0220 | |
269 | #define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff) | |
270 | #define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000) | |
271 | ||
272 | /* | |
f615e9a3 ID |
273 | * AC_TXOP1: AC_BE/AC_BK TXOP register |
274 | * AC2TXOP: AC_BE in unit of 32us | |
275 | * AC3TXOP: AC_BK in unit of 32us | |
b54f78a8 BZ |
276 | */ |
277 | #define WMM_TXOP1_CFG 0x0224 | |
278 | #define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff) | |
279 | #define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000) | |
280 | ||
281 | /* | |
282 | * GPIO_CTRL_CFG: | |
d96aa640 | 283 | * GPIOD: GPIO direction, 0: Output, 1: Input |
b54f78a8 BZ |
284 | */ |
285 | #define GPIO_CTRL_CFG 0x0228 | |
286 | #define GPIO_CTRL_CFG_BIT0 FIELD32(0x00000001) | |
287 | #define GPIO_CTRL_CFG_BIT1 FIELD32(0x00000002) | |
288 | #define GPIO_CTRL_CFG_BIT2 FIELD32(0x00000004) | |
289 | #define GPIO_CTRL_CFG_BIT3 FIELD32(0x00000008) | |
290 | #define GPIO_CTRL_CFG_BIT4 FIELD32(0x00000010) | |
291 | #define GPIO_CTRL_CFG_BIT5 FIELD32(0x00000020) | |
292 | #define GPIO_CTRL_CFG_BIT6 FIELD32(0x00000040) | |
293 | #define GPIO_CTRL_CFG_BIT7 FIELD32(0x00000080) | |
fe59147c ST |
294 | #define GPIO_CTRL_CFG_GPIOD_BIT0 FIELD32(0x00000100) |
295 | #define GPIO_CTRL_CFG_GPIOD_BIT1 FIELD32(0x00000200) | |
296 | #define GPIO_CTRL_CFG_GPIOD_BIT2 FIELD32(0x00000400) | |
297 | #define GPIO_CTRL_CFG_GPIOD_BIT3 FIELD32(0x00000800) | |
298 | #define GPIO_CTRL_CFG_GPIOD_BIT4 FIELD32(0x00001000) | |
299 | #define GPIO_CTRL_CFG_GPIOD_BIT5 FIELD32(0x00002000) | |
300 | #define GPIO_CTRL_CFG_GPIOD_BIT6 FIELD32(0x00004000) | |
301 | #define GPIO_CTRL_CFG_GPIOD_BIT7 FIELD32(0x00008000) | |
b54f78a8 BZ |
302 | |
303 | /* | |
304 | * MCU_CMD_CFG | |
305 | */ | |
306 | #define MCU_CMD_CFG 0x022c | |
307 | ||
308 | /* | |
f615e9a3 | 309 | * AC_VO register offsets |
b54f78a8 BZ |
310 | */ |
311 | #define TX_BASE_PTR0 0x0230 | |
312 | #define TX_MAX_CNT0 0x0234 | |
313 | #define TX_CTX_IDX0 0x0238 | |
314 | #define TX_DTX_IDX0 0x023c | |
315 | ||
316 | /* | |
f615e9a3 | 317 | * AC_VI register offsets |
b54f78a8 BZ |
318 | */ |
319 | #define TX_BASE_PTR1 0x0240 | |
320 | #define TX_MAX_CNT1 0x0244 | |
321 | #define TX_CTX_IDX1 0x0248 | |
322 | #define TX_DTX_IDX1 0x024c | |
323 | ||
324 | /* | |
f615e9a3 | 325 | * AC_BE register offsets |
b54f78a8 BZ |
326 | */ |
327 | #define TX_BASE_PTR2 0x0250 | |
328 | #define TX_MAX_CNT2 0x0254 | |
329 | #define TX_CTX_IDX2 0x0258 | |
330 | #define TX_DTX_IDX2 0x025c | |
331 | ||
332 | /* | |
f615e9a3 | 333 | * AC_BK register offsets |
b54f78a8 BZ |
334 | */ |
335 | #define TX_BASE_PTR3 0x0260 | |
336 | #define TX_MAX_CNT3 0x0264 | |
337 | #define TX_CTX_IDX3 0x0268 | |
338 | #define TX_DTX_IDX3 0x026c | |
339 | ||
340 | /* | |
341 | * HCCA register offsets | |
342 | */ | |
343 | #define TX_BASE_PTR4 0x0270 | |
344 | #define TX_MAX_CNT4 0x0274 | |
345 | #define TX_CTX_IDX4 0x0278 | |
346 | #define TX_DTX_IDX4 0x027c | |
347 | ||
348 | /* | |
349 | * MGMT register offsets | |
350 | */ | |
351 | #define TX_BASE_PTR5 0x0280 | |
352 | #define TX_MAX_CNT5 0x0284 | |
353 | #define TX_CTX_IDX5 0x0288 | |
354 | #define TX_DTX_IDX5 0x028c | |
355 | ||
356 | /* | |
357 | * RX register offsets | |
358 | */ | |
359 | #define RX_BASE_PTR 0x0290 | |
360 | #define RX_MAX_CNT 0x0294 | |
361 | #define RX_CRX_IDX 0x0298 | |
362 | #define RX_DRX_IDX 0x029c | |
363 | ||
785c3c06 GW |
364 | /* |
365 | * USB_DMA_CFG | |
366 | * RX_BULK_AGG_TIMEOUT: Rx Bulk Aggregation TimeOut in unit of 33ns. | |
367 | * RX_BULK_AGG_LIMIT: Rx Bulk Aggregation Limit in unit of 256 bytes. | |
368 | * PHY_CLEAR: phy watch dog enable. | |
369 | * TX_CLEAR: Clear USB DMA TX path. | |
370 | * TXOP_HALT: Halt TXOP count down when TX buffer is full. | |
371 | * RX_BULK_AGG_EN: Enable Rx Bulk Aggregation. | |
372 | * RX_BULK_EN: Enable USB DMA Rx. | |
373 | * TX_BULK_EN: Enable USB DMA Tx. | |
374 | * EP_OUT_VALID: OUT endpoint data valid. | |
375 | * RX_BUSY: USB DMA RX FSM busy. | |
376 | * TX_BUSY: USB DMA TX FSM busy. | |
377 | */ | |
378 | #define USB_DMA_CFG 0x02a0 | |
379 | #define USB_DMA_CFG_RX_BULK_AGG_TIMEOUT FIELD32(0x000000ff) | |
380 | #define USB_DMA_CFG_RX_BULK_AGG_LIMIT FIELD32(0x0000ff00) | |
381 | #define USB_DMA_CFG_PHY_CLEAR FIELD32(0x00010000) | |
382 | #define USB_DMA_CFG_TX_CLEAR FIELD32(0x00080000) | |
383 | #define USB_DMA_CFG_TXOP_HALT FIELD32(0x00100000) | |
384 | #define USB_DMA_CFG_RX_BULK_AGG_EN FIELD32(0x00200000) | |
385 | #define USB_DMA_CFG_RX_BULK_EN FIELD32(0x00400000) | |
386 | #define USB_DMA_CFG_TX_BULK_EN FIELD32(0x00800000) | |
387 | #define USB_DMA_CFG_EP_OUT_VALID FIELD32(0x3f000000) | |
388 | #define USB_DMA_CFG_RX_BUSY FIELD32(0x40000000) | |
389 | #define USB_DMA_CFG_TX_BUSY FIELD32(0x80000000) | |
390 | ||
391 | /* | |
392 | * US_CYC_CNT | |
c6fcc0e5 RJH |
393 | * BT_MODE_EN: Bluetooth mode enable |
394 | * CLOCK CYCLE: Clock cycle count in 1us. | |
395 | * PCI:0x21, PCIE:0x7d, USB:0x1e | |
785c3c06 GW |
396 | */ |
397 | #define US_CYC_CNT 0x02a4 | |
c6fcc0e5 | 398 | #define US_CYC_CNT_BT_MODE_EN FIELD32(0x00000100) |
785c3c06 GW |
399 | #define US_CYC_CNT_CLOCK_CYCLE FIELD32(0x000000ff) |
400 | ||
b54f78a8 BZ |
401 | /* |
402 | * PBF_SYS_CTRL | |
403 | * HOST_RAM_WRITE: enable Host program ram write selection | |
404 | */ | |
405 | #define PBF_SYS_CTRL 0x0400 | |
406 | #define PBF_SYS_CTRL_READY FIELD32(0x00000080) | |
407 | #define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000) | |
408 | ||
409 | /* | |
410 | * HOST-MCU shared memory | |
411 | */ | |
412 | #define HOST_CMD_CSR 0x0404 | |
413 | #define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff) | |
414 | ||
415 | /* | |
416 | * PBF registers | |
417 | * Most are for debug. Driver doesn't touch PBF register. | |
418 | */ | |
419 | #define PBF_CFG 0x0408 | |
420 | #define PBF_MAX_PCNT 0x040c | |
421 | #define PBF_CTRL 0x0410 | |
422 | #define PBF_INT_STA 0x0414 | |
423 | #define PBF_INT_ENA 0x0418 | |
424 | ||
425 | /* | |
426 | * BCN_OFFSET0: | |
427 | */ | |
428 | #define BCN_OFFSET0 0x042c | |
429 | #define BCN_OFFSET0_BCN0 FIELD32(0x000000ff) | |
430 | #define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00) | |
431 | #define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000) | |
432 | #define BCN_OFFSET0_BCN3 FIELD32(0xff000000) | |
433 | ||
434 | /* | |
435 | * BCN_OFFSET1: | |
436 | */ | |
437 | #define BCN_OFFSET1 0x0430 | |
438 | #define BCN_OFFSET1_BCN4 FIELD32(0x000000ff) | |
439 | #define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00) | |
440 | #define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000) | |
441 | #define BCN_OFFSET1_BCN7 FIELD32(0xff000000) | |
442 | ||
443 | /* | |
8c5765fd ID |
444 | * TXRXQ_PCNT: PBF register |
445 | * PCNT_TX0Q: Page count for TX hardware queue 0 | |
446 | * PCNT_TX1Q: Page count for TX hardware queue 1 | |
447 | * PCNT_TX2Q: Page count for TX hardware queue 2 | |
448 | * PCNT_RX0Q: Page count for RX hardware queue | |
b54f78a8 BZ |
449 | */ |
450 | #define TXRXQ_PCNT 0x0438 | |
8c5765fd ID |
451 | #define TXRXQ_PCNT_TX0Q FIELD32(0x000000ff) |
452 | #define TXRXQ_PCNT_TX1Q FIELD32(0x0000ff00) | |
453 | #define TXRXQ_PCNT_TX2Q FIELD32(0x00ff0000) | |
454 | #define TXRXQ_PCNT_RX0Q FIELD32(0xff000000) | |
455 | ||
456 | /* | |
457 | * PBF register | |
458 | * Debug. Driver doesn't touch PBF register. | |
459 | */ | |
b54f78a8 BZ |
460 | #define PBF_DBG 0x043c |
461 | ||
462 | /* | |
463 | * RF registers | |
464 | */ | |
465 | #define RF_CSR_CFG 0x0500 | |
466 | #define RF_CSR_CFG_DATA FIELD32(0x000000ff) | |
60687ba7 | 467 | #define RF_CSR_CFG_REGNUM FIELD32(0x00003f00) |
b54f78a8 BZ |
468 | #define RF_CSR_CFG_WRITE FIELD32(0x00010000) |
469 | #define RF_CSR_CFG_BUSY FIELD32(0x00020000) | |
470 | ||
30e84034 BZ |
471 | /* |
472 | * EFUSE_CSR: RT30x0 EEPROM | |
473 | */ | |
474 | #define EFUSE_CTRL 0x0580 | |
475 | #define EFUSE_CTRL_ADDRESS_IN FIELD32(0x03fe0000) | |
476 | #define EFUSE_CTRL_MODE FIELD32(0x000000c0) | |
477 | #define EFUSE_CTRL_KICK FIELD32(0x40000000) | |
478 | #define EFUSE_CTRL_PRESENT FIELD32(0x80000000) | |
479 | ||
480 | /* | |
481 | * EFUSE_DATA0 | |
482 | */ | |
483 | #define EFUSE_DATA0 0x0590 | |
484 | ||
485 | /* | |
486 | * EFUSE_DATA1 | |
487 | */ | |
488 | #define EFUSE_DATA1 0x0594 | |
489 | ||
490 | /* | |
491 | * EFUSE_DATA2 | |
492 | */ | |
493 | #define EFUSE_DATA2 0x0598 | |
494 | ||
495 | /* | |
496 | * EFUSE_DATA3 | |
497 | */ | |
498 | #define EFUSE_DATA3 0x059c | |
499 | ||
fab799c3 GW |
500 | /* |
501 | * LDO_CFG0 | |
502 | */ | |
503 | #define LDO_CFG0 0x05d4 | |
504 | #define LDO_CFG0_DELAY3 FIELD32(0x000000ff) | |
505 | #define LDO_CFG0_DELAY2 FIELD32(0x0000ff00) | |
506 | #define LDO_CFG0_DELAY1 FIELD32(0x00ff0000) | |
507 | #define LDO_CFG0_BGSEL FIELD32(0x03000000) | |
508 | #define LDO_CFG0_LDO_CORE_VLEVEL FIELD32(0x1c000000) | |
509 | #define LD0_CFG0_LDO25_LEVEL FIELD32(0x60000000) | |
510 | #define LDO_CFG0_LDO25_LARGEA FIELD32(0x80000000) | |
511 | ||
512 | /* | |
513 | * GPIO_SWITCH | |
514 | */ | |
515 | #define GPIO_SWITCH 0x05dc | |
516 | #define GPIO_SWITCH_0 FIELD32(0x00000001) | |
517 | #define GPIO_SWITCH_1 FIELD32(0x00000002) | |
518 | #define GPIO_SWITCH_2 FIELD32(0x00000004) | |
519 | #define GPIO_SWITCH_3 FIELD32(0x00000008) | |
520 | #define GPIO_SWITCH_4 FIELD32(0x00000010) | |
521 | #define GPIO_SWITCH_5 FIELD32(0x00000020) | |
522 | #define GPIO_SWITCH_6 FIELD32(0x00000040) | |
523 | #define GPIO_SWITCH_7 FIELD32(0x00000080) | |
524 | ||
b54f78a8 BZ |
525 | /* |
526 | * MAC Control/Status Registers(CSR). | |
527 | * Some values are set in TU, whereas 1 TU == 1024 us. | |
528 | */ | |
529 | ||
530 | /* | |
531 | * MAC_CSR0: ASIC revision number. | |
532 | * ASIC_REV: 0 | |
533 | * ASIC_VER: 2860 or 2870 | |
534 | */ | |
535 | #define MAC_CSR0 0x1000 | |
49e721ec GW |
536 | #define MAC_CSR0_REVISION FIELD32(0x0000ffff) |
537 | #define MAC_CSR0_CHIPSET FIELD32(0xffff0000) | |
b54f78a8 BZ |
538 | |
539 | /* | |
540 | * MAC_SYS_CTRL: | |
541 | */ | |
542 | #define MAC_SYS_CTRL 0x1004 | |
543 | #define MAC_SYS_CTRL_RESET_CSR FIELD32(0x00000001) | |
544 | #define MAC_SYS_CTRL_RESET_BBP FIELD32(0x00000002) | |
545 | #define MAC_SYS_CTRL_ENABLE_TX FIELD32(0x00000004) | |
546 | #define MAC_SYS_CTRL_ENABLE_RX FIELD32(0x00000008) | |
547 | #define MAC_SYS_CTRL_CONTINUOUS_TX FIELD32(0x00000010) | |
548 | #define MAC_SYS_CTRL_LOOPBACK FIELD32(0x00000020) | |
549 | #define MAC_SYS_CTRL_WLAN_HALT FIELD32(0x00000040) | |
550 | #define MAC_SYS_CTRL_RX_TIMESTAMP FIELD32(0x00000080) | |
551 | ||
552 | /* | |
553 | * MAC_ADDR_DW0: STA MAC register 0 | |
554 | */ | |
555 | #define MAC_ADDR_DW0 0x1008 | |
556 | #define MAC_ADDR_DW0_BYTE0 FIELD32(0x000000ff) | |
557 | #define MAC_ADDR_DW0_BYTE1 FIELD32(0x0000ff00) | |
558 | #define MAC_ADDR_DW0_BYTE2 FIELD32(0x00ff0000) | |
559 | #define MAC_ADDR_DW0_BYTE3 FIELD32(0xff000000) | |
560 | ||
561 | /* | |
562 | * MAC_ADDR_DW1: STA MAC register 1 | |
563 | * UNICAST_TO_ME_MASK: | |
564 | * Used to mask off bits from byte 5 of the MAC address | |
565 | * to determine the UNICAST_TO_ME bit for RX frames. | |
566 | * The full mask is complemented by BSS_ID_MASK: | |
567 | * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK | |
568 | */ | |
569 | #define MAC_ADDR_DW1 0x100c | |
570 | #define MAC_ADDR_DW1_BYTE4 FIELD32(0x000000ff) | |
571 | #define MAC_ADDR_DW1_BYTE5 FIELD32(0x0000ff00) | |
572 | #define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000) | |
573 | ||
574 | /* | |
575 | * MAC_BSSID_DW0: BSSID register 0 | |
576 | */ | |
577 | #define MAC_BSSID_DW0 0x1010 | |
578 | #define MAC_BSSID_DW0_BYTE0 FIELD32(0x000000ff) | |
579 | #define MAC_BSSID_DW0_BYTE1 FIELD32(0x0000ff00) | |
580 | #define MAC_BSSID_DW0_BYTE2 FIELD32(0x00ff0000) | |
581 | #define MAC_BSSID_DW0_BYTE3 FIELD32(0xff000000) | |
582 | ||
583 | /* | |
584 | * MAC_BSSID_DW1: BSSID register 1 | |
585 | * BSS_ID_MASK: | |
586 | * 0: 1-BSSID mode (BSS index = 0) | |
587 | * 1: 2-BSSID mode (BSS index: Byte5, bit 0) | |
588 | * 2: 4-BSSID mode (BSS index: byte5, bit 0 - 1) | |
589 | * 3: 8-BSSID mode (BSS index: byte5, bit 0 - 2) | |
590 | * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the | |
591 | * BSSID. This will make sure that those bits will be ignored | |
592 | * when determining the MY_BSS of RX frames. | |
593 | */ | |
594 | #define MAC_BSSID_DW1 0x1014 | |
595 | #define MAC_BSSID_DW1_BYTE4 FIELD32(0x000000ff) | |
596 | #define MAC_BSSID_DW1_BYTE5 FIELD32(0x0000ff00) | |
597 | #define MAC_BSSID_DW1_BSS_ID_MASK FIELD32(0x00030000) | |
598 | #define MAC_BSSID_DW1_BSS_BCN_NUM FIELD32(0x001c0000) | |
599 | ||
600 | /* | |
601 | * MAX_LEN_CFG: Maximum frame length register. | |
602 | * MAX_MPDU: rt2860b max 16k bytes | |
603 | * MAX_PSDU: Maximum PSDU length | |
604 | * (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16 | |
605 | */ | |
606 | #define MAX_LEN_CFG 0x1018 | |
607 | #define MAX_LEN_CFG_MAX_MPDU FIELD32(0x00000fff) | |
608 | #define MAX_LEN_CFG_MAX_PSDU FIELD32(0x00003000) | |
609 | #define MAX_LEN_CFG_MIN_PSDU FIELD32(0x0000c000) | |
610 | #define MAX_LEN_CFG_MIN_MPDU FIELD32(0x000f0000) | |
611 | ||
612 | /* | |
613 | * BBP_CSR_CFG: BBP serial control register | |
614 | * VALUE: Register value to program into BBP | |
615 | * REG_NUM: Selected BBP register | |
616 | * READ_CONTROL: 0 write BBP, 1 read BBP | |
617 | * BUSY: ASIC is busy executing BBP commands | |
618 | * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks | |
619 | * BBP_RW_MODE: 0 serial, 1 paralell | |
620 | */ | |
621 | #define BBP_CSR_CFG 0x101c | |
622 | #define BBP_CSR_CFG_VALUE FIELD32(0x000000ff) | |
623 | #define BBP_CSR_CFG_REGNUM FIELD32(0x0000ff00) | |
624 | #define BBP_CSR_CFG_READ_CONTROL FIELD32(0x00010000) | |
625 | #define BBP_CSR_CFG_BUSY FIELD32(0x00020000) | |
626 | #define BBP_CSR_CFG_BBP_PAR_DUR FIELD32(0x00040000) | |
627 | #define BBP_CSR_CFG_BBP_RW_MODE FIELD32(0x00080000) | |
628 | ||
629 | /* | |
630 | * RF_CSR_CFG0: RF control register | |
631 | * REGID_AND_VALUE: Register value to program into RF | |
632 | * BITWIDTH: Selected RF register | |
633 | * STANDBYMODE: 0 high when standby, 1 low when standby | |
634 | * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate | |
635 | * BUSY: ASIC is busy executing RF commands | |
636 | */ | |
637 | #define RF_CSR_CFG0 0x1020 | |
638 | #define RF_CSR_CFG0_REGID_AND_VALUE FIELD32(0x00ffffff) | |
639 | #define RF_CSR_CFG0_BITWIDTH FIELD32(0x1f000000) | |
640 | #define RF_CSR_CFG0_REG_VALUE_BW FIELD32(0x1fffffff) | |
641 | #define RF_CSR_CFG0_STANDBYMODE FIELD32(0x20000000) | |
642 | #define RF_CSR_CFG0_SEL FIELD32(0x40000000) | |
643 | #define RF_CSR_CFG0_BUSY FIELD32(0x80000000) | |
644 | ||
645 | /* | |
646 | * RF_CSR_CFG1: RF control register | |
647 | * REGID_AND_VALUE: Register value to program into RF | |
648 | * RFGAP: Gap between BB_CONTROL_RF and RF_LE | |
649 | * 0: 3 system clock cycle (37.5usec) | |
650 | * 1: 5 system clock cycle (62.5usec) | |
651 | */ | |
652 | #define RF_CSR_CFG1 0x1024 | |
653 | #define RF_CSR_CFG1_REGID_AND_VALUE FIELD32(0x00ffffff) | |
654 | #define RF_CSR_CFG1_RFGAP FIELD32(0x1f000000) | |
655 | ||
656 | /* | |
657 | * RF_CSR_CFG2: RF control register | |
658 | * VALUE: Register value to program into RF | |
b54f78a8 BZ |
659 | */ |
660 | #define RF_CSR_CFG2 0x1028 | |
661 | #define RF_CSR_CFG2_VALUE FIELD32(0x00ffffff) | |
662 | ||
663 | /* | |
664 | * LED_CFG: LED control | |
665 | * color LED's: | |
666 | * 0: off | |
667 | * 1: blinking upon TX2 | |
668 | * 2: periodic slow blinking | |
669 | * 3: always on | |
670 | * LED polarity: | |
671 | * 0: active low | |
672 | * 1: active high | |
673 | */ | |
674 | #define LED_CFG 0x102c | |
675 | #define LED_CFG_ON_PERIOD FIELD32(0x000000ff) | |
676 | #define LED_CFG_OFF_PERIOD FIELD32(0x0000ff00) | |
677 | #define LED_CFG_SLOW_BLINK_PERIOD FIELD32(0x003f0000) | |
678 | #define LED_CFG_R_LED_MODE FIELD32(0x03000000) | |
679 | #define LED_CFG_G_LED_MODE FIELD32(0x0c000000) | |
680 | #define LED_CFG_Y_LED_MODE FIELD32(0x30000000) | |
681 | #define LED_CFG_LED_POLAR FIELD32(0x40000000) | |
682 | ||
47ee3eb1 HS |
683 | /* |
684 | * AMPDU_BA_WINSIZE: Force BlockAck window size | |
685 | * FORCE_WINSIZE_ENABLE: | |
686 | * 0: Disable forcing of BlockAck window size | |
687 | * 1: Enable forcing of BlockAck window size, overwrites values BlockAck | |
688 | * window size values in the TXWI | |
689 | * FORCE_WINSIZE: BlockAck window size | |
690 | */ | |
691 | #define AMPDU_BA_WINSIZE 0x1040 | |
692 | #define AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE FIELD32(0x00000020) | |
693 | #define AMPDU_BA_WINSIZE_FORCE_WINSIZE FIELD32(0x0000001f) | |
694 | ||
b54f78a8 BZ |
695 | /* |
696 | * XIFS_TIME_CFG: MAC timing | |
697 | * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX | |
698 | * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX | |
699 | * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX | |
700 | * when MAC doesn't reference BBP signal BBRXEND | |
701 | * EIFS: unit 1us | |
702 | * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer | |
703 | * | |
704 | */ | |
705 | #define XIFS_TIME_CFG 0x1100 | |
706 | #define XIFS_TIME_CFG_CCKM_SIFS_TIME FIELD32(0x000000ff) | |
707 | #define XIFS_TIME_CFG_OFDM_SIFS_TIME FIELD32(0x0000ff00) | |
708 | #define XIFS_TIME_CFG_OFDM_XIFS_TIME FIELD32(0x000f0000) | |
709 | #define XIFS_TIME_CFG_EIFS FIELD32(0x1ff00000) | |
710 | #define XIFS_TIME_CFG_BB_RXEND_ENABLE FIELD32(0x20000000) | |
711 | ||
712 | /* | |
713 | * BKOFF_SLOT_CFG: | |
714 | */ | |
715 | #define BKOFF_SLOT_CFG 0x1104 | |
716 | #define BKOFF_SLOT_CFG_SLOT_TIME FIELD32(0x000000ff) | |
717 | #define BKOFF_SLOT_CFG_CC_DELAY_TIME FIELD32(0x0000ff00) | |
718 | ||
719 | /* | |
720 | * NAV_TIME_CFG: | |
721 | */ | |
722 | #define NAV_TIME_CFG 0x1108 | |
723 | #define NAV_TIME_CFG_SIFS FIELD32(0x000000ff) | |
724 | #define NAV_TIME_CFG_SLOT_TIME FIELD32(0x0000ff00) | |
725 | #define NAV_TIME_CFG_EIFS FIELD32(0x01ff0000) | |
726 | #define NAV_TIME_ZERO_SIFS FIELD32(0x02000000) | |
727 | ||
728 | /* | |
729 | * CH_TIME_CFG: count as channel busy | |
977206d7 HS |
730 | * EIFS_BUSY: Count EIFS as channel busy |
731 | * NAV_BUSY: Count NAS as channel busy | |
732 | * RX_BUSY: Count RX as channel busy | |
733 | * TX_BUSY: Count TX as channel busy | |
734 | * TMR_EN: Enable channel statistics timer | |
b54f78a8 BZ |
735 | */ |
736 | #define CH_TIME_CFG 0x110c | |
977206d7 HS |
737 | #define CH_TIME_CFG_EIFS_BUSY FIELD32(0x00000010) |
738 | #define CH_TIME_CFG_NAV_BUSY FIELD32(0x00000008) | |
739 | #define CH_TIME_CFG_RX_BUSY FIELD32(0x00000004) | |
740 | #define CH_TIME_CFG_TX_BUSY FIELD32(0x00000002) | |
741 | #define CH_TIME_CFG_TMR_EN FIELD32(0x00000001) | |
b54f78a8 BZ |
742 | |
743 | /* | |
744 | * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us | |
745 | */ | |
746 | #define PBF_LIFE_TIMER 0x1110 | |
747 | ||
748 | /* | |
749 | * BCN_TIME_CFG: | |
750 | * BEACON_INTERVAL: in unit of 1/16 TU | |
751 | * TSF_TICKING: Enable TSF auto counting | |
752 | * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode | |
753 | * BEACON_GEN: Enable beacon generator | |
754 | */ | |
755 | #define BCN_TIME_CFG 0x1114 | |
756 | #define BCN_TIME_CFG_BEACON_INTERVAL FIELD32(0x0000ffff) | |
757 | #define BCN_TIME_CFG_TSF_TICKING FIELD32(0x00010000) | |
758 | #define BCN_TIME_CFG_TSF_SYNC FIELD32(0x00060000) | |
759 | #define BCN_TIME_CFG_TBTT_ENABLE FIELD32(0x00080000) | |
760 | #define BCN_TIME_CFG_BEACON_GEN FIELD32(0x00100000) | |
761 | #define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000) | |
762 | ||
763 | /* | |
764 | * TBTT_SYNC_CFG: | |
c4c18a9d HS |
765 | * BCN_AIFSN: Beacon AIFSN after TBTT interrupt in slots |
766 | * BCN_CWMIN: Beacon CWMin after TBTT interrupt in slots | |
b54f78a8 BZ |
767 | */ |
768 | #define TBTT_SYNC_CFG 0x1118 | |
c4c18a9d HS |
769 | #define TBTT_SYNC_CFG_TBTT_ADJUST FIELD32(0x000000ff) |
770 | #define TBTT_SYNC_CFG_BCN_EXP_WIN FIELD32(0x0000ff00) | |
771 | #define TBTT_SYNC_CFG_BCN_AIFSN FIELD32(0x000f0000) | |
772 | #define TBTT_SYNC_CFG_BCN_CWMIN FIELD32(0x00f00000) | |
b54f78a8 BZ |
773 | |
774 | /* | |
775 | * TSF_TIMER_DW0: Local lsb TSF timer, read-only | |
776 | */ | |
777 | #define TSF_TIMER_DW0 0x111c | |
778 | #define TSF_TIMER_DW0_LOW_WORD FIELD32(0xffffffff) | |
779 | ||
780 | /* | |
781 | * TSF_TIMER_DW1: Local msb TSF timer, read-only | |
782 | */ | |
783 | #define TSF_TIMER_DW1 0x1120 | |
784 | #define TSF_TIMER_DW1_HIGH_WORD FIELD32(0xffffffff) | |
785 | ||
786 | /* | |
787 | * TBTT_TIMER: TImer remains till next TBTT, read-only | |
788 | */ | |
789 | #define TBTT_TIMER 0x1124 | |
790 | ||
791 | /* | |
9f926fb5 HS |
792 | * INT_TIMER_CFG: timer configuration |
793 | * PRE_TBTT_TIMER: leadtime to tbtt for pretbtt interrupt in units of 1/16 TU | |
794 | * GP_TIMER: period of general purpose timer in units of 1/16 TU | |
b54f78a8 BZ |
795 | */ |
796 | #define INT_TIMER_CFG 0x1128 | |
9f926fb5 HS |
797 | #define INT_TIMER_CFG_PRE_TBTT_TIMER FIELD32(0x0000ffff) |
798 | #define INT_TIMER_CFG_GP_TIMER FIELD32(0xffff0000) | |
b54f78a8 BZ |
799 | |
800 | /* | |
801 | * INT_TIMER_EN: GP-timer and pre-tbtt Int enable | |
802 | */ | |
803 | #define INT_TIMER_EN 0x112c | |
9f926fb5 HS |
804 | #define INT_TIMER_EN_PRE_TBTT_TIMER FIELD32(0x00000001) |
805 | #define INT_TIMER_EN_GP_TIMER FIELD32(0x00000002) | |
b54f78a8 BZ |
806 | |
807 | /* | |
d4ce3a5e | 808 | * CH_IDLE_STA: channel idle time (in us) |
b54f78a8 BZ |
809 | */ |
810 | #define CH_IDLE_STA 0x1130 | |
811 | ||
812 | /* | |
d4ce3a5e | 813 | * CH_BUSY_STA: channel busy time on primary channel (in us) |
b54f78a8 BZ |
814 | */ |
815 | #define CH_BUSY_STA 0x1134 | |
816 | ||
d4ce3a5e HS |
817 | /* |
818 | * CH_BUSY_STA_SEC: channel busy time on secondary channel in HT40 mode (in us) | |
819 | */ | |
820 | #define CH_BUSY_STA_SEC 0x1138 | |
821 | ||
b54f78a8 BZ |
822 | /* |
823 | * MAC_STATUS_CFG: | |
824 | * BBP_RF_BUSY: When set to 0, BBP and RF are stable. | |
825 | * if 1 or higher one of the 2 registers is busy. | |
826 | */ | |
827 | #define MAC_STATUS_CFG 0x1200 | |
828 | #define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003) | |
829 | ||
830 | /* | |
831 | * PWR_PIN_CFG: | |
832 | */ | |
833 | #define PWR_PIN_CFG 0x1204 | |
834 | ||
835 | /* | |
836 | * AUTOWAKEUP_CFG: Manual power control / status register | |
837 | * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set | |
838 | * AUTOWAKE: 0:sleep, 1:awake | |
839 | */ | |
840 | #define AUTOWAKEUP_CFG 0x1208 | |
841 | #define AUTOWAKEUP_CFG_AUTO_LEAD_TIME FIELD32(0x000000ff) | |
842 | #define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00) | |
843 | #define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000) | |
844 | ||
845 | /* | |
846 | * EDCA_AC0_CFG: | |
847 | */ | |
848 | #define EDCA_AC0_CFG 0x1300 | |
849 | #define EDCA_AC0_CFG_TX_OP FIELD32(0x000000ff) | |
850 | #define EDCA_AC0_CFG_AIFSN FIELD32(0x00000f00) | |
851 | #define EDCA_AC0_CFG_CWMIN FIELD32(0x0000f000) | |
852 | #define EDCA_AC0_CFG_CWMAX FIELD32(0x000f0000) | |
853 | ||
854 | /* | |
855 | * EDCA_AC1_CFG: | |
856 | */ | |
857 | #define EDCA_AC1_CFG 0x1304 | |
858 | #define EDCA_AC1_CFG_TX_OP FIELD32(0x000000ff) | |
859 | #define EDCA_AC1_CFG_AIFSN FIELD32(0x00000f00) | |
860 | #define EDCA_AC1_CFG_CWMIN FIELD32(0x0000f000) | |
861 | #define EDCA_AC1_CFG_CWMAX FIELD32(0x000f0000) | |
862 | ||
863 | /* | |
864 | * EDCA_AC2_CFG: | |
865 | */ | |
866 | #define EDCA_AC2_CFG 0x1308 | |
867 | #define EDCA_AC2_CFG_TX_OP FIELD32(0x000000ff) | |
868 | #define EDCA_AC2_CFG_AIFSN FIELD32(0x00000f00) | |
869 | #define EDCA_AC2_CFG_CWMIN FIELD32(0x0000f000) | |
870 | #define EDCA_AC2_CFG_CWMAX FIELD32(0x000f0000) | |
871 | ||
872 | /* | |
873 | * EDCA_AC3_CFG: | |
874 | */ | |
875 | #define EDCA_AC3_CFG 0x130c | |
876 | #define EDCA_AC3_CFG_TX_OP FIELD32(0x000000ff) | |
877 | #define EDCA_AC3_CFG_AIFSN FIELD32(0x00000f00) | |
878 | #define EDCA_AC3_CFG_CWMIN FIELD32(0x0000f000) | |
879 | #define EDCA_AC3_CFG_CWMAX FIELD32(0x000f0000) | |
880 | ||
881 | /* | |
882 | * EDCA_TID_AC_MAP: | |
883 | */ | |
884 | #define EDCA_TID_AC_MAP 0x1310 | |
885 | ||
5e846004 HS |
886 | /* |
887 | * TX_PWR_CFG: | |
888 | */ | |
889 | #define TX_PWR_CFG_RATE0 FIELD32(0x0000000f) | |
890 | #define TX_PWR_CFG_RATE1 FIELD32(0x000000f0) | |
891 | #define TX_PWR_CFG_RATE2 FIELD32(0x00000f00) | |
892 | #define TX_PWR_CFG_RATE3 FIELD32(0x0000f000) | |
893 | #define TX_PWR_CFG_RATE4 FIELD32(0x000f0000) | |
894 | #define TX_PWR_CFG_RATE5 FIELD32(0x00f00000) | |
895 | #define TX_PWR_CFG_RATE6 FIELD32(0x0f000000) | |
896 | #define TX_PWR_CFG_RATE7 FIELD32(0xf0000000) | |
897 | ||
b54f78a8 BZ |
898 | /* |
899 | * TX_PWR_CFG_0: | |
900 | */ | |
901 | #define TX_PWR_CFG_0 0x1314 | |
902 | #define TX_PWR_CFG_0_1MBS FIELD32(0x0000000f) | |
903 | #define TX_PWR_CFG_0_2MBS FIELD32(0x000000f0) | |
904 | #define TX_PWR_CFG_0_55MBS FIELD32(0x00000f00) | |
905 | #define TX_PWR_CFG_0_11MBS FIELD32(0x0000f000) | |
906 | #define TX_PWR_CFG_0_6MBS FIELD32(0x000f0000) | |
907 | #define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000) | |
908 | #define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000) | |
909 | #define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000) | |
910 | ||
911 | /* | |
912 | * TX_PWR_CFG_1: | |
913 | */ | |
914 | #define TX_PWR_CFG_1 0x1318 | |
915 | #define TX_PWR_CFG_1_24MBS FIELD32(0x0000000f) | |
916 | #define TX_PWR_CFG_1_36MBS FIELD32(0x000000f0) | |
917 | #define TX_PWR_CFG_1_48MBS FIELD32(0x00000f00) | |
918 | #define TX_PWR_CFG_1_54MBS FIELD32(0x0000f000) | |
919 | #define TX_PWR_CFG_1_MCS0 FIELD32(0x000f0000) | |
920 | #define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000) | |
921 | #define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000) | |
922 | #define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000) | |
923 | ||
924 | /* | |
925 | * TX_PWR_CFG_2: | |
926 | */ | |
927 | #define TX_PWR_CFG_2 0x131c | |
928 | #define TX_PWR_CFG_2_MCS4 FIELD32(0x0000000f) | |
929 | #define TX_PWR_CFG_2_MCS5 FIELD32(0x000000f0) | |
930 | #define TX_PWR_CFG_2_MCS6 FIELD32(0x00000f00) | |
931 | #define TX_PWR_CFG_2_MCS7 FIELD32(0x0000f000) | |
932 | #define TX_PWR_CFG_2_MCS8 FIELD32(0x000f0000) | |
933 | #define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000) | |
934 | #define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000) | |
935 | #define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000) | |
936 | ||
937 | /* | |
938 | * TX_PWR_CFG_3: | |
939 | */ | |
940 | #define TX_PWR_CFG_3 0x1320 | |
941 | #define TX_PWR_CFG_3_MCS12 FIELD32(0x0000000f) | |
942 | #define TX_PWR_CFG_3_MCS13 FIELD32(0x000000f0) | |
943 | #define TX_PWR_CFG_3_MCS14 FIELD32(0x00000f00) | |
944 | #define TX_PWR_CFG_3_MCS15 FIELD32(0x0000f000) | |
945 | #define TX_PWR_CFG_3_UKNOWN1 FIELD32(0x000f0000) | |
946 | #define TX_PWR_CFG_3_UKNOWN2 FIELD32(0x00f00000) | |
947 | #define TX_PWR_CFG_3_UKNOWN3 FIELD32(0x0f000000) | |
948 | #define TX_PWR_CFG_3_UKNOWN4 FIELD32(0xf0000000) | |
949 | ||
950 | /* | |
951 | * TX_PWR_CFG_4: | |
952 | */ | |
953 | #define TX_PWR_CFG_4 0x1324 | |
954 | #define TX_PWR_CFG_4_UKNOWN5 FIELD32(0x0000000f) | |
955 | #define TX_PWR_CFG_4_UKNOWN6 FIELD32(0x000000f0) | |
956 | #define TX_PWR_CFG_4_UKNOWN7 FIELD32(0x00000f00) | |
957 | #define TX_PWR_CFG_4_UKNOWN8 FIELD32(0x0000f000) | |
958 | ||
959 | /* | |
960 | * TX_PIN_CFG: | |
961 | */ | |
962 | #define TX_PIN_CFG 0x1328 | |
963 | #define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001) | |
964 | #define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002) | |
965 | #define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004) | |
966 | #define TX_PIN_CFG_PA_PE_G1_EN FIELD32(0x00000008) | |
967 | #define TX_PIN_CFG_PA_PE_A0_POL FIELD32(0x00000010) | |
968 | #define TX_PIN_CFG_PA_PE_G0_POL FIELD32(0x00000020) | |
969 | #define TX_PIN_CFG_PA_PE_A1_POL FIELD32(0x00000040) | |
970 | #define TX_PIN_CFG_PA_PE_G1_POL FIELD32(0x00000080) | |
971 | #define TX_PIN_CFG_LNA_PE_A0_EN FIELD32(0x00000100) | |
972 | #define TX_PIN_CFG_LNA_PE_G0_EN FIELD32(0x00000200) | |
973 | #define TX_PIN_CFG_LNA_PE_A1_EN FIELD32(0x00000400) | |
974 | #define TX_PIN_CFG_LNA_PE_G1_EN FIELD32(0x00000800) | |
975 | #define TX_PIN_CFG_LNA_PE_A0_POL FIELD32(0x00001000) | |
976 | #define TX_PIN_CFG_LNA_PE_G0_POL FIELD32(0x00002000) | |
977 | #define TX_PIN_CFG_LNA_PE_A1_POL FIELD32(0x00004000) | |
978 | #define TX_PIN_CFG_LNA_PE_G1_POL FIELD32(0x00008000) | |
979 | #define TX_PIN_CFG_RFTR_EN FIELD32(0x00010000) | |
980 | #define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000) | |
981 | #define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000) | |
982 | #define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000) | |
983 | ||
984 | /* | |
985 | * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz | |
986 | */ | |
987 | #define TX_BAND_CFG 0x132c | |
a21ee724 | 988 | #define TX_BAND_CFG_HT40_MINUS FIELD32(0x00000001) |
b54f78a8 BZ |
989 | #define TX_BAND_CFG_A FIELD32(0x00000002) |
990 | #define TX_BAND_CFG_BG FIELD32(0x00000004) | |
991 | ||
992 | /* | |
993 | * TX_SW_CFG0: | |
994 | */ | |
995 | #define TX_SW_CFG0 0x1330 | |
996 | ||
997 | /* | |
998 | * TX_SW_CFG1: | |
999 | */ | |
1000 | #define TX_SW_CFG1 0x1334 | |
1001 | ||
1002 | /* | |
1003 | * TX_SW_CFG2: | |
1004 | */ | |
1005 | #define TX_SW_CFG2 0x1338 | |
1006 | ||
1007 | /* | |
1008 | * TXOP_THRES_CFG: | |
1009 | */ | |
1010 | #define TXOP_THRES_CFG 0x133c | |
1011 | ||
1012 | /* | |
1013 | * TXOP_CTRL_CFG: | |
961621ab HS |
1014 | * TIMEOUT_TRUN_EN: Enable/Disable TXOP timeout truncation |
1015 | * AC_TRUN_EN: Enable/Disable truncation for AC change | |
1016 | * TXRATEGRP_TRUN_EN: Enable/Disable truncation for TX rate group change | |
1017 | * USER_MODE_TRUN_EN: Enable/Disable truncation for user TXOP mode | |
1018 | * MIMO_PS_TRUN_EN: Enable/Disable truncation for MIMO PS RTS/CTS | |
1019 | * RESERVED_TRUN_EN: Reserved | |
1020 | * LSIG_TXOP_EN: Enable/Disable L-SIG TXOP protection | |
1021 | * EXT_CCA_EN: Enable/Disable extension channel CCA reference (Defer 40Mhz | |
1022 | * transmissions if extension CCA is clear). | |
1023 | * EXT_CCA_DLY: Extension CCA signal delay time (unit: us) | |
1024 | * EXT_CWMIN: CwMin for extension channel backoff | |
1025 | * 0: Disabled | |
1026 | * | |
b54f78a8 BZ |
1027 | */ |
1028 | #define TXOP_CTRL_CFG 0x1340 | |
961621ab HS |
1029 | #define TXOP_CTRL_CFG_TIMEOUT_TRUN_EN FIELD32(0x00000001) |
1030 | #define TXOP_CTRL_CFG_AC_TRUN_EN FIELD32(0x00000002) | |
1031 | #define TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN FIELD32(0x00000004) | |
1032 | #define TXOP_CTRL_CFG_USER_MODE_TRUN_EN FIELD32(0x00000008) | |
1033 | #define TXOP_CTRL_CFG_MIMO_PS_TRUN_EN FIELD32(0x00000010) | |
1034 | #define TXOP_CTRL_CFG_RESERVED_TRUN_EN FIELD32(0x00000020) | |
1035 | #define TXOP_CTRL_CFG_LSIG_TXOP_EN FIELD32(0x00000040) | |
1036 | #define TXOP_CTRL_CFG_EXT_CCA_EN FIELD32(0x00000080) | |
1037 | #define TXOP_CTRL_CFG_EXT_CCA_DLY FIELD32(0x0000ff00) | |
1038 | #define TXOP_CTRL_CFG_EXT_CWMIN FIELD32(0x000f0000) | |
b54f78a8 BZ |
1039 | |
1040 | /* | |
1041 | * TX_RTS_CFG: | |
1042 | * RTS_THRES: unit:byte | |
1043 | * RTS_FBK_EN: enable rts rate fallback | |
1044 | */ | |
1045 | #define TX_RTS_CFG 0x1344 | |
1046 | #define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff) | |
1047 | #define TX_RTS_CFG_RTS_THRES FIELD32(0x00ffff00) | |
1048 | #define TX_RTS_CFG_RTS_FBK_EN FIELD32(0x01000000) | |
1049 | ||
1050 | /* | |
1051 | * TX_TIMEOUT_CFG: | |
1052 | * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us | |
1053 | * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure | |
1054 | * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation. | |
1055 | * it is recommended that: | |
1056 | * (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT) | |
1057 | */ | |
1058 | #define TX_TIMEOUT_CFG 0x1348 | |
1059 | #define TX_TIMEOUT_CFG_MPDU_LIFETIME FIELD32(0x000000f0) | |
1060 | #define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT FIELD32(0x0000ff00) | |
1061 | #define TX_TIMEOUT_CFG_TX_OP_TIMEOUT FIELD32(0x00ff0000) | |
1062 | ||
1063 | /* | |
1064 | * TX_RTY_CFG: | |
1065 | * SHORT_RTY_LIMIT: short retry limit | |
1066 | * LONG_RTY_LIMIT: long retry limit | |
1067 | * LONG_RTY_THRE: Long retry threshoold | |
1068 | * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode | |
1069 | * 0:expired by retry limit, 1: expired by mpdu life timer | |
1070 | * AGG_RTY_MODE: Aggregate MPDU retry mode | |
1071 | * 0:expired by retry limit, 1: expired by mpdu life timer | |
1072 | * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable | |
1073 | */ | |
1074 | #define TX_RTY_CFG 0x134c | |
1075 | #define TX_RTY_CFG_SHORT_RTY_LIMIT FIELD32(0x000000ff) | |
1076 | #define TX_RTY_CFG_LONG_RTY_LIMIT FIELD32(0x0000ff00) | |
1077 | #define TX_RTY_CFG_LONG_RTY_THRE FIELD32(0x0fff0000) | |
1078 | #define TX_RTY_CFG_NON_AGG_RTY_MODE FIELD32(0x10000000) | |
1079 | #define TX_RTY_CFG_AGG_RTY_MODE FIELD32(0x20000000) | |
1080 | #define TX_RTY_CFG_TX_AUTO_FB_ENABLE FIELD32(0x40000000) | |
1081 | ||
1082 | /* | |
1083 | * TX_LINK_CFG: | |
1084 | * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us | |
1085 | * MFB_ENABLE: TX apply remote MFB 1:enable | |
1086 | * REMOTE_UMFS_ENABLE: remote unsolicit MFB enable | |
1087 | * 0: not apply remote remote unsolicit (MFS=7) | |
1088 | * TX_MRQ_EN: MCS request TX enable | |
1089 | * TX_RDG_EN: RDG TX enable | |
1090 | * TX_CF_ACK_EN: Piggyback CF-ACK enable | |
1091 | * REMOTE_MFB: remote MCS feedback | |
1092 | * REMOTE_MFS: remote MCS feedback sequence number | |
1093 | */ | |
1094 | #define TX_LINK_CFG 0x1350 | |
1095 | #define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff) | |
1096 | #define TX_LINK_CFG_MFB_ENABLE FIELD32(0x00000100) | |
1097 | #define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200) | |
1098 | #define TX_LINK_CFG_TX_MRQ_EN FIELD32(0x00000400) | |
1099 | #define TX_LINK_CFG_TX_RDG_EN FIELD32(0x00000800) | |
1100 | #define TX_LINK_CFG_TX_CF_ACK_EN FIELD32(0x00001000) | |
1101 | #define TX_LINK_CFG_REMOTE_MFB FIELD32(0x00ff0000) | |
1102 | #define TX_LINK_CFG_REMOTE_MFS FIELD32(0xff000000) | |
1103 | ||
1104 | /* | |
1105 | * HT_FBK_CFG0: | |
1106 | */ | |
1107 | #define HT_FBK_CFG0 0x1354 | |
1108 | #define HT_FBK_CFG0_HTMCS0FBK FIELD32(0x0000000f) | |
1109 | #define HT_FBK_CFG0_HTMCS1FBK FIELD32(0x000000f0) | |
1110 | #define HT_FBK_CFG0_HTMCS2FBK FIELD32(0x00000f00) | |
1111 | #define HT_FBK_CFG0_HTMCS3FBK FIELD32(0x0000f000) | |
1112 | #define HT_FBK_CFG0_HTMCS4FBK FIELD32(0x000f0000) | |
1113 | #define HT_FBK_CFG0_HTMCS5FBK FIELD32(0x00f00000) | |
1114 | #define HT_FBK_CFG0_HTMCS6FBK FIELD32(0x0f000000) | |
1115 | #define HT_FBK_CFG0_HTMCS7FBK FIELD32(0xf0000000) | |
1116 | ||
1117 | /* | |
1118 | * HT_FBK_CFG1: | |
1119 | */ | |
1120 | #define HT_FBK_CFG1 0x1358 | |
1121 | #define HT_FBK_CFG1_HTMCS8FBK FIELD32(0x0000000f) | |
1122 | #define HT_FBK_CFG1_HTMCS9FBK FIELD32(0x000000f0) | |
1123 | #define HT_FBK_CFG1_HTMCS10FBK FIELD32(0x00000f00) | |
1124 | #define HT_FBK_CFG1_HTMCS11FBK FIELD32(0x0000f000) | |
1125 | #define HT_FBK_CFG1_HTMCS12FBK FIELD32(0x000f0000) | |
1126 | #define HT_FBK_CFG1_HTMCS13FBK FIELD32(0x00f00000) | |
1127 | #define HT_FBK_CFG1_HTMCS14FBK FIELD32(0x0f000000) | |
1128 | #define HT_FBK_CFG1_HTMCS15FBK FIELD32(0xf0000000) | |
1129 | ||
1130 | /* | |
1131 | * LG_FBK_CFG0: | |
1132 | */ | |
1133 | #define LG_FBK_CFG0 0x135c | |
1134 | #define LG_FBK_CFG0_OFDMMCS0FBK FIELD32(0x0000000f) | |
1135 | #define LG_FBK_CFG0_OFDMMCS1FBK FIELD32(0x000000f0) | |
1136 | #define LG_FBK_CFG0_OFDMMCS2FBK FIELD32(0x00000f00) | |
1137 | #define LG_FBK_CFG0_OFDMMCS3FBK FIELD32(0x0000f000) | |
1138 | #define LG_FBK_CFG0_OFDMMCS4FBK FIELD32(0x000f0000) | |
1139 | #define LG_FBK_CFG0_OFDMMCS5FBK FIELD32(0x00f00000) | |
1140 | #define LG_FBK_CFG0_OFDMMCS6FBK FIELD32(0x0f000000) | |
1141 | #define LG_FBK_CFG0_OFDMMCS7FBK FIELD32(0xf0000000) | |
1142 | ||
1143 | /* | |
1144 | * LG_FBK_CFG1: | |
1145 | */ | |
1146 | #define LG_FBK_CFG1 0x1360 | |
1147 | #define LG_FBK_CFG0_CCKMCS0FBK FIELD32(0x0000000f) | |
1148 | #define LG_FBK_CFG0_CCKMCS1FBK FIELD32(0x000000f0) | |
1149 | #define LG_FBK_CFG0_CCKMCS2FBK FIELD32(0x00000f00) | |
1150 | #define LG_FBK_CFG0_CCKMCS3FBK FIELD32(0x0000f000) | |
1151 | ||
1152 | /* | |
1153 | * CCK_PROT_CFG: CCK Protection | |
1154 | * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd) | |
1155 | * PROTECT_CTRL: Protection control frame type for CCK TX | |
1156 | * 0:none, 1:RTS/CTS, 2:CTS-to-self | |
6f492b6d ST |
1157 | * PROTECT_NAV_SHORT: TXOP protection type for CCK TX with short NAV |
1158 | * PROTECT_NAV_LONG: TXOP protection type for CCK TX with long NAV | |
b54f78a8 BZ |
1159 | * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow |
1160 | * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow | |
1161 | * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow | |
1162 | * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow | |
1163 | * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow | |
1164 | * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow | |
1165 | * RTS_TH_EN: RTS threshold enable on CCK TX | |
1166 | */ | |
1167 | #define CCK_PROT_CFG 0x1364 | |
1168 | #define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) | |
1169 | #define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) | |
6f492b6d ST |
1170 | #define CCK_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000) |
1171 | #define CCK_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000) | |
b54f78a8 BZ |
1172 | #define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) |
1173 | #define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) | |
1174 | #define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) | |
1175 | #define CCK_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000) | |
1176 | #define CCK_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000) | |
1177 | #define CCK_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000) | |
1178 | #define CCK_PROT_CFG_RTS_TH_EN FIELD32(0x04000000) | |
1179 | ||
1180 | /* | |
1181 | * OFDM_PROT_CFG: OFDM Protection | |
1182 | */ | |
1183 | #define OFDM_PROT_CFG 0x1368 | |
1184 | #define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) | |
1185 | #define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) | |
6f492b6d ST |
1186 | #define OFDM_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000) |
1187 | #define OFDM_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000) | |
b54f78a8 BZ |
1188 | #define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) |
1189 | #define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) | |
1190 | #define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) | |
1191 | #define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000) | |
1192 | #define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000) | |
1193 | #define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000) | |
1194 | #define OFDM_PROT_CFG_RTS_TH_EN FIELD32(0x04000000) | |
1195 | ||
1196 | /* | |
1197 | * MM20_PROT_CFG: MM20 Protection | |
1198 | */ | |
1199 | #define MM20_PROT_CFG 0x136c | |
1200 | #define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) | |
1201 | #define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) | |
6f492b6d ST |
1202 | #define MM20_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000) |
1203 | #define MM20_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000) | |
b54f78a8 BZ |
1204 | #define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) |
1205 | #define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) | |
1206 | #define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) | |
1207 | #define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000) | |
1208 | #define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000) | |
1209 | #define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000) | |
1210 | #define MM20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000) | |
1211 | ||
1212 | /* | |
1213 | * MM40_PROT_CFG: MM40 Protection | |
1214 | */ | |
1215 | #define MM40_PROT_CFG 0x1370 | |
1216 | #define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) | |
1217 | #define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) | |
6f492b6d ST |
1218 | #define MM40_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000) |
1219 | #define MM40_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000) | |
b54f78a8 BZ |
1220 | #define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) |
1221 | #define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) | |
1222 | #define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) | |
1223 | #define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000) | |
1224 | #define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000) | |
1225 | #define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000) | |
1226 | #define MM40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000) | |
1227 | ||
1228 | /* | |
1229 | * GF20_PROT_CFG: GF20 Protection | |
1230 | */ | |
1231 | #define GF20_PROT_CFG 0x1374 | |
1232 | #define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) | |
1233 | #define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) | |
6f492b6d ST |
1234 | #define GF20_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000) |
1235 | #define GF20_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000) | |
b54f78a8 BZ |
1236 | #define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) |
1237 | #define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) | |
1238 | #define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) | |
1239 | #define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000) | |
1240 | #define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000) | |
1241 | #define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000) | |
1242 | #define GF20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000) | |
1243 | ||
1244 | /* | |
1245 | * GF40_PROT_CFG: GF40 Protection | |
1246 | */ | |
1247 | #define GF40_PROT_CFG 0x1378 | |
1248 | #define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) | |
1249 | #define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) | |
6f492b6d ST |
1250 | #define GF40_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000) |
1251 | #define GF40_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000) | |
b54f78a8 BZ |
1252 | #define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) |
1253 | #define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) | |
1254 | #define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) | |
1255 | #define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000) | |
1256 | #define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000) | |
1257 | #define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000) | |
1258 | #define GF40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000) | |
1259 | ||
1260 | /* | |
1261 | * EXP_CTS_TIME: | |
1262 | */ | |
1263 | #define EXP_CTS_TIME 0x137c | |
1264 | ||
1265 | /* | |
1266 | * EXP_ACK_TIME: | |
1267 | */ | |
1268 | #define EXP_ACK_TIME 0x1380 | |
1269 | ||
1270 | /* | |
1271 | * RX_FILTER_CFG: RX configuration register. | |
1272 | */ | |
1273 | #define RX_FILTER_CFG 0x1400 | |
1274 | #define RX_FILTER_CFG_DROP_CRC_ERROR FIELD32(0x00000001) | |
1275 | #define RX_FILTER_CFG_DROP_PHY_ERROR FIELD32(0x00000002) | |
1276 | #define RX_FILTER_CFG_DROP_NOT_TO_ME FIELD32(0x00000004) | |
1277 | #define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008) | |
1278 | #define RX_FILTER_CFG_DROP_VER_ERROR FIELD32(0x00000010) | |
1279 | #define RX_FILTER_CFG_DROP_MULTICAST FIELD32(0x00000020) | |
1280 | #define RX_FILTER_CFG_DROP_BROADCAST FIELD32(0x00000040) | |
1281 | #define RX_FILTER_CFG_DROP_DUPLICATE FIELD32(0x00000080) | |
1282 | #define RX_FILTER_CFG_DROP_CF_END_ACK FIELD32(0x00000100) | |
1283 | #define RX_FILTER_CFG_DROP_CF_END FIELD32(0x00000200) | |
1284 | #define RX_FILTER_CFG_DROP_ACK FIELD32(0x00000400) | |
1285 | #define RX_FILTER_CFG_DROP_CTS FIELD32(0x00000800) | |
1286 | #define RX_FILTER_CFG_DROP_RTS FIELD32(0x00001000) | |
1287 | #define RX_FILTER_CFG_DROP_PSPOLL FIELD32(0x00002000) | |
1288 | #define RX_FILTER_CFG_DROP_BA FIELD32(0x00004000) | |
1289 | #define RX_FILTER_CFG_DROP_BAR FIELD32(0x00008000) | |
1290 | #define RX_FILTER_CFG_DROP_CNTL FIELD32(0x00010000) | |
1291 | ||
1292 | /* | |
1293 | * AUTO_RSP_CFG: | |
1294 | * AUTORESPONDER: 0: disable, 1: enable | |
1295 | * BAC_ACK_POLICY: 0:long, 1:short preamble | |
1296 | * CTS_40_MMODE: Response CTS 40MHz duplicate mode | |
1297 | * CTS_40_MREF: Response CTS 40MHz duplicate mode | |
1298 | * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble | |
1299 | * DUAL_CTS_EN: Power bit value in control frame | |
1300 | * ACK_CTS_PSM_BIT:Power bit value in control frame | |
1301 | */ | |
1302 | #define AUTO_RSP_CFG 0x1404 | |
1303 | #define AUTO_RSP_CFG_AUTORESPONDER FIELD32(0x00000001) | |
1304 | #define AUTO_RSP_CFG_BAC_ACK_POLICY FIELD32(0x00000002) | |
1305 | #define AUTO_RSP_CFG_CTS_40_MMODE FIELD32(0x00000004) | |
1306 | #define AUTO_RSP_CFG_CTS_40_MREF FIELD32(0x00000008) | |
1307 | #define AUTO_RSP_CFG_AR_PREAMBLE FIELD32(0x00000010) | |
1308 | #define AUTO_RSP_CFG_DUAL_CTS_EN FIELD32(0x00000040) | |
1309 | #define AUTO_RSP_CFG_ACK_CTS_PSM_BIT FIELD32(0x00000080) | |
1310 | ||
1311 | /* | |
1312 | * LEGACY_BASIC_RATE: | |
1313 | */ | |
1314 | #define LEGACY_BASIC_RATE 0x1408 | |
1315 | ||
1316 | /* | |
1317 | * HT_BASIC_RATE: | |
1318 | */ | |
1319 | #define HT_BASIC_RATE 0x140c | |
1320 | ||
1321 | /* | |
1322 | * HT_CTRL_CFG: | |
1323 | */ | |
1324 | #define HT_CTRL_CFG 0x1410 | |
1325 | ||
1326 | /* | |
1327 | * SIFS_COST_CFG: | |
1328 | */ | |
1329 | #define SIFS_COST_CFG 0x1414 | |
1330 | ||
1331 | /* | |
1332 | * RX_PARSER_CFG: | |
1333 | * Set NAV for all received frames | |
1334 | */ | |
1335 | #define RX_PARSER_CFG 0x1418 | |
1336 | ||
1337 | /* | |
1338 | * TX_SEC_CNT0: | |
1339 | */ | |
1340 | #define TX_SEC_CNT0 0x1500 | |
1341 | ||
1342 | /* | |
1343 | * RX_SEC_CNT0: | |
1344 | */ | |
1345 | #define RX_SEC_CNT0 0x1504 | |
1346 | ||
1347 | /* | |
1348 | * CCMP_FC_MUTE: | |
1349 | */ | |
1350 | #define CCMP_FC_MUTE 0x1508 | |
1351 | ||
1352 | /* | |
1353 | * TXOP_HLDR_ADDR0: | |
1354 | */ | |
1355 | #define TXOP_HLDR_ADDR0 0x1600 | |
1356 | ||
1357 | /* | |
1358 | * TXOP_HLDR_ADDR1: | |
1359 | */ | |
1360 | #define TXOP_HLDR_ADDR1 0x1604 | |
1361 | ||
1362 | /* | |
1363 | * TXOP_HLDR_ET: | |
1364 | */ | |
1365 | #define TXOP_HLDR_ET 0x1608 | |
1366 | ||
1367 | /* | |
1368 | * QOS_CFPOLL_RA_DW0: | |
1369 | */ | |
1370 | #define QOS_CFPOLL_RA_DW0 0x160c | |
1371 | ||
1372 | /* | |
1373 | * QOS_CFPOLL_RA_DW1: | |
1374 | */ | |
1375 | #define QOS_CFPOLL_RA_DW1 0x1610 | |
1376 | ||
1377 | /* | |
1378 | * QOS_CFPOLL_QC: | |
1379 | */ | |
1380 | #define QOS_CFPOLL_QC 0x1614 | |
1381 | ||
1382 | /* | |
1383 | * RX_STA_CNT0: RX PLCP error count & RX CRC error count | |
1384 | */ | |
1385 | #define RX_STA_CNT0 0x1700 | |
1386 | #define RX_STA_CNT0_CRC_ERR FIELD32(0x0000ffff) | |
1387 | #define RX_STA_CNT0_PHY_ERR FIELD32(0xffff0000) | |
1388 | ||
1389 | /* | |
1390 | * RX_STA_CNT1: RX False CCA count & RX LONG frame count | |
1391 | */ | |
1392 | #define RX_STA_CNT1 0x1704 | |
1393 | #define RX_STA_CNT1_FALSE_CCA FIELD32(0x0000ffff) | |
1394 | #define RX_STA_CNT1_PLCP_ERR FIELD32(0xffff0000) | |
1395 | ||
1396 | /* | |
1397 | * RX_STA_CNT2: | |
1398 | */ | |
1399 | #define RX_STA_CNT2 0x1708 | |
1400 | #define RX_STA_CNT2_RX_DUPLI_COUNT FIELD32(0x0000ffff) | |
1401 | #define RX_STA_CNT2_RX_FIFO_OVERFLOW FIELD32(0xffff0000) | |
1402 | ||
1403 | /* | |
1404 | * TX_STA_CNT0: TX Beacon count | |
1405 | */ | |
1406 | #define TX_STA_CNT0 0x170c | |
1407 | #define TX_STA_CNT0_TX_FAIL_COUNT FIELD32(0x0000ffff) | |
1408 | #define TX_STA_CNT0_TX_BEACON_COUNT FIELD32(0xffff0000) | |
1409 | ||
1410 | /* | |
1411 | * TX_STA_CNT1: TX tx count | |
1412 | */ | |
1413 | #define TX_STA_CNT1 0x1710 | |
1414 | #define TX_STA_CNT1_TX_SUCCESS FIELD32(0x0000ffff) | |
1415 | #define TX_STA_CNT1_TX_RETRANSMIT FIELD32(0xffff0000) | |
1416 | ||
1417 | /* | |
1418 | * TX_STA_CNT2: TX tx count | |
1419 | */ | |
1420 | #define TX_STA_CNT2 0x1714 | |
1421 | #define TX_STA_CNT2_TX_ZERO_LEN_COUNT FIELD32(0x0000ffff) | |
1422 | #define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000) | |
1423 | ||
1424 | /* | |
0856d9c0 HS |
1425 | * TX_STA_FIFO: TX Result for specific PID status fifo register. |
1426 | * | |
1427 | * This register is implemented as FIFO with 16 entries in the HW. Each | |
1428 | * register read fetches the next tx result. If the FIFO is full because | |
1429 | * it wasn't read fast enough after the according interrupt (TX_FIFO_STATUS) | |
1430 | * triggered, the hw seems to simply drop further tx results. | |
1431 | * | |
1432 | * VALID: 1: this tx result is valid | |
1433 | * 0: no valid tx result -> driver should stop reading | |
1434 | * PID_TYPE: The PID latched from the PID field in the TXWI, can be used | |
1435 | * to match a frame with its tx result (even though the PID is | |
1436 | * only 4 bits wide). | |
bc8a979e ID |
1437 | * PID_QUEUE: Part of PID_TYPE, this is the queue index number (0-3) |
1438 | * PID_ENTRY: Part of PID_TYPE, this is the queue entry index number (1-3) | |
1439 | * This identification number is calculated by ((idx % 3) + 1). | |
0856d9c0 HS |
1440 | * TX_SUCCESS: Indicates tx success (1) or failure (0) |
1441 | * TX_AGGRE: Indicates if the frame was part of an aggregate (1) or not (0) | |
1442 | * TX_ACK_REQUIRED: Indicates if the frame needed to get ack'ed (1) or not (0) | |
1443 | * WCID: The wireless client ID. | |
1444 | * MCS: The tx rate used during the last transmission of this frame, be it | |
1445 | * successful or not. | |
1446 | * PHYMODE: The phymode used for the transmission. | |
b54f78a8 BZ |
1447 | */ |
1448 | #define TX_STA_FIFO 0x1718 | |
1449 | #define TX_STA_FIFO_VALID FIELD32(0x00000001) | |
1450 | #define TX_STA_FIFO_PID_TYPE FIELD32(0x0000001e) | |
bc8a979e ID |
1451 | #define TX_STA_FIFO_PID_QUEUE FIELD32(0x00000006) |
1452 | #define TX_STA_FIFO_PID_ENTRY FIELD32(0x00000018) | |
b54f78a8 BZ |
1453 | #define TX_STA_FIFO_TX_SUCCESS FIELD32(0x00000020) |
1454 | #define TX_STA_FIFO_TX_AGGRE FIELD32(0x00000040) | |
1455 | #define TX_STA_FIFO_TX_ACK_REQUIRED FIELD32(0x00000080) | |
1456 | #define TX_STA_FIFO_WCID FIELD32(0x0000ff00) | |
1457 | #define TX_STA_FIFO_SUCCESS_RATE FIELD32(0xffff0000) | |
1458 | #define TX_STA_FIFO_MCS FIELD32(0x007f0000) | |
1459 | #define TX_STA_FIFO_PHYMODE FIELD32(0xc0000000) | |
1460 | ||
1461 | /* | |
1462 | * TX_AGG_CNT: Debug counter | |
1463 | */ | |
1464 | #define TX_AGG_CNT 0x171c | |
1465 | #define TX_AGG_CNT_NON_AGG_TX_COUNT FIELD32(0x0000ffff) | |
1466 | #define TX_AGG_CNT_AGG_TX_COUNT FIELD32(0xffff0000) | |
1467 | ||
1468 | /* | |
1469 | * TX_AGG_CNT0: | |
1470 | */ | |
1471 | #define TX_AGG_CNT0 0x1720 | |
1472 | #define TX_AGG_CNT0_AGG_SIZE_1_COUNT FIELD32(0x0000ffff) | |
1473 | #define TX_AGG_CNT0_AGG_SIZE_2_COUNT FIELD32(0xffff0000) | |
1474 | ||
1475 | /* | |
1476 | * TX_AGG_CNT1: | |
1477 | */ | |
1478 | #define TX_AGG_CNT1 0x1724 | |
1479 | #define TX_AGG_CNT1_AGG_SIZE_3_COUNT FIELD32(0x0000ffff) | |
1480 | #define TX_AGG_CNT1_AGG_SIZE_4_COUNT FIELD32(0xffff0000) | |
1481 | ||
1482 | /* | |
1483 | * TX_AGG_CNT2: | |
1484 | */ | |
1485 | #define TX_AGG_CNT2 0x1728 | |
1486 | #define TX_AGG_CNT2_AGG_SIZE_5_COUNT FIELD32(0x0000ffff) | |
1487 | #define TX_AGG_CNT2_AGG_SIZE_6_COUNT FIELD32(0xffff0000) | |
1488 | ||
1489 | /* | |
1490 | * TX_AGG_CNT3: | |
1491 | */ | |
1492 | #define TX_AGG_CNT3 0x172c | |
1493 | #define TX_AGG_CNT3_AGG_SIZE_7_COUNT FIELD32(0x0000ffff) | |
1494 | #define TX_AGG_CNT3_AGG_SIZE_8_COUNT FIELD32(0xffff0000) | |
1495 | ||
1496 | /* | |
1497 | * TX_AGG_CNT4: | |
1498 | */ | |
1499 | #define TX_AGG_CNT4 0x1730 | |
1500 | #define TX_AGG_CNT4_AGG_SIZE_9_COUNT FIELD32(0x0000ffff) | |
1501 | #define TX_AGG_CNT4_AGG_SIZE_10_COUNT FIELD32(0xffff0000) | |
1502 | ||
1503 | /* | |
1504 | * TX_AGG_CNT5: | |
1505 | */ | |
1506 | #define TX_AGG_CNT5 0x1734 | |
1507 | #define TX_AGG_CNT5_AGG_SIZE_11_COUNT FIELD32(0x0000ffff) | |
1508 | #define TX_AGG_CNT5_AGG_SIZE_12_COUNT FIELD32(0xffff0000) | |
1509 | ||
1510 | /* | |
1511 | * TX_AGG_CNT6: | |
1512 | */ | |
1513 | #define TX_AGG_CNT6 0x1738 | |
1514 | #define TX_AGG_CNT6_AGG_SIZE_13_COUNT FIELD32(0x0000ffff) | |
1515 | #define TX_AGG_CNT6_AGG_SIZE_14_COUNT FIELD32(0xffff0000) | |
1516 | ||
1517 | /* | |
1518 | * TX_AGG_CNT7: | |
1519 | */ | |
1520 | #define TX_AGG_CNT7 0x173c | |
1521 | #define TX_AGG_CNT7_AGG_SIZE_15_COUNT FIELD32(0x0000ffff) | |
1522 | #define TX_AGG_CNT7_AGG_SIZE_16_COUNT FIELD32(0xffff0000) | |
1523 | ||
1524 | /* | |
1525 | * MPDU_DENSITY_CNT: | |
1526 | * TX_ZERO_DEL: TX zero length delimiter count | |
1527 | * RX_ZERO_DEL: RX zero length delimiter count | |
1528 | */ | |
1529 | #define MPDU_DENSITY_CNT 0x1740 | |
1530 | #define MPDU_DENSITY_CNT_TX_ZERO_DEL FIELD32(0x0000ffff) | |
1531 | #define MPDU_DENSITY_CNT_RX_ZERO_DEL FIELD32(0xffff0000) | |
1532 | ||
1533 | /* | |
1534 | * Security key table memory. | |
2a0cfeb8 HS |
1535 | * |
1536 | * The pairwise key table shares some memory with the beacon frame | |
1537 | * buffers 6 and 7. That basically means that when beacon 6 & 7 | |
1538 | * are used we should only use the reduced pairwise key table which | |
1539 | * has a maximum of 222 entries. | |
1540 | * | |
1541 | * --------------------------------------------- | |
1542 | * |0x4000 | Pairwise Key | Reduced Pairwise | | |
1543 | * | | Table | Key Table | | |
1544 | * | | Size: 256 * 32 | Size: 222 * 32 | | |
1545 | * |0x5BC0 | |------------------- | |
1546 | * | | | Beacon 6 | | |
1547 | * |0x5DC0 | |------------------- | |
1548 | * | | | Beacon 7 | | |
1549 | * |0x5FC0 | |------------------- | |
1550 | * |0x5FFF | | | |
1551 | * -------------------------- | |
1552 | * | |
b54f78a8 BZ |
1553 | * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry |
1554 | * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry | |
1555 | * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry | |
1556 | * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry | |
a4385213 BZ |
1557 | * SHARED_KEY_TABLE_BASE: 32-byte * 16-entry |
1558 | * SHARED_KEY_MODE_BASE: 4-byte * 16-entry | |
b54f78a8 BZ |
1559 | */ |
1560 | #define MAC_WCID_BASE 0x1800 | |
1561 | #define PAIRWISE_KEY_TABLE_BASE 0x4000 | |
1562 | #define MAC_IVEIV_TABLE_BASE 0x6000 | |
1563 | #define MAC_WCID_ATTRIBUTE_BASE 0x6800 | |
1564 | #define SHARED_KEY_TABLE_BASE 0x6c00 | |
1565 | #define SHARED_KEY_MODE_BASE 0x7000 | |
1566 | ||
1567 | #define MAC_WCID_ENTRY(__idx) \ | |
fd8dab9a | 1568 | (MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry))) |
b54f78a8 | 1569 | #define PAIRWISE_KEY_ENTRY(__idx) \ |
fd8dab9a | 1570 | (PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry))) |
b54f78a8 | 1571 | #define MAC_IVEIV_ENTRY(__idx) \ |
fd8dab9a | 1572 | (MAC_IVEIV_TABLE_BASE + ((__idx) * sizeof(struct mac_iveiv_entry))) |
b54f78a8 | 1573 | #define MAC_WCID_ATTR_ENTRY(__idx) \ |
fd8dab9a | 1574 | (MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32))) |
b54f78a8 | 1575 | #define SHARED_KEY_ENTRY(__idx) \ |
fd8dab9a | 1576 | (SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry))) |
b54f78a8 | 1577 | #define SHARED_KEY_MODE_ENTRY(__idx) \ |
fd8dab9a | 1578 | (SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32))) |
b54f78a8 BZ |
1579 | |
1580 | struct mac_wcid_entry { | |
1581 | u8 mac[6]; | |
1582 | u8 reserved[2]; | |
ba2d3587 | 1583 | } __packed; |
b54f78a8 BZ |
1584 | |
1585 | struct hw_key_entry { | |
1586 | u8 key[16]; | |
1587 | u8 tx_mic[8]; | |
1588 | u8 rx_mic[8]; | |
ba2d3587 | 1589 | } __packed; |
b54f78a8 BZ |
1590 | |
1591 | struct mac_iveiv_entry { | |
1592 | u8 iv[8]; | |
ba2d3587 | 1593 | } __packed; |
b54f78a8 BZ |
1594 | |
1595 | /* | |
1596 | * MAC_WCID_ATTRIBUTE: | |
1597 | */ | |
1598 | #define MAC_WCID_ATTRIBUTE_KEYTAB FIELD32(0x00000001) | |
1599 | #define MAC_WCID_ATTRIBUTE_CIPHER FIELD32(0x0000000e) | |
1600 | #define MAC_WCID_ATTRIBUTE_BSS_IDX FIELD32(0x00000070) | |
1601 | #define MAC_WCID_ATTRIBUTE_RX_WIUDF FIELD32(0x00000380) | |
e4a0ab34 ID |
1602 | #define MAC_WCID_ATTRIBUTE_CIPHER_EXT FIELD32(0x00000400) |
1603 | #define MAC_WCID_ATTRIBUTE_BSS_IDX_EXT FIELD32(0x00000800) | |
1604 | #define MAC_WCID_ATTRIBUTE_WAPI_MCBC FIELD32(0x00008000) | |
1605 | #define MAC_WCID_ATTRIBUTE_WAPI_KEY_IDX FIELD32(0xff000000) | |
b54f78a8 BZ |
1606 | |
1607 | /* | |
1608 | * SHARED_KEY_MODE: | |
1609 | */ | |
1610 | #define SHARED_KEY_MODE_BSS0_KEY0 FIELD32(0x00000007) | |
1611 | #define SHARED_KEY_MODE_BSS0_KEY1 FIELD32(0x00000070) | |
1612 | #define SHARED_KEY_MODE_BSS0_KEY2 FIELD32(0x00000700) | |
1613 | #define SHARED_KEY_MODE_BSS0_KEY3 FIELD32(0x00007000) | |
1614 | #define SHARED_KEY_MODE_BSS1_KEY0 FIELD32(0x00070000) | |
1615 | #define SHARED_KEY_MODE_BSS1_KEY1 FIELD32(0x00700000) | |
1616 | #define SHARED_KEY_MODE_BSS1_KEY2 FIELD32(0x07000000) | |
1617 | #define SHARED_KEY_MODE_BSS1_KEY3 FIELD32(0x70000000) | |
1618 | ||
1619 | /* | |
1620 | * HOST-MCU communication | |
1621 | */ | |
1622 | ||
1623 | /* | |
1624 | * H2M_MAILBOX_CSR: Host-to-MCU Mailbox. | |
1625 | */ | |
1626 | #define H2M_MAILBOX_CSR 0x7010 | |
1627 | #define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff) | |
1628 | #define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00) | |
1629 | #define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000) | |
1630 | #define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000) | |
1631 | ||
1632 | /* | |
1633 | * H2M_MAILBOX_CID: | |
1634 | */ | |
1635 | #define H2M_MAILBOX_CID 0x7014 | |
1636 | #define H2M_MAILBOX_CID_CMD0 FIELD32(0x000000ff) | |
1637 | #define H2M_MAILBOX_CID_CMD1 FIELD32(0x0000ff00) | |
1638 | #define H2M_MAILBOX_CID_CMD2 FIELD32(0x00ff0000) | |
1639 | #define H2M_MAILBOX_CID_CMD3 FIELD32(0xff000000) | |
1640 | ||
1641 | /* | |
1642 | * H2M_MAILBOX_STATUS: | |
1643 | */ | |
1644 | #define H2M_MAILBOX_STATUS 0x701c | |
1645 | ||
1646 | /* | |
1647 | * H2M_INT_SRC: | |
1648 | */ | |
1649 | #define H2M_INT_SRC 0x7024 | |
1650 | ||
1651 | /* | |
1652 | * H2M_BBP_AGENT: | |
1653 | */ | |
1654 | #define H2M_BBP_AGENT 0x7028 | |
1655 | ||
1656 | /* | |
1657 | * MCU_LEDCS: LED control for MCU Mailbox. | |
1658 | */ | |
1659 | #define MCU_LEDCS_LED_MODE FIELD8(0x1f) | |
1660 | #define MCU_LEDCS_POLARITY FIELD8(0x01) | |
1661 | ||
1662 | /* | |
1663 | * HW_CS_CTS_BASE: | |
1664 | * Carrier-sense CTS frame base address. | |
1665 | * It's where mac stores carrier-sense frame for carrier-sense function. | |
1666 | */ | |
1667 | #define HW_CS_CTS_BASE 0x7700 | |
1668 | ||
1669 | /* | |
1670 | * HW_DFS_CTS_BASE: | |
a4385213 | 1671 | * DFS CTS frame base address. It's where mac stores CTS frame for DFS. |
b54f78a8 BZ |
1672 | */ |
1673 | #define HW_DFS_CTS_BASE 0x7780 | |
1674 | ||
1675 | /* | |
1676 | * TXRX control registers - base address 0x3000 | |
1677 | */ | |
1678 | ||
1679 | /* | |
1680 | * TXRX_CSR1: | |
1681 | * rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first.. | |
1682 | */ | |
1683 | #define TXRX_CSR1 0x77d0 | |
1684 | ||
1685 | /* | |
1686 | * HW_DEBUG_SETTING_BASE: | |
1687 | * since NULL frame won't be that long (256 byte) | |
1688 | * We steal 16 tail bytes to save debugging settings | |
1689 | */ | |
1690 | #define HW_DEBUG_SETTING_BASE 0x77f0 | |
1691 | #define HW_DEBUG_SETTING_BASE2 0x7770 | |
1692 | ||
1693 | /* | |
1694 | * HW_BEACON_BASE | |
1695 | * In order to support maximum 8 MBSS and its maximum length | |
1696 | * is 512 bytes for each beacon | |
1697 | * Three section discontinue memory segments will be used. | |
1698 | * 1. The original region for BCN 0~3 | |
1699 | * 2. Extract memory from FCE table for BCN 4~5 | |
1700 | * 3. Extract memory from Pair-wise key table for BCN 6~7 | |
1701 | * It occupied those memory of wcid 238~253 for BCN 6 | |
2a0cfeb8 HS |
1702 | * and wcid 222~237 for BCN 7 (see Security key table memory |
1703 | * for more info). | |
b54f78a8 BZ |
1704 | * |
1705 | * IMPORTANT NOTE: Not sure why legacy driver does this, | |
1706 | * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6. | |
1707 | */ | |
1708 | #define HW_BEACON_BASE0 0x7800 | |
1709 | #define HW_BEACON_BASE1 0x7a00 | |
1710 | #define HW_BEACON_BASE2 0x7c00 | |
1711 | #define HW_BEACON_BASE3 0x7e00 | |
1712 | #define HW_BEACON_BASE4 0x7200 | |
1713 | #define HW_BEACON_BASE5 0x7400 | |
1714 | #define HW_BEACON_BASE6 0x5dc0 | |
1715 | #define HW_BEACON_BASE7 0x5bc0 | |
1716 | ||
1717 | #define HW_BEACON_OFFSET(__index) \ | |
fd8dab9a ME |
1718 | (((__index) < 4) ? (HW_BEACON_BASE0 + (__index * 0x0200)) : \ |
1719 | (((__index) < 6) ? (HW_BEACON_BASE4 + ((__index - 4) * 0x0200)) : \ | |
1720 | (HW_BEACON_BASE6 - ((__index - 6) * 0x0200)))) | |
b54f78a8 BZ |
1721 | |
1722 | /* | |
1723 | * BBP registers. | |
1724 | * The wordsize of the BBP is 8 bits. | |
1725 | */ | |
1726 | ||
1727 | /* | |
e90c54b2 RJH |
1728 | * BBP 1: TX Antenna & Power Control |
1729 | * POWER_CTRL: | |
1730 | * 0 - normal, | |
1731 | * 1 - drop tx power by 6dBm, | |
1732 | * 2 - drop tx power by 12dBm, | |
1733 | * 3 - increase tx power by 6dBm | |
1734 | */ | |
1735 | #define BBP1_TX_POWER_CTRL FIELD8(0x07) | |
b54f78a8 BZ |
1736 | #define BBP1_TX_ANTENNA FIELD8(0x18) |
1737 | ||
1738 | /* | |
1739 | * BBP 3: RX Antenna | |
1740 | */ | |
1741 | #define BBP3_RX_ANTENNA FIELD8(0x18) | |
a21ee724 | 1742 | #define BBP3_HT40_MINUS FIELD8(0x20) |
b54f78a8 BZ |
1743 | |
1744 | /* | |
1745 | * BBP 4: Bandwidth | |
1746 | */ | |
1747 | #define BBP4_TX_BF FIELD8(0x01) | |
1748 | #define BBP4_BANDWIDTH FIELD8(0x18) | |
60687ba7 RST |
1749 | #define BBP4_MAC_IF_CTRL FIELD8(0x40) |
1750 | ||
1751 | /* | |
1752 | * BBP 109 | |
1753 | */ | |
1754 | #define BBP109_TX0_POWER FIELD8(0x0f) | |
1755 | #define BBP109_TX1_POWER FIELD8(0xf0) | |
b54f78a8 | 1756 | |
fab799c3 GW |
1757 | /* |
1758 | * BBP 138: Unknown | |
1759 | */ | |
1760 | #define BBP138_RX_ADC1 FIELD8(0x02) | |
1761 | #define BBP138_RX_ADC2 FIELD8(0x04) | |
1762 | #define BBP138_TX_DAC1 FIELD8(0x20) | |
1763 | #define BBP138_TX_DAC2 FIELD8(0x40) | |
1764 | ||
60687ba7 RST |
1765 | /* |
1766 | * BBP 152: Rx Ant | |
1767 | */ | |
1768 | #define BBP152_RX_DEFAULT_ANT FIELD8(0x80) | |
1769 | ||
b54f78a8 BZ |
1770 | /* |
1771 | * RFCSR registers | |
1772 | * The wordsize of the RFCSR is 8 bits. | |
1773 | */ | |
1774 | ||
e148b4c8 GW |
1775 | /* |
1776 | * RFCSR 1: | |
1777 | */ | |
1778 | #define RFCSR1_RF_BLOCK_EN FIELD8(0x01) | |
60687ba7 | 1779 | #define RFCSR1_PLL_PD FIELD8(0x02) |
e148b4c8 GW |
1780 | #define RFCSR1_RX0_PD FIELD8(0x04) |
1781 | #define RFCSR1_TX0_PD FIELD8(0x08) | |
1782 | #define RFCSR1_RX1_PD FIELD8(0x10) | |
1783 | #define RFCSR1_TX1_PD FIELD8(0x20) | |
1784 | ||
60687ba7 RST |
1785 | /* |
1786 | * RFCSR 2: | |
1787 | */ | |
1788 | #define RFCSR2_RESCAL_EN FIELD8(0x80) | |
1789 | ||
b54f78a8 BZ |
1790 | /* |
1791 | * RFCSR 6: | |
1792 | */ | |
fab799c3 GW |
1793 | #define RFCSR6_R1 FIELD8(0x03) |
1794 | #define RFCSR6_R2 FIELD8(0x40) | |
b54f78a8 BZ |
1795 | |
1796 | /* | |
1797 | * RFCSR 7: | |
1798 | */ | |
1799 | #define RFCSR7_RF_TUNING FIELD8(0x01) | |
1800 | ||
60687ba7 RST |
1801 | /* |
1802 | * RFCSR 11: | |
1803 | */ | |
1804 | #define RFCSR11_R FIELD8(0x03) | |
1805 | ||
b54f78a8 BZ |
1806 | /* |
1807 | * RFCSR 12: | |
1808 | */ | |
1809 | #define RFCSR12_TX_POWER FIELD8(0x1f) | |
1810 | ||
5a673964 HS |
1811 | /* |
1812 | * RFCSR 13: | |
1813 | */ | |
1814 | #define RFCSR13_TX_POWER FIELD8(0x1f) | |
1815 | ||
e148b4c8 GW |
1816 | /* |
1817 | * RFCSR 15: | |
1818 | */ | |
1819 | #define RFCSR15_TX_LO2_EN FIELD8(0x08) | |
1820 | ||
fab799c3 GW |
1821 | /* |
1822 | * RFCSR 17: | |
1823 | */ | |
e148b4c8 GW |
1824 | #define RFCSR17_TXMIXER_GAIN FIELD8(0x07) |
1825 | #define RFCSR17_TX_LO1_EN FIELD8(0x08) | |
1826 | #define RFCSR17_R FIELD8(0x20) | |
60687ba7 | 1827 | #define RFCSR17_CODE FIELD8(0x7f) |
fab799c3 | 1828 | |
e148b4c8 GW |
1829 | /* |
1830 | * RFCSR 20: | |
1831 | */ | |
1832 | #define RFCSR20_RX_LO1_EN FIELD8(0x08) | |
1833 | ||
1834 | /* | |
1835 | * RFCSR 21: | |
1836 | */ | |
1837 | #define RFCSR21_RX_LO2_EN FIELD8(0x08) | |
fab799c3 | 1838 | |
b54f78a8 BZ |
1839 | /* |
1840 | * RFCSR 22: | |
1841 | */ | |
1842 | #define RFCSR22_BASEBAND_LOOPBACK FIELD8(0x01) | |
1843 | ||
1844 | /* | |
1845 | * RFCSR 23: | |
1846 | */ | |
1847 | #define RFCSR23_FREQ_OFFSET FIELD8(0x7f) | |
1848 | ||
e148b4c8 GW |
1849 | /* |
1850 | * RFCSR 27: | |
1851 | */ | |
1852 | #define RFCSR27_R1 FIELD8(0x03) | |
1853 | #define RFCSR27_R2 FIELD8(0x04) | |
1854 | #define RFCSR27_R3 FIELD8(0x30) | |
1855 | #define RFCSR27_R4 FIELD8(0x40) | |
1856 | ||
b54f78a8 BZ |
1857 | /* |
1858 | * RFCSR 30: | |
1859 | */ | |
60687ba7 RST |
1860 | #define RFCSR30_TX_H20M FIELD8(0x02) |
1861 | #define RFCSR30_RX_H20M FIELD8(0x04) | |
1862 | #define RFCSR30_RX_VCM FIELD8(0x18) | |
b54f78a8 BZ |
1863 | #define RFCSR30_RF_CALIBRATION FIELD8(0x80) |
1864 | ||
80d184e6 RJH |
1865 | /* |
1866 | * RFCSR 31: | |
1867 | */ | |
1868 | #define RFCSR31_RX_AGC_FC FIELD8(0x1f) | |
1869 | #define RFCSR31_RX_H20M FIELD8(0x20) | |
1870 | ||
60687ba7 RST |
1871 | /* |
1872 | * RFCSR 38: | |
1873 | */ | |
1874 | #define RFCSR38_RX_LO1_EN FIELD8(0x20) | |
1875 | ||
1876 | /* | |
1877 | * RFCSR 39: | |
1878 | */ | |
1879 | #define RFCSR39_RX_LO2_EN FIELD8(0x80) | |
1880 | ||
1881 | /* | |
1882 | * RFCSR 49: | |
1883 | */ | |
1884 | #define RFCSR49_TX FIELD8(0x3f) | |
1885 | ||
b54f78a8 BZ |
1886 | /* |
1887 | * RF registers | |
1888 | */ | |
1889 | ||
1890 | /* | |
1891 | * RF 2 | |
1892 | */ | |
1893 | #define RF2_ANTENNA_RX2 FIELD32(0x00000040) | |
1894 | #define RF2_ANTENNA_TX1 FIELD32(0x00004000) | |
1895 | #define RF2_ANTENNA_RX1 FIELD32(0x00020000) | |
1896 | ||
1897 | /* | |
1898 | * RF 3 | |
1899 | */ | |
1900 | #define RF3_TXPOWER_G FIELD32(0x00003e00) | |
1901 | #define RF3_TXPOWER_A_7DBM_BOOST FIELD32(0x00000200) | |
1902 | #define RF3_TXPOWER_A FIELD32(0x00003c00) | |
1903 | ||
1904 | /* | |
1905 | * RF 4 | |
1906 | */ | |
1907 | #define RF4_TXPOWER_G FIELD32(0x000007c0) | |
1908 | #define RF4_TXPOWER_A_7DBM_BOOST FIELD32(0x00000040) | |
1909 | #define RF4_TXPOWER_A FIELD32(0x00000780) | |
1910 | #define RF4_FREQ_OFFSET FIELD32(0x001f8000) | |
1911 | #define RF4_HT40 FIELD32(0x00200000) | |
1912 | ||
1913 | /* | |
1914 | * EEPROM content. | |
1915 | * The wordsize of the EEPROM is 16 bits. | |
1916 | */ | |
1917 | ||
60687ba7 RST |
1918 | /* |
1919 | * Chip ID | |
1920 | */ | |
1921 | #define EEPROM_CHIP_ID 0x0000 | |
1922 | ||
b54f78a8 BZ |
1923 | /* |
1924 | * EEPROM Version | |
1925 | */ | |
1926 | #define EEPROM_VERSION 0x0001 | |
1927 | #define EEPROM_VERSION_FAE FIELD16(0x00ff) | |
1928 | #define EEPROM_VERSION_VERSION FIELD16(0xff00) | |
1929 | ||
1930 | /* | |
1931 | * HW MAC address. | |
1932 | */ | |
1933 | #define EEPROM_MAC_ADDR_0 0x0002 | |
1934 | #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff) | |
1935 | #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00) | |
1936 | #define EEPROM_MAC_ADDR_1 0x0003 | |
1937 | #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff) | |
1938 | #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00) | |
1939 | #define EEPROM_MAC_ADDR_2 0x0004 | |
1940 | #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff) | |
1941 | #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00) | |
1942 | ||
1943 | /* | |
38c8a566 | 1944 | * EEPROM NIC Configuration 0 |
b54f78a8 | 1945 | * RXPATH: 1: 1R, 2: 2R, 3: 3R |
38c8a566 RJH |
1946 | * TXPATH: 1: 1T, 2: 2T, 3: 3T |
1947 | * RF_TYPE: RFIC type | |
1948 | */ | |
1949 | #define EEPROM_NIC_CONF0 0x001a | |
1950 | #define EEPROM_NIC_CONF0_RXPATH FIELD16(0x000f) | |
1951 | #define EEPROM_NIC_CONF0_TXPATH FIELD16(0x00f0) | |
1952 | #define EEPROM_NIC_CONF0_RF_TYPE FIELD16(0x0f00) | |
1953 | ||
1954 | /* | |
1955 | * EEPROM NIC Configuration 1 | |
1956 | * HW_RADIO: 0: disable, 1: enable | |
1957 | * EXTERNAL_TX_ALC: 0: disable, 1: enable | |
1958 | * EXTERNAL_LNA_2G: 0: disable, 1: enable | |
1959 | * EXTERNAL_LNA_5G: 0: disable, 1: enable | |
1960 | * CARDBUS_ACCEL: 0: enable, 1: disable | |
1961 | * BW40M_SB_2G: 0: disable, 1: enable | |
1962 | * BW40M_SB_5G: 0: disable, 1: enable | |
1963 | * WPS_PBC: 0: disable, 1: enable | |
1964 | * BW40M_2G: 0: enable, 1: disable | |
1965 | * BW40M_5G: 0: enable, 1: disable | |
1966 | * BROADBAND_EXT_LNA: 0: disable, 1: enable | |
1967 | * ANT_DIVERSITY: 00: Disable, 01: Diversity, | |
1968 | * 10: Main antenna, 11: Aux antenna | |
1969 | * INTERNAL_TX_ALC: 0: disable, 1: enable | |
1970 | * BT_COEXIST: 0: disable, 1: enable | |
1971 | * DAC_TEST: 0: disable, 1: enable | |
1972 | */ | |
1973 | #define EEPROM_NIC_CONF1 0x001b | |
1974 | #define EEPROM_NIC_CONF1_HW_RADIO FIELD16(0x0001) | |
1975 | #define EEPROM_NIC_CONF1_EXTERNAL_TX_ALC FIELD16(0x0002) | |
1976 | #define EEPROM_NIC_CONF1_EXTERNAL_LNA_2G FIELD16(0x0004) | |
1977 | #define EEPROM_NIC_CONF1_EXTERNAL_LNA_5G FIELD16(0x0008) | |
1978 | #define EEPROM_NIC_CONF1_CARDBUS_ACCEL FIELD16(0x0010) | |
1979 | #define EEPROM_NIC_CONF1_BW40M_SB_2G FIELD16(0x0020) | |
1980 | #define EEPROM_NIC_CONF1_BW40M_SB_5G FIELD16(0x0040) | |
1981 | #define EEPROM_NIC_CONF1_WPS_PBC FIELD16(0x0080) | |
1982 | #define EEPROM_NIC_CONF1_BW40M_2G FIELD16(0x0100) | |
1983 | #define EEPROM_NIC_CONF1_BW40M_5G FIELD16(0x0200) | |
1984 | #define EEPROM_NIC_CONF1_BROADBAND_EXT_LNA FIELD16(0x400) | |
1985 | #define EEPROM_NIC_CONF1_ANT_DIVERSITY FIELD16(0x1800) | |
1986 | #define EEPROM_NIC_CONF1_INTERNAL_TX_ALC FIELD16(0x2000) | |
1987 | #define EEPROM_NIC_CONF1_BT_COEXIST FIELD16(0x4000) | |
1988 | #define EEPROM_NIC_CONF1_DAC_TEST FIELD16(0x8000) | |
b54f78a8 BZ |
1989 | |
1990 | /* | |
1991 | * EEPROM frequency | |
1992 | */ | |
1993 | #define EEPROM_FREQ 0x001d | |
1994 | #define EEPROM_FREQ_OFFSET FIELD16(0x00ff) | |
1995 | #define EEPROM_FREQ_LED_MODE FIELD16(0x7f00) | |
1996 | #define EEPROM_FREQ_LED_POLARITY FIELD16(0x1000) | |
1997 | ||
1998 | /* | |
1999 | * EEPROM LED | |
2000 | * POLARITY_RDY_G: Polarity RDY_G setting. | |
2001 | * POLARITY_RDY_A: Polarity RDY_A setting. | |
2002 | * POLARITY_ACT: Polarity ACT setting. | |
2003 | * POLARITY_GPIO_0: Polarity GPIO0 setting. | |
2004 | * POLARITY_GPIO_1: Polarity GPIO1 setting. | |
2005 | * POLARITY_GPIO_2: Polarity GPIO2 setting. | |
2006 | * POLARITY_GPIO_3: Polarity GPIO3 setting. | |
2007 | * POLARITY_GPIO_4: Polarity GPIO4 setting. | |
2008 | * LED_MODE: Led mode. | |
2009 | */ | |
38c8a566 RJH |
2010 | #define EEPROM_LED_AG_CONF 0x001e |
2011 | #define EEPROM_LED_ACT_CONF 0x001f | |
2012 | #define EEPROM_LED_POLARITY 0x0020 | |
b54f78a8 BZ |
2013 | #define EEPROM_LED_POLARITY_RDY_BG FIELD16(0x0001) |
2014 | #define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002) | |
2015 | #define EEPROM_LED_POLARITY_ACT FIELD16(0x0004) | |
2016 | #define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008) | |
2017 | #define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010) | |
2018 | #define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020) | |
2019 | #define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040) | |
2020 | #define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080) | |
2021 | #define EEPROM_LED_LED_MODE FIELD16(0x1f00) | |
2022 | ||
38c8a566 RJH |
2023 | /* |
2024 | * EEPROM NIC Configuration 2 | |
2025 | * RX_STREAM: 0: Reserved, 1: 1 Stream, 2: 2 Stream | |
2026 | * TX_STREAM: 0: Reserved, 1: 1 Stream, 2: 2 Stream | |
2027 | * CRYSTAL: 00: Reserved, 01: One crystal, 10: Two crystal, 11: Reserved | |
2028 | */ | |
2029 | #define EEPROM_NIC_CONF2 0x0021 | |
2030 | #define EEPROM_NIC_CONF2_RX_STREAM FIELD16(0x000f) | |
2031 | #define EEPROM_NIC_CONF2_TX_STREAM FIELD16(0x00f0) | |
2032 | #define EEPROM_NIC_CONF2_CRYSTAL FIELD16(0x0600) | |
2033 | ||
b54f78a8 BZ |
2034 | /* |
2035 | * EEPROM LNA | |
2036 | */ | |
2037 | #define EEPROM_LNA 0x0022 | |
2038 | #define EEPROM_LNA_BG FIELD16(0x00ff) | |
2039 | #define EEPROM_LNA_A0 FIELD16(0xff00) | |
2040 | ||
2041 | /* | |
2042 | * EEPROM RSSI BG offset | |
2043 | */ | |
2044 | #define EEPROM_RSSI_BG 0x0023 | |
2045 | #define EEPROM_RSSI_BG_OFFSET0 FIELD16(0x00ff) | |
2046 | #define EEPROM_RSSI_BG_OFFSET1 FIELD16(0xff00) | |
2047 | ||
2048 | /* | |
2049 | * EEPROM RSSI BG2 offset | |
2050 | */ | |
2051 | #define EEPROM_RSSI_BG2 0x0024 | |
2052 | #define EEPROM_RSSI_BG2_OFFSET2 FIELD16(0x00ff) | |
2053 | #define EEPROM_RSSI_BG2_LNA_A1 FIELD16(0xff00) | |
2054 | ||
e148b4c8 GW |
2055 | /* |
2056 | * EEPROM TXMIXER GAIN BG offset (note overlaps with EEPROM RSSI BG2). | |
2057 | */ | |
2058 | #define EEPROM_TXMIXER_GAIN_BG 0x0024 | |
2059 | #define EEPROM_TXMIXER_GAIN_BG_VAL FIELD16(0x0007) | |
2060 | ||
b54f78a8 BZ |
2061 | /* |
2062 | * EEPROM RSSI A offset | |
2063 | */ | |
2064 | #define EEPROM_RSSI_A 0x0025 | |
2065 | #define EEPROM_RSSI_A_OFFSET0 FIELD16(0x00ff) | |
2066 | #define EEPROM_RSSI_A_OFFSET1 FIELD16(0xff00) | |
2067 | ||
2068 | /* | |
2069 | * EEPROM RSSI A2 offset | |
2070 | */ | |
2071 | #define EEPROM_RSSI_A2 0x0026 | |
2072 | #define EEPROM_RSSI_A2_OFFSET2 FIELD16(0x00ff) | |
2073 | #define EEPROM_RSSI_A2_LNA_A2 FIELD16(0xff00) | |
2074 | ||
8d1331b3 | 2075 | /* |
e90c54b2 | 2076 | * EEPROM EIRP Maximum TX power values(unit: dbm) |
8d1331b3 | 2077 | */ |
e90c54b2 RJH |
2078 | #define EEPROM_EIRP_MAX_TX_POWER 0x0027 |
2079 | #define EEPROM_EIRP_MAX_TX_POWER_2GHZ FIELD16(0x00ff) | |
2080 | #define EEPROM_EIRP_MAX_TX_POWER_5GHZ FIELD16(0xff00) | |
8d1331b3 | 2081 | |
b54f78a8 BZ |
2082 | /* |
2083 | * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power. | |
38c8a566 | 2084 | * This is delta in 40MHZ. |
e90c54b2 | 2085 | * VALUE: Tx Power dalta value, MAX=4(unit: dbm) |
b54f78a8 | 2086 | * TYPE: 1: Plus the delta value, 0: minus the delta value |
e90c54b2 | 2087 | * ENABLE: enable tx power compensation for 40BW |
b54f78a8 BZ |
2088 | */ |
2089 | #define EEPROM_TXPOWER_DELTA 0x0028 | |
e90c54b2 RJH |
2090 | #define EEPROM_TXPOWER_DELTA_VALUE_2G FIELD16(0x003f) |
2091 | #define EEPROM_TXPOWER_DELTA_TYPE_2G FIELD16(0x0040) | |
2092 | #define EEPROM_TXPOWER_DELTA_ENABLE_2G FIELD16(0x0080) | |
2093 | #define EEPROM_TXPOWER_DELTA_VALUE_5G FIELD16(0x3f00) | |
2094 | #define EEPROM_TXPOWER_DELTA_TYPE_5G FIELD16(0x4000) | |
2095 | #define EEPROM_TXPOWER_DELTA_ENABLE_5G FIELD16(0x8000) | |
b54f78a8 BZ |
2096 | |
2097 | /* | |
2098 | * EEPROM TXPOWER 802.11BG | |
2099 | */ | |
2100 | #define EEPROM_TXPOWER_BG1 0x0029 | |
2101 | #define EEPROM_TXPOWER_BG2 0x0030 | |
2102 | #define EEPROM_TXPOWER_BG_SIZE 7 | |
2103 | #define EEPROM_TXPOWER_BG_1 FIELD16(0x00ff) | |
2104 | #define EEPROM_TXPOWER_BG_2 FIELD16(0xff00) | |
2105 | ||
2106 | /* | |
2107 | * EEPROM TXPOWER 802.11A | |
2108 | */ | |
2109 | #define EEPROM_TXPOWER_A1 0x003c | |
2110 | #define EEPROM_TXPOWER_A2 0x0053 | |
2111 | #define EEPROM_TXPOWER_A_SIZE 6 | |
2112 | #define EEPROM_TXPOWER_A_1 FIELD16(0x00ff) | |
2113 | #define EEPROM_TXPOWER_A_2 FIELD16(0xff00) | |
2114 | ||
2115 | /* | |
5e846004 | 2116 | * EEPROM TXPOWER by rate: tx power per tx rate for HT20 mode |
b54f78a8 BZ |
2117 | */ |
2118 | #define EEPROM_TXPOWER_BYRATE 0x006f | |
5e846004 HS |
2119 | #define EEPROM_TXPOWER_BYRATE_SIZE 9 |
2120 | ||
2121 | #define EEPROM_TXPOWER_BYRATE_RATE0 FIELD16(0x000f) | |
2122 | #define EEPROM_TXPOWER_BYRATE_RATE1 FIELD16(0x00f0) | |
2123 | #define EEPROM_TXPOWER_BYRATE_RATE2 FIELD16(0x0f00) | |
2124 | #define EEPROM_TXPOWER_BYRATE_RATE3 FIELD16(0xf000) | |
b54f78a8 BZ |
2125 | |
2126 | /* | |
2127 | * EEPROM BBP. | |
2128 | */ | |
2129 | #define EEPROM_BBP_START 0x0078 | |
2130 | #define EEPROM_BBP_SIZE 16 | |
2131 | #define EEPROM_BBP_VALUE FIELD16(0x00ff) | |
2132 | #define EEPROM_BBP_REG_ID FIELD16(0xff00) | |
2133 | ||
2134 | /* | |
2135 | * MCU mailbox commands. | |
2136 | */ | |
2137 | #define MCU_SLEEP 0x30 | |
2138 | #define MCU_WAKEUP 0x31 | |
2139 | #define MCU_RADIO_OFF 0x35 | |
2140 | #define MCU_CURRENT 0x36 | |
2141 | #define MCU_LED 0x50 | |
2142 | #define MCU_LED_STRENGTH 0x51 | |
38c8a566 RJH |
2143 | #define MCU_LED_AG_CONF 0x52 |
2144 | #define MCU_LED_ACT_CONF 0x53 | |
2145 | #define MCU_LED_LED_POLARITY 0x54 | |
b54f78a8 BZ |
2146 | #define MCU_RADAR 0x60 |
2147 | #define MCU_BOOT_SIGNAL 0x72 | |
d96aa640 | 2148 | #define MCU_ANT_SELECT 0X73 |
b54f78a8 BZ |
2149 | #define MCU_BBP_SIGNAL 0x80 |
2150 | #define MCU_POWER_SAVE 0x83 | |
2151 | ||
2152 | /* | |
2153 | * MCU mailbox tokens | |
2154 | */ | |
2155 | #define TOKEN_WAKUP 3 | |
2156 | ||
2157 | /* | |
2158 | * DMA descriptor defines. | |
2159 | */ | |
fd8dab9a ME |
2160 | #define TXWI_DESC_SIZE (4 * sizeof(__le32)) |
2161 | #define RXWI_DESC_SIZE (4 * sizeof(__le32)) | |
b54f78a8 BZ |
2162 | |
2163 | /* | |
2164 | * TX WI structure | |
2165 | */ | |
2166 | ||
2167 | /* | |
2168 | * Word0 | |
2169 | * FRAG: 1 To inform TKIP engine this is a fragment. | |
2170 | * MIMO_PS: The remote peer is in dynamic MIMO-PS mode | |
2171 | * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs | |
cb753b72 HS |
2172 | * BW: Channel bandwidth 0:20MHz, 1:40 MHz (for legacy rates this will |
2173 | * duplicate the frame to both channels). | |
b54f78a8 | 2174 | * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED |
2035c0cf | 2175 | * AMPDU: 1: this frame is eligible for AMPDU aggregation, the hw will |
74ee3802 HS |
2176 | * aggregate consecutive frames with the same RA and QoS TID. If |
2177 | * a frame A with the same RA and QoS TID but AMPDU=0 is queued | |
2178 | * directly after a frame B with AMPDU=1, frame A might still | |
2179 | * get aggregated into the AMPDU started by frame B. So, setting | |
2180 | * AMPDU to 0 does _not_ necessarily mean the frame is sent as | |
2181 | * MPDU, it can still end up in an AMPDU if the previous frame | |
2182 | * was tagged as AMPDU. | |
b54f78a8 BZ |
2183 | */ |
2184 | #define TXWI_W0_FRAG FIELD32(0x00000001) | |
2185 | #define TXWI_W0_MIMO_PS FIELD32(0x00000002) | |
2186 | #define TXWI_W0_CF_ACK FIELD32(0x00000004) | |
2187 | #define TXWI_W0_TS FIELD32(0x00000008) | |
2188 | #define TXWI_W0_AMPDU FIELD32(0x00000010) | |
2189 | #define TXWI_W0_MPDU_DENSITY FIELD32(0x000000e0) | |
2190 | #define TXWI_W0_TX_OP FIELD32(0x00000300) | |
2191 | #define TXWI_W0_MCS FIELD32(0x007f0000) | |
2192 | #define TXWI_W0_BW FIELD32(0x00800000) | |
2193 | #define TXWI_W0_SHORT_GI FIELD32(0x01000000) | |
2194 | #define TXWI_W0_STBC FIELD32(0x06000000) | |
2195 | #define TXWI_W0_IFS FIELD32(0x08000000) | |
2196 | #define TXWI_W0_PHYMODE FIELD32(0xc0000000) | |
2197 | ||
2198 | /* | |
2199 | * Word1 | |
0856d9c0 HS |
2200 | * ACK: 0: No Ack needed, 1: Ack needed |
2201 | * NSEQ: 0: Don't assign hw sequence number, 1: Assign hw sequence number | |
2202 | * BW_WIN_SIZE: BA windows size of the recipient | |
2203 | * WIRELESS_CLI_ID: Client ID for WCID table access | |
2204 | * MPDU_TOTAL_BYTE_COUNT: Length of 802.11 frame | |
2205 | * PACKETID: Will be latched into the TX_STA_FIFO register once the according | |
2035c0cf HS |
2206 | * frame was processed. If multiple frames are aggregated together |
2207 | * (AMPDU==1) the reported tx status will always contain the packet | |
2208 | * id of the first frame. 0: Don't report tx status for this frame. | |
bc8a979e ID |
2209 | * PACKETID_QUEUE: Part of PACKETID, This is the queue index (0-3) |
2210 | * PACKETID_ENTRY: Part of PACKETID, THis is the queue entry index (1-3) | |
2211 | * This identification number is calculated by ((idx % 3) + 1). | |
2212 | * The (+1) is required to prevent PACKETID to become 0. | |
b54f78a8 BZ |
2213 | */ |
2214 | #define TXWI_W1_ACK FIELD32(0x00000001) | |
2215 | #define TXWI_W1_NSEQ FIELD32(0x00000002) | |
2216 | #define TXWI_W1_BW_WIN_SIZE FIELD32(0x000000fc) | |
2217 | #define TXWI_W1_WIRELESS_CLI_ID FIELD32(0x0000ff00) | |
2218 | #define TXWI_W1_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000) | |
2219 | #define TXWI_W1_PACKETID FIELD32(0xf0000000) | |
bc8a979e ID |
2220 | #define TXWI_W1_PACKETID_QUEUE FIELD32(0x30000000) |
2221 | #define TXWI_W1_PACKETID_ENTRY FIELD32(0xc0000000) | |
b54f78a8 BZ |
2222 | |
2223 | /* | |
2224 | * Word2 | |
2225 | */ | |
2226 | #define TXWI_W2_IV FIELD32(0xffffffff) | |
2227 | ||
2228 | /* | |
2229 | * Word3 | |
2230 | */ | |
2231 | #define TXWI_W3_EIV FIELD32(0xffffffff) | |
2232 | ||
2233 | /* | |
2234 | * RX WI structure | |
2235 | */ | |
2236 | ||
2237 | /* | |
2238 | * Word0 | |
2239 | */ | |
2240 | #define RXWI_W0_WIRELESS_CLI_ID FIELD32(0x000000ff) | |
2241 | #define RXWI_W0_KEY_INDEX FIELD32(0x00000300) | |
2242 | #define RXWI_W0_BSSID FIELD32(0x00001c00) | |
2243 | #define RXWI_W0_UDF FIELD32(0x0000e000) | |
2244 | #define RXWI_W0_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000) | |
2245 | #define RXWI_W0_TID FIELD32(0xf0000000) | |
2246 | ||
2247 | /* | |
2248 | * Word1 | |
2249 | */ | |
2250 | #define RXWI_W1_FRAG FIELD32(0x0000000f) | |
2251 | #define RXWI_W1_SEQUENCE FIELD32(0x0000fff0) | |
2252 | #define RXWI_W1_MCS FIELD32(0x007f0000) | |
2253 | #define RXWI_W1_BW FIELD32(0x00800000) | |
2254 | #define RXWI_W1_SHORT_GI FIELD32(0x01000000) | |
2255 | #define RXWI_W1_STBC FIELD32(0x06000000) | |
2256 | #define RXWI_W1_PHYMODE FIELD32(0xc0000000) | |
2257 | ||
2258 | /* | |
2259 | * Word2 | |
2260 | */ | |
2261 | #define RXWI_W2_RSSI0 FIELD32(0x000000ff) | |
2262 | #define RXWI_W2_RSSI1 FIELD32(0x0000ff00) | |
2263 | #define RXWI_W2_RSSI2 FIELD32(0x00ff0000) | |
2264 | ||
2265 | /* | |
2266 | * Word3 | |
2267 | */ | |
2268 | #define RXWI_W3_SNR0 FIELD32(0x000000ff) | |
2269 | #define RXWI_W3_SNR1 FIELD32(0x0000ff00) | |
2270 | ||
2271 | /* | |
2272 | * Macros for converting txpower from EEPROM to mac80211 value | |
2273 | * and from mac80211 value to register value. | |
2274 | */ | |
2275 | #define MIN_G_TXPOWER 0 | |
2276 | #define MIN_A_TXPOWER -7 | |
2277 | #define MAX_G_TXPOWER 31 | |
2278 | #define MAX_A_TXPOWER 15 | |
2279 | #define DEFAULT_TXPOWER 5 | |
2280 | ||
2281 | #define TXPOWER_G_FROM_DEV(__txpower) \ | |
2282 | ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower) | |
2283 | ||
2284 | #define TXPOWER_G_TO_DEV(__txpower) \ | |
2285 | clamp_t(char, __txpower, MIN_G_TXPOWER, MAX_G_TXPOWER) | |
2286 | ||
2287 | #define TXPOWER_A_FROM_DEV(__txpower) \ | |
2288 | ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower) | |
2289 | ||
2290 | #define TXPOWER_A_TO_DEV(__txpower) \ | |
2291 | clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER) | |
2292 | ||
e90c54b2 RJH |
2293 | /* |
2294 | * Board's maximun TX power limitation | |
2295 | */ | |
2296 | #define EIRP_MAX_TX_POWER_LIMIT 0x50 | |
2297 | ||
b54f78a8 | 2298 | #endif /* RT2800_H */ |