projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| b54f78a8 | 1 | /* |
| bc8a979e ID |
2 | Copyright (C) 2004 - 2010 Ivo van Doorn <IvDoorn@gmail.com> |
| 3 | Copyright (C) 2010 Willow Garage <http://www.willowgarage.com> | |
| 9c9a0d14 GW |
4 | Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com> |
| 5 | Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org> | |
| 6 | Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com> | |
| 7 | Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de> | |
| 8 | Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com> | |
| 9 | Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com> | |
| 10 | Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com> | |
| b54f78a8 BZ |
11 | <http://rt2x00.serialmonkey.com> |
| 12 | ||
| 13 | This program is free software; you can redistribute it and/or modify | |
| 14 | it under the terms of the GNU General Public License as published by | |
| 15 | the Free Software Foundation; either version 2 of the License, or | |
| 16 | (at your option) any later version. | |
| 17 | ||
| 18 | This program is distributed in the hope that it will be useful, | |
| 19 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 20 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 21 | GNU General Public License for more details. | |
| 22 | ||
| 23 | You should have received a copy of the GNU General Public License | |
| 24 | along with this program; if not, write to the | |
| 25 | Free Software Foundation, Inc., | |
| 26 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
| 27 | */ | |
| 28 | ||
| 29 | /* | |
| 30 | Module: rt2800 | |
| 31 | Abstract: Data structures and registers for the rt2800 modules. | |
| 32 | Supported chipsets: RT2800E, RT2800ED & RT2800U. | |
| 33 | */ | |
| 34 | ||
| 35 | #ifndef RT2800_H | |
| 36 | #define RT2800_H | |
| 37 | ||
| 38 | /* | |
| 39 | * RF chip defines. | |
| 40 | * | |
| 41 | * RF2820 2.4G 2T3R | |
| 42 | * RF2850 2.4G/5G 2T3R | |
| 43 | * RF2720 2.4G 1T2R | |
| 44 | * RF2750 2.4G/5G 1T2R | |
| 45 | * RF3020 2.4G 1T1R | |
| 46 | * RF2020 2.4G B/G | |
| 47 | * RF3021 2.4G 1T2R | |
| 48 | * RF3022 2.4G 2T2R | |
| 8d4ff3f3 RJH |
49 | * RF3052 2.4G/5G 2T2R |
| 50 | * RF2853 2.4G/5G 3T3R | |
| 51 | * RF3320 2.4G 1T1R(RT3350/RT3370/RT3390) | |
| 52 | * RF3322 2.4G 2T2R(RT3352/RT3371/RT3372/RT3391/RT3392) | |
| 53 | * RF3853 2.4G/5G 3T3R(RT3883/RT3563/RT3573/RT3593/RT3662) | |
| b54f78a8 BZ |
54 | */ |
| 55 | #define RF2820 0x0001 | |
| 56 | #define RF2850 0x0002 | |
| 57 | #define RF2720 0x0003 | |
| 58 | #define RF2750 0x0004 | |
| 59 | #define RF3020 0x0005 | |
| 60 | #define RF2020 0x0006 | |
| 61 | #define RF3021 0x0007 | |
| 62 | #define RF3022 0x0008 | |
| 63 | #define RF3052 0x0009 | |
| 8d4ff3f3 | 64 | #define RF2853 0x000a |
| fab799c3 | 65 | #define RF3320 0x000b |
| 8d4ff3f3 RJH |
66 | #define RF3322 0x000c |
| 67 | #define RF3853 0x000d | |
| b54f78a8 BZ |
68 | |
| 69 | /* | |
| 8d0c9b65 | 70 | * Chipset revisions. |
| b54f78a8 | 71 | */ |
| 8d0c9b65 GW |
72 | #define REV_RT2860C 0x0100 |
| 73 | #define REV_RT2860D 0x0101 | |
| 8d0c9b65 GW |
74 | #define REV_RT2872E 0x0200 |
| 75 | #define REV_RT3070E 0x0200 | |
| 76 | #define REV_RT3070F 0x0201 | |
| 77 | #define REV_RT3071E 0x0211 | |
| 78 | #define REV_RT3090E 0x0211 | |
| 79 | #define REV_RT3390E 0x0211 | |
| b54f78a8 BZ |
80 | |
| 81 | /* | |
| 82 | * Signal information. | |
| 83 | * Default offset is required for RSSI <-> dBm conversion. | |
| 84 | */ | |
| 74861922 | 85 | #define DEFAULT_RSSI_OFFSET 120 |
| b54f78a8 BZ |
86 | |
| 87 | /* | |
| 88 | * Register layout information. | |
| 89 | */ | |
| 90 | #define CSR_REG_BASE 0x1000 | |
| 91 | #define CSR_REG_SIZE 0x0800 | |
| 92 | #define EEPROM_BASE 0x0000 | |
| 93 | #define EEPROM_SIZE 0x0110 | |
| 94 | #define BBP_BASE 0x0000 | |
| 95 | #define BBP_SIZE 0x0080 | |
| 96 | #define RF_BASE 0x0004 | |
| 97 | #define RF_SIZE 0x0010 | |
| 98 | ||
| 99 | /* | |
| 100 | * Number of TX queues. | |
| 101 | */ | |
| 102 | #define NUM_TX_QUEUES 4 | |
| 103 | ||
| 104 | /* | |
| fab799c3 | 105 | * Registers. |
| b54f78a8 BZ |
106 | */ |
| 107 | ||
| 785c3c06 GW |
108 | /* |
| 109 | * E2PROM_CSR: PCI EEPROM control register. | |
| 110 | * RELOAD: Write 1 to reload eeprom content. | |
| 111 | * TYPE: 0: 93c46, 1:93c66. | |
| 112 | * LOAD_STATUS: 1:loading, 0:done. | |
| 113 | */ | |
| 114 | #define E2PROM_CSR 0x0004 | |
| 115 | #define E2PROM_CSR_DATA_CLOCK FIELD32(0x00000001) | |
| 116 | #define E2PROM_CSR_CHIP_SELECT FIELD32(0x00000002) | |
| 117 | #define E2PROM_CSR_DATA_IN FIELD32(0x00000004) | |
| 118 | #define E2PROM_CSR_DATA_OUT FIELD32(0x00000008) | |
| 119 | #define E2PROM_CSR_TYPE FIELD32(0x00000030) | |
| 120 | #define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040) | |
| 121 | #define E2PROM_CSR_RELOAD FIELD32(0x00000080) | |
| 122 | ||
| fab799c3 GW |
123 | /* |
| 124 | * OPT_14: Unknown register used by rt3xxx devices. | |
| 125 | */ | |
| 126 | #define OPT_14_CSR 0x0114 | |
| 127 | #define OPT_14_CSR_BIT0 FIELD32(0x00000001) | |
| 128 | ||
| b54f78a8 BZ |
129 | /* |
| 130 | * INT_SOURCE_CSR: Interrupt source register. | |
| 131 | * Write one to clear corresponding bit. | |
| 0bdab171 | 132 | * TX_FIFO_STATUS: FIFO Statistics is full, sw should read TX_STA_FIFO |
| b54f78a8 BZ |
133 | */ |
| 134 | #define INT_SOURCE_CSR 0x0200 | |
| 135 | #define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001) | |
| 136 | #define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002) | |
| 137 | #define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004) | |
| 138 | #define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008) | |
| 139 | #define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010) | |
| 140 | #define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020) | |
| 141 | #define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040) | |
| 142 | #define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080) | |
| 143 | #define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100) | |
| 144 | #define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200) | |
| 145 | #define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400) | |
| 146 | #define INT_SOURCE_CSR_TBTT FIELD32(0x00000800) | |
| 147 | #define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000) | |
| 148 | #define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000) | |
| 149 | #define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000) | |
| 150 | #define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000) | |
| 151 | #define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000) | |
| 152 | #define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000) | |
| 153 | ||
| 154 | /* | |
| 155 | * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF. | |
| 156 | */ | |
| 157 | #define INT_MASK_CSR 0x0204 | |
| 158 | #define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001) | |
| 159 | #define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002) | |
| 160 | #define INT_MASK_CSR_RX_DONE FIELD32(0x00000004) | |
| 161 | #define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008) | |
| 162 | #define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010) | |
| 163 | #define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020) | |
| 164 | #define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040) | |
| 165 | #define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080) | |
| 166 | #define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100) | |
| 167 | #define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200) | |
| 168 | #define INT_MASK_CSR_RXTX_COHERENT FIELD32(0x00000400) | |
| 169 | #define INT_MASK_CSR_TBTT FIELD32(0x00000800) | |
| 170 | #define INT_MASK_CSR_PRE_TBTT FIELD32(0x00001000) | |
| 171 | #define INT_MASK_CSR_TX_FIFO_STATUS FIELD32(0x00002000) | |
| 172 | #define INT_MASK_CSR_AUTO_WAKEUP FIELD32(0x00004000) | |
| 173 | #define INT_MASK_CSR_GPTIMER FIELD32(0x00008000) | |
| 174 | #define INT_MASK_CSR_RX_COHERENT FIELD32(0x00010000) | |
| 175 | #define INT_MASK_CSR_TX_COHERENT FIELD32(0x00020000) | |
| 176 | ||
| 177 | /* | |
| 178 | * WPDMA_GLO_CFG | |
| 179 | */ | |
| 180 | #define WPDMA_GLO_CFG 0x0208 | |
| 181 | #define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001) | |
| 182 | #define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002) | |
| 183 | #define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004) | |
| 184 | #define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008) | |
| 185 | #define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030) | |
| 186 | #define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040) | |
| 187 | #define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080) | |
| 188 | #define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00) | |
| 189 | #define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000) | |
| 190 | ||
| 191 | /* | |
| 192 | * WPDMA_RST_IDX | |
| 193 | */ | |
| 194 | #define WPDMA_RST_IDX 0x020c | |
| 195 | #define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001) | |
| 196 | #define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002) | |
| 197 | #define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004) | |
| 198 | #define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008) | |
| 199 | #define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010) | |
| 200 | #define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020) | |
| 201 | #define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000) | |
| 202 | ||
| 203 | /* | |
| 204 | * DELAY_INT_CFG | |
| 205 | */ | |
| 206 | #define DELAY_INT_CFG 0x0210 | |
| 207 | #define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff) | |
| 208 | #define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00) | |
| 209 | #define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000) | |
| 210 | #define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000) | |
| 211 | #define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000) | |
| 212 | #define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000) | |
| 213 | ||
| 214 | /* | |
| 215 | * WMM_AIFSN_CFG: Aifsn for each EDCA AC | |
| f615e9a3 ID |
216 | * AIFSN0: AC_VO |
| 217 | * AIFSN1: AC_VI | |
| 218 | * AIFSN2: AC_BE | |
| 219 | * AIFSN3: AC_BK | |
| b54f78a8 BZ |
220 | */ |
| 221 | #define WMM_AIFSN_CFG 0x0214 | |
| 222 | #define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f) | |
| 223 | #define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0) | |
| 224 | #define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00) | |
| 225 | #define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000) | |
| 226 | ||
| 227 | /* | |
| 228 | * WMM_CWMIN_CSR: CWmin for each EDCA AC | |
| f615e9a3 ID |
229 | * CWMIN0: AC_VO |
| 230 | * CWMIN1: AC_VI | |
| 231 | * CWMIN2: AC_BE | |
| 232 | * CWMIN3: AC_BK | |
| b54f78a8 BZ |
233 | */ |
| 234 | #define WMM_CWMIN_CFG 0x0218 | |
| 235 | #define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f) | |
| 236 | #define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0) | |
| 237 | #define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00) | |
| 238 | #define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000) | |
| 239 | ||
| 240 | /* | |
| 241 | * WMM_CWMAX_CSR: CWmax for each EDCA AC | |
| f615e9a3 ID |
242 | * CWMAX0: AC_VO |
| 243 | * CWMAX1: AC_VI | |
| 244 | * CWMAX2: AC_BE | |
| 245 | * CWMAX3: AC_BK | |
| b54f78a8 BZ |
246 | */ |
| 247 | #define WMM_CWMAX_CFG 0x021c | |
| 248 | #define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f) | |
| 249 | #define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0) | |
| 250 | #define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00) | |
| 251 | #define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000) | |
| 252 | ||
| 253 | /* | |
| f615e9a3 ID |
254 | * AC_TXOP0: AC_VO/AC_VI TXOP register |
| 255 | * AC0TXOP: AC_VO in unit of 32us | |
| 256 | * AC1TXOP: AC_VI in unit of 32us | |
| b54f78a8 BZ |
257 | */ |
| 258 | #define WMM_TXOP0_CFG 0x0220 | |
| 259 | #define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff) | |
| 260 | #define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000) | |
| 261 | ||
| 262 | /* | |
| f615e9a3 ID |
263 | * AC_TXOP1: AC_BE/AC_BK TXOP register |
| 264 | * AC2TXOP: AC_BE in unit of 32us | |
| 265 | * AC3TXOP: AC_BK in unit of 32us | |
| b54f78a8 BZ |
266 | */ |
| 267 | #define WMM_TXOP1_CFG 0x0224 | |
| 268 | #define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff) | |
| 269 | #define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000) | |
| 270 | ||
| 271 | /* | |
| 272 | * GPIO_CTRL_CFG: | |
| d96aa640 | 273 | * GPIOD: GPIO direction, 0: Output, 1: Input |
| b54f78a8 BZ |
274 | */ |
| 275 | #define GPIO_CTRL_CFG 0x0228 | |
| 276 | #define GPIO_CTRL_CFG_BIT0 FIELD32(0x00000001) | |
| 277 | #define GPIO_CTRL_CFG_BIT1 FIELD32(0x00000002) | |
| 278 | #define GPIO_CTRL_CFG_BIT2 FIELD32(0x00000004) | |
| 279 | #define GPIO_CTRL_CFG_BIT3 FIELD32(0x00000008) | |
| 280 | #define GPIO_CTRL_CFG_BIT4 FIELD32(0x00000010) | |
| 281 | #define GPIO_CTRL_CFG_BIT5 FIELD32(0x00000020) | |
| 282 | #define GPIO_CTRL_CFG_BIT6 FIELD32(0x00000040) | |
| 283 | #define GPIO_CTRL_CFG_BIT7 FIELD32(0x00000080) | |
| 284 | #define GPIO_CTRL_CFG_BIT8 FIELD32(0x00000100) | |
| d96aa640 | 285 | #define GPIO_CTRL_CFG_GPIOD FIELD32(0x00000800) |
| b54f78a8 BZ |
286 | |
| 287 | /* | |
| 288 | * MCU_CMD_CFG | |
| 289 | */ | |
| 290 | #define MCU_CMD_CFG 0x022c | |
| 291 | ||
| 292 | /* | |
| f615e9a3 | 293 | * AC_VO register offsets |
| b54f78a8 BZ |
294 | */ |
| 295 | #define TX_BASE_PTR0 0x0230 | |
| 296 | #define TX_MAX_CNT0 0x0234 | |
| 297 | #define TX_CTX_IDX0 0x0238 | |
| 298 | #define TX_DTX_IDX0 0x023c | |
| 299 | ||
| 300 | /* | |
| f615e9a3 | 301 | * AC_VI register offsets |
| b54f78a8 BZ |
302 | */ |
| 303 | #define TX_BASE_PTR1 0x0240 | |
| 304 | #define TX_MAX_CNT1 0x0244 | |
| 305 | #define TX_CTX_IDX1 0x0248 | |
| 306 | #define TX_DTX_IDX1 0x024c | |
| 307 | ||
| 308 | /* | |
| f615e9a3 | 309 | * AC_BE register offsets |
| b54f78a8 BZ |
310 | */ |
| 311 | #define TX_BASE_PTR2 0x0250 | |
| 312 | #define TX_MAX_CNT2 0x0254 | |
| 313 | #define TX_CTX_IDX2 0x0258 | |
| 314 | #define TX_DTX_IDX2 0x025c | |
| 315 | ||
| 316 | /* | |
| f615e9a3 | 317 | * AC_BK register offsets |
| b54f78a8 BZ |
318 | */ |
| 319 | #define TX_BASE_PTR3 0x0260 | |
| 320 | #define TX_MAX_CNT3 0x0264 | |
| 321 | #define TX_CTX_IDX3 0x0268 | |
| 322 | #define TX_DTX_IDX3 0x026c | |
| 323 | ||
| 324 | /* | |
| 325 | * HCCA register offsets | |
| 326 | */ | |
| 327 | #define TX_BASE_PTR4 0x0270 | |
| 328 | #define TX_MAX_CNT4 0x0274 | |
| 329 | #define TX_CTX_IDX4 0x0278 | |
| 330 | #define TX_DTX_IDX4 0x027c | |
| 331 | ||
| 332 | /* | |
| 333 | * MGMT register offsets | |
| 334 | */ | |
| 335 | #define TX_BASE_PTR5 0x0280 | |
| 336 | #define TX_MAX_CNT5 0x0284 | |
| 337 | #define TX_CTX_IDX5 0x0288 | |
| 338 | #define TX_DTX_IDX5 0x028c | |
| 339 | ||
| 340 | /* | |
| 341 | * RX register offsets | |
| 342 | */ | |
| 343 | #define RX_BASE_PTR 0x0290 | |
| 344 | #define RX_MAX_CNT 0x0294 | |
| 345 | #define RX_CRX_IDX 0x0298 | |
| 346 | #define RX_DRX_IDX 0x029c | |
| 347 | ||
| 785c3c06 GW |
348 | /* |
| 349 | * USB_DMA_CFG | |
| 350 | * RX_BULK_AGG_TIMEOUT: Rx Bulk Aggregation TimeOut in unit of 33ns. | |
| 351 | * RX_BULK_AGG_LIMIT: Rx Bulk Aggregation Limit in unit of 256 bytes. | |
| 352 | * PHY_CLEAR: phy watch dog enable. | |
| 353 | * TX_CLEAR: Clear USB DMA TX path. | |
| 354 | * TXOP_HALT: Halt TXOP count down when TX buffer is full. | |
| 355 | * RX_BULK_AGG_EN: Enable Rx Bulk Aggregation. | |
| 356 | * RX_BULK_EN: Enable USB DMA Rx. | |
| 357 | * TX_BULK_EN: Enable USB DMA Tx. | |
| 358 | * EP_OUT_VALID: OUT endpoint data valid. | |
| 359 | * RX_BUSY: USB DMA RX FSM busy. | |
| 360 | * TX_BUSY: USB DMA TX FSM busy. | |
| 361 | */ | |
| 362 | #define USB_DMA_CFG 0x02a0 | |
| 363 | #define USB_DMA_CFG_RX_BULK_AGG_TIMEOUT FIELD32(0x000000ff) | |
| 364 | #define USB_DMA_CFG_RX_BULK_AGG_LIMIT FIELD32(0x0000ff00) | |
| 365 | #define USB_DMA_CFG_PHY_CLEAR FIELD32(0x00010000) | |
| 366 | #define USB_DMA_CFG_TX_CLEAR FIELD32(0x00080000) | |
| 367 | #define USB_DMA_CFG_TXOP_HALT FIELD32(0x00100000) | |
| 368 | #define USB_DMA_CFG_RX_BULK_AGG_EN FIELD32(0x00200000) | |
| 369 | #define USB_DMA_CFG_RX_BULK_EN FIELD32(0x00400000) | |
| 370 | #define USB_DMA_CFG_TX_BULK_EN FIELD32(0x00800000) | |
| 371 | #define USB_DMA_CFG_EP_OUT_VALID FIELD32(0x3f000000) | |
| 372 | #define USB_DMA_CFG_RX_BUSY FIELD32(0x40000000) | |
| 373 | #define USB_DMA_CFG_TX_BUSY FIELD32(0x80000000) | |
| 374 | ||
| 375 | /* | |
| 376 | * US_CYC_CNT | |
| c6fcc0e5 RJH |
377 | * BT_MODE_EN: Bluetooth mode enable |
| 378 | * CLOCK CYCLE: Clock cycle count in 1us. | |
| 379 | * PCI:0x21, PCIE:0x7d, USB:0x1e | |
| 785c3c06 GW |
380 | */ |
| 381 | #define US_CYC_CNT 0x02a4 | |
| c6fcc0e5 | 382 | #define US_CYC_CNT_BT_MODE_EN FIELD32(0x00000100) |
| 785c3c06 GW |
383 | #define US_CYC_CNT_CLOCK_CYCLE FIELD32(0x000000ff) |
| 384 | ||
| b54f78a8 BZ |
385 | /* |
| 386 | * PBF_SYS_CTRL | |
| 387 | * HOST_RAM_WRITE: enable Host program ram write selection | |
| 388 | */ | |
| 389 | #define PBF_SYS_CTRL 0x0400 | |
| 390 | #define PBF_SYS_CTRL_READY FIELD32(0x00000080) | |
| 391 | #define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000) | |
| 392 | ||
| 393 | /* | |
| 394 | * HOST-MCU shared memory | |
| 395 | */ | |
| 396 | #define HOST_CMD_CSR 0x0404 | |
| 397 | #define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff) | |
| 398 | ||
| 399 | /* | |
| 400 | * PBF registers | |
| 401 | * Most are for debug. Driver doesn't touch PBF register. | |
| 402 | */ | |
| 403 | #define PBF_CFG 0x0408 | |
| 404 | #define PBF_MAX_PCNT 0x040c | |
| 405 | #define PBF_CTRL 0x0410 | |
| 406 | #define PBF_INT_STA 0x0414 | |
| 407 | #define PBF_INT_ENA 0x0418 | |
| 408 | ||
| 409 | /* | |
| 410 | * BCN_OFFSET0: | |
| 411 | */ | |
| 412 | #define BCN_OFFSET0 0x042c | |
| 413 | #define BCN_OFFSET0_BCN0 FIELD32(0x000000ff) | |
| 414 | #define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00) | |
| 415 | #define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000) | |
| 416 | #define BCN_OFFSET0_BCN3 FIELD32(0xff000000) | |
| 417 | ||
| 418 | /* | |
| 419 | * BCN_OFFSET1: | |
| 420 | */ | |
| 421 | #define BCN_OFFSET1 0x0430 | |
| 422 | #define BCN_OFFSET1_BCN4 FIELD32(0x000000ff) | |
| 423 | #define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00) | |
| 424 | #define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000) | |
| 425 | #define BCN_OFFSET1_BCN7 FIELD32(0xff000000) | |
| 426 | ||
| 427 | /* | |
| 8c5765fd ID |
428 | * TXRXQ_PCNT: PBF register |
| 429 | * PCNT_TX0Q: Page count for TX hardware queue 0 | |
| 430 | * PCNT_TX1Q: Page count for TX hardware queue 1 | |
| 431 | * PCNT_TX2Q: Page count for TX hardware queue 2 | |
| 432 | * PCNT_RX0Q: Page count for RX hardware queue | |
| b54f78a8 BZ |
433 | */ |
| 434 | #define TXRXQ_PCNT 0x0438 | |
| 8c5765fd ID |
435 | #define TXRXQ_PCNT_TX0Q FIELD32(0x000000ff) |
| 436 | #define TXRXQ_PCNT_TX1Q FIELD32(0x0000ff00) | |
| 437 | #define TXRXQ_PCNT_TX2Q FIELD32(0x00ff0000) | |
| 438 | #define TXRXQ_PCNT_RX0Q FIELD32(0xff000000) | |
| 439 | ||
| 440 | /* | |
| 441 | * PBF register | |
| 442 | * Debug. Driver doesn't touch PBF register. | |
| 443 | */ | |
| b54f78a8 BZ |
444 | #define PBF_DBG 0x043c |
| 445 | ||
| 446 | /* | |
| 447 | * RF registers | |
| 448 | */ | |
| 449 | #define RF_CSR_CFG 0x0500 | |
| 450 | #define RF_CSR_CFG_DATA FIELD32(0x000000ff) | |
| 451 | #define RF_CSR_CFG_REGNUM FIELD32(0x00001f00) | |
| 452 | #define RF_CSR_CFG_WRITE FIELD32(0x00010000) | |
| 453 | #define RF_CSR_CFG_BUSY FIELD32(0x00020000) | |
| 454 | ||
| 30e84034 BZ |
455 | /* |
| 456 | * EFUSE_CSR: RT30x0 EEPROM | |
| 457 | */ | |
| 458 | #define EFUSE_CTRL 0x0580 | |
| 459 | #define EFUSE_CTRL_ADDRESS_IN FIELD32(0x03fe0000) | |
| 460 | #define EFUSE_CTRL_MODE FIELD32(0x000000c0) | |
| 461 | #define EFUSE_CTRL_KICK FIELD32(0x40000000) | |
| 462 | #define EFUSE_CTRL_PRESENT FIELD32(0x80000000) | |
| 463 | ||
| 464 | /* | |
| 465 | * EFUSE_DATA0 | |
| 466 | */ | |
| 467 | #define EFUSE_DATA0 0x0590 | |
| 468 | ||
| 469 | /* | |
| 470 | * EFUSE_DATA1 | |
| 471 | */ | |
| 472 | #define EFUSE_DATA1 0x0594 | |
| 473 | ||
| 474 | /* | |
| 475 | * EFUSE_DATA2 | |
| 476 | */ | |
| 477 | #define EFUSE_DATA2 0x0598 | |
| 478 | ||
| 479 | /* | |
| 480 | * EFUSE_DATA3 | |
| 481 | */ | |
| 482 | #define EFUSE_DATA3 0x059c | |
| 483 | ||
| fab799c3 GW |
484 | /* |
| 485 | * LDO_CFG0 | |
| 486 | */ | |
| 487 | #define LDO_CFG0 0x05d4 | |
| 488 | #define LDO_CFG0_DELAY3 FIELD32(0x000000ff) | |
| 489 | #define LDO_CFG0_DELAY2 FIELD32(0x0000ff00) | |
| 490 | #define LDO_CFG0_DELAY1 FIELD32(0x00ff0000) | |
| 491 | #define LDO_CFG0_BGSEL FIELD32(0x03000000) | |
| 492 | #define LDO_CFG0_LDO_CORE_VLEVEL FIELD32(0x1c000000) | |
| 493 | #define LD0_CFG0_LDO25_LEVEL FIELD32(0x60000000) | |
| 494 | #define LDO_CFG0_LDO25_LARGEA FIELD32(0x80000000) | |
| 495 | ||
| 496 | /* | |
| 497 | * GPIO_SWITCH | |
| 498 | */ | |
| 499 | #define GPIO_SWITCH 0x05dc | |
| 500 | #define GPIO_SWITCH_0 FIELD32(0x00000001) | |
| 501 | #define GPIO_SWITCH_1 FIELD32(0x00000002) | |
| 502 | #define GPIO_SWITCH_2 FIELD32(0x00000004) | |
| 503 | #define GPIO_SWITCH_3 FIELD32(0x00000008) | |
| 504 | #define GPIO_SWITCH_4 FIELD32(0x00000010) | |
| 505 | #define GPIO_SWITCH_5 FIELD32(0x00000020) | |
| 506 | #define GPIO_SWITCH_6 FIELD32(0x00000040) | |
| 507 | #define GPIO_SWITCH_7 FIELD32(0x00000080) | |
| 508 | ||
| b54f78a8 BZ |
509 | /* |
| 510 | * MAC Control/Status Registers(CSR). | |
| 511 | * Some values are set in TU, whereas 1 TU == 1024 us. | |
| 512 | */ | |
| 513 | ||
| 514 | /* | |
| 515 | * MAC_CSR0: ASIC revision number. | |
| 516 | * ASIC_REV: 0 | |
| 517 | * ASIC_VER: 2860 or 2870 | |
| 518 | */ | |
| 519 | #define MAC_CSR0 0x1000 | |
| 49e721ec GW |
520 | #define MAC_CSR0_REVISION FIELD32(0x0000ffff) |
| 521 | #define MAC_CSR0_CHIPSET FIELD32(0xffff0000) | |
| b54f78a8 BZ |
522 | |
| 523 | /* | |
| 524 | * MAC_SYS_CTRL: | |
| 525 | */ | |
| 526 | #define MAC_SYS_CTRL 0x1004 | |
| 527 | #define MAC_SYS_CTRL_RESET_CSR FIELD32(0x00000001) | |
| 528 | #define MAC_SYS_CTRL_RESET_BBP FIELD32(0x00000002) | |
| 529 | #define MAC_SYS_CTRL_ENABLE_TX FIELD32(0x00000004) | |
| 530 | #define MAC_SYS_CTRL_ENABLE_RX FIELD32(0x00000008) | |
| 531 | #define MAC_SYS_CTRL_CONTINUOUS_TX FIELD32(0x00000010) | |
| 532 | #define MAC_SYS_CTRL_LOOPBACK FIELD32(0x00000020) | |
| 533 | #define MAC_SYS_CTRL_WLAN_HALT FIELD32(0x00000040) | |
| 534 | #define MAC_SYS_CTRL_RX_TIMESTAMP FIELD32(0x00000080) | |
| 535 | ||
| 536 | /* | |
| 537 | * MAC_ADDR_DW0: STA MAC register 0 | |
| 538 | */ | |
| 539 | #define MAC_ADDR_DW0 0x1008 | |
| 540 | #define MAC_ADDR_DW0_BYTE0 FIELD32(0x000000ff) | |
| 541 | #define MAC_ADDR_DW0_BYTE1 FIELD32(0x0000ff00) | |
| 542 | #define MAC_ADDR_DW0_BYTE2 FIELD32(0x00ff0000) | |
| 543 | #define MAC_ADDR_DW0_BYTE3 FIELD32(0xff000000) | |
| 544 | ||
| 545 | /* | |
| 546 | * MAC_ADDR_DW1: STA MAC register 1 | |
| 547 | * UNICAST_TO_ME_MASK: | |
| 548 | * Used to mask off bits from byte 5 of the MAC address | |
| 549 | * to determine the UNICAST_TO_ME bit for RX frames. | |
| 550 | * The full mask is complemented by BSS_ID_MASK: | |
| 551 | * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK | |
| 552 | */ | |
| 553 | #define MAC_ADDR_DW1 0x100c | |
| 554 | #define MAC_ADDR_DW1_BYTE4 FIELD32(0x000000ff) | |
| 555 | #define MAC_ADDR_DW1_BYTE5 FIELD32(0x0000ff00) | |
| 556 | #define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000) | |
| 557 | ||
| 558 | /* | |
| 559 | * MAC_BSSID_DW0: BSSID register 0 | |
| 560 | */ | |
| 561 | #define MAC_BSSID_DW0 0x1010 | |
| 562 | #define MAC_BSSID_DW0_BYTE0 FIELD32(0x000000ff) | |
| 563 | #define MAC_BSSID_DW0_BYTE1 FIELD32(0x0000ff00) | |
| 564 | #define MAC_BSSID_DW0_BYTE2 FIELD32(0x00ff0000) | |
| 565 | #define MAC_BSSID_DW0_BYTE3 FIELD32(0xff000000) | |
| 566 | ||
| 567 | /* | |
| 568 | * MAC_BSSID_DW1: BSSID register 1 | |
| 569 | * BSS_ID_MASK: | |
| 570 | * 0: 1-BSSID mode (BSS index = 0) | |
| 571 | * 1: 2-BSSID mode (BSS index: Byte5, bit 0) | |
| 572 | * 2: 4-BSSID mode (BSS index: byte5, bit 0 - 1) | |
| 573 | * 3: 8-BSSID mode (BSS index: byte5, bit 0 - 2) | |
| 574 | * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the | |
| 575 | * BSSID. This will make sure that those bits will be ignored | |
| 576 | * when determining the MY_BSS of RX frames. | |
| 577 | */ | |
| 578 | #define MAC_BSSID_DW1 0x1014 | |
| 579 | #define MAC_BSSID_DW1_BYTE4 FIELD32(0x000000ff) | |
| 580 | #define MAC_BSSID_DW1_BYTE5 FIELD32(0x0000ff00) | |
| 581 | #define MAC_BSSID_DW1_BSS_ID_MASK FIELD32(0x00030000) | |
| 582 | #define MAC_BSSID_DW1_BSS_BCN_NUM FIELD32(0x001c0000) | |
| 583 | ||
| 584 | /* | |
| 585 | * MAX_LEN_CFG: Maximum frame length register. | |
| 586 | * MAX_MPDU: rt2860b max 16k bytes | |
| 587 | * MAX_PSDU: Maximum PSDU length | |
| 588 | * (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16 | |
| 589 | */ | |
| 590 | #define MAX_LEN_CFG 0x1018 | |
| 591 | #define MAX_LEN_CFG_MAX_MPDU FIELD32(0x00000fff) | |
| 592 | #define MAX_LEN_CFG_MAX_PSDU FIELD32(0x00003000) | |
| 593 | #define MAX_LEN_CFG_MIN_PSDU FIELD32(0x0000c000) | |
| 594 | #define MAX_LEN_CFG_MIN_MPDU FIELD32(0x000f0000) | |
| 595 | ||
| 596 | /* | |
| 597 | * BBP_CSR_CFG: BBP serial control register | |
| 598 | * VALUE: Register value to program into BBP | |
| 599 | * REG_NUM: Selected BBP register | |
| 600 | * READ_CONTROL: 0 write BBP, 1 read BBP | |
| 601 | * BUSY: ASIC is busy executing BBP commands | |
| 602 | * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks | |
| 603 | * BBP_RW_MODE: 0 serial, 1 paralell | |
| 604 | */ | |
| 605 | #define BBP_CSR_CFG 0x101c | |
| 606 | #define BBP_CSR_CFG_VALUE FIELD32(0x000000ff) | |
| 607 | #define BBP_CSR_CFG_REGNUM FIELD32(0x0000ff00) | |
| 608 | #define BBP_CSR_CFG_READ_CONTROL FIELD32(0x00010000) | |
| 609 | #define BBP_CSR_CFG_BUSY FIELD32(0x00020000) | |
| 610 | #define BBP_CSR_CFG_BBP_PAR_DUR FIELD32(0x00040000) | |
| 611 | #define BBP_CSR_CFG_BBP_RW_MODE FIELD32(0x00080000) | |
| 612 | ||
| 613 | /* | |
| 614 | * RF_CSR_CFG0: RF control register | |
| 615 | * REGID_AND_VALUE: Register value to program into RF | |
| 616 | * BITWIDTH: Selected RF register | |
| 617 | * STANDBYMODE: 0 high when standby, 1 low when standby | |
| 618 | * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate | |
| 619 | * BUSY: ASIC is busy executing RF commands | |
| 620 | */ | |
| 621 | #define RF_CSR_CFG0 0x1020 | |
| 622 | #define RF_CSR_CFG0_REGID_AND_VALUE FIELD32(0x00ffffff) | |
| 623 | #define RF_CSR_CFG0_BITWIDTH FIELD32(0x1f000000) | |
| 624 | #define RF_CSR_CFG0_REG_VALUE_BW FIELD32(0x1fffffff) | |
| 625 | #define RF_CSR_CFG0_STANDBYMODE FIELD32(0x20000000) | |
| 626 | #define RF_CSR_CFG0_SEL FIELD32(0x40000000) | |
| 627 | #define RF_CSR_CFG0_BUSY FIELD32(0x80000000) | |
| 628 | ||
| 629 | /* | |
| 630 | * RF_CSR_CFG1: RF control register | |
| 631 | * REGID_AND_VALUE: Register value to program into RF | |
| 632 | * RFGAP: Gap between BB_CONTROL_RF and RF_LE | |
| 633 | * 0: 3 system clock cycle (37.5usec) | |
| 634 | * 1: 5 system clock cycle (62.5usec) | |
| 635 | */ | |
| 636 | #define RF_CSR_CFG1 0x1024 | |
| 637 | #define RF_CSR_CFG1_REGID_AND_VALUE FIELD32(0x00ffffff) | |
| 638 | #define RF_CSR_CFG1_RFGAP FIELD32(0x1f000000) | |
| 639 | ||
| 640 | /* | |
| 641 | * RF_CSR_CFG2: RF control register | |
| 642 | * VALUE: Register value to program into RF | |
| b54f78a8 BZ |
643 | */ |
| 644 | #define RF_CSR_CFG2 0x1028 | |
| 645 | #define RF_CSR_CFG2_VALUE FIELD32(0x00ffffff) | |
| 646 | ||
| 647 | /* | |
| 648 | * LED_CFG: LED control | |
| 649 | * color LED's: | |
| 650 | * 0: off | |
| 651 | * 1: blinking upon TX2 | |
| 652 | * 2: periodic slow blinking | |
| 653 | * 3: always on | |
| 654 | * LED polarity: | |
| 655 | * 0: active low | |
| 656 | * 1: active high | |
| 657 | */ | |
| 658 | #define LED_CFG 0x102c | |
| 659 | #define LED_CFG_ON_PERIOD FIELD32(0x000000ff) | |
| 660 | #define LED_CFG_OFF_PERIOD FIELD32(0x0000ff00) | |
| 661 | #define LED_CFG_SLOW_BLINK_PERIOD FIELD32(0x003f0000) | |
| 662 | #define LED_CFG_R_LED_MODE FIELD32(0x03000000) | |
| 663 | #define LED_CFG_G_LED_MODE FIELD32(0x0c000000) | |
| 664 | #define LED_CFG_Y_LED_MODE FIELD32(0x30000000) | |
| 665 | #define LED_CFG_LED_POLAR FIELD32(0x40000000) | |
| 666 | ||
| 47ee3eb1 HS |
667 | /* |
| 668 | * AMPDU_BA_WINSIZE: Force BlockAck window size | |
| 669 | * FORCE_WINSIZE_ENABLE: | |
| 670 | * 0: Disable forcing of BlockAck window size | |
| 671 | * 1: Enable forcing of BlockAck window size, overwrites values BlockAck | |
| 672 | * window size values in the TXWI | |
| 673 | * FORCE_WINSIZE: BlockAck window size | |
| 674 | */ | |
| 675 | #define AMPDU_BA_WINSIZE 0x1040 | |
| 676 | #define AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE FIELD32(0x00000020) | |
| 677 | #define AMPDU_BA_WINSIZE_FORCE_WINSIZE FIELD32(0x0000001f) | |
| 678 | ||
| b54f78a8 BZ |
679 | /* |
| 680 | * XIFS_TIME_CFG: MAC timing | |
| 681 | * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX | |
| 682 | * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX | |
| 683 | * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX | |
| 684 | * when MAC doesn't reference BBP signal BBRXEND | |
| 685 | * EIFS: unit 1us | |
| 686 | * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer | |
| 687 | * | |
| 688 | */ | |
| 689 | #define XIFS_TIME_CFG 0x1100 | |
| 690 | #define XIFS_TIME_CFG_CCKM_SIFS_TIME FIELD32(0x000000ff) | |
| 691 | #define XIFS_TIME_CFG_OFDM_SIFS_TIME FIELD32(0x0000ff00) | |
| 692 | #define XIFS_TIME_CFG_OFDM_XIFS_TIME FIELD32(0x000f0000) | |
| 693 | #define XIFS_TIME_CFG_EIFS FIELD32(0x1ff00000) | |
| 694 | #define XIFS_TIME_CFG_BB_RXEND_ENABLE FIELD32(0x20000000) | |
| 695 | ||
| 696 | /* | |
| 697 | * BKOFF_SLOT_CFG: | |
| 698 | */ | |
| 699 | #define BKOFF_SLOT_CFG 0x1104 | |
| 700 | #define BKOFF_SLOT_CFG_SLOT_TIME FIELD32(0x000000ff) | |
| 701 | #define BKOFF_SLOT_CFG_CC_DELAY_TIME FIELD32(0x0000ff00) | |
| 702 | ||
| 703 | /* | |
| 704 | * NAV_TIME_CFG: | |
| 705 | */ | |
| 706 | #define NAV_TIME_CFG 0x1108 | |
| 707 | #define NAV_TIME_CFG_SIFS FIELD32(0x000000ff) | |
| 708 | #define NAV_TIME_CFG_SLOT_TIME FIELD32(0x0000ff00) | |
| 709 | #define NAV_TIME_CFG_EIFS FIELD32(0x01ff0000) | |
| 710 | #define NAV_TIME_ZERO_SIFS FIELD32(0x02000000) | |
| 711 | ||
| 712 | /* | |
| 713 | * CH_TIME_CFG: count as channel busy | |
| 977206d7 HS |
714 | * EIFS_BUSY: Count EIFS as channel busy |
| 715 | * NAV_BUSY: Count NAS as channel busy | |
| 716 | * RX_BUSY: Count RX as channel busy | |
| 717 | * TX_BUSY: Count TX as channel busy | |
| 718 | * TMR_EN: Enable channel statistics timer | |
| b54f78a8 BZ |
719 | */ |
| 720 | #define CH_TIME_CFG 0x110c | |
| 977206d7 HS |
721 | #define CH_TIME_CFG_EIFS_BUSY FIELD32(0x00000010) |
| 722 | #define CH_TIME_CFG_NAV_BUSY FIELD32(0x00000008) | |
| 723 | #define CH_TIME_CFG_RX_BUSY FIELD32(0x00000004) | |
| 724 | #define CH_TIME_CFG_TX_BUSY FIELD32(0x00000002) | |
| 725 | #define CH_TIME_CFG_TMR_EN FIELD32(0x00000001) | |
| b54f78a8 BZ |
726 | |
| 727 | /* | |
| 728 | * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us | |
| 729 | */ | |
| 730 | #define PBF_LIFE_TIMER 0x1110 | |
| 731 | ||
| 732 | /* | |
| 733 | * BCN_TIME_CFG: | |
| 734 | * BEACON_INTERVAL: in unit of 1/16 TU | |
| 735 | * TSF_TICKING: Enable TSF auto counting | |
| 736 | * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode | |
| 737 | * BEACON_GEN: Enable beacon generator | |
| 738 | */ | |
| 739 | #define BCN_TIME_CFG 0x1114 | |
| 740 | #define BCN_TIME_CFG_BEACON_INTERVAL FIELD32(0x0000ffff) | |
| 741 | #define BCN_TIME_CFG_TSF_TICKING FIELD32(0x00010000) | |
| 742 | #define BCN_TIME_CFG_TSF_SYNC FIELD32(0x00060000) | |
| 743 | #define BCN_TIME_CFG_TBTT_ENABLE FIELD32(0x00080000) | |
| 744 | #define BCN_TIME_CFG_BEACON_GEN FIELD32(0x00100000) | |
| 745 | #define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000) | |
| 746 | ||
| 747 | /* | |
| 748 | * TBTT_SYNC_CFG: | |
| c4c18a9d HS |
749 | * BCN_AIFSN: Beacon AIFSN after TBTT interrupt in slots |
| 750 | * BCN_CWMIN: Beacon CWMin after TBTT interrupt in slots | |
| b54f78a8 BZ |
751 | */ |
| 752 | #define TBTT_SYNC_CFG 0x1118 | |
| c4c18a9d HS |
753 | #define TBTT_SYNC_CFG_TBTT_ADJUST FIELD32(0x000000ff) |
| 754 | #define TBTT_SYNC_CFG_BCN_EXP_WIN FIELD32(0x0000ff00) | |
| 755 | #define TBTT_SYNC_CFG_BCN_AIFSN FIELD32(0x000f0000) | |
| 756 | #define TBTT_SYNC_CFG_BCN_CWMIN FIELD32(0x00f00000) | |
| b54f78a8 BZ |
757 | |
| 758 | /* | |
| 759 | * TSF_TIMER_DW0: Local lsb TSF timer, read-only | |
| 760 | */ | |
| 761 | #define TSF_TIMER_DW0 0x111c | |
| 762 | #define TSF_TIMER_DW0_LOW_WORD FIELD32(0xffffffff) | |
| 763 | ||
| 764 | /* | |
| 765 | * TSF_TIMER_DW1: Local msb TSF timer, read-only | |
| 766 | */ | |
| 767 | #define TSF_TIMER_DW1 0x1120 | |
| 768 | #define TSF_TIMER_DW1_HIGH_WORD FIELD32(0xffffffff) | |
| 769 | ||
| 770 | /* | |
| 771 | * TBTT_TIMER: TImer remains till next TBTT, read-only | |
| 772 | */ | |
| 773 | #define TBTT_TIMER 0x1124 | |
| 774 | ||
| 775 | /* | |
| 9f926fb5 HS |
776 | * INT_TIMER_CFG: timer configuration |
| 777 | * PRE_TBTT_TIMER: leadtime to tbtt for pretbtt interrupt in units of 1/16 TU | |
| 778 | * GP_TIMER: period of general purpose timer in units of 1/16 TU | |
| b54f78a8 BZ |
779 | */ |
| 780 | #define INT_TIMER_CFG 0x1128 | |
| 9f926fb5 HS |
781 | #define INT_TIMER_CFG_PRE_TBTT_TIMER FIELD32(0x0000ffff) |
| 782 | #define INT_TIMER_CFG_GP_TIMER FIELD32(0xffff0000) | |
| b54f78a8 BZ |
783 | |
| 784 | /* | |
| 785 | * INT_TIMER_EN: GP-timer and pre-tbtt Int enable | |
| 786 | */ | |
| 787 | #define INT_TIMER_EN 0x112c | |
| 9f926fb5 HS |
788 | #define INT_TIMER_EN_PRE_TBTT_TIMER FIELD32(0x00000001) |
| 789 | #define INT_TIMER_EN_GP_TIMER FIELD32(0x00000002) | |
| b54f78a8 BZ |
790 | |
| 791 | /* | |
| d4ce3a5e | 792 | * CH_IDLE_STA: channel idle time (in us) |
| b54f78a8 BZ |
793 | */ |
| 794 | #define CH_IDLE_STA 0x1130 | |
| 795 | ||
| 796 | /* | |
| d4ce3a5e | 797 | * CH_BUSY_STA: channel busy time on primary channel (in us) |
| b54f78a8 BZ |
798 | */ |
| 799 | #define CH_BUSY_STA 0x1134 | |
| 800 | ||
| d4ce3a5e HS |
801 | /* |
| 802 | * CH_BUSY_STA_SEC: channel busy time on secondary channel in HT40 mode (in us) | |
| 803 | */ | |
| 804 | #define CH_BUSY_STA_SEC 0x1138 | |
| 805 | ||
| b54f78a8 BZ |
806 | /* |
| 807 | * MAC_STATUS_CFG: | |
| 808 | * BBP_RF_BUSY: When set to 0, BBP and RF are stable. | |
| 809 | * if 1 or higher one of the 2 registers is busy. | |
| 810 | */ | |
| 811 | #define MAC_STATUS_CFG 0x1200 | |
| 812 | #define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003) | |
| 813 | ||
| 814 | /* | |
| 815 | * PWR_PIN_CFG: | |
| 816 | */ | |
| 817 | #define PWR_PIN_CFG 0x1204 | |
| 818 | ||
| 819 | /* | |
| 820 | * AUTOWAKEUP_CFG: Manual power control / status register | |
| 821 | * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set | |
| 822 | * AUTOWAKE: 0:sleep, 1:awake | |
| 823 | */ | |
| 824 | #define AUTOWAKEUP_CFG 0x1208 | |
| 825 | #define AUTOWAKEUP_CFG_AUTO_LEAD_TIME FIELD32(0x000000ff) | |
| 826 | #define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00) | |
| 827 | #define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000) | |
| 828 | ||
| 829 | /* | |
| 830 | * EDCA_AC0_CFG: | |
| 831 | */ | |
| 832 | #define EDCA_AC0_CFG 0x1300 | |
| 833 | #define EDCA_AC0_CFG_TX_OP FIELD32(0x000000ff) | |
| 834 | #define EDCA_AC0_CFG_AIFSN FIELD32(0x00000f00) | |
| 835 | #define EDCA_AC0_CFG_CWMIN FIELD32(0x0000f000) | |
| 836 | #define EDCA_AC0_CFG_CWMAX FIELD32(0x000f0000) | |
| 837 | ||
| 838 | /* | |
| 839 | * EDCA_AC1_CFG: | |
| 840 | */ | |
| 841 | #define EDCA_AC1_CFG 0x1304 | |
| 842 | #define EDCA_AC1_CFG_TX_OP FIELD32(0x000000ff) | |
| 843 | #define EDCA_AC1_CFG_AIFSN FIELD32(0x00000f00) | |
| 844 | #define EDCA_AC1_CFG_CWMIN FIELD32(0x0000f000) | |
| 845 | #define EDCA_AC1_CFG_CWMAX FIELD32(0x000f0000) | |
| 846 | ||
| 847 | /* | |
| 848 | * EDCA_AC2_CFG: | |
| 849 | */ | |
| 850 | #define EDCA_AC2_CFG 0x1308 | |
| 851 | #define EDCA_AC2_CFG_TX_OP FIELD32(0x000000ff) | |
| 852 | #define EDCA_AC2_CFG_AIFSN FIELD32(0x00000f00) | |
| 853 | #define EDCA_AC2_CFG_CWMIN FIELD32(0x0000f000) | |
| 854 | #define EDCA_AC2_CFG_CWMAX FIELD32(0x000f0000) | |
| 855 | ||
| 856 | /* | |
| 857 | * EDCA_AC3_CFG: | |
| 858 | */ | |
| 859 | #define EDCA_AC3_CFG 0x130c | |
| 860 | #define EDCA_AC3_CFG_TX_OP FIELD32(0x000000ff) | |
| 861 | #define EDCA_AC3_CFG_AIFSN FIELD32(0x00000f00) | |
| 862 | #define EDCA_AC3_CFG_CWMIN FIELD32(0x0000f000) | |
| 863 | #define EDCA_AC3_CFG_CWMAX FIELD32(0x000f0000) | |
| 864 | ||
| 865 | /* | |
| 866 | * EDCA_TID_AC_MAP: | |
| 867 | */ | |
| 868 | #define EDCA_TID_AC_MAP 0x1310 | |
| 869 | ||
| 5e846004 HS |
870 | /* |
| 871 | * TX_PWR_CFG: | |
| 872 | */ | |
| 873 | #define TX_PWR_CFG_RATE0 FIELD32(0x0000000f) | |
| 874 | #define TX_PWR_CFG_RATE1 FIELD32(0x000000f0) | |
| 875 | #define TX_PWR_CFG_RATE2 FIELD32(0x00000f00) | |
| 876 | #define TX_PWR_CFG_RATE3 FIELD32(0x0000f000) | |
| 877 | #define TX_PWR_CFG_RATE4 FIELD32(0x000f0000) | |
| 878 | #define TX_PWR_CFG_RATE5 FIELD32(0x00f00000) | |
| 879 | #define TX_PWR_CFG_RATE6 FIELD32(0x0f000000) | |
| 880 | #define TX_PWR_CFG_RATE7 FIELD32(0xf0000000) | |
| 881 | ||
| b54f78a8 BZ |
882 | /* |
| 883 | * TX_PWR_CFG_0: | |
| 884 | */ | |
| 885 | #define TX_PWR_CFG_0 0x1314 | |
| 886 | #define TX_PWR_CFG_0_1MBS FIELD32(0x0000000f) | |
| 887 | #define TX_PWR_CFG_0_2MBS FIELD32(0x000000f0) | |
| 888 | #define TX_PWR_CFG_0_55MBS FIELD32(0x00000f00) | |
| 889 | #define TX_PWR_CFG_0_11MBS FIELD32(0x0000f000) | |
| 890 | #define TX_PWR_CFG_0_6MBS FIELD32(0x000f0000) | |
| 891 | #define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000) | |
| 892 | #define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000) | |
| 893 | #define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000) | |
| 894 | ||
| 895 | /* | |
| 896 | * TX_PWR_CFG_1: | |
| 897 | */ | |
| 898 | #define TX_PWR_CFG_1 0x1318 | |
| 899 | #define TX_PWR_CFG_1_24MBS FIELD32(0x0000000f) | |
| 900 | #define TX_PWR_CFG_1_36MBS FIELD32(0x000000f0) | |
| 901 | #define TX_PWR_CFG_1_48MBS FIELD32(0x00000f00) | |
| 902 | #define TX_PWR_CFG_1_54MBS FIELD32(0x0000f000) | |
| 903 | #define TX_PWR_CFG_1_MCS0 FIELD32(0x000f0000) | |
| 904 | #define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000) | |
| 905 | #define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000) | |
| 906 | #define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000) | |
| 907 | ||
| 908 | /* | |
| 909 | * TX_PWR_CFG_2: | |
| 910 | */ | |
| 911 | #define TX_PWR_CFG_2 0x131c | |
| 912 | #define TX_PWR_CFG_2_MCS4 FIELD32(0x0000000f) | |
| 913 | #define TX_PWR_CFG_2_MCS5 FIELD32(0x000000f0) | |
| 914 | #define TX_PWR_CFG_2_MCS6 FIELD32(0x00000f00) | |
| 915 | #define TX_PWR_CFG_2_MCS7 FIELD32(0x0000f000) | |
| 916 | #define TX_PWR_CFG_2_MCS8 FIELD32(0x000f0000) | |
| 917 | #define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000) | |
| 918 | #define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000) | |
| 919 | #define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000) | |
| 920 | ||
| 921 | /* | |
| 922 | * TX_PWR_CFG_3: | |
| 923 | */ | |
| 924 | #define TX_PWR_CFG_3 0x1320 | |
| 925 | #define TX_PWR_CFG_3_MCS12 FIELD32(0x0000000f) | |
| 926 | #define TX_PWR_CFG_3_MCS13 FIELD32(0x000000f0) | |
| 927 | #define TX_PWR_CFG_3_MCS14 FIELD32(0x00000f00) | |
| 928 | #define TX_PWR_CFG_3_MCS15 FIELD32(0x0000f000) | |
| 929 | #define TX_PWR_CFG_3_UKNOWN1 FIELD32(0x000f0000) | |
| 930 | #define TX_PWR_CFG_3_UKNOWN2 FIELD32(0x00f00000) | |
| 931 | #define TX_PWR_CFG_3_UKNOWN3 FIELD32(0x0f000000) | |
| 932 | #define TX_PWR_CFG_3_UKNOWN4 FIELD32(0xf0000000) | |
| 933 | ||
| 934 | /* | |
| 935 | * TX_PWR_CFG_4: | |
| 936 | */ | |
| 937 | #define TX_PWR_CFG_4 0x1324 | |
| 938 | #define TX_PWR_CFG_4_UKNOWN5 FIELD32(0x0000000f) | |
| 939 | #define TX_PWR_CFG_4_UKNOWN6 FIELD32(0x000000f0) | |
| 940 | #define TX_PWR_CFG_4_UKNOWN7 FIELD32(0x00000f00) | |
| 941 | #define TX_PWR_CFG_4_UKNOWN8 FIELD32(0x0000f000) | |
| 942 | ||
| 943 | /* | |
| 944 | * TX_PIN_CFG: | |
| 945 | */ | |
| 946 | #define TX_PIN_CFG 0x1328 | |
| 947 | #define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001) | |
| 948 | #define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002) | |
| 949 | #define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004) | |
| 950 | #define TX_PIN_CFG_PA_PE_G1_EN FIELD32(0x00000008) | |
| 951 | #define TX_PIN_CFG_PA_PE_A0_POL FIELD32(0x00000010) | |
| 952 | #define TX_PIN_CFG_PA_PE_G0_POL FIELD32(0x00000020) | |
| 953 | #define TX_PIN_CFG_PA_PE_A1_POL FIELD32(0x00000040) | |
| 954 | #define TX_PIN_CFG_PA_PE_G1_POL FIELD32(0x00000080) | |
| 955 | #define TX_PIN_CFG_LNA_PE_A0_EN FIELD32(0x00000100) | |
| 956 | #define TX_PIN_CFG_LNA_PE_G0_EN FIELD32(0x00000200) | |
| 957 | #define TX_PIN_CFG_LNA_PE_A1_EN FIELD32(0x00000400) | |
| 958 | #define TX_PIN_CFG_LNA_PE_G1_EN FIELD32(0x00000800) | |
| 959 | #define TX_PIN_CFG_LNA_PE_A0_POL FIELD32(0x00001000) | |
| 960 | #define TX_PIN_CFG_LNA_PE_G0_POL FIELD32(0x00002000) | |
| 961 | #define TX_PIN_CFG_LNA_PE_A1_POL FIELD32(0x00004000) | |
| 962 | #define TX_PIN_CFG_LNA_PE_G1_POL FIELD32(0x00008000) | |
| 963 | #define TX_PIN_CFG_RFTR_EN FIELD32(0x00010000) | |
| 964 | #define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000) | |
| 965 | #define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000) | |
| 966 | #define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000) | |
| 967 | ||
| 968 | /* | |
| 969 | * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz | |
| 970 | */ | |
| 971 | #define TX_BAND_CFG 0x132c | |
| a21ee724 | 972 | #define TX_BAND_CFG_HT40_MINUS FIELD32(0x00000001) |
| b54f78a8 BZ |
973 | #define TX_BAND_CFG_A FIELD32(0x00000002) |
| 974 | #define TX_BAND_CFG_BG FIELD32(0x00000004) | |
| 975 | ||
| 976 | /* | |
| 977 | * TX_SW_CFG0: | |
| 978 | */ | |
| 979 | #define TX_SW_CFG0 0x1330 | |
| 980 | ||
| 981 | /* | |
| 982 | * TX_SW_CFG1: | |
| 983 | */ | |
| 984 | #define TX_SW_CFG1 0x1334 | |
| 985 | ||
| 986 | /* | |
| 987 | * TX_SW_CFG2: | |
| 988 | */ | |
| 989 | #define TX_SW_CFG2 0x1338 | |
| 990 | ||
| 991 | /* | |
| 992 | * TXOP_THRES_CFG: | |
| 993 | */ | |
| 994 | #define TXOP_THRES_CFG 0x133c | |
| 995 | ||
| 996 | /* | |
| 997 | * TXOP_CTRL_CFG: | |
| 961621ab HS |
998 | * TIMEOUT_TRUN_EN: Enable/Disable TXOP timeout truncation |
| 999 | * AC_TRUN_EN: Enable/Disable truncation for AC change | |
| 1000 | * TXRATEGRP_TRUN_EN: Enable/Disable truncation for TX rate group change | |
| 1001 | * USER_MODE_TRUN_EN: Enable/Disable truncation for user TXOP mode | |
| 1002 | * MIMO_PS_TRUN_EN: Enable/Disable truncation for MIMO PS RTS/CTS | |
| 1003 | * RESERVED_TRUN_EN: Reserved | |
| 1004 | * LSIG_TXOP_EN: Enable/Disable L-SIG TXOP protection | |
| 1005 | * EXT_CCA_EN: Enable/Disable extension channel CCA reference (Defer 40Mhz | |
| 1006 | * transmissions if extension CCA is clear). | |
| 1007 | * EXT_CCA_DLY: Extension CCA signal delay time (unit: us) | |
| 1008 | * EXT_CWMIN: CwMin for extension channel backoff | |
| 1009 | * 0: Disabled | |
| 1010 | * | |
| b54f78a8 BZ |
1011 | */ |
| 1012 | #define TXOP_CTRL_CFG 0x1340 | |
| 961621ab HS |
1013 | #define TXOP_CTRL_CFG_TIMEOUT_TRUN_EN FIELD32(0x00000001) |
| 1014 | #define TXOP_CTRL_CFG_AC_TRUN_EN FIELD32(0x00000002) | |
| 1015 | #define TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN FIELD32(0x00000004) | |
| 1016 | #define TXOP_CTRL_CFG_USER_MODE_TRUN_EN FIELD32(0x00000008) | |
| 1017 | #define TXOP_CTRL_CFG_MIMO_PS_TRUN_EN FIELD32(0x00000010) | |
| 1018 | #define TXOP_CTRL_CFG_RESERVED_TRUN_EN FIELD32(0x00000020) | |
| 1019 | #define TXOP_CTRL_CFG_LSIG_TXOP_EN FIELD32(0x00000040) | |
| 1020 | #define TXOP_CTRL_CFG_EXT_CCA_EN FIELD32(0x00000080) | |
| 1021 | #define TXOP_CTRL_CFG_EXT_CCA_DLY FIELD32(0x0000ff00) | |
| 1022 | #define TXOP_CTRL_CFG_EXT_CWMIN FIELD32(0x000f0000) | |
| b54f78a8 BZ |
1023 | |
| 1024 | /* | |
| 1025 | * TX_RTS_CFG: | |
| 1026 | * RTS_THRES: unit:byte | |
| 1027 | * RTS_FBK_EN: enable rts rate fallback | |
| 1028 | */ | |
| 1029 | #define TX_RTS_CFG 0x1344 | |
| 1030 | #define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff) | |
| 1031 | #define TX_RTS_CFG_RTS_THRES FIELD32(0x00ffff00) | |
| 1032 | #define TX_RTS_CFG_RTS_FBK_EN FIELD32(0x01000000) | |
| 1033 | ||
| 1034 | /* | |
| 1035 | * TX_TIMEOUT_CFG: | |
| 1036 | * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us | |
| 1037 | * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure | |
| 1038 | * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation. | |
| 1039 | * it is recommended that: | |
| 1040 | * (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT) | |
| 1041 | */ | |
| 1042 | #define TX_TIMEOUT_CFG 0x1348 | |
| 1043 | #define TX_TIMEOUT_CFG_MPDU_LIFETIME FIELD32(0x000000f0) | |
| 1044 | #define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT FIELD32(0x0000ff00) | |
| 1045 | #define TX_TIMEOUT_CFG_TX_OP_TIMEOUT FIELD32(0x00ff0000) | |
| 1046 | ||
| 1047 | /* | |
| 1048 | * TX_RTY_CFG: | |
| 1049 | * SHORT_RTY_LIMIT: short retry limit | |
| 1050 | * LONG_RTY_LIMIT: long retry limit | |
| 1051 | * LONG_RTY_THRE: Long retry threshoold | |
| 1052 | * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode | |
| 1053 | * 0:expired by retry limit, 1: expired by mpdu life timer | |
| 1054 | * AGG_RTY_MODE: Aggregate MPDU retry mode | |
| 1055 | * 0:expired by retry limit, 1: expired by mpdu life timer | |
| 1056 | * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable | |
| 1057 | */ | |
| 1058 | #define TX_RTY_CFG 0x134c | |
| 1059 | #define TX_RTY_CFG_SHORT_RTY_LIMIT FIELD32(0x000000ff) | |
| 1060 | #define TX_RTY_CFG_LONG_RTY_LIMIT FIELD32(0x0000ff00) | |
| 1061 | #define TX_RTY_CFG_LONG_RTY_THRE FIELD32(0x0fff0000) | |
| 1062 | #define TX_RTY_CFG_NON_AGG_RTY_MODE FIELD32(0x10000000) | |
| 1063 | #define TX_RTY_CFG_AGG_RTY_MODE FIELD32(0x20000000) | |
| 1064 | #define TX_RTY_CFG_TX_AUTO_FB_ENABLE FIELD32(0x40000000) | |
| 1065 | ||
| 1066 | /* | |
| 1067 | * TX_LINK_CFG: | |
| 1068 | * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us | |
| 1069 | * MFB_ENABLE: TX apply remote MFB 1:enable | |
| 1070 | * REMOTE_UMFS_ENABLE: remote unsolicit MFB enable | |
| 1071 | * 0: not apply remote remote unsolicit (MFS=7) | |
| 1072 | * TX_MRQ_EN: MCS request TX enable | |
| 1073 | * TX_RDG_EN: RDG TX enable | |
| 1074 | * TX_CF_ACK_EN: Piggyback CF-ACK enable | |
| 1075 | * REMOTE_MFB: remote MCS feedback | |
| 1076 | * REMOTE_MFS: remote MCS feedback sequence number | |
| 1077 | */ | |
| 1078 | #define TX_LINK_CFG 0x1350 | |
| 1079 | #define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff) | |
| 1080 | #define TX_LINK_CFG_MFB_ENABLE FIELD32(0x00000100) | |
| 1081 | #define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200) | |
| 1082 | #define TX_LINK_CFG_TX_MRQ_EN FIELD32(0x00000400) | |
| 1083 | #define TX_LINK_CFG_TX_RDG_EN FIELD32(0x00000800) | |
| 1084 | #define TX_LINK_CFG_TX_CF_ACK_EN FIELD32(0x00001000) | |
| 1085 | #define TX_LINK_CFG_REMOTE_MFB FIELD32(0x00ff0000) | |
| 1086 | #define TX_LINK_CFG_REMOTE_MFS FIELD32(0xff000000) | |
| 1087 | ||
| 1088 | /* | |
| 1089 | * HT_FBK_CFG0: | |
| 1090 | */ | |
| 1091 | #define HT_FBK_CFG0 0x1354 | |
| 1092 | #define HT_FBK_CFG0_HTMCS0FBK FIELD32(0x0000000f) | |
| 1093 | #define HT_FBK_CFG0_HTMCS1FBK FIELD32(0x000000f0) | |
| 1094 | #define HT_FBK_CFG0_HTMCS2FBK FIELD32(0x00000f00) | |
| 1095 | #define HT_FBK_CFG0_HTMCS3FBK FIELD32(0x0000f000) | |
| 1096 | #define HT_FBK_CFG0_HTMCS4FBK FIELD32(0x000f0000) | |
| 1097 | #define HT_FBK_CFG0_HTMCS5FBK FIELD32(0x00f00000) | |
| 1098 | #define HT_FBK_CFG0_HTMCS6FBK FIELD32(0x0f000000) | |
| 1099 | #define HT_FBK_CFG0_HTMCS7FBK FIELD32(0xf0000000) | |
| 1100 | ||
| 1101 | /* | |
| 1102 | * HT_FBK_CFG1: | |
| 1103 | */ | |
| 1104 | #define HT_FBK_CFG1 0x1358 | |
| 1105 | #define HT_FBK_CFG1_HTMCS8FBK FIELD32(0x0000000f) | |
| 1106 | #define HT_FBK_CFG1_HTMCS9FBK FIELD32(0x000000f0) | |
| 1107 | #define HT_FBK_CFG1_HTMCS10FBK FIELD32(0x00000f00) | |
| 1108 | #define HT_FBK_CFG1_HTMCS11FBK FIELD32(0x0000f000) | |
| 1109 | #define HT_FBK_CFG1_HTMCS12FBK FIELD32(0x000f0000) | |
| 1110 | #define HT_FBK_CFG1_HTMCS13FBK FIELD32(0x00f00000) | |
| 1111 | #define HT_FBK_CFG1_HTMCS14FBK FIELD32(0x0f000000) | |
| 1112 | #define HT_FBK_CFG1_HTMCS15FBK FIELD32(0xf0000000) | |
| 1113 | ||
| 1114 | /* | |
| 1115 | * LG_FBK_CFG0: | |
| 1116 | */ | |
| 1117 | #define LG_FBK_CFG0 0x135c | |
| 1118 | #define LG_FBK_CFG0_OFDMMCS0FBK FIELD32(0x0000000f) | |
| 1119 | #define LG_FBK_CFG0_OFDMMCS1FBK FIELD32(0x000000f0) | |
| 1120 | #define LG_FBK_CFG0_OFDMMCS2FBK FIELD32(0x00000f00) | |
| 1121 | #define LG_FBK_CFG0_OFDMMCS3FBK FIELD32(0x0000f000) | |
| 1122 | #define LG_FBK_CFG0_OFDMMCS4FBK FIELD32(0x000f0000) | |
| 1123 | #define LG_FBK_CFG0_OFDMMCS5FBK FIELD32(0x00f00000) | |
| 1124 | #define LG_FBK_CFG0_OFDMMCS6FBK FIELD32(0x0f000000) | |
| 1125 | #define LG_FBK_CFG0_OFDMMCS7FBK FIELD32(0xf0000000) | |
| 1126 | ||
| 1127 | /* | |
| 1128 | * LG_FBK_CFG1: | |
| 1129 | */ | |
| 1130 | #define LG_FBK_CFG1 0x1360 | |
| 1131 | #define LG_FBK_CFG0_CCKMCS0FBK FIELD32(0x0000000f) | |
| 1132 | #define LG_FBK_CFG0_CCKMCS1FBK FIELD32(0x000000f0) | |
| 1133 | #define LG_FBK_CFG0_CCKMCS2FBK FIELD32(0x00000f00) | |
| 1134 | #define LG_FBK_CFG0_CCKMCS3FBK FIELD32(0x0000f000) | |
| 1135 | ||
| 1136 | /* | |
| 1137 | * CCK_PROT_CFG: CCK Protection | |
| 1138 | * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd) | |
| 1139 | * PROTECT_CTRL: Protection control frame type for CCK TX | |
| 1140 | * 0:none, 1:RTS/CTS, 2:CTS-to-self | |
| 1141 | * PROTECT_NAV: TXOP protection type for CCK TX | |
| 1142 | * 0:none, 1:ShortNAVprotect, 2:LongNAVProtect | |
| 1143 | * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow | |
| 1144 | * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow | |
| 1145 | * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow | |
| 1146 | * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow | |
| 1147 | * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow | |
| 1148 | * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow | |
| 1149 | * RTS_TH_EN: RTS threshold enable on CCK TX | |
| 1150 | */ | |
| 1151 | #define CCK_PROT_CFG 0x1364 | |
| 1152 | #define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) | |
| 1153 | #define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) | |
| 1154 | #define CCK_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000) | |
| 1155 | #define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) | |
| 1156 | #define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) | |
| 1157 | #define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) | |
| 1158 | #define CCK_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000) | |
| 1159 | #define CCK_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000) | |
| 1160 | #define CCK_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000) | |
| 1161 | #define CCK_PROT_CFG_RTS_TH_EN FIELD32(0x04000000) | |
| 1162 | ||
| 1163 | /* | |
| 1164 | * OFDM_PROT_CFG: OFDM Protection | |
| 1165 | */ | |
| 1166 | #define OFDM_PROT_CFG 0x1368 | |
| 1167 | #define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) | |
| 1168 | #define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) | |
| 1169 | #define OFDM_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000) | |
| 1170 | #define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) | |
| 1171 | #define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) | |
| 1172 | #define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) | |
| 1173 | #define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000) | |
| 1174 | #define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000) | |
| 1175 | #define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000) | |
| 1176 | #define OFDM_PROT_CFG_RTS_TH_EN FIELD32(0x04000000) | |
| 1177 | ||
| 1178 | /* | |
| 1179 | * MM20_PROT_CFG: MM20 Protection | |
| 1180 | */ | |
| 1181 | #define MM20_PROT_CFG 0x136c | |
| 1182 | #define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) | |
| 1183 | #define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) | |
| 1184 | #define MM20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000) | |
| 1185 | #define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) | |
| 1186 | #define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) | |
| 1187 | #define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) | |
| 1188 | #define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000) | |
| 1189 | #define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000) | |
| 1190 | #define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000) | |
| 1191 | #define MM20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000) | |
| 1192 | ||
| 1193 | /* | |
| 1194 | * MM40_PROT_CFG: MM40 Protection | |
| 1195 | */ | |
| 1196 | #define MM40_PROT_CFG 0x1370 | |
| 1197 | #define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) | |
| 1198 | #define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) | |
| 1199 | #define MM40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000) | |
| 1200 | #define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) | |
| 1201 | #define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) | |
| 1202 | #define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) | |
| 1203 | #define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000) | |
| 1204 | #define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000) | |
| 1205 | #define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000) | |
| 1206 | #define MM40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000) | |
| 1207 | ||
| 1208 | /* | |
| 1209 | * GF20_PROT_CFG: GF20 Protection | |
| 1210 | */ | |
| 1211 | #define GF20_PROT_CFG 0x1374 | |
| 1212 | #define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) | |
| 1213 | #define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) | |
| 1214 | #define GF20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000) | |
| 1215 | #define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) | |
| 1216 | #define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) | |
| 1217 | #define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) | |
| 1218 | #define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000) | |
| 1219 | #define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000) | |
| 1220 | #define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000) | |
| 1221 | #define GF20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000) | |
| 1222 | ||
| 1223 | /* | |
| 1224 | * GF40_PROT_CFG: GF40 Protection | |
| 1225 | */ | |
| 1226 | #define GF40_PROT_CFG 0x1378 | |
| 1227 | #define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) | |
| 1228 | #define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) | |
| 1229 | #define GF40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000) | |
| 1230 | #define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) | |
| 1231 | #define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) | |
| 1232 | #define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) | |
| 1233 | #define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000) | |
| 1234 | #define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000) | |
| 1235 | #define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000) | |
| 1236 | #define GF40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000) | |
| 1237 | ||
| 1238 | /* | |
| 1239 | * EXP_CTS_TIME: | |
| 1240 | */ | |
| 1241 | #define EXP_CTS_TIME 0x137c | |
| 1242 | ||
| 1243 | /* | |
| 1244 | * EXP_ACK_TIME: | |
| 1245 | */ | |
| 1246 | #define EXP_ACK_TIME 0x1380 | |
| 1247 | ||
| 1248 | /* | |
| 1249 | * RX_FILTER_CFG: RX configuration register. | |
| 1250 | */ | |
| 1251 | #define RX_FILTER_CFG 0x1400 | |
| 1252 | #define RX_FILTER_CFG_DROP_CRC_ERROR FIELD32(0x00000001) | |
| 1253 | #define RX_FILTER_CFG_DROP_PHY_ERROR FIELD32(0x00000002) | |
| 1254 | #define RX_FILTER_CFG_DROP_NOT_TO_ME FIELD32(0x00000004) | |
| 1255 | #define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008) | |
| 1256 | #define RX_FILTER_CFG_DROP_VER_ERROR FIELD32(0x00000010) | |
| 1257 | #define RX_FILTER_CFG_DROP_MULTICAST FIELD32(0x00000020) | |
| 1258 | #define RX_FILTER_CFG_DROP_BROADCAST FIELD32(0x00000040) | |
| 1259 | #define RX_FILTER_CFG_DROP_DUPLICATE FIELD32(0x00000080) | |
| 1260 | #define RX_FILTER_CFG_DROP_CF_END_ACK FIELD32(0x00000100) | |
| 1261 | #define RX_FILTER_CFG_DROP_CF_END FIELD32(0x00000200) | |
| 1262 | #define RX_FILTER_CFG_DROP_ACK FIELD32(0x00000400) | |
| 1263 | #define RX_FILTER_CFG_DROP_CTS FIELD32(0x00000800) | |
| 1264 | #define RX_FILTER_CFG_DROP_RTS FIELD32(0x00001000) | |
| 1265 | #define RX_FILTER_CFG_DROP_PSPOLL FIELD32(0x00002000) | |
| 1266 | #define RX_FILTER_CFG_DROP_BA FIELD32(0x00004000) | |
| 1267 | #define RX_FILTER_CFG_DROP_BAR FIELD32(0x00008000) | |
| 1268 | #define RX_FILTER_CFG_DROP_CNTL FIELD32(0x00010000) | |
| 1269 | ||
| 1270 | /* | |
| 1271 | * AUTO_RSP_CFG: | |
| 1272 | * AUTORESPONDER: 0: disable, 1: enable | |
| 1273 | * BAC_ACK_POLICY: 0:long, 1:short preamble | |
| 1274 | * CTS_40_MMODE: Response CTS 40MHz duplicate mode | |
| 1275 | * CTS_40_MREF: Response CTS 40MHz duplicate mode | |
| 1276 | * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble | |
| 1277 | * DUAL_CTS_EN: Power bit value in control frame | |
| 1278 | * ACK_CTS_PSM_BIT:Power bit value in control frame | |
| 1279 | */ | |
| 1280 | #define AUTO_RSP_CFG 0x1404 | |
| 1281 | #define AUTO_RSP_CFG_AUTORESPONDER FIELD32(0x00000001) | |
| 1282 | #define AUTO_RSP_CFG_BAC_ACK_POLICY FIELD32(0x00000002) | |
| 1283 | #define AUTO_RSP_CFG_CTS_40_MMODE FIELD32(0x00000004) | |
| 1284 | #define AUTO_RSP_CFG_CTS_40_MREF FIELD32(0x00000008) | |
| 1285 | #define AUTO_RSP_CFG_AR_PREAMBLE FIELD32(0x00000010) | |
| 1286 | #define AUTO_RSP_CFG_DUAL_CTS_EN FIELD32(0x00000040) | |
| 1287 | #define AUTO_RSP_CFG_ACK_CTS_PSM_BIT FIELD32(0x00000080) | |
| 1288 | ||
| 1289 | /* | |
| 1290 | * LEGACY_BASIC_RATE: | |
| 1291 | */ | |
| 1292 | #define LEGACY_BASIC_RATE 0x1408 | |
| 1293 | ||
| 1294 | /* | |
| 1295 | * HT_BASIC_RATE: | |
| 1296 | */ | |
| 1297 | #define HT_BASIC_RATE 0x140c | |
| 1298 | ||
| 1299 | /* | |
| 1300 | * HT_CTRL_CFG: | |
| 1301 | */ | |
| 1302 | #define HT_CTRL_CFG 0x1410 | |
| 1303 | ||
| 1304 | /* | |
| 1305 | * SIFS_COST_CFG: | |
| 1306 | */ | |
| 1307 | #define SIFS_COST_CFG 0x1414 | |
| 1308 | ||
| 1309 | /* | |
| 1310 | * RX_PARSER_CFG: | |
| 1311 | * Set NAV for all received frames | |
| 1312 | */ | |
| 1313 | #define RX_PARSER_CFG 0x1418 | |
| 1314 | ||
| 1315 | /* | |
| 1316 | * TX_SEC_CNT0: | |
| 1317 | */ | |
| 1318 | #define TX_SEC_CNT0 0x1500 | |
| 1319 | ||
| 1320 | /* | |
| 1321 | * RX_SEC_CNT0: | |
| 1322 | */ | |
| 1323 | #define RX_SEC_CNT0 0x1504 | |
| 1324 | ||
| 1325 | /* | |
| 1326 | * CCMP_FC_MUTE: | |
| 1327 | */ | |
| 1328 | #define CCMP_FC_MUTE 0x1508 | |
| 1329 | ||
| 1330 | /* | |
| 1331 | * TXOP_HLDR_ADDR0: | |
| 1332 | */ | |
| 1333 | #define TXOP_HLDR_ADDR0 0x1600 | |
| 1334 | ||
| 1335 | /* | |
| 1336 | * TXOP_HLDR_ADDR1: | |
| 1337 | */ | |
| 1338 | #define TXOP_HLDR_ADDR1 0x1604 | |
| 1339 | ||
| 1340 | /* | |
| 1341 | * TXOP_HLDR_ET: | |
| 1342 | */ | |
| 1343 | #define TXOP_HLDR_ET 0x1608 | |
| 1344 | ||
| 1345 | /* | |
| 1346 | * QOS_CFPOLL_RA_DW0: | |
| 1347 | */ | |
| 1348 | #define QOS_CFPOLL_RA_DW0 0x160c | |
| 1349 | ||
| 1350 | /* | |
| 1351 | * QOS_CFPOLL_RA_DW1: | |
| 1352 | */ | |
| 1353 | #define QOS_CFPOLL_RA_DW1 0x1610 | |
| 1354 | ||
| 1355 | /* | |
| 1356 | * QOS_CFPOLL_QC: | |
| 1357 | */ | |
| 1358 | #define QOS_CFPOLL_QC 0x1614 | |
| 1359 | ||
| 1360 | /* | |
| 1361 | * RX_STA_CNT0: RX PLCP error count & RX CRC error count | |
| 1362 | */ | |
| 1363 | #define RX_STA_CNT0 0x1700 | |
| 1364 | #define RX_STA_CNT0_CRC_ERR FIELD32(0x0000ffff) | |
| 1365 | #define RX_STA_CNT0_PHY_ERR FIELD32(0xffff0000) | |
| 1366 | ||
| 1367 | /* | |
| 1368 | * RX_STA_CNT1: RX False CCA count & RX LONG frame count | |
| 1369 | */ | |
| 1370 | #define RX_STA_CNT1 0x1704 | |
| 1371 | #define RX_STA_CNT1_FALSE_CCA FIELD32(0x0000ffff) | |
| 1372 | #define RX_STA_CNT1_PLCP_ERR FIELD32(0xffff0000) | |
| 1373 | ||
| 1374 | /* | |
| 1375 | * RX_STA_CNT2: | |
| 1376 | */ | |
| 1377 | #define RX_STA_CNT2 0x1708 | |
| 1378 | #define RX_STA_CNT2_RX_DUPLI_COUNT FIELD32(0x0000ffff) | |
| 1379 | #define RX_STA_CNT2_RX_FIFO_OVERFLOW FIELD32(0xffff0000) | |
| 1380 | ||
| 1381 | /* | |
| 1382 | * TX_STA_CNT0: TX Beacon count | |
| 1383 | */ | |
| 1384 | #define TX_STA_CNT0 0x170c | |
| 1385 | #define TX_STA_CNT0_TX_FAIL_COUNT FIELD32(0x0000ffff) | |
| 1386 | #define TX_STA_CNT0_TX_BEACON_COUNT FIELD32(0xffff0000) | |
| 1387 | ||
| 1388 | /* | |
| 1389 | * TX_STA_CNT1: TX tx count | |
| 1390 | */ | |
| 1391 | #define TX_STA_CNT1 0x1710 | |
| 1392 | #define TX_STA_CNT1_TX_SUCCESS FIELD32(0x0000ffff) | |
| 1393 | #define TX_STA_CNT1_TX_RETRANSMIT FIELD32(0xffff0000) | |
| 1394 | ||
| 1395 | /* | |
| 1396 | * TX_STA_CNT2: TX tx count | |
| 1397 | */ | |
| 1398 | #define TX_STA_CNT2 0x1714 | |
| 1399 | #define TX_STA_CNT2_TX_ZERO_LEN_COUNT FIELD32(0x0000ffff) | |
| 1400 | #define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000) | |
| 1401 | ||
| 1402 | /* | |
| 0856d9c0 HS |
1403 | * TX_STA_FIFO: TX Result for specific PID status fifo register. |
| 1404 | * | |
| 1405 | * This register is implemented as FIFO with 16 entries in the HW. Each | |
| 1406 | * register read fetches the next tx result. If the FIFO is full because | |
| 1407 | * it wasn't read fast enough after the according interrupt (TX_FIFO_STATUS) | |
| 1408 | * triggered, the hw seems to simply drop further tx results. | |
| 1409 | * | |
| 1410 | * VALID: 1: this tx result is valid | |
| 1411 | * 0: no valid tx result -> driver should stop reading | |
| 1412 | * PID_TYPE: The PID latched from the PID field in the TXWI, can be used | |
| 1413 | * to match a frame with its tx result (even though the PID is | |
| 1414 | * only 4 bits wide). | |
| bc8a979e ID |
1415 | * PID_QUEUE: Part of PID_TYPE, this is the queue index number (0-3) |
| 1416 | * PID_ENTRY: Part of PID_TYPE, this is the queue entry index number (1-3) | |
| 1417 | * This identification number is calculated by ((idx % 3) + 1). | |
| 0856d9c0 HS |
1418 | * TX_SUCCESS: Indicates tx success (1) or failure (0) |
| 1419 | * TX_AGGRE: Indicates if the frame was part of an aggregate (1) or not (0) | |
| 1420 | * TX_ACK_REQUIRED: Indicates if the frame needed to get ack'ed (1) or not (0) | |
| 1421 | * WCID: The wireless client ID. | |
| 1422 | * MCS: The tx rate used during the last transmission of this frame, be it | |
| 1423 | * successful or not. | |
| 1424 | * PHYMODE: The phymode used for the transmission. | |
| b54f78a8 BZ |
1425 | */ |
| 1426 | #define TX_STA_FIFO 0x1718 | |
| 1427 | #define TX_STA_FIFO_VALID FIELD32(0x00000001) | |
| 1428 | #define TX_STA_FIFO_PID_TYPE FIELD32(0x0000001e) | |
| bc8a979e ID |
1429 | #define TX_STA_FIFO_PID_QUEUE FIELD32(0x00000006) |
| 1430 | #define TX_STA_FIFO_PID_ENTRY FIELD32(0x00000018) | |
| b54f78a8 BZ |
1431 | #define TX_STA_FIFO_TX_SUCCESS FIELD32(0x00000020) |
| 1432 | #define TX_STA_FIFO_TX_AGGRE FIELD32(0x00000040) | |
| 1433 | #define TX_STA_FIFO_TX_ACK_REQUIRED FIELD32(0x00000080) | |
| 1434 | #define TX_STA_FIFO_WCID FIELD32(0x0000ff00) | |
| 1435 | #define TX_STA_FIFO_SUCCESS_RATE FIELD32(0xffff0000) | |
| 1436 | #define TX_STA_FIFO_MCS FIELD32(0x007f0000) | |
| 1437 | #define TX_STA_FIFO_PHYMODE FIELD32(0xc0000000) | |
| 1438 | ||
| 1439 | /* | |
| 1440 | * TX_AGG_CNT: Debug counter | |
| 1441 | */ | |
| 1442 | #define TX_AGG_CNT 0x171c | |
| 1443 | #define TX_AGG_CNT_NON_AGG_TX_COUNT FIELD32(0x0000ffff) | |
| 1444 | #define TX_AGG_CNT_AGG_TX_COUNT FIELD32(0xffff0000) | |
| 1445 | ||
| 1446 | /* | |
| 1447 | * TX_AGG_CNT0: | |
| 1448 | */ | |
| 1449 | #define TX_AGG_CNT0 0x1720 | |
| 1450 | #define TX_AGG_CNT0_AGG_SIZE_1_COUNT FIELD32(0x0000ffff) | |
| 1451 | #define TX_AGG_CNT0_AGG_SIZE_2_COUNT FIELD32(0xffff0000) | |
| 1452 | ||
| 1453 | /* | |
| 1454 | * TX_AGG_CNT1: | |
| 1455 | */ | |
| 1456 | #define TX_AGG_CNT1 0x1724 | |
| 1457 | #define TX_AGG_CNT1_AGG_SIZE_3_COUNT FIELD32(0x0000ffff) | |
| 1458 | #define TX_AGG_CNT1_AGG_SIZE_4_COUNT FIELD32(0xffff0000) | |
| 1459 | ||
| 1460 | /* | |
| 1461 | * TX_AGG_CNT2: | |
| 1462 | */ | |
| 1463 | #define TX_AGG_CNT2 0x1728 | |
| 1464 | #define TX_AGG_CNT2_AGG_SIZE_5_COUNT FIELD32(0x0000ffff) | |
| 1465 | #define TX_AGG_CNT2_AGG_SIZE_6_COUNT FIELD32(0xffff0000) | |
| 1466 | ||
| 1467 | /* | |
| 1468 | * TX_AGG_CNT3: | |
| 1469 | */ | |
| 1470 | #define TX_AGG_CNT3 0x172c | |
| 1471 | #define TX_AGG_CNT3_AGG_SIZE_7_COUNT FIELD32(0x0000ffff) | |
| 1472 | #define TX_AGG_CNT3_AGG_SIZE_8_COUNT FIELD32(0xffff0000) | |
| 1473 | ||
| 1474 | /* | |
| 1475 | * TX_AGG_CNT4: | |
| 1476 | */ | |
| 1477 | #define TX_AGG_CNT4 0x1730 | |
| 1478 | #define TX_AGG_CNT4_AGG_SIZE_9_COUNT FIELD32(0x0000ffff) | |
| 1479 | #define TX_AGG_CNT4_AGG_SIZE_10_COUNT FIELD32(0xffff0000) | |
| 1480 | ||
| 1481 | /* | |
| 1482 | * TX_AGG_CNT5: | |
| 1483 | */ | |
| 1484 | #define TX_AGG_CNT5 0x1734 | |
| 1485 | #define TX_AGG_CNT5_AGG_SIZE_11_COUNT FIELD32(0x0000ffff) | |
| 1486 | #define TX_AGG_CNT5_AGG_SIZE_12_COUNT FIELD32(0xffff0000) | |
| 1487 | ||
| 1488 | /* | |
| 1489 | * TX_AGG_CNT6: | |
| 1490 | */ | |
| 1491 | #define TX_AGG_CNT6 0x1738 | |
| 1492 | #define TX_AGG_CNT6_AGG_SIZE_13_COUNT FIELD32(0x0000ffff) | |
| 1493 | #define TX_AGG_CNT6_AGG_SIZE_14_COUNT FIELD32(0xffff0000) | |
| 1494 | ||
| 1495 | /* | |
| 1496 | * TX_AGG_CNT7: | |
| 1497 | */ | |
| 1498 | #define TX_AGG_CNT7 0x173c | |
| 1499 | #define TX_AGG_CNT7_AGG_SIZE_15_COUNT FIELD32(0x0000ffff) | |
| 1500 | #define TX_AGG_CNT7_AGG_SIZE_16_COUNT FIELD32(0xffff0000) | |
| 1501 | ||
| 1502 | /* | |
| 1503 | * MPDU_DENSITY_CNT: | |
| 1504 | * TX_ZERO_DEL: TX zero length delimiter count | |
| 1505 | * RX_ZERO_DEL: RX zero length delimiter count | |
| 1506 | */ | |
| 1507 | #define MPDU_DENSITY_CNT 0x1740 | |
| 1508 | #define MPDU_DENSITY_CNT_TX_ZERO_DEL FIELD32(0x0000ffff) | |
| 1509 | #define MPDU_DENSITY_CNT_RX_ZERO_DEL FIELD32(0xffff0000) | |
| 1510 | ||
| 1511 | /* | |
| 1512 | * Security key table memory. | |
| 2a0cfeb8 HS |
1513 | * |
| 1514 | * The pairwise key table shares some memory with the beacon frame | |
| 1515 | * buffers 6 and 7. That basically means that when beacon 6 & 7 | |
| 1516 | * are used we should only use the reduced pairwise key table which | |
| 1517 | * has a maximum of 222 entries. | |
| 1518 | * | |
| 1519 | * --------------------------------------------- | |
| 1520 | * |0x4000 | Pairwise Key | Reduced Pairwise | | |
| 1521 | * | | Table | Key Table | | |
| 1522 | * | | Size: 256 * 32 | Size: 222 * 32 | | |
| 1523 | * |0x5BC0 | |------------------- | |
| 1524 | * | | | Beacon 6 | | |
| 1525 | * |0x5DC0 | |------------------- | |
| 1526 | * | | | Beacon 7 | | |
| 1527 | * |0x5FC0 | |------------------- | |
| 1528 | * |0x5FFF | | | |
| 1529 | * -------------------------- | |
| 1530 | * | |
| b54f78a8 BZ |
1531 | * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry |
| 1532 | * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry | |
| 1533 | * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry | |
| 1534 | * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry | |
| a4385213 BZ |
1535 | * SHARED_KEY_TABLE_BASE: 32-byte * 16-entry |
| 1536 | * SHARED_KEY_MODE_BASE: 4-byte * 16-entry | |
| b54f78a8 BZ |
1537 | */ |
| 1538 | #define MAC_WCID_BASE 0x1800 | |
| 1539 | #define PAIRWISE_KEY_TABLE_BASE 0x4000 | |
| 1540 | #define MAC_IVEIV_TABLE_BASE 0x6000 | |
| 1541 | #define MAC_WCID_ATTRIBUTE_BASE 0x6800 | |
| 1542 | #define SHARED_KEY_TABLE_BASE 0x6c00 | |
| 1543 | #define SHARED_KEY_MODE_BASE 0x7000 | |
| 1544 | ||
| 1545 | #define MAC_WCID_ENTRY(__idx) \ | |
| fd8dab9a | 1546 | (MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry))) |
| b54f78a8 | 1547 | #define PAIRWISE_KEY_ENTRY(__idx) \ |
| fd8dab9a | 1548 | (PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry))) |
| b54f78a8 | 1549 | #define MAC_IVEIV_ENTRY(__idx) \ |
| fd8dab9a | 1550 | (MAC_IVEIV_TABLE_BASE + ((__idx) * sizeof(struct mac_iveiv_entry))) |
| b54f78a8 | 1551 | #define MAC_WCID_ATTR_ENTRY(__idx) \ |
| fd8dab9a | 1552 | (MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32))) |
| b54f78a8 | 1553 | #define SHARED_KEY_ENTRY(__idx) \ |
| fd8dab9a | 1554 | (SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry))) |
| b54f78a8 | 1555 | #define SHARED_KEY_MODE_ENTRY(__idx) \ |
| fd8dab9a | 1556 | (SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32))) |
| b54f78a8 BZ |
1557 | |
| 1558 | struct mac_wcid_entry { | |
| 1559 | u8 mac[6]; | |
| 1560 | u8 reserved[2]; | |
| ba2d3587 | 1561 | } __packed; |
| b54f78a8 BZ |
1562 | |
| 1563 | struct hw_key_entry { | |
| 1564 | u8 key[16]; | |
| 1565 | u8 tx_mic[8]; | |
| 1566 | u8 rx_mic[8]; | |
| ba2d3587 | 1567 | } __packed; |
| b54f78a8 BZ |
1568 | |
| 1569 | struct mac_iveiv_entry { | |
| 1570 | u8 iv[8]; | |
| ba2d3587 | 1571 | } __packed; |
| b54f78a8 BZ |
1572 | |
| 1573 | /* | |
| 1574 | * MAC_WCID_ATTRIBUTE: | |
| 1575 | */ | |
| 1576 | #define MAC_WCID_ATTRIBUTE_KEYTAB FIELD32(0x00000001) | |
| 1577 | #define MAC_WCID_ATTRIBUTE_CIPHER FIELD32(0x0000000e) | |
| 1578 | #define MAC_WCID_ATTRIBUTE_BSS_IDX FIELD32(0x00000070) | |
| 1579 | #define MAC_WCID_ATTRIBUTE_RX_WIUDF FIELD32(0x00000380) | |
| e4a0ab34 ID |
1580 | #define MAC_WCID_ATTRIBUTE_CIPHER_EXT FIELD32(0x00000400) |
| 1581 | #define MAC_WCID_ATTRIBUTE_BSS_IDX_EXT FIELD32(0x00000800) | |
| 1582 | #define MAC_WCID_ATTRIBUTE_WAPI_MCBC FIELD32(0x00008000) | |
| 1583 | #define MAC_WCID_ATTRIBUTE_WAPI_KEY_IDX FIELD32(0xff000000) | |
| b54f78a8 BZ |
1584 | |
| 1585 | /* | |
| 1586 | * SHARED_KEY_MODE: | |
| 1587 | */ | |
| 1588 | #define SHARED_KEY_MODE_BSS0_KEY0 FIELD32(0x00000007) | |
| 1589 | #define SHARED_KEY_MODE_BSS0_KEY1 FIELD32(0x00000070) | |
| 1590 | #define SHARED_KEY_MODE_BSS0_KEY2 FIELD32(0x00000700) | |
| 1591 | #define SHARED_KEY_MODE_BSS0_KEY3 FIELD32(0x00007000) | |
| 1592 | #define SHARED_KEY_MODE_BSS1_KEY0 FIELD32(0x00070000) | |
| 1593 | #define SHARED_KEY_MODE_BSS1_KEY1 FIELD32(0x00700000) | |
| 1594 | #define SHARED_KEY_MODE_BSS1_KEY2 FIELD32(0x07000000) | |
| 1595 | #define SHARED_KEY_MODE_BSS1_KEY3 FIELD32(0x70000000) | |
| 1596 | ||
| 1597 | /* | |
| 1598 | * HOST-MCU communication | |
| 1599 | */ | |
| 1600 | ||
| 1601 | /* | |
| 1602 | * H2M_MAILBOX_CSR: Host-to-MCU Mailbox. | |
| 1603 | */ | |
| 1604 | #define H2M_MAILBOX_CSR 0x7010 | |
| 1605 | #define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff) | |
| 1606 | #define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00) | |
| 1607 | #define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000) | |
| 1608 | #define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000) | |
| 1609 | ||
| 1610 | /* | |
| 1611 | * H2M_MAILBOX_CID: | |
| 1612 | */ | |
| 1613 | #define H2M_MAILBOX_CID 0x7014 | |
| 1614 | #define H2M_MAILBOX_CID_CMD0 FIELD32(0x000000ff) | |
| 1615 | #define H2M_MAILBOX_CID_CMD1 FIELD32(0x0000ff00) | |
| 1616 | #define H2M_MAILBOX_CID_CMD2 FIELD32(0x00ff0000) | |
| 1617 | #define H2M_MAILBOX_CID_CMD3 FIELD32(0xff000000) | |
| 1618 | ||
| 1619 | /* | |
| 1620 | * H2M_MAILBOX_STATUS: | |
| 1621 | */ | |
| 1622 | #define H2M_MAILBOX_STATUS 0x701c | |
| 1623 | ||
| 1624 | /* | |
| 1625 | * H2M_INT_SRC: | |
| 1626 | */ | |
| 1627 | #define H2M_INT_SRC 0x7024 | |
| 1628 | ||
| 1629 | /* | |
| 1630 | * H2M_BBP_AGENT: | |
| 1631 | */ | |
| 1632 | #define H2M_BBP_AGENT 0x7028 | |
| 1633 | ||
| 1634 | /* | |
| 1635 | * MCU_LEDCS: LED control for MCU Mailbox. | |
| 1636 | */ | |
| 1637 | #define MCU_LEDCS_LED_MODE FIELD8(0x1f) | |
| 1638 | #define MCU_LEDCS_POLARITY FIELD8(0x01) | |
| 1639 | ||
| 1640 | /* | |
| 1641 | * HW_CS_CTS_BASE: | |
| 1642 | * Carrier-sense CTS frame base address. | |
| 1643 | * It's where mac stores carrier-sense frame for carrier-sense function. | |
| 1644 | */ | |
| 1645 | #define HW_CS_CTS_BASE 0x7700 | |
| 1646 | ||
| 1647 | /* | |
| 1648 | * HW_DFS_CTS_BASE: | |
| a4385213 | 1649 | * DFS CTS frame base address. It's where mac stores CTS frame for DFS. |
| b54f78a8 BZ |
1650 | */ |
| 1651 | #define HW_DFS_CTS_BASE 0x7780 | |
| 1652 | ||
| 1653 | /* | |
| 1654 | * TXRX control registers - base address 0x3000 | |
| 1655 | */ | |
| 1656 | ||
| 1657 | /* | |
| 1658 | * TXRX_CSR1: | |
| 1659 | * rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first.. | |
| 1660 | */ | |
| 1661 | #define TXRX_CSR1 0x77d0 | |
| 1662 | ||
| 1663 | /* | |
| 1664 | * HW_DEBUG_SETTING_BASE: | |
| 1665 | * since NULL frame won't be that long (256 byte) | |
| 1666 | * We steal 16 tail bytes to save debugging settings | |
| 1667 | */ | |
| 1668 | #define HW_DEBUG_SETTING_BASE 0x77f0 | |
| 1669 | #define HW_DEBUG_SETTING_BASE2 0x7770 | |
| 1670 | ||
| 1671 | /* | |
| 1672 | * HW_BEACON_BASE | |
| 1673 | * In order to support maximum 8 MBSS and its maximum length | |
| 1674 | * is 512 bytes for each beacon | |
| 1675 | * Three section discontinue memory segments will be used. | |
| 1676 | * 1. The original region for BCN 0~3 | |
| 1677 | * 2. Extract memory from FCE table for BCN 4~5 | |
| 1678 | * 3. Extract memory from Pair-wise key table for BCN 6~7 | |
| 1679 | * It occupied those memory of wcid 238~253 for BCN 6 | |
| 2a0cfeb8 HS |
1680 | * and wcid 222~237 for BCN 7 (see Security key table memory |
| 1681 | * for more info). | |
| b54f78a8 BZ |
1682 | * |
| 1683 | * IMPORTANT NOTE: Not sure why legacy driver does this, | |
| 1684 | * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6. | |
| 1685 | */ | |
| 1686 | #define HW_BEACON_BASE0 0x7800 | |
| 1687 | #define HW_BEACON_BASE1 0x7a00 | |
| 1688 | #define HW_BEACON_BASE2 0x7c00 | |
| 1689 | #define HW_BEACON_BASE3 0x7e00 | |
| 1690 | #define HW_BEACON_BASE4 0x7200 | |
| 1691 | #define HW_BEACON_BASE5 0x7400 | |
| 1692 | #define HW_BEACON_BASE6 0x5dc0 | |
| 1693 | #define HW_BEACON_BASE7 0x5bc0 | |
| 1694 | ||
| 1695 | #define HW_BEACON_OFFSET(__index) \ | |
| fd8dab9a ME |
1696 | (((__index) < 4) ? (HW_BEACON_BASE0 + (__index * 0x0200)) : \ |
| 1697 | (((__index) < 6) ? (HW_BEACON_BASE4 + ((__index - 4) * 0x0200)) : \ | |
| 1698 | (HW_BEACON_BASE6 - ((__index - 6) * 0x0200)))) | |
| b54f78a8 BZ |
1699 | |
| 1700 | /* | |
| 1701 | * BBP registers. | |
| 1702 | * The wordsize of the BBP is 8 bits. | |
| 1703 | */ | |
| 1704 | ||
| 1705 | /* | |
| 52b58fac HS |
1706 | * BBP 1: TX Antenna & Power |
| 1707 | * POWER: 0 - normal, 1 - drop tx power by 6dBm, 2 - drop tx power by 12dBm, | |
| 1708 | * 3 - increase tx power by 6dBm | |
| b54f78a8 BZ |
1709 | */ |
| 1710 | #define BBP1_TX_POWER FIELD8(0x07) | |
| 1711 | #define BBP1_TX_ANTENNA FIELD8(0x18) | |
| 1712 | ||
| 1713 | /* | |
| 1714 | * BBP 3: RX Antenna | |
| 1715 | */ | |
| 1716 | #define BBP3_RX_ANTENNA FIELD8(0x18) | |
| a21ee724 | 1717 | #define BBP3_HT40_MINUS FIELD8(0x20) |
| b54f78a8 BZ |
1718 | |
| 1719 | /* | |
| 1720 | * BBP 4: Bandwidth | |
| 1721 | */ | |
| 1722 | #define BBP4_TX_BF FIELD8(0x01) | |
| 1723 | #define BBP4_BANDWIDTH FIELD8(0x18) | |
| 1724 | ||
| fab799c3 GW |
1725 | /* |
| 1726 | * BBP 138: Unknown | |
| 1727 | */ | |
| 1728 | #define BBP138_RX_ADC1 FIELD8(0x02) | |
| 1729 | #define BBP138_RX_ADC2 FIELD8(0x04) | |
| 1730 | #define BBP138_TX_DAC1 FIELD8(0x20) | |
| 1731 | #define BBP138_TX_DAC2 FIELD8(0x40) | |
| 1732 | ||
| b54f78a8 BZ |
1733 | /* |
| 1734 | * RFCSR registers | |
| 1735 | * The wordsize of the RFCSR is 8 bits. | |
| 1736 | */ | |
| 1737 | ||
| e148b4c8 GW |
1738 | /* |
| 1739 | * RFCSR 1: | |
| 1740 | */ | |
| 1741 | #define RFCSR1_RF_BLOCK_EN FIELD8(0x01) | |
| 1742 | #define RFCSR1_RX0_PD FIELD8(0x04) | |
| 1743 | #define RFCSR1_TX0_PD FIELD8(0x08) | |
| 1744 | #define RFCSR1_RX1_PD FIELD8(0x10) | |
| 1745 | #define RFCSR1_TX1_PD FIELD8(0x20) | |
| 1746 | ||
| b54f78a8 BZ |
1747 | /* |
| 1748 | * RFCSR 6: | |
| 1749 | */ | |
| fab799c3 GW |
1750 | #define RFCSR6_R1 FIELD8(0x03) |
| 1751 | #define RFCSR6_R2 FIELD8(0x40) | |
| b54f78a8 BZ |
1752 | |
| 1753 | /* | |
| 1754 | * RFCSR 7: | |
| 1755 | */ | |
| 1756 | #define RFCSR7_RF_TUNING FIELD8(0x01) | |
| 1757 | ||
| 1758 | /* | |
| 1759 | * RFCSR 12: | |
| 1760 | */ | |
| 1761 | #define RFCSR12_TX_POWER FIELD8(0x1f) | |
| 1762 | ||
| 5a673964 HS |
1763 | /* |
| 1764 | * RFCSR 13: | |
| 1765 | */ | |
| 1766 | #define RFCSR13_TX_POWER FIELD8(0x1f) | |
| 1767 | ||
| e148b4c8 GW |
1768 | /* |
| 1769 | * RFCSR 15: | |
| 1770 | */ | |
| 1771 | #define RFCSR15_TX_LO2_EN FIELD8(0x08) | |
| 1772 | ||
| fab799c3 GW |
1773 | /* |
| 1774 | * RFCSR 17: | |
| 1775 | */ | |
| e148b4c8 GW |
1776 | #define RFCSR17_TXMIXER_GAIN FIELD8(0x07) |
| 1777 | #define RFCSR17_TX_LO1_EN FIELD8(0x08) | |
| 1778 | #define RFCSR17_R FIELD8(0x20) | |
| fab799c3 | 1779 | |
| e148b4c8 GW |
1780 | /* |
| 1781 | * RFCSR 20: | |
| 1782 | */ | |
| 1783 | #define RFCSR20_RX_LO1_EN FIELD8(0x08) | |
| 1784 | ||
| 1785 | /* | |
| 1786 | * RFCSR 21: | |
| 1787 | */ | |
| 1788 | #define RFCSR21_RX_LO2_EN FIELD8(0x08) | |
| fab799c3 | 1789 | |
| b54f78a8 BZ |
1790 | /* |
| 1791 | * RFCSR 22: | |
| 1792 | */ | |
| 1793 | #define RFCSR22_BASEBAND_LOOPBACK FIELD8(0x01) | |
| 1794 | ||
| 1795 | /* | |
| 1796 | * RFCSR 23: | |
| 1797 | */ | |
| 1798 | #define RFCSR23_FREQ_OFFSET FIELD8(0x7f) | |
| 1799 | ||
| e148b4c8 GW |
1800 | /* |
| 1801 | * RFCSR 27: | |
| 1802 | */ | |
| 1803 | #define RFCSR27_R1 FIELD8(0x03) | |
| 1804 | #define RFCSR27_R2 FIELD8(0x04) | |
| 1805 | #define RFCSR27_R3 FIELD8(0x30) | |
| 1806 | #define RFCSR27_R4 FIELD8(0x40) | |
| 1807 | ||
| b54f78a8 BZ |
1808 | /* |
| 1809 | * RFCSR 30: | |
| 1810 | */ | |
| 1811 | #define RFCSR30_RF_CALIBRATION FIELD8(0x80) | |
| 1812 | ||
| 80d184e6 RJH |
1813 | /* |
| 1814 | * RFCSR 31: | |
| 1815 | */ | |
| 1816 | #define RFCSR31_RX_AGC_FC FIELD8(0x1f) | |
| 1817 | #define RFCSR31_RX_H20M FIELD8(0x20) | |
| 1818 | ||
| b54f78a8 BZ |
1819 | /* |
| 1820 | * RF registers | |
| 1821 | */ | |
| 1822 | ||
| 1823 | /* | |
| 1824 | * RF 2 | |
| 1825 | */ | |
| 1826 | #define RF2_ANTENNA_RX2 FIELD32(0x00000040) | |
| 1827 | #define RF2_ANTENNA_TX1 FIELD32(0x00004000) | |
| 1828 | #define RF2_ANTENNA_RX1 FIELD32(0x00020000) | |
| 1829 | ||
| 1830 | /* | |
| 1831 | * RF 3 | |
| 1832 | */ | |
| 1833 | #define RF3_TXPOWER_G FIELD32(0x00003e00) | |
| 1834 | #define RF3_TXPOWER_A_7DBM_BOOST FIELD32(0x00000200) | |
| 1835 | #define RF3_TXPOWER_A FIELD32(0x00003c00) | |
| 1836 | ||
| 1837 | /* | |
| 1838 | * RF 4 | |
| 1839 | */ | |
| 1840 | #define RF4_TXPOWER_G FIELD32(0x000007c0) | |
| 1841 | #define RF4_TXPOWER_A_7DBM_BOOST FIELD32(0x00000040) | |
| 1842 | #define RF4_TXPOWER_A FIELD32(0x00000780) | |
| 1843 | #define RF4_FREQ_OFFSET FIELD32(0x001f8000) | |
| 1844 | #define RF4_HT40 FIELD32(0x00200000) | |
| 1845 | ||
| 1846 | /* | |
| 1847 | * EEPROM content. | |
| 1848 | * The wordsize of the EEPROM is 16 bits. | |
| 1849 | */ | |
| 1850 | ||
| 1851 | /* | |
| 1852 | * EEPROM Version | |
| 1853 | */ | |
| 1854 | #define EEPROM_VERSION 0x0001 | |
| 1855 | #define EEPROM_VERSION_FAE FIELD16(0x00ff) | |
| 1856 | #define EEPROM_VERSION_VERSION FIELD16(0xff00) | |
| 1857 | ||
| 1858 | /* | |
| 1859 | * HW MAC address. | |
| 1860 | */ | |
| 1861 | #define EEPROM_MAC_ADDR_0 0x0002 | |
| 1862 | #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff) | |
| 1863 | #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00) | |
| 1864 | #define EEPROM_MAC_ADDR_1 0x0003 | |
| 1865 | #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff) | |
| 1866 | #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00) | |
| 1867 | #define EEPROM_MAC_ADDR_2 0x0004 | |
| 1868 | #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff) | |
| 1869 | #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00) | |
| 1870 | ||
| 1871 | /* | |
| 38c8a566 | 1872 | * EEPROM NIC Configuration 0 |
| b54f78a8 | 1873 | * RXPATH: 1: 1R, 2: 2R, 3: 3R |
| 38c8a566 RJH |
1874 | * TXPATH: 1: 1T, 2: 2T, 3: 3T |
| 1875 | * RF_TYPE: RFIC type | |
| 1876 | */ | |
| 1877 | #define EEPROM_NIC_CONF0 0x001a | |
| 1878 | #define EEPROM_NIC_CONF0_RXPATH FIELD16(0x000f) | |
| 1879 | #define EEPROM_NIC_CONF0_TXPATH FIELD16(0x00f0) | |
| 1880 | #define EEPROM_NIC_CONF0_RF_TYPE FIELD16(0x0f00) | |
| 1881 | ||
| 1882 | /* | |
| 1883 | * EEPROM NIC Configuration 1 | |
| 1884 | * HW_RADIO: 0: disable, 1: enable | |
| 1885 | * EXTERNAL_TX_ALC: 0: disable, 1: enable | |
| 1886 | * EXTERNAL_LNA_2G: 0: disable, 1: enable | |
| 1887 | * EXTERNAL_LNA_5G: 0: disable, 1: enable | |
| 1888 | * CARDBUS_ACCEL: 0: enable, 1: disable | |
| 1889 | * BW40M_SB_2G: 0: disable, 1: enable | |
| 1890 | * BW40M_SB_5G: 0: disable, 1: enable | |
| 1891 | * WPS_PBC: 0: disable, 1: enable | |
| 1892 | * BW40M_2G: 0: enable, 1: disable | |
| 1893 | * BW40M_5G: 0: enable, 1: disable | |
| 1894 | * BROADBAND_EXT_LNA: 0: disable, 1: enable | |
| 1895 | * ANT_DIVERSITY: 00: Disable, 01: Diversity, | |
| 1896 | * 10: Main antenna, 11: Aux antenna | |
| 1897 | * INTERNAL_TX_ALC: 0: disable, 1: enable | |
| 1898 | * BT_COEXIST: 0: disable, 1: enable | |
| 1899 | * DAC_TEST: 0: disable, 1: enable | |
| 1900 | */ | |
| 1901 | #define EEPROM_NIC_CONF1 0x001b | |
| 1902 | #define EEPROM_NIC_CONF1_HW_RADIO FIELD16(0x0001) | |
| 1903 | #define EEPROM_NIC_CONF1_EXTERNAL_TX_ALC FIELD16(0x0002) | |
| 1904 | #define EEPROM_NIC_CONF1_EXTERNAL_LNA_2G FIELD16(0x0004) | |
| 1905 | #define EEPROM_NIC_CONF1_EXTERNAL_LNA_5G FIELD16(0x0008) | |
| 1906 | #define EEPROM_NIC_CONF1_CARDBUS_ACCEL FIELD16(0x0010) | |
| 1907 | #define EEPROM_NIC_CONF1_BW40M_SB_2G FIELD16(0x0020) | |
| 1908 | #define EEPROM_NIC_CONF1_BW40M_SB_5G FIELD16(0x0040) | |
| 1909 | #define EEPROM_NIC_CONF1_WPS_PBC FIELD16(0x0080) | |
| 1910 | #define EEPROM_NIC_CONF1_BW40M_2G FIELD16(0x0100) | |
| 1911 | #define EEPROM_NIC_CONF1_BW40M_5G FIELD16(0x0200) | |
| 1912 | #define EEPROM_NIC_CONF1_BROADBAND_EXT_LNA FIELD16(0x400) | |
| 1913 | #define EEPROM_NIC_CONF1_ANT_DIVERSITY FIELD16(0x1800) | |
| 1914 | #define EEPROM_NIC_CONF1_INTERNAL_TX_ALC FIELD16(0x2000) | |
| 1915 | #define EEPROM_NIC_CONF1_BT_COEXIST FIELD16(0x4000) | |
| 1916 | #define EEPROM_NIC_CONF1_DAC_TEST FIELD16(0x8000) | |
| b54f78a8 BZ |
1917 | |
| 1918 | /* | |
| 1919 | * EEPROM frequency | |
| 1920 | */ | |
| 1921 | #define EEPROM_FREQ 0x001d | |
| 1922 | #define EEPROM_FREQ_OFFSET FIELD16(0x00ff) | |
| 1923 | #define EEPROM_FREQ_LED_MODE FIELD16(0x7f00) | |
| 1924 | #define EEPROM_FREQ_LED_POLARITY FIELD16(0x1000) | |
| 1925 | ||
| 1926 | /* | |
| 1927 | * EEPROM LED | |
| 1928 | * POLARITY_RDY_G: Polarity RDY_G setting. | |
| 1929 | * POLARITY_RDY_A: Polarity RDY_A setting. | |
| 1930 | * POLARITY_ACT: Polarity ACT setting. | |
| 1931 | * POLARITY_GPIO_0: Polarity GPIO0 setting. | |
| 1932 | * POLARITY_GPIO_1: Polarity GPIO1 setting. | |
| 1933 | * POLARITY_GPIO_2: Polarity GPIO2 setting. | |
| 1934 | * POLARITY_GPIO_3: Polarity GPIO3 setting. | |
| 1935 | * POLARITY_GPIO_4: Polarity GPIO4 setting. | |
| 1936 | * LED_MODE: Led mode. | |
| 1937 | */ | |
| 38c8a566 RJH |
1938 | #define EEPROM_LED_AG_CONF 0x001e |
| 1939 | #define EEPROM_LED_ACT_CONF 0x001f | |
| 1940 | #define EEPROM_LED_POLARITY 0x0020 | |
| b54f78a8 BZ |
1941 | #define EEPROM_LED_POLARITY_RDY_BG FIELD16(0x0001) |
| 1942 | #define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002) | |
| 1943 | #define EEPROM_LED_POLARITY_ACT FIELD16(0x0004) | |
| 1944 | #define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008) | |
| 1945 | #define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010) | |
| 1946 | #define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020) | |
| 1947 | #define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040) | |
| 1948 | #define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080) | |
| 1949 | #define EEPROM_LED_LED_MODE FIELD16(0x1f00) | |
| 1950 | ||
| 38c8a566 RJH |
1951 | /* |
| 1952 | * EEPROM NIC Configuration 2 | |
| 1953 | * RX_STREAM: 0: Reserved, 1: 1 Stream, 2: 2 Stream | |
| 1954 | * TX_STREAM: 0: Reserved, 1: 1 Stream, 2: 2 Stream | |
| 1955 | * CRYSTAL: 00: Reserved, 01: One crystal, 10: Two crystal, 11: Reserved | |
| 1956 | */ | |
| 1957 | #define EEPROM_NIC_CONF2 0x0021 | |
| 1958 | #define EEPROM_NIC_CONF2_RX_STREAM FIELD16(0x000f) | |
| 1959 | #define EEPROM_NIC_CONF2_TX_STREAM FIELD16(0x00f0) | |
| 1960 | #define EEPROM_NIC_CONF2_CRYSTAL FIELD16(0x0600) | |
| 1961 | ||
| b54f78a8 BZ |
1962 | /* |
| 1963 | * EEPROM LNA | |
| 1964 | */ | |
| 1965 | #define EEPROM_LNA 0x0022 | |
| 1966 | #define EEPROM_LNA_BG FIELD16(0x00ff) | |
| 1967 | #define EEPROM_LNA_A0 FIELD16(0xff00) | |
| 1968 | ||
| 1969 | /* | |
| 1970 | * EEPROM RSSI BG offset | |
| 1971 | */ | |
| 1972 | #define EEPROM_RSSI_BG 0x0023 | |
| 1973 | #define EEPROM_RSSI_BG_OFFSET0 FIELD16(0x00ff) | |
| 1974 | #define EEPROM_RSSI_BG_OFFSET1 FIELD16(0xff00) | |
| 1975 | ||
| 1976 | /* | |
| 1977 | * EEPROM RSSI BG2 offset | |
| 1978 | */ | |
| 1979 | #define EEPROM_RSSI_BG2 0x0024 | |
| 1980 | #define EEPROM_RSSI_BG2_OFFSET2 FIELD16(0x00ff) | |
| 1981 | #define EEPROM_RSSI_BG2_LNA_A1 FIELD16(0xff00) | |
| 1982 | ||
| e148b4c8 GW |
1983 | /* |
| 1984 | * EEPROM TXMIXER GAIN BG offset (note overlaps with EEPROM RSSI BG2). | |
| 1985 | */ | |
| 1986 | #define EEPROM_TXMIXER_GAIN_BG 0x0024 | |
| 1987 | #define EEPROM_TXMIXER_GAIN_BG_VAL FIELD16(0x0007) | |
| 1988 | ||
| b54f78a8 BZ |
1989 | /* |
| 1990 | * EEPROM RSSI A offset | |
| 1991 | */ | |
| 1992 | #define EEPROM_RSSI_A 0x0025 | |
| 1993 | #define EEPROM_RSSI_A_OFFSET0 FIELD16(0x00ff) | |
| 1994 | #define EEPROM_RSSI_A_OFFSET1 FIELD16(0xff00) | |
| 1995 | ||
| 1996 | /* | |
| 1997 | * EEPROM RSSI A2 offset | |
| 1998 | */ | |
| 1999 | #define EEPROM_RSSI_A2 0x0026 | |
| 2000 | #define EEPROM_RSSI_A2_OFFSET2 FIELD16(0x00ff) | |
| 2001 | #define EEPROM_RSSI_A2_LNA_A2 FIELD16(0xff00) | |
| 2002 | ||
| 8d1331b3 ID |
2003 | /* |
| 2004 | * EEPROM Maximum TX power values | |
| 2005 | */ | |
| 2006 | #define EEPROM_MAX_TX_POWER 0x0027 | |
| 2007 | #define EEPROM_MAX_TX_POWER_24GHZ FIELD16(0x00ff) | |
| 2008 | #define EEPROM_MAX_TX_POWER_5GHZ FIELD16(0xff00) | |
| 2009 | ||
| b54f78a8 BZ |
2010 | /* |
| 2011 | * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power. | |
| 38c8a566 | 2012 | * This is delta in 40MHZ. |
| b54f78a8 BZ |
2013 | * VALUE: Tx Power dalta value (MAX=4) |
| 2014 | * TYPE: 1: Plus the delta value, 0: minus the delta value | |
| 2015 | * TXPOWER: Enable: | |
| 2016 | */ | |
| 2017 | #define EEPROM_TXPOWER_DELTA 0x0028 | |
| 2018 | #define EEPROM_TXPOWER_DELTA_VALUE FIELD16(0x003f) | |
| 2019 | #define EEPROM_TXPOWER_DELTA_TYPE FIELD16(0x0040) | |
| 2020 | #define EEPROM_TXPOWER_DELTA_TXPOWER FIELD16(0x0080) | |
| 2021 | ||
| 2022 | /* | |
| 2023 | * EEPROM TXPOWER 802.11BG | |
| 2024 | */ | |
| 2025 | #define EEPROM_TXPOWER_BG1 0x0029 | |
| 2026 | #define EEPROM_TXPOWER_BG2 0x0030 | |
| 2027 | #define EEPROM_TXPOWER_BG_SIZE 7 | |
| 2028 | #define EEPROM_TXPOWER_BG_1 FIELD16(0x00ff) | |
| 2029 | #define EEPROM_TXPOWER_BG_2 FIELD16(0xff00) | |
| 2030 | ||
| 2031 | /* | |
| 2032 | * EEPROM TXPOWER 802.11A | |
| 2033 | */ | |
| 2034 | #define EEPROM_TXPOWER_A1 0x003c | |
| 2035 | #define EEPROM_TXPOWER_A2 0x0053 | |
| 2036 | #define EEPROM_TXPOWER_A_SIZE 6 | |
| 2037 | #define EEPROM_TXPOWER_A_1 FIELD16(0x00ff) | |
| 2038 | #define EEPROM_TXPOWER_A_2 FIELD16(0xff00) | |
| 2039 | ||
| 2040 | /* | |
| 5e846004 | 2041 | * EEPROM TXPOWER by rate: tx power per tx rate for HT20 mode |
| b54f78a8 BZ |
2042 | */ |
| 2043 | #define EEPROM_TXPOWER_BYRATE 0x006f | |
| 5e846004 HS |
2044 | #define EEPROM_TXPOWER_BYRATE_SIZE 9 |
| 2045 | ||
| 2046 | #define EEPROM_TXPOWER_BYRATE_RATE0 FIELD16(0x000f) | |
| 2047 | #define EEPROM_TXPOWER_BYRATE_RATE1 FIELD16(0x00f0) | |
| 2048 | #define EEPROM_TXPOWER_BYRATE_RATE2 FIELD16(0x0f00) | |
| 2049 | #define EEPROM_TXPOWER_BYRATE_RATE3 FIELD16(0xf000) | |
| b54f78a8 BZ |
2050 | |
| 2051 | /* | |
| 2052 | * EEPROM BBP. | |
| 2053 | */ | |
| 2054 | #define EEPROM_BBP_START 0x0078 | |
| 2055 | #define EEPROM_BBP_SIZE 16 | |
| 2056 | #define EEPROM_BBP_VALUE FIELD16(0x00ff) | |
| 2057 | #define EEPROM_BBP_REG_ID FIELD16(0xff00) | |
| 2058 | ||
| 2059 | /* | |
| 2060 | * MCU mailbox commands. | |
| 2061 | */ | |
| 2062 | #define MCU_SLEEP 0x30 | |
| 2063 | #define MCU_WAKEUP 0x31 | |
| 2064 | #define MCU_RADIO_OFF 0x35 | |
| 2065 | #define MCU_CURRENT 0x36 | |
| 2066 | #define MCU_LED 0x50 | |
| 2067 | #define MCU_LED_STRENGTH 0x51 | |
| 38c8a566 RJH |
2068 | #define MCU_LED_AG_CONF 0x52 |
| 2069 | #define MCU_LED_ACT_CONF 0x53 | |
| 2070 | #define MCU_LED_LED_POLARITY 0x54 | |
| b54f78a8 BZ |
2071 | #define MCU_RADAR 0x60 |
| 2072 | #define MCU_BOOT_SIGNAL 0x72 | |
| d96aa640 | 2073 | #define MCU_ANT_SELECT 0X73 |
| b54f78a8 BZ |
2074 | #define MCU_BBP_SIGNAL 0x80 |
| 2075 | #define MCU_POWER_SAVE 0x83 | |
| 2076 | ||
| 2077 | /* | |
| 2078 | * MCU mailbox tokens | |
| 2079 | */ | |
| 2080 | #define TOKEN_WAKUP 3 | |
| 2081 | ||
| 2082 | /* | |
| 2083 | * DMA descriptor defines. | |
| 2084 | */ | |
| fd8dab9a ME |
2085 | #define TXWI_DESC_SIZE (4 * sizeof(__le32)) |
| 2086 | #define RXWI_DESC_SIZE (4 * sizeof(__le32)) | |
| b54f78a8 BZ |
2087 | |
| 2088 | /* | |
| 2089 | * TX WI structure | |
| 2090 | */ | |
| 2091 | ||
| 2092 | /* | |
| 2093 | * Word0 | |
| 2094 | * FRAG: 1 To inform TKIP engine this is a fragment. | |
| 2095 | * MIMO_PS: The remote peer is in dynamic MIMO-PS mode | |
| 2096 | * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs | |
| cb753b72 HS |
2097 | * BW: Channel bandwidth 0:20MHz, 1:40 MHz (for legacy rates this will |
| 2098 | * duplicate the frame to both channels). | |
| b54f78a8 | 2099 | * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED |
| 2035c0cf | 2100 | * AMPDU: 1: this frame is eligible for AMPDU aggregation, the hw will |
| 74ee3802 HS |
2101 | * aggregate consecutive frames with the same RA and QoS TID. If |
| 2102 | * a frame A with the same RA and QoS TID but AMPDU=0 is queued | |
| 2103 | * directly after a frame B with AMPDU=1, frame A might still | |
| 2104 | * get aggregated into the AMPDU started by frame B. So, setting | |
| 2105 | * AMPDU to 0 does _not_ necessarily mean the frame is sent as | |
| 2106 | * MPDU, it can still end up in an AMPDU if the previous frame | |
| 2107 | * was tagged as AMPDU. | |
| b54f78a8 BZ |
2108 | */ |
| 2109 | #define TXWI_W0_FRAG FIELD32(0x00000001) | |
| 2110 | #define TXWI_W0_MIMO_PS FIELD32(0x00000002) | |
| 2111 | #define TXWI_W0_CF_ACK FIELD32(0x00000004) | |
| 2112 | #define TXWI_W0_TS FIELD32(0x00000008) | |
| 2113 | #define TXWI_W0_AMPDU FIELD32(0x00000010) | |
| 2114 | #define TXWI_W0_MPDU_DENSITY FIELD32(0x000000e0) | |
| 2115 | #define TXWI_W0_TX_OP FIELD32(0x00000300) | |
| 2116 | #define TXWI_W0_MCS FIELD32(0x007f0000) | |
| 2117 | #define TXWI_W0_BW FIELD32(0x00800000) | |
| 2118 | #define TXWI_W0_SHORT_GI FIELD32(0x01000000) | |
| 2119 | #define TXWI_W0_STBC FIELD32(0x06000000) | |
| 2120 | #define TXWI_W0_IFS FIELD32(0x08000000) | |
| 2121 | #define TXWI_W0_PHYMODE FIELD32(0xc0000000) | |
| 2122 | ||
| 2123 | /* | |
| 2124 | * Word1 | |
| 0856d9c0 HS |
2125 | * ACK: 0: No Ack needed, 1: Ack needed |
| 2126 | * NSEQ: 0: Don't assign hw sequence number, 1: Assign hw sequence number | |
| 2127 | * BW_WIN_SIZE: BA windows size of the recipient | |
| 2128 | * WIRELESS_CLI_ID: Client ID for WCID table access | |
| 2129 | * MPDU_TOTAL_BYTE_COUNT: Length of 802.11 frame | |
| 2130 | * PACKETID: Will be latched into the TX_STA_FIFO register once the according | |
| 2035c0cf HS |
2131 | * frame was processed. If multiple frames are aggregated together |
| 2132 | * (AMPDU==1) the reported tx status will always contain the packet | |
| 2133 | * id of the first frame. 0: Don't report tx status for this frame. | |
| bc8a979e ID |
2134 | * PACKETID_QUEUE: Part of PACKETID, This is the queue index (0-3) |
| 2135 | * PACKETID_ENTRY: Part of PACKETID, THis is the queue entry index (1-3) | |
| 2136 | * This identification number is calculated by ((idx % 3) + 1). | |
| 2137 | * The (+1) is required to prevent PACKETID to become 0. | |
| b54f78a8 BZ |
2138 | */ |
| 2139 | #define TXWI_W1_ACK FIELD32(0x00000001) | |
| 2140 | #define TXWI_W1_NSEQ FIELD32(0x00000002) | |
| 2141 | #define TXWI_W1_BW_WIN_SIZE FIELD32(0x000000fc) | |
| 2142 | #define TXWI_W1_WIRELESS_CLI_ID FIELD32(0x0000ff00) | |
| 2143 | #define TXWI_W1_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000) | |
| 2144 | #define TXWI_W1_PACKETID FIELD32(0xf0000000) | |
| bc8a979e ID |
2145 | #define TXWI_W1_PACKETID_QUEUE FIELD32(0x30000000) |
| 2146 | #define TXWI_W1_PACKETID_ENTRY FIELD32(0xc0000000) | |
| b54f78a8 BZ |
2147 | |
| 2148 | /* | |
| 2149 | * Word2 | |
| 2150 | */ | |
| 2151 | #define TXWI_W2_IV FIELD32(0xffffffff) | |
| 2152 | ||
| 2153 | /* | |
| 2154 | * Word3 | |
| 2155 | */ | |
| 2156 | #define TXWI_W3_EIV FIELD32(0xffffffff) | |
| 2157 | ||
| 2158 | /* | |
| 2159 | * RX WI structure | |
| 2160 | */ | |
| 2161 | ||
| 2162 | /* | |
| 2163 | * Word0 | |
| 2164 | */ | |
| 2165 | #define RXWI_W0_WIRELESS_CLI_ID FIELD32(0x000000ff) | |
| 2166 | #define RXWI_W0_KEY_INDEX FIELD32(0x00000300) | |
| 2167 | #define RXWI_W0_BSSID FIELD32(0x00001c00) | |
| 2168 | #define RXWI_W0_UDF FIELD32(0x0000e000) | |
| 2169 | #define RXWI_W0_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000) | |
| 2170 | #define RXWI_W0_TID FIELD32(0xf0000000) | |
| 2171 | ||
| 2172 | /* | |
| 2173 | * Word1 | |
| 2174 | */ | |
| 2175 | #define RXWI_W1_FRAG FIELD32(0x0000000f) | |
| 2176 | #define RXWI_W1_SEQUENCE FIELD32(0x0000fff0) | |
| 2177 | #define RXWI_W1_MCS FIELD32(0x007f0000) | |
| 2178 | #define RXWI_W1_BW FIELD32(0x00800000) | |
| 2179 | #define RXWI_W1_SHORT_GI FIELD32(0x01000000) | |
| 2180 | #define RXWI_W1_STBC FIELD32(0x06000000) | |
| 2181 | #define RXWI_W1_PHYMODE FIELD32(0xc0000000) | |
| 2182 | ||
| 2183 | /* | |
| 2184 | * Word2 | |
| 2185 | */ | |
| 2186 | #define RXWI_W2_RSSI0 FIELD32(0x000000ff) | |
| 2187 | #define RXWI_W2_RSSI1 FIELD32(0x0000ff00) | |
| 2188 | #define RXWI_W2_RSSI2 FIELD32(0x00ff0000) | |
| 2189 | ||
| 2190 | /* | |
| 2191 | * Word3 | |
| 2192 | */ | |
| 2193 | #define RXWI_W3_SNR0 FIELD32(0x000000ff) | |
| 2194 | #define RXWI_W3_SNR1 FIELD32(0x0000ff00) | |
| 2195 | ||
| 2196 | /* | |
| 2197 | * Macros for converting txpower from EEPROM to mac80211 value | |
| 2198 | * and from mac80211 value to register value. | |
| 2199 | */ | |
| 2200 | #define MIN_G_TXPOWER 0 | |
| 2201 | #define MIN_A_TXPOWER -7 | |
| 2202 | #define MAX_G_TXPOWER 31 | |
| 2203 | #define MAX_A_TXPOWER 15 | |
| 2204 | #define DEFAULT_TXPOWER 5 | |
| 2205 | ||
| 2206 | #define TXPOWER_G_FROM_DEV(__txpower) \ | |
| 2207 | ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower) | |
| 2208 | ||
| 2209 | #define TXPOWER_G_TO_DEV(__txpower) \ | |
| 2210 | clamp_t(char, __txpower, MIN_G_TXPOWER, MAX_G_TXPOWER) | |
| 2211 | ||
| 2212 | #define TXPOWER_A_FROM_DEV(__txpower) \ | |
| 2213 | ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower) | |
| 2214 | ||
| 2215 | #define TXPOWER_A_TO_DEV(__txpower) \ | |
| 2216 | clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER) | |
| 2217 | ||
| 2218 | #endif /* RT2800_H */ |