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mac80211: remove support for IFF_PROMISC
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2800lib.c
CommitLineData
89297425 1/*
96481b20 2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
a5ea2f02 3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
9c9a0d14 4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
cce5fc45 5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
89297425 6
9c9a0d14 7 Based on the original rt2800pci.c and rt2800usb.c.
9c9a0d14
GW		 8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
89297425
BZ		 14 <http://rt2x00.serialmonkey.com>
15
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
20
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
25
26 You should have received a copy of the GNU General Public License
a05b8c58 27 along with this program; if not, see <http://www.gnu.org/licenses/>.
89297425
BZ		 28 */
29
30/*
31 Module: rt2800lib
32 Abstract: rt2800 generic device routines.
33 */
34
f31c9a8c 35#include <linux/crc-ccitt.h>
89297425
BZ		 36#include <linux/kernel.h>
37#include <linux/module.h>
5a0e3ad6 38#include <linux/slab.h>
89297425
BZ		 39
40#include "rt2x00.h"
41#include "rt2800lib.h"
42#include "rt2800.h"
43
89297425
BZ		 44/*
45 * Register access.
46 * All access to the CSR registers will go through the methods
47 * rt2800_register_read and rt2800_register_write.
48 * BBP and RF register require indirect register access,
49 * and use the CSR registers BBPCSR and RFCSR to achieve this.
50 * These indirect registers work with busy bits,
51 * and we will try maximal REGISTER_BUSY_COUNT times to access
52 * the register while taking a REGISTER_BUSY_DELAY us delay
53 * between each attampt. When the busy bit is still set at that time,
54 * the access attempt is considered to have failed,
55 * and we will print an error.
56 * The _lock versions must be used if you already hold the csr_mutex
57 */
58#define WAIT_FOR_BBP(__dev, __reg) \
59 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
60#define WAIT_FOR_RFCSR(__dev, __reg) \
61 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
62#define WAIT_FOR_RF(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
64#define WAIT_FOR_MCU(__dev, __reg) \
65 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
66 H2M_MAILBOX_CSR_OWNER, (__reg))
67
baff8006
HS		 68static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
69{
70 /* check for rt2872 on SoC */
71 if (!rt2x00_is_soc(rt2x00dev) ||
72 !rt2x00_rt(rt2x00dev, RT2872))
73 return false;
74
75 /* we know for sure that these rf chipsets are used on rt305x boards */
76 if (rt2x00_rf(rt2x00dev, RF3020) ||
77 rt2x00_rf(rt2x00dev, RF3021) ||
78 rt2x00_rf(rt2x00dev, RF3022))
79 return true;
80
ec9c4989 81 rt2x00_warn(rt2x00dev, "Unknown RF chipset on rt305x\n");
baff8006
HS		 82 return false;
83}
84
fcf51541
BZ		 85static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
86 const unsigned int word, const u8 value)
89297425
BZ		 87{
88 u32 reg;
89
90 mutex_lock(&rt2x00dev->csr_mutex);
91
92 /*
93 * Wait until the BBP becomes available, afterwards we
94 * can safely write the new data into the register.
95 */
96 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
97 reg = 0;
98 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
99 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
100 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
101 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
efc7d36f 102 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 103
104 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
105 }
106
107 mutex_unlock(&rt2x00dev->csr_mutex);
108}
89297425 109
fcf51541
BZ		 110static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
111 const unsigned int word, u8 *value)
89297425
BZ		 112{
113 u32 reg;
114
115 mutex_lock(&rt2x00dev->csr_mutex);
116
117 /*
118 * Wait until the BBP becomes available, afterwards we
119 * can safely write the read request into the register.
120 * After the data has been written, we wait until hardware
121 * returns the correct value, if at any time the register
122 * doesn't become available in time, reg will be 0xffffffff
123 * which means we return 0xff to the caller.
124 */
125 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
126 reg = 0;
127 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
128 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
129 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
efc7d36f 130 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 131
132 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
133
134 WAIT_FOR_BBP(rt2x00dev, &reg);
135 }
136
137 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
138
139 mutex_unlock(&rt2x00dev->csr_mutex);
140}
89297425 141
fcf51541
BZ		 142static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
143 const unsigned int word, const u8 value)
89297425
BZ		 144{
145 u32 reg;
146
147 mutex_lock(&rt2x00dev->csr_mutex);
148
149 /*
150 * Wait until the RFCSR becomes available, afterwards we
151 * can safely write the new data into the register.
152 */
153 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
154 reg = 0;
155 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
156 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
157 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
158 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
159
160 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
161 }
162
163 mutex_unlock(&rt2x00dev->csr_mutex);
164}
89297425 165
fcf51541
BZ		 166static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
167 const unsigned int word, u8 *value)
89297425
BZ		 168{
169 u32 reg;
170
171 mutex_lock(&rt2x00dev->csr_mutex);
172
173 /*
174 * Wait until the RFCSR becomes available, afterwards we
175 * can safely write the read request into the register.
176 * After the data has been written, we wait until hardware
177 * returns the correct value, if at any time the register
178 * doesn't become available in time, reg will be 0xffffffff
179 * which means we return 0xff to the caller.
180 */
181 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
182 reg = 0;
183 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
184 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
185 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
186
187 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
188
189 WAIT_FOR_RFCSR(rt2x00dev, &reg);
190 }
191
192 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
193
194 mutex_unlock(&rt2x00dev->csr_mutex);
195}
89297425 196
fcf51541
BZ		 197static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
198 const unsigned int word, const u32 value)
89297425
BZ		 199{
200 u32 reg;
201
202 mutex_lock(&rt2x00dev->csr_mutex);
203
204 /*
205 * Wait until the RF becomes available, afterwards we
206 * can safely write the new data into the register.
207 */
208 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
209 reg = 0;
210 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
211 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
212 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
213 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
214
215 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
216 rt2x00_rf_write(rt2x00dev, word, value);
217 }
218
219 mutex_unlock(&rt2x00dev->csr_mutex);
220}
89297425 221
379448fe
GJ		 222static const unsigned int rt2800_eeprom_map[EEPROM_WORD_COUNT] = {
223 [EEPROM_CHIP_ID] = 0x0000,
224 [EEPROM_VERSION] = 0x0001,
225 [EEPROM_MAC_ADDR_0] = 0x0002,
226 [EEPROM_MAC_ADDR_1] = 0x0003,
227 [EEPROM_MAC_ADDR_2] = 0x0004,
228 [EEPROM_NIC_CONF0] = 0x001a,
229 [EEPROM_NIC_CONF1] = 0x001b,
230 [EEPROM_FREQ] = 0x001d,
231 [EEPROM_LED_AG_CONF] = 0x001e,
232 [EEPROM_LED_ACT_CONF] = 0x001f,
233 [EEPROM_LED_POLARITY] = 0x0020,
234 [EEPROM_NIC_CONF2] = 0x0021,
235 [EEPROM_LNA] = 0x0022,
236 [EEPROM_RSSI_BG] = 0x0023,
237 [EEPROM_RSSI_BG2] = 0x0024,
238 [EEPROM_TXMIXER_GAIN_BG] = 0x0024, /* overlaps with RSSI_BG2 */
239 [EEPROM_RSSI_A] = 0x0025,
240 [EEPROM_RSSI_A2] = 0x0026,
241 [EEPROM_TXMIXER_GAIN_A] = 0x0026, /* overlaps with RSSI_A2 */
242 [EEPROM_EIRP_MAX_TX_POWER] = 0x0027,
243 [EEPROM_TXPOWER_DELTA] = 0x0028,
244 [EEPROM_TXPOWER_BG1] = 0x0029,
245 [EEPROM_TXPOWER_BG2] = 0x0030,
246 [EEPROM_TSSI_BOUND_BG1] = 0x0037,
247 [EEPROM_TSSI_BOUND_BG2] = 0x0038,
248 [EEPROM_TSSI_BOUND_BG3] = 0x0039,
249 [EEPROM_TSSI_BOUND_BG4] = 0x003a,
250 [EEPROM_TSSI_BOUND_BG5] = 0x003b,
251 [EEPROM_TXPOWER_A1] = 0x003c,
252 [EEPROM_TXPOWER_A2] = 0x0053,
253 [EEPROM_TSSI_BOUND_A1] = 0x006a,
254 [EEPROM_TSSI_BOUND_A2] = 0x006b,
255 [EEPROM_TSSI_BOUND_A3] = 0x006c,
256 [EEPROM_TSSI_BOUND_A4] = 0x006d,
257 [EEPROM_TSSI_BOUND_A5] = 0x006e,
258 [EEPROM_TXPOWER_BYRATE] = 0x006f,
259 [EEPROM_BBP_START] = 0x0078,
260};
261
fa31d157
GJ		 262static const unsigned int rt2800_eeprom_map_ext[EEPROM_WORD_COUNT] = {
263 [EEPROM_CHIP_ID] = 0x0000,
264 [EEPROM_VERSION] = 0x0001,
265 [EEPROM_MAC_ADDR_0] = 0x0002,
266 [EEPROM_MAC_ADDR_1] = 0x0003,
267 [EEPROM_MAC_ADDR_2] = 0x0004,
268 [EEPROM_NIC_CONF0] = 0x001a,
269 [EEPROM_NIC_CONF1] = 0x001b,
270 [EEPROM_NIC_CONF2] = 0x001c,
271 [EEPROM_EIRP_MAX_TX_POWER] = 0x0020,
272 [EEPROM_FREQ] = 0x0022,
273 [EEPROM_LED_AG_CONF] = 0x0023,
274 [EEPROM_LED_ACT_CONF] = 0x0024,
275 [EEPROM_LED_POLARITY] = 0x0025,
276 [EEPROM_LNA] = 0x0026,
277 [EEPROM_EXT_LNA2] = 0x0027,
278 [EEPROM_RSSI_BG] = 0x0028,
fa31d157 279 [EEPROM_RSSI_BG2] = 0x0029,
fa31d157
GJ		 280 [EEPROM_RSSI_A] = 0x002a,
281 [EEPROM_RSSI_A2] = 0x002b,
fa31d157
GJ		 282 [EEPROM_TXPOWER_BG1] = 0x0030,
283 [EEPROM_TXPOWER_BG2] = 0x0037,
284 [EEPROM_EXT_TXPOWER_BG3] = 0x003e,
285 [EEPROM_TSSI_BOUND_BG1] = 0x0045,
286 [EEPROM_TSSI_BOUND_BG2] = 0x0046,
287 [EEPROM_TSSI_BOUND_BG3] = 0x0047,
288 [EEPROM_TSSI_BOUND_BG4] = 0x0048,
289 [EEPROM_TSSI_BOUND_BG5] = 0x0049,
290 [EEPROM_TXPOWER_A1] = 0x004b,
291 [EEPROM_TXPOWER_A2] = 0x0065,
292 [EEPROM_EXT_TXPOWER_A3] = 0x007f,
293 [EEPROM_TSSI_BOUND_A1] = 0x009a,
294 [EEPROM_TSSI_BOUND_A2] = 0x009b,
295 [EEPROM_TSSI_BOUND_A3] = 0x009c,
296 [EEPROM_TSSI_BOUND_A4] = 0x009d,
297 [EEPROM_TSSI_BOUND_A5] = 0x009e,
298 [EEPROM_TXPOWER_BYRATE] = 0x00a0,
299};
300
379448fe
GJ		 301static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev *rt2x00dev,
302 const enum rt2800_eeprom_word word)
303{
304 const unsigned int *map;
305 unsigned int index;
306
307 if (WARN_ONCE(word >= EEPROM_WORD_COUNT,
308 "%s: invalid EEPROM word %d\n",
309 wiphy_name(rt2x00dev->hw->wiphy), word))
310 return 0;
311
fa31d157
GJ		 312 if (rt2x00_rt(rt2x00dev, RT3593))
313 map = rt2800_eeprom_map_ext;
314 else
315 map = rt2800_eeprom_map;
316
379448fe
GJ		 317 index = map[word];
318
319 /* Index 0 is valid only for EEPROM_CHIP_ID.
320 * Otherwise it means that the offset of the
321 * given word is not initialized in the map,
322 * or that the field is not usable on the
323 * actual chipset.
324 */
325 WARN_ONCE(word != EEPROM_CHIP_ID && index == 0,
326 "%s: invalid access of EEPROM word %d\n",
327 wiphy_name(rt2x00dev->hw->wiphy), word);
328
329 return index;
330}
331
3e38d3da
GJ		 332static void *rt2800_eeprom_addr(struct rt2x00_dev *rt2x00dev,
333 const enum rt2800_eeprom_word word)
334{
379448fe
GJ		 335 unsigned int index;
336
337 index = rt2800_eeprom_word_index(rt2x00dev, word);
338 return rt2x00_eeprom_addr(rt2x00dev, index);
3e38d3da
GJ		 339}
340
341static void rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev,
342 const enum rt2800_eeprom_word word, u16 *data)
343{
379448fe
GJ		 344 unsigned int index;
345
346 index = rt2800_eeprom_word_index(rt2x00dev, word);
347 rt2x00_eeprom_read(rt2x00dev, index, data);
3e38d3da
GJ		 348}
349
350static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev,
351 const enum rt2800_eeprom_word word, u16 data)
352{
379448fe
GJ		 353 unsigned int index;
354
355 index = rt2800_eeprom_word_index(rt2x00dev, word);
356 rt2x00_eeprom_write(rt2x00dev, index, data);
3e38d3da
GJ		 357}
358
022138ca
GJ		 359static void rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev,
360 const enum rt2800_eeprom_word array,
361 unsigned int offset,
362 u16 *data)
363{
379448fe
GJ		 364 unsigned int index;
365
366 index = rt2800_eeprom_word_index(rt2x00dev, array);
367 rt2x00_eeprom_read(rt2x00dev, index + offset, data);
022138ca
GJ		 368}
369
16ebd608
WH		 370static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)
371{
372 u32 reg;
373 int i, count;
374
375 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
376 if (rt2x00_get_field32(reg, WLAN_EN))
377 return 0;
378
379 rt2x00_set_field32(&reg, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff);
380 rt2x00_set_field32(&reg, FRC_WL_ANT_SET, 1);
381 rt2x00_set_field32(&reg, WLAN_CLK_EN, 0);
382 rt2x00_set_field32(&reg, WLAN_EN, 1);
383 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
384
385 udelay(REGISTER_BUSY_DELAY);
386
387 count = 0;
388 do {
389 /*
390 * Check PLL_LD & XTAL_RDY.
391 */
392 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
393 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
394 if (rt2x00_get_field32(reg, PLL_LD) &&
395 rt2x00_get_field32(reg, XTAL_RDY))
396 break;
397 udelay(REGISTER_BUSY_DELAY);
398 }
399
400 if (i >= REGISTER_BUSY_COUNT) {
401
402 if (count >= 10)
403 return -EIO;
404
405 rt2800_register_write(rt2x00dev, 0x58, 0x018);
406 udelay(REGISTER_BUSY_DELAY);
407 rt2800_register_write(rt2x00dev, 0x58, 0x418);
408 udelay(REGISTER_BUSY_DELAY);
409 rt2800_register_write(rt2x00dev, 0x58, 0x618);
410 udelay(REGISTER_BUSY_DELAY);
411 count++;
412 } else {
413 count = 0;
414 }
415
416 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
417 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 0);
418 rt2x00_set_field32(&reg, WLAN_CLK_EN, 1);
419 rt2x00_set_field32(&reg, WLAN_RESET, 1);
420 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
421 udelay(10);
422 rt2x00_set_field32(&reg, WLAN_RESET, 0);
423 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
424 udelay(10);
425 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff);
426 } while (count != 0);
427
428 return 0;
429}
430
89297425
BZ		 431void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
432 const u8 command, const u8 token,
433 const u8 arg0, const u8 arg1)
434{
435 u32 reg;
436
ee303e54 437 /*
cea90e55 438 * SOC devices don't support MCU requests.
ee303e54 439 */
cea90e55 440 if (rt2x00_is_soc(rt2x00dev))
ee303e54 441 return;
89297425
BZ		 442
443 mutex_lock(&rt2x00dev->csr_mutex);
444
445 /*
446 * Wait until the MCU becomes available, afterwards we
447 * can safely write the new data into the register.
448 */
449 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
450 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
451 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
452 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
453 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
454 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
455
456 reg = 0;
457 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
458 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
459 }
460
461 mutex_unlock(&rt2x00dev->csr_mutex);
462}
463EXPORT_SYMBOL_GPL(rt2800_mcu_request);
f4450616 464
5ffddc49
ID		 465int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
466{
467 unsigned int i = 0;
468 u32 reg;
469
470 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
471 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
472 if (reg && reg != ~0)
473 return 0;
474 msleep(1);
475 }
476
ec9c4989 477 rt2x00_err(rt2x00dev, "Unstable hardware\n");
5ffddc49
ID		 478 return -EBUSY;
479}
480EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
481
67a4c1e2
GW		 482int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
483{
484 unsigned int i;
485 u32 reg;
486
08e53100
HS		 487 /*
488 * Some devices are really slow to respond here. Wait a whole second
489 * before timing out.
490 */
67a4c1e2
GW		 491 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
492 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
493 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
494 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
495 return 0;
496
08e53100 497 msleep(10);
67a4c1e2
GW		 498 }
499
ec9c4989 500 rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg);
67a4c1e2
GW		 501 return -EACCES;
502}
503EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
504
f7b395e9
JK		 505void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
506{
507 u32 reg;
508
509 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
510 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
511 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
512 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
513 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
514 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
515 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
516}
517EXPORT_SYMBOL_GPL(rt2800_disable_wpdma);
518
ae1b1c5d
GJ		 519void rt2800_get_txwi_rxwi_size(struct rt2x00_dev *rt2x00dev,
520 unsigned short *txwi_size,
521 unsigned short *rxwi_size)
522{
523 switch (rt2x00dev->chip.rt) {
524 case RT3593:
525 *txwi_size = TXWI_DESC_SIZE_4WORDS;
526 *rxwi_size = RXWI_DESC_SIZE_5WORDS;
527 break;
528
529 case RT5592:
530 *txwi_size = TXWI_DESC_SIZE_5WORDS;
531 *rxwi_size = RXWI_DESC_SIZE_6WORDS;
532 break;
533
534 default:
535 *txwi_size = TXWI_DESC_SIZE_4WORDS;
536 *rxwi_size = RXWI_DESC_SIZE_4WORDS;
537 break;
538 }
539}
540EXPORT_SYMBOL_GPL(rt2800_get_txwi_rxwi_size);
541
f31c9a8c
ID		 542static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
543{
544 u16 fw_crc;
545 u16 crc;
546
547 /*
548 * The last 2 bytes in the firmware array are the crc checksum itself,
549 * this means that we should never pass those 2 bytes to the crc
550 * algorithm.
551 */
552 fw_crc = (data[len - 2] << 8 | data[len - 1]);
553
554 /*
555 * Use the crc ccitt algorithm.
556 * This will return the same value as the legacy driver which
557 * used bit ordering reversion on the both the firmware bytes
558 * before input input as well as on the final output.
559 * Obviously using crc ccitt directly is much more efficient.
560 */
561 crc = crc_ccitt(~0, data, len - 2);
562
563 /*
564 * There is a small difference between the crc-itu-t + bitrev and
565 * the crc-ccitt crc calculation. In the latter method the 2 bytes
566 * will be swapped, use swab16 to convert the crc to the correct
567 * value.
568 */
569 crc = swab16(crc);
570
571 return fw_crc == crc;
572}
573
574int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
575 const u8 *data, const size_t len)
576{
577 size_t offset = 0;
578 size_t fw_len;
579 bool multiple;
580
581 /*
582 * PCI(e) & SOC devices require firmware with a length
583 * of 8kb. USB devices require firmware files with a length
584 * of 4kb. Certain USB chipsets however require different firmware,
585 * which Ralink only provides attached to the original firmware
586 * file. Thus for USB devices, firmware files have a length
a89534ed
WH		 587 * which is a multiple of 4kb. The firmware for rt3290 chip also
588 * have a length which is a multiple of 4kb.
f31c9a8c 589 */
a89534ed 590 if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290))
f31c9a8c 591 fw_len = 4096;
a89534ed 592 else
f31c9a8c 593 fw_len = 8192;
f31c9a8c 594
a89534ed 595 multiple = true;
f31c9a8c
ID		 596 /*
597 * Validate the firmware length
598 */
599 if (len != fw_len && (!multiple || (len % fw_len) != 0))
600 return FW_BAD_LENGTH;
601
602 /*
603 * Check if the chipset requires one of the upper parts
604 * of the firmware.
605 */
606 if (rt2x00_is_usb(rt2x00dev) &&
607 !rt2x00_rt(rt2x00dev, RT2860) &&
608 !rt2x00_rt(rt2x00dev, RT2872) &&
609 !rt2x00_rt(rt2x00dev, RT3070) &&
610 ((len / fw_len) == 1))
611 return FW_BAD_VERSION;
612
613 /*
614 * 8kb firmware files must be checked as if it were
615 * 2 separate firmware files.
616 */
617 while (offset < len) {
618 if (!rt2800_check_firmware_crc(data + offset, fw_len))
619 return FW_BAD_CRC;
620
621 offset += fw_len;
622 }
623
624 return FW_OK;
625}
626EXPORT_SYMBOL_GPL(rt2800_check_firmware);
627
628int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
629 const u8 *data, const size_t len)
630{
631 unsigned int i;
632 u32 reg;
16ebd608
WH		 633 int retval;
634
635 if (rt2x00_rt(rt2x00dev, RT3290)) {
636 retval = rt2800_enable_wlan_rt3290(rt2x00dev);
637 if (retval)
638 return -EBUSY;
639 }
f31c9a8c
ID		 640
641 /*
b9eca242
ID		 642 * If driver doesn't wake up firmware here,
643 * rt2800_load_firmware will hang forever when interface is up again.
f31c9a8c 644 */
b9eca242 645 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
f31c9a8c 646
f31c9a8c
ID		 647 /*
648 * Wait for stable hardware.
649 */
5ffddc49 650 if (rt2800_wait_csr_ready(rt2x00dev))
f31c9a8c 651 return -EBUSY;
f31c9a8c 652
adde5882 653 if (rt2x00_is_pci(rt2x00dev)) {
a89534ed
WH		 654 if (rt2x00_rt(rt2x00dev, RT3290) ||
655 rt2x00_rt(rt2x00dev, RT3572) ||
2ed71884
JL		 656 rt2x00_rt(rt2x00dev, RT5390) ||
657 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 658 rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
659 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
660 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
661 rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
662 }
f31c9a8c 663 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
adde5882 664 }
f31c9a8c 665
b7e1d225
JK		 666 rt2800_disable_wpdma(rt2x00dev);
667
f31c9a8c
ID		 668 /*
669 * Write firmware to the device.
670 */
671 rt2800_drv_write_firmware(rt2x00dev, data, len);
672
673 /*
674 * Wait for device to stabilize.
675 */
676 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
677 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
678 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
679 break;
680 msleep(1);
681 }
682
683 if (i == REGISTER_BUSY_COUNT) {
ec9c4989 684 rt2x00_err(rt2x00dev, "PBF system register not ready\n");
f31c9a8c
ID		 685 return -EBUSY;
686 }
687
4ed1dd2a
SG		 688 /*
689 * Disable DMA, will be reenabled later when enabling
690 * the radio.
691 */
f7b395e9 692 rt2800_disable_wpdma(rt2x00dev);
4ed1dd2a 693
f31c9a8c
ID		 694 /*
695 * Initialize firmware.
696 */
697 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
698 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
8756130b 699 if (rt2x00_is_usb(rt2x00dev)) {
0c17cf96 700 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
8756130b
SG		 701 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
702 }
f31c9a8c
ID		 703 msleep(1);
704
705 return 0;
706}
707EXPORT_SYMBOL_GPL(rt2800_load_firmware);
708
0c5879bc
ID		 709void rt2800_write_tx_data(struct queue_entry *entry,
710 struct txentry_desc *txdesc)
59679b91 711{
0c5879bc 712 __le32 *txwi = rt2800_drv_get_txwi(entry);
59679b91 713 u32 word;
557985ae 714 int i;
59679b91
GW		 715
716 /*
717 * Initialize TX Info descriptor
718 */
719 rt2x00_desc_read(txwi, 0, &word);
720 rt2x00_set_field32(&word, TXWI_W0_FRAG,
721 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
84804cdc
ID		 722 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
723 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
59679b91
GW		 724 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
725 rt2x00_set_field32(&word, TXWI_W0_TS,
726 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
727 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
728 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
26a1d07f
HS		 729 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
730 txdesc->u.ht.mpdu_density);
731 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
732 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
59679b91
GW		 733 rt2x00_set_field32(&word, TXWI_W0_BW,
734 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
735 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
736 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
26a1d07f 737 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
59679b91
GW		 738 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
739 rt2x00_desc_write(txwi, 0, word);
740
741 rt2x00_desc_read(txwi, 1, &word);
742 rt2x00_set_field32(&word, TXWI_W1_ACK,
743 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
744 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
745 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
26a1d07f 746 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
59679b91
GW		 747 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
748 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
a2b1328a 749 txdesc->key_idx : txdesc->u.ht.wcid);
59679b91
GW		 750 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
751 txdesc->length);
2b23cdaa 752 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
bc8a979e 753 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
59679b91
GW		 754 rt2x00_desc_write(txwi, 1, word);
755
756 /*
557985ae
SG		 757 * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert
758 * the IV from the IVEIV register when TXD_W3_WIV is set to 0.
59679b91
GW		 759 * When TXD_W3_WIV is set to 1 it will use the IV data
760 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
761 * crypto entry in the registers should be used to encrypt the frame.
557985ae
SG		 762 *
763 * Nulify all remaining words as well, we don't know how to program them.
59679b91 764 */
557985ae
SG		 765 for (i = 2; i < entry->queue->winfo_size / sizeof(__le32); i++)
766 _rt2x00_desc_write(txwi, i, 0);
59679b91 767}
0c5879bc 768EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
59679b91 769
ff6133be 770static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
2de64dd2 771{
7fc41755
LT		 772 s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
773 s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
774 s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
74861922
ID		 775 u16 eeprom;
776 u8 offset0;
777 u8 offset1;
778 u8 offset2;
779
e5ef5bad 780 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
3e38d3da 781 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
74861922
ID		 782 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
783 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
3e38d3da 784 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
74861922
ID		 785 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
786 } else {
3e38d3da 787 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
74861922
ID		 788 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
789 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
3e38d3da 790 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
74861922
ID		 791 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
792 }
793
794 /*
795 * Convert the value from the descriptor into the RSSI value
796 * If the value in the descriptor is 0, it is considered invalid
797 * and the default (extremely low) rssi value is assumed
798 */
799 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
800 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
801 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
802
803 /*
804 * mac80211 only accepts a single RSSI value. Calculating the
805 * average doesn't deliver a fair answer either since -60:-60 would
806 * be considered equally good as -50:-70 while the second is the one
807 * which gives less energy...
808 */
809 rssi0 = max(rssi0, rssi1);
7fc41755 810 return (int)max(rssi0, rssi2);
74861922
ID		 811}
812
813void rt2800_process_rxwi(struct queue_entry *entry,
814 struct rxdone_entry_desc *rxdesc)
815{
816 __le32 *rxwi = (__le32 *) entry->skb->data;
2de64dd2
GW		 817 u32 word;
818
819 rt2x00_desc_read(rxwi, 0, &word);
820
821 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
822 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
823
824 rt2x00_desc_read(rxwi, 1, &word);
825
826 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
827 rxdesc->flags |= RX_FLAG_SHORT_GI;
828
829 if (rt2x00_get_field32(word, RXWI_W1_BW))
830 rxdesc->flags |= RX_FLAG_40MHZ;
831
832 /*
833 * Detect RX rate, always use MCS as signal type.
834 */
835 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
836 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
837 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
838
839 /*
840 * Mask of 0x8 bit to remove the short preamble flag.
841 */
842 if (rxdesc->rate_mode == RATE_MODE_CCK)
843 rxdesc->signal &= ~0x8;
844
845 rt2x00_desc_read(rxwi, 2, &word);
846
74861922
ID		 847 /*
848 * Convert descriptor AGC value to RSSI value.
849 */
850 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
f0bda571
SG		 851 /*
852 * Remove RXWI descriptor from start of the buffer.
853 */
854 skb_pull(entry->skb, entry->queue->winfo_size);
2de64dd2
GW		 855}
856EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
857
31937c42 858void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi)
14433331
HS		 859{
860 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
b34793ee 861 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
14433331
HS		 862 struct txdone_entry_desc txdesc;
863 u32 word;
864 u16 mcs, real_mcs;
b34793ee 865 int aggr, ampdu;
14433331
HS		 866
867 /*
868 * Obtain the status about this packet.
869 */
870 txdesc.flags = 0;
14433331 871 rt2x00_desc_read(txwi, 0, &word);
b34793ee 872
14433331 873 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
b34793ee
HS		 874 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
875
14433331 876 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
b34793ee
HS		 877 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
878
879 /*
880 * If a frame was meant to be sent as a single non-aggregated MPDU
881 * but ended up in an aggregate the used tx rate doesn't correlate
882 * with the one specified in the TXWI as the whole aggregate is sent
883 * with the same rate.
884 *
885 * For example: two frames are sent to rt2x00, the first one sets
886 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
887 * and requests MCS15. If the hw aggregates both frames into one
888 * AMDPU the tx status for both frames will contain MCS7 although
889 * the frame was sent successfully.
890 *
891 * Hence, replace the requested rate with the real tx rate to not
892 * confuse the rate control algortihm by providing clearly wrong
893 * data.
894 */
5356d963 895 if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
b34793ee
HS		 896 skbdesc->tx_rate_idx = real_mcs;
897 mcs = real_mcs;
898 }
14433331 899
f16d2db7
HS		 900 if (aggr == 1 || ampdu == 1)
901 __set_bit(TXDONE_AMPDU, &txdesc.flags);
902
14433331
HS		 903 /*
904 * Ralink has a retry mechanism using a global fallback
905 * table. We setup this fallback table to try the immediate
906 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
907 * always contains the MCS used for the last transmission, be
908 * it successful or not.
909 */
910 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
911 /*
912 * Transmission succeeded. The number of retries is
913 * mcs - real_mcs
914 */
915 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
916 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
917 } else {
918 /*
919 * Transmission failed. The number of retries is
920 * always 7 in this case (for a total number of 8
921 * frames sent).
922 */
923 __set_bit(TXDONE_FAILURE, &txdesc.flags);
924 txdesc.retry = rt2x00dev->long_retry;
925 }
926
927 /*
928 * the frame was retried at least once
929 * -> hw used fallback rates
930 */
931 if (txdesc.retry)
932 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
933
934 rt2x00lib_txdone(entry, &txdesc);
935}
936EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
937
21c6af6b
GJ		 938static unsigned int rt2800_hw_beacon_base(struct rt2x00_dev *rt2x00dev,
939 unsigned int index)
940{
941 return HW_BEACON_BASE(index);
942}
943
634b8059
GJ		 944static inline u8 rt2800_get_beacon_offset(struct rt2x00_dev *rt2x00dev,
945 unsigned int index)
946{
947 return BEACON_BASE_TO_OFFSET(rt2800_hw_beacon_base(rt2x00dev, index));
948}
949
ba08910e
SG		 950static void rt2800_update_beacons_setup(struct rt2x00_dev *rt2x00dev)
951{
952 struct data_queue *queue = rt2x00dev->bcn;
953 struct queue_entry *entry;
954 int i, bcn_num = 0;
955 u64 off, reg = 0;
956 u32 bssid_dw1;
957
958 /*
959 * Setup offsets of all active beacons in BCN_OFFSET{0,1} registers.
960 */
961 for (i = 0; i < queue->limit; i++) {
962 entry = &queue->entries[i];
963 if (!test_bit(ENTRY_BCN_ENABLED, &entry->flags))
964 continue;
965 off = rt2800_get_beacon_offset(rt2x00dev, entry->entry_idx);
966 reg |= off << (8 * bcn_num);
967 bcn_num++;
968 }
969
970 WARN_ON_ONCE(bcn_num != rt2x00dev->intf_beaconing);
971
972 rt2800_register_write(rt2x00dev, BCN_OFFSET0, (u32) reg);
973 rt2800_register_write(rt2x00dev, BCN_OFFSET1, (u32) (reg >> 32));
974
975 /*
976 * H/W sends up to MAC_BSSID_DW1_BSS_BCN_NUM + 1 consecutive beacons.
977 */
978 rt2800_register_read(rt2x00dev, MAC_BSSID_DW1, &bssid_dw1);
979 rt2x00_set_field32(&bssid_dw1, MAC_BSSID_DW1_BSS_BCN_NUM,
980 bcn_num > 0 ? bcn_num - 1 : 0);
981 rt2800_register_write(rt2x00dev, MAC_BSSID_DW1, bssid_dw1);
982}
983
f0194b2d
GW		 984void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
985{
986 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
987 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
988 unsigned int beacon_base;
739fd940 989 unsigned int padding_len;
d76dfc61 990 u32 orig_reg, reg;
f0bda571 991 const int txwi_desc_size = entry->queue->winfo_size;
f0194b2d
GW		 992
993 /*
994 * Disable beaconing while we are reloading the beacon data,
995 * otherwise we might be sending out invalid data.
996 */
997 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
d76dfc61 998 orig_reg = reg;
f0194b2d
GW		 999 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1000 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1001
1002 /*
1003 * Add space for the TXWI in front of the skb.
1004 */
f0bda571 1005 memset(skb_push(entry->skb, txwi_desc_size), 0, txwi_desc_size);
f0194b2d
GW		 1006
1007 /*
1008 * Register descriptor details in skb frame descriptor.
1009 */
1010 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
1011 skbdesc->desc = entry->skb->data;
f0bda571 1012 skbdesc->desc_len = txwi_desc_size;
f0194b2d
GW		 1013
1014 /*
1015 * Add the TXWI for the beacon to the skb.
1016 */
0c5879bc 1017 rt2800_write_tx_data(entry, txdesc);
f0194b2d
GW		 1018
1019 /*
1020 * Dump beacon to userspace through debugfs.
1021 */
1022 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
1023
1024 /*
739fd940 1025 * Write entire beacon with TXWI and padding to register.
f0194b2d 1026 */
739fd940 1027 padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
d76dfc61 1028 if (padding_len && skb_pad(entry->skb, padding_len)) {
ec9c4989 1029 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n");
d76dfc61
SF		 1030 /* skb freed by skb_pad() on failure */
1031 entry->skb = NULL;
1032 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1033 return;
1034 }
1035
21c6af6b
GJ		 1036 beacon_base = rt2800_hw_beacon_base(rt2x00dev, entry->entry_idx);
1037
739fd940
WK		 1038 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
1039 entry->skb->len + padding_len);
ba08910e
SG		 1040 __set_bit(ENTRY_BCN_ENABLED, &entry->flags);
1041
1042 /*
1043 * Change global beacons settings.
1044 */
1045 rt2800_update_beacons_setup(rt2x00dev);
f0194b2d
GW		 1046
1047 /*
bc0df75a 1048 * Restore beaconing state.
f0194b2d 1049 */
bc0df75a 1050 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
f0194b2d
GW		 1051
1052 /*
1053 * Clean up beacon skb.
1054 */
1055 dev_kfree_skb_any(entry->skb);
1056 entry->skb = NULL;
1057}
50e888ea 1058EXPORT_SYMBOL_GPL(rt2800_write_beacon);
f0194b2d 1059
69cf36a4 1060static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
77f7c0f3 1061 unsigned int index)
fdb87251
HS		 1062{
1063 int i;
0879f875 1064 const int txwi_desc_size = rt2x00dev->bcn->winfo_size;
77f7c0f3
GJ		 1065 unsigned int beacon_base;
1066
21c6af6b 1067 beacon_base = rt2800_hw_beacon_base(rt2x00dev, index);
fdb87251
HS		 1068
1069 /*
1070 * For the Beacon base registers we only need to clear
1071 * the whole TXWI which (when set to 0) will invalidate
1072 * the entire beacon.
1073 */
f0bda571 1074 for (i = 0; i < txwi_desc_size; i += sizeof(__le32))
fdb87251
HS		 1075 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
1076}
1077
69cf36a4
HS		 1078void rt2800_clear_beacon(struct queue_entry *entry)
1079{
1080 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
bc0df75a 1081 u32 orig_reg, reg;
69cf36a4
HS		 1082
1083 /*
1084 * Disable beaconing while we are reloading the beacon data,
1085 * otherwise we might be sending out invalid data.
1086 */
bc0df75a
SG		 1087 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &orig_reg);
1088 reg = orig_reg;
69cf36a4
HS		 1089 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1090 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1091
1092 /*
1093 * Clear beacon.
1094 */
77f7c0f3 1095 rt2800_clear_beacon_register(rt2x00dev, entry->entry_idx);
ba08910e 1096 __clear_bit(ENTRY_BCN_ENABLED, &entry->flags);
69cf36a4 1097
ba08910e
SG		 1098 /*
1099 * Change global beacons settings.
1100 */
1101 rt2800_update_beacons_setup(rt2x00dev);
69cf36a4 1102 /*
bc0df75a 1103 * Restore beaconing state.
69cf36a4 1104 */
bc0df75a 1105 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
69cf36a4
HS		 1106}
1107EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
1108
f4450616
BZ		 1109#ifdef CONFIG_RT2X00_LIB_DEBUGFS
1110const struct rt2x00debug rt2800_rt2x00debug = {
1111 .owner = THIS_MODULE,
1112 .csr = {
1113 .read = rt2800_register_read,
1114 .write = rt2800_register_write,
1115 .flags = RT2X00DEBUGFS_OFFSET,
1116 .word_base = CSR_REG_BASE,
1117 .word_size = sizeof(u32),
1118 .word_count = CSR_REG_SIZE / sizeof(u32),
1119 },
1120 .eeprom = {
3e38d3da
GJ		 1121 /* NOTE: The local EEPROM access functions can't
1122 * be used here, use the generic versions instead.
1123 */
f4450616
BZ		 1124 .read = rt2x00_eeprom_read,
1125 .write = rt2x00_eeprom_write,
1126 .word_base = EEPROM_BASE,
1127 .word_size = sizeof(u16),
1128 .word_count = EEPROM_SIZE / sizeof(u16),
1129 },
1130 .bbp = {
1131 .read = rt2800_bbp_read,
1132 .write = rt2800_bbp_write,
1133 .word_base = BBP_BASE,
1134 .word_size = sizeof(u8),
1135 .word_count = BBP_SIZE / sizeof(u8),
1136 },
1137 .rf = {
1138 .read = rt2x00_rf_read,
1139 .write = rt2800_rf_write,
1140 .word_base = RF_BASE,
1141 .word_size = sizeof(u32),
1142 .word_count = RF_SIZE / sizeof(u32),
1143 },
f2bd7f16
AA		 1144 .rfcsr = {
1145 .read = rt2800_rfcsr_read,
1146 .write = rt2800_rfcsr_write,
1147 .word_base = RFCSR_BASE,
1148 .word_size = sizeof(u8),
1149 .word_count = RFCSR_SIZE / sizeof(u8),
1150 },
f4450616
BZ		 1151};
1152EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
1153#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1154
1155int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
1156{
1157 u32 reg;
1158
a89534ed
WH		 1159 if (rt2x00_rt(rt2x00dev, RT3290)) {
1160 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
1161 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0);
1162 } else {
99bdf51a
GW		 1163 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1164 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2);
a89534ed 1165 }
f4450616
BZ		 1166}
1167EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
1168
1169#ifdef CONFIG_RT2X00_LIB_LEDS
1170static void rt2800_brightness_set(struct led_classdev *led_cdev,
1171 enum led_brightness brightness)
1172{
1173 struct rt2x00_led *led =
1174 container_of(led_cdev, struct rt2x00_led, led_dev);
1175 unsigned int enabled = brightness != LED_OFF;
1176 unsigned int bg_mode =
1177 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
1178 unsigned int polarity =
1179 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1180 EEPROM_FREQ_LED_POLARITY);
1181 unsigned int ledmode =
1182 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1183 EEPROM_FREQ_LED_MODE);
44704e5d 1184 u32 reg;
f4450616 1185
44704e5d
LE		 1186 /* Check for SoC (SOC devices don't support MCU requests) */
1187 if (rt2x00_is_soc(led->rt2x00dev)) {
1188 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
1189
1190 /* Set LED Polarity */
1191 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
1192
1193 /* Set LED Mode */
1194 if (led->type == LED_TYPE_RADIO) {
1195 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
1196 enabled ? 3 : 0);
1197 } else if (led->type == LED_TYPE_ASSOC) {
1198 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
1199 enabled ? 3 : 0);
1200 } else if (led->type == LED_TYPE_QUALITY) {
1201 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
1202 enabled ? 3 : 0);
1203 }
1204
1205 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
1206
1207 } else {
1208 if (led->type == LED_TYPE_RADIO) {
1209 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1210 enabled ? 0x20 : 0);
1211 } else if (led->type == LED_TYPE_ASSOC) {
1212 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1213 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
1214 } else if (led->type == LED_TYPE_QUALITY) {
1215 /*
1216 * The brightness is divided into 6 levels (0 - 5),
1217 * The specs tell us the following levels:
1218 * 0, 1 ,3, 7, 15, 31
1219 * to determine the level in a simple way we can simply
1220 * work with bitshifting:
1221 * (1 << level) - 1
1222 */
1223 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
1224 (1 << brightness / (LED_FULL / 6)) - 1,
1225 polarity);
1226 }
f4450616
BZ		 1227 }
1228}
1229
b3579d6a 1230static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
f4450616
BZ		 1231 struct rt2x00_led *led, enum led_type type)
1232{
1233 led->rt2x00dev = rt2x00dev;
1234 led->type = type;
1235 led->led_dev.brightness_set = rt2800_brightness_set;
f4450616
BZ		 1236 led->flags = LED_INITIALIZED;
1237}
f4450616
BZ		 1238#endif /* CONFIG_RT2X00_LIB_LEDS */
1239
1240/*
1241 * Configuration handlers.
1242 */
a2b1328a
HS		 1243static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
1244 const u8 *address,
1245 int wcid)
f4450616
BZ		 1246{
1247 struct mac_wcid_entry wcid_entry;
a2b1328a
HS		 1248 u32 offset;
1249
1250 offset = MAC_WCID_ENTRY(wcid);
1251
1252 memset(&wcid_entry, 0xff, sizeof(wcid_entry));
1253 if (address)
1254 memcpy(wcid_entry.mac, address, ETH_ALEN);
1255
1256 rt2800_register_multiwrite(rt2x00dev, offset,
1257 &wcid_entry, sizeof(wcid_entry));
1258}
1259
1260static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
1261{
1262 u32 offset;
1263 offset = MAC_WCID_ATTR_ENTRY(wcid);
1264 rt2800_register_write(rt2x00dev, offset, 0);
1265}
1266
1267static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
1268 int wcid, u32 bssidx)
1269{
1270 u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
1271 u32 reg;
1272
1273 /*
1274 * The BSS Idx numbers is split in a main value of 3 bits,
1275 * and a extended field for adding one additional bit to the value.
1276 */
1277 rt2800_register_read(rt2x00dev, offset, &reg);
1278 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
1279 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
1280 (bssidx & 0x8) >> 3);
1281 rt2800_register_write(rt2x00dev, offset, reg);
1282}
1283
1284static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
1285 struct rt2x00lib_crypto *crypto,
1286 struct ieee80211_key_conf *key)
1287{
f4450616
BZ		 1288 struct mac_iveiv_entry iveiv_entry;
1289 u32 offset;
1290 u32 reg;
1291
1292 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
1293
e4a0ab34
ID		 1294 if (crypto->cmd == SET_KEY) {
1295 rt2800_register_read(rt2x00dev, offset, &reg);
1296 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
1297 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
1298 /*
1299 * Both the cipher as the BSS Idx numbers are split in a main
1300 * value of 3 bits, and a extended field for adding one additional
1301 * bit to the value.
1302 */
1303 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
1304 (crypto->cipher & 0x7));
1305 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1306 (crypto->cipher & 0x8) >> 3);
e4a0ab34
ID		 1307 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1308 rt2800_register_write(rt2x00dev, offset, reg);
1309 } else {
a2b1328a
HS		 1310 /* Delete the cipher without touching the bssidx */
1311 rt2800_register_read(rt2x00dev, offset, &reg);
1312 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
1313 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
1314 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
1315 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
1316 rt2800_register_write(rt2x00dev, offset, reg);
e4a0ab34 1317 }
f4450616
BZ		 1318
1319 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1320
1321 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1322 if ((crypto->cipher == CIPHER_TKIP) ||
1323 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1324 (crypto->cipher == CIPHER_AES))
1325 iveiv_entry.iv[3] |= 0x20;
1326 iveiv_entry.iv[3] |= key->keyidx << 6;
1327 rt2800_register_multiwrite(rt2x00dev, offset,
1328 &iveiv_entry, sizeof(iveiv_entry));
f4450616
BZ		 1329}
1330
1331int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1332 struct rt2x00lib_crypto *crypto,
1333 struct ieee80211_key_conf *key)
1334{
1335 struct hw_key_entry key_entry;
1336 struct rt2x00_field32 field;
1337 u32 offset;
1338 u32 reg;
1339
1340 if (crypto->cmd == SET_KEY) {
1341 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1342
1343 memcpy(key_entry.key, crypto->key,
1344 sizeof(key_entry.key));
1345 memcpy(key_entry.tx_mic, crypto->tx_mic,
1346 sizeof(key_entry.tx_mic));
1347 memcpy(key_entry.rx_mic, crypto->rx_mic,
1348 sizeof(key_entry.rx_mic));
1349
1350 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1351 rt2800_register_multiwrite(rt2x00dev, offset,
1352 &key_entry, sizeof(key_entry));
1353 }
1354
1355 /*
1356 * The cipher types are stored over multiple registers
1357 * starting with SHARED_KEY_MODE_BASE each word will have
1358 * 32 bits and contains the cipher types for 2 bssidx each.
1359 * Using the correct defines correctly will cause overhead,
1360 * so just calculate the correct offset.
1361 */
1362 field.bit_offset = 4 * (key->hw_key_idx % 8);
1363 field.bit_mask = 0x7 << field.bit_offset;
1364
1365 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1366
1367 rt2800_register_read(rt2x00dev, offset, &reg);
1368 rt2x00_set_field32(&reg, field,
1369 (crypto->cmd == SET_KEY) * crypto->cipher);
1370 rt2800_register_write(rt2x00dev, offset, reg);
1371
1372 /*
1373 * Update WCID information
1374 */
a2b1328a
HS		 1375 rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1376 rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1377 crypto->bssidx);
1378 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
f4450616
BZ		 1379
1380 return 0;
1381}
1382EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1383
a2b1328a 1384static inline int rt2800_find_wcid(struct rt2x00_dev *rt2x00dev)
1ed3811c 1385{
a2b1328a 1386 struct mac_wcid_entry wcid_entry;
1ed3811c 1387 int idx;
a2b1328a 1388 u32 offset;
1ed3811c
HS		 1389
1390 /*
a2b1328a
HS		 1391 * Search for the first free WCID entry and return the corresponding
1392 * index.
1ed3811c
HS		 1393 *
1394 * Make sure the WCID starts _after_ the last possible shared key
1395 * entry (>32).
1396 *
1397 * Since parts of the pairwise key table might be shared with
1398 * the beacon frame buffers 6 & 7 we should only write into the
1399 * first 222 entries.
1400 */
1401 for (idx = 33; idx <= 222; idx++) {
a2b1328a
HS		 1402 offset = MAC_WCID_ENTRY(idx);
1403 rt2800_register_multiread(rt2x00dev, offset, &wcid_entry,
1404 sizeof(wcid_entry));
1405 if (is_broadcast_ether_addr(wcid_entry.mac))
1ed3811c
HS		 1406 return idx;
1407 }
a2b1328a
HS		 1408
1409 /*
1410 * Use -1 to indicate that we don't have any more space in the WCID
1411 * table.
1412 */
1ed3811c
HS		 1413 return -1;
1414}
1415
f4450616
BZ		 1416int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1417 struct rt2x00lib_crypto *crypto,
1418 struct ieee80211_key_conf *key)
1419{
1420 struct hw_key_entry key_entry;
1421 u32 offset;
1422
1423 if (crypto->cmd == SET_KEY) {
a2b1328a
HS		 1424 /*
1425 * Allow key configuration only for STAs that are
1426 * known by the hw.
1427 */
1428 if (crypto->wcid < 0)
f4450616 1429 return -ENOSPC;
a2b1328a 1430 key->hw_key_idx = crypto->wcid;
f4450616
BZ		 1431
1432 memcpy(key_entry.key, crypto->key,
1433 sizeof(key_entry.key));
1434 memcpy(key_entry.tx_mic, crypto->tx_mic,
1435 sizeof(key_entry.tx_mic));
1436 memcpy(key_entry.rx_mic, crypto->rx_mic,
1437 sizeof(key_entry.rx_mic));
1438
1439 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1440 rt2800_register_multiwrite(rt2x00dev, offset,
1441 &key_entry, sizeof(key_entry));
1442 }
1443
1444 /*
1445 * Update WCID information
1446 */
a2b1328a 1447 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
f4450616
BZ		 1448
1449 return 0;
1450}
1451EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1452
a2b1328a
HS		 1453int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif,
1454 struct ieee80211_sta *sta)
1455{
1456 int wcid;
1457 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1458
1459 /*
1460 * Find next free WCID.
1461 */
1462 wcid = rt2800_find_wcid(rt2x00dev);
1463
1464 /*
1465 * Store selected wcid even if it is invalid so that we can
1466 * later decide if the STA is uploaded into the hw.
1467 */
1468 sta_priv->wcid = wcid;
1469
1470 /*
1471 * No space left in the device, however, we can still communicate
1472 * with the STA -> No error.
1473 */
1474 if (wcid < 0)
1475 return 0;
1476
1477 /*
1478 * Clean up WCID attributes and write STA address to the device.
1479 */
1480 rt2800_delete_wcid_attr(rt2x00dev, wcid);
1481 rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1482 rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1483 rt2x00lib_get_bssidx(rt2x00dev, vif));
1484 return 0;
1485}
1486EXPORT_SYMBOL_GPL(rt2800_sta_add);
1487
1488int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, int wcid)
1489{
1490 /*
1491 * Remove WCID entry, no need to clean the attributes as they will
1492 * get renewed when the WCID is reused.
1493 */
1494 rt2800_config_wcid(rt2x00dev, NULL, wcid);
1495
1496 return 0;
1497}
1498EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1499
f4450616
BZ		 1500void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1501 const unsigned int filter_flags)
1502{
1503 u32 reg;
1504
1505 /*
1506 * Start configuration steps.
1507 * Note that the version error will always be dropped
1508 * and broadcast frames will always be accepted since
1509 * there is no filter for it at this time.
1510 */
1511 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1512 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1513 !(filter_flags & FIF_FCSFAIL));
1514 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1515 !(filter_flags & FIF_PLCPFAIL));
df140465 1516 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME, 1);
f4450616
BZ		 1517 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1518 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1519 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1520 !(filter_flags & FIF_ALLMULTI));
1521 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1522 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1523 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1524 !(filter_flags & FIF_CONTROL));
1525 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1526 !(filter_flags & FIF_CONTROL));
1527 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1528 !(filter_flags & FIF_CONTROL));
1529 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1530 !(filter_flags & FIF_CONTROL));
1531 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1532 !(filter_flags & FIF_CONTROL));
1533 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1534 !(filter_flags & FIF_PSPOLL));
84e9e8eb 1535 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 0);
48839938
HS		 1536 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,
1537 !(filter_flags & FIF_CONTROL));
f4450616
BZ		 1538 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1539 !(filter_flags & FIF_CONTROL));
1540 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1541}
1542EXPORT_SYMBOL_GPL(rt2800_config_filter);
1543
1544void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1545 struct rt2x00intf_conf *conf, const unsigned int flags)
1546{
f4450616 1547 u32 reg;
fa8b4b22 1548 bool update_bssid = false;
f4450616
BZ		 1549
1550 if (flags & CONFIG_UPDATE_TYPE) {
f4450616
BZ		 1551 /*
1552 * Enable synchronisation.
1553 */
1554 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
f4450616 1555 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
f4450616 1556 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
15a533c4
HS		 1557
1558 if (conf->sync == TSF_SYNC_AP_NONE) {
1559 /*
1560 * Tune beacon queue transmit parameters for AP mode
1561 */
1562 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1563 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1564 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1565 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1566 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1567 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1568 } else {
1569 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1570 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1571 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1572 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1573 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1574 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1575 }
f4450616
BZ		 1576 }
1577
1578 if (flags & CONFIG_UPDATE_MAC) {
fa8b4b22
HS		 1579 if (flags & CONFIG_UPDATE_TYPE &&
1580 conf->sync == TSF_SYNC_AP_NONE) {
1581 /*
1582 * The BSSID register has to be set to our own mac
1583 * address in AP mode.
1584 */
1585 memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1586 update_bssid = true;
1587 }
1588
c600c826
ID		 1589 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1590 reg = le32_to_cpu(conf->mac[1]);
1591 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1592 conf->mac[1] = cpu_to_le32(reg);
1593 }
f4450616
BZ		 1594
1595 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1596 conf->mac, sizeof(conf->mac));
1597 }
1598
fa8b4b22 1599 if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
c600c826
ID		 1600 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1601 reg = le32_to_cpu(conf->bssid[1]);
1602 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
88ff2f45 1603 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
c600c826
ID		 1604 conf->bssid[1] = cpu_to_le32(reg);
1605 }
f4450616
BZ		 1606
1607 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1608 conf->bssid, sizeof(conf->bssid));
1609 }
1610}
1611EXPORT_SYMBOL_GPL(rt2800_config_intf);
1612
87c1915d
HS		 1613static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1614 struct rt2x00lib_erp *erp)
1615{
1616 bool any_sta_nongf = !!(erp->ht_opmode &
1617 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1618 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1619 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1620 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1621 u32 reg;
1622
1623 /* default protection rate for HT20: OFDM 24M */
1624 mm20_rate = gf20_rate = 0x4004;
1625
1626 /* default protection rate for HT40: duplicate OFDM 24M */
1627 mm40_rate = gf40_rate = 0x4084;
1628
1629 switch (protection) {
1630 case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1631 /*
1632 * All STAs in this BSS are HT20/40 but there might be
1633 * STAs not supporting greenfield mode.
1634 * => Disable protection for HT transmissions.
1635 */
1636 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1637
1638 break;
1639 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1640 /*
1641 * All STAs in this BSS are HT20 or HT20/40 but there
1642 * might be STAs not supporting greenfield mode.
1643 * => Protect all HT40 transmissions.
1644 */
1645 mm20_mode = gf20_mode = 0;
1646 mm40_mode = gf40_mode = 2;
1647
1648 break;
1649 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1650 /*
1651 * Nonmember protection:
1652 * According to 802.11n we _should_ protect all
1653 * HT transmissions (but we don't have to).
1654 *
1655 * But if cts_protection is enabled we _shall_ protect
1656 * all HT transmissions using a CCK rate.
1657 *
1658 * And if any station is non GF we _shall_ protect
1659 * GF transmissions.
1660 *
1661 * We decide to protect everything
1662 * -> fall through to mixed mode.
1663 */
1664 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1665 /*
1666 * Legacy STAs are present
1667 * => Protect all HT transmissions.
1668 */
1669 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1670
1671 /*
1672 * If erp protection is needed we have to protect HT
1673 * transmissions with CCK 11M long preamble.
1674 */
1675 if (erp->cts_protection) {
1676 /* don't duplicate RTS/CTS in CCK mode */
1677 mm20_rate = mm40_rate = 0x0003;
1678 gf20_rate = gf40_rate = 0x0003;
1679 }
1680 break;
6403eab1 1681 }
87c1915d
HS		 1682
1683 /* check for STAs not supporting greenfield mode */
1684 if (any_sta_nongf)
1685 gf20_mode = gf40_mode = 2;
1686
1687 /* Update HT protection config */
1688 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1689 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1690 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1691 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1692
1693 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1694 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1695 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1696 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1697
1698 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1699 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1700 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1701 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1702
1703 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1704 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1705 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1706 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1707}
1708
02044643
HS		 1709void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1710 u32 changed)
f4450616
BZ		 1711{
1712 u32 reg;
1713
02044643
HS		 1714 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1715 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1716 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1717 !!erp->short_preamble);
1718 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1719 !!erp->short_preamble);
1720 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1721 }
f4450616 1722
02044643
HS		 1723 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1724 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1725 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1726 erp->cts_protection ? 2 : 0);
1727 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1728 }
f4450616 1729
02044643
HS		 1730 if (changed & BSS_CHANGED_BASIC_RATES) {
1731 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1732 erp->basic_rates);
1733 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1734 }
f4450616 1735
02044643
HS		 1736 if (changed & BSS_CHANGED_ERP_SLOT) {
1737 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1738 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1739 erp->slot_time);
1740 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
f4450616 1741
02044643
HS		 1742 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1743 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1744 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1745 }
f4450616 1746
02044643
HS		 1747 if (changed & BSS_CHANGED_BEACON_INT) {
1748 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1749 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1750 erp->beacon_int * 16);
1751 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1752 }
87c1915d
HS		 1753
1754 if (changed & BSS_CHANGED_HT)
1755 rt2800_config_ht_opmode(rt2x00dev, erp);
f4450616
BZ		 1756}
1757EXPORT_SYMBOL_GPL(rt2800_config_erp);
1758
872834df
GW		 1759static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
1760{
1761 u32 reg;
1762 u16 eeprom;
1763 u8 led_ctrl, led_g_mode, led_r_mode;
1764
1765 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
1766 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1767 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
1768 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
1769 } else {
1770 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
1771 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
1772 }
1773 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1774
1775 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1776 led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
1777 led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
1778 if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
1779 led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
3e38d3da 1780 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
872834df
GW		 1781 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
1782 if (led_ctrl == 0 || led_ctrl > 0x40) {
1783 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
1784 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
1785 rt2800_register_write(rt2x00dev, LED_CFG, reg);
1786 } else {
1787 rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
1788 (led_g_mode << 2) | led_r_mode, 1);
1789 }
1790 }
1791}
1792
d96aa640
RJH		 1793static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1794 enum antenna ant)
1795{
1796 u32 reg;
1797 u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1798 u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1799
1800 if (rt2x00_is_pci(rt2x00dev)) {
1801 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1802 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1803 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1804 } else if (rt2x00_is_usb(rt2x00dev))
1805 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1806 eesk_pin, 0);
1807
99bdf51a
GW		 1808 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1809 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
1810 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, gpio_bit3);
1811 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
d96aa640
RJH		 1812}
1813
f4450616
BZ		 1814void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1815{
1816 u8 r1;
1817 u8 r3;
d96aa640 1818 u16 eeprom;
f4450616
BZ		 1819
1820 rt2800_bbp_read(rt2x00dev, 1, &r1);
1821 rt2800_bbp_read(rt2x00dev, 3, &r3);
1822
872834df 1823 if (rt2x00_rt(rt2x00dev, RT3572) &&
c429dfef 1824 rt2x00_has_cap_bt_coexist(rt2x00dev))
872834df
GW		 1825 rt2800_config_3572bt_ant(rt2x00dev);
1826
f4450616
BZ		 1827 /*
1828 * Configure the TX antenna.
1829 */
d96aa640 1830 switch (ant->tx_chain_num) {
f4450616
BZ		 1831 case 1:
1832 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
f4450616
BZ		 1833 break;
1834 case 2:
872834df 1835 if (rt2x00_rt(rt2x00dev, RT3572) &&
c429dfef 1836 rt2x00_has_cap_bt_coexist(rt2x00dev))
872834df
GW		 1837 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
1838 else
1839 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
f4450616
BZ		 1840 break;
1841 case 3:
4788ac1e 1842 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
f4450616
BZ		 1843 break;
1844 }
1845
1846 /*
1847 * Configure the RX antenna.
1848 */
d96aa640 1849 switch (ant->rx_chain_num) {
f4450616 1850 case 1:
d96aa640
RJH		 1851 if (rt2x00_rt(rt2x00dev, RT3070) ||
1852 rt2x00_rt(rt2x00dev, RT3090) ||
03839951 1853 rt2x00_rt(rt2x00dev, RT3352) ||
d96aa640 1854 rt2x00_rt(rt2x00dev, RT3390)) {
3e38d3da 1855 rt2800_eeprom_read(rt2x00dev,
d96aa640
RJH		 1856 EEPROM_NIC_CONF1, &eeprom);
1857 if (rt2x00_get_field16(eeprom,
1858 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1859 rt2800_set_ant_diversity(rt2x00dev,
1860 rt2x00dev->default_ant.rx);
1861 }
f4450616
BZ		 1862 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1863 break;
1864 case 2:
872834df 1865 if (rt2x00_rt(rt2x00dev, RT3572) &&
c429dfef 1866 rt2x00_has_cap_bt_coexist(rt2x00dev)) {
872834df
GW		 1867 rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
1868 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
1869 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
1870 rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
1871 } else {
1872 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1873 }
f4450616
BZ		 1874 break;
1875 case 3:
1876 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1877 break;
1878 }
1879
1880 rt2800_bbp_write(rt2x00dev, 3, r3);
1881 rt2800_bbp_write(rt2x00dev, 1, r1);
5cddb3c2
GJ		 1882
1883 if (rt2x00_rt(rt2x00dev, RT3593)) {
1884 if (ant->rx_chain_num == 1)
1885 rt2800_bbp_write(rt2x00dev, 86, 0x00);
1886 else
1887 rt2800_bbp_write(rt2x00dev, 86, 0x46);
1888 }
f4450616
BZ		 1889}
1890EXPORT_SYMBOL_GPL(rt2800_config_ant);
1891
1892static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1893 struct rt2x00lib_conf *libconf)
1894{
1895 u16 eeprom;
1896 short lna_gain;
1897
1898 if (libconf->rf.channel <= 14) {
3e38d3da 1899 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
f4450616
BZ		 1900 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1901 } else if (libconf->rf.channel <= 64) {
3e38d3da 1902 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
f4450616
BZ		 1903 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1904 } else if (libconf->rf.channel <= 128) {
f36bb0ca
GJ		 1905 if (rt2x00_rt(rt2x00dev, RT3593)) {
1906 rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &eeprom);
1907 lna_gain = rt2x00_get_field16(eeprom,
1908 EEPROM_EXT_LNA2_A1);
1909 } else {
1910 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1911 lna_gain = rt2x00_get_field16(eeprom,
1912 EEPROM_RSSI_BG2_LNA_A1);
1913 }
f4450616 1914 } else {
f36bb0ca
GJ		 1915 if (rt2x00_rt(rt2x00dev, RT3593)) {
1916 rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &eeprom);
1917 lna_gain = rt2x00_get_field16(eeprom,
1918 EEPROM_EXT_LNA2_A2);
1919 } else {
1920 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1921 lna_gain = rt2x00_get_field16(eeprom,
1922 EEPROM_RSSI_A2_LNA_A2);
1923 }
f4450616
BZ		 1924 }
1925
1926 rt2x00dev->lna_gain = lna_gain;
1927}
1928
3f1b8739
GJ		 1929#define FREQ_OFFSET_BOUND 0x5f
1930
1931static void rt2800_adjust_freq_offset(struct rt2x00_dev *rt2x00dev)
1932{
1933 u8 freq_offset, prev_freq_offset;
1934 u8 rfcsr, prev_rfcsr;
1935
1936 freq_offset = rt2x00_get_field8(rt2x00dev->freq_offset, RFCSR17_CODE);
1937 freq_offset = min_t(u8, freq_offset, FREQ_OFFSET_BOUND);
1938
1939 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1940 prev_rfcsr = rfcsr;
1941
1942 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, freq_offset);
1943 if (rfcsr == prev_rfcsr)
1944 return;
1945
1946 if (rt2x00_is_usb(rt2x00dev)) {
1947 rt2800_mcu_request(rt2x00dev, MCU_FREQ_OFFSET, 0xff,
1948 freq_offset, prev_rfcsr);
1949 return;
1950 }
1951
1952 prev_freq_offset = rt2x00_get_field8(prev_rfcsr, RFCSR17_CODE);
1953 while (prev_freq_offset != freq_offset) {
1954 if (prev_freq_offset < freq_offset)
1955 prev_freq_offset++;
1956 else
1957 prev_freq_offset--;
1958
1959 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, prev_freq_offset);
1960 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
1961
1962 usleep_range(1000, 1500);
1963 }
1964}
1965
06855ef4
GW		 1966static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1967 struct ieee80211_conf *conf,
1968 struct rf_channel *rf,
1969 struct channel_info *info)
f4450616
BZ		 1970{
1971 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1972
d96aa640 1973 if (rt2x00dev->default_ant.tx_chain_num == 1)
f4450616
BZ		 1974 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1975
d96aa640 1976 if (rt2x00dev->default_ant.rx_chain_num == 1) {
f4450616
BZ		 1977 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1978 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
d96aa640 1979 } else if (rt2x00dev->default_ant.rx_chain_num == 2)
f4450616
BZ		 1980 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1981
1982 if (rf->channel > 14) {
1983 /*
1984 * When TX power is below 0, we should increase it by 7 to
25985edc 1985 * make it a positive value (Minimum value is -7).
f4450616
BZ		 1986 * However this means that values between 0 and 7 have
1987 * double meaning, and we should set a 7DBm boost flag.
1988 */
1989 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
8d1331b3 1990 (info->default_power1 >= 0));
f4450616 1991
8d1331b3
ID		 1992 if (info->default_power1 < 0)
1993 info->default_power1 += 7;
f4450616 1994
8d1331b3 1995 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
f4450616
BZ		 1996
1997 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
8d1331b3 1998 (info->default_power2 >= 0));
f4450616 1999
8d1331b3
ID		 2000 if (info->default_power2 < 0)
2001 info->default_power2 += 7;
f4450616 2002
8d1331b3 2003 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
f4450616 2004 } else {
8d1331b3
ID		 2005 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
2006 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
f4450616
BZ		 2007 }
2008
2009 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
2010
2011 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2012 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2013 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
2014 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2015
2016 udelay(200);
2017
2018 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2019 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2020 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
2021 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2022
2023 udelay(200);
2024
2025 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2026 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2027 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
2028 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2029}
2030
06855ef4
GW		 2031static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
2032 struct ieee80211_conf *conf,
2033 struct rf_channel *rf,
2034 struct channel_info *info)
f4450616 2035{
3a1c0128 2036 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
f1f12f98 2037 u8 rfcsr, calib_tx, calib_rx;
f4450616
BZ		 2038
2039 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
7f4666ab
SG		 2040
2041 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2042 rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
2043 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
f4450616
BZ		 2044
2045 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
fab799c3 2046 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
f4450616
BZ		 2047 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2048
2049 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
8d1331b3 2050 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
f4450616
BZ		 2051 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2052
5a673964 2053 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
8d1331b3 2054 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
5a673964 2055 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
e3bab197
SG		 2056
2057 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2058 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
7ad63035
GW		 2059 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2060 rt2x00dev->default_ant.rx_chain_num <= 1);
2061 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD,
2062 rt2x00dev->default_ant.rx_chain_num <= 2);
e3bab197 2063 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
7ad63035
GW		 2064 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2065 rt2x00dev->default_ant.tx_chain_num <= 1);
2066 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD,
2067 rt2x00dev->default_ant.tx_chain_num <= 2);
e3bab197 2068 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5a673964 2069
f4450616
BZ		 2070 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
2071 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2072 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2073
f1f12f98
SG		 2074 if (rt2x00_rt(rt2x00dev, RT3390)) {
2075 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
2076 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
2077 } else {
3a1c0128
GW		 2078 if (conf_is_ht40(conf)) {
2079 calib_tx = drv_data->calibration_bw40;
2080 calib_rx = drv_data->calibration_bw40;
2081 } else {
2082 calib_tx = drv_data->calibration_bw20;
2083 calib_rx = drv_data->calibration_bw20;
2084 }
f1f12f98
SG		 2085 }
2086
2087 rt2800_rfcsr_read(rt2x00dev, 24, &rfcsr);
2088 rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
2089 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
2090
2091 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
2092 rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
2093 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
f4450616 2094
71976907 2095 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
f4450616 2096 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
71976907 2097 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
3e0c7643
SG		 2098
2099 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2100 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2101 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2102 msleep(1);
2103 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2104 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
f4450616
BZ		 2105}
2106
872834df
GW		 2107static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
2108 struct ieee80211_conf *conf,
2109 struct rf_channel *rf,
2110 struct channel_info *info)
2111{
3a1c0128 2112 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
872834df
GW		 2113 u8 rfcsr;
2114 u32 reg;
2115
2116 if (rf->channel <= 14) {
5d137dff
GW		 2117 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2118 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
872834df
GW		 2119 } else {
2120 rt2800_bbp_write(rt2x00dev, 25, 0x09);
2121 rt2800_bbp_write(rt2x00dev, 26, 0xff);
2122 }
2123
2124 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
2125 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
2126
2127 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2128 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
2129 if (rf->channel <= 14)
2130 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
2131 else
2132 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
2133 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2134
2135 rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr);
2136 if (rf->channel <= 14)
2137 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
2138 else
2139 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
2140 rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
2141
2142 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
2143 if (rf->channel <= 14) {
2144 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
2145 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
569ffa56 2146 info->default_power1);
872834df
GW		 2147 } else {
2148 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
2149 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
2150 (info->default_power1 & 0x3) |
2151 ((info->default_power1 & 0xC) << 1));
2152 }
2153 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2154
2155 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
2156 if (rf->channel <= 14) {
2157 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
2158 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
569ffa56 2159 info->default_power2);
872834df
GW		 2160 } else {
2161 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
2162 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
2163 (info->default_power2 & 0x3) |
2164 ((info->default_power2 & 0xC) << 1));
2165 }
2166 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
2167
2168 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
872834df
GW		 2169 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2170 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2171 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2172 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
0cd461ef
GW		 2173 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2174 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
c429dfef 2175 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
872834df
GW		 2176 if (rf->channel <= 14) {
2177 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2178 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2179 }
2180 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2181 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2182 } else {
2183 switch (rt2x00dev->default_ant.tx_chain_num) {
2184 case 1:
2185 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2186 case 2:
2187 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2188 break;
2189 }
2190
2191 switch (rt2x00dev->default_ant.rx_chain_num) {
2192 case 1:
2193 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2194 case 2:
2195 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2196 break;
2197 }
2198 }
2199 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2200
2201 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
2202 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2203 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2204
3a1c0128
GW		 2205 if (conf_is_ht40(conf)) {
2206 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
2207 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
2208 } else {
2209 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
2210 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
2211 }
872834df
GW		 2212
2213 if (rf->channel <= 14) {
2214 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
2215 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
2216 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2217 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
2218 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
77c06c2c
GW		 2219 rfcsr = 0x4c;
2220 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2221 drv_data->txmixer_gain_24g);
2222 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
872834df
GW		 2223 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2224 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
2225 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
2226 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
2227 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2228 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2229 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
2230 } else {
58b8ae14
GW		 2231 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2232 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
2233 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
2234 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
2235 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
2236 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
872834df
GW		 2237 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2238 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2239 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
2240 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
77c06c2c
GW		 2241 rfcsr = 0x7a;
2242 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2243 drv_data->txmixer_gain_5g);
2244 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
872834df
GW		 2245 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2246 if (rf->channel <= 64) {
2247 rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
2248 rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
2249 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2250 } else if (rf->channel <= 128) {
2251 rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
2252 rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
2253 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2254 } else {
2255 rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
2256 rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
2257 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2258 }
2259 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
2260 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
2261 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
2262 }
2263
99bdf51a
GW		 2264 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
2265 rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
872834df 2266 if (rf->channel <= 14)
99bdf51a 2267 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
872834df 2268 else
99bdf51a
GW		 2269 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 0);
2270 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
872834df
GW		 2271
2272 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2273 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2274 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2275}
60687ba7 2276
f42b0465
GJ		 2277static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev,
2278 struct ieee80211_conf *conf,
2279 struct rf_channel *rf,
2280 struct channel_info *info)
2281{
2282 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2283 u8 txrx_agc_fc;
2284 u8 txrx_h20m;
2285 u8 rfcsr;
2286 u8 bbp;
2287 const bool txbf_enabled = false; /* TODO */
2288
2289 /* TODO: use TX{0,1,2}FinePowerControl values from EEPROM */
2290 rt2800_bbp_read(rt2x00dev, 109, &bbp);
2291 rt2x00_set_field8(&bbp, BBP109_TX0_POWER, 0);
2292 rt2x00_set_field8(&bbp, BBP109_TX1_POWER, 0);
2293 rt2800_bbp_write(rt2x00dev, 109, bbp);
2294
2295 rt2800_bbp_read(rt2x00dev, 110, &bbp);
2296 rt2x00_set_field8(&bbp, BBP110_TX2_POWER, 0);
2297 rt2800_bbp_write(rt2x00dev, 110, bbp);
2298
2299 if (rf->channel <= 14) {
2300 /* Restore BBP 25 & 26 for 2.4 GHz */
2301 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2302 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
2303 } else {
2304 /* Hard code BBP 25 & 26 for 5GHz */
2305
2306 /* Enable IQ Phase correction */
2307 rt2800_bbp_write(rt2x00dev, 25, 0x09);
2308 /* Setup IQ Phase correction value */
2309 rt2800_bbp_write(rt2x00dev, 26, 0xff);
2310 }
2311
2312 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2313 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3 & 0xf);
2314
2315 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2316 rt2x00_set_field8(&rfcsr, RFCSR11_R, (rf->rf2 & 0x3));
2317 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2318
2319 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2320 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_IDOH, 1);
2321 if (rf->channel <= 14)
2322 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 1);
2323 else
2324 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 2);
2325 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2326
2327 rt2800_rfcsr_read(rt2x00dev, 53, &rfcsr);
2328 if (rf->channel <= 14) {
2329 rfcsr = 0;
2330 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2331 info->default_power1 & 0x1f);
2332 } else {
2333 if (rt2x00_is_usb(rt2x00dev))
2334 rfcsr = 0x40;
2335
2336 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2337 ((info->default_power1 & 0x18) << 1) |
2338 (info->default_power1 & 7));
2339 }
2340 rt2800_rfcsr_write(rt2x00dev, 53, rfcsr);
2341
2342 rt2800_rfcsr_read(rt2x00dev, 55, &rfcsr);
2343 if (rf->channel <= 14) {
2344 rfcsr = 0;
2345 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2346 info->default_power2 & 0x1f);
2347 } else {
2348 if (rt2x00_is_usb(rt2x00dev))
2349 rfcsr = 0x40;
2350
2351 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2352 ((info->default_power2 & 0x18) << 1) |
2353 (info->default_power2 & 7));
2354 }
2355 rt2800_rfcsr_write(rt2x00dev, 55, rfcsr);
2356
2357 rt2800_rfcsr_read(rt2x00dev, 54, &rfcsr);
2358 if (rf->channel <= 14) {
2359 rfcsr = 0;
2360 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2361 info->default_power3 & 0x1f);
2362 } else {
2363 if (rt2x00_is_usb(rt2x00dev))
2364 rfcsr = 0x40;
2365
2366 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2367 ((info->default_power3 & 0x18) << 1) |
2368 (info->default_power3 & 7));
2369 }
2370 rt2800_rfcsr_write(rt2x00dev, 54, rfcsr);
2371
2372 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2373 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2374 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2375 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2376 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2377 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2378 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2379 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2380 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2381
2382 switch (rt2x00dev->default_ant.tx_chain_num) {
2383 case 3:
2384 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2385 /* fallthrough */
2386 case 2:
2387 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2388 /* fallthrough */
2389 case 1:
2390 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2391 break;
2392 }
2393
2394 switch (rt2x00dev->default_ant.rx_chain_num) {
2395 case 3:
2396 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2397 /* fallthrough */
2398 case 2:
2399 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2400 /* fallthrough */
2401 case 1:
2402 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2403 break;
2404 }
2405 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2406
e979a8ab 2407 rt2800_adjust_freq_offset(rt2x00dev);
f42b0465
GJ		 2408
2409 if (conf_is_ht40(conf)) {
2410 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw40,
2411 RFCSR24_TX_AGC_FC);
2412 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw40,
2413 RFCSR24_TX_H20M);
2414 } else {
2415 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw20,
2416 RFCSR24_TX_AGC_FC);
2417 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw20,
2418 RFCSR24_TX_H20M);
2419 }
2420
2421 /* NOTE: the reference driver does not writes the new value
2422 * back to RFCSR 32
2423 */
2424 rt2800_rfcsr_read(rt2x00dev, 32, &rfcsr);
2425 rt2x00_set_field8(&rfcsr, RFCSR32_TX_AGC_FC, txrx_agc_fc);
2426
2427 if (rf->channel <= 14)
2428 rfcsr = 0xa0;
2429 else
2430 rfcsr = 0x80;
2431 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2432
2433 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2434 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, txrx_h20m);
2435 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, txrx_h20m);
2436 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2437
2438 /* Band selection */
2439 rt2800_rfcsr_read(rt2x00dev, 36, &rfcsr);
2440 if (rf->channel <= 14)
2441 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1);
2442 else
2443 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0);
2444 rt2800_rfcsr_write(rt2x00dev, 36, rfcsr);
2445
2446 rt2800_rfcsr_read(rt2x00dev, 34, &rfcsr);
2447 if (rf->channel <= 14)
2448 rfcsr = 0x3c;
2449 else
2450 rfcsr = 0x20;
2451 rt2800_rfcsr_write(rt2x00dev, 34, rfcsr);
2452
2453 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
2454 if (rf->channel <= 14)
2455 rfcsr = 0x1a;
2456 else
2457 rfcsr = 0x12;
2458 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2459
2460 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2461 if (rf->channel >= 1 && rf->channel <= 14)
2462 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2463 else if (rf->channel >= 36 && rf->channel <= 64)
2464 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2465 else if (rf->channel >= 100 && rf->channel <= 128)
2466 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2467 else
2468 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2469 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2470
2471 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2472 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
2473 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2474
2475 rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
2476
2477 if (rf->channel <= 14) {
2478 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
2479 rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
2480 } else {
2481 rt2800_rfcsr_write(rt2x00dev, 10, 0xd8);
2482 rt2800_rfcsr_write(rt2x00dev, 13, 0x23);
2483 }
2484
2485 rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
2486 rt2x00_set_field8(&rfcsr, RFCSR51_BITS01, 1);
2487 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2488
2489 rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
2490 if (rf->channel <= 14) {
2491 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 5);
2492 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 3);
2493 } else {
2494 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 4);
2495 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 2);
2496 }
2497 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2498
2499 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2500 if (rf->channel <= 14)
2501 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 3);
2502 else
2503 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 2);
2504
2505 if (txbf_enabled)
2506 rt2x00_set_field8(&rfcsr, RFCSR49_TX_DIV, 1);
2507
2508 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2509
2510 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2511 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO1_EN, 0);
2512 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2513
2514 rt2800_rfcsr_read(rt2x00dev, 57, &rfcsr);
2515 if (rf->channel <= 14)
2516 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x1b);
2517 else
2518 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x0f);
2519 rt2800_rfcsr_write(rt2x00dev, 57, rfcsr);
2520
2521 if (rf->channel <= 14) {
2522 rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
2523 rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
2524 } else {
2525 rt2800_rfcsr_write(rt2x00dev, 44, 0x9b);
2526 rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
2527 }
2528
2529 /* Initiate VCO calibration */
2530 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2531 if (rf->channel <= 14) {
2532 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2533 } else {
2534 rt2x00_set_field8(&rfcsr, RFCSR3_BIT1, 1);
2535 rt2x00_set_field8(&rfcsr, RFCSR3_BIT2, 1);
2536 rt2x00_set_field8(&rfcsr, RFCSR3_BIT3, 1);
2537 rt2x00_set_field8(&rfcsr, RFCSR3_BIT4, 1);
2538 rt2x00_set_field8(&rfcsr, RFCSR3_BIT5, 1);
2539 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2540 }
2541 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2542
2543 if (rf->channel >= 1 && rf->channel <= 14) {
2544 rfcsr = 0x23;
2545 if (txbf_enabled)
2546 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2547 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2548
2549 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
2550 } else if (rf->channel >= 36 && rf->channel <= 64) {
2551 rfcsr = 0x36;
2552 if (txbf_enabled)
2553 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2554 rt2800_rfcsr_write(rt2x00dev, 39, 0x36);
2555
2556 rt2800_rfcsr_write(rt2x00dev, 45, 0xeb);
2557 } else if (rf->channel >= 100 && rf->channel <= 128) {
2558 rfcsr = 0x32;
2559 if (txbf_enabled)
2560 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2561 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2562
2563 rt2800_rfcsr_write(rt2x00dev, 45, 0xb3);
2564 } else {
2565 rfcsr = 0x30;
2566 if (txbf_enabled)
2567 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2568 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2569
2570 rt2800_rfcsr_write(rt2x00dev, 45, 0x9b);
2571 }
2572}
2573
7573cb5b 2574#define POWER_BOUND 0x27
8f821098 2575#define POWER_BOUND_5G 0x2b
0c9e5fb9 2576
a89534ed
WH		 2577static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
2578 struct ieee80211_conf *conf,
2579 struct rf_channel *rf,
2580 struct channel_info *info)
2581{
2582 u8 rfcsr;
2583
2584 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2585 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2586 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2587 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2588 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2589
2590 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
7573cb5b
SG		 2591 if (info->default_power1 > POWER_BOUND)
2592 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
a89534ed
WH		 2593 else
2594 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2595 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2596
0c9e5fb9 2597 rt2800_adjust_freq_offset(rt2x00dev);
a89534ed
WH		 2598
2599 if (rf->channel <= 14) {
2600 if (rf->channel == 6)
2601 rt2800_bbp_write(rt2x00dev, 68, 0x0c);
2602 else
2603 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
2604
2605 if (rf->channel >= 1 && rf->channel <= 6)
2606 rt2800_bbp_write(rt2x00dev, 59, 0x0f);
2607 else if (rf->channel >= 7 && rf->channel <= 11)
2608 rt2800_bbp_write(rt2x00dev, 59, 0x0e);
2609 else if (rf->channel >= 12 && rf->channel <= 14)
2610 rt2800_bbp_write(rt2x00dev, 59, 0x0d);
2611 }
2612}
2613
03839951
DG		 2614static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
2615 struct ieee80211_conf *conf,
2616 struct rf_channel *rf,
2617 struct channel_info *info)
2618{
2619 u8 rfcsr;
2620
2621 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2622 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2623
2624 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
2625 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
2626 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
2627
2628 if (info->default_power1 > POWER_BOUND)
2629 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND);
2630 else
2631 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);
2632
2633 if (info->default_power2 > POWER_BOUND)
2634 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND);
2635 else
2636 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
2637
0c9e5fb9 2638 rt2800_adjust_freq_offset(rt2x00dev);
03839951
DG		 2639
2640 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2641 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2642 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2643
2644 if ( rt2x00dev->default_ant.tx_chain_num == 2 )
2645 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2646 else
2647 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2648
2649 if ( rt2x00dev->default_ant.rx_chain_num == 2 )
2650 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2651 else
2652 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2653
2654 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2655 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2656
2657 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2658
2659 rt2800_rfcsr_write(rt2x00dev, 31, 80);
2660}
2661
60687ba7 2662static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
adde5882
GJ		 2663 struct ieee80211_conf *conf,
2664 struct rf_channel *rf,
2665 struct channel_info *info)
2666{
2667 u8 rfcsr;
adde5882
GJ		 2668
2669 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2670 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2671 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2672 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2673 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2674
2675 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
7573cb5b
SG		 2676 if (info->default_power1 > POWER_BOUND)
2677 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
adde5882
GJ		 2678 else
2679 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2680 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2681
cff3d1f0
ZL		 2682 if (rt2x00_rt(rt2x00dev, RT5392)) {
2683 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
6264995f 2684 if (info->default_power2 > POWER_BOUND)
7573cb5b 2685 rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND);
cff3d1f0
ZL		 2686 else
2687 rt2x00_set_field8(&rfcsr, RFCSR50_TX,
2688 info->default_power2);
2689 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2690 }
2691
adde5882 2692 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
cff3d1f0
ZL		 2693 if (rt2x00_rt(rt2x00dev, RT5392)) {
2694 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2695 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2696 }
adde5882
GJ		 2697 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2698 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2699 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2700 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2701 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2702
0c9e5fb9 2703 rt2800_adjust_freq_offset(rt2x00dev);
adde5882 2704
adde5882
GJ		 2705 if (rf->channel <= 14) {
2706 int idx = rf->channel-1;
2707
c429dfef 2708 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
adde5882
GJ		 2709 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2710 /* r55/r59 value array of channel 1~14 */
2711 static const char r55_bt_rev[] = {0x83, 0x83,
2712 0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
2713 0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
2714 static const char r59_bt_rev[] = {0x0e, 0x0e,
2715 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
2716 0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
2717
2718 rt2800_rfcsr_write(rt2x00dev, 55,
2719 r55_bt_rev[idx]);
2720 rt2800_rfcsr_write(rt2x00dev, 59,
2721 r59_bt_rev[idx]);
2722 } else {
2723 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
2724 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
2725 0x88, 0x88, 0x86, 0x85, 0x84};
2726
2727 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
2728 }
2729 } else {
2730 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2731 static const char r55_nonbt_rev[] = {0x23, 0x23,
2732 0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
2733 0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
2734 static const char r59_nonbt_rev[] = {0x07, 0x07,
2735 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
2736 0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
2737
2738 rt2800_rfcsr_write(rt2x00dev, 55,
2739 r55_nonbt_rev[idx]);
2740 rt2800_rfcsr_write(rt2x00dev, 59,
2741 r59_nonbt_rev[idx]);
2ed71884 2742 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
e6d227b9 2743 rt2x00_rt(rt2x00dev, RT5392)) {
adde5882
GJ		 2744 static const char r59_non_bt[] = {0x8f, 0x8f,
2745 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
2746 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
2747
2748 rt2800_rfcsr_write(rt2x00dev, 59,
2749 r59_non_bt[idx]);
2750 }
2751 }
2752 }
60687ba7
RST		 2753}
2754
8f821098
SG		 2755static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev,
2756 struct ieee80211_conf *conf,
2757 struct rf_channel *rf,
2758 struct channel_info *info)
2759{
2760 u8 rfcsr, ep_reg;
d5ae7a6b 2761 u32 reg;
8f821098
SG		 2762 int power_bound;
2763
2764 /* TODO */
2765 const bool is_11b = false;
2766 const bool is_type_ep = false;
2767
d5ae7a6b
SG		 2768 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2769 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL,
2770 (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0);
2771 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
8f821098
SG		 2772
2773 /* Order of values on rf_channel entry: N, K, mod, R */
2774 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff);
2775
2776 rt2800_rfcsr_read(rt2x00dev, 9, &rfcsr);
2777 rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf);
2778 rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8);
2779 rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2);
2780 rt2800_rfcsr_write(rt2x00dev, 9, rfcsr);
2781
2782 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2783 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1);
2784 rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3);
2785 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2786
2787 if (rf->channel <= 14) {
2788 rt2800_rfcsr_write(rt2x00dev, 10, 0x90);
2789 /* FIXME: RF11 owerwrite ? */
2790 rt2800_rfcsr_write(rt2x00dev, 11, 0x4A);
2791 rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
2792 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2793 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2794 rt2800_rfcsr_write(rt2x00dev, 24, 0x4A);
2795 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
2796 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2797 rt2800_rfcsr_write(rt2x00dev, 36, 0x80);
2798 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
2799 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
2800 rt2800_rfcsr_write(rt2x00dev, 39, 0x1B);
2801 rt2800_rfcsr_write(rt2x00dev, 40, 0x0D);
2802 rt2800_rfcsr_write(rt2x00dev, 41, 0x9B);
2803 rt2800_rfcsr_write(rt2x00dev, 42, 0xD5);
2804 rt2800_rfcsr_write(rt2x00dev, 43, 0x72);
2805 rt2800_rfcsr_write(rt2x00dev, 44, 0x0E);
2806 rt2800_rfcsr_write(rt2x00dev, 45, 0xA2);
2807 rt2800_rfcsr_write(rt2x00dev, 46, 0x6B);
2808 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
2809 rt2800_rfcsr_write(rt2x00dev, 51, 0x3E);
2810 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
2811 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
2812 rt2800_rfcsr_write(rt2x00dev, 56, 0xA1);
2813 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
2814 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
2815 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
2816 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
2817 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
2818
2819 /* TODO RF27 <- tssi */
2820
2821 rfcsr = rf->channel <= 10 ? 0x07 : 0x06;
2822 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2823 rt2800_rfcsr_write(rt2x00dev, 59, rfcsr);
2824
2825 if (is_11b) {
2826 /* CCK */
2827 rt2800_rfcsr_write(rt2x00dev, 31, 0xF8);
2828 rt2800_rfcsr_write(rt2x00dev, 32, 0xC0);
2829 if (is_type_ep)
2830 rt2800_rfcsr_write(rt2x00dev, 55, 0x06);
2831 else
2832 rt2800_rfcsr_write(rt2x00dev, 55, 0x47);
2833 } else {
2834 /* OFDM */
2835 if (is_type_ep)
2836 rt2800_rfcsr_write(rt2x00dev, 55, 0x03);
2837 else
2838 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
2839 }
2840
2841 power_bound = POWER_BOUND;
2842 ep_reg = 0x2;
2843 } else {
2844 rt2800_rfcsr_write(rt2x00dev, 10, 0x97);
2845 /* FIMXE: RF11 overwrite */
2846 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
2847 rt2800_rfcsr_write(rt2x00dev, 25, 0xBF);
2848 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2849 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
2850 rt2800_rfcsr_write(rt2x00dev, 37, 0x04);
2851 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
2852 rt2800_rfcsr_write(rt2x00dev, 40, 0x42);
2853 rt2800_rfcsr_write(rt2x00dev, 41, 0xBB);
2854 rt2800_rfcsr_write(rt2x00dev, 42, 0xD7);
2855 rt2800_rfcsr_write(rt2x00dev, 45, 0x41);
2856 rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
2857 rt2800_rfcsr_write(rt2x00dev, 57, 0x77);
2858 rt2800_rfcsr_write(rt2x00dev, 60, 0x05);
2859 rt2800_rfcsr_write(rt2x00dev, 61, 0x01);
2860
2861 /* TODO RF27 <- tssi */
2862
2863 if (rf->channel >= 36 && rf->channel <= 64) {
2864
2865 rt2800_rfcsr_write(rt2x00dev, 12, 0x2E);
2866 rt2800_rfcsr_write(rt2x00dev, 13, 0x22);
2867 rt2800_rfcsr_write(rt2x00dev, 22, 0x60);
2868 rt2800_rfcsr_write(rt2x00dev, 23, 0x7F);
2869 if (rf->channel <= 50)
2870 rt2800_rfcsr_write(rt2x00dev, 24, 0x09);
2871 else if (rf->channel >= 52)
2872 rt2800_rfcsr_write(rt2x00dev, 24, 0x07);
2873 rt2800_rfcsr_write(rt2x00dev, 39, 0x1C);
2874 rt2800_rfcsr_write(rt2x00dev, 43, 0x5B);
2875 rt2800_rfcsr_write(rt2x00dev, 44, 0X40);
2876 rt2800_rfcsr_write(rt2x00dev, 46, 0X00);
2877 rt2800_rfcsr_write(rt2x00dev, 51, 0xFE);
2878 rt2800_rfcsr_write(rt2x00dev, 52, 0x0C);
2879 rt2800_rfcsr_write(rt2x00dev, 54, 0xF8);
2880 if (rf->channel <= 50) {
2881 rt2800_rfcsr_write(rt2x00dev, 55, 0x06),
2882 rt2800_rfcsr_write(rt2x00dev, 56, 0xD3);
2883 } else if (rf->channel >= 52) {
2884 rt2800_rfcsr_write(rt2x00dev, 55, 0x04);
2885 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2886 }
2887
2888 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2889 rt2800_rfcsr_write(rt2x00dev, 59, 0x7F);
2890 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2891
2892 } else if (rf->channel >= 100 && rf->channel <= 165) {
2893
2894 rt2800_rfcsr_write(rt2x00dev, 12, 0x0E);
2895 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2896 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2897 if (rf->channel <= 153) {
2898 rt2800_rfcsr_write(rt2x00dev, 23, 0x3C);
2899 rt2800_rfcsr_write(rt2x00dev, 24, 0x06);
2900 } else if (rf->channel >= 155) {
2901 rt2800_rfcsr_write(rt2x00dev, 23, 0x38);
2902 rt2800_rfcsr_write(rt2x00dev, 24, 0x05);
2903 }
2904 if (rf->channel <= 138) {
2905 rt2800_rfcsr_write(rt2x00dev, 39, 0x1A);
2906 rt2800_rfcsr_write(rt2x00dev, 43, 0x3B);
2907 rt2800_rfcsr_write(rt2x00dev, 44, 0x20);
2908 rt2800_rfcsr_write(rt2x00dev, 46, 0x18);
2909 } else if (rf->channel >= 140) {
2910 rt2800_rfcsr_write(rt2x00dev, 39, 0x18);
2911 rt2800_rfcsr_write(rt2x00dev, 43, 0x1B);
2912 rt2800_rfcsr_write(rt2x00dev, 44, 0x10);
2913 rt2800_rfcsr_write(rt2x00dev, 46, 0X08);
2914 }
2915 if (rf->channel <= 124)
2916 rt2800_rfcsr_write(rt2x00dev, 51, 0xFC);
2917 else if (rf->channel >= 126)
2918 rt2800_rfcsr_write(rt2x00dev, 51, 0xEC);
2919 if (rf->channel <= 138)
2920 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2921 else if (rf->channel >= 140)
2922 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2923 rt2800_rfcsr_write(rt2x00dev, 54, 0xEB);
2924 if (rf->channel <= 138)
2925 rt2800_rfcsr_write(rt2x00dev, 55, 0x01);
2926 else if (rf->channel >= 140)
2927 rt2800_rfcsr_write(rt2x00dev, 55, 0x00);
2928 if (rf->channel <= 128)
2929 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2930 else if (rf->channel >= 130)
2931 rt2800_rfcsr_write(rt2x00dev, 56, 0xAB);
2932 if (rf->channel <= 116)
2933 rt2800_rfcsr_write(rt2x00dev, 58, 0x1D);
2934 else if (rf->channel >= 118)
2935 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2936 if (rf->channel <= 138)
2937 rt2800_rfcsr_write(rt2x00dev, 59, 0x3F);
2938 else if (rf->channel >= 140)
2939 rt2800_rfcsr_write(rt2x00dev, 59, 0x7C);
2940 if (rf->channel <= 116)
2941 rt2800_rfcsr_write(rt2x00dev, 62, 0x1D);
2942 else if (rf->channel >= 118)
2943 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2944 }
2945
2946 power_bound = POWER_BOUND_5G;
2947 ep_reg = 0x3;
2948 }
2949
2950 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2951 if (info->default_power1 > power_bound)
2952 rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound);
2953 else
2954 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2955 if (is_type_ep)
2956 rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg);
2957 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2958
2959 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
0847beb2 2960 if (info->default_power2 > power_bound)
8f821098
SG		 2961 rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound);
2962 else
2963 rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2);
2964 if (is_type_ep)
2965 rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg);
2966 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2967
2968 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2969 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2970 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2971
2972 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD,
2973 rt2x00dev->default_ant.tx_chain_num >= 1);
2974 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2975 rt2x00dev->default_ant.tx_chain_num == 2);
2976 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2977
2978 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD,
2979 rt2x00dev->default_ant.rx_chain_num >= 1);
2980 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2981 rt2x00dev->default_ant.rx_chain_num == 2);
2982 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2983
2984 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2985 rt2800_rfcsr_write(rt2x00dev, 6, 0xe4);
2986
2987 if (conf_is_ht40(conf))
2988 rt2800_rfcsr_write(rt2x00dev, 30, 0x16);
2989 else
2990 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
2991
2992 if (!is_11b) {
2993 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
2994 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
2995 }
2996
2997 /* TODO proper frequency adjustment */
0c9e5fb9 2998 rt2800_adjust_freq_offset(rt2x00dev);
8f821098
SG		 2999
3000 /* TODO merge with others */
3001 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
3002 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
3003 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
6803141b
SG		 3004
3005 /* BBP settings */
3006 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3007 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3008 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3009
3010 rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18);
3011 rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08);
3012 rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38);
3013 rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92);
3014
3015 /* GLRT band configuration */
3016 rt2800_bbp_write(rt2x00dev, 195, 128);
3017 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0);
3018 rt2800_bbp_write(rt2x00dev, 195, 129);
3019 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E);
3020 rt2800_bbp_write(rt2x00dev, 195, 130);
3021 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28);
3022 rt2800_bbp_write(rt2x00dev, 195, 131);
3023 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20);
3024 rt2800_bbp_write(rt2x00dev, 195, 133);
3025 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F);
3026 rt2800_bbp_write(rt2x00dev, 195, 124);
3027 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F);
8f821098
SG		 3028}
3029
5bc2dd06
SG		 3030static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev,
3031 const unsigned int word,
3032 const u8 value)
3033{
3034 u8 chain, reg;
3035
3036 for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) {
3037 rt2800_bbp_read(rt2x00dev, 27, &reg);
3038 rt2x00_set_field8(&reg, BBP27_RX_CHAIN_SEL, chain);
3039 rt2800_bbp_write(rt2x00dev, 27, reg);
3040
3041 rt2800_bbp_write(rt2x00dev, word, value);
3042 }
3043}
3044
8756130b
SG		 3045static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel)
3046{
3047 u8 cal;
3048
415e3f2f 3049 /* TX0 IQ Gain */
8756130b 3050 rt2800_bbp_write(rt2x00dev, 158, 0x2c);
415e3f2f
SG		 3051 if (channel <= 14)
3052 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G);
3053 else if (channel >= 36 && channel <= 64)
3054 cal = rt2x00_eeprom_byte(rt2x00dev,
3055 EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G);
3056 else if (channel >= 100 && channel <= 138)
3057 cal = rt2x00_eeprom_byte(rt2x00dev,
3058 EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G);
3059 else if (channel >= 140 && channel <= 165)
3060 cal = rt2x00_eeprom_byte(rt2x00dev,
3061 EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G);
3062 else
3063 cal = 0;
8756130b
SG		 3064 rt2800_bbp_write(rt2x00dev, 159, cal);
3065
415e3f2f 3066 /* TX0 IQ Phase */
8756130b 3067 rt2800_bbp_write(rt2x00dev, 158, 0x2d);
415e3f2f
SG		 3068 if (channel <= 14)
3069 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G);
3070 else if (channel >= 36 && channel <= 64)
3071 cal = rt2x00_eeprom_byte(rt2x00dev,
3072 EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G);
3073 else if (channel >= 100 && channel <= 138)
3074 cal = rt2x00_eeprom_byte(rt2x00dev,
3075 EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G);
3076 else if (channel >= 140 && channel <= 165)
3077 cal = rt2x00_eeprom_byte(rt2x00dev,
3078 EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G);
3079 else
3080 cal = 0;
8756130b
SG		 3081 rt2800_bbp_write(rt2x00dev, 159, cal);
3082
415e3f2f 3083 /* TX1 IQ Gain */
8756130b 3084 rt2800_bbp_write(rt2x00dev, 158, 0x4a);
415e3f2f
SG		 3085 if (channel <= 14)
3086 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G);
3087 else if (channel >= 36 && channel <= 64)
3088 cal = rt2x00_eeprom_byte(rt2x00dev,
3089 EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G);
3090 else if (channel >= 100 && channel <= 138)
3091 cal = rt2x00_eeprom_byte(rt2x00dev,
3092 EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G);
3093 else if (channel >= 140 && channel <= 165)
3094 cal = rt2x00_eeprom_byte(rt2x00dev,
3095 EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G);
3096 else
3097 cal = 0;
8756130b
SG		 3098 rt2800_bbp_write(rt2x00dev, 159, cal);
3099
415e3f2f 3100 /* TX1 IQ Phase */
8756130b 3101 rt2800_bbp_write(rt2x00dev, 158, 0x4b);
415e3f2f
SG		 3102 if (channel <= 14)
3103 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G);
3104 else if (channel >= 36 && channel <= 64)
3105 cal = rt2x00_eeprom_byte(rt2x00dev,
3106 EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G);
3107 else if (channel >= 100 && channel <= 138)
3108 cal = rt2x00_eeprom_byte(rt2x00dev,
3109 EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G);
3110 else if (channel >= 140 && channel <= 165)
3111 cal = rt2x00_eeprom_byte(rt2x00dev,
3112 EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G);
3113 else
3114 cal = 0;
8756130b
SG		 3115 rt2800_bbp_write(rt2x00dev, 159, cal);
3116
415e3f2f
SG		 3117 /* FIXME: possible RX0, RX1 callibration ? */
3118
8756130b
SG		 3119 /* RF IQ compensation control */
3120 rt2800_bbp_write(rt2x00dev, 158, 0x04);
3121 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL);
3122 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
3123
3124 /* RF IQ imbalance compensation control */
3125 rt2800_bbp_write(rt2x00dev, 158, 0x03);
415e3f2f
SG		 3126 cal = rt2x00_eeprom_byte(rt2x00dev,
3127 EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL);
8756130b
SG		 3128 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
3129}
3130
97aa03f1
GJ		 3131static char rt2800_txpower_to_dev(struct rt2x00_dev *rt2x00dev,
3132 unsigned int channel,
3133 char txpower)
3134{
fc739cfe
GJ		 3135 if (rt2x00_rt(rt2x00dev, RT3593))
3136 txpower = rt2x00_get_field8(txpower, EEPROM_TXPOWER_ALC);
3137
97aa03f1
GJ		 3138 if (channel <= 14)
3139 return clamp_t(char, txpower, MIN_G_TXPOWER, MAX_G_TXPOWER);
fc739cfe
GJ		 3140
3141 if (rt2x00_rt(rt2x00dev, RT3593))
3142 return clamp_t(char, txpower, MIN_A_TXPOWER_3593,
3143 MAX_A_TXPOWER_3593);
97aa03f1
GJ		 3144 else
3145 return clamp_t(char, txpower, MIN_A_TXPOWER, MAX_A_TXPOWER);
3146}
3147
f4450616
BZ		 3148static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
3149 struct ieee80211_conf *conf,
3150 struct rf_channel *rf,
3151 struct channel_info *info)
3152{
3153 u32 reg;
3154 unsigned int tx_pin;
a89534ed 3155 u8 bbp, rfcsr;
f4450616 3156
97aa03f1
GJ		 3157 info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3158 info->default_power1);
3159 info->default_power2 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3160 info->default_power2);
c0a14369
GJ		 3161 if (rt2x00dev->default_ant.tx_chain_num > 2)
3162 info->default_power3 =
3163 rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3164 info->default_power3);
46323e11 3165
5aa57015
GW		 3166 switch (rt2x00dev->chip.rf) {
3167 case RF2020:
3168 case RF3020:
3169 case RF3021:
3170 case RF3022:
3171 case RF3320:
06855ef4 3172 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
5aa57015
GW		 3173 break;
3174 case RF3052:
872834df 3175 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
5aa57015 3176 break;
f42b0465
GJ		 3177 case RF3053:
3178 rt2800_config_channel_rf3053(rt2x00dev, conf, rf, info);
3179 break;
a89534ed
WH		 3180 case RF3290:
3181 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
3182 break;
03839951
DG		 3183 case RF3322:
3184 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
3185 break;
3b9b74ba 3186 case RF3070:
ccf91bd6 3187 case RF5360:
ac0372ab 3188 case RF5362:
5aa57015 3189 case RF5370:
2ed71884 3190 case RF5372:
5aa57015 3191 case RF5390:
cff3d1f0 3192 case RF5392:
adde5882 3193 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
5aa57015 3194 break;
8f821098
SG		 3195 case RF5592:
3196 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info);
3197 break;
5aa57015 3198 default:
06855ef4 3199 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
5aa57015 3200 }
f4450616 3201
3b9b74ba
SG		 3202 if (rt2x00_rf(rt2x00dev, RF3070) ||
3203 rt2x00_rf(rt2x00dev, RF3290) ||
03839951 3204 rt2x00_rf(rt2x00dev, RF3322) ||
a89534ed 3205 rt2x00_rf(rt2x00dev, RF5360) ||
ac0372ab 3206 rt2x00_rf(rt2x00dev, RF5362) ||
a89534ed
WH		 3207 rt2x00_rf(rt2x00dev, RF5370) ||
3208 rt2x00_rf(rt2x00dev, RF5372) ||
3209 rt2x00_rf(rt2x00dev, RF5390) ||
3210 rt2x00_rf(rt2x00dev, RF5392)) {
3211 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3212 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
3213 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
3214 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3215
3216 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
d6d82020 3217 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
a89534ed
WH		 3218 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3219 }
3220
f4450616
BZ		 3221 /*
3222 * Change BBP settings
3223 */
03839951
DG		 3224 if (rt2x00_rt(rt2x00dev, RT3352)) {
3225 rt2800_bbp_write(rt2x00dev, 27, 0x0);
cf193f6d 3226 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
03839951 3227 rt2800_bbp_write(rt2x00dev, 27, 0x20);
cf193f6d 3228 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
f42b0465
GJ		 3229 } else if (rt2x00_rt(rt2x00dev, RT3593)) {
3230 if (rf->channel > 14) {
3231 /* Disable CCK Packet detection on 5GHz */
3232 rt2800_bbp_write(rt2x00dev, 70, 0x00);
3233 } else {
3234 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3235 }
3236
3237 if (conf_is_ht40(conf))
3238 rt2800_bbp_write(rt2x00dev, 105, 0x04);
3239 else
3240 rt2800_bbp_write(rt2x00dev, 105, 0x34);
3241
3242 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3243 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3244 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3245 rt2800_bbp_write(rt2x00dev, 77, 0x98);
03839951
DG		 3246 } else {
3247 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3248 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3249 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3250 rt2800_bbp_write(rt2x00dev, 86, 0);
3251 }
f4450616
BZ		 3252
3253 if (rf->channel <= 14) {
2ed71884 3254 if (!rt2x00_rt(rt2x00dev, RT5390) &&
e6d227b9 3255 !rt2x00_rt(rt2x00dev, RT5392)) {
c429dfef 3256 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
adde5882
GJ		 3257 rt2800_bbp_write(rt2x00dev, 82, 0x62);
3258 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3259 } else {
f42b0465
GJ		 3260 if (rt2x00_rt(rt2x00dev, RT3593))
3261 rt2800_bbp_write(rt2x00dev, 82, 0x62);
3262 else
3263 rt2800_bbp_write(rt2x00dev, 82, 0x84);
adde5882
GJ		 3264 rt2800_bbp_write(rt2x00dev, 75, 0x50);
3265 }
f42b0465
GJ		 3266 if (rt2x00_rt(rt2x00dev, RT3593))
3267 rt2800_bbp_write(rt2x00dev, 83, 0x8a);
f4450616 3268 }
f42b0465 3269
f4450616 3270 } else {
872834df
GW		 3271 if (rt2x00_rt(rt2x00dev, RT3572))
3272 rt2800_bbp_write(rt2x00dev, 82, 0x94);
f42b0465
GJ		 3273 else if (rt2x00_rt(rt2x00dev, RT3593))
3274 rt2800_bbp_write(rt2x00dev, 82, 0x82);
872834df
GW		 3275 else
3276 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
f4450616 3277
f42b0465
GJ		 3278 if (rt2x00_rt(rt2x00dev, RT3593))
3279 rt2800_bbp_write(rt2x00dev, 83, 0x9a);
3280
c429dfef 3281 if (rt2x00_has_cap_external_lna_a(rt2x00dev))
f4450616
BZ		 3282 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3283 else
3284 rt2800_bbp_write(rt2x00dev, 75, 0x50);
3285 }
3286
3287 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
a21ee724 3288 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 3289 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
3290 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
3291 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
3292
872834df
GW		 3293 if (rt2x00_rt(rt2x00dev, RT3572))
3294 rt2800_rfcsr_write(rt2x00dev, 8, 0);
3295
f4450616
BZ		 3296 tx_pin = 0;
3297
bb16d488
GJ		 3298 switch (rt2x00dev->default_ant.tx_chain_num) {
3299 case 3:
3300 /* Turn on tertiary PAs */
3301 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN,
3302 rf->channel > 14);
3303 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN,
3304 rf->channel <= 14);
3305 /* fall-through */
3306 case 2:
3307 /* Turn on secondary PAs */
65f31b5e
GW		 3308 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
3309 rf->channel > 14);
3310 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
3311 rf->channel <= 14);
bb16d488
GJ		 3312 /* fall-through */
3313 case 1:
3314 /* Turn on primary PAs */
3315 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN,
3316 rf->channel > 14);
c429dfef 3317 if (rt2x00_has_cap_bt_coexist(rt2x00dev))
bb16d488
GJ		 3318 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
3319 else
3320 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
3321 rf->channel <= 14);
3322 break;
f4450616
BZ		 3323 }
3324
bb16d488
GJ		 3325 switch (rt2x00dev->default_ant.rx_chain_num) {
3326 case 3:
3327 /* Turn on tertiary LNAs */
3328 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A2_EN, 1);
3329 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G2_EN, 1);
3330 /* fall-through */
3331 case 2:
3332 /* Turn on secondary LNAs */
f4450616
BZ		 3333 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
3334 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
bb16d488
GJ		 3335 /* fall-through */
3336 case 1:
3337 /* Turn on primary LNAs */
3338 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
3339 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
3340 break;
f4450616
BZ		 3341 }
3342
f4450616
BZ		 3343 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
3344 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
f4450616
BZ		 3345
3346 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
3347
733aec6a 3348 if (rt2x00_rt(rt2x00dev, RT3572)) {
872834df
GW		 3349 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
3350
733aec6a
GJ		 3351 /* AGC init */
3352 if (rf->channel <= 14)
3353 reg = 0x1c + (2 * rt2x00dev->lna_gain);
3354 else
3355 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
3356
3357 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3358 }
3359
f42b0465 3360 if (rt2x00_rt(rt2x00dev, RT3593)) {
60751001 3361 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
f42b0465 3362
60751001
GJ		 3363 /* Band selection */
3364 if (rt2x00_is_usb(rt2x00dev) ||
3365 rt2x00_is_pcie(rt2x00dev)) {
3366 /* GPIO #8 controls all paths */
f42b0465
GJ		 3367 rt2x00_set_field32(&reg, GPIO_CTRL_DIR8, 0);
3368 if (rf->channel <= 14)
3369 rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 1);
3370 else
3371 rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 0);
60751001 3372 }
f42b0465 3373
60751001
GJ		 3374 /* LNA PE control. */
3375 if (rt2x00_is_usb(rt2x00dev)) {
3376 /* GPIO #4 controls PE0 and PE1,
3377 * GPIO #7 controls PE2
3378 */
f42b0465
GJ		 3379 rt2x00_set_field32(&reg, GPIO_CTRL_DIR4, 0);
3380 rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
3381
f42b0465
GJ		 3382 rt2x00_set_field32(&reg, GPIO_CTRL_VAL4, 1);
3383 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
60751001
GJ		 3384 } else if (rt2x00_is_pcie(rt2x00dev)) {
3385 /* GPIO #4 controls PE0, PE1 and PE2 */
3386 rt2x00_set_field32(&reg, GPIO_CTRL_DIR4, 0);
3387 rt2x00_set_field32(&reg, GPIO_CTRL_VAL4, 1);
f42b0465
GJ		 3388 }
3389
60751001
GJ		 3390 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
3391
f42b0465
GJ		 3392 /* AGC init */
3393 if (rf->channel <= 14)
3394 reg = 0x1c + 2 * rt2x00dev->lna_gain;
3395 else
3396 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
3397
3398 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3399
3400 usleep_range(1000, 1500);
3401 }
3402
6803141b
SG		 3403 if (rt2x00_rt(rt2x00dev, RT5592)) {
3404 rt2800_bbp_write(rt2x00dev, 195, 141);
3405 rt2800_bbp_write(rt2x00dev, 196, conf_is_ht40(conf) ? 0x10 : 0x1a);
3406
8ba0ebf3
SG		 3407 /* AGC init */
3408 reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2 * rt2x00dev->lna_gain;
3409 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3410
8756130b 3411 rt2800_iq_calibrate(rt2x00dev, rf->channel);
6803141b
SG		 3412 }
3413
f4450616
BZ		 3414 rt2800_bbp_read(rt2x00dev, 4, &bbp);
3415 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
3416 rt2800_bbp_write(rt2x00dev, 4, bbp);
3417
3418 rt2800_bbp_read(rt2x00dev, 3, &bbp);
a21ee724 3419 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 3420 rt2800_bbp_write(rt2x00dev, 3, bbp);
3421
8d0c9b65 3422 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
f4450616
BZ		 3423 if (conf_is_ht40(conf)) {
3424 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
3425 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3426 rt2800_bbp_write(rt2x00dev, 73, 0x16);
3427 } else {
3428 rt2800_bbp_write(rt2x00dev, 69, 0x16);
3429 rt2800_bbp_write(rt2x00dev, 70, 0x08);
3430 rt2800_bbp_write(rt2x00dev, 73, 0x11);
3431 }
3432 }
3433
3434 msleep(1);
977206d7
HS		 3435
3436 /*
3437 * Clear channel statistic counters
3438 */
3439 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
3440 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
3441 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
03839951
DG		 3442
3443 /*
3444 * Clear update flag
3445 */
3446 if (rt2x00_rt(rt2x00dev, RT3352)) {
3447 rt2800_bbp_read(rt2x00dev, 49, &bbp);
3448 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0);
3449 rt2800_bbp_write(rt2x00dev, 49, bbp);
3450 }
f4450616
BZ		 3451}
3452
9e33a355
HS		 3453static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
3454{
3455 u8 tssi_bounds[9];
3456 u8 current_tssi;
3457 u16 eeprom;
3458 u8 step;
3459 int i;
3460
6e956da2
SG		 3461 /*
3462 * First check if temperature compensation is supported.
3463 */
3464 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3465 if (!rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC))
3466 return 0;
3467
9e33a355
HS		 3468 /*
3469 * Read TSSI boundaries for temperature compensation from
3470 * the EEPROM.
3471 *
3472 * Array idx 0 1 2 3 4 5 6 7 8
3473 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4
3474 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
3475 */
3476 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
3e38d3da 3477 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
9e33a355
HS		 3478 tssi_bounds[0] = rt2x00_get_field16(eeprom,
3479 EEPROM_TSSI_BOUND_BG1_MINUS4);
3480 tssi_bounds[1] = rt2x00_get_field16(eeprom,
3481 EEPROM_TSSI_BOUND_BG1_MINUS3);
3482
3e38d3da 3483 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
9e33a355
HS		 3484 tssi_bounds[2] = rt2x00_get_field16(eeprom,
3485 EEPROM_TSSI_BOUND_BG2_MINUS2);
3486 tssi_bounds[3] = rt2x00_get_field16(eeprom,
3487 EEPROM_TSSI_BOUND_BG2_MINUS1);
3488
3e38d3da 3489 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
9e33a355
HS		 3490 tssi_bounds[4] = rt2x00_get_field16(eeprom,
3491 EEPROM_TSSI_BOUND_BG3_REF);
3492 tssi_bounds[5] = rt2x00_get_field16(eeprom,
3493 EEPROM_TSSI_BOUND_BG3_PLUS1);
3494
3e38d3da 3495 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
9e33a355
HS		 3496 tssi_bounds[6] = rt2x00_get_field16(eeprom,
3497 EEPROM_TSSI_BOUND_BG4_PLUS2);
3498 tssi_bounds[7] = rt2x00_get_field16(eeprom,
3499 EEPROM_TSSI_BOUND_BG4_PLUS3);
3500
3e38d3da 3501 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
9e33a355
HS		 3502 tssi_bounds[8] = rt2x00_get_field16(eeprom,
3503 EEPROM_TSSI_BOUND_BG5_PLUS4);
3504
3505 step = rt2x00_get_field16(eeprom,
3506 EEPROM_TSSI_BOUND_BG5_AGC_STEP);
3507 } else {
3e38d3da 3508 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
9e33a355
HS		 3509 tssi_bounds[0] = rt2x00_get_field16(eeprom,
3510 EEPROM_TSSI_BOUND_A1_MINUS4);
3511 tssi_bounds[1] = rt2x00_get_field16(eeprom,
3512 EEPROM_TSSI_BOUND_A1_MINUS3);
3513
3e38d3da 3514 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
9e33a355
HS		 3515 tssi_bounds[2] = rt2x00_get_field16(eeprom,
3516 EEPROM_TSSI_BOUND_A2_MINUS2);
3517 tssi_bounds[3] = rt2x00_get_field16(eeprom,
3518 EEPROM_TSSI_BOUND_A2_MINUS1);
3519
3e38d3da 3520 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
9e33a355
HS		 3521 tssi_bounds[4] = rt2x00_get_field16(eeprom,
3522 EEPROM_TSSI_BOUND_A3_REF);
3523 tssi_bounds[5] = rt2x00_get_field16(eeprom,
3524 EEPROM_TSSI_BOUND_A3_PLUS1);
3525
3e38d3da 3526 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
9e33a355
HS		 3527 tssi_bounds[6] = rt2x00_get_field16(eeprom,
3528 EEPROM_TSSI_BOUND_A4_PLUS2);
3529 tssi_bounds[7] = rt2x00_get_field16(eeprom,
3530 EEPROM_TSSI_BOUND_A4_PLUS3);
3531
3e38d3da 3532 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
9e33a355
HS		 3533 tssi_bounds[8] = rt2x00_get_field16(eeprom,
3534 EEPROM_TSSI_BOUND_A5_PLUS4);
3535
3536 step = rt2x00_get_field16(eeprom,
3537 EEPROM_TSSI_BOUND_A5_AGC_STEP);
3538 }
3539
3540 /*
3541 * Check if temperature compensation is supported.
3542 */
bf7e1abe 3543 if (tssi_bounds[4] == 0xff || step == 0xff)
9e33a355
HS		 3544 return 0;
3545
3546 /*
3547 * Read current TSSI (BBP 49).
3548 */
3549 rt2800_bbp_read(rt2x00dev, 49, &current_tssi);
3550
3551 /*
3552 * Compare TSSI value (BBP49) with the compensation boundaries
3553 * from the EEPROM and increase or decrease tx power.
3554 */
3555 for (i = 0; i <= 3; i++) {
3556 if (current_tssi > tssi_bounds[i])
3557 break;
3558 }
3559
3560 if (i == 4) {
3561 for (i = 8; i >= 5; i--) {
3562 if (current_tssi < tssi_bounds[i])
3563 break;
3564 }
3565 }
3566
3567 return (i - 4) * step;
3568}
3569
e90c54b2
RJH		 3570static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
3571 enum ieee80211_band band)
3572{
3573 u16 eeprom;
3574 u8 comp_en;
3575 u8 comp_type;
75faae8b 3576 int comp_value = 0;
e90c54b2 3577
3e38d3da 3578 rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
e90c54b2 3579
75faae8b
HS		 3580 /*
3581 * HT40 compensation not required.
3582 */
3583 if (eeprom == 0xffff ||
3584 !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
e90c54b2
RJH		 3585 return 0;
3586
3587 if (band == IEEE80211_BAND_2GHZ) {
3588 comp_en = rt2x00_get_field16(eeprom,
3589 EEPROM_TXPOWER_DELTA_ENABLE_2G);
3590 if (comp_en) {
3591 comp_type = rt2x00_get_field16(eeprom,
3592 EEPROM_TXPOWER_DELTA_TYPE_2G);
3593 comp_value = rt2x00_get_field16(eeprom,
3594 EEPROM_TXPOWER_DELTA_VALUE_2G);
3595 if (!comp_type)
3596 comp_value = -comp_value;
3597 }
3598 } else {
3599 comp_en = rt2x00_get_field16(eeprom,
3600 EEPROM_TXPOWER_DELTA_ENABLE_5G);
3601 if (comp_en) {
3602 comp_type = rt2x00_get_field16(eeprom,
3603 EEPROM_TXPOWER_DELTA_TYPE_5G);
3604 comp_value = rt2x00_get_field16(eeprom,
3605 EEPROM_TXPOWER_DELTA_VALUE_5G);
3606 if (!comp_type)
3607 comp_value = -comp_value;
3608 }
3609 }
3610
3611 return comp_value;
3612}
3613
1e4cf249
SG		 3614static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev,
3615 int power_level, int max_power)
3616{
3617 int delta;
3618
c429dfef 3619 if (rt2x00_has_cap_power_limit(rt2x00dev))
1e4cf249
SG		 3620 return 0;
3621
3622 /*
3623 * XXX: We don't know the maximum transmit power of our hardware since
3624 * the EEPROM doesn't expose it. We only know that we are calibrated
3625 * to 100% tx power.
3626 *
3627 * Hence, we assume the regulatory limit that cfg80211 calulated for
3628 * the current channel is our maximum and if we are requested to lower
3629 * the value we just reduce our tx power accordingly.
3630 */
3631 delta = power_level - max_power;
3632 return min(delta, 0);
3633}
3634
fa71a160
HS		 3635static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
3636 enum ieee80211_band band, int power_level,
3637 u8 txpower, int delta)
e90c54b2 3638{
e90c54b2
RJH		 3639 u16 eeprom;
3640 u8 criterion;
3641 u8 eirp_txpower;
3642 u8 eirp_txpower_criterion;
3643 u8 reg_limit;
e90c54b2 3644
34542ff5
GJ		 3645 if (rt2x00_rt(rt2x00dev, RT3593))
3646 return min_t(u8, txpower, 0xc);
3647
c429dfef 3648 if (rt2x00_has_cap_power_limit(rt2x00dev)) {
e90c54b2
RJH		 3649 /*
3650 * Check if eirp txpower exceed txpower_limit.
3651 * We use OFDM 6M as criterion and its eirp txpower
3652 * is stored at EEPROM_EIRP_MAX_TX_POWER.
3653 * .11b data rate need add additional 4dbm
3654 * when calculating eirp txpower.
3655 */
022138ca
GJ		 3656 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3657 1, &eeprom);
d9bceaeb
SG		 3658 criterion = rt2x00_get_field16(eeprom,
3659 EEPROM_TXPOWER_BYRATE_RATE0);
e90c54b2 3660
3e38d3da 3661 rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER,
d9bceaeb 3662 &eeprom);
e90c54b2
RJH		 3663
3664 if (band == IEEE80211_BAND_2GHZ)
3665 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
3666 EEPROM_EIRP_MAX_TX_POWER_2GHZ);
3667 else
3668 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
3669 EEPROM_EIRP_MAX_TX_POWER_5GHZ);
3670
3671 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
2af242e1 3672 (is_rate_b ? 4 : 0) + delta;
e90c54b2
RJH		 3673
3674 reg_limit = (eirp_txpower > power_level) ?
3675 (eirp_txpower - power_level) : 0;
3676 } else
3677 reg_limit = 0;
3678
19f3fa24
SG		 3679 txpower = max(0, txpower + delta - reg_limit);
3680 return min_t(u8, txpower, 0xc);
e90c54b2
RJH		 3681}
3682
34542ff5
GJ		 3683
3684enum {
3685 TX_PWR_CFG_0_IDX,
3686 TX_PWR_CFG_1_IDX,
3687 TX_PWR_CFG_2_IDX,
3688 TX_PWR_CFG_3_IDX,
3689 TX_PWR_CFG_4_IDX,
3690 TX_PWR_CFG_5_IDX,
3691 TX_PWR_CFG_6_IDX,
3692 TX_PWR_CFG_7_IDX,
3693 TX_PWR_CFG_8_IDX,
3694 TX_PWR_CFG_9_IDX,
3695 TX_PWR_CFG_0_EXT_IDX,
3696 TX_PWR_CFG_1_EXT_IDX,
3697 TX_PWR_CFG_2_EXT_IDX,
3698 TX_PWR_CFG_3_EXT_IDX,
3699 TX_PWR_CFG_4_EXT_IDX,
3700 TX_PWR_CFG_IDX_COUNT,
3701};
3702
3703static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev,
3704 struct ieee80211_channel *chan,
3705 int power_level)
3706{
3707 u8 txpower;
3708 u16 eeprom;
3709 u32 regs[TX_PWR_CFG_IDX_COUNT];
3710 unsigned int offset;
3711 enum ieee80211_band band = chan->band;
3712 int delta;
3713 int i;
3714
3715 memset(regs, '\0', sizeof(regs));
3716
3717 /* TODO: adapt TX power reduction from the rt28xx code */
3718
3719 /* calculate temperature compensation delta */
3720 delta = rt2800_get_gain_calibration_delta(rt2x00dev);
3721
3722 if (band == IEEE80211_BAND_5GHZ)
3723 offset = 16;
3724 else
3725 offset = 0;
3726
3727 if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
3728 offset += 8;
3729
3730 /* read the next four txpower values */
3731 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3732 offset, &eeprom);
3733
3734 /* CCK 1MBS,2MBS */
3735 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3736 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
3737 txpower, delta);
3738 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3739 TX_PWR_CFG_0_CCK1_CH0, txpower);
3740 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3741 TX_PWR_CFG_0_CCK1_CH1, txpower);
3742 rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3743 TX_PWR_CFG_0_EXT_CCK1_CH2, txpower);
3744
3745 /* CCK 5.5MBS,11MBS */
3746 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3747 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
3748 txpower, delta);
3749 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3750 TX_PWR_CFG_0_CCK5_CH0, txpower);
3751 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3752 TX_PWR_CFG_0_CCK5_CH1, txpower);
3753 rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3754 TX_PWR_CFG_0_EXT_CCK5_CH2, txpower);
3755
3756 /* OFDM 6MBS,9MBS */
3757 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3758 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3759 txpower, delta);
3760 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3761 TX_PWR_CFG_0_OFDM6_CH0, txpower);
3762 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3763 TX_PWR_CFG_0_OFDM6_CH1, txpower);
3764 rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3765 TX_PWR_CFG_0_EXT_OFDM6_CH2, txpower);
3766
3767 /* OFDM 12MBS,18MBS */
3768 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3769 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3770 txpower, delta);
3771 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3772 TX_PWR_CFG_0_OFDM12_CH0, txpower);
3773 rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3774 TX_PWR_CFG_0_OFDM12_CH1, txpower);
3775 rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3776 TX_PWR_CFG_0_EXT_OFDM12_CH2, txpower);
3777
3778 /* read the next four txpower values */
3779 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3780 offset + 1, &eeprom);
3781
3782 /* OFDM 24MBS,36MBS */
3783 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3784 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3785 txpower, delta);
3786 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3787 TX_PWR_CFG_1_OFDM24_CH0, txpower);
3788 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3789 TX_PWR_CFG_1_OFDM24_CH1, txpower);
3790 rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3791 TX_PWR_CFG_1_EXT_OFDM24_CH2, txpower);
3792
3793 /* OFDM 48MBS */
3794 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3795 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3796 txpower, delta);
3797 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3798 TX_PWR_CFG_1_OFDM48_CH0, txpower);
3799 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3800 TX_PWR_CFG_1_OFDM48_CH1, txpower);
3801 rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3802 TX_PWR_CFG_1_EXT_OFDM48_CH2, txpower);
3803
3804 /* OFDM 54MBS */
3805 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3806 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3807 txpower, delta);
3808 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3809 TX_PWR_CFG_7_OFDM54_CH0, txpower);
3810 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3811 TX_PWR_CFG_7_OFDM54_CH1, txpower);
3812 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3813 TX_PWR_CFG_7_OFDM54_CH2, txpower);
3814
3815 /* read the next four txpower values */
3816 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3817 offset + 2, &eeprom);
3818
3819 /* MCS 0,1 */
3820 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3821 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3822 txpower, delta);
3823 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3824 TX_PWR_CFG_1_MCS0_CH0, txpower);
3825 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3826 TX_PWR_CFG_1_MCS0_CH1, txpower);
3827 rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3828 TX_PWR_CFG_1_EXT_MCS0_CH2, txpower);
3829
3830 /* MCS 2,3 */
3831 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3832 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3833 txpower, delta);
3834 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3835 TX_PWR_CFG_1_MCS2_CH0, txpower);
3836 rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3837 TX_PWR_CFG_1_MCS2_CH1, txpower);
3838 rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3839 TX_PWR_CFG_1_EXT_MCS2_CH2, txpower);
3840
3841 /* MCS 4,5 */
3842 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3843 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3844 txpower, delta);
3845 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3846 TX_PWR_CFG_2_MCS4_CH0, txpower);
3847 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3848 TX_PWR_CFG_2_MCS4_CH1, txpower);
3849 rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3850 TX_PWR_CFG_2_EXT_MCS4_CH2, txpower);
3851
3852 /* MCS 6 */
3853 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3854 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3855 txpower, delta);
3856 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3857 TX_PWR_CFG_2_MCS6_CH0, txpower);
3858 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3859 TX_PWR_CFG_2_MCS6_CH1, txpower);
3860 rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3861 TX_PWR_CFG_2_EXT_MCS6_CH2, txpower);
3862
3863 /* read the next four txpower values */
3864 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3865 offset + 3, &eeprom);
3866
3867 /* MCS 7 */
3868 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3869 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3870 txpower, delta);
3871 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3872 TX_PWR_CFG_7_MCS7_CH0, txpower);
3873 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3874 TX_PWR_CFG_7_MCS7_CH1, txpower);
3875 rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3876 TX_PWR_CFG_7_MCS7_CH2, txpower);
3877
3878 /* MCS 8,9 */
3879 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3880 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3881 txpower, delta);
3882 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3883 TX_PWR_CFG_2_MCS8_CH0, txpower);
3884 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3885 TX_PWR_CFG_2_MCS8_CH1, txpower);
3886 rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3887 TX_PWR_CFG_2_EXT_MCS8_CH2, txpower);
3888
3889 /* MCS 10,11 */
3890 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3891 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3892 txpower, delta);
3893 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3894 TX_PWR_CFG_2_MCS10_CH0, txpower);
3895 rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3896 TX_PWR_CFG_2_MCS10_CH1, txpower);
3897 rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3898 TX_PWR_CFG_2_EXT_MCS10_CH2, txpower);
3899
3900 /* MCS 12,13 */
3901 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3902 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3903 txpower, delta);
3904 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3905 TX_PWR_CFG_3_MCS12_CH0, txpower);
3906 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3907 TX_PWR_CFG_3_MCS12_CH1, txpower);
3908 rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3909 TX_PWR_CFG_3_EXT_MCS12_CH2, txpower);
3910
3911 /* read the next four txpower values */
3912 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3913 offset + 4, &eeprom);
3914
3915 /* MCS 14 */
3916 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3917 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3918 txpower, delta);
3919 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3920 TX_PWR_CFG_3_MCS14_CH0, txpower);
3921 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3922 TX_PWR_CFG_3_MCS14_CH1, txpower);
3923 rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3924 TX_PWR_CFG_3_EXT_MCS14_CH2, txpower);
3925
3926 /* MCS 15 */
3927 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3928 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3929 txpower, delta);
3930 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3931 TX_PWR_CFG_8_MCS15_CH0, txpower);
3932 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3933 TX_PWR_CFG_8_MCS15_CH1, txpower);
3934 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3935 TX_PWR_CFG_8_MCS15_CH2, txpower);
3936
3937 /* MCS 16,17 */
3938 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3939 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3940 txpower, delta);
3941 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3942 TX_PWR_CFG_5_MCS16_CH0, txpower);
3943 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3944 TX_PWR_CFG_5_MCS16_CH1, txpower);
3945 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3946 TX_PWR_CFG_5_MCS16_CH2, txpower);
3947
3948 /* MCS 18,19 */
3949 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3950 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3951 txpower, delta);
3952 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3953 TX_PWR_CFG_5_MCS18_CH0, txpower);
3954 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3955 TX_PWR_CFG_5_MCS18_CH1, txpower);
3956 rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3957 TX_PWR_CFG_5_MCS18_CH2, txpower);
3958
3959 /* read the next four txpower values */
3960 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3961 offset + 5, &eeprom);
3962
3963 /* MCS 20,21 */
3964 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3965 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3966 txpower, delta);
3967 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3968 TX_PWR_CFG_6_MCS20_CH0, txpower);
3969 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3970 TX_PWR_CFG_6_MCS20_CH1, txpower);
3971 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3972 TX_PWR_CFG_6_MCS20_CH2, txpower);
3973
3974 /* MCS 22 */
3975 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3976 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3977 txpower, delta);
3978 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3979 TX_PWR_CFG_6_MCS22_CH0, txpower);
3980 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3981 TX_PWR_CFG_6_MCS22_CH1, txpower);
3982 rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3983 TX_PWR_CFG_6_MCS22_CH2, txpower);
3984
3985 /* MCS 23 */
3986 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3987 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3988 txpower, delta);
3989 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3990 TX_PWR_CFG_8_MCS23_CH0, txpower);
3991 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3992 TX_PWR_CFG_8_MCS23_CH1, txpower);
3993 rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3994 TX_PWR_CFG_8_MCS23_CH2, txpower);
3995
3996 /* read the next four txpower values */
3997 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3998 offset + 6, &eeprom);
3999
4000 /* STBC, MCS 0,1 */
4001 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4002 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4003 txpower, delta);
4004 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4005 TX_PWR_CFG_3_STBC0_CH0, txpower);
4006 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4007 TX_PWR_CFG_3_STBC0_CH1, txpower);
4008 rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
4009 TX_PWR_CFG_3_EXT_STBC0_CH2, txpower);
4010
4011 /* STBC, MCS 2,3 */
4012 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4013 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4014 txpower, delta);
4015 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4016 TX_PWR_CFG_3_STBC2_CH0, txpower);
4017 rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4018 TX_PWR_CFG_3_STBC2_CH1, txpower);
4019 rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
4020 TX_PWR_CFG_3_EXT_STBC2_CH2, txpower);
4021
4022 /* STBC, MCS 4,5 */
4023 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4024 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4025 txpower, delta);
4026 rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE0, txpower);
4027 rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE1, txpower);
4028 rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE0,
4029 txpower);
4030
4031 /* STBC, MCS 6 */
4032 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4033 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4034 txpower, delta);
4035 rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE2, txpower);
4036 rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE3, txpower);
4037 rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE2,
4038 txpower);
4039
4040 /* read the next four txpower values */
4041 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4042 offset + 7, &eeprom);
4043
4044 /* STBC, MCS 7 */
4045 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4046 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4047 txpower, delta);
4048 rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
4049 TX_PWR_CFG_9_STBC7_CH0, txpower);
4050 rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
4051 TX_PWR_CFG_9_STBC7_CH1, txpower);
4052 rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
4053 TX_PWR_CFG_9_STBC7_CH2, txpower);
4054
4055 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, regs[TX_PWR_CFG_0_IDX]);
4056 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, regs[TX_PWR_CFG_1_IDX]);
4057 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, regs[TX_PWR_CFG_2_IDX]);
4058 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, regs[TX_PWR_CFG_3_IDX]);
4059 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, regs[TX_PWR_CFG_4_IDX]);
4060 rt2800_register_write(rt2x00dev, TX_PWR_CFG_5, regs[TX_PWR_CFG_5_IDX]);
4061 rt2800_register_write(rt2x00dev, TX_PWR_CFG_6, regs[TX_PWR_CFG_6_IDX]);
4062 rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, regs[TX_PWR_CFG_7_IDX]);
4063 rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, regs[TX_PWR_CFG_8_IDX]);
4064 rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, regs[TX_PWR_CFG_9_IDX]);
4065
4066 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0_EXT,
4067 regs[TX_PWR_CFG_0_EXT_IDX]);
4068 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1_EXT,
4069 regs[TX_PWR_CFG_1_EXT_IDX]);
4070 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2_EXT,
4071 regs[TX_PWR_CFG_2_EXT_IDX]);
4072 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3_EXT,
4073 regs[TX_PWR_CFG_3_EXT_IDX]);
4074 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4_EXT,
4075 regs[TX_PWR_CFG_4_EXT_IDX]);
4076
4077 for (i = 0; i < TX_PWR_CFG_IDX_COUNT; i++)
4078 rt2x00_dbg(rt2x00dev,
4079 "band:%cGHz, BW:%c0MHz, TX_PWR_CFG_%d%s = %08lx\n",
4080 (band == IEEE80211_BAND_5GHZ) ? '5' : '2',
4081 (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) ?
4082 '4' : '2',
4083 (i > TX_PWR_CFG_9_IDX) ?
4084 (i - TX_PWR_CFG_9_IDX - 1) : i,
4085 (i > TX_PWR_CFG_9_IDX) ? "_EXT" : "",
4086 (unsigned long) regs[i]);
4087}
4088
7a66205a
SG		 4089/*
4090 * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and
4091 * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values,
4092 * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power
4093 * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm.
4094 * Reference per rate transmit power values are located in the EEPROM at
4095 * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to
4096 * current conditions (i.e. band, bandwidth, temperature, user settings).
4097 */
34542ff5
GJ		 4098static void rt2800_config_txpower_rt28xx(struct rt2x00_dev *rt2x00dev,
4099 struct ieee80211_channel *chan,
4100 int power_level)
f4450616 4101{
cee2c731 4102 u8 txpower, r1;
5e846004 4103 u16 eeprom;
cee2c731
SG		 4104 u32 reg, offset;
4105 int i, is_rate_b, delta, power_ctrl;
146c3b0c 4106 enum ieee80211_band band = chan->band;
2af242e1
HS		 4107
4108 /*
7a66205a
SG		 4109 * Calculate HT40 compensation. For 40MHz we need to add or subtract
4110 * value read from EEPROM (different for 2GHz and for 5GHz).
2af242e1
HS		 4111 */
4112 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
f4450616 4113
9e33a355 4114 /*
7a66205a
SG		 4115 * Calculate temperature compensation. Depends on measurement of current
4116 * TSSI (Transmitter Signal Strength Indication) we know TX power (due
4117 * to temperature or maybe other factors) is smaller or bigger than
4118 * expected. We adjust it, based on TSSI reference and boundaries values
4119 * provided in EEPROM.
9e33a355 4120 */
87dd2d76
SG		 4121 switch (rt2x00dev->chip.rt) {
4122 case RT2860:
4123 case RT2872:
4124 case RT2883:
4125 case RT3070:
4126 case RT3071:
4127 case RT3090:
4128 case RT3572:
4129 delta += rt2800_get_gain_calibration_delta(rt2x00dev);
4130 break;
4131 default:
4132 /* TODO: temperature compensation code for other chips. */
4133 break;
4134 }
f4450616 4135
1e4cf249 4136 /*
7a66205a
SG		 4137 * Decrease power according to user settings, on devices with unknown
4138 * maximum tx power. For other devices we take user power_level into
4139 * consideration on rt2800_compensate_txpower().
1e4cf249
SG		 4140 */
4141 delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level,
4142 chan->max_power);
4143
5e846004 4144 /*
cee2c731
SG		 4145 * BBP_R1 controls TX power for all rates, it allow to set the following
4146 * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively.
4147 *
4148 * TODO: we do not use +6 dBm option to do not increase power beyond
4149 * regulatory limit, however this could be utilized for devices with
4150 * CAPABILITY_POWER_LIMIT.
8c8d2017 4151 */
87dd2d76
SG		 4152 if (delta <= -12) {
4153 power_ctrl = 2;
4154 delta += 12;
4155 } else if (delta <= -6) {
4156 power_ctrl = 1;
4157 delta += 6;
4158 } else {
4159 power_ctrl = 0;
cee2c731 4160 }
87dd2d76
SG		 4161 rt2800_bbp_read(rt2x00dev, 1, &r1);
4162 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl);
4163 rt2800_bbp_write(rt2x00dev, 1, r1);
8c8d2017 4164
5e846004
HS		 4165 offset = TX_PWR_CFG_0;
4166
4167 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
4168 /* just to be safe */
4169 if (offset > TX_PWR_CFG_4)
4170 break;
4171
4172 rt2800_register_read(rt2x00dev, offset, &reg);
4173
4174 /* read the next four txpower values */
022138ca
GJ		 4175 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4176 i, &eeprom);
5e846004 4177
e90c54b2
RJH		 4178 is_rate_b = i ? 0 : 1;
4179 /*
4180 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
5e846004 4181 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
e90c54b2
RJH		 4182 * TX_PWR_CFG_4: unknown
4183 */
5e846004
HS		 4184 txpower = rt2x00_get_field16(eeprom,
4185 EEPROM_TXPOWER_BYRATE_RATE0);
fa71a160 4186 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4187 power_level, txpower, delta);
e90c54b2 4188 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
5e846004 4189
e90c54b2
RJH		 4190 /*
4191 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
5e846004 4192 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
e90c54b2
RJH		 4193 * TX_PWR_CFG_4: unknown
4194 */
5e846004
HS		 4195 txpower = rt2x00_get_field16(eeprom,
4196 EEPROM_TXPOWER_BYRATE_RATE1);
fa71a160 4197 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4198 power_level, txpower, delta);
e90c54b2 4199 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
5e846004 4200
e90c54b2
RJH		 4201 /*
4202 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
5e846004 4203 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
e90c54b2
RJH		 4204 * TX_PWR_CFG_4: unknown
4205 */
5e846004
HS		 4206 txpower = rt2x00_get_field16(eeprom,
4207 EEPROM_TXPOWER_BYRATE_RATE2);
fa71a160 4208 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4209 power_level, txpower, delta);
e90c54b2 4210 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
5e846004 4211
e90c54b2
RJH		 4212 /*
4213 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
5e846004 4214 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
e90c54b2
RJH		 4215 * TX_PWR_CFG_4: unknown
4216 */
5e846004
HS		 4217 txpower = rt2x00_get_field16(eeprom,
4218 EEPROM_TXPOWER_BYRATE_RATE3);
fa71a160 4219 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4220 power_level, txpower, delta);
e90c54b2 4221 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
5e846004
HS		 4222
4223 /* read the next four txpower values */
022138ca
GJ		 4224 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4225 i + 1, &eeprom);
5e846004 4226
e90c54b2
RJH		 4227 is_rate_b = 0;
4228 /*
4229 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
5e846004 4230 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 4231 * TX_PWR_CFG_4: unknown
4232 */
5e846004
HS		 4233 txpower = rt2x00_get_field16(eeprom,
4234 EEPROM_TXPOWER_BYRATE_RATE0);
fa71a160 4235 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4236 power_level, txpower, delta);
e90c54b2 4237 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
5e846004 4238
e90c54b2
RJH		 4239 /*
4240 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
5e846004 4241 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 4242 * TX_PWR_CFG_4: unknown
4243 */
5e846004
HS		 4244 txpower = rt2x00_get_field16(eeprom,
4245 EEPROM_TXPOWER_BYRATE_RATE1);
fa71a160 4246 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4247 power_level, txpower, delta);
e90c54b2 4248 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
5e846004 4249
e90c54b2
RJH		 4250 /*
4251 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
5e846004 4252 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 4253 * TX_PWR_CFG_4: unknown
4254 */
5e846004
HS		 4255 txpower = rt2x00_get_field16(eeprom,
4256 EEPROM_TXPOWER_BYRATE_RATE2);
fa71a160 4257 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4258 power_level, txpower, delta);
e90c54b2 4259 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
5e846004 4260
e90c54b2
RJH		 4261 /*
4262 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
5e846004 4263 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
e90c54b2
RJH		 4264 * TX_PWR_CFG_4: unknown
4265 */
5e846004
HS		 4266 txpower = rt2x00_get_field16(eeprom,
4267 EEPROM_TXPOWER_BYRATE_RATE3);
fa71a160 4268 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2af242e1 4269 power_level, txpower, delta);
e90c54b2 4270 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
5e846004
HS		 4271
4272 rt2800_register_write(rt2x00dev, offset, reg);
4273
4274 /* next TX_PWR_CFG register */
4275 offset += 4;
4276 }
f4450616
BZ		 4277}
4278
34542ff5
GJ		 4279static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
4280 struct ieee80211_channel *chan,
4281 int power_level)
4282{
4283 if (rt2x00_rt(rt2x00dev, RT3593))
4284 rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level);
4285 else
4286 rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level);
4287}
4288
9e33a355
HS		 4289void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
4290{
675a0b04 4291 rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan,
9e33a355
HS		 4292 rt2x00dev->tx_power);
4293}
4294EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
4295
2e9c43dd
JL		 4296void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
4297{
4298 u32 tx_pin;
4299 u8 rfcsr;
4300
4301 /*
4302 * A voltage-controlled oscillator(VCO) is an electronic oscillator
4303 * designed to be controlled in oscillation frequency by a voltage
4304 * input. Maybe the temperature will affect the frequency of
4305 * oscillation to be shifted. The VCO calibration will be called
4306 * periodically to adjust the frequency to be precision.
4307 */
4308
4309 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
4310 tx_pin &= TX_PIN_CFG_PA_PE_DISABLE;
4311 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
4312
4313 switch (rt2x00dev->chip.rf) {
4314 case RF2020:
4315 case RF3020:
4316 case RF3021:
4317 case RF3022:
4318 case RF3320:
4319 case RF3052:
4320 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
4321 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
4322 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
4323 break;
1095df07 4324 case RF3053:
3b9b74ba 4325 case RF3070:
a89534ed 4326 case RF3290:
ccf91bd6 4327 case RF5360:
ac0372ab 4328 case RF5362:
2e9c43dd
JL		 4329 case RF5370:
4330 case RF5372:
4331 case RF5390:
cff3d1f0 4332 case RF5392:
2e9c43dd 4333 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
d6d82020 4334 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2e9c43dd
JL		 4335 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
4336 break;
4337 default:
4338 return;
4339 }
4340
4341 mdelay(1);
4342
4343 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
4344 if (rt2x00dev->rf_channel <= 14) {
4345 switch (rt2x00dev->default_ant.tx_chain_num) {
4346 case 3:
4347 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1);
4348 /* fall through */
4349 case 2:
4350 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
4351 /* fall through */
4352 case 1:
4353 default:
4354 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
4355 break;
4356 }
4357 } else {
4358 switch (rt2x00dev->default_ant.tx_chain_num) {
4359 case 3:
4360 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1);
4361 /* fall through */
4362 case 2:
4363 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
4364 /* fall through */
4365 case 1:
4366 default:
4367 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
4368 break;
4369 }
4370 }
4371 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
4372
4373}
4374EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
4375
f4450616
BZ		 4376static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
4377 struct rt2x00lib_conf *libconf)
4378{
4379 u32 reg;
4380
4381 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
4382 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
4383 libconf->conf->short_frame_max_tx_count);
4384 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
4385 libconf->conf->long_frame_max_tx_count);
f4450616
BZ		 4386 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
4387}
4388
4389static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
4390 struct rt2x00lib_conf *libconf)
4391{
4392 enum dev_state state =
4393 (libconf->conf->flags & IEEE80211_CONF_PS) ?
4394 STATE_SLEEP : STATE_AWAKE;
4395 u32 reg;
4396
4397 if (state == STATE_SLEEP) {
4398 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
4399
4400 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
4401 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
4402 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
4403 libconf->conf->listen_interval - 1);
4404 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
4405 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
4406
4407 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
4408 } else {
f4450616
BZ		 4409 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
4410 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
4411 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
4412 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
4413 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5731858d
GW		 4414
4415 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
f4450616
BZ		 4416 }
4417}
4418
4419void rt2800_config(struct rt2x00_dev *rt2x00dev,
4420 struct rt2x00lib_conf *libconf,
4421 const unsigned int flags)
4422{
4423 /* Always recalculate LNA gain before changing configuration */
4424 rt2800_config_lna_gain(rt2x00dev, libconf);
4425
e90c54b2 4426 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
f4450616
BZ		 4427 rt2800_config_channel(rt2x00dev, libconf->conf,
4428 &libconf->rf, &libconf->channel);
675a0b04 4429 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
9e33a355 4430 libconf->conf->power_level);
e90c54b2 4431 }
f4450616 4432 if (flags & IEEE80211_CONF_CHANGE_POWER)
675a0b04 4433 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
9e33a355 4434 libconf->conf->power_level);
f4450616
BZ		 4435 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
4436 rt2800_config_retry_limit(rt2x00dev, libconf);
4437 if (flags & IEEE80211_CONF_CHANGE_PS)
4438 rt2800_config_ps(rt2x00dev, libconf);
4439}
4440EXPORT_SYMBOL_GPL(rt2800_config);
4441
4442/*
4443 * Link tuning
4444 */
4445void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
4446{
4447 u32 reg;
4448
4449 /*
4450 * Update FCS error count from register.
4451 */
4452 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
4453 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
4454}
4455EXPORT_SYMBOL_GPL(rt2800_link_stats);
4456
4457static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
4458{
8c6728b0
GW		 4459 u8 vgc;
4460
f4450616 4461 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
d5385bfc 4462 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 4463 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 4464 rt2x00_rt(rt2x00dev, RT3090) ||
a89534ed 4465 rt2x00_rt(rt2x00dev, RT3290) ||
adde5882 4466 rt2x00_rt(rt2x00dev, RT3390) ||
d961e447 4467 rt2x00_rt(rt2x00dev, RT3572) ||
0ffd2a9a 4468 rt2x00_rt(rt2x00dev, RT3593) ||
2ed71884 4469 rt2x00_rt(rt2x00dev, RT5390) ||
3d81535e
SG		 4470 rt2x00_rt(rt2x00dev, RT5392) ||
4471 rt2x00_rt(rt2x00dev, RT5592))
8c6728b0
GW		 4472 vgc = 0x1c + (2 * rt2x00dev->lna_gain);
4473 else
4474 vgc = 0x2e + rt2x00dev->lna_gain;
4475 } else { /* 5GHZ band */
733aec6a 4476 if (rt2x00_rt(rt2x00dev, RT3593))
0ffd2a9a 4477 vgc = 0x20 + (rt2x00dev->lna_gain * 5) / 3;
3d81535e
SG		 4478 else if (rt2x00_rt(rt2x00dev, RT5592))
4479 vgc = 0x24 + (2 * rt2x00dev->lna_gain);
d961e447
GW		 4480 else {
4481 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
4482 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
4483 else
4484 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
4485 }
f4450616
BZ		 4486 }
4487
8c6728b0 4488 return vgc;
f4450616
BZ		 4489}
4490
4491static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
4492 struct link_qual *qual, u8 vgc_level)
4493{
4494 if (qual->vgc_level != vgc_level) {
271f1a4d
GJ		 4495 if (rt2x00_rt(rt2x00dev, RT3572) ||
4496 rt2x00_rt(rt2x00dev, RT3593)) {
4497 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66,
4498 vgc_level);
4499 } else if (rt2x00_rt(rt2x00dev, RT5592)) {
3d81535e
SG		 4500 rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a);
4501 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level);
271f1a4d 4502 } else {
3d81535e 4503 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
271f1a4d
GJ		 4504 }
4505
f4450616
BZ		 4506 qual->vgc_level = vgc_level;
4507 qual->vgc_level_reg = vgc_level;
4508 }
4509}
4510
4511void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
4512{
4513 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
4514}
4515EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
4516
4517void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
4518 const u32 count)
4519{
3d81535e
SG		 4520 u8 vgc;
4521
8d0c9b65 4522 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
f4450616 4523 return;
e25aa82a
GJ		 4524
4525 /* When RSSI is better than a certain threshold, increase VGC
4526 * with a chip specific value in order to improve the balance
4527 * between sensibility and noise isolation.
f4450616 4528 */
3d81535e
SG		 4529
4530 vgc = rt2800_get_default_vgc(rt2x00dev);
4531
e25aa82a
GJ		 4532 switch (rt2x00dev->chip.rt) {
4533 case RT3572:
4534 case RT3593:
4535 if (qual->rssi > -65) {
4536 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ)
4537 vgc += 0x20;
4538 else
4539 vgc += 0x10;
4540 }
4541 break;
4542
4543 case RT5592:
0beb1bbf
GJ		 4544 if (qual->rssi > -65)
4545 vgc += 0x20;
e25aa82a
GJ		 4546 break;
4547
4548 default:
0beb1bbf
GJ		 4549 if (qual->rssi > -80)
4550 vgc += 0x10;
e25aa82a 4551 break;
0beb1bbf 4552 }
3d81535e
SG		 4553
4554 rt2800_set_vgc(rt2x00dev, qual, vgc);
f4450616
BZ		 4555}
4556EXPORT_SYMBOL_GPL(rt2800_link_tuner);
fcf51541
BZ		 4557
4558/*
4559 * Initialization functions.
4560 */
b9a07ae9 4561static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 4562{
4563 u32 reg;
d5385bfc 4564 u16 eeprom;
fcf51541 4565 unsigned int i;
e3a896b9 4566 int ret;
fcf51541 4567
f7b395e9 4568 rt2800_disable_wpdma(rt2x00dev);
a9dce149 4569
e3a896b9
GW		 4570 ret = rt2800_drv_init_registers(rt2x00dev);
4571 if (ret)
4572 return ret;
fcf51541 4573
fcf51541
BZ		 4574 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
4575 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
4576
4577 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
4578
4579 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
8544df32 4580 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
fcf51541
BZ		 4581 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
4582 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
4583 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
4584 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
4585 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
4586 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
4587
a9dce149
GW		 4588 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
4589
4590 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
4591 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
4592 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
4593 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
4594
a89534ed
WH		 4595 if (rt2x00_rt(rt2x00dev, RT3290)) {
4596 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
4597 if (rt2x00_get_field32(reg, WLAN_EN) == 1) {
4598 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 1);
4599 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
4600 }
4601
4602 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
4603 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) {
4604 rt2x00_set_field32(&reg, LDO0_EN, 1);
4605 rt2x00_set_field32(&reg, LDO_BGSEL, 3);
4606 rt2800_register_write(rt2x00dev, CMB_CTRL, reg);
4607 }
4608
4609 rt2800_register_read(rt2x00dev, OSC_CTRL, &reg);
4610 rt2x00_set_field32(&reg, OSC_ROSC_EN, 1);
4611 rt2x00_set_field32(&reg, OSC_CAL_REQ, 1);
4612 rt2x00_set_field32(&reg, OSC_REF_CYCLE, 0x27);
4613 rt2800_register_write(rt2x00dev, OSC_CTRL, reg);
4614
4615 rt2800_register_read(rt2x00dev, COEX_CFG0, &reg);
4616 rt2x00_set_field32(&reg, COEX_CFG_ANT, 0x5e);
4617 rt2800_register_write(rt2x00dev, COEX_CFG0, reg);
4618
4619 rt2800_register_read(rt2x00dev, COEX_CFG2, &reg);
4620 rt2x00_set_field32(&reg, BT_COEX_CFG1, 0x00);
4621 rt2x00_set_field32(&reg, BT_COEX_CFG0, 0x17);
4622 rt2x00_set_field32(&reg, WL_COEX_CFG1, 0x93);
4623 rt2x00_set_field32(&reg, WL_COEX_CFG0, 0x7f);
4624 rt2800_register_write(rt2x00dev, COEX_CFG2, reg);
4625
4626 rt2800_register_read(rt2x00dev, PLL_CTRL, &reg);
4627 rt2x00_set_field32(&reg, PLL_CONTROL, 1);
4628 rt2800_register_write(rt2x00dev, PLL_CTRL, reg);
4629 }
4630
64522957 4631 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904 4632 rt2x00_rt(rt2x00dev, RT3090) ||
a89534ed 4633 rt2x00_rt(rt2x00dev, RT3290) ||
cc78e904 4634 rt2x00_rt(rt2x00dev, RT3390)) {
a89534ed
WH		 4635
4636 if (rt2x00_rt(rt2x00dev, RT3290))
4637 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
4638 0x00000404);
4639 else
4640 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
4641 0x00000400);
4642
fcf51541 4643 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
64522957 4644 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 4645 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
4646 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
3e38d3da
GJ		 4647 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
4648 &eeprom);
38c8a566 4649 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
d5385bfc
GW		 4650 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4651 0x0000002c);
4652 else
4653 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4654 0x0000000f);
4655 } else {
4656 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4657 }
d5385bfc 4658 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
fcf51541 4659 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
8cdd15e0
GW		 4660
4661 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
4662 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4663 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
4664 } else {
4665 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4666 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4667 }
c295a81d
HS		 4668 } else if (rt2800_is_305x_soc(rt2x00dev)) {
4669 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
4670 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
961636ba 4671 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
03839951
DG		 4672 } else if (rt2x00_rt(rt2x00dev, RT3352)) {
4673 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
4674 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4675 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
872834df
GW		 4676 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
4677 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
4678 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1706d15d
GJ		 4679 } else if (rt2x00_rt(rt2x00dev, RT3593)) {
4680 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
4681 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4682 if (rt2x00_rt_rev_lt(rt2x00dev, RT3593, REV_RT3593E)) {
4683 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
4684 &eeprom);
4685 if (rt2x00_get_field16(eeprom,
4686 EEPROM_NIC_CONF1_DAC_TEST))
4687 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4688 0x0000001f);
4689 else
4690 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4691 0x0000000f);
4692 } else {
4693 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4694 0x00000000);
4695 }
2ed71884 4696 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
7641328d
SG		 4697 rt2x00_rt(rt2x00dev, RT5392) ||
4698 rt2x00_rt(rt2x00dev, RT5592)) {
adde5882
GJ		 4699 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
4700 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4701 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
fcf51541
BZ		 4702 } else {
4703 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
4704 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4705 }
4706
4707 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
4708 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
4709 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
4710 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
4711 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
4712 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
4713 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
4714 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
4715 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
4716 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
4717
4718 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
4719 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
a9dce149 4720 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
fcf51541
BZ		 4721 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
4722 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
4723
4724 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
4725 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
8d0c9b65 4726 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
49e721ec 4727 rt2x00_rt(rt2x00dev, RT2883) ||
8d0c9b65 4728 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
fcf51541
BZ		 4729 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
4730 else
4731 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
4732 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
4733 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
4734 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
4735
a9dce149
GW		 4736 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
4737 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
4738 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
4739 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
4740 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
4741 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
4742 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
4743 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
4744 rt2800_register_write(rt2x00dev, LED_CFG, reg);
4745
fcf51541
BZ		 4746 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
4747
a9dce149
GW		 4748 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
4749 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
4750 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
4751 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
4752 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
4753 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
4754 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
4755 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
4756
fcf51541
BZ		 4757 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
4758 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
a9dce149 4759 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
fcf51541
BZ		 4760 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
4761 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
a9dce149 4762 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
fcf51541
BZ		 4763 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
4764 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
4765 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
4766
4767 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
a9dce149 4768 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
fcf51541 4769 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 4770 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 4771 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4772 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4773 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 4774 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 4775 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 4776 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4777 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 4778 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
4779
4780 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
a9dce149 4781 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
fcf51541 4782 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 4783 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 4784 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4785 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4786 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 4787 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 4788 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 4789 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4790 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 4791 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
4792
4793 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
4794 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
4795 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 4796 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 4797 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4798 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4799 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4800 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4801 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4802 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 4803 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 4804 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
4805
4806 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
4807 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
d13a97f0 4808 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 4809 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 4810 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4811 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4812 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4813 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
4814 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4815 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 4816 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 4817 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
4818
4819 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
4820 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
4821 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 4822 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 4823 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4824 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4825 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4826 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4827 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4828 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 4829 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 4830 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
4831
4832 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
4833 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
4834 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
6f492b6d 4835 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
fcf51541
BZ		 4836 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4837 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4838 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4839 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
4840 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4841 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 4842 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 4843 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
4844
cea90e55 4845 if (rt2x00_is_usb(rt2x00dev)) {
fcf51541
BZ		 4846 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
4847
4848 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
4849 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
4850 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
4851 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
4852 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
4853 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
4854 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
4855 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
4856 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
4857 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
4858 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
4859 }
4860
961621ab
HS		 4861 /*
4862 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
4863 * although it is reserved.
4864 */
4865 rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
4866 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
4867 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
4868 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
4869 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
4870 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
4871 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
4872 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
4873 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
4874 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
4875 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
4876 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
4877
7641328d
SG		 4878 reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002;
4879 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg);
fcf51541
BZ		 4880
4881 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
4882 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
4883 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
4884 IEEE80211_MAX_RTS_THRESHOLD);
4885 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
4886 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
4887
4888 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
a9dce149 4889
a21c2ab4
HS		 4890 /*
4891 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
4892 * time should be set to 16. However, the original Ralink driver uses
4893 * 16 for both and indeed using a value of 10 for CCK SIFS results in
4894 * connection problems with 11g + CTS protection. Hence, use the same
4895 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
4896 */
a9dce149 4897 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
a21c2ab4
HS		 4898 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
4899 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
a9dce149
GW		 4900 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
4901 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
4902 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
4903 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
4904
fcf51541
BZ		 4905 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
4906
4907 /*
4908 * ASIC will keep garbage value after boot, clear encryption keys.
4909 */
4910 for (i = 0; i < 4; i++)
4911 rt2800_register_write(rt2x00dev,
4912 SHARED_KEY_MODE_ENTRY(i), 0);
4913
4914 for (i = 0; i < 256; i++) {
d7d259d3
HS		 4915 rt2800_config_wcid(rt2x00dev, NULL, i);
4916 rt2800_delete_wcid_attr(rt2x00dev, i);
fcf51541
BZ		 4917 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
4918 }
4919
4920 /*
4921 * Clear all beacons
fcf51541 4922 */
77f7c0f3
GJ		 4923 for (i = 0; i < 8; i++)
4924 rt2800_clear_beacon_register(rt2x00dev, i);
fcf51541 4925
cea90e55 4926 if (rt2x00_is_usb(rt2x00dev)) {
785c3c06
GW		 4927 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
4928 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
4929 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
c6fcc0e5
RJH		 4930 } else if (rt2x00_is_pcie(rt2x00dev)) {
4931 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
4932 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
4933 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
fcf51541
BZ		 4934 }
4935
4936 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
4937 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
4938 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
4939 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
4940 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
4941 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
4942 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
4943 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
4944 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
4945 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
4946
4947 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
4948 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
4949 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
4950 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
4951 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
4952 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
4953 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
4954 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
4955 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
4956 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
4957
4958 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
4959 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
4960 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
4961 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
4962 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
4963 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
4964 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
4965 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
4966 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
4967 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
4968
4969 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
4970 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
4971 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
4972 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
4973 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
4974 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
4975
47ee3eb1
HS		 4976 /*
4977 * Do not force the BA window size, we use the TXWI to set it
4978 */
4979 rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
4980 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
4981 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
4982 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
4983
fcf51541
BZ		 4984 /*
4985 * We must clear the error counters.
4986 * These registers are cleared on read,
4987 * so we may pass a useless variable to store the value.
4988 */
4989 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
4990 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
4991 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
4992 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
4993 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
4994 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
4995
9f926fb5
HS		 4996 /*
4997 * Setup leadtime for pre tbtt interrupt to 6ms
4998 */
4999 rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
5000 rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
5001 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
5002
977206d7
HS		 5003 /*
5004 * Set up channel statistics timer
5005 */
5006 rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
5007 rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
5008 rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
5009 rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
5010 rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
5011 rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
5012 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
5013
fcf51541
BZ		 5014 return 0;
5015}
fcf51541
BZ		 5016
5017static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
5018{
5019 unsigned int i;
5020 u32 reg;
5021
5022 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
5023 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
5024 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
5025 return 0;
5026
5027 udelay(REGISTER_BUSY_DELAY);
5028 }
5029
ec9c4989 5030 rt2x00_err(rt2x00dev, "BBP/RF register access failed, aborting\n");
fcf51541
BZ		 5031 return -EACCES;
5032}
5033
5034static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
5035{
5036 unsigned int i;
5037 u8 value;
5038
5039 /*
5040 * BBP was enabled after firmware was loaded,
5041 * but we need to reactivate it now.
5042 */
5043 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
5044 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
5045 msleep(1);
5046
5047 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
5048 rt2800_bbp_read(rt2x00dev, 0, &value);
5049 if ((value != 0xff) && (value != 0x00))
5050 return 0;
5051 udelay(REGISTER_BUSY_DELAY);
5052 }
5053
ec9c4989 5054 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
fcf51541
BZ		 5055 return -EACCES;
5056}
5057
a7bbbe5c
SG		 5058static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev)
5059{
5060 u8 value;
5061
5062 rt2800_bbp_read(rt2x00dev, 4, &value);
5063 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
5064 rt2800_bbp_write(rt2x00dev, 4, value);
5065}
5066
c2675487
SG		 5067static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev)
5068{
5069 rt2800_bbp_write(rt2x00dev, 142, 1);
5070 rt2800_bbp_write(rt2x00dev, 143, 57);
5071}
5072
a7bbbe5c
SG		 5073static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev)
5074{
5075 const u8 glrt_table[] = {
5076 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */
5077 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */
5078 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */
5079 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */
5080 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */
5081 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */
5082 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */
5083 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */
5084 0x2E, 0x36, 0x30, 0x6E, /* 208 ~ 211 */
5085 };
5086 int i;
5087
5088 for (i = 0; i < ARRAY_SIZE(glrt_table); i++) {
5089 rt2800_bbp_write(rt2x00dev, 195, 128 + i);
5090 rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]);
5091 }
5092};
5093
624708b8 5094static void rt2800_init_bbp_early(struct rt2x00_dev *rt2x00dev)
a4969d0d
SG		 5095{
5096 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
5097 rt2800_bbp_write(rt2x00dev, 66, 0x38);
5098 rt2800_bbp_write(rt2x00dev, 68, 0x0B);
5099 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5100 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5101 rt2800_bbp_write(rt2x00dev, 73, 0x10);
5102 rt2800_bbp_write(rt2x00dev, 81, 0x37);
5103 rt2800_bbp_write(rt2x00dev, 82, 0x62);
5104 rt2800_bbp_write(rt2x00dev, 83, 0x6A);
5105 rt2800_bbp_write(rt2x00dev, 84, 0x99);
5106 rt2800_bbp_write(rt2x00dev, 86, 0x00);
5107 rt2800_bbp_write(rt2x00dev, 91, 0x04);
5108 rt2800_bbp_write(rt2x00dev, 92, 0x00);
5109 rt2800_bbp_write(rt2x00dev, 103, 0x00);
5110 rt2800_bbp_write(rt2x00dev, 105, 0x05);
5111 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5112}
5113
5df1ff3a
SG		 5114static void rt2800_disable_unused_dac_adc(struct rt2x00_dev *rt2x00dev)
5115{
5116 u16 eeprom;
5117 u8 value;
5118
5119 rt2800_bbp_read(rt2x00dev, 138, &value);
3e38d3da 5120 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5df1ff3a
SG		 5121 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5122 value |= 0x20;
5123 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5124 value &= ~0x02;
5125 rt2800_bbp_write(rt2x00dev, 138, value);
5126}
5127
dae62957
SG		 5128static void rt2800_init_bbp_305x_soc(struct rt2x00_dev *rt2x00dev)
5129{
b2f8e0bd 5130 rt2800_bbp_write(rt2x00dev, 31, 0x08);
e379de12
SG		 5131
5132 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5133 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 5134
5135 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5136 rt2800_bbp_write(rt2x00dev, 73, 0x10);
8d97be38
SG		 5137
5138 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5139
5140 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
5141 rt2800_bbp_write(rt2x00dev, 80, 0x08);
fa1e3424
SG		 5142
5143 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5144
5145 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 5146
5147 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 5148
5149 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 5150
5151 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5152
5153 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 5154
5155 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
49d61118
SG		 5156
5157 rt2800_bbp_write(rt2x00dev, 105, 0x01);
f867085e
SG		 5158
5159 rt2800_bbp_write(rt2x00dev, 106, 0x35);
dae62957
SG		 5160}
5161
39ab3e8b
SG		 5162static void rt2800_init_bbp_28xx(struct rt2x00_dev *rt2x00dev)
5163{
e379de12
SG		 5164 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5165 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 5166
5167 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
5168 rt2800_bbp_write(rt2x00dev, 69, 0x16);
5169 rt2800_bbp_write(rt2x00dev, 73, 0x12);
5170 } else {
5171 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5172 rt2800_bbp_write(rt2x00dev, 73, 0x10);
5173 }
8d97be38
SG		 5174
5175 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5176
5177 rt2800_bbp_write(rt2x00dev, 81, 0x37);
fa1e3424
SG		 5178
5179 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5180
5181 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 5182
5183 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
5184 rt2800_bbp_write(rt2x00dev, 84, 0x19);
5185 else
5186 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 5187
5188 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 5189
5190 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5191
5192 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 5193
5194 rt2800_bbp_write(rt2x00dev, 103, 0x00);
49d61118
SG		 5195
5196 rt2800_bbp_write(rt2x00dev, 105, 0x05);
f867085e
SG		 5197
5198 rt2800_bbp_write(rt2x00dev, 106, 0x35);
39ab3e8b
SG		 5199}
5200
5201static void rt2800_init_bbp_30xx(struct rt2x00_dev *rt2x00dev)
5202{
e379de12
SG		 5203 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5204 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 5205
5206 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5207 rt2800_bbp_write(rt2x00dev, 73, 0x10);
8d97be38
SG		 5208
5209 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5210
5211 rt2800_bbp_write(rt2x00dev, 79, 0x13);
5212 rt2800_bbp_write(rt2x00dev, 80, 0x05);
5213 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 5214
5215 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5216
5217 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 5218
5219 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 5220
5221 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 5222
5223 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5224
5225 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 5226
5227 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
5228 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
5229 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E))
5230 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5231 else
5232 rt2800_bbp_write(rt2x00dev, 103, 0x00);
49d61118
SG		 5233
5234 rt2800_bbp_write(rt2x00dev, 105, 0x05);
f867085e
SG		 5235
5236 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5df1ff3a
SG		 5237
5238 if (rt2x00_rt(rt2x00dev, RT3071) ||
5239 rt2x00_rt(rt2x00dev, RT3090))
5240 rt2800_disable_unused_dac_adc(rt2x00dev);
39ab3e8b
SG		 5241}
5242
5243static void rt2800_init_bbp_3290(struct rt2x00_dev *rt2x00dev)
5244{
6addb24e
SG		 5245 u8 value;
5246
c3223573 5247 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
b2f8e0bd
SG		 5248
5249 rt2800_bbp_write(rt2x00dev, 31, 0x08);
e379de12
SG		 5250
5251 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5252 rt2800_bbp_write(rt2x00dev, 66, 0x38);
59dcabb5
SG		 5253
5254 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
72ffe142
SG		 5255
5256 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5257 rt2800_bbp_write(rt2x00dev, 73, 0x13);
5258 rt2800_bbp_write(rt2x00dev, 75, 0x46);
5259 rt2800_bbp_write(rt2x00dev, 76, 0x28);
5260
5261 rt2800_bbp_write(rt2x00dev, 77, 0x58);
8d97be38
SG		 5262
5263 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5264
5265 rt2800_bbp_write(rt2x00dev, 74, 0x0b);
5266 rt2800_bbp_write(rt2x00dev, 79, 0x18);
5267 rt2800_bbp_write(rt2x00dev, 80, 0x09);
5268 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 5269
5270 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5271
5272 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
3c20a122
SG		 5273
5274 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
aef9f38b
SG		 5275
5276 rt2800_bbp_write(rt2x00dev, 86, 0x38);
7af98742
SG		 5277
5278 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5279
5280 rt2800_bbp_write(rt2x00dev, 92, 0x02);
672d1188
SG		 5281
5282 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
1ad4408a
SG		 5283
5284 rt2800_bbp_write(rt2x00dev, 104, 0x92);
49d61118
SG		 5285
5286 rt2800_bbp_write(rt2x00dev, 105, 0x1c);
f867085e
SG		 5287
5288 rt2800_bbp_write(rt2x00dev, 106, 0x03);
f2b6777c
SG		 5289
5290 rt2800_bbp_write(rt2x00dev, 128, 0x12);
6addb24e
SG		 5291
5292 rt2800_bbp_write(rt2x00dev, 67, 0x24);
5293 rt2800_bbp_write(rt2x00dev, 143, 0x04);
5294 rt2800_bbp_write(rt2x00dev, 142, 0x99);
5295 rt2800_bbp_write(rt2x00dev, 150, 0x30);
5296 rt2800_bbp_write(rt2x00dev, 151, 0x2e);
5297 rt2800_bbp_write(rt2x00dev, 152, 0x20);
5298 rt2800_bbp_write(rt2x00dev, 153, 0x34);
5299 rt2800_bbp_write(rt2x00dev, 154, 0x40);
5300 rt2800_bbp_write(rt2x00dev, 155, 0x3b);
5301 rt2800_bbp_write(rt2x00dev, 253, 0x04);
5302
5303 rt2800_bbp_read(rt2x00dev, 47, &value);
5304 rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1);
5305 rt2800_bbp_write(rt2x00dev, 47, value);
5306
5307 /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
5308 rt2800_bbp_read(rt2x00dev, 3, &value);
5309 rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1);
5310 rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1);
5311 rt2800_bbp_write(rt2x00dev, 3, value);
39ab3e8b
SG		 5312}
5313
5314static void rt2800_init_bbp_3352(struct rt2x00_dev *rt2x00dev)
5315{
29f3a58b
SG		 5316 rt2800_bbp_write(rt2x00dev, 3, 0x00);
5317 rt2800_bbp_write(rt2x00dev, 4, 0x50);
b2f8e0bd
SG		 5318
5319 rt2800_bbp_write(rt2x00dev, 31, 0x08);
3420f797
SG		 5320
5321 rt2800_bbp_write(rt2x00dev, 47, 0x48);
e379de12
SG		 5322
5323 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5324 rt2800_bbp_write(rt2x00dev, 66, 0x38);
59dcabb5
SG		 5325
5326 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
72ffe142
SG		 5327
5328 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5329 rt2800_bbp_write(rt2x00dev, 73, 0x13);
5330 rt2800_bbp_write(rt2x00dev, 75, 0x46);
5331 rt2800_bbp_write(rt2x00dev, 76, 0x28);
5332
5333 rt2800_bbp_write(rt2x00dev, 77, 0x59);
8d97be38
SG		 5334
5335 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5336
5337 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
5338 rt2800_bbp_write(rt2x00dev, 80, 0x08);
5339 rt2800_bbp_write(rt2x00dev, 81, 0x37);
fa1e3424
SG		 5340
5341 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5342
5343 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 5344
5345 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 5346
5347 rt2800_bbp_write(rt2x00dev, 86, 0x38);
9400fa87
SG		 5348
5349 rt2800_bbp_write(rt2x00dev, 88, 0x90);
7af98742
SG		 5350
5351 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5352
5353 rt2800_bbp_write(rt2x00dev, 92, 0x02);
672d1188
SG		 5354
5355 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
1ad4408a
SG		 5356
5357 rt2800_bbp_write(rt2x00dev, 104, 0x92);
49d61118
SG		 5358
5359 rt2800_bbp_write(rt2x00dev, 105, 0x34);
f867085e
SG		 5360
5361 rt2800_bbp_write(rt2x00dev, 106, 0x05);
46b90d32
SG		 5362
5363 rt2800_bbp_write(rt2x00dev, 120, 0x50);
b7feb9ba
SG		 5364
5365 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
c2da5273
SG		 5366
5367 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
5368 /* Set ITxBF timeout to 0x9c40=1000msec */
5369 rt2800_bbp_write(rt2x00dev, 179, 0x02);
5370 rt2800_bbp_write(rt2x00dev, 180, 0x00);
5371 rt2800_bbp_write(rt2x00dev, 182, 0x40);
5372 rt2800_bbp_write(rt2x00dev, 180, 0x01);
5373 rt2800_bbp_write(rt2x00dev, 182, 0x9c);
5374 rt2800_bbp_write(rt2x00dev, 179, 0x00);
5375 /* Reprogram the inband interface to put right values in RXWI */
5376 rt2800_bbp_write(rt2x00dev, 142, 0x04);
5377 rt2800_bbp_write(rt2x00dev, 143, 0x3b);
5378 rt2800_bbp_write(rt2x00dev, 142, 0x06);
5379 rt2800_bbp_write(rt2x00dev, 143, 0xa0);
5380 rt2800_bbp_write(rt2x00dev, 142, 0x07);
5381 rt2800_bbp_write(rt2x00dev, 143, 0xa1);
5382 rt2800_bbp_write(rt2x00dev, 142, 0x08);
5383 rt2800_bbp_write(rt2x00dev, 143, 0xa2);
5384
5385 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
39ab3e8b
SG		 5386}
5387
5388static void rt2800_init_bbp_3390(struct rt2x00_dev *rt2x00dev)
5389{
e379de12
SG		 5390 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5391 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 5392
5393 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5394 rt2800_bbp_write(rt2x00dev, 73, 0x10);
8d97be38
SG		 5395
5396 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5397
5398 rt2800_bbp_write(rt2x00dev, 79, 0x13);
5399 rt2800_bbp_write(rt2x00dev, 80, 0x05);
5400 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 5401
5402 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5403
5404 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 5405
5406 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 5407
5408 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 5409
5410 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5411
5412 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 5413
5414 if (rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E))
5415 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5416 else
5417 rt2800_bbp_write(rt2x00dev, 103, 0x00);
49d61118
SG		 5418
5419 rt2800_bbp_write(rt2x00dev, 105, 0x05);
f867085e
SG		 5420
5421 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5df1ff3a
SG		 5422
5423 rt2800_disable_unused_dac_adc(rt2x00dev);
39ab3e8b
SG		 5424}
5425
5426static void rt2800_init_bbp_3572(struct rt2x00_dev *rt2x00dev)
5427{
b2f8e0bd 5428 rt2800_bbp_write(rt2x00dev, 31, 0x08);
e379de12
SG		 5429
5430 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5431 rt2800_bbp_write(rt2x00dev, 66, 0x38);
72ffe142
SG		 5432
5433 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5434 rt2800_bbp_write(rt2x00dev, 73, 0x10);
8d97be38
SG		 5435
5436 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
43f535e2
SG		 5437
5438 rt2800_bbp_write(rt2x00dev, 79, 0x13);
5439 rt2800_bbp_write(rt2x00dev, 80, 0x05);
5440 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 5441
5442 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5443
5444 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3c20a122
SG		 5445
5446 rt2800_bbp_write(rt2x00dev, 84, 0x99);
aef9f38b
SG		 5447
5448 rt2800_bbp_write(rt2x00dev, 86, 0x00);
7af98742
SG		 5449
5450 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5451
5452 rt2800_bbp_write(rt2x00dev, 92, 0x00);
672d1188
SG		 5453
5454 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
49d61118
SG		 5455
5456 rt2800_bbp_write(rt2x00dev, 105, 0x05);
f867085e
SG		 5457
5458 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5df1ff3a
SG		 5459
5460 rt2800_disable_unused_dac_adc(rt2x00dev);
39ab3e8b
SG		 5461}
5462
b189a181
GJ		 5463static void rt2800_init_bbp_3593(struct rt2x00_dev *rt2x00dev)
5464{
5465 rt2800_init_bbp_early(rt2x00dev);
5466
5467 rt2800_bbp_write(rt2x00dev, 79, 0x13);
5468 rt2800_bbp_write(rt2x00dev, 80, 0x05);
5469 rt2800_bbp_write(rt2x00dev, 81, 0x33);
5470 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
5471
5472 rt2800_bbp_write(rt2x00dev, 84, 0x19);
5473
5474 /* Enable DC filter */
5475 if (rt2x00_rt_rev_gte(rt2x00dev, RT3593, REV_RT3593E))
5476 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5477}
5478
39ab3e8b
SG		 5479static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev)
5480{
32ef8f49
SG		 5481 int ant, div_mode;
5482 u16 eeprom;
5483 u8 value;
5484
c3223573 5485 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
b2f8e0bd
SG		 5486
5487 rt2800_bbp_write(rt2x00dev, 31, 0x08);
e379de12
SG		 5488
5489 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5490 rt2800_bbp_write(rt2x00dev, 66, 0x38);
59dcabb5
SG		 5491
5492 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
72ffe142 5493
58422191 5494 rt2800_bbp_write(rt2x00dev, 69, 0x12);
72ffe142
SG		 5495 rt2800_bbp_write(rt2x00dev, 73, 0x13);
5496 rt2800_bbp_write(rt2x00dev, 75, 0x46);
5497 rt2800_bbp_write(rt2x00dev, 76, 0x28);
5498
5499 rt2800_bbp_write(rt2x00dev, 77, 0x59);
8d97be38 5500
58422191
SG		 5501 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5502
43f535e2
SG		 5503 rt2800_bbp_write(rt2x00dev, 79, 0x13);
5504 rt2800_bbp_write(rt2x00dev, 80, 0x05);
5505 rt2800_bbp_write(rt2x00dev, 81, 0x33);
fa1e3424
SG		 5506
5507 rt2800_bbp_write(rt2x00dev, 82, 0x62);
885f2414
SG		 5508
5509 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
3c20a122
SG		 5510
5511 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
aef9f38b
SG		 5512
5513 rt2800_bbp_write(rt2x00dev, 86, 0x38);
9400fa87
SG		 5514
5515 if (rt2x00_rt(rt2x00dev, RT5392))
5516 rt2800_bbp_write(rt2x00dev, 88, 0x90);
7af98742
SG		 5517
5518 rt2800_bbp_write(rt2x00dev, 91, 0x04);
b4e121d1
SG		 5519
5520 rt2800_bbp_write(rt2x00dev, 92, 0x02);
90fed535
SG		 5521
5522 if (rt2x00_rt(rt2x00dev, RT5392)) {
5523 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
5524 rt2800_bbp_write(rt2x00dev, 98, 0x12);
5525 }
672d1188
SG		 5526
5527 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
1ad4408a
SG		 5528
5529 rt2800_bbp_write(rt2x00dev, 104, 0x92);
49d61118
SG		 5530
5531 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
f867085e
SG		 5532
5533 if (rt2x00_rt(rt2x00dev, RT5390))
5534 rt2800_bbp_write(rt2x00dev, 106, 0x03);
5535 else if (rt2x00_rt(rt2x00dev, RT5392))
5536 rt2800_bbp_write(rt2x00dev, 106, 0x12);
5537 else
5538 WARN_ON(1);
f2b6777c
SG		 5539
5540 rt2800_bbp_write(rt2x00dev, 128, 0x12);
72917140
SG		 5541
5542 if (rt2x00_rt(rt2x00dev, RT5392)) {
5543 rt2800_bbp_write(rt2x00dev, 134, 0xd0);
5544 rt2800_bbp_write(rt2x00dev, 135, 0xf6);
5545 }
5df1ff3a
SG		 5546
5547 rt2800_disable_unused_dac_adc(rt2x00dev);
32ef8f49 5548
3e38d3da 5549 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
32ef8f49
SG		 5550 div_mode = rt2x00_get_field16(eeprom,
5551 EEPROM_NIC_CONF1_ANT_DIVERSITY);
5552 ant = (div_mode == 3) ? 1 : 0;
5553
5554 /* check if this is a Bluetooth combo card */
c429dfef 5555 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
32ef8f49
SG		 5556 u32 reg;
5557
5558 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
5559 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
5560 rt2x00_set_field32(&reg, GPIO_CTRL_DIR6, 0);
5561 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 0);
5562 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 0);
5563 if (ant == 0)
5564 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 1);
5565 else if (ant == 1)
5566 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 1);
5567 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
5568 }
5569
5570 /* This chip has hardware antenna diversity*/
5571 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
5572 rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */
5573 rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */
5574 rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
5575 }
5576
5577 rt2800_bbp_read(rt2x00dev, 152, &value);
5578 if (ant == 0)
5579 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
5580 else
5581 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
5582 rt2800_bbp_write(rt2x00dev, 152, value);
5583
5584 rt2800_init_freq_calibration(rt2x00dev);
39ab3e8b
SG		 5585}
5586
a7bbbe5c
SG		 5587static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev)
5588{
5589 int ant, div_mode;
5590 u16 eeprom;
5591 u8 value;
5592
624708b8 5593 rt2800_init_bbp_early(rt2x00dev);
a4969d0d 5594
a7bbbe5c
SG		 5595 rt2800_bbp_read(rt2x00dev, 105, &value);
5596 rt2x00_set_field8(&value, BBP105_MLD,
5597 rt2x00dev->default_ant.rx_chain_num == 2);
5598 rt2800_bbp_write(rt2x00dev, 105, value);
5599
5600 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5601
5602 rt2800_bbp_write(rt2x00dev, 20, 0x06);
5603 rt2800_bbp_write(rt2x00dev, 31, 0x08);
5604 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
5605 rt2800_bbp_write(rt2x00dev, 68, 0xDD);
5606 rt2800_bbp_write(rt2x00dev, 69, 0x1A);
5607 rt2800_bbp_write(rt2x00dev, 70, 0x05);
5608 rt2800_bbp_write(rt2x00dev, 73, 0x13);
5609 rt2800_bbp_write(rt2x00dev, 74, 0x0F);
5610 rt2800_bbp_write(rt2x00dev, 75, 0x4F);
5611 rt2800_bbp_write(rt2x00dev, 76, 0x28);
5612 rt2800_bbp_write(rt2x00dev, 77, 0x59);
5613 rt2800_bbp_write(rt2x00dev, 84, 0x9A);
5614 rt2800_bbp_write(rt2x00dev, 86, 0x38);
5615 rt2800_bbp_write(rt2x00dev, 88, 0x90);
5616 rt2800_bbp_write(rt2x00dev, 91, 0x04);
5617 rt2800_bbp_write(rt2x00dev, 92, 0x02);
5618 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
5619 rt2800_bbp_write(rt2x00dev, 98, 0x12);
5620 rt2800_bbp_write(rt2x00dev, 103, 0xC0);
5621 rt2800_bbp_write(rt2x00dev, 104, 0x92);
5622 /* FIXME BBP105 owerwrite */
5623 rt2800_bbp_write(rt2x00dev, 105, 0x3C);
5624 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5625 rt2800_bbp_write(rt2x00dev, 128, 0x12);
5626 rt2800_bbp_write(rt2x00dev, 134, 0xD0);
5627 rt2800_bbp_write(rt2x00dev, 135, 0xF6);
5628 rt2800_bbp_write(rt2x00dev, 137, 0x0F);
5629
5630 /* Initialize GLRT (Generalized Likehood Radio Test) */
5631 rt2800_init_bbp_5592_glrt(rt2x00dev);
5632
5633 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5634
3e38d3da 5635 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
a7bbbe5c
SG		 5636 div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY);
5637 ant = (div_mode == 3) ? 1 : 0;
5638 rt2800_bbp_read(rt2x00dev, 152, &value);
5639 if (ant == 0) {
5640 /* Main antenna */
5641 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
5642 } else {
5643 /* Auxiliary antenna */
5644 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
5645 }
5646 rt2800_bbp_write(rt2x00dev, 152, value);
5647
5648 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) {
5649 rt2800_bbp_read(rt2x00dev, 254, &value);
5650 rt2x00_set_field8(&value, BBP254_BIT7, 1);
5651 rt2800_bbp_write(rt2x00dev, 254, value);
5652 }
5653
c2675487
SG		 5654 rt2800_init_freq_calibration(rt2x00dev);
5655
a7bbbe5c 5656 rt2800_bbp_write(rt2x00dev, 84, 0x19);
6e04f253
SG		 5657 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
5658 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
a7bbbe5c
SG		 5659}
5660
a1ef5039 5661static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
fcf51541
BZ		 5662{
5663 unsigned int i;
5664 u16 eeprom;
5665 u8 reg_id;
5666 u8 value;
5667
dae62957
SG		 5668 if (rt2800_is_305x_soc(rt2x00dev))
5669 rt2800_init_bbp_305x_soc(rt2x00dev);
5670
39ab3e8b
SG		 5671 switch (rt2x00dev->chip.rt) {
5672 case RT2860:
5673 case RT2872:
5674 case RT2883:
5675 rt2800_init_bbp_28xx(rt2x00dev);
5676 break;
5677 case RT3070:
5678 case RT3071:
5679 case RT3090:
5680 rt2800_init_bbp_30xx(rt2x00dev);
5681 break;
5682 case RT3290:
5683 rt2800_init_bbp_3290(rt2x00dev);
5684 break;
5685 case RT3352:
5686 rt2800_init_bbp_3352(rt2x00dev);
5687 break;
5688 case RT3390:
5689 rt2800_init_bbp_3390(rt2x00dev);
5690 break;
5691 case RT3572:
5692 rt2800_init_bbp_3572(rt2x00dev);
5693 break;
b189a181
GJ		 5694 case RT3593:
5695 rt2800_init_bbp_3593(rt2x00dev);
5696 return;
39ab3e8b
SG		 5697 case RT5390:
5698 case RT5392:
5699 rt2800_init_bbp_53xx(rt2x00dev);
5700 break;
5701 case RT5592:
a7bbbe5c 5702 rt2800_init_bbp_5592(rt2x00dev);
a1ef5039 5703 return;
a7bbbe5c
SG		 5704 }
5705
fcf51541 5706 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
022138ca
GJ		 5707 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_BBP_START, i,
5708 &eeprom);
fcf51541
BZ		 5709
5710 if (eeprom != 0xffff && eeprom != 0x0000) {
5711 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
5712 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
5713 rt2800_bbp_write(rt2x00dev, reg_id, value);
5714 }
5715 }
fcf51541 5716}
fcf51541 5717
d9517f2f
SG		 5718static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev)
5719{
5720 u32 reg;
5721
5722 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
5723 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
5724 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
5725}
5726
c5b3c350
SG		 5727static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40,
5728 u8 filter_target)
fcf51541
BZ		 5729{
5730 unsigned int i;
5731 u8 bbp;
5732 u8 rfcsr;
5733 u8 passband;
5734 u8 stopband;
5735 u8 overtuned = 0;
c5b3c350 5736 u8 rfcsr24 = (bw40) ? 0x27 : 0x07;
fcf51541
BZ		 5737
5738 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
5739
5740 rt2800_bbp_read(rt2x00dev, 4, &bbp);
5741 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
5742 rt2800_bbp_write(rt2x00dev, 4, bbp);
5743
80d184e6
RJH		 5744 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
5745 rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
5746 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
5747
fcf51541
BZ		 5748 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
5749 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
5750 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
5751
5752 /*
5753 * Set power & frequency of passband test tone
5754 */
5755 rt2800_bbp_write(rt2x00dev, 24, 0);
5756
5757 for (i = 0; i < 100; i++) {
5758 rt2800_bbp_write(rt2x00dev, 25, 0x90);
5759 msleep(1);
5760
5761 rt2800_bbp_read(rt2x00dev, 55, &passband);
5762 if (passband)
5763 break;
5764 }
5765
5766 /*
5767 * Set power & frequency of stopband test tone
5768 */
5769 rt2800_bbp_write(rt2x00dev, 24, 0x06);
5770
5771 for (i = 0; i < 100; i++) {
5772 rt2800_bbp_write(rt2x00dev, 25, 0x90);
5773 msleep(1);
5774
5775 rt2800_bbp_read(rt2x00dev, 55, &stopband);
5776
5777 if ((passband - stopband) <= filter_target) {
5778 rfcsr24++;
5779 overtuned += ((passband - stopband) == filter_target);
5780 } else
5781 break;
5782
5783 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
5784 }
5785
5786 rfcsr24 -= !!overtuned;
5787
5788 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
5789 return rfcsr24;
5790}
5791
ce94ede9
SG		 5792static void rt2800_rf_init_calibration(struct rt2x00_dev *rt2x00dev,
5793 const unsigned int rf_reg)
5794{
5795 u8 rfcsr;
5796
5797 rt2800_rfcsr_read(rt2x00dev, rf_reg, &rfcsr);
5798 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 1);
5799 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
5800 msleep(1);
5801 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 0);
5802 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
5803}
5804
c5b3c350
SG		 5805static void rt2800_rx_filter_calibration(struct rt2x00_dev *rt2x00dev)
5806{
5807 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5808 u8 filter_tgt_bw20;
5809 u8 filter_tgt_bw40;
5810 u8 rfcsr, bbp;
5811
5812 /*
5813 * TODO: sync filter_tgt values with vendor driver
5814 */
5815 if (rt2x00_rt(rt2x00dev, RT3070)) {
5816 filter_tgt_bw20 = 0x16;
5817 filter_tgt_bw40 = 0x19;
5818 } else {
5819 filter_tgt_bw20 = 0x13;
5820 filter_tgt_bw40 = 0x15;
5821 }
5822
5823 drv_data->calibration_bw20 =
5824 rt2800_init_rx_filter(rt2x00dev, false, filter_tgt_bw20);
5825 drv_data->calibration_bw40 =
5826 rt2800_init_rx_filter(rt2x00dev, true, filter_tgt_bw40);
5827
5828 /*
5829 * Save BBP 25 & 26 values for later use in channel switching (for 3052)
5830 */
5831 rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
5832 rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
5833
5834 /*
5835 * Set back to initial state
5836 */
5837 rt2800_bbp_write(rt2x00dev, 24, 0);
5838
5839 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
5840 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
5841 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
5842
5843 /*
5844 * Set BBP back to BW20
5845 */
5846 rt2800_bbp_read(rt2x00dev, 4, &bbp);
5847 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
5848 rt2800_bbp_write(rt2x00dev, 4, bbp);
5849}
5850
da8064c2
SG		 5851static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev)
5852{
5853 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5854 u8 min_gain, rfcsr, bbp;
5855 u16 eeprom;
5856
5857 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
5858
5859 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
5860 if (rt2x00_rt(rt2x00dev, RT3070) ||
5861 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
5862 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
5863 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
c429dfef 5864 if (!rt2x00_has_cap_external_lna_bg(rt2x00dev))
da8064c2
SG		 5865 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
5866 }
5867
5868 min_gain = rt2x00_rt(rt2x00dev, RT3070) ? 1 : 2;
5869 if (drv_data->txmixer_gain_24g >= min_gain) {
5870 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
5871 drv_data->txmixer_gain_24g);
5872 }
5873
5874 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
5875
5876 if (rt2x00_rt(rt2x00dev, RT3090)) {
5877 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
5878 rt2800_bbp_read(rt2x00dev, 138, &bbp);
3e38d3da 5879 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
da8064c2
SG		 5880 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5881 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
5882 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5883 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
5884 rt2800_bbp_write(rt2x00dev, 138, bbp);
5885 }
5886
5887 if (rt2x00_rt(rt2x00dev, RT3070)) {
5888 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
5889 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
5890 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
5891 else
5892 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
5893 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
5894 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
5895 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
5896 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
5897 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
5898 rt2x00_rt(rt2x00dev, RT3090) ||
5899 rt2x00_rt(rt2x00dev, RT3390)) {
5900 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
5901 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
5902 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
5903 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
5904 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
5905 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
5906 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5907
5908 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
5909 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
5910 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
5911
5912 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
5913 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
5914 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
5915
5916 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
5917 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
5918 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
5919 }
5920}
5921
ab7078ac
GJ		 5922static void rt2800_normal_mode_setup_3593(struct rt2x00_dev *rt2x00dev)
5923{
5924 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5925 u8 rfcsr;
5926 u8 tx_gain;
5927
5928 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
5929 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO2_EN, 0);
5930 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
5931
5932 rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
5933 tx_gain = rt2x00_get_field8(drv_data->txmixer_gain_24g,
5934 RFCSR17_TXMIXER_GAIN);
5935 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, tx_gain);
5936 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
5937
5938 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
5939 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
5940 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
5941
5942 rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
5943 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
5944 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
5945
5946 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
5947 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
5948 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
5949 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5950
5951 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
5952 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
5953 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
5954
5955 /* TODO: enable stream mode */
5956}
5957
f7df8fe5
SG		 5958static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev)
5959{
5960 u8 reg;
5961 u16 eeprom;
5962
5963 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
5964 rt2800_bbp_read(rt2x00dev, 138, &reg);
3e38d3da 5965 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
f7df8fe5
SG		 5966 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5967 rt2x00_set_field8(&reg, BBP138_RX_ADC1, 0);
5968 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5969 rt2x00_set_field8(&reg, BBP138_TX_DAC1, 1);
5970 rt2800_bbp_write(rt2x00dev, 138, reg);
5971
5972 rt2800_rfcsr_read(rt2x00dev, 38, &reg);
5973 rt2x00_set_field8(&reg, RFCSR38_RX_LO1_EN, 0);
5974 rt2800_rfcsr_write(rt2x00dev, 38, reg);
5975
5976 rt2800_rfcsr_read(rt2x00dev, 39, &reg);
5977 rt2x00_set_field8(&reg, RFCSR39_RX_LO2_EN, 0);
5978 rt2800_rfcsr_write(rt2x00dev, 39, reg);
5979
5980 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5981
5982 rt2800_rfcsr_read(rt2x00dev, 30, &reg);
5983 rt2x00_set_field8(&reg, RFCSR30_RX_VCM, 2);
5984 rt2800_rfcsr_write(rt2x00dev, 30, reg);
5985}
5986
d5374ef1
SG		 5987static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev)
5988{
ce94ede9
SG		 5989 rt2800_rf_init_calibration(rt2x00dev, 30);
5990
d5374ef1
SG		 5991 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
5992 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
5993 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
5994 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
5995 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
5996 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
5997 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
5998 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
5999 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
6000 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
6001 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
6002 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
6003 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
6004 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
6005 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
6006 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
6007 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
6008 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
6009 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
6010 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
6011 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
6012 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
6013 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
6014 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
6015 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
6016 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
6017 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
6018 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
6019 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
6020 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
6021 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
6022 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
6023}
6024
6025static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev)
6026{
c9a221b2
SG		 6027 u8 rfcsr;
6028 u16 eeprom;
6029 u32 reg;
6030
ce94ede9
SG		 6031 /* XXX vendor driver do this only for 3070 */
6032 rt2800_rf_init_calibration(rt2x00dev, 30);
6033
d5374ef1
SG		 6034 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
6035 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
6036 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
6037 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
6038 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
6039 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
6040 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
6041 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
6042 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
6043 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
6044 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
6045 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
6046 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
6047 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
6048 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
6049 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
6050 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
772eb433 6051 rt2800_rfcsr_write(rt2x00dev, 25, 0x03);
d5374ef1 6052 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
c9a221b2
SG		 6053
6054 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
6055 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6056 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6057 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6058 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6059 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
6060 rt2x00_rt(rt2x00dev, RT3090)) {
6061 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
6062
6063 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
6064 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
6065 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
6066
6067 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6068 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6069 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
6070 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
3e38d3da
GJ		 6071 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
6072 &eeprom);
c9a221b2
SG		 6073 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
6074 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6075 else
6076 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
6077 }
6078 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6079
6080 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
6081 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
6082 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
6083 }
c5b3c350
SG		 6084
6085 rt2800_rx_filter_calibration(rt2x00dev);
5de5a1f4
SG		 6086
6087 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
6088 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
6089 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E))
6090 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
d9517f2f
SG		 6091
6092 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 6093 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 6094}
6095
6096static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev)
6097{
f9cdcbb1
SG		 6098 u8 rfcsr;
6099
ce94ede9
SG		 6100 rt2800_rf_init_calibration(rt2x00dev, 2);
6101
d5374ef1
SG		 6102 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
6103 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6104 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
6105 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
6106 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
6107 rt2800_rfcsr_write(rt2x00dev, 8, 0xf3);
6108 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
6109 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
6110 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
6111 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
6112 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
6113 rt2800_rfcsr_write(rt2x00dev, 18, 0x02);
6114 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6115 rt2800_rfcsr_write(rt2x00dev, 25, 0x83);
6116 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
6117 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
6118 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6119 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6120 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6121 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
6122 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
6123 rt2800_rfcsr_write(rt2x00dev, 34, 0x05);
6124 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6125 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
6126 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
6127 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
6128 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
6129 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
6130 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
6131 rt2800_rfcsr_write(rt2x00dev, 43, 0x7b);
6132 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
6133 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
6134 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
6135 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
6136 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
6137 rt2800_rfcsr_write(rt2x00dev, 49, 0x98);
6138 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
6139 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
6140 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
6141 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
6142 rt2800_rfcsr_write(rt2x00dev, 56, 0x02);
6143 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
6144 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
6145 rt2800_rfcsr_write(rt2x00dev, 59, 0x09);
6146 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
6147 rt2800_rfcsr_write(rt2x00dev, 61, 0xc1);
f9cdcbb1
SG		 6148
6149 rt2800_rfcsr_read(rt2x00dev, 29, &rfcsr);
6150 rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3);
6151 rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
d9517f2f
SG		 6152
6153 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 6154 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 6155}
6156
6157static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev)
6158{
ce94ede9
SG		 6159 rt2800_rf_init_calibration(rt2x00dev, 30);
6160
d5374ef1
SG		 6161 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
6162 rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
6163 rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
6164 rt2800_rfcsr_write(rt2x00dev, 3, 0x18);
6165 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
6166 rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
6167 rt2800_rfcsr_write(rt2x00dev, 6, 0x33);
6168 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6169 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
6170 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
6171 rt2800_rfcsr_write(rt2x00dev, 10, 0xd2);
6172 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
6173 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
6174 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
6175 rt2800_rfcsr_write(rt2x00dev, 14, 0x5a);
6176 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6177 rt2800_rfcsr_write(rt2x00dev, 16, 0x01);
6178 rt2800_rfcsr_write(rt2x00dev, 18, 0x45);
6179 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
6180 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
6181 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
6182 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
6183 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
6184 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
6185 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
6186 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
6187 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
6188 rt2800_rfcsr_write(rt2x00dev, 28, 0x03);
6189 rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
6190 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6191 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6192 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
6193 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
6194 rt2800_rfcsr_write(rt2x00dev, 34, 0x01);
6195 rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
6196 rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
6197 rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
6198 rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
6199 rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
6200 rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
6201 rt2800_rfcsr_write(rt2x00dev, 41, 0x5b);
6202 rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
6203 rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
6204 rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
6205 rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
6206 rt2800_rfcsr_write(rt2x00dev, 46, 0xdd);
6207 rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
6208 rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
6209 rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
6210 rt2800_rfcsr_write(rt2x00dev, 50, 0x2d);
6211 rt2800_rfcsr_write(rt2x00dev, 51, 0x7f);
6212 rt2800_rfcsr_write(rt2x00dev, 52, 0x00);
6213 rt2800_rfcsr_write(rt2x00dev, 53, 0x52);
6214 rt2800_rfcsr_write(rt2x00dev, 54, 0x1b);
6215 rt2800_rfcsr_write(rt2x00dev, 55, 0x7f);
6216 rt2800_rfcsr_write(rt2x00dev, 56, 0x00);
6217 rt2800_rfcsr_write(rt2x00dev, 57, 0x52);
6218 rt2800_rfcsr_write(rt2x00dev, 58, 0x1b);
6219 rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
6220 rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
6221 rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
6222 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
6223 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
c5b3c350
SG		 6224
6225 rt2800_rx_filter_calibration(rt2x00dev);
d9517f2f 6226 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 6227 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 6228}
6229
6230static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev)
6231{
2971e66f
SG		 6232 u32 reg;
6233
ce94ede9
SG		 6234 rt2800_rf_init_calibration(rt2x00dev, 30);
6235
d5374ef1
SG		 6236 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
6237 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
6238 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
6239 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
6240 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
6241 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
6242 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
6243 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
6244 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
6245 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
6246 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
6247 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
6248 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
6249 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
6250 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
6251 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
6252 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
6253 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
6254 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
6255 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
6256 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
6257 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
6258 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
6259 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
6260 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
6261 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
6262 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
6263 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
6264 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
6265 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
6266 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
6267 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
2971e66f
SG		 6268
6269 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
6270 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
6271 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
c5b3c350
SG		 6272
6273 rt2800_rx_filter_calibration(rt2x00dev);
5de5a1f4
SG		 6274
6275 if (rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
6276 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
d9517f2f
SG		 6277
6278 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 6279 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 6280}
6281
6282static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev)
6283{
87d91db9
SG		 6284 u8 rfcsr;
6285 u32 reg;
6286
ce94ede9
SG		 6287 rt2800_rf_init_calibration(rt2x00dev, 30);
6288
d5374ef1
SG		 6289 rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
6290 rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
6291 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
6292 rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
6293 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
6294 rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
6295 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
6296 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
6297 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
6298 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
6299 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
6300 rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
6301 rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
6302 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
6303 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
6304 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
6305 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
6306 rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
6307 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
6308 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
6309 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
6310 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
6311 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
6312 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
6313 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
6314 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
6315 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
6316 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6317 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
6318 rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
6319 rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
87d91db9
SG		 6320
6321 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
6322 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
6323 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
6324
6325 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6326 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6327 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6328 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6329 msleep(1);
6330 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6331 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
6332 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6333 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
c5b3c350
SG		 6334
6335 rt2800_rx_filter_calibration(rt2x00dev);
d9517f2f 6336 rt2800_led_open_drain_enable(rt2x00dev);
da8064c2 6337 rt2800_normal_mode_setup_3xxx(rt2x00dev);
d5374ef1
SG		 6338}
6339
d63f7e8c
GJ		 6340static void rt3593_post_bbp_init(struct rt2x00_dev *rt2x00dev)
6341{
6342 u8 bbp;
6343 bool txbf_enabled = false; /* FIXME */
6344
6345 rt2800_bbp_read(rt2x00dev, 105, &bbp);
6346 if (rt2x00dev->default_ant.rx_chain_num == 1)
6347 rt2x00_set_field8(&bbp, BBP105_MLD, 0);
6348 else
6349 rt2x00_set_field8(&bbp, BBP105_MLD, 1);
6350 rt2800_bbp_write(rt2x00dev, 105, bbp);
6351
6352 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6353
6354 rt2800_bbp_write(rt2x00dev, 92, 0x02);
6355 rt2800_bbp_write(rt2x00dev, 82, 0x82);
6356 rt2800_bbp_write(rt2x00dev, 106, 0x05);
6357 rt2800_bbp_write(rt2x00dev, 104, 0x92);
6358 rt2800_bbp_write(rt2x00dev, 88, 0x90);
6359 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
6360 rt2800_bbp_write(rt2x00dev, 47, 0x48);
6361 rt2800_bbp_write(rt2x00dev, 120, 0x50);
6362
6363 if (txbf_enabled)
6364 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
6365 else
6366 rt2800_bbp_write(rt2x00dev, 163, 0x9d);
6367
6368 /* SNR mapping */
6369 rt2800_bbp_write(rt2x00dev, 142, 6);
6370 rt2800_bbp_write(rt2x00dev, 143, 160);
6371 rt2800_bbp_write(rt2x00dev, 142, 7);
6372 rt2800_bbp_write(rt2x00dev, 143, 161);
6373 rt2800_bbp_write(rt2x00dev, 142, 8);
6374 rt2800_bbp_write(rt2x00dev, 143, 162);
6375
6376 /* ADC/DAC control */
6377 rt2800_bbp_write(rt2x00dev, 31, 0x08);
6378
6379 /* RX AGC energy lower bound in log2 */
6380 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
6381
6382 /* FIXME: BBP 105 owerwrite? */
6383 rt2800_bbp_write(rt2x00dev, 105, 0x04);
f42b0465 6384
d63f7e8c
GJ		 6385}
6386
ab7078ac
GJ		 6387static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev)
6388{
6389 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
6390 u32 reg;
6391 u8 rfcsr;
6392
6393 /* Disable GPIO #4 and #7 function for LAN PE control */
6394 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
6395 rt2x00_set_field32(&reg, GPIO_SWITCH_4, 0);
6396 rt2x00_set_field32(&reg, GPIO_SWITCH_7, 0);
6397 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
6398
6399 /* Initialize default register values */
6400 rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
6401 rt2800_rfcsr_write(rt2x00dev, 3, 0x80);
6402 rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
6403 rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
6404 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
6405 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
6406 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
6407 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
6408 rt2800_rfcsr_write(rt2x00dev, 12, 0x4e);
6409 rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
6410 rt2800_rfcsr_write(rt2x00dev, 18, 0x40);
6411 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6412 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6413 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6414 rt2800_rfcsr_write(rt2x00dev, 32, 0x78);
6415 rt2800_rfcsr_write(rt2x00dev, 33, 0x3b);
6416 rt2800_rfcsr_write(rt2x00dev, 34, 0x3c);
6417 rt2800_rfcsr_write(rt2x00dev, 35, 0xe0);
6418 rt2800_rfcsr_write(rt2x00dev, 38, 0x86);
6419 rt2800_rfcsr_write(rt2x00dev, 39, 0x23);
6420 rt2800_rfcsr_write(rt2x00dev, 44, 0xd3);
6421 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
6422 rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
6423 rt2800_rfcsr_write(rt2x00dev, 49, 0x8e);
6424 rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
6425 rt2800_rfcsr_write(rt2x00dev, 51, 0x75);
6426 rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
6427 rt2800_rfcsr_write(rt2x00dev, 53, 0x18);
6428 rt2800_rfcsr_write(rt2x00dev, 54, 0x18);
6429 rt2800_rfcsr_write(rt2x00dev, 55, 0x18);
6430 rt2800_rfcsr_write(rt2x00dev, 56, 0xdb);
6431 rt2800_rfcsr_write(rt2x00dev, 57, 0x6e);
6432
6433 /* Initiate calibration */
6434 /* TODO: use rt2800_rf_init_calibration ? */
6435 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
6436 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
6437 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
6438
6439 rt2800_adjust_freq_offset(rt2x00dev);
6440
6441 rt2800_rfcsr_read(rt2x00dev, 18, &rfcsr);
6442 rt2x00_set_field8(&rfcsr, RFCSR18_XO_TUNE_BYPASS, 1);
6443 rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
6444
6445 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6446 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6447 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6448 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6449 usleep_range(1000, 1500);
6450 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6451 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
6452 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6453
6454 /* Set initial values for RX filter calibration */
6455 drv_data->calibration_bw20 = 0x1f;
6456 drv_data->calibration_bw40 = 0x2f;
6457
6458 /* Save BBP 25 & 26 values for later use in channel switching */
6459 rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
6460 rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
6461
6462 rt2800_led_open_drain_enable(rt2x00dev);
6463 rt2800_normal_mode_setup_3593(rt2x00dev);
6464
d63f7e8c 6465 rt3593_post_bbp_init(rt2x00dev);
ab7078ac
GJ		 6466
6467 /* TODO: enable stream mode support */
6468}
6469
d5374ef1
SG		 6470static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
6471{
ce94ede9
SG		 6472 rt2800_rf_init_calibration(rt2x00dev, 2);
6473
d5374ef1
SG		 6474 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
6475 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6476 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
6477 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
6478 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6479 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
6480 else
6481 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
6482 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6483 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
6484 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
c8520bcb 6485 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
d5374ef1
SG		 6486 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
6487 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
6488 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6489 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
6490 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
6491 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
6492
6493 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
6494 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
6495 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6496 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
6497 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
c8520bcb
KL		 6498 if (rt2x00_is_usb(rt2x00dev) &&
6499 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
d5374ef1
SG		 6500 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
6501 else
6502 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
6503 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
6504 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
6505 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6506 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6507
7122e660 6508 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
d5374ef1
SG		 6509 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6510 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
6511 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
6512 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
6513 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6514 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
6515 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
6516 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
6517 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
6518
c8520bcb 6519 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
d5374ef1
SG		 6520 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
6521 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
6522 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
6523 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
6524 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
6525 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6526 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
6527 else
6528 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
6529 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
6530 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
6531 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
6532
6533 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
6534 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6535 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
6536 else
6537 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
6538 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
6539 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
c8520bcb
KL		 6540 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6541 rt2800_rfcsr_write(rt2x00dev, 56, 0x42);
6542 else
6543 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
d5374ef1
SG		 6544 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
6545 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
7122e660 6546 rt2800_rfcsr_write(rt2x00dev, 59, 0x8f);
d5374ef1
SG		 6547
6548 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
c8520bcb
KL		 6549 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
6550 if (rt2x00_is_usb(rt2x00dev))
6551 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
6552 else
6553 rt2800_rfcsr_write(rt2x00dev, 61, 0xd5);
6554 } else {
6555 if (rt2x00_is_usb(rt2x00dev))
6556 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
6557 else
6558 rt2800_rfcsr_write(rt2x00dev, 61, 0xb5);
6559 }
d5374ef1
SG		 6560 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
6561 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
f7df8fe5
SG		 6562
6563 rt2800_normal_mode_setup_5xxx(rt2x00dev);
d9517f2f
SG		 6564
6565 rt2800_led_open_drain_enable(rt2x00dev);
d5374ef1
SG		 6566}
6567
6568static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev)
6569{
ce94ede9
SG		 6570 rt2800_rf_init_calibration(rt2x00dev, 2);
6571
d5374ef1 6572 rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
d5374ef1
SG		 6573 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
6574 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
6575 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
6576 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6577 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
6578 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
6579 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
6580 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
6581 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
6582 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6583 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
6584 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
6585 rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
6586 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
6587 rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
6588 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6589 rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
6590 rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
6591 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
6592 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
6593 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
6594 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6595 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6596 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6597 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6598 rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
6599 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
6600 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
6601 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6602 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
6603 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
6604 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
6605 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
6606 rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
6607 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
6608 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
6609 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
6610 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
6611 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
6612 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
6613 rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
6614 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
6615 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
6616 rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
6617 rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
6618 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
6619 rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
6620 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
6621 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
6622 rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
6623 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
6624 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
6625 rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
6626 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
6627 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
6628 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
6629 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
f7df8fe5
SG		 6630
6631 rt2800_normal_mode_setup_5xxx(rt2x00dev);
d9517f2f
SG		 6632
6633 rt2800_led_open_drain_enable(rt2x00dev);
d5374ef1
SG		 6634}
6635
0c9e5fb9
SG		 6636static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev)
6637{
ce94ede9
SG		 6638 rt2800_rf_init_calibration(rt2x00dev, 30);
6639
0c9e5fb9
SG		 6640 rt2800_rfcsr_write(rt2x00dev, 1, 0x3F);
6641 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
0c9e5fb9
SG		 6642 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
6643 rt2800_rfcsr_write(rt2x00dev, 6, 0xE4);
6644 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6645 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
6646 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6647 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
6648 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
6649 rt2800_rfcsr_write(rt2x00dev, 19, 0x4D);
6650 rt2800_rfcsr_write(rt2x00dev, 20, 0x10);
6651 rt2800_rfcsr_write(rt2x00dev, 21, 0x8D);
6652 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
6653 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6654 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6655 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
6656 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
6657 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6658 rt2800_rfcsr_write(rt2x00dev, 47, 0x0C);
6659 rt2800_rfcsr_write(rt2x00dev, 53, 0x22);
6660 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
6661
6662 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6663 msleep(1);
6664
6665 rt2800_adjust_freq_offset(rt2x00dev);
c630ccf1 6666
c630ccf1
SG		 6667 /* Enable DC filter */
6668 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
6669 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6670
f7df8fe5 6671 rt2800_normal_mode_setup_5xxx(rt2x00dev);
5de5a1f4
SG		 6672
6673 if (rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C))
6674 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
d9517f2f
SG		 6675
6676 rt2800_led_open_drain_enable(rt2x00dev);
0c9e5fb9
SG		 6677}
6678
074f2529 6679static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
fcf51541 6680{
d5374ef1
SG		 6681 if (rt2800_is_305x_soc(rt2x00dev)) {
6682 rt2800_init_rfcsr_305x_soc(rt2x00dev);
074f2529 6683 return;
d5374ef1
SG		 6684 }
6685
6686 switch (rt2x00dev->chip.rt) {
6687 case RT3070:
6688 case RT3071:
6689 case RT3090:
6690 rt2800_init_rfcsr_30xx(rt2x00dev);
6691 break;
6692 case RT3290:
6693 rt2800_init_rfcsr_3290(rt2x00dev);
6694 break;
6695 case RT3352:
6696 rt2800_init_rfcsr_3352(rt2x00dev);
6697 break;
6698 case RT3390:
6699 rt2800_init_rfcsr_3390(rt2x00dev);
6700 break;
6701 case RT3572:
6702 rt2800_init_rfcsr_3572(rt2x00dev);
6703 break;
ab7078ac
GJ		 6704 case RT3593:
6705 rt2800_init_rfcsr_3593(rt2x00dev);
6706 break;
d5374ef1
SG		 6707 case RT5390:
6708 rt2800_init_rfcsr_5390(rt2x00dev);
6709 break;
6710 case RT5392:
6711 rt2800_init_rfcsr_5392(rt2x00dev);
6712 break;
0c9e5fb9
SG		 6713 case RT5592:
6714 rt2800_init_rfcsr_5592(rt2x00dev);
074f2529 6715 break;
8cdd15e0 6716 }
fcf51541 6717}
b9a07ae9
ID		 6718
6719int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
6720{
6721 u32 reg;
6722 u16 word;
6723
6724 /*
61edc7fa 6725 * Initialize MAC registers.
b9a07ae9
ID		 6726 */
6727 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
c630ccf1 6728 rt2800_init_registers(rt2x00dev)))
b9a07ae9
ID		 6729 return -EIO;
6730
61edc7fa
SG		 6731 /*
6732 * Wait BBP/RF to wake up.
6733 */
f4e1a4d3
SG		 6734 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev)))
6735 return -EIO;
6736
b9a07ae9 6737 /*
61edc7fa 6738 * Send signal during boot time to initialize firmware.
b9a07ae9 6739 */
c630ccf1
SG		 6740 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
6741 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
f4e1a4d3 6742 if (rt2x00_is_usb(rt2x00dev))
c630ccf1 6743 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
f4e1a4d3 6744 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
c630ccf1
SG		 6745 msleep(1);
6746
61edc7fa
SG		 6747 /*
6748 * Make sure BBP is up and running.
6749 */
f4e1a4d3 6750 if (unlikely(rt2800_wait_bbp_ready(rt2x00dev)))
c630ccf1 6751 return -EIO;
b9a07ae9 6752
61edc7fa
SG		 6753 /*
6754 * Initialize BBP/RF registers.
6755 */
a1ef5039 6756 rt2800_init_bbp(rt2x00dev);
074f2529
SG		 6757 rt2800_init_rfcsr(rt2x00dev);
6758
b9a07ae9
ID		 6759 if (rt2x00_is_usb(rt2x00dev) &&
6760 (rt2x00_rt(rt2x00dev, RT3070) ||
6761 rt2x00_rt(rt2x00dev, RT3071) ||
6762 rt2x00_rt(rt2x00dev, RT3572))) {
6763 udelay(200);
6764 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
6765 udelay(10);
6766 }
6767
6768 /*
6769 * Enable RX.
6770 */
6771 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
6772 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
6773 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
6774 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
6775
6776 udelay(50);
6777
6778 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
6779 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
6780 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
6781 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
6782 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
6783 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
6784
6785 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
6786 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
6787 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
6788 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
6789
6790 /*
6791 * Initialize LED control
6792 */
3e38d3da 6793 rt2800_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
38c8a566 6794 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
b9a07ae9
ID		 6795 word & 0xff, (word >> 8) & 0xff);
6796
3e38d3da 6797 rt2800_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
38c8a566 6798 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
b9a07ae9
ID		 6799 word & 0xff, (word >> 8) & 0xff);
6800
3e38d3da 6801 rt2800_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
38c8a566 6802 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
b9a07ae9
ID		 6803 word & 0xff, (word >> 8) & 0xff);
6804
6805 return 0;
6806}
6807EXPORT_SYMBOL_GPL(rt2800_enable_radio);
6808
6809void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
6810{
6811 u32 reg;
6812
f7b395e9 6813 rt2800_disable_wpdma(rt2x00dev);
b9a07ae9
ID		 6814
6815 /* Wait for DMA, ignore error */
6816 rt2800_wait_wpdma_ready(rt2x00dev);
6817
6818 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
6819 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
6820 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
6821 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
b9a07ae9
ID		 6822}
6823EXPORT_SYMBOL_GPL(rt2800_disable_radio);
2ce33995 6824
30e84034
BZ		 6825int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
6826{
6827 u32 reg;
a89534ed 6828 u16 efuse_ctrl_reg;
30e84034 6829
a89534ed
WH		 6830 if (rt2x00_rt(rt2x00dev, RT3290))
6831 efuse_ctrl_reg = EFUSE_CTRL_3290;
6832 else
6833 efuse_ctrl_reg = EFUSE_CTRL;
30e84034 6834
a89534ed 6835 rt2800_register_read(rt2x00dev, efuse_ctrl_reg, &reg);
30e84034
BZ		 6836 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
6837}
6838EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
6839
6840static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
6841{
6842 u32 reg;
a89534ed
WH		 6843 u16 efuse_ctrl_reg;
6844 u16 efuse_data0_reg;
6845 u16 efuse_data1_reg;
6846 u16 efuse_data2_reg;
6847 u16 efuse_data3_reg;
6848
6849 if (rt2x00_rt(rt2x00dev, RT3290)) {
6850 efuse_ctrl_reg = EFUSE_CTRL_3290;
6851 efuse_data0_reg = EFUSE_DATA0_3290;
6852 efuse_data1_reg = EFUSE_DATA1_3290;
6853 efuse_data2_reg = EFUSE_DATA2_3290;
6854 efuse_data3_reg = EFUSE_DATA3_3290;
6855 } else {
6856 efuse_ctrl_reg = EFUSE_CTRL;
6857 efuse_data0_reg = EFUSE_DATA0;
6858 efuse_data1_reg = EFUSE_DATA1;
6859 efuse_data2_reg = EFUSE_DATA2;
6860 efuse_data3_reg = EFUSE_DATA3;
6861 }
31a4cf1f
GW		 6862 mutex_lock(&rt2x00dev->csr_mutex);
6863
a89534ed 6864 rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg, &reg);
30e84034
BZ		 6865 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
6866 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
6867 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
a89534ed 6868 rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg);
30e84034
BZ		 6869
6870 /* Wait until the EEPROM has been loaded */
a89534ed 6871 rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, &reg);
30e84034 6872 /* Apparently the data is read from end to start */
a89534ed 6873 rt2800_register_read_lock(rt2x00dev, efuse_data3_reg, &reg);
daabead1 6874 /* The returned value is in CPU order, but eeprom is le */
68fa64ef 6875 *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
a89534ed 6876 rt2800_register_read_lock(rt2x00dev, efuse_data2_reg, &reg);
daabead1 6877 *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
a89534ed 6878 rt2800_register_read_lock(rt2x00dev, efuse_data1_reg, &reg);
daabead1 6879 *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
a89534ed 6880 rt2800_register_read_lock(rt2x00dev, efuse_data0_reg, &reg);
daabead1 6881 *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
31a4cf1f
GW		 6882
6883 mutex_unlock(&rt2x00dev->csr_mutex);
30e84034
BZ		 6884}
6885
a02308e9 6886int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
30e84034
BZ		 6887{
6888 unsigned int i;
6889
6890 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
6891 rt2800_efuse_read(rt2x00dev, i);
a02308e9
GJ		 6892
6893 return 0;
30e84034
BZ		 6894}
6895EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
6896
a3f1625d
GJ		 6897static u8 rt2800_get_txmixer_gain_24g(struct rt2x00_dev *rt2x00dev)
6898{
6899 u16 word;
6900
6316c786
GJ		 6901 if (rt2x00_rt(rt2x00dev, RT3593))
6902 return 0;
6903
a3f1625d
GJ		 6904 rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &word);
6905 if ((word & 0x00ff) != 0x00ff)
6906 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
6907
6908 return 0;
6909}
6910
6911static u8 rt2800_get_txmixer_gain_5g(struct rt2x00_dev *rt2x00dev)
6912{
6913 u16 word;
6914
6316c786
GJ		 6915 if (rt2x00_rt(rt2x00dev, RT3593))
6916 return 0;
6917
a3f1625d
GJ		 6918 rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A, &word);
6919 if ((word & 0x00ff) != 0x00ff)
6920 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
6921
6922 return 0;
6923}
6924
ad417a53 6925static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
38bd7b8a 6926{
77c06c2c 6927 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
38bd7b8a
BZ		 6928 u16 word;
6929 u8 *mac;
6930 u8 default_lna_gain;
a02308e9 6931 int retval;
38bd7b8a 6932
ad417a53
GW		 6933 /*
6934 * Read the EEPROM.
6935 */
a02308e9
GJ		 6936 retval = rt2800_read_eeprom(rt2x00dev);
6937 if (retval)
6938 return retval;
ad417a53 6939
38bd7b8a
BZ		 6940 /*
6941 * Start validation of the data that has been read.
6942 */
3e38d3da 6943 mac = rt2800_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
38bd7b8a 6944 if (!is_valid_ether_addr(mac)) {
f4f7f414 6945 eth_random_addr(mac);
ec9c4989 6946 rt2x00_eeprom_dbg(rt2x00dev, "MAC: %pM\n", mac);
38bd7b8a
BZ		 6947 }
6948
3e38d3da 6949 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
38bd7b8a 6950 if (word == 0xffff) {
38c8a566
RJH		 6951 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
6952 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
6953 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
3e38d3da 6954 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
ec9c4989 6955 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
49e721ec 6956 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
e148b4c8 6957 rt2x00_rt(rt2x00dev, RT2872)) {
38bd7b8a
BZ		 6958 /*
6959 * There is a max of 2 RX streams for RT28x0 series
6960 */
38c8a566
RJH		 6961 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
6962 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
3e38d3da 6963 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
38bd7b8a
BZ		 6964 }
6965
3e38d3da 6966 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
38bd7b8a 6967 if (word == 0xffff) {
38c8a566
RJH		 6968 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
6969 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
6970 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
6971 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
6972 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
6973 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
6974 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
6975 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
6976 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
6977 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
6978 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
6979 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
6980 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
6981 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
6982 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
3e38d3da 6983 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
ec9c4989 6984 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
38bd7b8a
BZ		 6985 }
6986
3e38d3da 6987 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
38bd7b8a
BZ		 6988 if ((word & 0x00ff) == 0x00ff) {
6989 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
3e38d3da 6990 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
ec9c4989 6991 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word);
ec2d1791
GW		 6992 }
6993 if ((word & 0xff00) == 0xff00) {
38bd7b8a
BZ		 6994 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
6995 LED_MODE_TXRX_ACTIVITY);
6996 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
3e38d3da
GJ		 6997 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
6998 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
6999 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
7000 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
ec9c4989 7001 rt2x00_eeprom_dbg(rt2x00dev, "Led Mode: 0x%04x\n", word);
38bd7b8a
BZ		 7002 }
7003
7004 /*
7005 * During the LNA validation we are going to use
7006 * lna0 as correct value. Note that EEPROM_LNA
7007 * is never validated.
7008 */
3e38d3da 7009 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
38bd7b8a
BZ		 7010 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
7011
3e38d3da 7012 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
38bd7b8a
BZ		 7013 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
7014 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
7015 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
7016 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
3e38d3da 7017 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
38bd7b8a 7018
a3f1625d 7019 drv_data->txmixer_gain_24g = rt2800_get_txmixer_gain_24g(rt2x00dev);
77c06c2c 7020
3e38d3da 7021 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
38bd7b8a
BZ		 7022 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
7023 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
f36bb0ca
GJ		 7024 if (!rt2x00_rt(rt2x00dev, RT3593)) {
7025 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
7026 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
7027 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
7028 default_lna_gain);
7029 }
3e38d3da 7030 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
38bd7b8a 7031
a3f1625d 7032 drv_data->txmixer_gain_5g = rt2800_get_txmixer_gain_5g(rt2x00dev);
77c06c2c 7033
3e38d3da 7034 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
38bd7b8a
BZ		 7035 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
7036 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
7037 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
7038 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
3e38d3da 7039 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
38bd7b8a 7040
3e38d3da 7041 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
38bd7b8a
BZ		 7042 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
7043 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
f36bb0ca
GJ		 7044 if (!rt2x00_rt(rt2x00dev, RT3593)) {
7045 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
7046 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
7047 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
7048 default_lna_gain);
7049 }
3e38d3da 7050 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
38bd7b8a 7051
f36bb0ca
GJ		 7052 if (rt2x00_rt(rt2x00dev, RT3593)) {
7053 rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &word);
7054 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0x00 ||
7055 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0xff)
7056 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
7057 default_lna_gain);
7058 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0x00 ||
7059 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0xff)
7060 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
7061 default_lna_gain);
7062 rt2800_eeprom_write(rt2x00dev, EEPROM_EXT_LNA2, word);
7063 }
7064
38bd7b8a
BZ		 7065 return 0;
7066}
38bd7b8a 7067
ad417a53 7068static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
38bd7b8a 7069{
38bd7b8a
BZ		 7070 u16 value;
7071 u16 eeprom;
86868b26 7072 u16 rf;
38bd7b8a 7073
86868b26
GJ		 7074 /*
7075 * Read EEPROM word for configuration.
7076 */
3e38d3da 7077 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
86868b26
GJ		 7078
7079 /*
7080 * Identify RF chipset by EEPROM value
7081 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
7082 * RT53xx: defined in "EEPROM_CHIP_ID" field
7083 */
7084 if (rt2x00_rt(rt2x00dev, RT3290) ||
7085 rt2x00_rt(rt2x00dev, RT5390) ||
7086 rt2x00_rt(rt2x00dev, RT5392))
3e38d3da 7087 rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &rf);
86868b26
GJ		 7088 else
7089 rf = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
7090
7091 switch (rf) {
d331eb51
LF		 7092 case RF2820:
7093 case RF2850:
7094 case RF2720:
7095 case RF2750:
7096 case RF3020:
7097 case RF2020:
7098 case RF3021:
7099 case RF3022:
7100 case RF3052:
0f5af26a 7101 case RF3053:
3b9b74ba 7102 case RF3070:
a89534ed 7103 case RF3290:
d331eb51 7104 case RF3320:
03839951 7105 case RF3322:
ccf91bd6 7106 case RF5360:
ac0372ab 7107 case RF5362:
d331eb51 7108 case RF5370:
2ed71884 7109 case RF5372:
d331eb51 7110 case RF5390:
cff3d1f0 7111 case RF5392:
b8863f8b 7112 case RF5592:
d331eb51
LF		 7113 break;
7114 default:
ec9c4989
JP		 7115 rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n",
7116 rf);
38bd7b8a
BZ		 7117 return -ENODEV;
7118 }
7119
86868b26
GJ		 7120 rt2x00_set_rf(rt2x00dev, rf);
7121
38bd7b8a
BZ		 7122 /*
7123 * Identify default antenna configuration.
7124 */
d96aa640 7125 rt2x00dev->default_ant.tx_chain_num =
38c8a566 7126 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
d96aa640 7127 rt2x00dev->default_ant.rx_chain_num =
38c8a566 7128 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
38bd7b8a 7129
3e38d3da 7130 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
d96aa640
RJH		 7131
7132 if (rt2x00_rt(rt2x00dev, RT3070) ||
7133 rt2x00_rt(rt2x00dev, RT3090) ||
03839951 7134 rt2x00_rt(rt2x00dev, RT3352) ||
d96aa640
RJH		 7135 rt2x00_rt(rt2x00dev, RT3390)) {
7136 value = rt2x00_get_field16(eeprom,
7137 EEPROM_NIC_CONF1_ANT_DIVERSITY);
7138 switch (value) {
7139 case 0:
7140 case 1:
7141 case 2:
7142 rt2x00dev->default_ant.tx = ANTENNA_A;
7143 rt2x00dev->default_ant.rx = ANTENNA_A;
7144 break;
7145 case 3:
7146 rt2x00dev->default_ant.tx = ANTENNA_A;
7147 rt2x00dev->default_ant.rx = ANTENNA_B;
7148 break;
7149 }
7150 } else {
7151 rt2x00dev->default_ant.tx = ANTENNA_A;
7152 rt2x00dev->default_ant.rx = ANTENNA_A;
7153 }
7154
0586a11b
AA		 7155 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
7156 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */
7157 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */
7158 }
7159
38bd7b8a 7160 /*
9328fdac 7161 * Determine external LNA informations.
38bd7b8a 7162 */
38c8a566 7163 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
7dab73b3 7164 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
38c8a566 7165 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
7dab73b3 7166 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
38bd7b8a
BZ		 7167
7168 /*
7169 * Detect if this device has an hardware controlled radio.
7170 */
38c8a566 7171 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
7dab73b3 7172 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
38bd7b8a 7173
fdbc7b0a
GW		 7174 /*
7175 * Detect if this device has Bluetooth co-existence.
7176 */
7177 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
7178 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
7179
9328fdac
GW		 7180 /*
7181 * Read frequency offset and RF programming sequence.
7182 */
3e38d3da 7183 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
9328fdac
GW		 7184 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
7185
38bd7b8a
BZ		 7186 /*
7187 * Store led settings, for correct led behaviour.
7188 */
7189#ifdef CONFIG_RT2X00_LIB_LEDS
7190 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
7191 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
7192 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
7193
9328fdac 7194 rt2x00dev->led_mcu_reg = eeprom;
38bd7b8a
BZ		 7195#endif /* CONFIG_RT2X00_LIB_LEDS */
7196
e90c54b2
RJH		 7197 /*
7198 * Check if support EIRP tx power limit feature.
7199 */
3e38d3da 7200 rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
e90c54b2
RJH		 7201
7202 if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
7203 EIRP_MAX_TX_POWER_LIMIT)
7dab73b3 7204 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
e90c54b2 7205
38bd7b8a
BZ		 7206 return 0;
7207}
38bd7b8a 7208
4da2933f 7209/*
55f9321a 7210 * RF value list for rt28xx
4da2933f
BZ		 7211 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
7212 */
7213static const struct rf_channel rf_vals[] = {
7214 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
7215 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
7216 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
7217 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
7218 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
7219 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
7220 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
7221 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
7222 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
7223 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
7224 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
7225 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
7226 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
7227 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
7228
7229 /* 802.11 UNI / HyperLan 2 */
7230 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
7231 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
7232 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
7233 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
7234 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
7235 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
7236 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
7237 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
7238 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
7239 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
7240 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
7241 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
7242
7243 /* 802.11 HyperLan 2 */
7244 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
7245 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
7246 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
7247 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
7248 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
7249 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
7250 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
7251 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
7252 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
7253 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
7254 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
7255 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
7256 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
7257 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
7258 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
7259 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
7260
7261 /* 802.11 UNII */
7262 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
7263 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
7264 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
7265 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
7266 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
7267 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
7268 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
7269 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
7270 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
7271 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
7272 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
7273
7274 /* 802.11 Japan */
7275 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
7276 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
7277 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
7278 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
7279 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
7280 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
7281 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
7282};
7283
7284/*
55f9321a 7285 * RF value list for rt3xxx
b6b561c3 7286 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052 & RF3053)
4da2933f 7287 */
55f9321a 7288static const struct rf_channel rf_vals_3x[] = {
4da2933f
BZ		 7289 {1, 241, 2, 2 },
7290 {2, 241, 2, 7 },
7291 {3, 242, 2, 2 },
7292 {4, 242, 2, 7 },
7293 {5, 243, 2, 2 },
7294 {6, 243, 2, 7 },
7295 {7, 244, 2, 2 },
7296 {8, 244, 2, 7 },
7297 {9, 245, 2, 2 },
7298 {10, 245, 2, 7 },
7299 {11, 246, 2, 2 },
7300 {12, 246, 2, 7 },
7301 {13, 247, 2, 2 },
7302 {14, 248, 2, 4 },
55f9321a
ID		 7303
7304 /* 802.11 UNI / HyperLan 2 */
7305 {36, 0x56, 0, 4},
7306 {38, 0x56, 0, 6},
7307 {40, 0x56, 0, 8},
7308 {44, 0x57, 0, 0},
7309 {46, 0x57, 0, 2},
7310 {48, 0x57, 0, 4},
7311 {52, 0x57, 0, 8},
7312 {54, 0x57, 0, 10},
7313 {56, 0x58, 0, 0},
7314 {60, 0x58, 0, 4},
7315 {62, 0x58, 0, 6},
7316 {64, 0x58, 0, 8},
7317
7318 /* 802.11 HyperLan 2 */
7319 {100, 0x5b, 0, 8},
7320 {102, 0x5b, 0, 10},
7321 {104, 0x5c, 0, 0},
7322 {108, 0x5c, 0, 4},
7323 {110, 0x5c, 0, 6},
7324 {112, 0x5c, 0, 8},
7325 {116, 0x5d, 0, 0},
7326 {118, 0x5d, 0, 2},
7327 {120, 0x5d, 0, 4},
7328 {124, 0x5d, 0, 8},
7329 {126, 0x5d, 0, 10},
7330 {128, 0x5e, 0, 0},
7331 {132, 0x5e, 0, 4},
7332 {134, 0x5e, 0, 6},
7333 {136, 0x5e, 0, 8},
7334 {140, 0x5f, 0, 0},
7335
7336 /* 802.11 UNII */
7337 {149, 0x5f, 0, 9},
7338 {151, 0x5f, 0, 11},
7339 {153, 0x60, 0, 1},
7340 {157, 0x60, 0, 5},
7341 {159, 0x60, 0, 7},
7342 {161, 0x60, 0, 9},
7343 {165, 0x61, 0, 1},
7344 {167, 0x61, 0, 3},
7345 {169, 0x61, 0, 5},
7346 {171, 0x61, 0, 7},
7347 {173, 0x61, 0, 9},
4da2933f
BZ		 7348};
7349
7848b231
SG		 7350static const struct rf_channel rf_vals_5592_xtal20[] = {
7351 /* Channel, N, K, mod, R */
7352 {1, 482, 4, 10, 3},
7353 {2, 483, 4, 10, 3},
7354 {3, 484, 4, 10, 3},
7355 {4, 485, 4, 10, 3},
7356 {5, 486, 4, 10, 3},
7357 {6, 487, 4, 10, 3},
7358 {7, 488, 4, 10, 3},
7359 {8, 489, 4, 10, 3},
7360 {9, 490, 4, 10, 3},
7361 {10, 491, 4, 10, 3},
7362 {11, 492, 4, 10, 3},
7363 {12, 493, 4, 10, 3},
7364 {13, 494, 4, 10, 3},
7365 {14, 496, 8, 10, 3},
7366 {36, 172, 8, 12, 1},
7367 {38, 173, 0, 12, 1},
7368 {40, 173, 4, 12, 1},
7369 {42, 173, 8, 12, 1},
7370 {44, 174, 0, 12, 1},
7371 {46, 174, 4, 12, 1},
7372 {48, 174, 8, 12, 1},
7373 {50, 175, 0, 12, 1},
7374 {52, 175, 4, 12, 1},
7375 {54, 175, 8, 12, 1},
7376 {56, 176, 0, 12, 1},
7377 {58, 176, 4, 12, 1},
7378 {60, 176, 8, 12, 1},
7379 {62, 177, 0, 12, 1},
7380 {64, 177, 4, 12, 1},
7381 {100, 183, 4, 12, 1},
7382 {102, 183, 8, 12, 1},
7383 {104, 184, 0, 12, 1},
7384 {106, 184, 4, 12, 1},
7385 {108, 184, 8, 12, 1},
7386 {110, 185, 0, 12, 1},
7387 {112, 185, 4, 12, 1},
7388 {114, 185, 8, 12, 1},
7389 {116, 186, 0, 12, 1},
7390 {118, 186, 4, 12, 1},
7391 {120, 186, 8, 12, 1},
7392 {122, 187, 0, 12, 1},
7393 {124, 187, 4, 12, 1},
7394 {126, 187, 8, 12, 1},
7395 {128, 188, 0, 12, 1},
7396 {130, 188, 4, 12, 1},
7397 {132, 188, 8, 12, 1},
7398 {134, 189, 0, 12, 1},
7399 {136, 189, 4, 12, 1},
7400 {138, 189, 8, 12, 1},
7401 {140, 190, 0, 12, 1},
7402 {149, 191, 6, 12, 1},
7403 {151, 191, 10, 12, 1},
7404 {153, 192, 2, 12, 1},
7405 {155, 192, 6, 12, 1},
7406 {157, 192, 10, 12, 1},
7407 {159, 193, 2, 12, 1},
7408 {161, 193, 6, 12, 1},
7409 {165, 194, 2, 12, 1},
7410 {184, 164, 0, 12, 1},
7411 {188, 164, 4, 12, 1},
7412 {192, 165, 8, 12, 1},
7413 {196, 166, 0, 12, 1},
7414};
7415
7416static const struct rf_channel rf_vals_5592_xtal40[] = {
7417 /* Channel, N, K, mod, R */
7418 {1, 241, 2, 10, 3},
7419 {2, 241, 7, 10, 3},
7420 {3, 242, 2, 10, 3},
7421 {4, 242, 7, 10, 3},
7422 {5, 243, 2, 10, 3},
7423 {6, 243, 7, 10, 3},
7424 {7, 244, 2, 10, 3},
7425 {8, 244, 7, 10, 3},
7426 {9, 245, 2, 10, 3},
7427 {10, 245, 7, 10, 3},
7428 {11, 246, 2, 10, 3},
7429 {12, 246, 7, 10, 3},
7430 {13, 247, 2, 10, 3},
7431 {14, 248, 4, 10, 3},
7432 {36, 86, 4, 12, 1},
7433 {38, 86, 6, 12, 1},
7434 {40, 86, 8, 12, 1},
7435 {42, 86, 10, 12, 1},
7436 {44, 87, 0, 12, 1},
7437 {46, 87, 2, 12, 1},
7438 {48, 87, 4, 12, 1},
7439 {50, 87, 6, 12, 1},
7440 {52, 87, 8, 12, 1},
7441 {54, 87, 10, 12, 1},
7442 {56, 88, 0, 12, 1},
7443 {58, 88, 2, 12, 1},
7444 {60, 88, 4, 12, 1},
7445 {62, 88, 6, 12, 1},
7446 {64, 88, 8, 12, 1},
7447 {100, 91, 8, 12, 1},
7448 {102, 91, 10, 12, 1},
7449 {104, 92, 0, 12, 1},
7450 {106, 92, 2, 12, 1},
7451 {108, 92, 4, 12, 1},
7452 {110, 92, 6, 12, 1},
7453 {112, 92, 8, 12, 1},
7454 {114, 92, 10, 12, 1},
7455 {116, 93, 0, 12, 1},
7456 {118, 93, 2, 12, 1},
7457 {120, 93, 4, 12, 1},
7458 {122, 93, 6, 12, 1},
7459 {124, 93, 8, 12, 1},
7460 {126, 93, 10, 12, 1},
7461 {128, 94, 0, 12, 1},
7462 {130, 94, 2, 12, 1},
7463 {132, 94, 4, 12, 1},
7464 {134, 94, 6, 12, 1},
7465 {136, 94, 8, 12, 1},
7466 {138, 94, 10, 12, 1},
7467 {140, 95, 0, 12, 1},
7468 {149, 95, 9, 12, 1},
7469 {151, 95, 11, 12, 1},
7470 {153, 96, 1, 12, 1},
7471 {155, 96, 3, 12, 1},
7472 {157, 96, 5, 12, 1},
7473 {159, 96, 7, 12, 1},
7474 {161, 96, 9, 12, 1},
7475 {165, 97, 1, 12, 1},
7476 {184, 82, 0, 12, 1},
7477 {188, 82, 4, 12, 1},
7478 {192, 82, 8, 12, 1},
7479 {196, 83, 0, 12, 1},
7480};
7481
ad417a53 7482static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
4da2933f 7483{
4da2933f
BZ		 7484 struct hw_mode_spec *spec = &rt2x00dev->spec;
7485 struct channel_info *info;
8d1331b3
ID		 7486 char *default_power1;
7487 char *default_power2;
c0a14369 7488 char *default_power3;
4da2933f 7489 unsigned int i;
7848b231 7490 u32 reg;
4da2933f 7491
93b6bd26 7492 /*
58e33a21 7493 * Disable powersaving as default.
93b6bd26 7494 */
58e33a21 7495 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
93b6bd26 7496
4da2933f
BZ		 7497 /*
7498 * Initialize all hw fields.
7499 */
7500 rt2x00dev->hw->flags =
4da2933f
BZ		 7501 IEEE80211_HW_SIGNAL_DBM |
7502 IEEE80211_HW_SUPPORTS_PS |
1df90809 7503 IEEE80211_HW_PS_NULLFUNC_STACK |
9d4f09b8 7504 IEEE80211_HW_AMPDU_AGGREGATION |
2dfca312
FF		 7505 IEEE80211_HW_REPORTS_TX_ACK_STATUS |
7506 IEEE80211_HW_SUPPORTS_HT_CCK_RATES;
9d4f09b8 7507
5a5b6ed6
HS		 7508 /*
7509 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
7510 * unless we are capable of sending the buffered frames out after the
7511 * DTIM transmission using rt2x00lib_beacondone. This will send out
7512 * multicast and broadcast traffic immediately instead of buffering it
7513 * infinitly and thus dropping it after some time.
7514 */
7515 if (!rt2x00_is_usb(rt2x00dev))
7516 rt2x00dev->hw->flags |=
7517 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
4da2933f 7518
4da2933f
BZ		 7519 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
7520 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
3e38d3da 7521 rt2800_eeprom_addr(rt2x00dev,
4da2933f
BZ		 7522 EEPROM_MAC_ADDR_0));
7523
3f2bee24
HS		 7524 /*
7525 * As rt2800 has a global fallback table we cannot specify
7526 * more then one tx rate per frame but since the hw will
7527 * try several rates (based on the fallback table) we should
ba3b9e5e 7528 * initialize max_report_rates to the maximum number of rates
3f2bee24
HS		 7529 * we are going to try. Otherwise mac80211 will truncate our
7530 * reported tx rates and the rc algortihm will end up with
7531 * incorrect data.
7532 */
ba3b9e5e
HS		 7533 rt2x00dev->hw->max_rates = 1;
7534 rt2x00dev->hw->max_report_rates = 7;
3f2bee24
HS		 7535 rt2x00dev->hw->max_rate_tries = 1;
7536
4da2933f
BZ		 7537 /*
7538 * Initialize hw_mode information.
7539 */
4da2933f
BZ		 7540 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
7541
4a32c36d
GJ		 7542 switch (rt2x00dev->chip.rf) {
7543 case RF2720:
7544 case RF2820:
4da2933f
BZ		 7545 spec->num_channels = 14;
7546 spec->channels = rf_vals;
4a32c36d
GJ		 7547 break;
7548
7549 case RF2750:
7550 case RF2850:
4da2933f
BZ		 7551 spec->num_channels = ARRAY_SIZE(rf_vals);
7552 spec->channels = rf_vals;
4a32c36d
GJ		 7553 break;
7554
7555 case RF2020:
7556 case RF3020:
7557 case RF3021:
7558 case RF3022:
7559 case RF3070:
7560 case RF3290:
7561 case RF3320:
7562 case RF3322:
7563 case RF5360:
ac0372ab 7564 case RF5362:
4a32c36d
GJ		 7565 case RF5370:
7566 case RF5372:
7567 case RF5390:
7568 case RF5392:
55f9321a
ID		 7569 spec->num_channels = 14;
7570 spec->channels = rf_vals_3x;
4a32c36d
GJ		 7571 break;
7572
7573 case RF3052:
7574 case RF3053:
55f9321a
ID		 7575 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
7576 spec->channels = rf_vals_3x;
4a32c36d 7577 break;
7848b231 7578
4a32c36d 7579 case RF5592:
7848b231
SG		 7580 rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX, &reg);
7581 if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) {
7582 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40);
7583 spec->channels = rf_vals_5592_xtal40;
7584 } else {
7585 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20);
7586 spec->channels = rf_vals_5592_xtal20;
7587 }
4a32c36d 7588 break;
4da2933f
BZ		 7589 }
7590
53216d6a
SG		 7591 if (WARN_ON_ONCE(!spec->channels))
7592 return -ENODEV;
7593
53c5a099
GJ		 7594 spec->supported_bands = SUPPORT_BAND_2GHZ;
7595 if (spec->num_channels > 14)
7596 spec->supported_bands |= SUPPORT_BAND_5GHZ;
7597
4da2933f
BZ		 7598 /*
7599 * Initialize HT information.
7600 */
5122d898 7601 if (!rt2x00_rf(rt2x00dev, RF2020))
38a522e6
GW		 7602 spec->ht.ht_supported = true;
7603 else
7604 spec->ht.ht_supported = false;
7605
4da2933f 7606 spec->ht.cap =
06443e46 7607 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
4da2933f
BZ		 7608 IEEE80211_HT_CAP_GRN_FLD |
7609 IEEE80211_HT_CAP_SGI_20 |
aa674631 7610 IEEE80211_HT_CAP_SGI_40;
22cabaa6 7611
aa10350d 7612 if (rt2x00dev->default_ant.tx_chain_num >= 2)
22cabaa6
HS		 7613 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
7614
aa10350d
GJ		 7615 spec->ht.cap |= rt2x00dev->default_ant.rx_chain_num <<
7616 IEEE80211_HT_CAP_RX_STBC_SHIFT;
aa674631 7617
4da2933f
BZ		 7618 spec->ht.ampdu_factor = 3;
7619 spec->ht.ampdu_density = 4;
7620 spec->ht.mcs.tx_params =
7621 IEEE80211_HT_MCS_TX_DEFINED |
7622 IEEE80211_HT_MCS_TX_RX_DIFF |
aa10350d
GJ		 7623 ((rt2x00dev->default_ant.tx_chain_num - 1) <<
7624 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
4da2933f 7625
aa10350d 7626 switch (rt2x00dev->default_ant.rx_chain_num) {
4da2933f
BZ		 7627 case 3:
7628 spec->ht.mcs.rx_mask[2] = 0xff;
7629 case 2:
7630 spec->ht.mcs.rx_mask[1] = 0xff;
7631 case 1:
7632 spec->ht.mcs.rx_mask[0] = 0xff;
7633 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
7634 break;
7635 }
7636
7637 /*
7638 * Create channel information array
7639 */
baeb2ffa 7640 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
4da2933f
BZ		 7641 if (!info)
7642 return -ENOMEM;
7643
7644 spec->channels_info = info;
7645
3e38d3da
GJ		 7646 default_power1 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
7647 default_power2 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
4da2933f 7648
c0a14369
GJ		 7649 if (rt2x00dev->default_ant.tx_chain_num > 2)
7650 default_power3 = rt2800_eeprom_addr(rt2x00dev,
7651 EEPROM_EXT_TXPOWER_BG3);
7652 else
7653 default_power3 = NULL;
7654
4da2933f 7655 for (i = 0; i < 14; i++) {
e90c54b2
RJH		 7656 info[i].default_power1 = default_power1[i];
7657 info[i].default_power2 = default_power2[i];
c0a14369
GJ		 7658 if (default_power3)
7659 info[i].default_power3 = default_power3[i];
4da2933f
BZ		 7660 }
7661
7662 if (spec->num_channels > 14) {
3e38d3da
GJ		 7663 default_power1 = rt2800_eeprom_addr(rt2x00dev,
7664 EEPROM_TXPOWER_A1);
7665 default_power2 = rt2800_eeprom_addr(rt2x00dev,
7666 EEPROM_TXPOWER_A2);
4da2933f 7667
c0a14369
GJ		 7668 if (rt2x00dev->default_ant.tx_chain_num > 2)
7669 default_power3 =
7670 rt2800_eeprom_addr(rt2x00dev,
7671 EEPROM_EXT_TXPOWER_A3);
7672 else
7673 default_power3 = NULL;
7674
4da2933f 7675 for (i = 14; i < spec->num_channels; i++) {
0a6f3a8e
GJ		 7676 info[i].default_power1 = default_power1[i - 14];
7677 info[i].default_power2 = default_power2[i - 14];
c0a14369
GJ		 7678 if (default_power3)
7679 info[i].default_power3 = default_power3[i - 14];
4da2933f
BZ		 7680 }
7681 }
7682
2e9c43dd
JL		 7683 switch (rt2x00dev->chip.rf) {
7684 case RF2020:
7685 case RF3020:
7686 case RF3021:
7687 case RF3022:
7688 case RF3320:
7689 case RF3052:
1095df07 7690 case RF3053:
3b9b74ba 7691 case RF3070:
a89534ed 7692 case RF3290:
ccf91bd6 7693 case RF5360:
ac0372ab 7694 case RF5362:
2e9c43dd
JL		 7695 case RF5370:
7696 case RF5372:
7697 case RF5390:
cff3d1f0 7698 case RF5392:
2e9c43dd
JL		 7699 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
7700 break;
7701 }
7702
4da2933f
BZ		 7703 return 0;
7704}
ad417a53 7705
cbafb601
GJ		 7706static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev)
7707{
7708 u32 reg;
7709 u32 rt;
7710 u32 rev;
7711
7712 if (rt2x00_rt(rt2x00dev, RT3290))
7713 rt2800_register_read(rt2x00dev, MAC_CSR0_3290, &reg);
7714 else
7715 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
7716
7717 rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET);
7718 rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION);
7719
7720 switch (rt) {
7721 case RT2860:
7722 case RT2872:
7723 case RT2883:
7724 case RT3070:
7725 case RT3071:
7726 case RT3090:
7727 case RT3290:
7728 case RT3352:
7729 case RT3390:
7730 case RT3572:
2dc2bd2f 7731 case RT3593:
cbafb601
GJ		 7732 case RT5390:
7733 case RT5392:
7734 case RT5592:
7735 break;
7736 default:
ec9c4989
JP		 7737 rt2x00_err(rt2x00dev, "Invalid RT chipset 0x%04x, rev %04x detected\n",
7738 rt, rev);
cbafb601
GJ		 7739 return -ENODEV;
7740 }
7741
7742 rt2x00_set_rt(rt2x00dev, rt, rev);
7743
7744 return 0;
7745}
7746
ad417a53
GW		 7747int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev)
7748{
7749 int retval;
7750 u32 reg;
7751
cbafb601
GJ		 7752 retval = rt2800_probe_rt(rt2x00dev);
7753 if (retval)
7754 return retval;
7755
ad417a53
GW		 7756 /*
7757 * Allocate eeprom data.
7758 */
7759 retval = rt2800_validate_eeprom(rt2x00dev);
7760 if (retval)
7761 return retval;
7762
7763 retval = rt2800_init_eeprom(rt2x00dev);
7764 if (retval)
7765 return retval;
7766
7767 /*
7768 * Enable rfkill polling by setting GPIO direction of the
7769 * rfkill switch GPIO pin correctly.
7770 */
7771 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
7772 rt2x00_set_field32(&reg, GPIO_CTRL_DIR2, 1);
7773 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
7774
7775 /*
7776 * Initialize hw specifications.
7777 */
7778 retval = rt2800_probe_hw_mode(rt2x00dev);
7779 if (retval)
7780 return retval;
7781
7782 /*
7783 * Set device capabilities.
7784 */
7785 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
7786 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
7787 if (!rt2x00_is_usb(rt2x00dev))
7788 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
7789
7790 /*
7791 * Set device requirements.
7792 */
7793 if (!rt2x00_is_soc(rt2x00dev))
7794 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
7795 __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
7796 __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
7797 if (!rt2800_hwcrypt_disabled(rt2x00dev))
7798 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
7799 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
7800 __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
7801 if (rt2x00_is_usb(rt2x00dev))
7802 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
7803 else {
7804 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
7805 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
7806 }
7807
7808 /*
7809 * Set the rssi offset.
7810 */
7811 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
7812
7813 return 0;
7814}
7815EXPORT_SYMBOL_GPL(rt2800_probe_hw);
4da2933f 7816
2ce33995
BZ		 7817/*
7818 * IEEE80211 stack callback functions.
7819 */
e783619e
HS		 7820void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
7821 u16 *iv16)
2ce33995
BZ		 7822{
7823 struct rt2x00_dev *rt2x00dev = hw->priv;
7824 struct mac_iveiv_entry iveiv_entry;
7825 u32 offset;
7826
7827 offset = MAC_IVEIV_ENTRY(hw_key_idx);
7828 rt2800_register_multiread(rt2x00dev, offset,
7829 &iveiv_entry, sizeof(iveiv_entry));
7830
855da5e0
JL		 7831 memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
7832 memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
2ce33995 7833}
e783619e 7834EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
2ce33995 7835
e783619e 7836int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2ce33995
BZ		 7837{
7838 struct rt2x00_dev *rt2x00dev = hw->priv;
7839 u32 reg;
7840 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
7841
7842 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
7843 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
7844 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
7845
7846 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
7847 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
7848 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
7849
7850 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
7851 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
7852 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
7853
7854 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
7855 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
7856 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
7857
7858 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
7859 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
7860 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
7861
7862 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
7863 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
7864 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
7865
7866 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
7867 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
7868 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
7869
7870 return 0;
7871}
e783619e 7872EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
2ce33995 7873
8a3a3c85
EP		 7874int rt2800_conf_tx(struct ieee80211_hw *hw,
7875 struct ieee80211_vif *vif, u16 queue_idx,
e783619e 7876 const struct ieee80211_tx_queue_params *params)
2ce33995
BZ		 7877{
7878 struct rt2x00_dev *rt2x00dev = hw->priv;
7879 struct data_queue *queue;
7880 struct rt2x00_field32 field;
7881 int retval;
7882 u32 reg;
7883 u32 offset;
7884
7885 /*
7886 * First pass the configuration through rt2x00lib, that will
7887 * update the queue settings and validate the input. After that
7888 * we are free to update the registers based on the value
7889 * in the queue parameter.
7890 */
8a3a3c85 7891 retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
2ce33995
BZ		 7892 if (retval)
7893 return retval;
7894
7895 /*
7896 * We only need to perform additional register initialization
7897 * for WMM queues/
7898 */
7899 if (queue_idx >= 4)
7900 return 0;
7901
11f818e0 7902 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
2ce33995
BZ		 7903
7904 /* Update WMM TXOP register */
7905 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
7906 field.bit_offset = (queue_idx & 1) * 16;
7907 field.bit_mask = 0xffff << field.bit_offset;
7908
7909 rt2800_register_read(rt2x00dev, offset, &reg);
7910 rt2x00_set_field32(&reg, field, queue->txop);
7911 rt2800_register_write(rt2x00dev, offset, reg);
7912
7913 /* Update WMM registers */
7914 field.bit_offset = queue_idx * 4;
7915 field.bit_mask = 0xf << field.bit_offset;
7916
7917 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
7918 rt2x00_set_field32(&reg, field, queue->aifs);
7919 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
7920
7921 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
7922 rt2x00_set_field32(&reg, field, queue->cw_min);
7923 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
7924
7925 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
7926 rt2x00_set_field32(&reg, field, queue->cw_max);
7927 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
7928
7929 /* Update EDCA registers */
7930 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
7931
7932 rt2800_register_read(rt2x00dev, offset, &reg);
7933 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
7934 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
7935 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
7936 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
7937 rt2800_register_write(rt2x00dev, offset, reg);
7938
7939 return 0;
7940}
e783619e 7941EXPORT_SYMBOL_GPL(rt2800_conf_tx);
2ce33995 7942
37a41b4a 7943u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
2ce33995
BZ		 7944{
7945 struct rt2x00_dev *rt2x00dev = hw->priv;
7946 u64 tsf;
7947 u32 reg;
7948
7949 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
7950 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
7951 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
7952 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
7953
7954 return tsf;
7955}
e783619e 7956EXPORT_SYMBOL_GPL(rt2800_get_tsf);
2ce33995 7957
e783619e
HS		 7958int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
7959 enum ieee80211_ampdu_mlme_action action,
0b01f030
JB		 7960 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
7961 u8 buf_size)
1df90809 7962{
af35323d 7963 struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
1df90809
HS		 7964 int ret = 0;
7965
af35323d
HS		 7966 /*
7967 * Don't allow aggregation for stations the hardware isn't aware
7968 * of because tx status reports for frames to an unknown station
7969 * always contain wcid=255 and thus we can't distinguish between
7970 * multiple stations which leads to unwanted situations when the
7971 * hw reorders frames due to aggregation.
7972 */
7973 if (sta_priv->wcid < 0)
7974 return 1;
7975
1df90809
HS		 7976 switch (action) {
7977 case IEEE80211_AMPDU_RX_START:
7978 case IEEE80211_AMPDU_RX_STOP:
58ed826e
HS		 7979 /*
7980 * The hw itself takes care of setting up BlockAck mechanisms.
7981 * So, we only have to allow mac80211 to nagotiate a BlockAck
7982 * agreement. Once that is done, the hw will BlockAck incoming
7983 * AMPDUs without further setup.
7984 */
1df90809
HS		 7985 break;
7986 case IEEE80211_AMPDU_TX_START:
7987 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
7988 break;
18b559d5
JB		 7989 case IEEE80211_AMPDU_TX_STOP_CONT:
7990 case IEEE80211_AMPDU_TX_STOP_FLUSH:
7991 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
1df90809
HS		 7992 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
7993 break;
7994 case IEEE80211_AMPDU_TX_OPERATIONAL:
7995 break;
7996 default:
ec9c4989
JP		 7997 rt2x00_warn((struct rt2x00_dev *)hw->priv,
7998 "Unknown AMPDU action\n");
1df90809
HS		 7999 }
8000
8001 return ret;
8002}
e783619e 8003EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
a5ea2f02 8004
977206d7
HS		 8005int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
8006 struct survey_info *survey)
8007{
8008 struct rt2x00_dev *rt2x00dev = hw->priv;
8009 struct ieee80211_conf *conf = &hw->conf;
8010 u32 idle, busy, busy_ext;
8011
8012 if (idx != 0)
8013 return -ENOENT;
8014
675a0b04 8015 survey->channel = conf->chandef.chan;
977206d7
HS		 8016
8017 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
8018 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
8019 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
8020
8021 if (idle || busy) {
4ed20beb
JB		 8022 survey->filled = SURVEY_INFO_TIME |
8023 SURVEY_INFO_TIME_BUSY |
8024 SURVEY_INFO_TIME_EXT_BUSY;
977206d7 8025
4ed20beb
JB		 8026 survey->time = (idle + busy) / 1000;
8027 survey->time_busy = busy / 1000;
8028 survey->time_ext_busy = busy_ext / 1000;
977206d7
HS		 8029 }
8030
9931df26
HS		 8031 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
8032 survey->filled |= SURVEY_INFO_IN_USE;
8033
977206d7
HS		 8034 return 0;
8035
8036}
8037EXPORT_SYMBOL_GPL(rt2800_get_survey);
8038
a5ea2f02
ID		 8039MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
8040MODULE_VERSION(DRV_VERSION);
8041MODULE_DESCRIPTION("Ralink RT2800 library");
8042MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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