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drivers/net: Convert unbounded kzalloc calls to kcalloc
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt61pci.c
CommitLineData
95ea3627 1/*
9c9a0d14 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt61pci
23 Abstract: rt61pci device specific routines.
24 Supported chipsets: RT2561, RT2561s, RT2661.
25 */
26
a7f3a06c 27#include <linux/crc-itu-t.h>
95ea3627
ID		 28#include <linux/delay.h>
29#include <linux/etherdevice.h>
30#include <linux/init.h>
31#include <linux/kernel.h>
32#include <linux/module.h>
5a0e3ad6 33#include <linux/slab.h>
95ea3627
ID		 34#include <linux/pci.h>
35#include <linux/eeprom_93cx6.h>
36
37#include "rt2x00.h"
38#include "rt2x00pci.h"
39#include "rt61pci.h"
40
008c4482
ID		 41/*
42 * Allow hardware encryption to be disabled.
43 */
44static int modparam_nohwcrypt = 0;
45module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
46MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
47
95ea3627
ID		 48/*
49 * Register access.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
b34e620f 55 * between each attempt. When the busy bit is still set at that time,
95ea3627
ID		 56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 */
c9c3b1a5
ID		 59#define WAIT_FOR_BBP(__dev, __reg) \
60 rt2x00pci_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
61#define WAIT_FOR_RF(__dev, __reg) \
62 rt2x00pci_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
63#define WAIT_FOR_MCU(__dev, __reg) \
64 rt2x00pci_regbusy_read((__dev), H2M_MAILBOX_CSR, \
65 H2M_MAILBOX_CSR_OWNER, (__reg))
95ea3627 66
0e14f6d3 67static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 68 const unsigned int word, const u8 value)
69{
70 u32 reg;
71
8ff48a8b
ID		 72 mutex_lock(&rt2x00dev->csr_mutex);
73
95ea3627 74 /*
c9c3b1a5
ID		 75 * Wait until the BBP becomes available, afterwards we
76 * can safely write the new data into the register.
95ea3627 77 */
c9c3b1a5
ID		 78 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
79 reg = 0;
80 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
81 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
82 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
83 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
84
85 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
86 }
8ff48a8b 87
8ff48a8b 88 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 89}
90
0e14f6d3 91static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 92 const unsigned int word, u8 *value)
93{
94 u32 reg;
95
8ff48a8b
ID		 96 mutex_lock(&rt2x00dev->csr_mutex);
97
95ea3627 98 /*
c9c3b1a5
ID		 99 * Wait until the BBP becomes available, afterwards we
100 * can safely write the read request into the register.
101 * After the data has been written, we wait until hardware
102 * returns the correct value, if at any time the register
103 * doesn't become available in time, reg will be 0xffffffff
104 * which means we return 0xff to the caller.
95ea3627 105 */
c9c3b1a5
ID		 106 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
107 reg = 0;
108 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
109 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
110 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
95ea3627 111
c9c3b1a5 112 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
95ea3627 113
c9c3b1a5
ID		 114 WAIT_FOR_BBP(rt2x00dev, &reg);
115 }
95ea3627
ID		 116
117 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
8ff48a8b 118
8ff48a8b 119 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 120}
121
0e14f6d3 122static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 123 const unsigned int word, const u32 value)
124{
125 u32 reg;
95ea3627 126
8ff48a8b
ID		 127 mutex_lock(&rt2x00dev->csr_mutex);
128
c9c3b1a5
ID		 129 /*
130 * Wait until the RF becomes available, afterwards we
131 * can safely write the new data into the register.
132 */
133 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
134 reg = 0;
135 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
136 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 21);
137 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
138 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
139
140 rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
141 rt2x00_rf_write(rt2x00dev, word, value);
95ea3627
ID		 142 }
143
8ff48a8b 144 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 145}
146
0e14f6d3 147static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 148 const u8 command, const u8 token,
149 const u8 arg0, const u8 arg1)
150{
151 u32 reg;
152
8ff48a8b
ID		 153 mutex_lock(&rt2x00dev->csr_mutex);
154
c9c3b1a5
ID		 155 /*
156 * Wait until the MCU becomes available, afterwards we
157 * can safely write the new data into the register.
158 */
159 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
160 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
161 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
162 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
163 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
164 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
165
166 rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, &reg);
167 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
168 rt2x00_set_field32(&reg, HOST_CMD_CSR_INTERRUPT_MCU, 1);
169 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
170 }
8ff48a8b 171
8ff48a8b
ID		 172 mutex_unlock(&rt2x00dev->csr_mutex);
173
95ea3627
ID		 174}
175
176static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
177{
178 struct rt2x00_dev *rt2x00dev = eeprom->data;
179 u32 reg;
180
181 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
182
183 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
184 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
185 eeprom->reg_data_clock =
186 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
187 eeprom->reg_chip_select =
188 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
189}
190
191static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
192{
193 struct rt2x00_dev *rt2x00dev = eeprom->data;
194 u32 reg = 0;
195
196 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
197 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
198 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
199 !!eeprom->reg_data_clock);
200 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
201 !!eeprom->reg_chip_select);
202
203 rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
204}
205
206#ifdef CONFIG_RT2X00_LIB_DEBUGFS
95ea3627
ID		 207static const struct rt2x00debug rt61pci_rt2x00debug = {
208 .owner = THIS_MODULE,
209 .csr = {
743b97ca
ID		 210 .read = rt2x00pci_register_read,
211 .write = rt2x00pci_register_write,
212 .flags = RT2X00DEBUGFS_OFFSET,
213 .word_base = CSR_REG_BASE,
95ea3627
ID		 214 .word_size = sizeof(u32),
215 .word_count = CSR_REG_SIZE / sizeof(u32),
216 },
217 .eeprom = {
218 .read = rt2x00_eeprom_read,
219 .write = rt2x00_eeprom_write,
743b97ca 220 .word_base = EEPROM_BASE,
95ea3627
ID		 221 .word_size = sizeof(u16),
222 .word_count = EEPROM_SIZE / sizeof(u16),
223 },
224 .bbp = {
225 .read = rt61pci_bbp_read,
226 .write = rt61pci_bbp_write,
743b97ca 227 .word_base = BBP_BASE,
95ea3627
ID		 228 .word_size = sizeof(u8),
229 .word_count = BBP_SIZE / sizeof(u8),
230 },
231 .rf = {
232 .read = rt2x00_rf_read,
233 .write = rt61pci_rf_write,
743b97ca 234 .word_base = RF_BASE,
95ea3627
ID		 235 .word_size = sizeof(u32),
236 .word_count = RF_SIZE / sizeof(u32),
237 },
238};
239#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
240
95ea3627
ID		 241static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
242{
243 u32 reg;
244
245 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
181d6902 246 return rt2x00_get_field32(reg, MAC_CSR13_BIT5);
95ea3627 247}
95ea3627 248
771fd565 249#ifdef CONFIG_RT2X00_LIB_LEDS
a2e1d52a 250static void rt61pci_brightness_set(struct led_classdev *led_cdev,
a9450b70
ID		 251 enum led_brightness brightness)
252{
253 struct rt2x00_led *led =
254 container_of(led_cdev, struct rt2x00_led, led_dev);
255 unsigned int enabled = brightness != LED_OFF;
256 unsigned int a_mode =
257 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
258 unsigned int bg_mode =
259 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
260
261 if (led->type == LED_TYPE_RADIO) {
262 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
263 MCU_LEDCS_RADIO_STATUS, enabled);
264
265 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
266 (led->rt2x00dev->led_mcu_reg & 0xff),
267 ((led->rt2x00dev->led_mcu_reg >> 8)));
268 } else if (led->type == LED_TYPE_ASSOC) {
269 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
270 MCU_LEDCS_LINK_BG_STATUS, bg_mode);
271 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
272 MCU_LEDCS_LINK_A_STATUS, a_mode);
273
274 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
275 (led->rt2x00dev->led_mcu_reg & 0xff),
276 ((led->rt2x00dev->led_mcu_reg >> 8)));
277 } else if (led->type == LED_TYPE_QUALITY) {
278 /*
279 * The brightness is divided into 6 levels (0 - 5),
280 * this means we need to convert the brightness
281 * argument into the matching level within that range.
282 */
283 rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
284 brightness / (LED_FULL / 6), 0);
285 }
286}
a2e1d52a
ID		 287
288static int rt61pci_blink_set(struct led_classdev *led_cdev,
289 unsigned long *delay_on,
290 unsigned long *delay_off)
291{
292 struct rt2x00_led *led =
293 container_of(led_cdev, struct rt2x00_led, led_dev);
294 u32 reg;
295
296 rt2x00pci_register_read(led->rt2x00dev, MAC_CSR14, &reg);
297 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
298 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
299 rt2x00pci_register_write(led->rt2x00dev, MAC_CSR14, reg);
300
301 return 0;
302}
475433be
ID		 303
304static void rt61pci_init_led(struct rt2x00_dev *rt2x00dev,
305 struct rt2x00_led *led,
306 enum led_type type)
307{
308 led->rt2x00dev = rt2x00dev;
309 led->type = type;
310 led->led_dev.brightness_set = rt61pci_brightness_set;
311 led->led_dev.blink_set = rt61pci_blink_set;
312 led->flags = LED_INITIALIZED;
313}
771fd565 314#endif /* CONFIG_RT2X00_LIB_LEDS */
a9450b70 315
95ea3627
ID		 316/*
317 * Configuration handlers.
318 */
61e754f4
ID		 319static int rt61pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
320 struct rt2x00lib_crypto *crypto,
321 struct ieee80211_key_conf *key)
322{
323 struct hw_key_entry key_entry;
324 struct rt2x00_field32 field;
325 u32 mask;
326 u32 reg;
327
328 if (crypto->cmd == SET_KEY) {
329 /*
330 * rt2x00lib can't determine the correct free
331 * key_idx for shared keys. We have 1 register
332 * with key valid bits. The goal is simple, read
333 * the register, if that is full we have no slots
334 * left.
335 * Note that each BSS is allowed to have up to 4
336 * shared keys, so put a mask over the allowed
337 * entries.
338 */
339 mask = (0xf << crypto->bssidx);
340
341 rt2x00pci_register_read(rt2x00dev, SEC_CSR0, &reg);
342 reg &= mask;
343
344 if (reg && reg == mask)
345 return -ENOSPC;
346
acaf908d 347 key->hw_key_idx += reg ? ffz(reg) : 0;
61e754f4
ID		 348
349 /*
350 * Upload key to hardware
351 */
352 memcpy(key_entry.key, crypto->key,
353 sizeof(key_entry.key));
354 memcpy(key_entry.tx_mic, crypto->tx_mic,
355 sizeof(key_entry.tx_mic));
356 memcpy(key_entry.rx_mic, crypto->rx_mic,
357 sizeof(key_entry.rx_mic));
358
359 reg = SHARED_KEY_ENTRY(key->hw_key_idx);
360 rt2x00pci_register_multiwrite(rt2x00dev, reg,
361 &key_entry, sizeof(key_entry));
362
363 /*
364 * The cipher types are stored over 2 registers.
365 * bssidx 0 and 1 keys are stored in SEC_CSR1 and
366 * bssidx 1 and 2 keys are stored in SEC_CSR5.
367 * Using the correct defines correctly will cause overhead,
368 * so just calculate the correct offset.
369 */
370 if (key->hw_key_idx < 8) {
371 field.bit_offset = (3 * key->hw_key_idx);
372 field.bit_mask = 0x7 << field.bit_offset;
373
374 rt2x00pci_register_read(rt2x00dev, SEC_CSR1, &reg);
375 rt2x00_set_field32(&reg, field, crypto->cipher);
376 rt2x00pci_register_write(rt2x00dev, SEC_CSR1, reg);
377 } else {
378 field.bit_offset = (3 * (key->hw_key_idx - 8));
379 field.bit_mask = 0x7 << field.bit_offset;
380
381 rt2x00pci_register_read(rt2x00dev, SEC_CSR5, &reg);
382 rt2x00_set_field32(&reg, field, crypto->cipher);
383 rt2x00pci_register_write(rt2x00dev, SEC_CSR5, reg);
384 }
385
386 /*
387 * The driver does not support the IV/EIV generation
388 * in hardware. However it doesn't support the IV/EIV
389 * inside the ieee80211 frame either, but requires it
b34e620f 390 * to be provided separately for the descriptor.
61e754f4
ID		 391 * rt2x00lib will cut the IV/EIV data out of all frames
392 * given to us by mac80211, but we must tell mac80211
393 * to generate the IV/EIV data.
394 */
395 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
396 }
397
398 /*
399 * SEC_CSR0 contains only single-bit fields to indicate
400 * a particular key is valid. Because using the FIELD32()
b34e620f 401 * defines directly will cause a lot of overhead, we use
61e754f4
ID		 402 * a calculation to determine the correct bit directly.
403 */
404 mask = 1 << key->hw_key_idx;
405
406 rt2x00pci_register_read(rt2x00dev, SEC_CSR0, &reg);
407 if (crypto->cmd == SET_KEY)
408 reg |= mask;
409 else if (crypto->cmd == DISABLE_KEY)
410 reg &= ~mask;
411 rt2x00pci_register_write(rt2x00dev, SEC_CSR0, reg);
412
413 return 0;
414}
415
416static int rt61pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
417 struct rt2x00lib_crypto *crypto,
418 struct ieee80211_key_conf *key)
419{
420 struct hw_pairwise_ta_entry addr_entry;
421 struct hw_key_entry key_entry;
422 u32 mask;
423 u32 reg;
424
425 if (crypto->cmd == SET_KEY) {
426 /*
427 * rt2x00lib can't determine the correct free
428 * key_idx for pairwise keys. We have 2 registers
b34e620f
TLSC		 429 * with key valid bits. The goal is simple: read
430 * the first register. If that is full, move to
61e754f4 431 * the next register.
b34e620f
TLSC		 432 * When both registers are full, we drop the key.
433 * Otherwise, we use the first invalid entry.
61e754f4
ID		 434 */
435 rt2x00pci_register_read(rt2x00dev, SEC_CSR2, &reg);
436 if (reg && reg == ~0) {
437 key->hw_key_idx = 32;
438 rt2x00pci_register_read(rt2x00dev, SEC_CSR3, &reg);
439 if (reg && reg == ~0)
440 return -ENOSPC;
441 }
442
acaf908d 443 key->hw_key_idx += reg ? ffz(reg) : 0;
61e754f4
ID		 444
445 /*
446 * Upload key to hardware
447 */
448 memcpy(key_entry.key, crypto->key,
449 sizeof(key_entry.key));
450 memcpy(key_entry.tx_mic, crypto->tx_mic,
451 sizeof(key_entry.tx_mic));
452 memcpy(key_entry.rx_mic, crypto->rx_mic,
453 sizeof(key_entry.rx_mic));
454
455 memset(&addr_entry, 0, sizeof(addr_entry));
456 memcpy(&addr_entry, crypto->address, ETH_ALEN);
457 addr_entry.cipher = crypto->cipher;
458
459 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
460 rt2x00pci_register_multiwrite(rt2x00dev, reg,
461 &key_entry, sizeof(key_entry));
462
463 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
464 rt2x00pci_register_multiwrite(rt2x00dev, reg,
465 &addr_entry, sizeof(addr_entry));
466
467 /*
b34e620f
TLSC		 468 * Enable pairwise lookup table for given BSS idx.
469 * Without this, received frames will not be decrypted
61e754f4
ID		 470 * by the hardware.
471 */
472 rt2x00pci_register_read(rt2x00dev, SEC_CSR4, &reg);
473 reg |= (1 << crypto->bssidx);
474 rt2x00pci_register_write(rt2x00dev, SEC_CSR4, reg);
475
476 /*
477 * The driver does not support the IV/EIV generation
478 * in hardware. However it doesn't support the IV/EIV
479 * inside the ieee80211 frame either, but requires it
3ad2f3fb 480 * to be provided separately for the descriptor.
61e754f4
ID		 481 * rt2x00lib will cut the IV/EIV data out of all frames
482 * given to us by mac80211, but we must tell mac80211
483 * to generate the IV/EIV data.
484 */
485 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
486 }
487
488 /*
489 * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
490 * a particular key is valid. Because using the FIELD32()
b34e620f 491 * defines directly will cause a lot of overhead, we use
61e754f4
ID		 492 * a calculation to determine the correct bit directly.
493 */
494 if (key->hw_key_idx < 32) {
495 mask = 1 << key->hw_key_idx;
496
497 rt2x00pci_register_read(rt2x00dev, SEC_CSR2, &reg);
498 if (crypto->cmd == SET_KEY)
499 reg |= mask;
500 else if (crypto->cmd == DISABLE_KEY)
501 reg &= ~mask;
502 rt2x00pci_register_write(rt2x00dev, SEC_CSR2, reg);
503 } else {
504 mask = 1 << (key->hw_key_idx - 32);
505
506 rt2x00pci_register_read(rt2x00dev, SEC_CSR3, &reg);
507 if (crypto->cmd == SET_KEY)
508 reg |= mask;
509 else if (crypto->cmd == DISABLE_KEY)
510 reg &= ~mask;
511 rt2x00pci_register_write(rt2x00dev, SEC_CSR3, reg);
512 }
513
514 return 0;
515}
516
3a643d24
ID		 517static void rt61pci_config_filter(struct rt2x00_dev *rt2x00dev,
518 const unsigned int filter_flags)
519{
520 u32 reg;
521
522 /*
523 * Start configuration steps.
524 * Note that the version error will always be dropped
525 * and broadcast frames will always be accepted since
526 * there is no filter for it at this time.
527 */
528 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
529 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
530 !(filter_flags & FIF_FCSFAIL));
531 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
532 !(filter_flags & FIF_PLCPFAIL));
533 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
1afcfd54 534 !(filter_flags & (FIF_CONTROL | FIF_PSPOLL)));
3a643d24
ID		 535 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
536 !(filter_flags & FIF_PROMISC_IN_BSS));
537 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
e0b005fa
ID		 538 !(filter_flags & FIF_PROMISC_IN_BSS) &&
539 !rt2x00dev->intf_ap_count);
3a643d24
ID		 540 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
541 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
542 !(filter_flags & FIF_ALLMULTI));
543 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
544 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
545 !(filter_flags & FIF_CONTROL));
546 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
547}
548
6bb40dd1
ID		 549static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
550 struct rt2x00_intf *intf,
551 struct rt2x00intf_conf *conf,
552 const unsigned int flags)
95ea3627 553{
6bb40dd1
ID		 554 unsigned int beacon_base;
555 u32 reg;
95ea3627 556
6bb40dd1
ID		 557 if (flags & CONFIG_UPDATE_TYPE) {
558 /*
559 * Clear current synchronisation setup.
b34e620f 560 * For the Beacon base registers, we only need to clear
6bb40dd1
ID		 561 * the first byte since that byte contains the VALID and OWNER
562 * bits which (when set to 0) will invalidate the entire beacon.
563 */
564 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
6bb40dd1 565 rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
95ea3627 566
6bb40dd1
ID		 567 /*
568 * Enable synchronisation.
569 */
570 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
fd3c91c5 571 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
6bb40dd1 572 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
fd3c91c5 573 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
6bb40dd1
ID		 574 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
575 }
95ea3627 576
6bb40dd1
ID		 577 if (flags & CONFIG_UPDATE_MAC) {
578 reg = le32_to_cpu(conf->mac[1]);
579 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
580 conf->mac[1] = cpu_to_le32(reg);
95ea3627 581
6bb40dd1
ID		 582 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2,
583 conf->mac, sizeof(conf->mac));
584 }
95ea3627 585
6bb40dd1
ID		 586 if (flags & CONFIG_UPDATE_BSSID) {
587 reg = le32_to_cpu(conf->bssid[1]);
588 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
589 conf->bssid[1] = cpu_to_le32(reg);
95ea3627 590
6bb40dd1
ID		 591 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4,
592 conf->bssid, sizeof(conf->bssid));
593 }
95ea3627
ID		 594}
595
3a643d24
ID		 596static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev,
597 struct rt2x00lib_erp *erp)
95ea3627 598{
95ea3627 599 u32 reg;
95ea3627
ID		 600
601 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
4789666e 602 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, 0x32);
8a566afe 603 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
95ea3627
ID		 604 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
605
606 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
8a566afe 607 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
4f5af6eb 608 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
72810379 609 !!erp->short_preamble);
95ea3627 610 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
95ea3627 611
e4ea1c40 612 rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, erp->basic_rates);
95ea3627 613
8a566afe
ID		 614 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
615 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
616 erp->beacon_int * 16);
617 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
618
e4ea1c40
ID		 619 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
620 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time);
621 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
95ea3627 622
e4ea1c40
ID		 623 rt2x00pci_register_read(rt2x00dev, MAC_CSR8, &reg);
624 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs);
625 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
626 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs);
627 rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
95ea3627
ID		 628}
629
630static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
addc81bd 631 struct antenna_setup *ant)
95ea3627
ID		 632{
633 u8 r3;
634 u8 r4;
635 u8 r77;
636
637 rt61pci_bbp_read(rt2x00dev, 3, &r3);
638 rt61pci_bbp_read(rt2x00dev, 4, &r4);
639 rt61pci_bbp_read(rt2x00dev, 77, &r77);
640
5122d898 641 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF5325));
e4cd2ff8
ID		 642
643 /*
644 * Configure the RX antenna.
645 */
addc81bd 646 switch (ant->rx) {
95ea3627 647 case ANTENNA_HW_DIVERSITY:
acaa410d 648 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
95ea3627 649 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
8318d78a 650 (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ));
95ea3627
ID		 651 break;
652 case ANTENNA_A:
acaa410d 653 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 654 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 655 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
acaa410d
MN		 656 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
657 else
658 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
95ea3627
ID		 659 break;
660 case ANTENNA_B:
a4fe07d9 661 default:
acaa410d 662 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 663 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 664 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
acaa410d
MN		 665 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
666 else
667 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
95ea3627
ID		 668 break;
669 }
670
671 rt61pci_bbp_write(rt2x00dev, 77, r77);
672 rt61pci_bbp_write(rt2x00dev, 3, r3);
673 rt61pci_bbp_write(rt2x00dev, 4, r4);
674}
675
676static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
addc81bd 677 struct antenna_setup *ant)
95ea3627
ID		 678{
679 u8 r3;
680 u8 r4;
681 u8 r77;
682
683 rt61pci_bbp_read(rt2x00dev, 3, &r3);
684 rt61pci_bbp_read(rt2x00dev, 4, &r4);
685 rt61pci_bbp_read(rt2x00dev, 77, &r77);
686
5122d898 687 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF2529));
95ea3627
ID		 688 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
689 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
690
e4cd2ff8
ID		 691 /*
692 * Configure the RX antenna.
693 */
addc81bd 694 switch (ant->rx) {
95ea3627 695 case ANTENNA_HW_DIVERSITY:
acaa410d 696 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
95ea3627
ID		 697 break;
698 case ANTENNA_A:
acaa410d
MN		 699 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
700 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
95ea3627
ID		 701 break;
702 case ANTENNA_B:
a4fe07d9 703 default:
acaa410d
MN		 704 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
705 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
95ea3627
ID		 706 break;
707 }
708
709 rt61pci_bbp_write(rt2x00dev, 77, r77);
710 rt61pci_bbp_write(rt2x00dev, 3, r3);
711 rt61pci_bbp_write(rt2x00dev, 4, r4);
712}
713
714static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
715 const int p1, const int p2)
716{
717 u32 reg;
718
719 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
720
acaa410d
MN		 721 rt2x00_set_field32(&reg, MAC_CSR13_BIT4, p1);
722 rt2x00_set_field32(&reg, MAC_CSR13_BIT12, 0);
723
724 rt2x00_set_field32(&reg, MAC_CSR13_BIT3, !p2);
725 rt2x00_set_field32(&reg, MAC_CSR13_BIT11, 0);
726
727 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
95ea3627
ID		 728}
729
730static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
addc81bd 731 struct antenna_setup *ant)
95ea3627 732{
95ea3627
ID		 733 u8 r3;
734 u8 r4;
735 u8 r77;
736
737 rt61pci_bbp_read(rt2x00dev, 3, &r3);
738 rt61pci_bbp_read(rt2x00dev, 4, &r4);
739 rt61pci_bbp_read(rt2x00dev, 77, &r77);
e4cd2ff8 740
e4cd2ff8
ID		 741 /*
742 * Configure the RX antenna.
743 */
744 switch (ant->rx) {
745 case ANTENNA_A:
acaa410d
MN		 746 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
747 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
748 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
e4cd2ff8 749 break;
e4cd2ff8
ID		 750 case ANTENNA_HW_DIVERSITY:
751 /*
a4fe07d9
ID		 752 * FIXME: Antenna selection for the rf 2529 is very confusing
753 * in the legacy driver. Just default to antenna B until the
754 * legacy code can be properly translated into rt2x00 code.
e4cd2ff8
ID		 755 */
756 case ANTENNA_B:
a4fe07d9 757 default:
acaa410d
MN		 758 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
759 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
760 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
e4cd2ff8
ID		 761 break;
762 }
763
e4cd2ff8 764 rt61pci_bbp_write(rt2x00dev, 77, r77);
95ea3627
ID		 765 rt61pci_bbp_write(rt2x00dev, 3, r3);
766 rt61pci_bbp_write(rt2x00dev, 4, r4);
767}
768
769struct antenna_sel {
770 u8 word;
771 /*
772 * value[0] -> non-LNA
773 * value[1] -> LNA
774 */
775 u8 value[2];
776};
777
778static const struct antenna_sel antenna_sel_a[] = {
779 { 96, { 0x58, 0x78 } },
780 { 104, { 0x38, 0x48 } },
781 { 75, { 0xfe, 0x80 } },
782 { 86, { 0xfe, 0x80 } },
783 { 88, { 0xfe, 0x80 } },
784 { 35, { 0x60, 0x60 } },
785 { 97, { 0x58, 0x58 } },
786 { 98, { 0x58, 0x58 } },
787};
788
789static const struct antenna_sel antenna_sel_bg[] = {
790 { 96, { 0x48, 0x68 } },
791 { 104, { 0x2c, 0x3c } },
792 { 75, { 0xfe, 0x80 } },
793 { 86, { 0xfe, 0x80 } },
794 { 88, { 0xfe, 0x80 } },
795 { 35, { 0x50, 0x50 } },
796 { 97, { 0x48, 0x48 } },
797 { 98, { 0x48, 0x48 } },
798};
799
e4ea1c40
ID		 800static void rt61pci_config_ant(struct rt2x00_dev *rt2x00dev,
801 struct antenna_setup *ant)
95ea3627
ID		 802{
803 const struct antenna_sel *sel;
804 unsigned int lna;
805 unsigned int i;
806 u32 reg;
807
a4fe07d9
ID		 808 /*
809 * We should never come here because rt2x00lib is supposed
810 * to catch this and send us the correct antenna explicitely.
811 */
812 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
813 ant->tx == ANTENNA_SW_DIVERSITY);
814
8318d78a 815 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 816 sel = antenna_sel_a;
817 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
95ea3627
ID		 818 } else {
819 sel = antenna_sel_bg;
820 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
95ea3627
ID		 821 }
822
acaa410d
MN		 823 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
824 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
825
826 rt2x00pci_register_read(rt2x00dev, PHY_CSR0, &reg);
827
ddc827f9 828 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
8318d78a 829 rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
ddc827f9 830 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
8318d78a 831 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
ddc827f9 832
95ea3627
ID		 833 rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
834
5122d898 835 if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325))
addc81bd 836 rt61pci_config_antenna_5x(rt2x00dev, ant);
5122d898 837 else if (rt2x00_rf(rt2x00dev, RF2527))
addc81bd 838 rt61pci_config_antenna_2x(rt2x00dev, ant);
5122d898 839 else if (rt2x00_rf(rt2x00dev, RF2529)) {
95ea3627 840 if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))
addc81bd 841 rt61pci_config_antenna_2x(rt2x00dev, ant);
95ea3627 842 else
addc81bd 843 rt61pci_config_antenna_2529(rt2x00dev, ant);
95ea3627
ID		 844 }
845}
846
e4ea1c40
ID		 847static void rt61pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,
848 struct rt2x00lib_conf *libconf)
849{
850 u16 eeprom;
851 short lna_gain = 0;
852
853 if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) {
854 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
855 lna_gain += 14;
856
857 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
858 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
859 } else {
860 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
861 lna_gain += 14;
862
863 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
864 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
865 }
866
867 rt2x00dev->lna_gain = lna_gain;
868}
869
870static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
871 struct rf_channel *rf, const int txpower)
872{
873 u8 r3;
874 u8 r94;
875 u8 smart;
876
877 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
878 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
879
5122d898 880 smart = !(rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527));
e4ea1c40
ID		 881
882 rt61pci_bbp_read(rt2x00dev, 3, &r3);
883 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
884 rt61pci_bbp_write(rt2x00dev, 3, r3);
885
886 r94 = 6;
887 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
888 r94 += txpower - MAX_TXPOWER;
889 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
890 r94 += txpower;
891 rt61pci_bbp_write(rt2x00dev, 94, r94);
892
893 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
894 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
895 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
896 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
897
898 udelay(200);
899
900 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
901 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
902 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
903 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
904
905 udelay(200);
906
907 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
908 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
909 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
910 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
911
912 msleep(1);
913}
914
915static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
916 const int txpower)
917{
918 struct rf_channel rf;
919
920 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
921 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
922 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
923 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
924
925 rt61pci_config_channel(rt2x00dev, &rf, txpower);
926}
927
928static void rt61pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
5c58ee51 929 struct rt2x00lib_conf *libconf)
95ea3627
ID		 930{
931 u32 reg;
932
e4ea1c40 933 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
e1b4d7b7
ID		 934 rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_RATE_DOWN, 1);
935 rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_RATE_STEP, 0);
936 rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_FALLBACK_CCK, 0);
e4ea1c40
ID		 937 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT,
938 libconf->conf->long_frame_max_tx_count);
939 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT,
940 libconf->conf->short_frame_max_tx_count);
941 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
942}
95ea3627 943
7d7f19cc
ID		 944static void rt61pci_config_ps(struct rt2x00_dev *rt2x00dev,
945 struct rt2x00lib_conf *libconf)
946{
947 enum dev_state state =
948 (libconf->conf->flags & IEEE80211_CONF_PS) ?
949 STATE_SLEEP : STATE_AWAKE;
950 u32 reg;
951
952 if (state == STATE_SLEEP) {
953 rt2x00pci_register_read(rt2x00dev, MAC_CSR11, &reg);
954 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN,
6b347bff 955 rt2x00dev->beacon_int - 10);
7d7f19cc
ID		 956 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP,
957 libconf->conf->listen_interval - 1);
958 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 5);
959
960 /* We must first disable autowake before it can be enabled */
961 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
962 rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
963
964 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 1);
965 rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
966
967 rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000005);
968 rt2x00pci_register_write(rt2x00dev, IO_CNTL_CSR, 0x0000001c);
969 rt2x00pci_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000060);
970
971 rt61pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 0);
972 } else {
973 rt2x00pci_register_read(rt2x00dev, MAC_CSR11, &reg);
974 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN, 0);
975 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0);
976 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
977 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 0);
978 rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
979
980 rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000007);
981 rt2x00pci_register_write(rt2x00dev, IO_CNTL_CSR, 0x00000018);
982 rt2x00pci_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000020);
983
984 rt61pci_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
985 }
986}
987
95ea3627 988static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 989 struct rt2x00lib_conf *libconf,
990 const unsigned int flags)
95ea3627 991{
ba2ab471
ID		 992 /* Always recalculate LNA gain before changing configuration */
993 rt61pci_config_lna_gain(rt2x00dev, libconf);
994
e4ea1c40 995 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
5c58ee51
ID		 996 rt61pci_config_channel(rt2x00dev, &libconf->rf,
997 libconf->conf->power_level);
e4ea1c40
ID		 998 if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
999 !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
5c58ee51 1000 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
e4ea1c40
ID		 1001 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1002 rt61pci_config_retry_limit(rt2x00dev, libconf);
7d7f19cc
ID		 1003 if (flags & IEEE80211_CONF_CHANGE_PS)
1004 rt61pci_config_ps(rt2x00dev, libconf);
95ea3627
ID		 1005}
1006
95ea3627
ID		 1007/*
1008 * Link tuning
1009 */
ebcf26da
ID		 1010static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
1011 struct link_qual *qual)
95ea3627
ID		 1012{
1013 u32 reg;
1014
1015 /*
1016 * Update FCS error count from register.
1017 */
1018 rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
ebcf26da 1019 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
95ea3627
ID		 1020
1021 /*
1022 * Update False CCA count from register.
1023 */
1024 rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
ebcf26da 1025 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
95ea3627
ID		 1026}
1027
5352ff65
ID		 1028static inline void rt61pci_set_vgc(struct rt2x00_dev *rt2x00dev,
1029 struct link_qual *qual, u8 vgc_level)
eb20b4e8 1030{
5352ff65 1031 if (qual->vgc_level != vgc_level) {
eb20b4e8 1032 rt61pci_bbp_write(rt2x00dev, 17, vgc_level);
5352ff65
ID		 1033 qual->vgc_level = vgc_level;
1034 qual->vgc_level_reg = vgc_level;
eb20b4e8
ID		 1035 }
1036}
1037
5352ff65
ID		 1038static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
1039 struct link_qual *qual)
95ea3627 1040{
5352ff65 1041 rt61pci_set_vgc(rt2x00dev, qual, 0x20);
95ea3627
ID		 1042}
1043
5352ff65
ID		 1044static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev,
1045 struct link_qual *qual, const u32 count)
95ea3627 1046{
95ea3627
ID		 1047 u8 up_bound;
1048 u8 low_bound;
1049
95ea3627
ID		 1050 /*
1051 * Determine r17 bounds.
1052 */
1497074a 1053 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 1054 low_bound = 0x28;
1055 up_bound = 0x48;
1056 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1057 low_bound += 0x10;
1058 up_bound += 0x10;
1059 }
1060 } else {
1061 low_bound = 0x20;
1062 up_bound = 0x40;
1063 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1064 low_bound += 0x10;
1065 up_bound += 0x10;
1066 }
1067 }
1068
6bb40dd1
ID		 1069 /*
1070 * If we are not associated, we should go straight to the
1071 * dynamic CCA tuning.
1072 */
1073 if (!rt2x00dev->intf_associated)
1074 goto dynamic_cca_tune;
1075
95ea3627
ID		 1076 /*
1077 * Special big-R17 for very short distance
1078 */
5352ff65
ID		 1079 if (qual->rssi >= -35) {
1080 rt61pci_set_vgc(rt2x00dev, qual, 0x60);
95ea3627
ID		 1081 return;
1082 }
1083
1084 /*
1085 * Special big-R17 for short distance
1086 */
5352ff65
ID		 1087 if (qual->rssi >= -58) {
1088 rt61pci_set_vgc(rt2x00dev, qual, up_bound);
95ea3627
ID		 1089 return;
1090 }
1091
1092 /*
1093 * Special big-R17 for middle-short distance
1094 */
5352ff65
ID		 1095 if (qual->rssi >= -66) {
1096 rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x10);
95ea3627
ID		 1097 return;
1098 }
1099
1100 /*
1101 * Special mid-R17 for middle distance
1102 */
5352ff65
ID		 1103 if (qual->rssi >= -74) {
1104 rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x08);
95ea3627
ID		 1105 return;
1106 }
1107
1108 /*
1109 * Special case: Change up_bound based on the rssi.
1110 * Lower up_bound when rssi is weaker then -74 dBm.
1111 */
5352ff65 1112 up_bound -= 2 * (-74 - qual->rssi);
95ea3627
ID		 1113 if (low_bound > up_bound)
1114 up_bound = low_bound;
1115
5352ff65
ID		 1116 if (qual->vgc_level > up_bound) {
1117 rt61pci_set_vgc(rt2x00dev, qual, up_bound);
95ea3627
ID		 1118 return;
1119 }
1120
6bb40dd1
ID		 1121dynamic_cca_tune:
1122
95ea3627
ID		 1123 /*
1124 * r17 does not yet exceed upper limit, continue and base
1125 * the r17 tuning on the false CCA count.
1126 */
5352ff65
ID		 1127 if ((qual->false_cca > 512) && (qual->vgc_level < up_bound))
1128 rt61pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level);
1129 else if ((qual->false_cca < 100) && (qual->vgc_level > low_bound))
1130 rt61pci_set_vgc(rt2x00dev, qual, --qual->vgc_level);
95ea3627
ID		 1131}
1132
1133/*
a7f3a06c 1134 * Firmware functions
95ea3627
ID		 1135 */
1136static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1137{
49e721ec 1138 u16 chip;
95ea3627
ID		 1139 char *fw_name;
1140
49e721ec
GW		 1141 pci_read_config_word(to_pci_dev(rt2x00dev->dev), PCI_DEVICE_ID, &chip);
1142 switch (chip) {
1143 case RT2561_PCI_ID:
95ea3627
ID		 1144 fw_name = FIRMWARE_RT2561;
1145 break;
49e721ec 1146 case RT2561s_PCI_ID:
95ea3627
ID		 1147 fw_name = FIRMWARE_RT2561s;
1148 break;
49e721ec 1149 case RT2661_PCI_ID:
95ea3627
ID		 1150 fw_name = FIRMWARE_RT2661;
1151 break;
1152 default:
1153 fw_name = NULL;
1154 break;
1155 }
1156
1157 return fw_name;
1158}
1159
0cbe0064
ID		 1160static int rt61pci_check_firmware(struct rt2x00_dev *rt2x00dev,
1161 const u8 *data, const size_t len)
a7f3a06c 1162{
0cbe0064 1163 u16 fw_crc;
a7f3a06c
ID		 1164 u16 crc;
1165
1166 /*
0cbe0064
ID		 1167 * Only support 8kb firmware files.
1168 */
1169 if (len != 8192)
1170 return FW_BAD_LENGTH;
1171
1172 /*
b34e620f
TLSC		 1173 * The last 2 bytes in the firmware array are the crc checksum itself.
1174 * This means that we should never pass those 2 bytes to the crc
a7f3a06c
ID		 1175 * algorithm.
1176 */
0cbe0064
ID		 1177 fw_crc = (data[len - 2] << 8 | data[len - 1]);
1178
1179 /*
1180 * Use the crc itu-t algorithm.
1181 */
a7f3a06c
ID		 1182 crc = crc_itu_t(0, data, len - 2);
1183 crc = crc_itu_t_byte(crc, 0);
1184 crc = crc_itu_t_byte(crc, 0);
1185
0cbe0064 1186 return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
a7f3a06c
ID		 1187}
1188
0cbe0064
ID		 1189static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev,
1190 const u8 *data, const size_t len)
95ea3627
ID		 1191{
1192 int i;
1193 u32 reg;
1194
1195 /*
1196 * Wait for stable hardware.
1197 */
1198 for (i = 0; i < 100; i++) {
1199 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1200 if (reg)
1201 break;
1202 msleep(1);
1203 }
1204
1205 if (!reg) {
1206 ERROR(rt2x00dev, "Unstable hardware.\n");
1207 return -EBUSY;
1208 }
1209
1210 /*
1211 * Prepare MCU and mailbox for firmware loading.
1212 */
1213 reg = 0;
1214 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1215 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1216 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1217 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1218 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
1219
1220 /*
1221 * Write firmware to device.
1222 */
1223 reg = 0;
1224 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1225 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 1);
1226 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1227
1228 rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
1229 data, len);
1230
1231 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 0);
1232 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1233
1234 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 0);
1235 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1236
1237 for (i = 0; i < 100; i++) {
1238 rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, &reg);
1239 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
1240 break;
1241 msleep(1);
1242 }
1243
1244 if (i == 100) {
1245 ERROR(rt2x00dev, "MCU Control register not ready.\n");
1246 return -EBUSY;
1247 }
1248
e6d3e902
ID		 1249 /*
1250 * Hardware needs another millisecond before it is ready.
1251 */
1252 msleep(1);
1253
95ea3627
ID		 1254 /*
1255 * Reset MAC and BBP registers.
1256 */
1257 reg = 0;
1258 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1259 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1260 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1261
1262 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1263 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1264 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1265 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1266
1267 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1268 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1269 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1270
1271 return 0;
1272}
1273
a7f3a06c
ID		 1274/*
1275 * Initialization functions.
1276 */
798b7adb 1277static bool rt61pci_get_entry_state(struct queue_entry *entry)
95ea3627 1278{
b8be63ff 1279 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
95ea3627
ID		 1280 u32 word;
1281
798b7adb
ID		 1282 if (entry->queue->qid == QID_RX) {
1283 rt2x00_desc_read(entry_priv->desc, 0, &word);
95ea3627 1284
798b7adb
ID		 1285 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
1286 } else {
1287 rt2x00_desc_read(entry_priv->desc, 0, &word);
1288
1289 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1290 rt2x00_get_field32(word, TXD_W0_VALID));
1291 }
95ea3627
ID		 1292}
1293
798b7adb 1294static void rt61pci_clear_entry(struct queue_entry *entry)
95ea3627 1295{
b8be63ff 1296 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
798b7adb 1297 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
95ea3627
ID		 1298 u32 word;
1299
798b7adb
ID		 1300 if (entry->queue->qid == QID_RX) {
1301 rt2x00_desc_read(entry_priv->desc, 5, &word);
1302 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
1303 skbdesc->skb_dma);
1304 rt2x00_desc_write(entry_priv->desc, 5, word);
1305
1306 rt2x00_desc_read(entry_priv->desc, 0, &word);
1307 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
1308 rt2x00_desc_write(entry_priv->desc, 0, word);
1309 } else {
1310 rt2x00_desc_read(entry_priv->desc, 0, &word);
1311 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1312 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
1313 rt2x00_desc_write(entry_priv->desc, 0, word);
1314 }
95ea3627
ID		 1315}
1316
181d6902 1317static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
95ea3627 1318{
b8be63ff 1319 struct queue_entry_priv_pci *entry_priv;
95ea3627
ID		 1320 u32 reg;
1321
95ea3627
ID		 1322 /*
1323 * Initialize registers.
1324 */
1325 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, &reg);
1326 rt2x00_set_field32(&reg, TX_RING_CSR0_AC0_RING_SIZE,
181d6902 1327 rt2x00dev->tx[0].limit);
95ea3627 1328 rt2x00_set_field32(&reg, TX_RING_CSR0_AC1_RING_SIZE,
181d6902 1329 rt2x00dev->tx[1].limit);
95ea3627 1330 rt2x00_set_field32(&reg, TX_RING_CSR0_AC2_RING_SIZE,
181d6902 1331 rt2x00dev->tx[2].limit);
95ea3627 1332 rt2x00_set_field32(&reg, TX_RING_CSR0_AC3_RING_SIZE,
181d6902 1333 rt2x00dev->tx[3].limit);
95ea3627
ID		 1334 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
1335
1336 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, &reg);
95ea3627 1337 rt2x00_set_field32(&reg, TX_RING_CSR1_TXD_SIZE,
181d6902 1338 rt2x00dev->tx[0].desc_size / 4);
95ea3627
ID		 1339 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1340
b8be63ff 1341 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
95ea3627 1342 rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
30b3a23c 1343 rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER,
b8be63ff 1344 entry_priv->desc_dma);
95ea3627
ID		 1345 rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1346
b8be63ff 1347 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
95ea3627 1348 rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
30b3a23c 1349 rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER,
b8be63ff 1350 entry_priv->desc_dma);
95ea3627
ID		 1351 rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1352
b8be63ff 1353 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
95ea3627 1354 rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
30b3a23c 1355 rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER,
b8be63ff 1356 entry_priv->desc_dma);
95ea3627
ID		 1357 rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1358
b8be63ff 1359 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
95ea3627 1360 rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
30b3a23c 1361 rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER,
b8be63ff 1362 entry_priv->desc_dma);
95ea3627
ID		 1363 rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1364
95ea3627 1365 rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg);
181d6902 1366 rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit);
95ea3627
ID		 1367 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_SIZE,
1368 rt2x00dev->rx->desc_size / 4);
1369 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1370 rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1371
b8be63ff 1372 entry_priv = rt2x00dev->rx->entries[0].priv_data;
95ea3627 1373 rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg);
30b3a23c 1374 rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER,
b8be63ff 1375 entry_priv->desc_dma);
95ea3627
ID		 1376 rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1377
1378 rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg);
1379 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC0, 2);
1380 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC1, 2);
1381 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC2, 2);
1382 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC3, 2);
95ea3627
ID		 1383 rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1384
1385 rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, &reg);
1386 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
1387 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
1388 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
1389 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
95ea3627
ID		 1390 rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1391
1392 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1393 rt2x00_set_field32(&reg, RX_CNTL_CSR_LOAD_RXD, 1);
1394 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1395
1396 return 0;
1397}
1398
1399static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1400{
1401 u32 reg;
1402
1403 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1404 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1405 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1406 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1407 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1408
1409 rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, &reg);
1410 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1411 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1412 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1413 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1414 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1415 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1416 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1417 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1418 rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
1419
1420 /*
1421 * CCK TXD BBP registers
1422 */
1423 rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, &reg);
1424 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1425 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1426 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1427 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1428 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1429 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1430 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1431 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1432 rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
1433
1434 /*
1435 * OFDM TXD BBP registers
1436 */
1437 rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, &reg);
1438 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1439 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1440 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1441 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1442 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1443 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1444 rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
1445
1446 rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, &reg);
1447 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1448 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1449 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1450 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1451 rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
1452
1453 rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, &reg);
1454 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1455 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1456 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1457 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1458 rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
1459
1f909162
ID		 1460 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1461 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
1462 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1463 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
1464 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1465 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1466 rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
1467 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1468
95ea3627
ID		 1469 rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1470
1471 rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1472
1473 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
1474 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1475 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
1476
1477 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
1478
1479 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1480 return -EBUSY;
1481
1482 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1483
1484 /*
1485 * Invalidate all Shared Keys (SEC_CSR0),
1486 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1487 */
1488 rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1489 rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1490 rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1491
1492 rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1493 rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1494 rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1495 rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1496
1497 rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1498
1499 rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1500
1501 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1502
6bb40dd1
ID		 1503 /*
1504 * Clear all beacons
1505 * For the Beacon base registers we only need to clear
1506 * the first byte since that byte contains the VALID and OWNER
1507 * bits which (when set to 0) will invalidate the entire beacon.
1508 */
1509 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1510 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1511 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1512 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1513
95ea3627
ID		 1514 /*
1515 * We must clear the error counters.
1516 * These registers are cleared on read,
1517 * so we may pass a useless variable to store the value.
1518 */
1519 rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
1520 rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
1521 rt2x00pci_register_read(rt2x00dev, STA_CSR2, &reg);
1522
1523 /*
1524 * Reset MAC and BBP registers.
1525 */
1526 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1527 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1528 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1529 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1530
1531 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1532 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1533 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1534 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1535
1536 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1537 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1538 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1539
1540 return 0;
1541}
1542
2b08da3f 1543static int rt61pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 1544{
1545 unsigned int i;
95ea3627
ID		 1546 u8 value;
1547
1548 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1549 rt61pci_bbp_read(rt2x00dev, 0, &value);
1550 if ((value != 0xff) && (value != 0x00))
2b08da3f 1551 return 0;
95ea3627
ID		 1552 udelay(REGISTER_BUSY_DELAY);
1553 }
1554
1555 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1556 return -EACCES;
2b08da3f
ID		 1557}
1558
1559static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1560{
1561 unsigned int i;
1562 u16 eeprom;
1563 u8 reg_id;
1564 u8 value;
1565
1566 if (unlikely(rt61pci_wait_bbp_ready(rt2x00dev)))
1567 return -EACCES;
95ea3627 1568
95ea3627
ID		 1569 rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1570 rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1571 rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1572 rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1573 rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1574 rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1575 rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1576 rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1577 rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1578 rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1579 rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1580 rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1581 rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1582 rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1583 rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1584 rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1585 rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1586 rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1587 rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1588 rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1589 rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1590 rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1591 rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1592 rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1593
95ea3627
ID		 1594 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1595 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1596
1597 if (eeprom != 0xffff && eeprom != 0x0000) {
1598 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1599 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
95ea3627
ID		 1600 rt61pci_bbp_write(rt2x00dev, reg_id, value);
1601 }
1602 }
95ea3627
ID		 1603
1604 return 0;
1605}
1606
1607/*
1608 * Device state switch handlers.
1609 */
1610static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1611 enum dev_state state)
1612{
1613 u32 reg;
1614
1615 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1616 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
2b08da3f
ID		 1617 (state == STATE_RADIO_RX_OFF) ||
1618 (state == STATE_RADIO_RX_OFF_LINK));
95ea3627
ID		 1619 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1620}
1621
1622static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1623 enum dev_state state)
1624{
78e256c9
HS		 1625 int mask = (state == STATE_RADIO_IRQ_OFF) ||
1626 (state == STATE_RADIO_IRQ_OFF_ISR);
95ea3627
ID		 1627 u32 reg;
1628
1629 /*
1630 * When interrupts are being enabled, the interrupt registers
1631 * should clear the register to assure a clean state.
1632 */
1633 if (state == STATE_RADIO_IRQ_ON) {
1634 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1635 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1636
1637 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg);
1638 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1639 }
1640
1641 /*
1642 * Only toggle the interrupts bits we are going to use.
1643 * Non-checked interrupt bits are disabled by default.
1644 */
1645 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1646 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask);
1647 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask);
1648 rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, mask);
1649 rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1650 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1651
1652 rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
1653 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_0, mask);
1654 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_1, mask);
1655 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_2, mask);
1656 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_3, mask);
1657 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_4, mask);
1658 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_5, mask);
1659 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_6, mask);
1660 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, mask);
1661 rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1662}
1663
1664static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1665{
1666 u32 reg;
1667
1668 /*
1669 * Initialize all registers.
1670 */
2b08da3f
ID		 1671 if (unlikely(rt61pci_init_queues(rt2x00dev) ||
1672 rt61pci_init_registers(rt2x00dev) ||
1673 rt61pci_init_bbp(rt2x00dev)))
95ea3627 1674 return -EIO;
95ea3627
ID		 1675
1676 /*
1677 * Enable RX.
1678 */
1679 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1680 rt2x00_set_field32(&reg, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
1681 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1682
95ea3627
ID		 1683 return 0;
1684}
1685
1686static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1687{
95ea3627 1688 /*
a2c9b652 1689 * Disable power
95ea3627 1690 */
a2c9b652 1691 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
95ea3627
ID		 1692}
1693
1694static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1695{
9655a6ec 1696 u32 reg, reg2;
95ea3627
ID		 1697 unsigned int i;
1698 char put_to_sleep;
95ea3627
ID		 1699
1700 put_to_sleep = (state != STATE_AWAKE);
1701
1702 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1703 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1704 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1705 rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1706
1707 /*
1708 * Device is not guaranteed to be in the requested state yet.
1709 * We must wait until the register indicates that the
1710 * device has entered the correct state.
1711 */
1712 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
9655a6ec
GW		 1713 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg2);
1714 state = rt2x00_get_field32(reg2, MAC_CSR12_BBP_CURRENT_STATE);
2b08da3f 1715 if (state == !put_to_sleep)
95ea3627 1716 return 0;
9655a6ec 1717 rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
95ea3627
ID		 1718 msleep(10);
1719 }
1720
95ea3627
ID		 1721 return -EBUSY;
1722}
1723
1724static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1725 enum dev_state state)
1726{
1727 int retval = 0;
1728
1729 switch (state) {
1730 case STATE_RADIO_ON:
1731 retval = rt61pci_enable_radio(rt2x00dev);
1732 break;
1733 case STATE_RADIO_OFF:
1734 rt61pci_disable_radio(rt2x00dev);
1735 break;
1736 case STATE_RADIO_RX_ON:
61667d8d 1737 case STATE_RADIO_RX_ON_LINK:
95ea3627 1738 case STATE_RADIO_RX_OFF:
61667d8d 1739 case STATE_RADIO_RX_OFF_LINK:
2b08da3f
ID		 1740 rt61pci_toggle_rx(rt2x00dev, state);
1741 break;
1742 case STATE_RADIO_IRQ_ON:
78e256c9 1743 case STATE_RADIO_IRQ_ON_ISR:
2b08da3f 1744 case STATE_RADIO_IRQ_OFF:
78e256c9 1745 case STATE_RADIO_IRQ_OFF_ISR:
2b08da3f 1746 rt61pci_toggle_irq(rt2x00dev, state);
95ea3627
ID		 1747 break;
1748 case STATE_DEEP_SLEEP:
1749 case STATE_SLEEP:
1750 case STATE_STANDBY:
1751 case STATE_AWAKE:
1752 retval = rt61pci_set_state(rt2x00dev, state);
1753 break;
1754 default:
1755 retval = -ENOTSUPP;
1756 break;
1757 }
1758
2b08da3f
ID		 1759 if (unlikely(retval))
1760 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1761 state, retval);
1762
95ea3627
ID		 1763 return retval;
1764}
1765
1766/*
1767 * TX descriptor initialization
1768 */
1769static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
61e754f4
ID		 1770 struct sk_buff *skb,
1771 struct txentry_desc *txdesc)
95ea3627 1772{
181d6902 1773 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
85b7a8b3
GW		 1774 struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
1775 __le32 *txd = entry_priv->desc;
95ea3627
ID		 1776 u32 word;
1777
1778 /*
1779 * Start writing the descriptor words.
1780 */
1781 rt2x00_desc_read(txd, 1, &word);
181d6902
ID		 1782 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1783 rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1784 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1785 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
61e754f4 1786 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
5adf6d63
ID		 1787 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1788 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
4de36fe5 1789 rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
95ea3627
ID		 1790 rt2x00_desc_write(txd, 1, word);
1791
1792 rt2x00_desc_read(txd, 2, &word);
181d6902
ID		 1793 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1794 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1795 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1796 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
95ea3627
ID		 1797 rt2x00_desc_write(txd, 2, word);
1798
61e754f4 1799 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1ce9cdac
ID		 1800 _rt2x00_desc_write(txd, 3, skbdesc->iv[0]);
1801 _rt2x00_desc_write(txd, 4, skbdesc->iv[1]);
61e754f4
ID		 1802 }
1803
95ea3627 1804 rt2x00_desc_read(txd, 5, &word);
4de36fe5
GW		 1805 rt2x00_set_field32(&word, TXD_W5_PID_TYPE, skbdesc->entry->queue->qid);
1806 rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE,
1807 skbdesc->entry->entry_idx);
95ea3627 1808 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
ac1aa7e4 1809 TXPOWER_TO_DEV(rt2x00dev->tx_power));
95ea3627
ID		 1810 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1811 rt2x00_desc_write(txd, 5, word);
1812
6b97cb04
GW		 1813 if (txdesc->queue != QID_BEACON) {
1814 rt2x00_desc_read(txd, 6, &word);
1815 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
1816 skbdesc->skb_dma);
1817 rt2x00_desc_write(txd, 6, word);
4de36fe5 1818
d7bafff3 1819 rt2x00_desc_read(txd, 11, &word);
df624ca5
GW		 1820 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0,
1821 txdesc->length);
d7bafff3
AB		 1822 rt2x00_desc_write(txd, 11, word);
1823 }
95ea3627 1824
e01f1ec3
GW		 1825 /*
1826 * Writing TXD word 0 must the last to prevent a race condition with
1827 * the device, whereby the device may take hold of the TXD before we
1828 * finished updating it.
1829 */
95ea3627
ID		 1830 rt2x00_desc_read(txd, 0, &word);
1831 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1832 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1833 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
181d6902 1834 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
95ea3627 1835 rt2x00_set_field32(&word, TXD_W0_ACK,
181d6902 1836 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
95ea3627 1837 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
181d6902 1838 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
95ea3627 1839 rt2x00_set_field32(&word, TXD_W0_OFDM,
076f9582 1840 (txdesc->rate_mode == RATE_MODE_OFDM));
181d6902 1841 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
95ea3627 1842 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
61486e0f 1843 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
61e754f4
ID		 1844 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
1845 test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
1846 rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1847 test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
1848 rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
df624ca5 1849 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length);
95ea3627 1850 rt2x00_set_field32(&word, TXD_W0_BURST,
181d6902 1851 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
61e754f4 1852 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
95ea3627 1853 rt2x00_desc_write(txd, 0, word);
85b7a8b3
GW		 1854
1855 /*
1856 * Register descriptor details in skb frame descriptor.
1857 */
1858 skbdesc->desc = txd;
1859 skbdesc->desc_len =
1860 (txdesc->queue == QID_BEACON) ? TXINFO_SIZE : TXD_DESC_SIZE;
95ea3627
ID		 1861}
1862
1863/*
1864 * TX data initialization
1865 */
f224f4ef
GW		 1866static void rt61pci_write_beacon(struct queue_entry *entry,
1867 struct txentry_desc *txdesc)
bd88a781
ID		 1868{
1869 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
85b7a8b3 1870 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
bd88a781
ID		 1871 unsigned int beacon_base;
1872 u32 reg;
1873
1874 /*
1875 * Disable beaconing while we are reloading the beacon data,
1876 * otherwise we might be sending out invalid data.
1877 */
1878 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
bd88a781
ID		 1879 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1880 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1881
5c3b685c
GW		 1882 /*
1883 * Write the TX descriptor for the beacon.
1884 */
1885 rt61pci_write_tx_desc(rt2x00dev, entry->skb, txdesc);
1886
1887 /*
1888 * Dump beacon to userspace through debugfs.
1889 */
1890 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
1891
bd88a781
ID		 1892 /*
1893 * Write entire beacon with descriptor to register.
1894 */
1895 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
85b7a8b3
GW		 1896 rt2x00pci_register_multiwrite(rt2x00dev, beacon_base,
1897 entry_priv->desc, TXINFO_SIZE);
1898 rt2x00pci_register_multiwrite(rt2x00dev, beacon_base + TXINFO_SIZE,
bd88a781
ID		 1899 entry->skb->data, entry->skb->len);
1900
d61cb266
GW		 1901 /*
1902 * Enable beaconing again.
1903 *
1904 * For Wi-Fi faily generated beacons between participating
1905 * stations. Set TBTT phase adaptive adjustment step to 8us.
1906 */
1907 rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1908
1909 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1910 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1911 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1912 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1913
bd88a781
ID		 1914 /*
1915 * Clean up beacon skb.
1916 */
1917 dev_kfree_skb_any(entry->skb);
1918 entry->skb = NULL;
1919}
1920
95ea3627 1921static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
e58c6aca 1922 const enum data_queue_qid queue)
95ea3627
ID		 1923{
1924 u32 reg;
1925
95ea3627 1926 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
e58c6aca
ID		 1927 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0, (queue == QID_AC_BE));
1928 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1, (queue == QID_AC_BK));
1929 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2, (queue == QID_AC_VI));
1930 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3, (queue == QID_AC_VO));
95ea3627
ID		 1931 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1932}
1933
a2c9b652
ID		 1934static void rt61pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
1935 const enum data_queue_qid qid)
1936{
1937 u32 reg;
1938
1939 if (qid == QID_BEACON) {
1940 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
1941 return;
1942 }
1943
1944 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1945 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, (qid == QID_AC_BE));
1946 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, (qid == QID_AC_BK));
1947 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, (qid == QID_AC_VI));
1948 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, (qid == QID_AC_VO));
1949 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1950}
1951
95ea3627
ID		 1952/*
1953 * RX control handlers
1954 */
1955static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1956{
ba2ab471 1957 u8 offset = rt2x00dev->lna_gain;
95ea3627
ID		 1958 u8 lna;
1959
1960 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1961 switch (lna) {
1962 case 3:
ba2ab471 1963 offset += 90;
95ea3627
ID		 1964 break;
1965 case 2:
ba2ab471 1966 offset += 74;
95ea3627
ID		 1967 break;
1968 case 1:
ba2ab471 1969 offset += 64;
95ea3627
ID		 1970 break;
1971 default:
1972 return 0;
1973 }
1974
8318d78a 1975 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 1976 if (lna == 3 || lna == 2)
1977 offset += 10;
95ea3627
ID		 1978 }
1979
1980 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1981}
1982
181d6902 1983static void rt61pci_fill_rxdone(struct queue_entry *entry,
55887511 1984 struct rxdone_entry_desc *rxdesc)
95ea3627 1985{
61e754f4 1986 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
b8be63ff 1987 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
95ea3627
ID		 1988 u32 word0;
1989 u32 word1;
1990
b8be63ff
ID		 1991 rt2x00_desc_read(entry_priv->desc, 0, &word0);
1992 rt2x00_desc_read(entry_priv->desc, 1, &word1);
95ea3627 1993
4150c572 1994 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1995 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
95ea3627 1996
78b8f3b0
GW		 1997 rxdesc->cipher = rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
1998 rxdesc->cipher_status = rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
61e754f4
ID		 1999
2000 if (rxdesc->cipher != CIPHER_NONE) {
1ce9cdac
ID		 2001 _rt2x00_desc_read(entry_priv->desc, 2, &rxdesc->iv[0]);
2002 _rt2x00_desc_read(entry_priv->desc, 3, &rxdesc->iv[1]);
74415edb
ID		 2003 rxdesc->dev_flags |= RXDONE_CRYPTO_IV;
2004
61e754f4 2005 _rt2x00_desc_read(entry_priv->desc, 4, &rxdesc->icv);
74415edb 2006 rxdesc->dev_flags |= RXDONE_CRYPTO_ICV;
61e754f4
ID		 2007
2008 /*
2009 * Hardware has stripped IV/EIV data from 802.11 frame during
b34e620f 2010 * decryption. It has provided the data separately but rt2x00lib
61e754f4
ID		 2011 * should decide if it should be reinserted.
2012 */
2013 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
2014
2015 /*
2016 * FIXME: Legacy driver indicates that the frame does
2017 * contain the Michael Mic. Unfortunately, in rt2x00
2018 * the MIC seems to be missing completely...
2019 */
2020 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
2021
2022 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
2023 rxdesc->flags |= RX_FLAG_DECRYPTED;
2024 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
2025 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
2026 }
2027
95ea3627
ID		 2028 /*
2029 * Obtain the status about this packet.
89993890
ID		 2030 * When frame was received with an OFDM bitrate,
2031 * the signal is the PLCP value. If it was received with
2032 * a CCK bitrate the signal is the rate in 100kbit/s.
95ea3627 2033 */
181d6902 2034 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
61e754f4 2035 rxdesc->rssi = rt61pci_agc_to_rssi(rt2x00dev, word1);
181d6902 2036 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
19d30e02 2037
19d30e02
ID		 2038 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
2039 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
6c6aa3c0
ID		 2040 else
2041 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
19d30e02
ID		 2042 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
2043 rxdesc->dev_flags |= RXDONE_MY_BSS;
95ea3627
ID		 2044}
2045
2046/*
2047 * Interrupt functions.
2048 */
2049static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
2050{
181d6902
ID		 2051 struct data_queue *queue;
2052 struct queue_entry *entry;
2053 struct queue_entry *entry_done;
b8be63ff 2054 struct queue_entry_priv_pci *entry_priv;
181d6902 2055 struct txdone_entry_desc txdesc;
95ea3627
ID		 2056 u32 word;
2057 u32 reg;
95ea3627
ID		 2058 int type;
2059 int index;
e6474c3c 2060 int i;
95ea3627
ID		 2061
2062 /*
e6474c3c
ID		 2063 * TX_STA_FIFO is a stack of X entries, hence read TX_STA_FIFO
2064 * at most X times and also stop processing once the TX_STA_FIFO_VALID
2065 * flag is not set anymore.
2066 *
2067 * The legacy drivers use X=TX_RING_SIZE but state in a comment
2068 * that the TX_STA_FIFO stack has a size of 16. We stick to our
2069 * tx ring size for now.
95ea3627 2070 */
e6474c3c 2071 for (i = 0; i < TX_ENTRIES; i++) {
95ea3627
ID		 2072 rt2x00pci_register_read(rt2x00dev, STA_CSR4, &reg);
2073 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
2074 break;
2075
95ea3627
ID		 2076 /*
2077 * Skip this entry when it contains an invalid
181d6902 2078 * queue identication number.
95ea3627
ID		 2079 */
2080 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
181d6902
ID		 2081 queue = rt2x00queue_get_queue(rt2x00dev, type);
2082 if (unlikely(!queue))
95ea3627
ID		 2083 continue;
2084
2085 /*
2086 * Skip this entry when it contains an invalid
2087 * index number.
2088 */
2089 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
181d6902 2090 if (unlikely(index >= queue->limit))
95ea3627
ID		 2091 continue;
2092
181d6902 2093 entry = &queue->entries[index];
b8be63ff
ID		 2094 entry_priv = entry->priv_data;
2095 rt2x00_desc_read(entry_priv->desc, 0, &word);
95ea3627
ID		 2096
2097 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
2098 !rt2x00_get_field32(word, TXD_W0_VALID))
2099 return;
2100
181d6902 2101 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
62bc060b 2102 while (entry != entry_done) {
181d6902
ID		 2103 /* Catch up.
2104 * Just report any entries we missed as failed.
2105 */
62bc060b 2106 WARNING(rt2x00dev,
181d6902
ID		 2107 "TX status report missed for entry %d\n",
2108 entry_done->entry_idx);
2109
fb55f4d1
ID		 2110 txdesc.flags = 0;
2111 __set_bit(TXDONE_UNKNOWN, &txdesc.flags);
181d6902
ID		 2112 txdesc.retry = 0;
2113
e513a0b6 2114 rt2x00lib_txdone(entry_done, &txdesc);
181d6902 2115 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
62bc060b
MN		 2116 }
2117
95ea3627
ID		 2118 /*
2119 * Obtain the status about this packet.
2120 */
fb55f4d1
ID		 2121 txdesc.flags = 0;
2122 switch (rt2x00_get_field32(reg, STA_CSR4_TX_RESULT)) {
2123 case 0: /* Success, maybe with retry */
2124 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
2125 break;
2126 case 6: /* Failure, excessive retries */
2127 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
2128 /* Don't break, this is a failed frame! */
2129 default: /* Failure */
2130 __set_bit(TXDONE_FAILURE, &txdesc.flags);
2131 }
181d6902 2132 txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
95ea3627 2133
e1b4d7b7
ID		 2134 /*
2135 * the frame was retried at least once
2136 * -> hw used fallback rates
2137 */
2138 if (txdesc.retry)
2139 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
2140
e513a0b6 2141 rt2x00lib_txdone(entry, &txdesc);
95ea3627
ID		 2142 }
2143}
2144
9e189446
GW		 2145static void rt61pci_wakeup(struct rt2x00_dev *rt2x00dev)
2146{
2147 struct ieee80211_conf conf = { .flags = 0 };
2148 struct rt2x00lib_conf libconf = { .conf = &conf };
2149
2150 rt61pci_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
2151}
2152
78e256c9 2153static irqreturn_t rt61pci_interrupt_thread(int irq, void *dev_instance)
95ea3627
ID		 2154{
2155 struct rt2x00_dev *rt2x00dev = dev_instance;
78e256c9
HS		 2156 u32 reg = rt2x00dev->irqvalue[0];
2157 u32 reg_mcu = rt2x00dev->irqvalue[1];
95ea3627
ID		 2158
2159 /*
2160 * Handle interrupts, walk through all bits
2161 * and run the tasks, the bits are checked in order of
2162 * priority.
2163 */
2164
2165 /*
2166 * 1 - Rx ring done interrupt.
2167 */
2168 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
2169 rt2x00pci_rxdone(rt2x00dev);
2170
2171 /*
2172 * 2 - Tx ring done interrupt.
2173 */
2174 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
2175 rt61pci_txdone(rt2x00dev);
2176
2177 /*
2178 * 3 - Handle MCU command done.
2179 */
2180 if (reg_mcu)
2181 rt2x00pci_register_write(rt2x00dev,
2182 M2H_CMD_DONE_CSR, 0xffffffff);
2183
9e189446
GW		 2184 /*
2185 * 4 - MCU Autowakeup interrupt.
2186 */
2187 if (rt2x00_get_field32(reg_mcu, MCU_INT_SOURCE_CSR_TWAKEUP))
2188 rt61pci_wakeup(rt2x00dev);
2189
fa43750f
HS		 2190 /*
2191 * 5 - Beacon done interrupt.
2192 */
2193 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_BEACON_DONE))
2194 rt2x00lib_beacondone(rt2x00dev);
2195
78e256c9
HS		 2196 /* Enable interrupts again. */
2197 rt2x00dev->ops->lib->set_device_state(rt2x00dev,
2198 STATE_RADIO_IRQ_ON_ISR);
95ea3627
ID		 2199 return IRQ_HANDLED;
2200}
2201
78e256c9
HS		 2202
2203static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
2204{
2205 struct rt2x00_dev *rt2x00dev = dev_instance;
2206 u32 reg_mcu;
2207 u32 reg;
2208
2209 /*
2210 * Get the interrupt sources & saved to local variable.
2211 * Write register value back to clear pending interrupts.
2212 */
2213 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg_mcu);
2214 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
2215
2216 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
2217 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
2218
2219 if (!reg && !reg_mcu)
2220 return IRQ_NONE;
2221
2222 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2223 return IRQ_HANDLED;
2224
2225 /* Store irqvalues for use in the interrupt thread. */
2226 rt2x00dev->irqvalue[0] = reg;
2227 rt2x00dev->irqvalue[1] = reg_mcu;
2228
2229 /* Disable interrupts, will be enabled again in the interrupt thread. */
2230 rt2x00dev->ops->lib->set_device_state(rt2x00dev,
2231 STATE_RADIO_IRQ_OFF_ISR);
2232 return IRQ_WAKE_THREAD;
2233}
2234
95ea3627
ID		 2235/*
2236 * Device probe functions.
2237 */
2238static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2239{
2240 struct eeprom_93cx6 eeprom;
2241 u32 reg;
2242 u16 word;
2243 u8 *mac;
2244 s8 value;
2245
2246 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
2247
2248 eeprom.data = rt2x00dev;
2249 eeprom.register_read = rt61pci_eepromregister_read;
2250 eeprom.register_write = rt61pci_eepromregister_write;
2251 eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
2252 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
2253 eeprom.reg_data_in = 0;
2254 eeprom.reg_data_out = 0;
2255 eeprom.reg_data_clock = 0;
2256 eeprom.reg_chip_select = 0;
2257
2258 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
2259 EEPROM_SIZE / sizeof(u16));
2260
2261 /*
2262 * Start validation of the data that has been read.
2263 */
2264 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2265 if (!is_valid_ether_addr(mac)) {
2266 random_ether_addr(mac);
e174961c 2267 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
95ea3627
ID		 2268 }
2269
2270 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2271 if (word == 0xffff) {
2272 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
362f3b6b
ID		 2273 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
2274 ANTENNA_B);
2275 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
2276 ANTENNA_B);
95ea3627
ID		 2277 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
2278 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
2279 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
2280 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
2281 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2282 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2283 }
2284
2285 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2286 if (word == 0xffff) {
2287 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
2288 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
91581b62
ID		 2289 rt2x00_set_field16(&word, EEPROM_NIC_RX_FIXED, 0);
2290 rt2x00_set_field16(&word, EEPROM_NIC_TX_FIXED, 0);
95ea3627
ID		 2291 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2292 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2293 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2294 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2295 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2296 }
2297
2298 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
2299 if (word == 0xffff) {
2300 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
2301 LED_MODE_DEFAULT);
2302 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
2303 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
2304 }
2305
2306 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2307 if (word == 0xffff) {
2308 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2309 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
2310 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2311 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2312 }
2313
2314 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
2315 if (word == 0xffff) {
2316 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2317 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2318 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2319 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
2320 } else {
2321 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
2322 if (value < -10 || value > 10)
2323 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2324 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
2325 if (value < -10 || value > 10)
2326 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2327 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2328 }
2329
2330 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
2331 if (word == 0xffff) {
2332 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2333 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2334 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
417f412f 2335 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
95ea3627
ID		 2336 } else {
2337 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
2338 if (value < -10 || value > 10)
2339 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2340 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
2341 if (value < -10 || value > 10)
2342 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2343 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2344 }
2345
2346 return 0;
2347}
2348
2349static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2350{
2351 u32 reg;
2352 u16 value;
2353 u16 eeprom;
95ea3627
ID		 2354
2355 /*
2356 * Read EEPROM word for configuration.
2357 */
2358 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2359
2360 /*
2361 * Identify RF chipset.
95ea3627 2362 */
95ea3627
ID		 2363 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2364 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
49e721ec
GW		 2365 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
2366 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
95ea3627 2367
5122d898
GW		 2368 if (!rt2x00_rf(rt2x00dev, RF5225) &&
2369 !rt2x00_rf(rt2x00dev, RF5325) &&
2370 !rt2x00_rf(rt2x00dev, RF2527) &&
2371 !rt2x00_rf(rt2x00dev, RF2529)) {
95ea3627
ID		 2372 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2373 return -ENODEV;
2374 }
2375
e4cd2ff8 2376 /*
49513481 2377 * Determine number of antennas.
e4cd2ff8
ID		 2378 */
2379 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
2380 __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags);
2381
95ea3627
ID		 2382 /*
2383 * Identify default antenna configuration.
2384 */
addc81bd 2385 rt2x00dev->default_ant.tx =
95ea3627 2386 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 2387 rt2x00dev->default_ant.rx =
95ea3627
ID		 2388 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
2389
2390 /*
2391 * Read the Frame type.
2392 */
2393 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
2394 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
2395
95ea3627 2396 /*
b34e620f 2397 * Detect if this device has a hardware controlled radio.
95ea3627
ID		 2398 */
2399 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
066cb637 2400 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
95ea3627
ID		 2401
2402 /*
2403 * Read frequency offset and RF programming sequence.
2404 */
2405 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2406 if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
2407 __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags);
2408
2409 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2410
2411 /*
2412 * Read external LNA informations.
2413 */
2414 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2415
2416 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2417 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2418 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2419 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2420
e4cd2ff8 2421 /*
b34e620f 2422 * When working with a RF2529 chip without double antenna,
e4cd2ff8
ID		 2423 * the antenna settings should be gathered from the NIC
2424 * eeprom word.
2425 */
5122d898 2426 if (rt2x00_rf(rt2x00dev, RF2529) &&
e4cd2ff8 2427 !test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) {
91581b62
ID		 2428 rt2x00dev->default_ant.rx =
2429 ANTENNA_A + rt2x00_get_field16(eeprom, EEPROM_NIC_RX_FIXED);
2430 rt2x00dev->default_ant.tx =
2431 ANTENNA_B - rt2x00_get_field16(eeprom, EEPROM_NIC_TX_FIXED);
e4cd2ff8
ID		 2432
2433 if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY))
2434 rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY;
2435 if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY))
2436 rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY;
2437 }
2438
95ea3627
ID		 2439 /*
2440 * Store led settings, for correct led behaviour.
2441 * If the eeprom value is invalid,
2442 * switch to default led mode.
2443 */
771fd565 2444#ifdef CONFIG_RT2X00_LIB_LEDS
95ea3627 2445 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
a9450b70
ID		 2446 value = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
2447
475433be
ID		 2448 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2449 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2450 if (value == LED_MODE_SIGNAL_STRENGTH)
2451 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
2452 LED_TYPE_QUALITY);
95ea3627 2453
a9450b70
ID		 2454 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
2455 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
95ea3627
ID		 2456 rt2x00_get_field16(eeprom,
2457 EEPROM_LED_POLARITY_GPIO_0));
a9450b70 2458 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
95ea3627
ID		 2459 rt2x00_get_field16(eeprom,
2460 EEPROM_LED_POLARITY_GPIO_1));
a9450b70 2461 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
95ea3627
ID		 2462 rt2x00_get_field16(eeprom,
2463 EEPROM_LED_POLARITY_GPIO_2));
a9450b70 2464 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
95ea3627
ID		 2465 rt2x00_get_field16(eeprom,
2466 EEPROM_LED_POLARITY_GPIO_3));
a9450b70 2467 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
95ea3627
ID		 2468 rt2x00_get_field16(eeprom,
2469 EEPROM_LED_POLARITY_GPIO_4));
a9450b70 2470 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
95ea3627 2471 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
a9450b70 2472 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
95ea3627
ID		 2473 rt2x00_get_field16(eeprom,
2474 EEPROM_LED_POLARITY_RDY_G));
a9450b70 2475 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
95ea3627
ID		 2476 rt2x00_get_field16(eeprom,
2477 EEPROM_LED_POLARITY_RDY_A));
771fd565 2478#endif /* CONFIG_RT2X00_LIB_LEDS */
95ea3627
ID		 2479
2480 return 0;
2481}
2482
2483/*
2484 * RF value list for RF5225 & RF5325
2485 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2486 */
2487static const struct rf_channel rf_vals_noseq[] = {
2488 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2489 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2490 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2491 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2492 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2493 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2494 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2495 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2496 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2497 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2498 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2499 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2500 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2501 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2502
2503 /* 802.11 UNI / HyperLan 2 */
2504 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2505 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2506 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2507 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2508 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2509 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2510 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2511 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2512
2513 /* 802.11 HyperLan 2 */
2514 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2515 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2516 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2517 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2518 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2519 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2520 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2521 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2522 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2523 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2524
2525 /* 802.11 UNII */
2526 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2527 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2528 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2529 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2530 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2531 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2532
2533 /* MMAC(Japan)J52 ch 34,38,42,46 */
2534 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2535 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2536 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2537 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2538};
2539
2540/*
2541 * RF value list for RF5225 & RF5325
2542 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2543 */
2544static const struct rf_channel rf_vals_seq[] = {
2545 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2546 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2547 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2548 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2549 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2550 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2551 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2552 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2553 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2554 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2555 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2556 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2557 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2558 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2559
2560 /* 802.11 UNI / HyperLan 2 */
2561 { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2562 { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2563 { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2564 { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2565 { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2566 { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2567 { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2568 { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2569
2570 /* 802.11 HyperLan 2 */
2571 { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2572 { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2573 { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2574 { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2575 { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2576 { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2577 { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2578 { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2579 { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2580 { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2581
2582 /* 802.11 UNII */
2583 { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2584 { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2585 { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2586 { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2587 { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2588 { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2589
2590 /* MMAC(Japan)J52 ch 34,38,42,46 */
2591 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2592 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2593 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2594 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2595};
2596
8c5e7a5f 2597static int rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 2598{
2599 struct hw_mode_spec *spec = &rt2x00dev->spec;
8c5e7a5f
ID		 2600 struct channel_info *info;
2601 char *tx_power;
95ea3627
ID		 2602 unsigned int i;
2603
93b6bd26
GW		 2604 /*
2605 * Disable powersaving as default.
2606 */
2607 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2608
95ea3627
ID		 2609 /*
2610 * Initialize all hw fields.
2611 */
2612 rt2x00dev->hw->flags =
566bfe5a 2613 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
4be8c387
JB		 2614 IEEE80211_HW_SIGNAL_DBM |
2615 IEEE80211_HW_SUPPORTS_PS |
2616 IEEE80211_HW_PS_NULLFUNC_STACK;
95ea3627 2617
14a3bf89 2618 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
95ea3627
ID		 2619 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2620 rt2x00_eeprom_addr(rt2x00dev,
2621 EEPROM_MAC_ADDR_0));
2622
95ea3627 2623 /*
e1b4d7b7
ID		 2624 * As rt61 has a global fallback table we cannot specify
2625 * more then one tx rate per frame but since the hw will
2626 * try several rates (based on the fallback table) we should
2627 * still initialize max_rates to the maximum number of rates
2628 * we are going to try. Otherwise mac80211 will truncate our
2629 * reported tx rates and the rc algortihm will end up with
2630 * incorrect data.
2631 */
2632 rt2x00dev->hw->max_rates = 7;
2633 rt2x00dev->hw->max_rate_tries = 1;
2634
2635 /*
95ea3627
ID		 2636 * Initialize hw_mode information.
2637 */
31562e80
ID		 2638 spec->supported_bands = SUPPORT_BAND_2GHZ;
2639 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
95ea3627
ID		 2640
2641 if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
2642 spec->num_channels = 14;
2643 spec->channels = rf_vals_noseq;
2644 } else {
2645 spec->num_channels = 14;
2646 spec->channels = rf_vals_seq;
2647 }
2648
5122d898 2649 if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325)) {
31562e80 2650 spec->supported_bands |= SUPPORT_BAND_5GHZ;
95ea3627 2651 spec->num_channels = ARRAY_SIZE(rf_vals_seq);
8c5e7a5f
ID		 2652 }
2653
2654 /*
2655 * Create channel information array
2656 */
baeb2ffa 2657 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
8c5e7a5f
ID		 2658 if (!info)
2659 return -ENOMEM;
2660
2661 spec->channels_info = info;
95ea3627 2662
8c5e7a5f
ID		 2663 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2664 for (i = 0; i < 14; i++)
2665 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
95ea3627 2666
8c5e7a5f
ID		 2667 if (spec->num_channels > 14) {
2668 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2669 for (i = 14; i < spec->num_channels; i++)
2670 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
95ea3627 2671 }
8c5e7a5f
ID		 2672
2673 return 0;
95ea3627
ID		 2674}
2675
2676static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2677{
2678 int retval;
2679
117839bd
PR		 2680 /*
2681 * Disable power saving.
2682 */
2683 rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000007);
2684
95ea3627
ID		 2685 /*
2686 * Allocate eeprom data.
2687 */
2688 retval = rt61pci_validate_eeprom(rt2x00dev);
2689 if (retval)
2690 return retval;
2691
2692 retval = rt61pci_init_eeprom(rt2x00dev);
2693 if (retval)
2694 return retval;
2695
2696 /*
2697 * Initialize hw specifications.
2698 */
8c5e7a5f
ID		 2699 retval = rt61pci_probe_hw_mode(rt2x00dev);
2700 if (retval)
2701 return retval;
95ea3627 2702
1afcfd54
IP		 2703 /*
2704 * This device has multiple filters for control frames,
2705 * but has no a separate filter for PS Poll frames.
2706 */
2707 __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
2708
95ea3627 2709 /*
c4da0048 2710 * This device requires firmware and DMA mapped skbs.
95ea3627 2711 */
066cb637 2712 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
c4da0048 2713 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
008c4482
ID		 2714 if (!modparam_nohwcrypt)
2715 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
27df2a9c 2716 __set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags);
95ea3627
ID		 2717
2718 /*
2719 * Set the rssi offset.
2720 */
2721 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2722
2723 return 0;
2724}
2725
2726/*
2727 * IEEE80211 stack callback functions.
2728 */
2af0a570
ID		 2729static int rt61pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2730 const struct ieee80211_tx_queue_params *params)
2731{
2732 struct rt2x00_dev *rt2x00dev = hw->priv;
2733 struct data_queue *queue;
2734 struct rt2x00_field32 field;
2735 int retval;
2736 u32 reg;
5e790023 2737 u32 offset;
2af0a570
ID		 2738
2739 /*
2740 * First pass the configuration through rt2x00lib, that will
2741 * update the queue settings and validate the input. After that
2742 * we are free to update the registers based on the value
2743 * in the queue parameter.
2744 */
2745 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2746 if (retval)
2747 return retval;
2748
5e790023
ID		 2749 /*
2750 * We only need to perform additional register initialization
b34e620f 2751 * for WMM queues.
5e790023
ID		 2752 */
2753 if (queue_idx >= 4)
2754 return 0;
2755
2af0a570
ID		 2756 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2757
2758 /* Update WMM TXOP register */
5e790023
ID		 2759 offset = AC_TXOP_CSR0 + (sizeof(u32) * (!!(queue_idx & 2)));
2760 field.bit_offset = (queue_idx & 1) * 16;
2761 field.bit_mask = 0xffff << field.bit_offset;
2762
2763 rt2x00pci_register_read(rt2x00dev, offset, &reg);
2764 rt2x00_set_field32(&reg, field, queue->txop);
2765 rt2x00pci_register_write(rt2x00dev, offset, reg);
2af0a570
ID		 2766
2767 /* Update WMM registers */
2768 field.bit_offset = queue_idx * 4;
2769 field.bit_mask = 0xf << field.bit_offset;
2770
2771 rt2x00pci_register_read(rt2x00dev, AIFSN_CSR, &reg);
2772 rt2x00_set_field32(&reg, field, queue->aifs);
2773 rt2x00pci_register_write(rt2x00dev, AIFSN_CSR, reg);
2774
2775 rt2x00pci_register_read(rt2x00dev, CWMIN_CSR, &reg);
2776 rt2x00_set_field32(&reg, field, queue->cw_min);
2777 rt2x00pci_register_write(rt2x00dev, CWMIN_CSR, reg);
2778
2779 rt2x00pci_register_read(rt2x00dev, CWMAX_CSR, &reg);
2780 rt2x00_set_field32(&reg, field, queue->cw_max);
2781 rt2x00pci_register_write(rt2x00dev, CWMAX_CSR, reg);
2782
2783 return 0;
2784}
2785
95ea3627
ID		 2786static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
2787{
2788 struct rt2x00_dev *rt2x00dev = hw->priv;
2789 u64 tsf;
2790 u32 reg;
2791
2792 rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, &reg);
2793 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2794 rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, &reg);
2795 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2796
2797 return tsf;
2798}
2799
95ea3627
ID		 2800static const struct ieee80211_ops rt61pci_mac80211_ops = {
2801 .tx = rt2x00mac_tx,
4150c572
JB		 2802 .start = rt2x00mac_start,
2803 .stop = rt2x00mac_stop,
95ea3627
ID		 2804 .add_interface = rt2x00mac_add_interface,
2805 .remove_interface = rt2x00mac_remove_interface,
2806 .config = rt2x00mac_config,
3a643d24 2807 .configure_filter = rt2x00mac_configure_filter,
61e754f4 2808 .set_key = rt2x00mac_set_key,
d8147f9d
ID		 2809 .sw_scan_start = rt2x00mac_sw_scan_start,
2810 .sw_scan_complete = rt2x00mac_sw_scan_complete,
95ea3627 2811 .get_stats = rt2x00mac_get_stats,
471b3efd 2812 .bss_info_changed = rt2x00mac_bss_info_changed,
2af0a570 2813 .conf_tx = rt61pci_conf_tx,
95ea3627 2814 .get_tsf = rt61pci_get_tsf,
e47a5cdd 2815 .rfkill_poll = rt2x00mac_rfkill_poll,
95ea3627
ID		 2816};
2817
2818static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2819 .irq_handler = rt61pci_interrupt,
78e256c9 2820 .irq_handler_thread = rt61pci_interrupt_thread,
95ea3627
ID		 2821 .probe_hw = rt61pci_probe_hw,
2822 .get_firmware_name = rt61pci_get_firmware_name,
0cbe0064 2823 .check_firmware = rt61pci_check_firmware,
95ea3627
ID		 2824 .load_firmware = rt61pci_load_firmware,
2825 .initialize = rt2x00pci_initialize,
2826 .uninitialize = rt2x00pci_uninitialize,
798b7adb
ID		 2827 .get_entry_state = rt61pci_get_entry_state,
2828 .clear_entry = rt61pci_clear_entry,
95ea3627 2829 .set_device_state = rt61pci_set_device_state,
95ea3627 2830 .rfkill_poll = rt61pci_rfkill_poll,
95ea3627
ID		 2831 .link_stats = rt61pci_link_stats,
2832 .reset_tuner = rt61pci_reset_tuner,
2833 .link_tuner = rt61pci_link_tuner,
2834 .write_tx_desc = rt61pci_write_tx_desc,
bd88a781 2835 .write_beacon = rt61pci_write_beacon,
95ea3627 2836 .kick_tx_queue = rt61pci_kick_tx_queue,
a2c9b652 2837 .kill_tx_queue = rt61pci_kill_tx_queue,
95ea3627 2838 .fill_rxdone = rt61pci_fill_rxdone,
61e754f4
ID		 2839 .config_shared_key = rt61pci_config_shared_key,
2840 .config_pairwise_key = rt61pci_config_pairwise_key,
3a643d24 2841 .config_filter = rt61pci_config_filter,
6bb40dd1 2842 .config_intf = rt61pci_config_intf,
72810379 2843 .config_erp = rt61pci_config_erp,
e4ea1c40 2844 .config_ant = rt61pci_config_ant,
95ea3627
ID		 2845 .config = rt61pci_config,
2846};
2847
181d6902
ID		 2848static const struct data_queue_desc rt61pci_queue_rx = {
2849 .entry_num = RX_ENTRIES,
2850 .data_size = DATA_FRAME_SIZE,
2851 .desc_size = RXD_DESC_SIZE,
b8be63ff 2852 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 2853};
2854
2855static const struct data_queue_desc rt61pci_queue_tx = {
2856 .entry_num = TX_ENTRIES,
2857 .data_size = DATA_FRAME_SIZE,
2858 .desc_size = TXD_DESC_SIZE,
b8be63ff 2859 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 2860};
2861
2862static const struct data_queue_desc rt61pci_queue_bcn = {
6bb40dd1 2863 .entry_num = 4 * BEACON_ENTRIES,
78720897 2864 .data_size = 0, /* No DMA required for beacons */
181d6902 2865 .desc_size = TXINFO_SIZE,
b8be63ff 2866 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 2867};
2868
95ea3627 2869static const struct rt2x00_ops rt61pci_ops = {
04d0362e
GW		 2870 .name = KBUILD_MODNAME,
2871 .max_sta_intf = 1,
2872 .max_ap_intf = 4,
2873 .eeprom_size = EEPROM_SIZE,
2874 .rf_size = RF_SIZE,
2875 .tx_queues = NUM_TX_QUEUES,
e6218cc4 2876 .extra_tx_headroom = 0,
04d0362e
GW		 2877 .rx = &rt61pci_queue_rx,
2878 .tx = &rt61pci_queue_tx,
2879 .bcn = &rt61pci_queue_bcn,
2880 .lib = &rt61pci_rt2x00_ops,
2881 .hw = &rt61pci_mac80211_ops,
95ea3627 2882#ifdef CONFIG_RT2X00_LIB_DEBUGFS
04d0362e 2883 .debugfs = &rt61pci_rt2x00debug,
95ea3627
ID		 2884#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2885};
2886
2887/*
2888 * RT61pci module information.
2889 */
a3aa1884 2890static DEFINE_PCI_DEVICE_TABLE(rt61pci_device_table) = {
95ea3627
ID		 2891 /* RT2561s */
2892 { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) },
2893 /* RT2561 v2 */
2894 { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) },
2895 /* RT2661 */
2896 { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) },
2897 { 0, }
2898};
2899
2900MODULE_AUTHOR(DRV_PROJECT);
2901MODULE_VERSION(DRV_VERSION);
2902MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
2903MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
2904 "PCI & PCMCIA chipset based cards");
2905MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
2906MODULE_FIRMWARE(FIRMWARE_RT2561);
2907MODULE_FIRMWARE(FIRMWARE_RT2561s);
2908MODULE_FIRMWARE(FIRMWARE_RT2661);
2909MODULE_LICENSE("GPL");
2910
2911static struct pci_driver rt61pci_driver = {
2360157c 2912 .name = KBUILD_MODNAME,
95ea3627
ID		 2913 .id_table = rt61pci_device_table,
2914 .probe = rt2x00pci_probe,
2915 .remove = __devexit_p(rt2x00pci_remove),
2916 .suspend = rt2x00pci_suspend,
2917 .resume = rt2x00pci_resume,
2918};
2919
2920static int __init rt61pci_init(void)
2921{
2922 return pci_register_driver(&rt61pci_driver);
2923}
2924
2925static void __exit rt61pci_exit(void)
2926{
2927 pci_unregister_driver(&rt61pci_driver);
2928}
2929
2930module_init(rt61pci_init);
2931module_exit(rt61pci_exit);
Linux kernel - Deliverables
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