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rtl8180: add rtl8187se HW initialization
[deliverable/linux.git] / drivers / net / wireless / rtl818x / rtl8180 / dev.c
CommitLineData
f6532111
MW		 1
2/*
3 * Linux device driver for RTL8180 / RTL8185
4 *
5 * Copyright 2007 Michael Wu <flamingice@sourmilk.net>
93ba2a85 6 * Copyright 2007 Andrea Merello <andrea.merello@gmail.com>
f6532111
MW		 7 *
8 * Based on the r8180 driver, which is:
93ba2a85 9 * Copyright 2004-2005 Andrea Merello <andrea.merello@gmail.com>, et al.
f6532111
MW		 10 *
11 * Thanks to Realtek for their support!
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
a6b7a407 18#include <linux/interrupt.h>
f6532111 19#include <linux/pci.h>
5a0e3ad6 20#include <linux/slab.h>
f6532111
MW		 21#include <linux/delay.h>
22#include <linux/etherdevice.h>
23#include <linux/eeprom_93cx6.h>
9d9779e7 24#include <linux/module.h>
f6532111
MW		 25#include <net/mac80211.h>
26
27#include "rtl8180.h"
3cfeb0c3
JL		 28#include "rtl8225.h"
29#include "sa2400.h"
30#include "max2820.h"
31#include "grf5101.h"
711d4ed3 32#include "rtl8225se.h"
f6532111
MW		 33
34MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
93ba2a85 35MODULE_AUTHOR("Andrea Merello <andrea.merello@gmail.com>");
f6532111
MW		 36MODULE_DESCRIPTION("RTL8180 / RTL8185 PCI wireless driver");
37MODULE_LICENSE("GPL");
38
a3aa1884 39static DEFINE_PCI_DEVICE_TABLE(rtl8180_table) = {
f6532111
MW		 40 /* rtl8185 */
41 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8185) },
4fcc5470 42 { PCI_DEVICE(PCI_VENDOR_ID_BELKIN, 0x700f) },
f6532111
MW		 43 { PCI_DEVICE(PCI_VENDOR_ID_BELKIN, 0x701f) },
44
45 /* rtl8180 */
46 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8180) },
47 { PCI_DEVICE(0x1799, 0x6001) },
48 { PCI_DEVICE(0x1799, 0x6020) },
49 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x3300) },
29a6b508
XVP		 50 { PCI_DEVICE(0x1186, 0x3301) },
51 { PCI_DEVICE(0x1432, 0x7106) },
f6532111
MW		 52 { }
53};
54
55MODULE_DEVICE_TABLE(pci, rtl8180_table);
56
8318d78a
JB		 57static const struct ieee80211_rate rtl818x_rates[] = {
58 { .bitrate = 10, .hw_value = 0, },
59 { .bitrate = 20, .hw_value = 1, },
60 { .bitrate = 55, .hw_value = 2, },
61 { .bitrate = 110, .hw_value = 3, },
62 { .bitrate = 60, .hw_value = 4, },
63 { .bitrate = 90, .hw_value = 5, },
64 { .bitrate = 120, .hw_value = 6, },
65 { .bitrate = 180, .hw_value = 7, },
66 { .bitrate = 240, .hw_value = 8, },
67 { .bitrate = 360, .hw_value = 9, },
68 { .bitrate = 480, .hw_value = 10, },
69 { .bitrate = 540, .hw_value = 11, },
70};
71
72static const struct ieee80211_channel rtl818x_channels[] = {
73 { .center_freq = 2412 },
74 { .center_freq = 2417 },
75 { .center_freq = 2422 },
76 { .center_freq = 2427 },
77 { .center_freq = 2432 },
78 { .center_freq = 2437 },
79 { .center_freq = 2442 },
80 { .center_freq = 2447 },
81 { .center_freq = 2452 },
82 { .center_freq = 2457 },
83 { .center_freq = 2462 },
84 { .center_freq = 2467 },
85 { .center_freq = 2472 },
86 { .center_freq = 2484 },
87};
88
3ee44d60
AM		 89/* Queues for rtl8187se card
90 *
91 * name | reg | queue
92 * BC | 7 | 6
93 * MG | 1 | 0
94 * HI | 6 | 1
95 * VO | 5 | 2
96 * VI | 4 | 3
97 * BE | 3 | 4
98 * BK | 2 | 5
99 *
100 * The complete map for DMA kick reg using use all queue is:
101 * static const int rtl8187se_queues_map[RTL8187SE_NR_TX_QUEUES] =
102 * {1, 6, 5, 4, 3, 2, 7};
103 *
104 * .. but.. Because for mac80211 4 queues are enough for QoS we use this
105 *
106 * name | reg | queue
107 * BC | 7 | 4 <- currently not used yet
108 * MG | 1 | x <- Not used
109 * HI | 6 | x <- Not used
110 * VO | 5 | 0 <- used
111 * VI | 4 | 1 <- used
112 * BE | 3 | 2 <- used
113 * BK | 2 | 3 <- used
114 *
115 * Beacon queue could be used, but this is not finished yet.
116 *
117 * I thougth about using the other two queues but I decided not to do this:
118 *
119 * - I'm unsure whether the mac80211 will ever try to use more than 4 queues
120 * by itself.
121 *
122 * - I could route MGMT frames (currently sent over VO queue) to the MGMT
123 * queue but since mac80211 will do not know about it, I will probably gain
124 * some HW priority whenever the VO queue is not empty, but this gain is
125 * limited by the fact that I had to stop the mac80211 queue whenever one of
126 * the VO or MGMT queues is full, stopping also submitting of MGMT frame
127 * to the driver.
128 *
129 * - I don't know how to set in the HW the contention window params for MGMT
130 * and HI-prio queues.
131 */
132
133static const int rtl8187se_queues_map[RTL8187SE_NR_TX_QUEUES] = {5, 4, 3, 2, 7};
134
fd6564fc
AM		 135/* Queues for rtl8180/rtl8185 cards
136 *
137 * name | reg | prio
138 * BC | 7 | 3
139 * HI | 6 | 0
140 * NO | 5 | 1
141 * LO | 4 | 2
142 *
143 * The complete map for DMA kick reg using all queue is:
144 * static const int rtl8180_queues_map[RTL8180_NR_TX_QUEUES] = {6, 5, 4, 7};
145 *
146 * .. but .. Because the mac80211 needs at least 4 queues for QoS or
147 * otherwise QoS can't be done, we use just one.
148 * Beacon queue could be used, but this is not finished yet.
149 * Actual map is:
150 *
151 * name | reg | prio
152 * BC | 7 | 1 <- currently not used yet.
153 * HI | 6 | x <- not used
154 * NO | 5 | x <- not used
155 * LO | 4 | 0 <- used
156 */
157
158static const int rtl8180_queues_map[RTL8180_NR_TX_QUEUES] = {4, 7};
8318d78a 159
f6532111
MW		 160void rtl8180_write_phy(struct ieee80211_hw *dev, u8 addr, u32 data)
161{
162 struct rtl8180_priv *priv = dev->priv;
163 int i = 10;
164 u32 buf;
165
166 buf = (data << 8) | addr;
167
168 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->PHY[0], buf | 0x80);
169 while (i--) {
170 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->PHY[0], buf);
171 if (rtl818x_ioread8(priv, &priv->map->PHY[2]) == (data & 0xFF))
172 return;
173 }
174}
175
a6d27d2a 176static void rtl8180_handle_rx(struct ieee80211_hw *dev)
f6532111
MW		 177{
178 struct rtl8180_priv *priv = dev->priv;
21025920 179 struct rtl818x_rx_cmd_desc *cmd_desc;
a6d27d2a 180 unsigned int count = 32;
8b73fb8e 181 u8 signal, agc, sq;
2b4db05e 182 dma_addr_t mapping;
f6532111 183
a6d27d2a 184 while (count--) {
21025920 185 void *entry = priv->rx_ring + priv->rx_idx * priv->rx_ring_sz;
f6532111 186 struct sk_buff *skb = priv->rx_buf[priv->rx_idx];
21025920
AM		 187 u32 flags, flags2;
188 u64 tsft;
189
190 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
191 struct rtl8187se_rx_desc *desc = entry;
192
193 flags = le32_to_cpu(desc->flags);
194 flags2 = le32_to_cpu(desc->flags2);
195 tsft = le64_to_cpu(desc->tsft);
196 } else {
197 struct rtl8180_rx_desc *desc = entry;
198
199 flags = le32_to_cpu(desc->flags);
200 flags2 = le32_to_cpu(desc->flags2);
201 tsft = le64_to_cpu(desc->tsft);
202 }
f6532111 203
38e3b0d8 204 if (flags & RTL818X_RX_DESC_FLAG_OWN)
a6d27d2a 205 return;
f6532111 206
38e3b0d8
HRK		 207 if (unlikely(flags & (RTL818X_RX_DESC_FLAG_DMA_FAIL |
208 RTL818X_RX_DESC_FLAG_FOF |
209 RTL818X_RX_DESC_FLAG_RX_ERR)))
f6532111
MW		 210 goto done;
211 else {
f6532111
MW		 212 struct ieee80211_rx_status rx_status = {0};
213 struct sk_buff *new_skb = dev_alloc_skb(MAX_RX_SIZE);
214
215 if (unlikely(!new_skb))
216 goto done;
217
2b4db05e 218 mapping = pci_map_single(priv->pdev,
219 skb_tail_pointer(new_skb),
220 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
221
222 if (pci_dma_mapping_error(priv->pdev, mapping)) {
223 kfree_skb(new_skb);
224 dev_err(&priv->pdev->dev, "RX DMA map error\n");
225
226 goto done;
227 }
228
f6532111
MW		 229 pci_unmap_single(priv->pdev,
230 *((dma_addr_t *)skb->cb),
231 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
232 skb_put(skb, flags & 0xFFF);
233
234 rx_status.antenna = (flags2 >> 15) & 1;
8318d78a 235 rx_status.rate_idx = (flags >> 20) & 0xF;
8b73fb8e 236 agc = (flags2 >> 17) & 0x7F;
6caefd12
AM		 237
238 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8185) {
8b73fb8e
JL		 239 if (rx_status.rate_idx > 3)
240 signal = 90 - clamp_t(u8, agc, 25, 90);
241 else
242 signal = 95 - clamp_t(u8, agc, 30, 95);
21025920
AM		 243 } else if (priv->chip_family ==
244 RTL818X_CHIP_FAMILY_RTL8180) {
8b73fb8e
JL		 245 sq = flags2 & 0xff;
246 signal = priv->rf->calc_rssi(agc, sq);
21025920
AM		 247 } else {
248 /* TODO: rtl8187se rssi */
249 signal = 10;
8b73fb8e 250 }
8b74964c 251 rx_status.signal = signal;
675a0b04
KB		 252 rx_status.freq = dev->conf.chandef.chan->center_freq;
253 rx_status.band = dev->conf.chandef.chan->band;
21025920 254 rx_status.mactime = tsft;
f4bda337 255 rx_status.flag |= RX_FLAG_MACTIME_START;
38e3b0d8 256 if (flags & RTL818X_RX_DESC_FLAG_CRC32_ERR)
f6532111
MW		 257 rx_status.flag |= RX_FLAG_FAILED_FCS_CRC;
258
f1d58c25 259 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
a6d27d2a 260 ieee80211_rx_irqsafe(dev, skb);
f6532111
MW		 261
262 skb = new_skb;
263 priv->rx_buf[priv->rx_idx] = skb;
2b4db05e 264 *((dma_addr_t *) skb->cb) = mapping;
f6532111
MW		 265 }
266
267 done:
21025920
AM		 268 cmd_desc = entry;
269 cmd_desc->rx_buf = cpu_to_le32(*((dma_addr_t *)skb->cb));
270 cmd_desc->flags = cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN |
f6532111
MW		 271 MAX_RX_SIZE);
272 if (priv->rx_idx == 31)
21025920
AM		 273 cmd_desc->flags |=
274 cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR);
f6532111
MW		 275 priv->rx_idx = (priv->rx_idx + 1) % 32;
276 }
a6d27d2a
JL		 277}
278
279static void rtl8180_handle_tx(struct ieee80211_hw *dev, unsigned int prio)
280{
281 struct rtl8180_priv *priv = dev->priv;
282 struct rtl8180_tx_ring *ring = &priv->tx_ring[prio];
e6a9854b 283
a6d27d2a
JL		 284 while (skb_queue_len(&ring->queue)) {
285 struct rtl8180_tx_desc *entry = &ring->desc[ring->idx];
286 struct sk_buff *skb;
287 struct ieee80211_tx_info *info;
288 u32 flags = le32_to_cpu(entry->flags);
f6532111 289
a6d27d2a
JL		 290 if (flags & RTL818X_TX_DESC_FLAG_OWN)
291 return;
292
293 ring->idx = (ring->idx + 1) % ring->entries;
294 skb = __skb_dequeue(&ring->queue);
295 pci_unmap_single(priv->pdev, le32_to_cpu(entry->tx_buf),
296 skb->len, PCI_DMA_TODEVICE);
297
298 info = IEEE80211_SKB_CB(skb);
299 ieee80211_tx_info_clear_status(info);
300
301 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK) &&
302 (flags & RTL818X_TX_DESC_FLAG_TX_OK))
303 info->flags |= IEEE80211_TX_STAT_ACK;
304
305 info->status.rates[0].count = (flags & 0xFF) + 1;
306 info->status.rates[1].idx = -1;
030725d2 307
a6d27d2a
JL		 308 ieee80211_tx_status_irqsafe(dev, skb);
309 if (ring->entries - skb_queue_len(&ring->queue) == 2)
310 ieee80211_wake_queue(dev, prio);
311 }
f6532111
MW		 312}
313
a373ebcb
AM		 314static irqreturn_t rtl8187se_interrupt(int irq, void *dev_id)
315{
316 struct ieee80211_hw *dev = dev_id;
317 struct rtl8180_priv *priv = dev->priv;
318 u32 reg;
319 unsigned long flags;
320 static int desc_err;
321
322 spin_lock_irqsave(&priv->lock, flags);
323 /* Note: 32-bit interrupt status */
324 reg = rtl818x_ioread32(priv, &priv->map->INT_STATUS_SE);
325 if (unlikely(reg == 0xFFFFFFFF)) {
326 spin_unlock_irqrestore(&priv->lock, flags);
327 return IRQ_HANDLED;
328 }
329
330 rtl818x_iowrite32(priv, &priv->map->INT_STATUS_SE, reg);
331
332 if (reg & IMR_TIMEOUT1)
333 rtl818x_iowrite32(priv, &priv->map->INT_TIMEOUT, 0);
334
335 if (reg & (IMR_TBDOK | IMR_TBDER))
336 rtl8180_handle_tx(dev, 4);
337
338 if (reg & (IMR_TVODOK | IMR_TVODER))
339 rtl8180_handle_tx(dev, 0);
340
341 if (reg & (IMR_TVIDOK | IMR_TVIDER))
342 rtl8180_handle_tx(dev, 1);
343
344 if (reg & (IMR_TBEDOK | IMR_TBEDER))
345 rtl8180_handle_tx(dev, 2);
346
347 if (reg & (IMR_TBKDOK | IMR_TBKDER))
348 rtl8180_handle_tx(dev, 3);
349
350 if (reg & (IMR_ROK | IMR_RER | RTL818X_INT_SE_RX_DU | IMR_RQOSOK))
351 rtl8180_handle_rx(dev);
352 /* The interface sometimes generates several RX DMA descriptor errors
353 * at startup. Do not report these.
354 */
355 if ((reg & RTL818X_INT_SE_RX_DU) && desc_err++ > 2)
356 if (net_ratelimit())
357 wiphy_err(dev->wiphy, "No RX DMA Descriptor avail\n");
358
359 spin_unlock_irqrestore(&priv->lock, flags);
360 return IRQ_HANDLED;
361}
362
f6532111
MW		 363static irqreturn_t rtl8180_interrupt(int irq, void *dev_id)
364{
365 struct ieee80211_hw *dev = dev_id;
366 struct rtl8180_priv *priv = dev->priv;
367 u16 reg;
368
a6d27d2a 369 spin_lock(&priv->lock);
f6532111 370 reg = rtl818x_ioread16(priv, &priv->map->INT_STATUS);
a6d27d2a
JL		 371 if (unlikely(reg == 0xFFFF)) {
372 spin_unlock(&priv->lock);
f6532111 373 return IRQ_HANDLED;
a6d27d2a 374 }
f6532111
MW		 375
376 rtl818x_iowrite16(priv, &priv->map->INT_STATUS, reg);
377
a6d27d2a 378 if (reg & (RTL818X_INT_TXB_OK | RTL818X_INT_TXB_ERR))
a6d27d2a 379 rtl8180_handle_tx(dev, 1);
f6532111 380
a6d27d2a
JL		 381 if (reg & (RTL818X_INT_TXL_OK | RTL818X_INT_TXL_ERR))
382 rtl8180_handle_tx(dev, 0);
383
384 if (reg & (RTL818X_INT_RX_OK | RTL818X_INT_RX_ERR))
385 rtl8180_handle_rx(dev);
386
387 spin_unlock(&priv->lock);
f6532111
MW		 388
389 return IRQ_HANDLED;
390}
391
36323f81
TH		 392static void rtl8180_tx(struct ieee80211_hw *dev,
393 struct ieee80211_tx_control *control,
394 struct sk_buff *skb)
f6532111 395{
e039fa4a 396 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
51e080de 397 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
f6532111
MW		 398 struct rtl8180_priv *priv = dev->priv;
399 struct rtl8180_tx_ring *ring;
400 struct rtl8180_tx_desc *entry;
a6d27d2a 401 unsigned long flags;
fd6564fc 402 unsigned int idx, prio, hw_prio;
f6532111
MW		 403 dma_addr_t mapping;
404 u32 tx_flags;
e6a9854b 405 u8 rc_flags;
f6532111
MW		 406 u16 plcp_len = 0;
407 __le16 rts_duration = 0;
3ee44d60
AM		 408 /* do arithmetic and then convert to le16 */
409 u16 frame_duration = 0;
f6532111 410
e2530083 411 prio = skb_get_queue_mapping(skb);
f6532111
MW		 412 ring = &priv->tx_ring[prio];
413
414 mapping = pci_map_single(priv->pdev, skb->data,
415 skb->len, PCI_DMA_TODEVICE);
416
348f7d4a 417 if (pci_dma_mapping_error(priv->pdev, mapping)) {
418 kfree_skb(skb);
419 dev_err(&priv->pdev->dev, "TX DMA mapping error\n");
420 return;
348f7d4a 421 }
422
38e3b0d8
HRK		 423 tx_flags = RTL818X_TX_DESC_FLAG_OWN | RTL818X_TX_DESC_FLAG_FS |
424 RTL818X_TX_DESC_FLAG_LS |
e039fa4a 425 (ieee80211_get_tx_rate(dev, info)->hw_value << 24) |
2e92e6f2 426 skb->len;
f6532111 427
6caefd12 428 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180)
38e3b0d8
HRK		 429 tx_flags |= RTL818X_TX_DESC_FLAG_DMA |
430 RTL818X_TX_DESC_FLAG_NO_ENC;
f6532111 431
e6a9854b
JB		 432 rc_flags = info->control.rates[0].flags;
433 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
38e3b0d8 434 tx_flags |= RTL818X_TX_DESC_FLAG_RTS;
e039fa4a 435 tx_flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
e6a9854b 436 } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
38e3b0d8 437 tx_flags |= RTL818X_TX_DESC_FLAG_CTS;
e039fa4a 438 tx_flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
aa68cbfb 439 }
f6532111 440
e6a9854b 441 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS)
32bfd35d 442 rts_duration = ieee80211_rts_duration(dev, priv->vif, skb->len,
e039fa4a 443 info);
f6532111 444
6caefd12 445 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180) {
f6532111
MW		 446 unsigned int remainder;
447
448 plcp_len = DIV_ROUND_UP(16 * (skb->len + 4),
e039fa4a 449 (ieee80211_get_tx_rate(dev, info)->bitrate * 2) / 10);
f6532111 450 remainder = (16 * (skb->len + 4)) %
e039fa4a 451 ((ieee80211_get_tx_rate(dev, info)->bitrate * 2) / 10);
35a0ace7 452 if (remainder <= 6)
f6532111
MW		 453 plcp_len |= 1 << 15;
454 }
455
3ee44d60
AM		 456 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
457 __le16 duration;
458 /* SIFS time (required by HW) is already included by
459 * ieee80211_generic_frame_duration
460 */
461 duration = ieee80211_generic_frame_duration(dev, priv->vif,
462 IEEE80211_BAND_2GHZ, skb->len,
463 ieee80211_get_tx_rate(dev, info));
464
465 frame_duration = priv->ack_time + le16_to_cpu(duration);
466 }
467
a6d27d2a 468 spin_lock_irqsave(&priv->lock, flags);
51e080de
JL		 469
470 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
471 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
472 priv->seqno += 0x10;
473 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
474 hdr->seq_ctrl |= cpu_to_le16(priv->seqno);
475 }
476
f6532111
MW		 477 idx = (ring->idx + skb_queue_len(&ring->queue)) % ring->entries;
478 entry = &ring->desc[idx];
479
3ee44d60
AM		 480 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
481 entry->frame_duration = cpu_to_le16(frame_duration);
482 entry->frame_len_se = cpu_to_le16(skb->len);
483
484 /* tpc polarity */
485 entry->flags3 = cpu_to_le16(1<<4);
486 } else
487 entry->frame_len = cpu_to_le32(skb->len);
488
f6532111
MW		 489 entry->rts_duration = rts_duration;
490 entry->plcp_len = cpu_to_le16(plcp_len);
491 entry->tx_buf = cpu_to_le32(mapping);
3ee44d60 492
e6a9854b 493 entry->flags2 = info->control.rates[1].idx >= 0 ?
870abdf6 494 ieee80211_get_alt_retry_rate(dev, info, 0)->bitrate << 4 : 0;
e6a9854b 495 entry->retry_limit = info->control.rates[0].count;
4c552a5b 496
497 /* We must be sure that tx_flags is written last because the HW
498 * looks at it to check if the rest of data is valid or not
499 */
500 wmb();
f6532111 501 entry->flags = cpu_to_le32(tx_flags);
c24782e6 502 /* We must be sure this has been written before followings HW
503 * register write, because this write will made the HW attempts
504 * to DMA the just-written data
505 */
506 wmb();
507
f6532111
MW		 508 __skb_queue_tail(&ring->queue, skb);
509 if (ring->entries - skb_queue_len(&ring->queue) < 2)
d10e2e02 510 ieee80211_stop_queue(dev, prio);
51e080de 511
a6d27d2a 512 spin_unlock_irqrestore(&priv->lock, flags);
f6532111 513
3ee44d60
AM		 514 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
515 /* just poll: rings are stopped with TPPollStop reg */
516 hw_prio = rtl8187se_queues_map[prio];
517 rtl818x_iowrite8(priv, &priv->map->TX_DMA_POLLING,
518 (1 << hw_prio));
519 } else {
520 hw_prio = rtl8180_queues_map[prio];
521 rtl818x_iowrite8(priv, &priv->map->TX_DMA_POLLING,
fd6564fc
AM		 522 (1 << hw_prio) | /* ring to poll */
523 (1<<1) | (1<<2));/* stopped rings */
3ee44d60 524 }
f6532111
MW		 525}
526
ff3cbc2c
AM		 527static void rtl8180_set_anaparam3(struct rtl8180_priv *priv, u16 anaparam3)
528{
529 u8 reg;
530
531 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
532 RTL818X_EEPROM_CMD_CONFIG);
533
534 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
535 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
536 reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
537
538 rtl818x_iowrite16(priv, &priv->map->ANAPARAM3, anaparam3);
539
540 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
541 reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
542
543 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
544 RTL818X_EEPROM_CMD_NORMAL);
545}
546
547void rtl8180_set_anaparam2(struct rtl8180_priv *priv, u32 anaparam2)
548{
549 u8 reg;
550
551 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
552 RTL818X_EEPROM_CMD_CONFIG);
553
554 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
555 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
556 reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
557
558 rtl818x_iowrite32(priv, &priv->map->ANAPARAM2, anaparam2);
559
560 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
561 reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
562
563 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
564 RTL818X_EEPROM_CMD_NORMAL);
565}
566
f6532111
MW		 567void rtl8180_set_anaparam(struct rtl8180_priv *priv, u32 anaparam)
568{
569 u8 reg;
570
571 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
572 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
573 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
574 reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
575 rtl818x_iowrite32(priv, &priv->map->ANAPARAM, anaparam);
576 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
577 reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
578 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
579}
580
4a67aa5d
AM		 581static void rtl8187se_mac_config(struct ieee80211_hw *dev)
582{
583 struct rtl8180_priv *priv = dev->priv;
584 u8 reg;
585
586 rtl818x_iowrite32(priv, REG_ADDR4(0x1F0), 0);
587 rtl818x_ioread32(priv, REG_ADDR4(0x1F0));
588 rtl818x_iowrite32(priv, REG_ADDR4(0x1F4), 0);
589 rtl818x_ioread32(priv, REG_ADDR4(0x1F4));
590 rtl818x_iowrite8(priv, REG_ADDR1(0x1F8), 0);
591 rtl818x_ioread8(priv, REG_ADDR1(0x1F8));
592 /* Enable DA10 TX power saving */
593 reg = rtl818x_ioread8(priv, &priv->map->PHY_PR);
594 rtl818x_iowrite8(priv, &priv->map->PHY_PR, reg | 0x04);
595 /* Power */
596 rtl818x_iowrite16(priv, PI_DATA_REG, 0x1000);
597 rtl818x_iowrite16(priv, SI_DATA_REG, 0x1000);
598 /* AFE - default to power ON */
599 rtl818x_iowrite16(priv, REG_ADDR2(0x370), 0x0560);
600 rtl818x_iowrite16(priv, REG_ADDR2(0x372), 0x0560);
601 rtl818x_iowrite16(priv, REG_ADDR2(0x374), 0x0DA4);
602 rtl818x_iowrite16(priv, REG_ADDR2(0x376), 0x0DA4);
603 rtl818x_iowrite16(priv, REG_ADDR2(0x378), 0x0560);
604 rtl818x_iowrite16(priv, REG_ADDR2(0x37A), 0x0560);
605 rtl818x_iowrite16(priv, REG_ADDR2(0x37C), 0x00EC);
606 rtl818x_iowrite16(priv, REG_ADDR2(0x37E), 0x00EC);
607 rtl818x_iowrite8(priv, REG_ADDR1(0x24E), 0x01);
608 /* unknown, needed for suspend to RAM resume */
609 rtl818x_iowrite8(priv, REG_ADDR1(0x0A), 0x72);
610}
611
612static void rtl8187se_set_antenna_config(struct ieee80211_hw *dev, u8 def_ant,
613 bool diversity)
614{
615 struct rtl8180_priv *priv = dev->priv;
616
617 rtl8225_write_phy_cck(dev, 0x0C, 0x09);
618 if (diversity) {
619 if (def_ant == 1) {
620 rtl818x_iowrite8(priv, &priv->map->TX_ANTENNA, 0x00);
621 rtl8225_write_phy_cck(dev, 0x11, 0xBB);
622 rtl8225_write_phy_cck(dev, 0x01, 0xC7);
623 rtl8225_write_phy_ofdm(dev, 0x0D, 0x54);
624 rtl8225_write_phy_ofdm(dev, 0x18, 0xB2);
625 } else { /* main antenna */
626 rtl818x_iowrite8(priv, &priv->map->TX_ANTENNA, 0x03);
627 rtl8225_write_phy_cck(dev, 0x11, 0x9B);
628 rtl8225_write_phy_cck(dev, 0x01, 0xC7);
629 rtl8225_write_phy_ofdm(dev, 0x0D, 0x5C);
630 rtl8225_write_phy_ofdm(dev, 0x18, 0xB2);
631 }
632 } else { /* disable antenna diversity */
633 if (def_ant == 1) {
634 rtl818x_iowrite8(priv, &priv->map->TX_ANTENNA, 0x00);
635 rtl8225_write_phy_cck(dev, 0x11, 0xBB);
636 rtl8225_write_phy_cck(dev, 0x01, 0x47);
637 rtl8225_write_phy_ofdm(dev, 0x0D, 0x54);
638 rtl8225_write_phy_ofdm(dev, 0x18, 0x32);
639 } else { /* main antenna */
640 rtl818x_iowrite8(priv, &priv->map->TX_ANTENNA, 0x03);
641 rtl8225_write_phy_cck(dev, 0x11, 0x9B);
642 rtl8225_write_phy_cck(dev, 0x01, 0x47);
643 rtl8225_write_phy_ofdm(dev, 0x0D, 0x5C);
644 rtl8225_write_phy_ofdm(dev, 0x18, 0x32);
645 }
646 }
647 /* priv->curr_ant = def_ant; */
648}
649
732c8932
AM		 650static void rtl8180_int_enable(struct ieee80211_hw *dev)
651{
652 struct rtl8180_priv *priv = dev->priv;
653
654 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
655 rtl818x_iowrite32(priv, &priv->map->IMR, IMR_TMGDOK |
656 IMR_TBDER | IMR_THPDER |
657 IMR_THPDER | IMR_THPDOK |
658 IMR_TVODER | IMR_TVODOK |
659 IMR_TVIDER | IMR_TVIDOK |
660 IMR_TBEDER | IMR_TBEDOK |
661 IMR_TBKDER | IMR_TBKDOK |
662 IMR_RDU | IMR_RER |
663 IMR_ROK | IMR_RQOSOK);
664 } else {
665 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
666 }
667}
668
669static void rtl8180_int_disable(struct ieee80211_hw *dev)
670{
671 struct rtl8180_priv *priv = dev->priv;
672
673 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
674 rtl818x_iowrite32(priv, &priv->map->IMR, 0);
675 } else {
676 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
677 }
678}
679
516a0930
AM		 680static void rtl8180_conf_basic_rates(struct ieee80211_hw *dev,
681 u32 rates_mask)
682{
683 struct rtl8180_priv *priv = dev->priv;
684
685 u8 max, min;
686 u16 reg;
687
688 max = fls(rates_mask) - 1;
689 min = ffs(rates_mask) - 1;
690
691 switch (priv->chip_family) {
692
693 case RTL818X_CHIP_FAMILY_RTL8180:
694 /* in 8180 this is NOT a BITMAP */
695 reg = rtl818x_ioread16(priv, &priv->map->BRSR);
696 reg &= ~3;
697 reg |= max;
698 rtl818x_iowrite16(priv, &priv->map->BRSR, reg);
516a0930
AM		 699 break;
700
701 case RTL818X_CHIP_FAMILY_RTL8185:
702 /* in 8185 this is a BITMAP */
703 rtl818x_iowrite16(priv, &priv->map->BRSR, rates_mask);
704 rtl818x_iowrite8(priv, &priv->map->RESP_RATE, (max << 4) | min);
705 break;
d209f3b4
AM		 706
707 case RTL818X_CHIP_FAMILY_RTL8187SE:
708 /* in 8187se this is a BITMAP */
709 rtl818x_iowrite16(priv, &priv->map->BRSR_8187SE, rates_mask);
710 break;
516a0930
AM		 711 }
712}
713
f1026df8
AM		 714static void rtl8180_config_cardbus(struct ieee80211_hw *dev)
715{
716 struct rtl8180_priv *priv = dev->priv;
717 u16 reg16;
718 u8 reg8;
719
720 reg8 = rtl818x_ioread8(priv, &priv->map->CONFIG3);
721 reg8 |= 1 << 1;
722 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg8);
723
724 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
725 rtl818x_iowrite16(priv, FEMR_SE, 0xffff);
726 } else {
727 reg16 = rtl818x_ioread16(priv, &priv->map->FEMR);
728 reg16 |= (1 << 15) | (1 << 14) | (1 << 4);
729 rtl818x_iowrite16(priv, &priv->map->FEMR, reg16);
730 }
731
732}
733
f6532111
MW		 734static int rtl8180_init_hw(struct ieee80211_hw *dev)
735{
736 struct rtl8180_priv *priv = dev->priv;
737 u16 reg;
4a67aa5d 738 u32 reg32;
f6532111
MW		 739
740 rtl818x_iowrite8(priv, &priv->map->CMD, 0);
741 rtl818x_ioread8(priv, &priv->map->CMD);
742 msleep(10);
743
744 /* reset */
732c8932 745 rtl8180_int_disable(dev);
f6532111
MW		 746 rtl818x_ioread8(priv, &priv->map->CMD);
747
748 reg = rtl818x_ioread8(priv, &priv->map->CMD);
749 reg &= (1 << 1);
750 reg |= RTL818X_CMD_RESET;
751 rtl818x_iowrite8(priv, &priv->map->CMD, RTL818X_CMD_RESET);
752 rtl818x_ioread8(priv, &priv->map->CMD);
753 msleep(200);
754
755 /* check success of reset */
756 if (rtl818x_ioread8(priv, &priv->map->CMD) & RTL818X_CMD_RESET) {
c96c31e4 757 wiphy_err(dev->wiphy, "reset timeout!\n");
f6532111
MW		 758 return -ETIMEDOUT;
759 }
760
761 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_LOAD);
762 rtl818x_ioread8(priv, &priv->map->CMD);
763 msleep(200);
764
765 if (rtl818x_ioread8(priv, &priv->map->CONFIG3) & (1 << 3)) {
f1026df8 766 rtl8180_config_cardbus(dev);
f6532111
MW		 767 }
768
4a67aa5d
AM		 769 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE)
770 rtl818x_iowrite8(priv, &priv->map->MSR, RTL818X_MSR_ENEDCA);
771 else
772 rtl818x_iowrite8(priv, &priv->map->MSR, 0);
f6532111 773
6caefd12 774 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180)
f6532111
MW		 775 rtl8180_set_anaparam(priv, priv->anaparam);
776
777 rtl818x_iowrite32(priv, &priv->map->RDSAR, priv->rx_ring_dma);
4a67aa5d
AM		 778 /* mac80211 queue have higher prio for lower index. The last queue
779 * (that mac80211 is not aware of) is reserved for beacons (and have
780 * the highest priority on the NIC)
781 */
782 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8187SE) {
783 rtl818x_iowrite32(priv, &priv->map->TBDA,
784 priv->tx_ring[1].dma);
785 rtl818x_iowrite32(priv, &priv->map->TLPDA,
786 priv->tx_ring[0].dma);
787 } else {
788 rtl818x_iowrite32(priv, &priv->map->TBDA,
789 priv->tx_ring[4].dma);
790 rtl818x_iowrite32(priv, &priv->map->TVODA,
791 priv->tx_ring[0].dma);
792 rtl818x_iowrite32(priv, &priv->map->TVIDA,
793 priv->tx_ring[1].dma);
794 rtl818x_iowrite32(priv, &priv->map->TBEDA,
795 priv->tx_ring[2].dma);
796 rtl818x_iowrite32(priv, &priv->map->TBKDA,
797 priv->tx_ring[3].dma);
798 }
f6532111
MW		 799
800 /* TODO: necessary? specs indicate not */
801 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
802 reg = rtl818x_ioread8(priv, &priv->map->CONFIG2);
803 rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg & ~(1 << 3));
6caefd12 804 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8185) {
f6532111
MW		 805 reg = rtl818x_ioread8(priv, &priv->map->CONFIG2);
806 rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg | (1 << 4));
807 }
808 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
809
810 /* TODO: set CONFIG5 for calibrating AGC on rtl8180 + philips radio? */
811
812 /* TODO: turn off hw wep on rtl8180 */
813
814 rtl818x_iowrite32(priv, &priv->map->INT_TIMEOUT, 0);
815
6caefd12 816 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180) {
f6532111
MW		 817 rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0);
818 rtl818x_iowrite8(priv, &priv->map->RATE_FALLBACK, 0x81);
4a67aa5d
AM		 819 } else {
820 rtl818x_iowrite8(priv, &priv->map->SECURITY, 0);
821
822 rtl818x_iowrite8(priv, &priv->map->PHY_DELAY, 0x6);
823 rtl818x_iowrite8(priv, &priv->map->CARRIER_SENSE_COUNTER, 0x4C);
824 }
f6532111 825
4a67aa5d 826 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8185) {
f6532111
MW		 827 /* TODO: set ClkRun enable? necessary? */
828 reg = rtl818x_ioread8(priv, &priv->map->GP_ENABLE);
829 rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, reg & ~(1 << 6));
830 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
831 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
832 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg | (1 << 2));
833 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
4a67aa5d 834 }
f6532111 835
4a67aa5d
AM		 836 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
837
838 /* the set auto rate fallback bitmask from 1M to 54 Mb/s */
839 rtl818x_iowrite16(priv, ARFR, 0xFFF);
840 rtl818x_ioread16(priv, ARFR);
841
842 /* stop unused queus (no dma alloc) */
843 rtl818x_iowrite8(priv, &priv->map->TPPOLL_STOP,
844 RTL818x_TPPOLL_STOP_MG | RTL818x_TPPOLL_STOP_HI);
845
846 rtl818x_iowrite8(priv, &priv->map->ACM_CONTROL, 0x00);
847 rtl818x_iowrite16(priv, &priv->map->TID_AC_MAP, 0xFA50);
848
849 rtl818x_iowrite16(priv, &priv->map->INT_MIG, 0);
850
851 /* some black magic here.. */
852 rtl8187se_mac_config(dev);
853
854 rtl818x_iowrite16(priv, RFSW_CTRL, 0x569A);
855 rtl818x_ioread16(priv, RFSW_CTRL);
856
857 rtl8180_set_anaparam(priv, RTL8225SE_ANAPARAM_ON);
858 rtl8180_set_anaparam2(priv, RTL8225SE_ANAPARAM2_ON);
859 rtl8180_set_anaparam3(priv, RTL8225SE_ANAPARAM3);
860
861
862 rtl818x_iowrite8(priv, &priv->map->CONFIG5,
863 rtl818x_ioread8(priv, &priv->map->CONFIG5) & 0x7F);
864
865 /*probably this switch led on */
866 rtl818x_iowrite8(priv, &priv->map->PGSELECT,
867 rtl818x_ioread8(priv, &priv->map->PGSELECT) | 0x08);
868
869 rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, 0x0480);
870 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1BFF);
871 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0x2488);
872
873 rtl818x_iowrite32(priv, &priv->map->RF_TIMING, 0x4003);
874
875 /* the reference code mac hardcode table write
876 * this reg by doing byte-wide accesses.
877 * It does it just for lowest and highest byte..
878 */
879 reg32 = rtl818x_ioread32(priv, &priv->map->RF_PARA);
880 reg32 &= 0x00ffff00;
881 reg32 |= 0xb8000054;
882 rtl818x_iowrite32(priv, &priv->map->RF_PARA, reg32);
f6532111
MW		 883 }
884
885 priv->rf->init(dev);
516a0930
AM		 886
887 /* default basic rates are 1,2 Mbps for rtl8180. 1,2,6,9,12,18,24 Mbps
888 * otherwise. bitmask 0x3 and 0x01f3 respectively.
889 * NOTE: currenty rtl8225 RF code changes basic rates, so we need to do
890 * this after rf init.
891 * TODO: try to find out whether RF code really needs to do this..
892 */
893 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180)
894 rtl8180_conf_basic_rates(dev, 0x3);
895 else
896 rtl8180_conf_basic_rates(dev, 0x1f3);
897
4a67aa5d
AM		 898 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE)
899 rtl8187se_set_antenna_config(dev,
900 priv->antenna_diversity_default,
901 priv->antenna_diversity_en);
f6532111
MW		 902 return 0;
903}
904
905static int rtl8180_init_rx_ring(struct ieee80211_hw *dev)
906{
907 struct rtl8180_priv *priv = dev->priv;
21025920 908 struct rtl818x_rx_cmd_desc *entry;
f6532111
MW		 909 int i;
910
21025920
AM		 911 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE)
912 priv->rx_ring_sz = sizeof(struct rtl8187se_rx_desc);
913 else
914 priv->rx_ring_sz = sizeof(struct rtl8180_rx_desc);
915
f6532111 916 priv->rx_ring = pci_alloc_consistent(priv->pdev,
21025920 917 priv->rx_ring_sz * 32,
f6532111
MW		 918 &priv->rx_ring_dma);
919
920 if (!priv->rx_ring || (unsigned long)priv->rx_ring & 0xFF) {
5db55844 921 wiphy_err(dev->wiphy, "Cannot allocate RX ring\n");
f6532111
MW		 922 return -ENOMEM;
923 }
924
21025920 925 memset(priv->rx_ring, 0, priv->rx_ring_sz * 32);
f6532111
MW		 926 priv->rx_idx = 0;
927
928 for (i = 0; i < 32; i++) {
929 struct sk_buff *skb = dev_alloc_skb(MAX_RX_SIZE);
930 dma_addr_t *mapping;
21025920 931 entry = priv->rx_ring + priv->rx_ring_sz*i;
4da18bb4 932 if (!skb) {
933 wiphy_err(dev->wiphy, "Cannot allocate RX skb\n");
934 return -ENOMEM;
935 }
f6532111
MW		 936 priv->rx_buf[i] = skb;
937 mapping = (dma_addr_t *)skb->cb;
938 *mapping = pci_map_single(priv->pdev, skb_tail_pointer(skb),
939 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
ec1da08d 940
941 if (pci_dma_mapping_error(priv->pdev, *mapping)) {
942 kfree_skb(skb);
943 wiphy_err(dev->wiphy, "Cannot map DMA for RX skb\n");
944 return -ENOMEM;
945 }
946
f6532111 947 entry->rx_buf = cpu_to_le32(*mapping);
38e3b0d8 948 entry->flags = cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN |
f6532111
MW		 949 MAX_RX_SIZE);
950 }
38e3b0d8 951 entry->flags |= cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR);
f6532111
MW		 952 return 0;
953}
954
955static void rtl8180_free_rx_ring(struct ieee80211_hw *dev)
956{
957 struct rtl8180_priv *priv = dev->priv;
958 int i;
959
960 for (i = 0; i < 32; i++) {
961 struct sk_buff *skb = priv->rx_buf[i];
962 if (!skb)
963 continue;
964
965 pci_unmap_single(priv->pdev,
966 *((dma_addr_t *)skb->cb),
967 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
968 kfree_skb(skb);
969 }
970
21025920 971 pci_free_consistent(priv->pdev, priv->rx_ring_sz * 32,
f6532111
MW		 972 priv->rx_ring, priv->rx_ring_dma);
973 priv->rx_ring = NULL;
974}
975
976static int rtl8180_init_tx_ring(struct ieee80211_hw *dev,
977 unsigned int prio, unsigned int entries)
978{
979 struct rtl8180_priv *priv = dev->priv;
980 struct rtl8180_tx_desc *ring;
981 dma_addr_t dma;
982 int i;
983
984 ring = pci_alloc_consistent(priv->pdev, sizeof(*ring) * entries, &dma);
985 if (!ring || (unsigned long)ring & 0xFF) {
5db55844 986 wiphy_err(dev->wiphy, "Cannot allocate TX ring (prio = %d)\n",
c96c31e4 987 prio);
f6532111
MW		 988 return -ENOMEM;
989 }
990
991 memset(ring, 0, sizeof(*ring)*entries);
992 priv->tx_ring[prio].desc = ring;
993 priv->tx_ring[prio].dma = dma;
994 priv->tx_ring[prio].idx = 0;
995 priv->tx_ring[prio].entries = entries;
996 skb_queue_head_init(&priv->tx_ring[prio].queue);
997
998 for (i = 0; i < entries; i++)
999 ring[i].next_tx_desc =
1000 cpu_to_le32((u32)dma + ((i + 1) % entries) * sizeof(*ring));
1001
1002 return 0;
1003}
1004
1005static void rtl8180_free_tx_ring(struct ieee80211_hw *dev, unsigned int prio)
1006{
1007 struct rtl8180_priv *priv = dev->priv;
1008 struct rtl8180_tx_ring *ring = &priv->tx_ring[prio];
1009
1010 while (skb_queue_len(&ring->queue)) {
1011 struct rtl8180_tx_desc *entry = &ring->desc[ring->idx];
1012 struct sk_buff *skb = __skb_dequeue(&ring->queue);
1013
1014 pci_unmap_single(priv->pdev, le32_to_cpu(entry->tx_buf),
1015 skb->len, PCI_DMA_TODEVICE);
f6532111
MW		 1016 kfree_skb(skb);
1017 ring->idx = (ring->idx + 1) % ring->entries;
1018 }
1019
1020 pci_free_consistent(priv->pdev, sizeof(*ring->desc)*ring->entries,
1021 ring->desc, ring->dma);
1022 ring->desc = NULL;
1023}
1024
1025static int rtl8180_start(struct ieee80211_hw *dev)
1026{
1027 struct rtl8180_priv *priv = dev->priv;
1028 int ret, i;
1029 u32 reg;
1030
1031 ret = rtl8180_init_rx_ring(dev);
1032 if (ret)
1033 return ret;
1034
fd6564fc 1035 for (i = 0; i < (dev->queues + 1); i++)
f6532111
MW		 1036 if ((ret = rtl8180_init_tx_ring(dev, i, 16)))
1037 goto err_free_rings;
1038
1039 ret = rtl8180_init_hw(dev);
1040 if (ret)
1041 goto err_free_rings;
1042
a373ebcb
AM		 1043 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
1044 ret = request_irq(priv->pdev->irq, rtl8187se_interrupt,
f6532111 1045 IRQF_SHARED, KBUILD_MODNAME, dev);
a373ebcb
AM		 1046 } else {
1047 ret = request_irq(priv->pdev->irq, rtl8180_interrupt,
1048 IRQF_SHARED, KBUILD_MODNAME, dev);
1049 }
1050
f6532111 1051 if (ret) {
5db55844 1052 wiphy_err(dev->wiphy, "failed to register IRQ handler\n");
f6532111
MW		 1053 goto err_free_rings;
1054 }
1055
732c8932 1056 rtl8180_int_enable(dev);
f6532111 1057
f18f112b
AM		 1058 /* in rtl8187se at MAR regs offset there is the management
1059 * TX descriptor DMA addres..
1060 */
1061 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8187SE) {
1062 rtl818x_iowrite32(priv, &priv->map->MAR[0], ~0);
1063 rtl818x_iowrite32(priv, &priv->map->MAR[1], ~0);
1064 }
f6532111
MW		 1065
1066 reg = RTL818X_RX_CONF_ONLYERLPKT |
1067 RTL818X_RX_CONF_RX_AUTORESETPHY |
1068 RTL818X_RX_CONF_MGMT |
1069 RTL818X_RX_CONF_DATA |
1070 (7 << 8 /* MAX RX DMA */) |
1071 RTL818X_RX_CONF_BROADCAST |
1072 RTL818X_RX_CONF_NICMAC;
1073
6caefd12 1074 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8185)
f6532111 1075 reg |= RTL818X_RX_CONF_CSDM1 | RTL818X_RX_CONF_CSDM2;
4a67aa5d 1076 else if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180) {
f6532111
MW		 1077 reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE1)
1078 ? RTL818X_RX_CONF_CSDM1 : 0;
1079 reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE2)
1080 ? RTL818X_RX_CONF_CSDM2 : 0;
4a67aa5d
AM		 1081 } else {
1082 reg &= ~(RTL818X_RX_CONF_CSDM1 | RTL818X_RX_CONF_CSDM2);
f6532111
MW		 1083 }
1084
1085 priv->rx_conf = reg;
1086 rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
1087
6caefd12 1088 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180) {
f6532111 1089 reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
14c76150 1090
1091 /* CW is not on per-packet basis.
1092 * in rtl8185 the CW_VALUE reg is used.
1093 */
6f7343d4 1094 reg &= ~RTL818X_CW_CONF_PERPACKET_CW;
14c76150 1095 /* retry limit IS on per-packet basis.
1096 * the short and long retry limit in TX_CONF
1097 * reg are ignored
1098 */
6f7343d4 1099 reg |= RTL818X_CW_CONF_PERPACKET_RETRY;
f6532111
MW		 1100 rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
1101
1102 reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
14c76150 1103 /* TX antenna and TX gain are not on per-packet basis.
1104 * TX Antenna is selected by ANTSEL reg (RX in BB regs).
1105 * TX gain is selected with CCK_TX_AGC and OFDM_TX_AGC regs
1106 */
6f7343d4 1107 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN;
1108 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL;
f6532111
MW		 1109 reg |= RTL818X_TX_AGC_CTL_FEEDBACK_ANT;
1110 rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
1111
1112 /* disable early TX */
1113 rtl818x_iowrite8(priv, (u8 __iomem *)priv->map + 0xec, 0x3f);
1114 }
1115
1116 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
1117 reg |= (6 << 21 /* MAX TX DMA */) |
1118 RTL818X_TX_CONF_NO_ICV;
1119
4a67aa5d
AM		 1120 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE)
1121 reg |= 1<<30; /* "duration procedure mode" */
6caefd12
AM		 1122
1123 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180)
f6532111
MW		 1124 reg &= ~RTL818X_TX_CONF_PROBE_DTS;
1125 else
1126 reg &= ~RTL818X_TX_CONF_HW_SEQNUM;
1127
e74075a9 1128 reg &= ~RTL818X_TX_CONF_DISCW;
1129
f6532111
MW		 1130 /* different meaning, same value on both rtl8185 and rtl8180 */
1131 reg &= ~RTL818X_TX_CONF_SAT_HWPLCP;
1132
1133 rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
1134
1135 reg = rtl818x_ioread8(priv, &priv->map->CMD);
1136 reg |= RTL818X_CMD_RX_ENABLE;
1137 reg |= RTL818X_CMD_TX_ENABLE;
1138 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
1139
f6532111
MW		 1140 return 0;
1141
1142 err_free_rings:
1143 rtl8180_free_rx_ring(dev);
fd6564fc 1144 for (i = 0; i < (dev->queues + 1); i++)
f6532111
MW		 1145 if (priv->tx_ring[i].desc)
1146 rtl8180_free_tx_ring(dev, i);
1147
1148 return ret;
1149}
1150
1151static void rtl8180_stop(struct ieee80211_hw *dev)
1152{
1153 struct rtl8180_priv *priv = dev->priv;
1154 u8 reg;
1155 int i;
1156
732c8932 1157 rtl8180_int_disable(dev);
f6532111
MW		 1158
1159 reg = rtl818x_ioread8(priv, &priv->map->CMD);
1160 reg &= ~RTL818X_CMD_TX_ENABLE;
1161 reg &= ~RTL818X_CMD_RX_ENABLE;
1162 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
1163
1164 priv->rf->stop(dev);
1165
1166 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
1167 reg = rtl818x_ioread8(priv, &priv->map->CONFIG4);
1168 rtl818x_iowrite8(priv, &priv->map->CONFIG4, reg | RTL818X_CONFIG4_VCOOFF);
1169 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
1170
1171 free_irq(priv->pdev->irq, dev);
1172
1173 rtl8180_free_rx_ring(dev);
fd6564fc 1174 for (i = 0; i < (dev->queues + 1); i++)
f6532111
MW		 1175 rtl8180_free_tx_ring(dev, i);
1176}
1177
37a41b4a
EP		 1178static u64 rtl8180_get_tsf(struct ieee80211_hw *dev,
1179 struct ieee80211_vif *vif)
c809e86c
JL		 1180{
1181 struct rtl8180_priv *priv = dev->priv;
1182
1183 return rtl818x_ioread32(priv, &priv->map->TSFT[0]) |
1184 (u64)(rtl818x_ioread32(priv, &priv->map->TSFT[1])) << 32;
1185}
1186
a3275e24 1187static void rtl8180_beacon_work(struct work_struct *work)
c809e86c
JL		 1188{
1189 struct rtl8180_vif *vif_priv =
1190 container_of(work, struct rtl8180_vif, beacon_work.work);
1191 struct ieee80211_vif *vif =
1192 container_of((void *)vif_priv, struct ieee80211_vif, drv_priv);
1193 struct ieee80211_hw *dev = vif_priv->dev;
1194 struct ieee80211_mgmt *mgmt;
1195 struct sk_buff *skb;
c809e86c
JL		 1196
1197 /* don't overflow the tx ring */
1198 if (ieee80211_queue_stopped(dev, 0))
1199 goto resched;
1200
1201 /* grab a fresh beacon */
1202 skb = ieee80211_beacon_get(dev, vif);
8f1d2d2b
JL		 1203 if (!skb)
1204 goto resched;
c809e86c
JL		 1205
1206 /*
1207 * update beacon timestamp w/ TSF value
1208 * TODO: make hardware update beacon timestamp
1209 */
1210 mgmt = (struct ieee80211_mgmt *)skb->data;
37a41b4a 1211 mgmt->u.beacon.timestamp = cpu_to_le64(rtl8180_get_tsf(dev, vif));
c809e86c
JL		 1212
1213 /* TODO: use actual beacon queue */
1214 skb_set_queue_mapping(skb, 0);
1215
36323f81 1216 rtl8180_tx(dev, NULL, skb);
c809e86c
JL		 1217
1218resched:
1219 /*
1220 * schedule next beacon
1221 * TODO: use hardware support for beacon timing
1222 */
1223 schedule_delayed_work(&vif_priv->beacon_work,
1224 usecs_to_jiffies(1024 * vif->bss_conf.beacon_int));
1225}
1226
f6532111 1227static int rtl8180_add_interface(struct ieee80211_hw *dev,
1ed32e4f 1228 struct ieee80211_vif *vif)
f6532111
MW		 1229{
1230 struct rtl8180_priv *priv = dev->priv;
c809e86c 1231 struct rtl8180_vif *vif_priv;
f6532111 1232
643aab67
JL		 1233 /*
1234 * We only support one active interface at a time.
1235 */
1236 if (priv->vif)
1237 return -EBUSY;
f6532111 1238
1ed32e4f 1239 switch (vif->type) {
05c914fe 1240 case NL80211_IFTYPE_STATION:
c809e86c 1241 case NL80211_IFTYPE_ADHOC:
f6532111
MW		 1242 break;
1243 default:
1244 return -EOPNOTSUPP;
1245 }
1246
1ed32e4f 1247 priv->vif = vif;
32bfd35d 1248
c809e86c
JL		 1249 /* Initialize driver private area */
1250 vif_priv = (struct rtl8180_vif *)&vif->drv_priv;
1251 vif_priv->dev = dev;
1252 INIT_DELAYED_WORK(&vif_priv->beacon_work, rtl8180_beacon_work);
1253 vif_priv->enable_beacon = false;
1254
f6532111
MW		 1255 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
1256 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->MAC[0],
1ed32e4f 1257 le32_to_cpu(*(__le32 *)vif->addr));
f6532111 1258 rtl818x_iowrite16(priv, (__le16 __iomem *)&priv->map->MAC[4],
1ed32e4f 1259 le16_to_cpu(*(__le16 *)(vif->addr + 4)));
f6532111
MW		 1260 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
1261
1262 return 0;
1263}
1264
1265static void rtl8180_remove_interface(struct ieee80211_hw *dev,
1ed32e4f 1266 struct ieee80211_vif *vif)
f6532111
MW		 1267{
1268 struct rtl8180_priv *priv = dev->priv;
32bfd35d 1269 priv->vif = NULL;
f6532111
MW		 1270}
1271
e8975581 1272static int rtl8180_config(struct ieee80211_hw *dev, u32 changed)
f6532111
MW		 1273{
1274 struct rtl8180_priv *priv = dev->priv;
e8975581 1275 struct ieee80211_conf *conf = &dev->conf;
f6532111
MW		 1276
1277 priv->rf->set_chan(dev, conf);
1278
1279 return 0;
1280}
1281
9069af79
AM		 1282static int rtl8180_conf_tx(struct ieee80211_hw *dev,
1283 struct ieee80211_vif *vif, u16 queue,
1284 const struct ieee80211_tx_queue_params *params)
1285{
1286 struct rtl8180_priv *priv = dev->priv;
1287 u8 cw_min, cw_max;
1288
1289 /* nothing to do ? */
1290 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180)
1291 return 0;
1292
1293 cw_min = fls(params->cw_min);
1294 cw_max = fls(params->cw_max);
1295
1296 rtl818x_iowrite8(priv, &priv->map->CW_VAL, (cw_max << 4) | cw_min);
1297
1298 return 0;
1299}
1300
1301static void rtl8180_conf_erp(struct ieee80211_hw *dev,
1302 struct ieee80211_bss_conf *info)
1303{
1304 struct rtl8180_priv *priv = dev->priv;
1305 u8 sifs, difs;
1306 int eifs;
1307 u8 hw_eifs;
1308
1309 /* TODO: should we do something ? */
1310 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180)
1311 return;
1312
1313 /* I _hope_ this means 10uS for the HW.
1314 * In reference code it is 0x22 for
1315 * both rtl8187L and rtl8187SE
1316 */
1317 sifs = 0x22;
1318
1319 if (info->use_short_slot)
1320 priv->slot_time = 9;
1321 else
1322 priv->slot_time = 20;
1323
1324 /* 10 is SIFS time in uS */
1325 difs = 10 + 2 * priv->slot_time;
1326 eifs = 10 + difs + priv->ack_time;
1327
1328 /* HW should use 4uS units for EIFS (I'm sure for rtl8185)*/
1329 hw_eifs = DIV_ROUND_UP(eifs, 4);
1330
1331
1332 rtl818x_iowrite8(priv, &priv->map->SLOT, priv->slot_time);
1333 rtl818x_iowrite8(priv, &priv->map->SIFS, sifs);
1334 rtl818x_iowrite8(priv, &priv->map->DIFS, difs);
1335
1336 /* from reference code. set ack timeout reg = eifs reg */
1337 rtl818x_iowrite8(priv, &priv->map->CARRIER_SENSE_COUNTER, hw_eifs);
1338
1339 /* rtl8187/rtl8185 HW bug. After EIFS is elapsed,
1340 * the HW still wait for DIFS.
1341 * HW uses 4uS units for EIFS.
1342 */
1343 hw_eifs = DIV_ROUND_UP(eifs - difs, 4);
1344
1345 rtl818x_iowrite8(priv, &priv->map->EIFS, hw_eifs);
1346}
1347
da81dede
JL		 1348static void rtl8180_bss_info_changed(struct ieee80211_hw *dev,
1349 struct ieee80211_vif *vif,
1350 struct ieee80211_bss_conf *info,
1351 u32 changed)
1352{
1353 struct rtl8180_priv *priv = dev->priv;
c809e86c 1354 struct rtl8180_vif *vif_priv;
2d0ddec5 1355 int i;
0f956e71 1356 u8 reg;
2d0ddec5 1357
c809e86c
JL		 1358 vif_priv = (struct rtl8180_vif *)&vif->drv_priv;
1359
2d0ddec5
JB		 1360 if (changed & BSS_CHANGED_BSSID) {
1361 for (i = 0; i < ETH_ALEN; i++)
1362 rtl818x_iowrite8(priv, &priv->map->BSSID[i],
1363 info->bssid[i]);
1364
0f956e71
JL		 1365 if (is_valid_ether_addr(info->bssid)) {
1366 if (vif->type == NL80211_IFTYPE_ADHOC)
1367 reg = RTL818X_MSR_ADHOC;
1368 else
1369 reg = RTL818X_MSR_INFRA;
1370 } else
1371 reg = RTL818X_MSR_NO_LINK;
1372 rtl818x_iowrite8(priv, &priv->map->MSR, reg);
2d0ddec5 1373 }
da81dede 1374
516a0930
AM		 1375 if (changed & BSS_CHANGED_BASIC_RATES)
1376 rtl8180_conf_basic_rates(dev, info->basic_rates);
1377
9069af79
AM		 1378 if (changed & (BSS_CHANGED_ERP_SLOT | BSS_CHANGED_ERP_PREAMBLE)) {
1379
1380 /* when preamble changes, acktime duration changes, and erp must
1381 * be recalculated. ACK time is calculated at lowest rate.
1382 * Since mac80211 include SIFS time we remove it (-10)
1383 */
1384 priv->ack_time =
1385 le16_to_cpu(ieee80211_generic_frame_duration(dev,
1386 priv->vif,
1387 IEEE80211_BAND_2GHZ, 10,
1388 &priv->rates[0])) - 10;
1389
1390 rtl8180_conf_erp(dev, info);
1391 }
c809e86c
JL		 1392
1393 if (changed & BSS_CHANGED_BEACON_ENABLED)
1394 vif_priv->enable_beacon = info->enable_beacon;
1395
1396 if (changed & (BSS_CHANGED_BEACON_ENABLED | BSS_CHANGED_BEACON)) {
1397 cancel_delayed_work_sync(&vif_priv->beacon_work);
1398 if (vif_priv->enable_beacon)
1399 schedule_work(&vif_priv->beacon_work.work);
1400 }
da81dede
JL		 1401}
1402
22bedad3
JP		 1403static u64 rtl8180_prepare_multicast(struct ieee80211_hw *dev,
1404 struct netdev_hw_addr_list *mc_list)
3ac64bee 1405{
22bedad3 1406 return netdev_hw_addr_list_count(mc_list);
3ac64bee
JB		 1407}
1408
f6532111
MW		 1409static void rtl8180_configure_filter(struct ieee80211_hw *dev,
1410 unsigned int changed_flags,
1411 unsigned int *total_flags,
3ac64bee 1412 u64 multicast)
f6532111
MW		 1413{
1414 struct rtl8180_priv *priv = dev->priv;
1415
1416 if (changed_flags & FIF_FCSFAIL)
1417 priv->rx_conf ^= RTL818X_RX_CONF_FCS;
1418 if (changed_flags & FIF_CONTROL)
1419 priv->rx_conf ^= RTL818X_RX_CONF_CTRL;
1420 if (changed_flags & FIF_OTHER_BSS)
1421 priv->rx_conf ^= RTL818X_RX_CONF_MONITOR;
3ac64bee 1422 if (*total_flags & FIF_ALLMULTI || multicast > 0)
f6532111
MW		 1423 priv->rx_conf |= RTL818X_RX_CONF_MULTICAST;
1424 else
1425 priv->rx_conf &= ~RTL818X_RX_CONF_MULTICAST;
1426
1427 *total_flags = 0;
1428
1429 if (priv->rx_conf & RTL818X_RX_CONF_FCS)
1430 *total_flags |= FIF_FCSFAIL;
1431 if (priv->rx_conf & RTL818X_RX_CONF_CTRL)
1432 *total_flags |= FIF_CONTROL;
1433 if (priv->rx_conf & RTL818X_RX_CONF_MONITOR)
1434 *total_flags |= FIF_OTHER_BSS;
1435 if (priv->rx_conf & RTL818X_RX_CONF_MULTICAST)
1436 *total_flags |= FIF_ALLMULTI;
1437
1438 rtl818x_iowrite32(priv, &priv->map->RX_CONF, priv->rx_conf);
1439}
1440
1441static const struct ieee80211_ops rtl8180_ops = {
1442 .tx = rtl8180_tx,
1443 .start = rtl8180_start,
1444 .stop = rtl8180_stop,
1445 .add_interface = rtl8180_add_interface,
1446 .remove_interface = rtl8180_remove_interface,
1447 .config = rtl8180_config,
da81dede 1448 .bss_info_changed = rtl8180_bss_info_changed,
9069af79 1449 .conf_tx = rtl8180_conf_tx,
3ac64bee 1450 .prepare_multicast = rtl8180_prepare_multicast,
f6532111 1451 .configure_filter = rtl8180_configure_filter,
d2bb8e02 1452 .get_tsf = rtl8180_get_tsf,
f6532111
MW		 1453};
1454
1455static void rtl8180_eeprom_register_read(struct eeprom_93cx6 *eeprom)
1456{
7d4b829a 1457 struct rtl8180_priv *priv = eeprom->data;
f6532111
MW		 1458 u8 reg = rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
1459
1460 eeprom->reg_data_in = reg & RTL818X_EEPROM_CMD_WRITE;
1461 eeprom->reg_data_out = reg & RTL818X_EEPROM_CMD_READ;
1462 eeprom->reg_data_clock = reg & RTL818X_EEPROM_CMD_CK;
1463 eeprom->reg_chip_select = reg & RTL818X_EEPROM_CMD_CS;
1464}
1465
1466static void rtl8180_eeprom_register_write(struct eeprom_93cx6 *eeprom)
1467{
7d4b829a 1468 struct rtl8180_priv *priv = eeprom->data;
f6532111
MW		 1469 u8 reg = 2 << 6;
1470
1471 if (eeprom->reg_data_in)
1472 reg |= RTL818X_EEPROM_CMD_WRITE;
1473 if (eeprom->reg_data_out)
1474 reg |= RTL818X_EEPROM_CMD_READ;
1475 if (eeprom->reg_data_clock)
1476 reg |= RTL818X_EEPROM_CMD_CK;
1477 if (eeprom->reg_chip_select)
1478 reg |= RTL818X_EEPROM_CMD_CS;
1479
1480 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, reg);
1481 rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
1482 udelay(10);
1483}
1484
7d4b829a
AM		 1485static void rtl8180_eeprom_read(struct rtl8180_priv *priv)
1486{
1487 struct eeprom_93cx6 eeprom;
1488 int eeprom_cck_table_adr;
1489 u16 eeprom_val;
1490 int i;
1491
1492 eeprom.data = priv;
1493 eeprom.register_read = rtl8180_eeprom_register_read;
1494 eeprom.register_write = rtl8180_eeprom_register_write;
1495 if (rtl818x_ioread32(priv, &priv->map->RX_CONF) & (1 << 6))
1496 eeprom.width = PCI_EEPROM_WIDTH_93C66;
1497 else
1498 eeprom.width = PCI_EEPROM_WIDTH_93C46;
1499
1500 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
1501 RTL818X_EEPROM_CMD_PROGRAM);
1502 rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
1503 udelay(10);
1504
1505 eeprom_93cx6_read(&eeprom, 0x06, &eeprom_val);
1506 eeprom_val &= 0xFF;
1507 priv->rf_type = eeprom_val;
1508
1509 eeprom_93cx6_read(&eeprom, 0x17, &eeprom_val);
1510 priv->csthreshold = eeprom_val >> 8;
1511
1512 eeprom_93cx6_multiread(&eeprom, 0x7, (__le16 *)priv->mac_addr, 3);
1513
fc32ac91
AM		 1514 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE)
1515 eeprom_cck_table_adr = 0x30;
1516 else
1517 eeprom_cck_table_adr = 0x10;
7d4b829a
AM		 1518
1519 /* CCK TX power */
1520 for (i = 0; i < 14; i += 2) {
1521 u16 txpwr;
1522 eeprom_93cx6_read(&eeprom, eeprom_cck_table_adr + (i >> 1),
1523 &txpwr);
1524 priv->channels[i].hw_value = txpwr & 0xFF;
1525 priv->channels[i + 1].hw_value = txpwr >> 8;
1526 }
1527
1528 /* OFDM TX power */
1529 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180) {
1530 for (i = 0; i < 14; i += 2) {
1531 u16 txpwr;
1532 eeprom_93cx6_read(&eeprom, 0x20 + (i >> 1), &txpwr);
1533 priv->channels[i].hw_value |= (txpwr & 0xFF) << 8;
1534 priv->channels[i + 1].hw_value |= txpwr & 0xFF00;
1535 }
1536 }
1537
1538 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180) {
1539 __le32 anaparam;
1540 eeprom_93cx6_multiread(&eeprom, 0xD, (__le16 *)&anaparam, 2);
1541 priv->anaparam = le32_to_cpu(anaparam);
1542 eeprom_93cx6_read(&eeprom, 0x19, &priv->rfparam);
1543 }
1544
fc32ac91
AM		 1545 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
1546 eeprom_93cx6_read(&eeprom, 0x3F, &eeprom_val);
1547 priv->antenna_diversity_en = !!(eeprom_val & 0x100);
1548 priv->antenna_diversity_default = (eeprom_val & 0xC00) == 0x400;
1549
1550 eeprom_93cx6_read(&eeprom, 0x7C, &eeprom_val);
1551 priv->xtal_out = eeprom_val & 0xF;
1552 priv->xtal_in = (eeprom_val & 0xF0) >> 4;
1553 priv->xtal_cal = !!(eeprom_val & 0x1000);
1554 priv->thermal_meter_val = (eeprom_val & 0xF00) >> 8;
1555 priv->thermal_meter_en = !!(eeprom_val & 0x2000);
1556 }
1557
7d4b829a
AM		 1558 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
1559 RTL818X_EEPROM_CMD_NORMAL);
1560}
1561
fb4e899d 1562static int rtl8180_probe(struct pci_dev *pdev,
f6532111
MW		 1563 const struct pci_device_id *id)
1564{
1565 struct ieee80211_hw *dev;
1566 struct rtl8180_priv *priv;
1567 unsigned long mem_addr, mem_len;
1568 unsigned int io_addr, io_len;
7d4b829a 1569 int err;
f6532111
MW		 1570 const char *chip_name, *rf_name = NULL;
1571 u32 reg;
f6532111
MW		 1572
1573 err = pci_enable_device(pdev);
1574 if (err) {
1575 printk(KERN_ERR "%s (rtl8180): Cannot enable new PCI device\n",
1576 pci_name(pdev));
1577 return err;
1578 }
1579
1580 err = pci_request_regions(pdev, KBUILD_MODNAME);
1581 if (err) {
1582 printk(KERN_ERR "%s (rtl8180): Cannot obtain PCI resources\n",
1583 pci_name(pdev));
1584 return err;
1585 }
1586
1587 io_addr = pci_resource_start(pdev, 0);
1588 io_len = pci_resource_len(pdev, 0);
1589 mem_addr = pci_resource_start(pdev, 1);
1590 mem_len = pci_resource_len(pdev, 1);
1591
1592 if (mem_len < sizeof(struct rtl818x_csr) ||
1593 io_len < sizeof(struct rtl818x_csr)) {
1594 printk(KERN_ERR "%s (rtl8180): Too short PCI resources\n",
1595 pci_name(pdev));
1596 err = -ENOMEM;
1597 goto err_free_reg;
1598 }
1599
9e385c56
JL		 1600 if ((err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) ||
1601 (err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))) {
f6532111
MW		 1602 printk(KERN_ERR "%s (rtl8180): No suitable DMA available\n",
1603 pci_name(pdev));
1604 goto err_free_reg;
1605 }
1606
1607 pci_set_master(pdev);
1608
1609 dev = ieee80211_alloc_hw(sizeof(*priv), &rtl8180_ops);
1610 if (!dev) {
1611 printk(KERN_ERR "%s (rtl8180): ieee80211 alloc failed\n",
1612 pci_name(pdev));
1613 err = -ENOMEM;
1614 goto err_free_reg;
1615 }
1616
1617 priv = dev->priv;
1618 priv->pdev = pdev;
1619
e6a9854b 1620 dev->max_rates = 2;
f6532111
MW		 1621 SET_IEEE80211_DEV(dev, &pdev->dev);
1622 pci_set_drvdata(pdev, dev);
1623
1624 priv->map = pci_iomap(pdev, 1, mem_len);
1625 if (!priv->map)
1626 priv->map = pci_iomap(pdev, 0, io_len);
1627
1628 if (!priv->map) {
1629 printk(KERN_ERR "%s (rtl8180): Cannot map device memory\n",
1630 pci_name(pdev));
1631 goto err_free_dev;
1632 }
1633
8318d78a
JB		 1634 BUILD_BUG_ON(sizeof(priv->channels) != sizeof(rtl818x_channels));
1635 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(rtl818x_rates));
1636
f6532111
MW		 1637 memcpy(priv->channels, rtl818x_channels, sizeof(rtl818x_channels));
1638 memcpy(priv->rates, rtl818x_rates, sizeof(rtl818x_rates));
8318d78a
JB		 1639
1640 priv->band.band = IEEE80211_BAND_2GHZ;
1641 priv->band.channels = priv->channels;
1642 priv->band.n_channels = ARRAY_SIZE(rtl818x_channels);
1643 priv->band.bitrates = priv->rates;
1644 priv->band.n_bitrates = 4;
1645 dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
1646
f6532111 1647 dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
566bfe5a
BR		 1648 IEEE80211_HW_RX_INCLUDES_FCS |
1649 IEEE80211_HW_SIGNAL_UNSPEC;
c809e86c
JL		 1650 dev->vif_data_size = sizeof(struct rtl8180_vif);
1651 dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
1652 BIT(NL80211_IFTYPE_ADHOC);
566bfe5a 1653 dev->max_signal = 65;
f6532111
MW		 1654
1655 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
1656 reg &= RTL818X_TX_CONF_HWVER_MASK;
1657 switch (reg) {
1658 case RTL818X_TX_CONF_R8180_ABCD:
1659 chip_name = "RTL8180";
6caefd12 1660 priv->chip_family = RTL818X_CHIP_FAMILY_RTL8180;
f6532111 1661 break;
6caefd12 1662
f6532111
MW		 1663 case RTL818X_TX_CONF_R8180_F:
1664 chip_name = "RTL8180vF";
6caefd12 1665 priv->chip_family = RTL818X_CHIP_FAMILY_RTL8180;
f6532111 1666 break;
6caefd12 1667
f6532111
MW		 1668 case RTL818X_TX_CONF_R8185_ABC:
1669 chip_name = "RTL8185";
6caefd12 1670 priv->chip_family = RTL818X_CHIP_FAMILY_RTL8185;
f6532111 1671 break;
6caefd12 1672
f6532111
MW		 1673 case RTL818X_TX_CONF_R8185_D:
1674 chip_name = "RTL8185vD";
6caefd12 1675 priv->chip_family = RTL818X_CHIP_FAMILY_RTL8185;
f6532111
MW		 1676 break;
1677 default:
1678 printk(KERN_ERR "%s (rtl8180): Unknown chip! (0x%x)\n",
1679 pci_name(pdev), reg >> 25);
1680 goto err_iounmap;
1681 }
1682
fd6564fc
AM		 1683 /* we declare to MAC80211 all the queues except for beacon queue
1684 * that will be eventually handled by DRV.
1685 * TX rings are arranged in such a way that lower is the IDX,
1686 * higher is the priority, in order to achieve direct mapping
1687 * with mac80211, however the beacon queue is an exception and it
1688 * is mapped on the highst tx ring IDX.
1689 */
1690 dev->queues = RTL8180_NR_TX_QUEUES - 1;
1691
6caefd12 1692 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180) {
8318d78a 1693 priv->band.n_bitrates = ARRAY_SIZE(rtl818x_rates);
f6532111
MW		 1694 pci_try_set_mwi(pdev);
1695 }
1696
7d4b829a 1697 rtl8180_eeprom_read(priv);
f6532111 1698
7d4b829a 1699 switch (priv->rf_type) {
f6532111
MW		 1700 case 1: rf_name = "Intersil";
1701 break;
1702 case 2: rf_name = "RFMD";
1703 break;
1704 case 3: priv->rf = &sa2400_rf_ops;
1705 break;
1706 case 4: priv->rf = &max2820_rf_ops;
1707 break;
1708 case 5: priv->rf = &grf5101_rf_ops;
1709 break;
1710 case 9: priv->rf = rtl8180_detect_rf(dev);
1711 break;
1712 case 10:
1713 rf_name = "RTL8255";
1714 break;
1715 default:
1716 printk(KERN_ERR "%s (rtl8180): Unknown RF! (0x%x)\n",
7d4b829a 1717 pci_name(pdev), priv->rf_type);
f6532111
MW		 1718 goto err_iounmap;
1719 }
1720
1721 if (!priv->rf) {
1722 printk(KERN_ERR "%s (rtl8180): %s RF frontend not supported!\n",
1723 pci_name(pdev), rf_name);
1724 goto err_iounmap;
1725 }
1726
7d4b829a 1727 if (!is_valid_ether_addr(priv->mac_addr)) {
f6532111
MW		 1728 printk(KERN_WARNING "%s (rtl8180): Invalid hwaddr! Using"
1729 " randomly generated MAC addr\n", pci_name(pdev));
7d4b829a 1730 eth_random_addr(priv->mac_addr);
f6532111 1731 }
7d4b829a 1732 SET_IEEE80211_PERM_ADDR(dev, priv->mac_addr);
f6532111
MW		 1733
1734 spin_lock_init(&priv->lock);
1735
1736 err = ieee80211_register_hw(dev);
1737 if (err) {
1738 printk(KERN_ERR "%s (rtl8180): Cannot register device\n",
1739 pci_name(pdev));
1740 goto err_iounmap;
1741 }
1742
c96c31e4 1743 wiphy_info(dev->wiphy, "hwaddr %pm, %s + %s\n",
7d4b829a 1744 priv->mac_addr, chip_name, priv->rf->name);
f6532111
MW		 1745
1746 return 0;
1747
1748 err_iounmap:
0269da28 1749 pci_iounmap(pdev, priv->map);
f6532111
MW		 1750
1751 err_free_dev:
f6532111
MW		 1752 ieee80211_free_hw(dev);
1753
1754 err_free_reg:
1755 pci_release_regions(pdev);
1756 pci_disable_device(pdev);
1757 return err;
1758}
1759
fb4e899d 1760static void rtl8180_remove(struct pci_dev *pdev)
f6532111
MW		 1761{
1762 struct ieee80211_hw *dev = pci_get_drvdata(pdev);
1763 struct rtl8180_priv *priv;
1764
1765 if (!dev)
1766 return;
1767
1768 ieee80211_unregister_hw(dev);
1769
1770 priv = dev->priv;
1771
1772 pci_iounmap(pdev, priv->map);
1773 pci_release_regions(pdev);
1774 pci_disable_device(pdev);
1775 ieee80211_free_hw(dev);
1776}
1777
1778#ifdef CONFIG_PM
1779static int rtl8180_suspend(struct pci_dev *pdev, pm_message_t state)
1780{
1781 pci_save_state(pdev);
1782 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1783 return 0;
1784}
1785
1786static int rtl8180_resume(struct pci_dev *pdev)
1787{
1788 pci_set_power_state(pdev, PCI_D0);
1789 pci_restore_state(pdev);
1790 return 0;
1791}
1792
1793#endif /* CONFIG_PM */
1794
1795static struct pci_driver rtl8180_driver = {
1796 .name = KBUILD_MODNAME,
1797 .id_table = rtl8180_table,
1798 .probe = rtl8180_probe,
fb4e899d 1799 .remove = rtl8180_remove,
f6532111
MW		 1800#ifdef CONFIG_PM
1801 .suspend = rtl8180_suspend,
1802 .resume = rtl8180_resume,
1803#endif /* CONFIG_PM */
1804};
1805
5b0a3b7e 1806module_pci_driver(rtl8180_driver);
Linux kernel - Deliverables
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