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f6532111 MW |
1 | |
2 | /* | |
3 | * Linux device driver for RTL8180 / RTL8185 | |
4 | * | |
5 | * Copyright 2007 Michael Wu <flamingice@sourmilk.net> | |
6 | * Copyright 2007 Andrea Merello <andreamrl@tiscali.it> | |
7 | * | |
8 | * Based on the r8180 driver, which is: | |
9 | * Copyright 2004-2005 Andrea Merello <andreamrl@tiscali.it>, et al. | |
10 | * | |
11 | * Thanks to Realtek for their support! | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License version 2 as | |
15 | * published by the Free Software Foundation. | |
16 | */ | |
17 | ||
18 | #include <linux/init.h> | |
a6b7a407 | 19 | #include <linux/interrupt.h> |
f6532111 | 20 | #include <linux/pci.h> |
5a0e3ad6 | 21 | #include <linux/slab.h> |
f6532111 MW |
22 | #include <linux/delay.h> |
23 | #include <linux/etherdevice.h> | |
24 | #include <linux/eeprom_93cx6.h> | |
9d9779e7 | 25 | #include <linux/module.h> |
f6532111 MW |
26 | #include <net/mac80211.h> |
27 | ||
28 | #include "rtl8180.h" | |
3cfeb0c3 JL |
29 | #include "rtl8225.h" |
30 | #include "sa2400.h" | |
31 | #include "max2820.h" | |
32 | #include "grf5101.h" | |
f6532111 MW |
33 | |
34 | MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>"); | |
35 | MODULE_AUTHOR("Andrea Merello <andreamrl@tiscali.it>"); | |
36 | MODULE_DESCRIPTION("RTL8180 / RTL8185 PCI wireless driver"); | |
37 | MODULE_LICENSE("GPL"); | |
38 | ||
a3aa1884 | 39 | static DEFINE_PCI_DEVICE_TABLE(rtl8180_table) = { |
f6532111 MW |
40 | /* rtl8185 */ |
41 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8185) }, | |
4fcc5470 | 42 | { PCI_DEVICE(PCI_VENDOR_ID_BELKIN, 0x700f) }, |
f6532111 MW |
43 | { PCI_DEVICE(PCI_VENDOR_ID_BELKIN, 0x701f) }, |
44 | ||
45 | /* rtl8180 */ | |
46 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8180) }, | |
47 | { PCI_DEVICE(0x1799, 0x6001) }, | |
48 | { PCI_DEVICE(0x1799, 0x6020) }, | |
49 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x3300) }, | |
29a6b508 XVP |
50 | { PCI_DEVICE(0x1186, 0x3301) }, |
51 | { PCI_DEVICE(0x1432, 0x7106) }, | |
f6532111 MW |
52 | { } |
53 | }; | |
54 | ||
55 | MODULE_DEVICE_TABLE(pci, rtl8180_table); | |
56 | ||
8318d78a JB |
57 | static const struct ieee80211_rate rtl818x_rates[] = { |
58 | { .bitrate = 10, .hw_value = 0, }, | |
59 | { .bitrate = 20, .hw_value = 1, }, | |
60 | { .bitrate = 55, .hw_value = 2, }, | |
61 | { .bitrate = 110, .hw_value = 3, }, | |
62 | { .bitrate = 60, .hw_value = 4, }, | |
63 | { .bitrate = 90, .hw_value = 5, }, | |
64 | { .bitrate = 120, .hw_value = 6, }, | |
65 | { .bitrate = 180, .hw_value = 7, }, | |
66 | { .bitrate = 240, .hw_value = 8, }, | |
67 | { .bitrate = 360, .hw_value = 9, }, | |
68 | { .bitrate = 480, .hw_value = 10, }, | |
69 | { .bitrate = 540, .hw_value = 11, }, | |
70 | }; | |
71 | ||
72 | static const struct ieee80211_channel rtl818x_channels[] = { | |
73 | { .center_freq = 2412 }, | |
74 | { .center_freq = 2417 }, | |
75 | { .center_freq = 2422 }, | |
76 | { .center_freq = 2427 }, | |
77 | { .center_freq = 2432 }, | |
78 | { .center_freq = 2437 }, | |
79 | { .center_freq = 2442 }, | |
80 | { .center_freq = 2447 }, | |
81 | { .center_freq = 2452 }, | |
82 | { .center_freq = 2457 }, | |
83 | { .center_freq = 2462 }, | |
84 | { .center_freq = 2467 }, | |
85 | { .center_freq = 2472 }, | |
86 | { .center_freq = 2484 }, | |
87 | }; | |
88 | ||
89 | ||
f6532111 MW |
90 | void rtl8180_write_phy(struct ieee80211_hw *dev, u8 addr, u32 data) |
91 | { | |
92 | struct rtl8180_priv *priv = dev->priv; | |
93 | int i = 10; | |
94 | u32 buf; | |
95 | ||
96 | buf = (data << 8) | addr; | |
97 | ||
98 | rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->PHY[0], buf | 0x80); | |
99 | while (i--) { | |
100 | rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->PHY[0], buf); | |
101 | if (rtl818x_ioread8(priv, &priv->map->PHY[2]) == (data & 0xFF)) | |
102 | return; | |
103 | } | |
104 | } | |
105 | ||
a6d27d2a | 106 | static void rtl8180_handle_rx(struct ieee80211_hw *dev) |
f6532111 MW |
107 | { |
108 | struct rtl8180_priv *priv = dev->priv; | |
a6d27d2a | 109 | unsigned int count = 32; |
8b73fb8e | 110 | u8 signal, agc, sq; |
f6532111 | 111 | |
a6d27d2a | 112 | while (count--) { |
f6532111 MW |
113 | struct rtl8180_rx_desc *entry = &priv->rx_ring[priv->rx_idx]; |
114 | struct sk_buff *skb = priv->rx_buf[priv->rx_idx]; | |
115 | u32 flags = le32_to_cpu(entry->flags); | |
116 | ||
38e3b0d8 | 117 | if (flags & RTL818X_RX_DESC_FLAG_OWN) |
a6d27d2a | 118 | return; |
f6532111 | 119 | |
38e3b0d8 HRK |
120 | if (unlikely(flags & (RTL818X_RX_DESC_FLAG_DMA_FAIL | |
121 | RTL818X_RX_DESC_FLAG_FOF | | |
122 | RTL818X_RX_DESC_FLAG_RX_ERR))) | |
f6532111 MW |
123 | goto done; |
124 | else { | |
125 | u32 flags2 = le32_to_cpu(entry->flags2); | |
126 | struct ieee80211_rx_status rx_status = {0}; | |
127 | struct sk_buff *new_skb = dev_alloc_skb(MAX_RX_SIZE); | |
128 | ||
129 | if (unlikely(!new_skb)) | |
130 | goto done; | |
131 | ||
132 | pci_unmap_single(priv->pdev, | |
133 | *((dma_addr_t *)skb->cb), | |
134 | MAX_RX_SIZE, PCI_DMA_FROMDEVICE); | |
135 | skb_put(skb, flags & 0xFFF); | |
136 | ||
137 | rx_status.antenna = (flags2 >> 15) & 1; | |
8318d78a | 138 | rx_status.rate_idx = (flags >> 20) & 0xF; |
8b73fb8e JL |
139 | agc = (flags2 >> 17) & 0x7F; |
140 | if (priv->r8185) { | |
141 | if (rx_status.rate_idx > 3) | |
142 | signal = 90 - clamp_t(u8, agc, 25, 90); | |
143 | else | |
144 | signal = 95 - clamp_t(u8, agc, 30, 95); | |
145 | } else { | |
146 | sq = flags2 & 0xff; | |
147 | signal = priv->rf->calc_rssi(agc, sq); | |
148 | } | |
8b74964c | 149 | rx_status.signal = signal; |
675a0b04 KB |
150 | rx_status.freq = dev->conf.chandef.chan->center_freq; |
151 | rx_status.band = dev->conf.chandef.chan->band; | |
f6532111 | 152 | rx_status.mactime = le64_to_cpu(entry->tsft); |
f4bda337 | 153 | rx_status.flag |= RX_FLAG_MACTIME_START; |
38e3b0d8 | 154 | if (flags & RTL818X_RX_DESC_FLAG_CRC32_ERR) |
f6532111 MW |
155 | rx_status.flag |= RX_FLAG_FAILED_FCS_CRC; |
156 | ||
f1d58c25 | 157 | memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status)); |
a6d27d2a | 158 | ieee80211_rx_irqsafe(dev, skb); |
f6532111 MW |
159 | |
160 | skb = new_skb; | |
161 | priv->rx_buf[priv->rx_idx] = skb; | |
162 | *((dma_addr_t *) skb->cb) = | |
163 | pci_map_single(priv->pdev, skb_tail_pointer(skb), | |
164 | MAX_RX_SIZE, PCI_DMA_FROMDEVICE); | |
165 | } | |
166 | ||
167 | done: | |
168 | entry->rx_buf = cpu_to_le32(*((dma_addr_t *)skb->cb)); | |
38e3b0d8 | 169 | entry->flags = cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN | |
f6532111 MW |
170 | MAX_RX_SIZE); |
171 | if (priv->rx_idx == 31) | |
38e3b0d8 | 172 | entry->flags |= cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR); |
f6532111 MW |
173 | priv->rx_idx = (priv->rx_idx + 1) % 32; |
174 | } | |
a6d27d2a JL |
175 | } |
176 | ||
177 | static void rtl8180_handle_tx(struct ieee80211_hw *dev, unsigned int prio) | |
178 | { | |
179 | struct rtl8180_priv *priv = dev->priv; | |
180 | struct rtl8180_tx_ring *ring = &priv->tx_ring[prio]; | |
e6a9854b | 181 | |
a6d27d2a JL |
182 | while (skb_queue_len(&ring->queue)) { |
183 | struct rtl8180_tx_desc *entry = &ring->desc[ring->idx]; | |
184 | struct sk_buff *skb; | |
185 | struct ieee80211_tx_info *info; | |
186 | u32 flags = le32_to_cpu(entry->flags); | |
f6532111 | 187 | |
a6d27d2a JL |
188 | if (flags & RTL818X_TX_DESC_FLAG_OWN) |
189 | return; | |
190 | ||
191 | ring->idx = (ring->idx + 1) % ring->entries; | |
192 | skb = __skb_dequeue(&ring->queue); | |
193 | pci_unmap_single(priv->pdev, le32_to_cpu(entry->tx_buf), | |
194 | skb->len, PCI_DMA_TODEVICE); | |
195 | ||
196 | info = IEEE80211_SKB_CB(skb); | |
197 | ieee80211_tx_info_clear_status(info); | |
198 | ||
199 | if (!(info->flags & IEEE80211_TX_CTL_NO_ACK) && | |
200 | (flags & RTL818X_TX_DESC_FLAG_TX_OK)) | |
201 | info->flags |= IEEE80211_TX_STAT_ACK; | |
202 | ||
203 | info->status.rates[0].count = (flags & 0xFF) + 1; | |
204 | info->status.rates[1].idx = -1; | |
030725d2 | 205 | |
a6d27d2a JL |
206 | ieee80211_tx_status_irqsafe(dev, skb); |
207 | if (ring->entries - skb_queue_len(&ring->queue) == 2) | |
208 | ieee80211_wake_queue(dev, prio); | |
209 | } | |
f6532111 MW |
210 | } |
211 | ||
212 | static irqreturn_t rtl8180_interrupt(int irq, void *dev_id) | |
213 | { | |
214 | struct ieee80211_hw *dev = dev_id; | |
215 | struct rtl8180_priv *priv = dev->priv; | |
216 | u16 reg; | |
217 | ||
a6d27d2a | 218 | spin_lock(&priv->lock); |
f6532111 | 219 | reg = rtl818x_ioread16(priv, &priv->map->INT_STATUS); |
a6d27d2a JL |
220 | if (unlikely(reg == 0xFFFF)) { |
221 | spin_unlock(&priv->lock); | |
f6532111 | 222 | return IRQ_HANDLED; |
a6d27d2a | 223 | } |
f6532111 MW |
224 | |
225 | rtl818x_iowrite16(priv, &priv->map->INT_STATUS, reg); | |
226 | ||
a6d27d2a JL |
227 | if (reg & (RTL818X_INT_TXB_OK | RTL818X_INT_TXB_ERR)) |
228 | rtl8180_handle_tx(dev, 3); | |
229 | ||
230 | if (reg & (RTL818X_INT_TXH_OK | RTL818X_INT_TXH_ERR)) | |
231 | rtl8180_handle_tx(dev, 2); | |
232 | ||
233 | if (reg & (RTL818X_INT_TXN_OK | RTL818X_INT_TXN_ERR)) | |
234 | rtl8180_handle_tx(dev, 1); | |
f6532111 | 235 | |
a6d27d2a JL |
236 | if (reg & (RTL818X_INT_TXL_OK | RTL818X_INT_TXL_ERR)) |
237 | rtl8180_handle_tx(dev, 0); | |
238 | ||
239 | if (reg & (RTL818X_INT_RX_OK | RTL818X_INT_RX_ERR)) | |
240 | rtl8180_handle_rx(dev); | |
241 | ||
242 | spin_unlock(&priv->lock); | |
f6532111 MW |
243 | |
244 | return IRQ_HANDLED; | |
245 | } | |
246 | ||
36323f81 TH |
247 | static void rtl8180_tx(struct ieee80211_hw *dev, |
248 | struct ieee80211_tx_control *control, | |
249 | struct sk_buff *skb) | |
f6532111 | 250 | { |
e039fa4a | 251 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
51e080de | 252 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
f6532111 MW |
253 | struct rtl8180_priv *priv = dev->priv; |
254 | struct rtl8180_tx_ring *ring; | |
255 | struct rtl8180_tx_desc *entry; | |
a6d27d2a | 256 | unsigned long flags; |
f6532111 MW |
257 | unsigned int idx, prio; |
258 | dma_addr_t mapping; | |
259 | u32 tx_flags; | |
e6a9854b | 260 | u8 rc_flags; |
f6532111 MW |
261 | u16 plcp_len = 0; |
262 | __le16 rts_duration = 0; | |
263 | ||
e2530083 | 264 | prio = skb_get_queue_mapping(skb); |
f6532111 MW |
265 | ring = &priv->tx_ring[prio]; |
266 | ||
267 | mapping = pci_map_single(priv->pdev, skb->data, | |
268 | skb->len, PCI_DMA_TODEVICE); | |
269 | ||
38e3b0d8 HRK |
270 | tx_flags = RTL818X_TX_DESC_FLAG_OWN | RTL818X_TX_DESC_FLAG_FS | |
271 | RTL818X_TX_DESC_FLAG_LS | | |
e039fa4a | 272 | (ieee80211_get_tx_rate(dev, info)->hw_value << 24) | |
2e92e6f2 | 273 | skb->len; |
f6532111 MW |
274 | |
275 | if (priv->r8185) | |
38e3b0d8 HRK |
276 | tx_flags |= RTL818X_TX_DESC_FLAG_DMA | |
277 | RTL818X_TX_DESC_FLAG_NO_ENC; | |
f6532111 | 278 | |
e6a9854b JB |
279 | rc_flags = info->control.rates[0].flags; |
280 | if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) { | |
38e3b0d8 | 281 | tx_flags |= RTL818X_TX_DESC_FLAG_RTS; |
e039fa4a | 282 | tx_flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19; |
e6a9854b | 283 | } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { |
38e3b0d8 | 284 | tx_flags |= RTL818X_TX_DESC_FLAG_CTS; |
e039fa4a | 285 | tx_flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19; |
aa68cbfb | 286 | } |
f6532111 | 287 | |
e6a9854b | 288 | if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) |
32bfd35d | 289 | rts_duration = ieee80211_rts_duration(dev, priv->vif, skb->len, |
e039fa4a | 290 | info); |
f6532111 MW |
291 | |
292 | if (!priv->r8185) { | |
293 | unsigned int remainder; | |
294 | ||
295 | plcp_len = DIV_ROUND_UP(16 * (skb->len + 4), | |
e039fa4a | 296 | (ieee80211_get_tx_rate(dev, info)->bitrate * 2) / 10); |
f6532111 | 297 | remainder = (16 * (skb->len + 4)) % |
e039fa4a | 298 | ((ieee80211_get_tx_rate(dev, info)->bitrate * 2) / 10); |
35a0ace7 | 299 | if (remainder <= 6) |
f6532111 MW |
300 | plcp_len |= 1 << 15; |
301 | } | |
302 | ||
a6d27d2a | 303 | spin_lock_irqsave(&priv->lock, flags); |
51e080de JL |
304 | |
305 | if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { | |
306 | if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) | |
307 | priv->seqno += 0x10; | |
308 | hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); | |
309 | hdr->seq_ctrl |= cpu_to_le16(priv->seqno); | |
310 | } | |
311 | ||
f6532111 MW |
312 | idx = (ring->idx + skb_queue_len(&ring->queue)) % ring->entries; |
313 | entry = &ring->desc[idx]; | |
314 | ||
315 | entry->rts_duration = rts_duration; | |
316 | entry->plcp_len = cpu_to_le16(plcp_len); | |
317 | entry->tx_buf = cpu_to_le32(mapping); | |
318 | entry->frame_len = cpu_to_le32(skb->len); | |
e6a9854b | 319 | entry->flags2 = info->control.rates[1].idx >= 0 ? |
870abdf6 | 320 | ieee80211_get_alt_retry_rate(dev, info, 0)->bitrate << 4 : 0; |
e6a9854b | 321 | entry->retry_limit = info->control.rates[0].count; |
f6532111 MW |
322 | entry->flags = cpu_to_le32(tx_flags); |
323 | __skb_queue_tail(&ring->queue, skb); | |
324 | if (ring->entries - skb_queue_len(&ring->queue) < 2) | |
d10e2e02 | 325 | ieee80211_stop_queue(dev, prio); |
51e080de | 326 | |
a6d27d2a | 327 | spin_unlock_irqrestore(&priv->lock, flags); |
f6532111 MW |
328 | |
329 | rtl818x_iowrite8(priv, &priv->map->TX_DMA_POLLING, (1 << (prio + 4))); | |
f6532111 MW |
330 | } |
331 | ||
332 | void rtl8180_set_anaparam(struct rtl8180_priv *priv, u32 anaparam) | |
333 | { | |
334 | u8 reg; | |
335 | ||
336 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG); | |
337 | reg = rtl818x_ioread8(priv, &priv->map->CONFIG3); | |
338 | rtl818x_iowrite8(priv, &priv->map->CONFIG3, | |
339 | reg | RTL818X_CONFIG3_ANAPARAM_WRITE); | |
340 | rtl818x_iowrite32(priv, &priv->map->ANAPARAM, anaparam); | |
341 | rtl818x_iowrite8(priv, &priv->map->CONFIG3, | |
342 | reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE); | |
343 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL); | |
344 | } | |
345 | ||
346 | static int rtl8180_init_hw(struct ieee80211_hw *dev) | |
347 | { | |
348 | struct rtl8180_priv *priv = dev->priv; | |
349 | u16 reg; | |
350 | ||
351 | rtl818x_iowrite8(priv, &priv->map->CMD, 0); | |
352 | rtl818x_ioread8(priv, &priv->map->CMD); | |
353 | msleep(10); | |
354 | ||
355 | /* reset */ | |
356 | rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0); | |
357 | rtl818x_ioread8(priv, &priv->map->CMD); | |
358 | ||
359 | reg = rtl818x_ioread8(priv, &priv->map->CMD); | |
360 | reg &= (1 << 1); | |
361 | reg |= RTL818X_CMD_RESET; | |
362 | rtl818x_iowrite8(priv, &priv->map->CMD, RTL818X_CMD_RESET); | |
363 | rtl818x_ioread8(priv, &priv->map->CMD); | |
364 | msleep(200); | |
365 | ||
366 | /* check success of reset */ | |
367 | if (rtl818x_ioread8(priv, &priv->map->CMD) & RTL818X_CMD_RESET) { | |
c96c31e4 | 368 | wiphy_err(dev->wiphy, "reset timeout!\n"); |
f6532111 MW |
369 | return -ETIMEDOUT; |
370 | } | |
371 | ||
372 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_LOAD); | |
373 | rtl818x_ioread8(priv, &priv->map->CMD); | |
374 | msleep(200); | |
375 | ||
376 | if (rtl818x_ioread8(priv, &priv->map->CONFIG3) & (1 << 3)) { | |
377 | /* For cardbus */ | |
378 | reg = rtl818x_ioread8(priv, &priv->map->CONFIG3); | |
379 | reg |= 1 << 1; | |
380 | rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg); | |
381 | reg = rtl818x_ioread16(priv, &priv->map->FEMR); | |
382 | reg |= (1 << 15) | (1 << 14) | (1 << 4); | |
383 | rtl818x_iowrite16(priv, &priv->map->FEMR, reg); | |
384 | } | |
385 | ||
386 | rtl818x_iowrite8(priv, &priv->map->MSR, 0); | |
387 | ||
388 | if (!priv->r8185) | |
389 | rtl8180_set_anaparam(priv, priv->anaparam); | |
390 | ||
391 | rtl818x_iowrite32(priv, &priv->map->RDSAR, priv->rx_ring_dma); | |
392 | rtl818x_iowrite32(priv, &priv->map->TBDA, priv->tx_ring[3].dma); | |
393 | rtl818x_iowrite32(priv, &priv->map->THPDA, priv->tx_ring[2].dma); | |
394 | rtl818x_iowrite32(priv, &priv->map->TNPDA, priv->tx_ring[1].dma); | |
395 | rtl818x_iowrite32(priv, &priv->map->TLPDA, priv->tx_ring[0].dma); | |
396 | ||
397 | /* TODO: necessary? specs indicate not */ | |
398 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG); | |
399 | reg = rtl818x_ioread8(priv, &priv->map->CONFIG2); | |
400 | rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg & ~(1 << 3)); | |
401 | if (priv->r8185) { | |
402 | reg = rtl818x_ioread8(priv, &priv->map->CONFIG2); | |
403 | rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg | (1 << 4)); | |
404 | } | |
405 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL); | |
406 | ||
407 | /* TODO: set CONFIG5 for calibrating AGC on rtl8180 + philips radio? */ | |
408 | ||
409 | /* TODO: turn off hw wep on rtl8180 */ | |
410 | ||
411 | rtl818x_iowrite32(priv, &priv->map->INT_TIMEOUT, 0); | |
412 | ||
413 | if (priv->r8185) { | |
414 | rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0); | |
415 | rtl818x_iowrite8(priv, &priv->map->RATE_FALLBACK, 0x81); | |
416 | rtl818x_iowrite8(priv, &priv->map->RESP_RATE, (8 << 4) | 0); | |
417 | ||
418 | rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3); | |
419 | ||
420 | /* TODO: set ClkRun enable? necessary? */ | |
421 | reg = rtl818x_ioread8(priv, &priv->map->GP_ENABLE); | |
422 | rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, reg & ~(1 << 6)); | |
423 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG); | |
424 | reg = rtl818x_ioread8(priv, &priv->map->CONFIG3); | |
425 | rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg | (1 << 2)); | |
426 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL); | |
427 | } else { | |
428 | rtl818x_iowrite16(priv, &priv->map->BRSR, 0x1); | |
429 | rtl818x_iowrite8(priv, &priv->map->SECURITY, 0); | |
430 | ||
431 | rtl818x_iowrite8(priv, &priv->map->PHY_DELAY, 0x6); | |
432 | rtl818x_iowrite8(priv, &priv->map->CARRIER_SENSE_COUNTER, 0x4C); | |
433 | } | |
434 | ||
435 | priv->rf->init(dev); | |
436 | if (priv->r8185) | |
437 | rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3); | |
438 | return 0; | |
439 | } | |
440 | ||
441 | static int rtl8180_init_rx_ring(struct ieee80211_hw *dev) | |
442 | { | |
443 | struct rtl8180_priv *priv = dev->priv; | |
444 | struct rtl8180_rx_desc *entry; | |
445 | int i; | |
446 | ||
447 | priv->rx_ring = pci_alloc_consistent(priv->pdev, | |
448 | sizeof(*priv->rx_ring) * 32, | |
449 | &priv->rx_ring_dma); | |
450 | ||
451 | if (!priv->rx_ring || (unsigned long)priv->rx_ring & 0xFF) { | |
5db55844 | 452 | wiphy_err(dev->wiphy, "Cannot allocate RX ring\n"); |
f6532111 MW |
453 | return -ENOMEM; |
454 | } | |
455 | ||
456 | memset(priv->rx_ring, 0, sizeof(*priv->rx_ring) * 32); | |
457 | priv->rx_idx = 0; | |
458 | ||
459 | for (i = 0; i < 32; i++) { | |
460 | struct sk_buff *skb = dev_alloc_skb(MAX_RX_SIZE); | |
461 | dma_addr_t *mapping; | |
462 | entry = &priv->rx_ring[i]; | |
463 | if (!skb) | |
464 | return 0; | |
465 | ||
466 | priv->rx_buf[i] = skb; | |
467 | mapping = (dma_addr_t *)skb->cb; | |
468 | *mapping = pci_map_single(priv->pdev, skb_tail_pointer(skb), | |
469 | MAX_RX_SIZE, PCI_DMA_FROMDEVICE); | |
470 | entry->rx_buf = cpu_to_le32(*mapping); | |
38e3b0d8 | 471 | entry->flags = cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN | |
f6532111 MW |
472 | MAX_RX_SIZE); |
473 | } | |
38e3b0d8 | 474 | entry->flags |= cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR); |
f6532111 MW |
475 | return 0; |
476 | } | |
477 | ||
478 | static void rtl8180_free_rx_ring(struct ieee80211_hw *dev) | |
479 | { | |
480 | struct rtl8180_priv *priv = dev->priv; | |
481 | int i; | |
482 | ||
483 | for (i = 0; i < 32; i++) { | |
484 | struct sk_buff *skb = priv->rx_buf[i]; | |
485 | if (!skb) | |
486 | continue; | |
487 | ||
488 | pci_unmap_single(priv->pdev, | |
489 | *((dma_addr_t *)skb->cb), | |
490 | MAX_RX_SIZE, PCI_DMA_FROMDEVICE); | |
491 | kfree_skb(skb); | |
492 | } | |
493 | ||
494 | pci_free_consistent(priv->pdev, sizeof(*priv->rx_ring) * 32, | |
495 | priv->rx_ring, priv->rx_ring_dma); | |
496 | priv->rx_ring = NULL; | |
497 | } | |
498 | ||
499 | static int rtl8180_init_tx_ring(struct ieee80211_hw *dev, | |
500 | unsigned int prio, unsigned int entries) | |
501 | { | |
502 | struct rtl8180_priv *priv = dev->priv; | |
503 | struct rtl8180_tx_desc *ring; | |
504 | dma_addr_t dma; | |
505 | int i; | |
506 | ||
507 | ring = pci_alloc_consistent(priv->pdev, sizeof(*ring) * entries, &dma); | |
508 | if (!ring || (unsigned long)ring & 0xFF) { | |
5db55844 | 509 | wiphy_err(dev->wiphy, "Cannot allocate TX ring (prio = %d)\n", |
c96c31e4 | 510 | prio); |
f6532111 MW |
511 | return -ENOMEM; |
512 | } | |
513 | ||
514 | memset(ring, 0, sizeof(*ring)*entries); | |
515 | priv->tx_ring[prio].desc = ring; | |
516 | priv->tx_ring[prio].dma = dma; | |
517 | priv->tx_ring[prio].idx = 0; | |
518 | priv->tx_ring[prio].entries = entries; | |
519 | skb_queue_head_init(&priv->tx_ring[prio].queue); | |
520 | ||
521 | for (i = 0; i < entries; i++) | |
522 | ring[i].next_tx_desc = | |
523 | cpu_to_le32((u32)dma + ((i + 1) % entries) * sizeof(*ring)); | |
524 | ||
525 | return 0; | |
526 | } | |
527 | ||
528 | static void rtl8180_free_tx_ring(struct ieee80211_hw *dev, unsigned int prio) | |
529 | { | |
530 | struct rtl8180_priv *priv = dev->priv; | |
531 | struct rtl8180_tx_ring *ring = &priv->tx_ring[prio]; | |
532 | ||
533 | while (skb_queue_len(&ring->queue)) { | |
534 | struct rtl8180_tx_desc *entry = &ring->desc[ring->idx]; | |
535 | struct sk_buff *skb = __skb_dequeue(&ring->queue); | |
536 | ||
537 | pci_unmap_single(priv->pdev, le32_to_cpu(entry->tx_buf), | |
538 | skb->len, PCI_DMA_TODEVICE); | |
f6532111 MW |
539 | kfree_skb(skb); |
540 | ring->idx = (ring->idx + 1) % ring->entries; | |
541 | } | |
542 | ||
543 | pci_free_consistent(priv->pdev, sizeof(*ring->desc)*ring->entries, | |
544 | ring->desc, ring->dma); | |
545 | ring->desc = NULL; | |
546 | } | |
547 | ||
548 | static int rtl8180_start(struct ieee80211_hw *dev) | |
549 | { | |
550 | struct rtl8180_priv *priv = dev->priv; | |
551 | int ret, i; | |
552 | u32 reg; | |
553 | ||
554 | ret = rtl8180_init_rx_ring(dev); | |
555 | if (ret) | |
556 | return ret; | |
557 | ||
558 | for (i = 0; i < 4; i++) | |
559 | if ((ret = rtl8180_init_tx_ring(dev, i, 16))) | |
560 | goto err_free_rings; | |
561 | ||
562 | ret = rtl8180_init_hw(dev); | |
563 | if (ret) | |
564 | goto err_free_rings; | |
565 | ||
566 | rtl818x_iowrite32(priv, &priv->map->RDSAR, priv->rx_ring_dma); | |
567 | rtl818x_iowrite32(priv, &priv->map->TBDA, priv->tx_ring[3].dma); | |
568 | rtl818x_iowrite32(priv, &priv->map->THPDA, priv->tx_ring[2].dma); | |
569 | rtl818x_iowrite32(priv, &priv->map->TNPDA, priv->tx_ring[1].dma); | |
570 | rtl818x_iowrite32(priv, &priv->map->TLPDA, priv->tx_ring[0].dma); | |
571 | ||
ea31ba35 | 572 | ret = request_irq(priv->pdev->irq, rtl8180_interrupt, |
f6532111 MW |
573 | IRQF_SHARED, KBUILD_MODNAME, dev); |
574 | if (ret) { | |
5db55844 | 575 | wiphy_err(dev->wiphy, "failed to register IRQ handler\n"); |
f6532111 MW |
576 | goto err_free_rings; |
577 | } | |
578 | ||
579 | rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF); | |
580 | ||
581 | rtl818x_iowrite32(priv, &priv->map->MAR[0], ~0); | |
582 | rtl818x_iowrite32(priv, &priv->map->MAR[1], ~0); | |
583 | ||
584 | reg = RTL818X_RX_CONF_ONLYERLPKT | | |
585 | RTL818X_RX_CONF_RX_AUTORESETPHY | | |
586 | RTL818X_RX_CONF_MGMT | | |
587 | RTL818X_RX_CONF_DATA | | |
588 | (7 << 8 /* MAX RX DMA */) | | |
589 | RTL818X_RX_CONF_BROADCAST | | |
590 | RTL818X_RX_CONF_NICMAC; | |
591 | ||
592 | if (priv->r8185) | |
593 | reg |= RTL818X_RX_CONF_CSDM1 | RTL818X_RX_CONF_CSDM2; | |
594 | else { | |
595 | reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE1) | |
596 | ? RTL818X_RX_CONF_CSDM1 : 0; | |
597 | reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE2) | |
598 | ? RTL818X_RX_CONF_CSDM2 : 0; | |
599 | } | |
600 | ||
601 | priv->rx_conf = reg; | |
602 | rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg); | |
603 | ||
604 | if (priv->r8185) { | |
605 | reg = rtl818x_ioread8(priv, &priv->map->CW_CONF); | |
606 | reg &= ~RTL818X_CW_CONF_PERPACKET_CW_SHIFT; | |
607 | reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT; | |
608 | rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg); | |
609 | ||
610 | reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL); | |
611 | reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT; | |
612 | reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT; | |
613 | reg |= RTL818X_TX_AGC_CTL_FEEDBACK_ANT; | |
614 | rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg); | |
615 | ||
616 | /* disable early TX */ | |
617 | rtl818x_iowrite8(priv, (u8 __iomem *)priv->map + 0xec, 0x3f); | |
618 | } | |
619 | ||
620 | reg = rtl818x_ioread32(priv, &priv->map->TX_CONF); | |
621 | reg |= (6 << 21 /* MAX TX DMA */) | | |
622 | RTL818X_TX_CONF_NO_ICV; | |
623 | ||
624 | if (priv->r8185) | |
625 | reg &= ~RTL818X_TX_CONF_PROBE_DTS; | |
626 | else | |
627 | reg &= ~RTL818X_TX_CONF_HW_SEQNUM; | |
628 | ||
629 | /* different meaning, same value on both rtl8185 and rtl8180 */ | |
630 | reg &= ~RTL818X_TX_CONF_SAT_HWPLCP; | |
631 | ||
632 | rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg); | |
633 | ||
634 | reg = rtl818x_ioread8(priv, &priv->map->CMD); | |
635 | reg |= RTL818X_CMD_RX_ENABLE; | |
636 | reg |= RTL818X_CMD_TX_ENABLE; | |
637 | rtl818x_iowrite8(priv, &priv->map->CMD, reg); | |
638 | ||
f6532111 MW |
639 | return 0; |
640 | ||
641 | err_free_rings: | |
642 | rtl8180_free_rx_ring(dev); | |
643 | for (i = 0; i < 4; i++) | |
644 | if (priv->tx_ring[i].desc) | |
645 | rtl8180_free_tx_ring(dev, i); | |
646 | ||
647 | return ret; | |
648 | } | |
649 | ||
650 | static void rtl8180_stop(struct ieee80211_hw *dev) | |
651 | { | |
652 | struct rtl8180_priv *priv = dev->priv; | |
653 | u8 reg; | |
654 | int i; | |
655 | ||
f6532111 MW |
656 | rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0); |
657 | ||
658 | reg = rtl818x_ioread8(priv, &priv->map->CMD); | |
659 | reg &= ~RTL818X_CMD_TX_ENABLE; | |
660 | reg &= ~RTL818X_CMD_RX_ENABLE; | |
661 | rtl818x_iowrite8(priv, &priv->map->CMD, reg); | |
662 | ||
663 | priv->rf->stop(dev); | |
664 | ||
665 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG); | |
666 | reg = rtl818x_ioread8(priv, &priv->map->CONFIG4); | |
667 | rtl818x_iowrite8(priv, &priv->map->CONFIG4, reg | RTL818X_CONFIG4_VCOOFF); | |
668 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL); | |
669 | ||
670 | free_irq(priv->pdev->irq, dev); | |
671 | ||
672 | rtl8180_free_rx_ring(dev); | |
673 | for (i = 0; i < 4; i++) | |
674 | rtl8180_free_tx_ring(dev, i); | |
675 | } | |
676 | ||
37a41b4a EP |
677 | static u64 rtl8180_get_tsf(struct ieee80211_hw *dev, |
678 | struct ieee80211_vif *vif) | |
c809e86c JL |
679 | { |
680 | struct rtl8180_priv *priv = dev->priv; | |
681 | ||
682 | return rtl818x_ioread32(priv, &priv->map->TSFT[0]) | | |
683 | (u64)(rtl818x_ioread32(priv, &priv->map->TSFT[1])) << 32; | |
684 | } | |
685 | ||
a3275e24 | 686 | static void rtl8180_beacon_work(struct work_struct *work) |
c809e86c JL |
687 | { |
688 | struct rtl8180_vif *vif_priv = | |
689 | container_of(work, struct rtl8180_vif, beacon_work.work); | |
690 | struct ieee80211_vif *vif = | |
691 | container_of((void *)vif_priv, struct ieee80211_vif, drv_priv); | |
692 | struct ieee80211_hw *dev = vif_priv->dev; | |
693 | struct ieee80211_mgmt *mgmt; | |
694 | struct sk_buff *skb; | |
c809e86c JL |
695 | |
696 | /* don't overflow the tx ring */ | |
697 | if (ieee80211_queue_stopped(dev, 0)) | |
698 | goto resched; | |
699 | ||
700 | /* grab a fresh beacon */ | |
701 | skb = ieee80211_beacon_get(dev, vif); | |
8f1d2d2b JL |
702 | if (!skb) |
703 | goto resched; | |
c809e86c JL |
704 | |
705 | /* | |
706 | * update beacon timestamp w/ TSF value | |
707 | * TODO: make hardware update beacon timestamp | |
708 | */ | |
709 | mgmt = (struct ieee80211_mgmt *)skb->data; | |
37a41b4a | 710 | mgmt->u.beacon.timestamp = cpu_to_le64(rtl8180_get_tsf(dev, vif)); |
c809e86c JL |
711 | |
712 | /* TODO: use actual beacon queue */ | |
713 | skb_set_queue_mapping(skb, 0); | |
714 | ||
36323f81 | 715 | rtl8180_tx(dev, NULL, skb); |
c809e86c JL |
716 | |
717 | resched: | |
718 | /* | |
719 | * schedule next beacon | |
720 | * TODO: use hardware support for beacon timing | |
721 | */ | |
722 | schedule_delayed_work(&vif_priv->beacon_work, | |
723 | usecs_to_jiffies(1024 * vif->bss_conf.beacon_int)); | |
724 | } | |
725 | ||
f6532111 | 726 | static int rtl8180_add_interface(struct ieee80211_hw *dev, |
1ed32e4f | 727 | struct ieee80211_vif *vif) |
f6532111 MW |
728 | { |
729 | struct rtl8180_priv *priv = dev->priv; | |
c809e86c | 730 | struct rtl8180_vif *vif_priv; |
f6532111 | 731 | |
643aab67 JL |
732 | /* |
733 | * We only support one active interface at a time. | |
734 | */ | |
735 | if (priv->vif) | |
736 | return -EBUSY; | |
f6532111 | 737 | |
1ed32e4f | 738 | switch (vif->type) { |
05c914fe | 739 | case NL80211_IFTYPE_STATION: |
c809e86c | 740 | case NL80211_IFTYPE_ADHOC: |
f6532111 MW |
741 | break; |
742 | default: | |
743 | return -EOPNOTSUPP; | |
744 | } | |
745 | ||
1ed32e4f | 746 | priv->vif = vif; |
32bfd35d | 747 | |
c809e86c JL |
748 | /* Initialize driver private area */ |
749 | vif_priv = (struct rtl8180_vif *)&vif->drv_priv; | |
750 | vif_priv->dev = dev; | |
751 | INIT_DELAYED_WORK(&vif_priv->beacon_work, rtl8180_beacon_work); | |
752 | vif_priv->enable_beacon = false; | |
753 | ||
f6532111 MW |
754 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG); |
755 | rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->MAC[0], | |
1ed32e4f | 756 | le32_to_cpu(*(__le32 *)vif->addr)); |
f6532111 | 757 | rtl818x_iowrite16(priv, (__le16 __iomem *)&priv->map->MAC[4], |
1ed32e4f | 758 | le16_to_cpu(*(__le16 *)(vif->addr + 4))); |
f6532111 MW |
759 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL); |
760 | ||
761 | return 0; | |
762 | } | |
763 | ||
764 | static void rtl8180_remove_interface(struct ieee80211_hw *dev, | |
1ed32e4f | 765 | struct ieee80211_vif *vif) |
f6532111 MW |
766 | { |
767 | struct rtl8180_priv *priv = dev->priv; | |
32bfd35d | 768 | priv->vif = NULL; |
f6532111 MW |
769 | } |
770 | ||
e8975581 | 771 | static int rtl8180_config(struct ieee80211_hw *dev, u32 changed) |
f6532111 MW |
772 | { |
773 | struct rtl8180_priv *priv = dev->priv; | |
e8975581 | 774 | struct ieee80211_conf *conf = &dev->conf; |
f6532111 MW |
775 | |
776 | priv->rf->set_chan(dev, conf); | |
777 | ||
778 | return 0; | |
779 | } | |
780 | ||
da81dede JL |
781 | static void rtl8180_bss_info_changed(struct ieee80211_hw *dev, |
782 | struct ieee80211_vif *vif, | |
783 | struct ieee80211_bss_conf *info, | |
784 | u32 changed) | |
785 | { | |
786 | struct rtl8180_priv *priv = dev->priv; | |
c809e86c | 787 | struct rtl8180_vif *vif_priv; |
2d0ddec5 | 788 | int i; |
0f956e71 | 789 | u8 reg; |
2d0ddec5 | 790 | |
c809e86c JL |
791 | vif_priv = (struct rtl8180_vif *)&vif->drv_priv; |
792 | ||
2d0ddec5 JB |
793 | if (changed & BSS_CHANGED_BSSID) { |
794 | for (i = 0; i < ETH_ALEN; i++) | |
795 | rtl818x_iowrite8(priv, &priv->map->BSSID[i], | |
796 | info->bssid[i]); | |
797 | ||
0f956e71 JL |
798 | if (is_valid_ether_addr(info->bssid)) { |
799 | if (vif->type == NL80211_IFTYPE_ADHOC) | |
800 | reg = RTL818X_MSR_ADHOC; | |
801 | else | |
802 | reg = RTL818X_MSR_INFRA; | |
803 | } else | |
804 | reg = RTL818X_MSR_NO_LINK; | |
805 | rtl818x_iowrite8(priv, &priv->map->MSR, reg); | |
2d0ddec5 | 806 | } |
da81dede JL |
807 | |
808 | if (changed & BSS_CHANGED_ERP_SLOT && priv->rf->conf_erp) | |
c809e86c JL |
809 | priv->rf->conf_erp(dev, info); |
810 | ||
811 | if (changed & BSS_CHANGED_BEACON_ENABLED) | |
812 | vif_priv->enable_beacon = info->enable_beacon; | |
813 | ||
814 | if (changed & (BSS_CHANGED_BEACON_ENABLED | BSS_CHANGED_BEACON)) { | |
815 | cancel_delayed_work_sync(&vif_priv->beacon_work); | |
816 | if (vif_priv->enable_beacon) | |
817 | schedule_work(&vif_priv->beacon_work.work); | |
818 | } | |
da81dede JL |
819 | } |
820 | ||
22bedad3 JP |
821 | static u64 rtl8180_prepare_multicast(struct ieee80211_hw *dev, |
822 | struct netdev_hw_addr_list *mc_list) | |
3ac64bee | 823 | { |
22bedad3 | 824 | return netdev_hw_addr_list_count(mc_list); |
3ac64bee JB |
825 | } |
826 | ||
f6532111 MW |
827 | static void rtl8180_configure_filter(struct ieee80211_hw *dev, |
828 | unsigned int changed_flags, | |
829 | unsigned int *total_flags, | |
3ac64bee | 830 | u64 multicast) |
f6532111 MW |
831 | { |
832 | struct rtl8180_priv *priv = dev->priv; | |
833 | ||
834 | if (changed_flags & FIF_FCSFAIL) | |
835 | priv->rx_conf ^= RTL818X_RX_CONF_FCS; | |
836 | if (changed_flags & FIF_CONTROL) | |
837 | priv->rx_conf ^= RTL818X_RX_CONF_CTRL; | |
838 | if (changed_flags & FIF_OTHER_BSS) | |
839 | priv->rx_conf ^= RTL818X_RX_CONF_MONITOR; | |
3ac64bee | 840 | if (*total_flags & FIF_ALLMULTI || multicast > 0) |
f6532111 MW |
841 | priv->rx_conf |= RTL818X_RX_CONF_MULTICAST; |
842 | else | |
843 | priv->rx_conf &= ~RTL818X_RX_CONF_MULTICAST; | |
844 | ||
845 | *total_flags = 0; | |
846 | ||
847 | if (priv->rx_conf & RTL818X_RX_CONF_FCS) | |
848 | *total_flags |= FIF_FCSFAIL; | |
849 | if (priv->rx_conf & RTL818X_RX_CONF_CTRL) | |
850 | *total_flags |= FIF_CONTROL; | |
851 | if (priv->rx_conf & RTL818X_RX_CONF_MONITOR) | |
852 | *total_flags |= FIF_OTHER_BSS; | |
853 | if (priv->rx_conf & RTL818X_RX_CONF_MULTICAST) | |
854 | *total_flags |= FIF_ALLMULTI; | |
855 | ||
856 | rtl818x_iowrite32(priv, &priv->map->RX_CONF, priv->rx_conf); | |
857 | } | |
858 | ||
859 | static const struct ieee80211_ops rtl8180_ops = { | |
860 | .tx = rtl8180_tx, | |
861 | .start = rtl8180_start, | |
862 | .stop = rtl8180_stop, | |
863 | .add_interface = rtl8180_add_interface, | |
864 | .remove_interface = rtl8180_remove_interface, | |
865 | .config = rtl8180_config, | |
da81dede | 866 | .bss_info_changed = rtl8180_bss_info_changed, |
3ac64bee | 867 | .prepare_multicast = rtl8180_prepare_multicast, |
f6532111 | 868 | .configure_filter = rtl8180_configure_filter, |
d2bb8e02 | 869 | .get_tsf = rtl8180_get_tsf, |
f6532111 MW |
870 | }; |
871 | ||
872 | static void rtl8180_eeprom_register_read(struct eeprom_93cx6 *eeprom) | |
873 | { | |
874 | struct ieee80211_hw *dev = eeprom->data; | |
875 | struct rtl8180_priv *priv = dev->priv; | |
876 | u8 reg = rtl818x_ioread8(priv, &priv->map->EEPROM_CMD); | |
877 | ||
878 | eeprom->reg_data_in = reg & RTL818X_EEPROM_CMD_WRITE; | |
879 | eeprom->reg_data_out = reg & RTL818X_EEPROM_CMD_READ; | |
880 | eeprom->reg_data_clock = reg & RTL818X_EEPROM_CMD_CK; | |
881 | eeprom->reg_chip_select = reg & RTL818X_EEPROM_CMD_CS; | |
882 | } | |
883 | ||
884 | static void rtl8180_eeprom_register_write(struct eeprom_93cx6 *eeprom) | |
885 | { | |
886 | struct ieee80211_hw *dev = eeprom->data; | |
887 | struct rtl8180_priv *priv = dev->priv; | |
888 | u8 reg = 2 << 6; | |
889 | ||
890 | if (eeprom->reg_data_in) | |
891 | reg |= RTL818X_EEPROM_CMD_WRITE; | |
892 | if (eeprom->reg_data_out) | |
893 | reg |= RTL818X_EEPROM_CMD_READ; | |
894 | if (eeprom->reg_data_clock) | |
895 | reg |= RTL818X_EEPROM_CMD_CK; | |
896 | if (eeprom->reg_chip_select) | |
897 | reg |= RTL818X_EEPROM_CMD_CS; | |
898 | ||
899 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, reg); | |
900 | rtl818x_ioread8(priv, &priv->map->EEPROM_CMD); | |
901 | udelay(10); | |
902 | } | |
903 | ||
fb4e899d | 904 | static int rtl8180_probe(struct pci_dev *pdev, |
f6532111 MW |
905 | const struct pci_device_id *id) |
906 | { | |
907 | struct ieee80211_hw *dev; | |
908 | struct rtl8180_priv *priv; | |
909 | unsigned long mem_addr, mem_len; | |
910 | unsigned int io_addr, io_len; | |
911 | int err, i; | |
912 | struct eeprom_93cx6 eeprom; | |
913 | const char *chip_name, *rf_name = NULL; | |
914 | u32 reg; | |
915 | u16 eeprom_val; | |
c693bf90 | 916 | u8 mac_addr[ETH_ALEN]; |
f6532111 MW |
917 | |
918 | err = pci_enable_device(pdev); | |
919 | if (err) { | |
920 | printk(KERN_ERR "%s (rtl8180): Cannot enable new PCI device\n", | |
921 | pci_name(pdev)); | |
922 | return err; | |
923 | } | |
924 | ||
925 | err = pci_request_regions(pdev, KBUILD_MODNAME); | |
926 | if (err) { | |
927 | printk(KERN_ERR "%s (rtl8180): Cannot obtain PCI resources\n", | |
928 | pci_name(pdev)); | |
929 | return err; | |
930 | } | |
931 | ||
932 | io_addr = pci_resource_start(pdev, 0); | |
933 | io_len = pci_resource_len(pdev, 0); | |
934 | mem_addr = pci_resource_start(pdev, 1); | |
935 | mem_len = pci_resource_len(pdev, 1); | |
936 | ||
937 | if (mem_len < sizeof(struct rtl818x_csr) || | |
938 | io_len < sizeof(struct rtl818x_csr)) { | |
939 | printk(KERN_ERR "%s (rtl8180): Too short PCI resources\n", | |
940 | pci_name(pdev)); | |
941 | err = -ENOMEM; | |
942 | goto err_free_reg; | |
943 | } | |
944 | ||
9e385c56 JL |
945 | if ((err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) || |
946 | (err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))) { | |
f6532111 MW |
947 | printk(KERN_ERR "%s (rtl8180): No suitable DMA available\n", |
948 | pci_name(pdev)); | |
949 | goto err_free_reg; | |
950 | } | |
951 | ||
952 | pci_set_master(pdev); | |
953 | ||
954 | dev = ieee80211_alloc_hw(sizeof(*priv), &rtl8180_ops); | |
955 | if (!dev) { | |
956 | printk(KERN_ERR "%s (rtl8180): ieee80211 alloc failed\n", | |
957 | pci_name(pdev)); | |
958 | err = -ENOMEM; | |
959 | goto err_free_reg; | |
960 | } | |
961 | ||
962 | priv = dev->priv; | |
963 | priv->pdev = pdev; | |
964 | ||
e6a9854b | 965 | dev->max_rates = 2; |
f6532111 MW |
966 | SET_IEEE80211_DEV(dev, &pdev->dev); |
967 | pci_set_drvdata(pdev, dev); | |
968 | ||
969 | priv->map = pci_iomap(pdev, 1, mem_len); | |
970 | if (!priv->map) | |
971 | priv->map = pci_iomap(pdev, 0, io_len); | |
972 | ||
973 | if (!priv->map) { | |
974 | printk(KERN_ERR "%s (rtl8180): Cannot map device memory\n", | |
975 | pci_name(pdev)); | |
976 | goto err_free_dev; | |
977 | } | |
978 | ||
8318d78a JB |
979 | BUILD_BUG_ON(sizeof(priv->channels) != sizeof(rtl818x_channels)); |
980 | BUILD_BUG_ON(sizeof(priv->rates) != sizeof(rtl818x_rates)); | |
981 | ||
f6532111 MW |
982 | memcpy(priv->channels, rtl818x_channels, sizeof(rtl818x_channels)); |
983 | memcpy(priv->rates, rtl818x_rates, sizeof(rtl818x_rates)); | |
8318d78a JB |
984 | |
985 | priv->band.band = IEEE80211_BAND_2GHZ; | |
986 | priv->band.channels = priv->channels; | |
987 | priv->band.n_channels = ARRAY_SIZE(rtl818x_channels); | |
988 | priv->band.bitrates = priv->rates; | |
989 | priv->band.n_bitrates = 4; | |
990 | dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band; | |
991 | ||
f6532111 | 992 | dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | |
566bfe5a BR |
993 | IEEE80211_HW_RX_INCLUDES_FCS | |
994 | IEEE80211_HW_SIGNAL_UNSPEC; | |
c809e86c JL |
995 | dev->vif_data_size = sizeof(struct rtl8180_vif); |
996 | dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | | |
997 | BIT(NL80211_IFTYPE_ADHOC); | |
f6532111 | 998 | dev->queues = 1; |
566bfe5a | 999 | dev->max_signal = 65; |
f6532111 MW |
1000 | |
1001 | reg = rtl818x_ioread32(priv, &priv->map->TX_CONF); | |
1002 | reg &= RTL818X_TX_CONF_HWVER_MASK; | |
1003 | switch (reg) { | |
1004 | case RTL818X_TX_CONF_R8180_ABCD: | |
1005 | chip_name = "RTL8180"; | |
1006 | break; | |
1007 | case RTL818X_TX_CONF_R8180_F: | |
1008 | chip_name = "RTL8180vF"; | |
1009 | break; | |
1010 | case RTL818X_TX_CONF_R8185_ABC: | |
1011 | chip_name = "RTL8185"; | |
1012 | break; | |
1013 | case RTL818X_TX_CONF_R8185_D: | |
1014 | chip_name = "RTL8185vD"; | |
1015 | break; | |
1016 | default: | |
1017 | printk(KERN_ERR "%s (rtl8180): Unknown chip! (0x%x)\n", | |
1018 | pci_name(pdev), reg >> 25); | |
1019 | goto err_iounmap; | |
1020 | } | |
1021 | ||
1022 | priv->r8185 = reg & RTL818X_TX_CONF_R8185_ABC; | |
1023 | if (priv->r8185) { | |
8318d78a | 1024 | priv->band.n_bitrates = ARRAY_SIZE(rtl818x_rates); |
f6532111 MW |
1025 | pci_try_set_mwi(pdev); |
1026 | } | |
1027 | ||
f6532111 MW |
1028 | eeprom.data = dev; |
1029 | eeprom.register_read = rtl8180_eeprom_register_read; | |
1030 | eeprom.register_write = rtl8180_eeprom_register_write; | |
1031 | if (rtl818x_ioread32(priv, &priv->map->RX_CONF) & (1 << 6)) | |
1032 | eeprom.width = PCI_EEPROM_WIDTH_93C66; | |
1033 | else | |
1034 | eeprom.width = PCI_EEPROM_WIDTH_93C46; | |
1035 | ||
1036 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_PROGRAM); | |
1037 | rtl818x_ioread8(priv, &priv->map->EEPROM_CMD); | |
1038 | udelay(10); | |
1039 | ||
1040 | eeprom_93cx6_read(&eeprom, 0x06, &eeprom_val); | |
1041 | eeprom_val &= 0xFF; | |
1042 | switch (eeprom_val) { | |
1043 | case 1: rf_name = "Intersil"; | |
1044 | break; | |
1045 | case 2: rf_name = "RFMD"; | |
1046 | break; | |
1047 | case 3: priv->rf = &sa2400_rf_ops; | |
1048 | break; | |
1049 | case 4: priv->rf = &max2820_rf_ops; | |
1050 | break; | |
1051 | case 5: priv->rf = &grf5101_rf_ops; | |
1052 | break; | |
1053 | case 9: priv->rf = rtl8180_detect_rf(dev); | |
1054 | break; | |
1055 | case 10: | |
1056 | rf_name = "RTL8255"; | |
1057 | break; | |
1058 | default: | |
1059 | printk(KERN_ERR "%s (rtl8180): Unknown RF! (0x%x)\n", | |
1060 | pci_name(pdev), eeprom_val); | |
1061 | goto err_iounmap; | |
1062 | } | |
1063 | ||
1064 | if (!priv->rf) { | |
1065 | printk(KERN_ERR "%s (rtl8180): %s RF frontend not supported!\n", | |
1066 | pci_name(pdev), rf_name); | |
1067 | goto err_iounmap; | |
1068 | } | |
1069 | ||
1070 | eeprom_93cx6_read(&eeprom, 0x17, &eeprom_val); | |
1071 | priv->csthreshold = eeprom_val >> 8; | |
1072 | if (!priv->r8185) { | |
1073 | __le32 anaparam; | |
1074 | eeprom_93cx6_multiread(&eeprom, 0xD, (__le16 *)&anaparam, 2); | |
1075 | priv->anaparam = le32_to_cpu(anaparam); | |
1076 | eeprom_93cx6_read(&eeprom, 0x19, &priv->rfparam); | |
1077 | } | |
1078 | ||
c693bf90 JL |
1079 | eeprom_93cx6_multiread(&eeprom, 0x7, (__le16 *)mac_addr, 3); |
1080 | if (!is_valid_ether_addr(mac_addr)) { | |
f6532111 MW |
1081 | printk(KERN_WARNING "%s (rtl8180): Invalid hwaddr! Using" |
1082 | " randomly generated MAC addr\n", pci_name(pdev)); | |
f4f7f414 | 1083 | eth_random_addr(mac_addr); |
f6532111 | 1084 | } |
c693bf90 | 1085 | SET_IEEE80211_PERM_ADDR(dev, mac_addr); |
f6532111 MW |
1086 | |
1087 | /* CCK TX power */ | |
1088 | for (i = 0; i < 14; i += 2) { | |
1089 | u16 txpwr; | |
1090 | eeprom_93cx6_read(&eeprom, 0x10 + (i >> 1), &txpwr); | |
8318d78a JB |
1091 | priv->channels[i].hw_value = txpwr & 0xFF; |
1092 | priv->channels[i + 1].hw_value = txpwr >> 8; | |
f6532111 MW |
1093 | } |
1094 | ||
1095 | /* OFDM TX power */ | |
1096 | if (priv->r8185) { | |
1097 | for (i = 0; i < 14; i += 2) { | |
1098 | u16 txpwr; | |
1099 | eeprom_93cx6_read(&eeprom, 0x20 + (i >> 1), &txpwr); | |
8318d78a JB |
1100 | priv->channels[i].hw_value |= (txpwr & 0xFF) << 8; |
1101 | priv->channels[i + 1].hw_value |= txpwr & 0xFF00; | |
f6532111 MW |
1102 | } |
1103 | } | |
1104 | ||
1105 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL); | |
1106 | ||
1107 | spin_lock_init(&priv->lock); | |
1108 | ||
1109 | err = ieee80211_register_hw(dev); | |
1110 | if (err) { | |
1111 | printk(KERN_ERR "%s (rtl8180): Cannot register device\n", | |
1112 | pci_name(pdev)); | |
1113 | goto err_iounmap; | |
1114 | } | |
1115 | ||
c96c31e4 JP |
1116 | wiphy_info(dev->wiphy, "hwaddr %pm, %s + %s\n", |
1117 | mac_addr, chip_name, priv->rf->name); | |
f6532111 MW |
1118 | |
1119 | return 0; | |
1120 | ||
1121 | err_iounmap: | |
1122 | iounmap(priv->map); | |
1123 | ||
1124 | err_free_dev: | |
1125 | pci_set_drvdata(pdev, NULL); | |
1126 | ieee80211_free_hw(dev); | |
1127 | ||
1128 | err_free_reg: | |
1129 | pci_release_regions(pdev); | |
1130 | pci_disable_device(pdev); | |
1131 | return err; | |
1132 | } | |
1133 | ||
fb4e899d | 1134 | static void rtl8180_remove(struct pci_dev *pdev) |
f6532111 MW |
1135 | { |
1136 | struct ieee80211_hw *dev = pci_get_drvdata(pdev); | |
1137 | struct rtl8180_priv *priv; | |
1138 | ||
1139 | if (!dev) | |
1140 | return; | |
1141 | ||
1142 | ieee80211_unregister_hw(dev); | |
1143 | ||
1144 | priv = dev->priv; | |
1145 | ||
1146 | pci_iounmap(pdev, priv->map); | |
1147 | pci_release_regions(pdev); | |
1148 | pci_disable_device(pdev); | |
1149 | ieee80211_free_hw(dev); | |
1150 | } | |
1151 | ||
1152 | #ifdef CONFIG_PM | |
1153 | static int rtl8180_suspend(struct pci_dev *pdev, pm_message_t state) | |
1154 | { | |
1155 | pci_save_state(pdev); | |
1156 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | |
1157 | return 0; | |
1158 | } | |
1159 | ||
1160 | static int rtl8180_resume(struct pci_dev *pdev) | |
1161 | { | |
1162 | pci_set_power_state(pdev, PCI_D0); | |
1163 | pci_restore_state(pdev); | |
1164 | return 0; | |
1165 | } | |
1166 | ||
1167 | #endif /* CONFIG_PM */ | |
1168 | ||
1169 | static struct pci_driver rtl8180_driver = { | |
1170 | .name = KBUILD_MODNAME, | |
1171 | .id_table = rtl8180_table, | |
1172 | .probe = rtl8180_probe, | |
fb4e899d | 1173 | .remove = rtl8180_remove, |
f6532111 MW |
1174 | #ifdef CONFIG_PM |
1175 | .suspend = rtl8180_suspend, | |
1176 | .resume = rtl8180_resume, | |
1177 | #endif /* CONFIG_PM */ | |
1178 | }; | |
1179 | ||
5b0a3b7e | 1180 | module_pci_driver(rtl8180_driver); |