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rtl8180: config carbus register for rtl8187se
[deliverable/linux.git] / drivers / net / wireless / rtl818x / rtl8180 / dev.c
CommitLineData
f6532111
MW		 1
2/*
3 * Linux device driver for RTL8180 / RTL8185
4 *
5 * Copyright 2007 Michael Wu <flamingice@sourmilk.net>
93ba2a85 6 * Copyright 2007 Andrea Merello <andrea.merello@gmail.com>
f6532111
MW		 7 *
8 * Based on the r8180 driver, which is:
93ba2a85 9 * Copyright 2004-2005 Andrea Merello <andrea.merello@gmail.com>, et al.
f6532111
MW		 10 *
11 * Thanks to Realtek for their support!
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
a6b7a407 18#include <linux/interrupt.h>
f6532111 19#include <linux/pci.h>
5a0e3ad6 20#include <linux/slab.h>
f6532111
MW		 21#include <linux/delay.h>
22#include <linux/etherdevice.h>
23#include <linux/eeprom_93cx6.h>
9d9779e7 24#include <linux/module.h>
f6532111
MW		 25#include <net/mac80211.h>
26
27#include "rtl8180.h"
3cfeb0c3
JL		 28#include "rtl8225.h"
29#include "sa2400.h"
30#include "max2820.h"
31#include "grf5101.h"
f6532111
MW		 32
33MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
93ba2a85 34MODULE_AUTHOR("Andrea Merello <andrea.merello@gmail.com>");
f6532111
MW		 35MODULE_DESCRIPTION("RTL8180 / RTL8185 PCI wireless driver");
36MODULE_LICENSE("GPL");
37
a3aa1884 38static DEFINE_PCI_DEVICE_TABLE(rtl8180_table) = {
f6532111
MW		 39 /* rtl8185 */
40 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8185) },
4fcc5470 41 { PCI_DEVICE(PCI_VENDOR_ID_BELKIN, 0x700f) },
f6532111
MW		 42 { PCI_DEVICE(PCI_VENDOR_ID_BELKIN, 0x701f) },
43
44 /* rtl8180 */
45 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8180) },
46 { PCI_DEVICE(0x1799, 0x6001) },
47 { PCI_DEVICE(0x1799, 0x6020) },
48 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x3300) },
29a6b508
XVP		 49 { PCI_DEVICE(0x1186, 0x3301) },
50 { PCI_DEVICE(0x1432, 0x7106) },
f6532111
MW		 51 { }
52};
53
54MODULE_DEVICE_TABLE(pci, rtl8180_table);
55
8318d78a
JB		 56static const struct ieee80211_rate rtl818x_rates[] = {
57 { .bitrate = 10, .hw_value = 0, },
58 { .bitrate = 20, .hw_value = 1, },
59 { .bitrate = 55, .hw_value = 2, },
60 { .bitrate = 110, .hw_value = 3, },
61 { .bitrate = 60, .hw_value = 4, },
62 { .bitrate = 90, .hw_value = 5, },
63 { .bitrate = 120, .hw_value = 6, },
64 { .bitrate = 180, .hw_value = 7, },
65 { .bitrate = 240, .hw_value = 8, },
66 { .bitrate = 360, .hw_value = 9, },
67 { .bitrate = 480, .hw_value = 10, },
68 { .bitrate = 540, .hw_value = 11, },
69};
70
71static const struct ieee80211_channel rtl818x_channels[] = {
72 { .center_freq = 2412 },
73 { .center_freq = 2417 },
74 { .center_freq = 2422 },
75 { .center_freq = 2427 },
76 { .center_freq = 2432 },
77 { .center_freq = 2437 },
78 { .center_freq = 2442 },
79 { .center_freq = 2447 },
80 { .center_freq = 2452 },
81 { .center_freq = 2457 },
82 { .center_freq = 2462 },
83 { .center_freq = 2467 },
84 { .center_freq = 2472 },
85 { .center_freq = 2484 },
86};
87
3ee44d60
AM		 88/* Queues for rtl8187se card
89 *
90 * name | reg | queue
91 * BC | 7 | 6
92 * MG | 1 | 0
93 * HI | 6 | 1
94 * VO | 5 | 2
95 * VI | 4 | 3
96 * BE | 3 | 4
97 * BK | 2 | 5
98 *
99 * The complete map for DMA kick reg using use all queue is:
100 * static const int rtl8187se_queues_map[RTL8187SE_NR_TX_QUEUES] =
101 * {1, 6, 5, 4, 3, 2, 7};
102 *
103 * .. but.. Because for mac80211 4 queues are enough for QoS we use this
104 *
105 * name | reg | queue
106 * BC | 7 | 4 <- currently not used yet
107 * MG | 1 | x <- Not used
108 * HI | 6 | x <- Not used
109 * VO | 5 | 0 <- used
110 * VI | 4 | 1 <- used
111 * BE | 3 | 2 <- used
112 * BK | 2 | 3 <- used
113 *
114 * Beacon queue could be used, but this is not finished yet.
115 *
116 * I thougth about using the other two queues but I decided not to do this:
117 *
118 * - I'm unsure whether the mac80211 will ever try to use more than 4 queues
119 * by itself.
120 *
121 * - I could route MGMT frames (currently sent over VO queue) to the MGMT
122 * queue but since mac80211 will do not know about it, I will probably gain
123 * some HW priority whenever the VO queue is not empty, but this gain is
124 * limited by the fact that I had to stop the mac80211 queue whenever one of
125 * the VO or MGMT queues is full, stopping also submitting of MGMT frame
126 * to the driver.
127 *
128 * - I don't know how to set in the HW the contention window params for MGMT
129 * and HI-prio queues.
130 */
131
132static const int rtl8187se_queues_map[RTL8187SE_NR_TX_QUEUES] = {5, 4, 3, 2, 7};
133
fd6564fc
AM		 134/* Queues for rtl8180/rtl8185 cards
135 *
136 * name | reg | prio
137 * BC | 7 | 3
138 * HI | 6 | 0
139 * NO | 5 | 1
140 * LO | 4 | 2
141 *
142 * The complete map for DMA kick reg using all queue is:
143 * static const int rtl8180_queues_map[RTL8180_NR_TX_QUEUES] = {6, 5, 4, 7};
144 *
145 * .. but .. Because the mac80211 needs at least 4 queues for QoS or
146 * otherwise QoS can't be done, we use just one.
147 * Beacon queue could be used, but this is not finished yet.
148 * Actual map is:
149 *
150 * name | reg | prio
151 * BC | 7 | 1 <- currently not used yet.
152 * HI | 6 | x <- not used
153 * NO | 5 | x <- not used
154 * LO | 4 | 0 <- used
155 */
156
157static const int rtl8180_queues_map[RTL8180_NR_TX_QUEUES] = {4, 7};
8318d78a 158
f6532111
MW		 159void rtl8180_write_phy(struct ieee80211_hw *dev, u8 addr, u32 data)
160{
161 struct rtl8180_priv *priv = dev->priv;
162 int i = 10;
163 u32 buf;
164
165 buf = (data << 8) | addr;
166
167 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->PHY[0], buf | 0x80);
168 while (i--) {
169 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->PHY[0], buf);
170 if (rtl818x_ioread8(priv, &priv->map->PHY[2]) == (data & 0xFF))
171 return;
172 }
173}
174
a6d27d2a 175static void rtl8180_handle_rx(struct ieee80211_hw *dev)
f6532111
MW		 176{
177 struct rtl8180_priv *priv = dev->priv;
21025920 178 struct rtl818x_rx_cmd_desc *cmd_desc;
a6d27d2a 179 unsigned int count = 32;
8b73fb8e 180 u8 signal, agc, sq;
2b4db05e 181 dma_addr_t mapping;
f6532111 182
a6d27d2a 183 while (count--) {
21025920 184 void *entry = priv->rx_ring + priv->rx_idx * priv->rx_ring_sz;
f6532111 185 struct sk_buff *skb = priv->rx_buf[priv->rx_idx];
21025920
AM		 186 u32 flags, flags2;
187 u64 tsft;
188
189 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
190 struct rtl8187se_rx_desc *desc = entry;
191
192 flags = le32_to_cpu(desc->flags);
193 flags2 = le32_to_cpu(desc->flags2);
194 tsft = le64_to_cpu(desc->tsft);
195 } else {
196 struct rtl8180_rx_desc *desc = entry;
197
198 flags = le32_to_cpu(desc->flags);
199 flags2 = le32_to_cpu(desc->flags2);
200 tsft = le64_to_cpu(desc->tsft);
201 }
f6532111 202
38e3b0d8 203 if (flags & RTL818X_RX_DESC_FLAG_OWN)
a6d27d2a 204 return;
f6532111 205
38e3b0d8
HRK		 206 if (unlikely(flags & (RTL818X_RX_DESC_FLAG_DMA_FAIL |
207 RTL818X_RX_DESC_FLAG_FOF |
208 RTL818X_RX_DESC_FLAG_RX_ERR)))
f6532111
MW		 209 goto done;
210 else {
f6532111
MW		 211 struct ieee80211_rx_status rx_status = {0};
212 struct sk_buff *new_skb = dev_alloc_skb(MAX_RX_SIZE);
213
214 if (unlikely(!new_skb))
215 goto done;
216
2b4db05e 217 mapping = pci_map_single(priv->pdev,
218 skb_tail_pointer(new_skb),
219 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
220
221 if (pci_dma_mapping_error(priv->pdev, mapping)) {
222 kfree_skb(new_skb);
223 dev_err(&priv->pdev->dev, "RX DMA map error\n");
224
225 goto done;
226 }
227
f6532111
MW		 228 pci_unmap_single(priv->pdev,
229 *((dma_addr_t *)skb->cb),
230 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
231 skb_put(skb, flags & 0xFFF);
232
233 rx_status.antenna = (flags2 >> 15) & 1;
8318d78a 234 rx_status.rate_idx = (flags >> 20) & 0xF;
8b73fb8e 235 agc = (flags2 >> 17) & 0x7F;
6caefd12
AM		 236
237 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8185) {
8b73fb8e
JL		 238 if (rx_status.rate_idx > 3)
239 signal = 90 - clamp_t(u8, agc, 25, 90);
240 else
241 signal = 95 - clamp_t(u8, agc, 30, 95);
21025920
AM		 242 } else if (priv->chip_family ==
243 RTL818X_CHIP_FAMILY_RTL8180) {
8b73fb8e
JL		 244 sq = flags2 & 0xff;
245 signal = priv->rf->calc_rssi(agc, sq);
21025920
AM		 246 } else {
247 /* TODO: rtl8187se rssi */
248 signal = 10;
8b73fb8e 249 }
8b74964c 250 rx_status.signal = signal;
675a0b04
KB		 251 rx_status.freq = dev->conf.chandef.chan->center_freq;
252 rx_status.band = dev->conf.chandef.chan->band;
21025920 253 rx_status.mactime = tsft;
f4bda337 254 rx_status.flag |= RX_FLAG_MACTIME_START;
38e3b0d8 255 if (flags & RTL818X_RX_DESC_FLAG_CRC32_ERR)
f6532111
MW		 256 rx_status.flag |= RX_FLAG_FAILED_FCS_CRC;
257
f1d58c25 258 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
a6d27d2a 259 ieee80211_rx_irqsafe(dev, skb);
f6532111
MW		 260
261 skb = new_skb;
262 priv->rx_buf[priv->rx_idx] = skb;
2b4db05e 263 *((dma_addr_t *) skb->cb) = mapping;
f6532111
MW		 264 }
265
266 done:
21025920
AM		 267 cmd_desc = entry;
268 cmd_desc->rx_buf = cpu_to_le32(*((dma_addr_t *)skb->cb));
269 cmd_desc->flags = cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN |
f6532111
MW		 270 MAX_RX_SIZE);
271 if (priv->rx_idx == 31)
21025920
AM		 272 cmd_desc->flags |=
273 cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR);
f6532111
MW		 274 priv->rx_idx = (priv->rx_idx + 1) % 32;
275 }
a6d27d2a
JL		 276}
277
278static void rtl8180_handle_tx(struct ieee80211_hw *dev, unsigned int prio)
279{
280 struct rtl8180_priv *priv = dev->priv;
281 struct rtl8180_tx_ring *ring = &priv->tx_ring[prio];
e6a9854b 282
a6d27d2a
JL		 283 while (skb_queue_len(&ring->queue)) {
284 struct rtl8180_tx_desc *entry = &ring->desc[ring->idx];
285 struct sk_buff *skb;
286 struct ieee80211_tx_info *info;
287 u32 flags = le32_to_cpu(entry->flags);
f6532111 288
a6d27d2a
JL		 289 if (flags & RTL818X_TX_DESC_FLAG_OWN)
290 return;
291
292 ring->idx = (ring->idx + 1) % ring->entries;
293 skb = __skb_dequeue(&ring->queue);
294 pci_unmap_single(priv->pdev, le32_to_cpu(entry->tx_buf),
295 skb->len, PCI_DMA_TODEVICE);
296
297 info = IEEE80211_SKB_CB(skb);
298 ieee80211_tx_info_clear_status(info);
299
300 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK) &&
301 (flags & RTL818X_TX_DESC_FLAG_TX_OK))
302 info->flags |= IEEE80211_TX_STAT_ACK;
303
304 info->status.rates[0].count = (flags & 0xFF) + 1;
305 info->status.rates[1].idx = -1;
030725d2 306
a6d27d2a
JL		 307 ieee80211_tx_status_irqsafe(dev, skb);
308 if (ring->entries - skb_queue_len(&ring->queue) == 2)
309 ieee80211_wake_queue(dev, prio);
310 }
f6532111
MW		 311}
312
a373ebcb
AM		 313static irqreturn_t rtl8187se_interrupt(int irq, void *dev_id)
314{
315 struct ieee80211_hw *dev = dev_id;
316 struct rtl8180_priv *priv = dev->priv;
317 u32 reg;
318 unsigned long flags;
319 static int desc_err;
320
321 spin_lock_irqsave(&priv->lock, flags);
322 /* Note: 32-bit interrupt status */
323 reg = rtl818x_ioread32(priv, &priv->map->INT_STATUS_SE);
324 if (unlikely(reg == 0xFFFFFFFF)) {
325 spin_unlock_irqrestore(&priv->lock, flags);
326 return IRQ_HANDLED;
327 }
328
329 rtl818x_iowrite32(priv, &priv->map->INT_STATUS_SE, reg);
330
331 if (reg & IMR_TIMEOUT1)
332 rtl818x_iowrite32(priv, &priv->map->INT_TIMEOUT, 0);
333
334 if (reg & (IMR_TBDOK | IMR_TBDER))
335 rtl8180_handle_tx(dev, 4);
336
337 if (reg & (IMR_TVODOK | IMR_TVODER))
338 rtl8180_handle_tx(dev, 0);
339
340 if (reg & (IMR_TVIDOK | IMR_TVIDER))
341 rtl8180_handle_tx(dev, 1);
342
343 if (reg & (IMR_TBEDOK | IMR_TBEDER))
344 rtl8180_handle_tx(dev, 2);
345
346 if (reg & (IMR_TBKDOK | IMR_TBKDER))
347 rtl8180_handle_tx(dev, 3);
348
349 if (reg & (IMR_ROK | IMR_RER | RTL818X_INT_SE_RX_DU | IMR_RQOSOK))
350 rtl8180_handle_rx(dev);
351 /* The interface sometimes generates several RX DMA descriptor errors
352 * at startup. Do not report these.
353 */
354 if ((reg & RTL818X_INT_SE_RX_DU) && desc_err++ > 2)
355 if (net_ratelimit())
356 wiphy_err(dev->wiphy, "No RX DMA Descriptor avail\n");
357
358 spin_unlock_irqrestore(&priv->lock, flags);
359 return IRQ_HANDLED;
360}
361
f6532111
MW		 362static irqreturn_t rtl8180_interrupt(int irq, void *dev_id)
363{
364 struct ieee80211_hw *dev = dev_id;
365 struct rtl8180_priv *priv = dev->priv;
366 u16 reg;
367
a6d27d2a 368 spin_lock(&priv->lock);
f6532111 369 reg = rtl818x_ioread16(priv, &priv->map->INT_STATUS);
a6d27d2a
JL		 370 if (unlikely(reg == 0xFFFF)) {
371 spin_unlock(&priv->lock);
f6532111 372 return IRQ_HANDLED;
a6d27d2a 373 }
f6532111
MW		 374
375 rtl818x_iowrite16(priv, &priv->map->INT_STATUS, reg);
376
a6d27d2a 377 if (reg & (RTL818X_INT_TXB_OK | RTL818X_INT_TXB_ERR))
a6d27d2a 378 rtl8180_handle_tx(dev, 1);
f6532111 379
a6d27d2a
JL		 380 if (reg & (RTL818X_INT_TXL_OK | RTL818X_INT_TXL_ERR))
381 rtl8180_handle_tx(dev, 0);
382
383 if (reg & (RTL818X_INT_RX_OK | RTL818X_INT_RX_ERR))
384 rtl8180_handle_rx(dev);
385
386 spin_unlock(&priv->lock);
f6532111
MW		 387
388 return IRQ_HANDLED;
389}
390
36323f81
TH		 391static void rtl8180_tx(struct ieee80211_hw *dev,
392 struct ieee80211_tx_control *control,
393 struct sk_buff *skb)
f6532111 394{
e039fa4a 395 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
51e080de 396 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
f6532111
MW		 397 struct rtl8180_priv *priv = dev->priv;
398 struct rtl8180_tx_ring *ring;
399 struct rtl8180_tx_desc *entry;
a6d27d2a 400 unsigned long flags;
fd6564fc 401 unsigned int idx, prio, hw_prio;
f6532111
MW		 402 dma_addr_t mapping;
403 u32 tx_flags;
e6a9854b 404 u8 rc_flags;
f6532111
MW		 405 u16 plcp_len = 0;
406 __le16 rts_duration = 0;
3ee44d60
AM		 407 /* do arithmetic and then convert to le16 */
408 u16 frame_duration = 0;
f6532111 409
e2530083 410 prio = skb_get_queue_mapping(skb);
f6532111
MW		 411 ring = &priv->tx_ring[prio];
412
413 mapping = pci_map_single(priv->pdev, skb->data,
414 skb->len, PCI_DMA_TODEVICE);
415
348f7d4a 416 if (pci_dma_mapping_error(priv->pdev, mapping)) {
417 kfree_skb(skb);
418 dev_err(&priv->pdev->dev, "TX DMA mapping error\n");
419 return;
348f7d4a 420 }
421
38e3b0d8
HRK		 422 tx_flags = RTL818X_TX_DESC_FLAG_OWN | RTL818X_TX_DESC_FLAG_FS |
423 RTL818X_TX_DESC_FLAG_LS |
e039fa4a 424 (ieee80211_get_tx_rate(dev, info)->hw_value << 24) |
2e92e6f2 425 skb->len;
f6532111 426
6caefd12 427 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180)
38e3b0d8
HRK		 428 tx_flags |= RTL818X_TX_DESC_FLAG_DMA |
429 RTL818X_TX_DESC_FLAG_NO_ENC;
f6532111 430
e6a9854b
JB		 431 rc_flags = info->control.rates[0].flags;
432 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
38e3b0d8 433 tx_flags |= RTL818X_TX_DESC_FLAG_RTS;
e039fa4a 434 tx_flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
e6a9854b 435 } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
38e3b0d8 436 tx_flags |= RTL818X_TX_DESC_FLAG_CTS;
e039fa4a 437 tx_flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
aa68cbfb 438 }
f6532111 439
e6a9854b 440 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS)
32bfd35d 441 rts_duration = ieee80211_rts_duration(dev, priv->vif, skb->len,
e039fa4a 442 info);
f6532111 443
6caefd12 444 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180) {
f6532111
MW		 445 unsigned int remainder;
446
447 plcp_len = DIV_ROUND_UP(16 * (skb->len + 4),
e039fa4a 448 (ieee80211_get_tx_rate(dev, info)->bitrate * 2) / 10);
f6532111 449 remainder = (16 * (skb->len + 4)) %
e039fa4a 450 ((ieee80211_get_tx_rate(dev, info)->bitrate * 2) / 10);
35a0ace7 451 if (remainder <= 6)
f6532111
MW		 452 plcp_len |= 1 << 15;
453 }
454
3ee44d60
AM		 455 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
456 __le16 duration;
457 /* SIFS time (required by HW) is already included by
458 * ieee80211_generic_frame_duration
459 */
460 duration = ieee80211_generic_frame_duration(dev, priv->vif,
461 IEEE80211_BAND_2GHZ, skb->len,
462 ieee80211_get_tx_rate(dev, info));
463
464 frame_duration = priv->ack_time + le16_to_cpu(duration);
465 }
466
a6d27d2a 467 spin_lock_irqsave(&priv->lock, flags);
51e080de
JL		 468
469 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
470 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
471 priv->seqno += 0x10;
472 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
473 hdr->seq_ctrl |= cpu_to_le16(priv->seqno);
474 }
475
f6532111
MW		 476 idx = (ring->idx + skb_queue_len(&ring->queue)) % ring->entries;
477 entry = &ring->desc[idx];
478
3ee44d60
AM		 479 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
480 entry->frame_duration = cpu_to_le16(frame_duration);
481 entry->frame_len_se = cpu_to_le16(skb->len);
482
483 /* tpc polarity */
484 entry->flags3 = cpu_to_le16(1<<4);
485 } else
486 entry->frame_len = cpu_to_le32(skb->len);
487
f6532111
MW		 488 entry->rts_duration = rts_duration;
489 entry->plcp_len = cpu_to_le16(plcp_len);
490 entry->tx_buf = cpu_to_le32(mapping);
3ee44d60 491
e6a9854b 492 entry->flags2 = info->control.rates[1].idx >= 0 ?
870abdf6 493 ieee80211_get_alt_retry_rate(dev, info, 0)->bitrate << 4 : 0;
e6a9854b 494 entry->retry_limit = info->control.rates[0].count;
4c552a5b 495
496 /* We must be sure that tx_flags is written last because the HW
497 * looks at it to check if the rest of data is valid or not
498 */
499 wmb();
f6532111 500 entry->flags = cpu_to_le32(tx_flags);
c24782e6 501 /* We must be sure this has been written before followings HW
502 * register write, because this write will made the HW attempts
503 * to DMA the just-written data
504 */
505 wmb();
506
f6532111
MW		 507 __skb_queue_tail(&ring->queue, skb);
508 if (ring->entries - skb_queue_len(&ring->queue) < 2)
d10e2e02 509 ieee80211_stop_queue(dev, prio);
51e080de 510
a6d27d2a 511 spin_unlock_irqrestore(&priv->lock, flags);
f6532111 512
3ee44d60
AM		 513 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
514 /* just poll: rings are stopped with TPPollStop reg */
515 hw_prio = rtl8187se_queues_map[prio];
516 rtl818x_iowrite8(priv, &priv->map->TX_DMA_POLLING,
517 (1 << hw_prio));
518 } else {
519 hw_prio = rtl8180_queues_map[prio];
520 rtl818x_iowrite8(priv, &priv->map->TX_DMA_POLLING,
fd6564fc
AM		 521 (1 << hw_prio) | /* ring to poll */
522 (1<<1) | (1<<2));/* stopped rings */
3ee44d60 523 }
f6532111
MW		 524}
525
526void rtl8180_set_anaparam(struct rtl8180_priv *priv, u32 anaparam)
527{
528 u8 reg;
529
530 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
531 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
532 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
533 reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
534 rtl818x_iowrite32(priv, &priv->map->ANAPARAM, anaparam);
535 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
536 reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
537 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
538}
539
732c8932
AM		 540static void rtl8180_int_enable(struct ieee80211_hw *dev)
541{
542 struct rtl8180_priv *priv = dev->priv;
543
544 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
545 rtl818x_iowrite32(priv, &priv->map->IMR, IMR_TMGDOK |
546 IMR_TBDER | IMR_THPDER |
547 IMR_THPDER | IMR_THPDOK |
548 IMR_TVODER | IMR_TVODOK |
549 IMR_TVIDER | IMR_TVIDOK |
550 IMR_TBEDER | IMR_TBEDOK |
551 IMR_TBKDER | IMR_TBKDOK |
552 IMR_RDU | IMR_RER |
553 IMR_ROK | IMR_RQOSOK);
554 } else {
555 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
556 }
557}
558
559static void rtl8180_int_disable(struct ieee80211_hw *dev)
560{
561 struct rtl8180_priv *priv = dev->priv;
562
563 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
564 rtl818x_iowrite32(priv, &priv->map->IMR, 0);
565 } else {
566 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
567 }
568}
569
516a0930
AM		 570static void rtl8180_conf_basic_rates(struct ieee80211_hw *dev,
571 u32 rates_mask)
572{
573 struct rtl8180_priv *priv = dev->priv;
574
575 u8 max, min;
576 u16 reg;
577
578 max = fls(rates_mask) - 1;
579 min = ffs(rates_mask) - 1;
580
581 switch (priv->chip_family) {
582
583 case RTL818X_CHIP_FAMILY_RTL8180:
584 /* in 8180 this is NOT a BITMAP */
585 reg = rtl818x_ioread16(priv, &priv->map->BRSR);
586 reg &= ~3;
587 reg |= max;
588 rtl818x_iowrite16(priv, &priv->map->BRSR, reg);
516a0930
AM		 589 break;
590
591 case RTL818X_CHIP_FAMILY_RTL8185:
592 /* in 8185 this is a BITMAP */
593 rtl818x_iowrite16(priv, &priv->map->BRSR, rates_mask);
594 rtl818x_iowrite8(priv, &priv->map->RESP_RATE, (max << 4) | min);
595 break;
d209f3b4
AM		 596
597 case RTL818X_CHIP_FAMILY_RTL8187SE:
598 /* in 8187se this is a BITMAP */
599 rtl818x_iowrite16(priv, &priv->map->BRSR_8187SE, rates_mask);
600 break;
516a0930
AM		 601 }
602}
603
f1026df8
AM		 604static void rtl8180_config_cardbus(struct ieee80211_hw *dev)
605{
606 struct rtl8180_priv *priv = dev->priv;
607 u16 reg16;
608 u8 reg8;
609
610 reg8 = rtl818x_ioread8(priv, &priv->map->CONFIG3);
611 reg8 |= 1 << 1;
612 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg8);
613
614 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
615 rtl818x_iowrite16(priv, FEMR_SE, 0xffff);
616 } else {
617 reg16 = rtl818x_ioread16(priv, &priv->map->FEMR);
618 reg16 |= (1 << 15) | (1 << 14) | (1 << 4);
619 rtl818x_iowrite16(priv, &priv->map->FEMR, reg16);
620 }
621
622}
623
f6532111
MW		 624static int rtl8180_init_hw(struct ieee80211_hw *dev)
625{
626 struct rtl8180_priv *priv = dev->priv;
627 u16 reg;
628
629 rtl818x_iowrite8(priv, &priv->map->CMD, 0);
630 rtl818x_ioread8(priv, &priv->map->CMD);
631 msleep(10);
632
633 /* reset */
732c8932 634 rtl8180_int_disable(dev);
f6532111
MW		 635 rtl818x_ioread8(priv, &priv->map->CMD);
636
637 reg = rtl818x_ioread8(priv, &priv->map->CMD);
638 reg &= (1 << 1);
639 reg |= RTL818X_CMD_RESET;
640 rtl818x_iowrite8(priv, &priv->map->CMD, RTL818X_CMD_RESET);
641 rtl818x_ioread8(priv, &priv->map->CMD);
642 msleep(200);
643
644 /* check success of reset */
645 if (rtl818x_ioread8(priv, &priv->map->CMD) & RTL818X_CMD_RESET) {
c96c31e4 646 wiphy_err(dev->wiphy, "reset timeout!\n");
f6532111
MW		 647 return -ETIMEDOUT;
648 }
649
650 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_LOAD);
651 rtl818x_ioread8(priv, &priv->map->CMD);
652 msleep(200);
653
654 if (rtl818x_ioread8(priv, &priv->map->CONFIG3) & (1 << 3)) {
f1026df8 655 rtl8180_config_cardbus(dev);
f6532111
MW		 656 }
657
658 rtl818x_iowrite8(priv, &priv->map->MSR, 0);
659
6caefd12 660 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180)
f6532111
MW		 661 rtl8180_set_anaparam(priv, priv->anaparam);
662
663 rtl818x_iowrite32(priv, &priv->map->RDSAR, priv->rx_ring_dma);
fd6564fc 664 rtl818x_iowrite32(priv, &priv->map->TBDA, priv->tx_ring[1].dma);
f6532111
MW		 665 rtl818x_iowrite32(priv, &priv->map->TLPDA, priv->tx_ring[0].dma);
666
667 /* TODO: necessary? specs indicate not */
668 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
669 reg = rtl818x_ioread8(priv, &priv->map->CONFIG2);
670 rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg & ~(1 << 3));
6caefd12 671 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8185) {
f6532111
MW		 672 reg = rtl818x_ioread8(priv, &priv->map->CONFIG2);
673 rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg | (1 << 4));
674 }
675 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
676
677 /* TODO: set CONFIG5 for calibrating AGC on rtl8180 + philips radio? */
678
679 /* TODO: turn off hw wep on rtl8180 */
680
681 rtl818x_iowrite32(priv, &priv->map->INT_TIMEOUT, 0);
682
6caefd12 683 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180) {
f6532111
MW		 684 rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0);
685 rtl818x_iowrite8(priv, &priv->map->RATE_FALLBACK, 0x81);
f6532111
MW		 686
687 /* TODO: set ClkRun enable? necessary? */
688 reg = rtl818x_ioread8(priv, &priv->map->GP_ENABLE);
689 rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, reg & ~(1 << 6));
690 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
691 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
692 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg | (1 << 2));
693 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
694 } else {
f6532111
MW		 695 rtl818x_iowrite8(priv, &priv->map->SECURITY, 0);
696
697 rtl818x_iowrite8(priv, &priv->map->PHY_DELAY, 0x6);
698 rtl818x_iowrite8(priv, &priv->map->CARRIER_SENSE_COUNTER, 0x4C);
699 }
700
701 priv->rf->init(dev);
516a0930
AM		 702
703 /* default basic rates are 1,2 Mbps for rtl8180. 1,2,6,9,12,18,24 Mbps
704 * otherwise. bitmask 0x3 and 0x01f3 respectively.
705 * NOTE: currenty rtl8225 RF code changes basic rates, so we need to do
706 * this after rf init.
707 * TODO: try to find out whether RF code really needs to do this..
708 */
709 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180)
710 rtl8180_conf_basic_rates(dev, 0x3);
711 else
712 rtl8180_conf_basic_rates(dev, 0x1f3);
713
f6532111
MW		 714 return 0;
715}
716
717static int rtl8180_init_rx_ring(struct ieee80211_hw *dev)
718{
719 struct rtl8180_priv *priv = dev->priv;
21025920 720 struct rtl818x_rx_cmd_desc *entry;
f6532111
MW		 721 int i;
722
21025920
AM		 723 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE)
724 priv->rx_ring_sz = sizeof(struct rtl8187se_rx_desc);
725 else
726 priv->rx_ring_sz = sizeof(struct rtl8180_rx_desc);
727
f6532111 728 priv->rx_ring = pci_alloc_consistent(priv->pdev,
21025920 729 priv->rx_ring_sz * 32,
f6532111
MW		 730 &priv->rx_ring_dma);
731
732 if (!priv->rx_ring || (unsigned long)priv->rx_ring & 0xFF) {
5db55844 733 wiphy_err(dev->wiphy, "Cannot allocate RX ring\n");
f6532111
MW		 734 return -ENOMEM;
735 }
736
21025920 737 memset(priv->rx_ring, 0, priv->rx_ring_sz * 32);
f6532111
MW		 738 priv->rx_idx = 0;
739
740 for (i = 0; i < 32; i++) {
741 struct sk_buff *skb = dev_alloc_skb(MAX_RX_SIZE);
742 dma_addr_t *mapping;
21025920 743 entry = priv->rx_ring + priv->rx_ring_sz*i;
4da18bb4 744 if (!skb) {
745 wiphy_err(dev->wiphy, "Cannot allocate RX skb\n");
746 return -ENOMEM;
747 }
f6532111
MW		 748 priv->rx_buf[i] = skb;
749 mapping = (dma_addr_t *)skb->cb;
750 *mapping = pci_map_single(priv->pdev, skb_tail_pointer(skb),
751 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
ec1da08d 752
753 if (pci_dma_mapping_error(priv->pdev, *mapping)) {
754 kfree_skb(skb);
755 wiphy_err(dev->wiphy, "Cannot map DMA for RX skb\n");
756 return -ENOMEM;
757 }
758
f6532111 759 entry->rx_buf = cpu_to_le32(*mapping);
38e3b0d8 760 entry->flags = cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN |
f6532111
MW		 761 MAX_RX_SIZE);
762 }
38e3b0d8 763 entry->flags |= cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR);
f6532111
MW		 764 return 0;
765}
766
767static void rtl8180_free_rx_ring(struct ieee80211_hw *dev)
768{
769 struct rtl8180_priv *priv = dev->priv;
770 int i;
771
772 for (i = 0; i < 32; i++) {
773 struct sk_buff *skb = priv->rx_buf[i];
774 if (!skb)
775 continue;
776
777 pci_unmap_single(priv->pdev,
778 *((dma_addr_t *)skb->cb),
779 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
780 kfree_skb(skb);
781 }
782
21025920 783 pci_free_consistent(priv->pdev, priv->rx_ring_sz * 32,
f6532111
MW		 784 priv->rx_ring, priv->rx_ring_dma);
785 priv->rx_ring = NULL;
786}
787
788static int rtl8180_init_tx_ring(struct ieee80211_hw *dev,
789 unsigned int prio, unsigned int entries)
790{
791 struct rtl8180_priv *priv = dev->priv;
792 struct rtl8180_tx_desc *ring;
793 dma_addr_t dma;
794 int i;
795
796 ring = pci_alloc_consistent(priv->pdev, sizeof(*ring) * entries, &dma);
797 if (!ring || (unsigned long)ring & 0xFF) {
5db55844 798 wiphy_err(dev->wiphy, "Cannot allocate TX ring (prio = %d)\n",
c96c31e4 799 prio);
f6532111
MW		 800 return -ENOMEM;
801 }
802
803 memset(ring, 0, sizeof(*ring)*entries);
804 priv->tx_ring[prio].desc = ring;
805 priv->tx_ring[prio].dma = dma;
806 priv->tx_ring[prio].idx = 0;
807 priv->tx_ring[prio].entries = entries;
808 skb_queue_head_init(&priv->tx_ring[prio].queue);
809
810 for (i = 0; i < entries; i++)
811 ring[i].next_tx_desc =
812 cpu_to_le32((u32)dma + ((i + 1) % entries) * sizeof(*ring));
813
814 return 0;
815}
816
817static void rtl8180_free_tx_ring(struct ieee80211_hw *dev, unsigned int prio)
818{
819 struct rtl8180_priv *priv = dev->priv;
820 struct rtl8180_tx_ring *ring = &priv->tx_ring[prio];
821
822 while (skb_queue_len(&ring->queue)) {
823 struct rtl8180_tx_desc *entry = &ring->desc[ring->idx];
824 struct sk_buff *skb = __skb_dequeue(&ring->queue);
825
826 pci_unmap_single(priv->pdev, le32_to_cpu(entry->tx_buf),
827 skb->len, PCI_DMA_TODEVICE);
f6532111
MW		 828 kfree_skb(skb);
829 ring->idx = (ring->idx + 1) % ring->entries;
830 }
831
832 pci_free_consistent(priv->pdev, sizeof(*ring->desc)*ring->entries,
833 ring->desc, ring->dma);
834 ring->desc = NULL;
835}
836
837static int rtl8180_start(struct ieee80211_hw *dev)
838{
839 struct rtl8180_priv *priv = dev->priv;
840 int ret, i;
841 u32 reg;
842
843 ret = rtl8180_init_rx_ring(dev);
844 if (ret)
845 return ret;
846
fd6564fc 847 for (i = 0; i < (dev->queues + 1); i++)
f6532111
MW		 848 if ((ret = rtl8180_init_tx_ring(dev, i, 16)))
849 goto err_free_rings;
850
851 ret = rtl8180_init_hw(dev);
852 if (ret)
853 goto err_free_rings;
854
a373ebcb
AM		 855 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
856 ret = request_irq(priv->pdev->irq, rtl8187se_interrupt,
f6532111 857 IRQF_SHARED, KBUILD_MODNAME, dev);
a373ebcb
AM		 858 } else {
859 ret = request_irq(priv->pdev->irq, rtl8180_interrupt,
860 IRQF_SHARED, KBUILD_MODNAME, dev);
861 }
862
f6532111 863 if (ret) {
5db55844 864 wiphy_err(dev->wiphy, "failed to register IRQ handler\n");
f6532111
MW		 865 goto err_free_rings;
866 }
867
732c8932 868 rtl8180_int_enable(dev);
f6532111 869
f18f112b
AM		 870 /* in rtl8187se at MAR regs offset there is the management
871 * TX descriptor DMA addres..
872 */
873 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8187SE) {
874 rtl818x_iowrite32(priv, &priv->map->MAR[0], ~0);
875 rtl818x_iowrite32(priv, &priv->map->MAR[1], ~0);
876 }
f6532111
MW		 877
878 reg = RTL818X_RX_CONF_ONLYERLPKT |
879 RTL818X_RX_CONF_RX_AUTORESETPHY |
880 RTL818X_RX_CONF_MGMT |
881 RTL818X_RX_CONF_DATA |
882 (7 << 8 /* MAX RX DMA */) |
883 RTL818X_RX_CONF_BROADCAST |
884 RTL818X_RX_CONF_NICMAC;
885
6caefd12 886 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8185)
f6532111
MW		 887 reg |= RTL818X_RX_CONF_CSDM1 | RTL818X_RX_CONF_CSDM2;
888 else {
889 reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE1)
890 ? RTL818X_RX_CONF_CSDM1 : 0;
891 reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE2)
892 ? RTL818X_RX_CONF_CSDM2 : 0;
893 }
894
895 priv->rx_conf = reg;
896 rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
897
6caefd12 898 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180) {
f6532111 899 reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
14c76150 900
901 /* CW is not on per-packet basis.
902 * in rtl8185 the CW_VALUE reg is used.
903 */
6f7343d4 904 reg &= ~RTL818X_CW_CONF_PERPACKET_CW;
14c76150 905 /* retry limit IS on per-packet basis.
906 * the short and long retry limit in TX_CONF
907 * reg are ignored
908 */
6f7343d4 909 reg |= RTL818X_CW_CONF_PERPACKET_RETRY;
f6532111
MW		 910 rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
911
912 reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
14c76150 913 /* TX antenna and TX gain are not on per-packet basis.
914 * TX Antenna is selected by ANTSEL reg (RX in BB regs).
915 * TX gain is selected with CCK_TX_AGC and OFDM_TX_AGC regs
916 */
6f7343d4 917 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN;
918 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL;
f6532111
MW		 919 reg |= RTL818X_TX_AGC_CTL_FEEDBACK_ANT;
920 rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
921
922 /* disable early TX */
923 rtl818x_iowrite8(priv, (u8 __iomem *)priv->map + 0xec, 0x3f);
924 }
925
926 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
927 reg |= (6 << 21 /* MAX TX DMA */) |
928 RTL818X_TX_CONF_NO_ICV;
929
6caefd12
AM		 930
931
932 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180)
f6532111
MW		 933 reg &= ~RTL818X_TX_CONF_PROBE_DTS;
934 else
935 reg &= ~RTL818X_TX_CONF_HW_SEQNUM;
936
e74075a9 937 reg &= ~RTL818X_TX_CONF_DISCW;
938
f6532111
MW		 939 /* different meaning, same value on both rtl8185 and rtl8180 */
940 reg &= ~RTL818X_TX_CONF_SAT_HWPLCP;
941
942 rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
943
944 reg = rtl818x_ioread8(priv, &priv->map->CMD);
945 reg |= RTL818X_CMD_RX_ENABLE;
946 reg |= RTL818X_CMD_TX_ENABLE;
947 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
948
f6532111
MW		 949 return 0;
950
951 err_free_rings:
952 rtl8180_free_rx_ring(dev);
fd6564fc 953 for (i = 0; i < (dev->queues + 1); i++)
f6532111
MW		 954 if (priv->tx_ring[i].desc)
955 rtl8180_free_tx_ring(dev, i);
956
957 return ret;
958}
959
960static void rtl8180_stop(struct ieee80211_hw *dev)
961{
962 struct rtl8180_priv *priv = dev->priv;
963 u8 reg;
964 int i;
965
732c8932 966 rtl8180_int_disable(dev);
f6532111
MW		 967
968 reg = rtl818x_ioread8(priv, &priv->map->CMD);
969 reg &= ~RTL818X_CMD_TX_ENABLE;
970 reg &= ~RTL818X_CMD_RX_ENABLE;
971 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
972
973 priv->rf->stop(dev);
974
975 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
976 reg = rtl818x_ioread8(priv, &priv->map->CONFIG4);
977 rtl818x_iowrite8(priv, &priv->map->CONFIG4, reg | RTL818X_CONFIG4_VCOOFF);
978 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
979
980 free_irq(priv->pdev->irq, dev);
981
982 rtl8180_free_rx_ring(dev);
fd6564fc 983 for (i = 0; i < (dev->queues + 1); i++)
f6532111
MW		 984 rtl8180_free_tx_ring(dev, i);
985}
986
37a41b4a
EP		 987static u64 rtl8180_get_tsf(struct ieee80211_hw *dev,
988 struct ieee80211_vif *vif)
c809e86c
JL		 989{
990 struct rtl8180_priv *priv = dev->priv;
991
992 return rtl818x_ioread32(priv, &priv->map->TSFT[0]) |
993 (u64)(rtl818x_ioread32(priv, &priv->map->TSFT[1])) << 32;
994}
995
a3275e24 996static void rtl8180_beacon_work(struct work_struct *work)
c809e86c
JL		 997{
998 struct rtl8180_vif *vif_priv =
999 container_of(work, struct rtl8180_vif, beacon_work.work);
1000 struct ieee80211_vif *vif =
1001 container_of((void *)vif_priv, struct ieee80211_vif, drv_priv);
1002 struct ieee80211_hw *dev = vif_priv->dev;
1003 struct ieee80211_mgmt *mgmt;
1004 struct sk_buff *skb;
c809e86c
JL		 1005
1006 /* don't overflow the tx ring */
1007 if (ieee80211_queue_stopped(dev, 0))
1008 goto resched;
1009
1010 /* grab a fresh beacon */
1011 skb = ieee80211_beacon_get(dev, vif);
8f1d2d2b
JL		 1012 if (!skb)
1013 goto resched;
c809e86c
JL		 1014
1015 /*
1016 * update beacon timestamp w/ TSF value
1017 * TODO: make hardware update beacon timestamp
1018 */
1019 mgmt = (struct ieee80211_mgmt *)skb->data;
37a41b4a 1020 mgmt->u.beacon.timestamp = cpu_to_le64(rtl8180_get_tsf(dev, vif));
c809e86c
JL		 1021
1022 /* TODO: use actual beacon queue */
1023 skb_set_queue_mapping(skb, 0);
1024
36323f81 1025 rtl8180_tx(dev, NULL, skb);
c809e86c
JL		 1026
1027resched:
1028 /*
1029 * schedule next beacon
1030 * TODO: use hardware support for beacon timing
1031 */
1032 schedule_delayed_work(&vif_priv->beacon_work,
1033 usecs_to_jiffies(1024 * vif->bss_conf.beacon_int));
1034}
1035
f6532111 1036static int rtl8180_add_interface(struct ieee80211_hw *dev,
1ed32e4f 1037 struct ieee80211_vif *vif)
f6532111
MW		 1038{
1039 struct rtl8180_priv *priv = dev->priv;
c809e86c 1040 struct rtl8180_vif *vif_priv;
f6532111 1041
643aab67
JL		 1042 /*
1043 * We only support one active interface at a time.
1044 */
1045 if (priv->vif)
1046 return -EBUSY;
f6532111 1047
1ed32e4f 1048 switch (vif->type) {
05c914fe 1049 case NL80211_IFTYPE_STATION:
c809e86c 1050 case NL80211_IFTYPE_ADHOC:
f6532111
MW		 1051 break;
1052 default:
1053 return -EOPNOTSUPP;
1054 }
1055
1ed32e4f 1056 priv->vif = vif;
32bfd35d 1057
c809e86c
JL		 1058 /* Initialize driver private area */
1059 vif_priv = (struct rtl8180_vif *)&vif->drv_priv;
1060 vif_priv->dev = dev;
1061 INIT_DELAYED_WORK(&vif_priv->beacon_work, rtl8180_beacon_work);
1062 vif_priv->enable_beacon = false;
1063
f6532111
MW		 1064 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
1065 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->MAC[0],
1ed32e4f 1066 le32_to_cpu(*(__le32 *)vif->addr));
f6532111 1067 rtl818x_iowrite16(priv, (__le16 __iomem *)&priv->map->MAC[4],
1ed32e4f 1068 le16_to_cpu(*(__le16 *)(vif->addr + 4)));
f6532111
MW		 1069 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
1070
1071 return 0;
1072}
1073
1074static void rtl8180_remove_interface(struct ieee80211_hw *dev,
1ed32e4f 1075 struct ieee80211_vif *vif)
f6532111
MW		 1076{
1077 struct rtl8180_priv *priv = dev->priv;
32bfd35d 1078 priv->vif = NULL;
f6532111
MW		 1079}
1080
e8975581 1081static int rtl8180_config(struct ieee80211_hw *dev, u32 changed)
f6532111
MW		 1082{
1083 struct rtl8180_priv *priv = dev->priv;
e8975581 1084 struct ieee80211_conf *conf = &dev->conf;
f6532111
MW		 1085
1086 priv->rf->set_chan(dev, conf);
1087
1088 return 0;
1089}
1090
9069af79
AM		 1091static int rtl8180_conf_tx(struct ieee80211_hw *dev,
1092 struct ieee80211_vif *vif, u16 queue,
1093 const struct ieee80211_tx_queue_params *params)
1094{
1095 struct rtl8180_priv *priv = dev->priv;
1096 u8 cw_min, cw_max;
1097
1098 /* nothing to do ? */
1099 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180)
1100 return 0;
1101
1102 cw_min = fls(params->cw_min);
1103 cw_max = fls(params->cw_max);
1104
1105 rtl818x_iowrite8(priv, &priv->map->CW_VAL, (cw_max << 4) | cw_min);
1106
1107 return 0;
1108}
1109
1110static void rtl8180_conf_erp(struct ieee80211_hw *dev,
1111 struct ieee80211_bss_conf *info)
1112{
1113 struct rtl8180_priv *priv = dev->priv;
1114 u8 sifs, difs;
1115 int eifs;
1116 u8 hw_eifs;
1117
1118 /* TODO: should we do something ? */
1119 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180)
1120 return;
1121
1122 /* I _hope_ this means 10uS for the HW.
1123 * In reference code it is 0x22 for
1124 * both rtl8187L and rtl8187SE
1125 */
1126 sifs = 0x22;
1127
1128 if (info->use_short_slot)
1129 priv->slot_time = 9;
1130 else
1131 priv->slot_time = 20;
1132
1133 /* 10 is SIFS time in uS */
1134 difs = 10 + 2 * priv->slot_time;
1135 eifs = 10 + difs + priv->ack_time;
1136
1137 /* HW should use 4uS units for EIFS (I'm sure for rtl8185)*/
1138 hw_eifs = DIV_ROUND_UP(eifs, 4);
1139
1140
1141 rtl818x_iowrite8(priv, &priv->map->SLOT, priv->slot_time);
1142 rtl818x_iowrite8(priv, &priv->map->SIFS, sifs);
1143 rtl818x_iowrite8(priv, &priv->map->DIFS, difs);
1144
1145 /* from reference code. set ack timeout reg = eifs reg */
1146 rtl818x_iowrite8(priv, &priv->map->CARRIER_SENSE_COUNTER, hw_eifs);
1147
1148 /* rtl8187/rtl8185 HW bug. After EIFS is elapsed,
1149 * the HW still wait for DIFS.
1150 * HW uses 4uS units for EIFS.
1151 */
1152 hw_eifs = DIV_ROUND_UP(eifs - difs, 4);
1153
1154 rtl818x_iowrite8(priv, &priv->map->EIFS, hw_eifs);
1155}
1156
da81dede
JL		 1157static void rtl8180_bss_info_changed(struct ieee80211_hw *dev,
1158 struct ieee80211_vif *vif,
1159 struct ieee80211_bss_conf *info,
1160 u32 changed)
1161{
1162 struct rtl8180_priv *priv = dev->priv;
c809e86c 1163 struct rtl8180_vif *vif_priv;
2d0ddec5 1164 int i;
0f956e71 1165 u8 reg;
2d0ddec5 1166
c809e86c
JL		 1167 vif_priv = (struct rtl8180_vif *)&vif->drv_priv;
1168
2d0ddec5
JB		 1169 if (changed & BSS_CHANGED_BSSID) {
1170 for (i = 0; i < ETH_ALEN; i++)
1171 rtl818x_iowrite8(priv, &priv->map->BSSID[i],
1172 info->bssid[i]);
1173
0f956e71
JL		 1174 if (is_valid_ether_addr(info->bssid)) {
1175 if (vif->type == NL80211_IFTYPE_ADHOC)
1176 reg = RTL818X_MSR_ADHOC;
1177 else
1178 reg = RTL818X_MSR_INFRA;
1179 } else
1180 reg = RTL818X_MSR_NO_LINK;
1181 rtl818x_iowrite8(priv, &priv->map->MSR, reg);
2d0ddec5 1182 }
da81dede 1183
516a0930
AM		 1184 if (changed & BSS_CHANGED_BASIC_RATES)
1185 rtl8180_conf_basic_rates(dev, info->basic_rates);
1186
9069af79
AM		 1187 if (changed & (BSS_CHANGED_ERP_SLOT | BSS_CHANGED_ERP_PREAMBLE)) {
1188
1189 /* when preamble changes, acktime duration changes, and erp must
1190 * be recalculated. ACK time is calculated at lowest rate.
1191 * Since mac80211 include SIFS time we remove it (-10)
1192 */
1193 priv->ack_time =
1194 le16_to_cpu(ieee80211_generic_frame_duration(dev,
1195 priv->vif,
1196 IEEE80211_BAND_2GHZ, 10,
1197 &priv->rates[0])) - 10;
1198
1199 rtl8180_conf_erp(dev, info);
1200 }
c809e86c
JL		 1201
1202 if (changed & BSS_CHANGED_BEACON_ENABLED)
1203 vif_priv->enable_beacon = info->enable_beacon;
1204
1205 if (changed & (BSS_CHANGED_BEACON_ENABLED | BSS_CHANGED_BEACON)) {
1206 cancel_delayed_work_sync(&vif_priv->beacon_work);
1207 if (vif_priv->enable_beacon)
1208 schedule_work(&vif_priv->beacon_work.work);
1209 }
da81dede
JL		 1210}
1211
22bedad3
JP		 1212static u64 rtl8180_prepare_multicast(struct ieee80211_hw *dev,
1213 struct netdev_hw_addr_list *mc_list)
3ac64bee 1214{
22bedad3 1215 return netdev_hw_addr_list_count(mc_list);
3ac64bee
JB		 1216}
1217
f6532111
MW		 1218static void rtl8180_configure_filter(struct ieee80211_hw *dev,
1219 unsigned int changed_flags,
1220 unsigned int *total_flags,
3ac64bee 1221 u64 multicast)
f6532111
MW		 1222{
1223 struct rtl8180_priv *priv = dev->priv;
1224
1225 if (changed_flags & FIF_FCSFAIL)
1226 priv->rx_conf ^= RTL818X_RX_CONF_FCS;
1227 if (changed_flags & FIF_CONTROL)
1228 priv->rx_conf ^= RTL818X_RX_CONF_CTRL;
1229 if (changed_flags & FIF_OTHER_BSS)
1230 priv->rx_conf ^= RTL818X_RX_CONF_MONITOR;
3ac64bee 1231 if (*total_flags & FIF_ALLMULTI || multicast > 0)
f6532111
MW		 1232 priv->rx_conf |= RTL818X_RX_CONF_MULTICAST;
1233 else
1234 priv->rx_conf &= ~RTL818X_RX_CONF_MULTICAST;
1235
1236 *total_flags = 0;
1237
1238 if (priv->rx_conf & RTL818X_RX_CONF_FCS)
1239 *total_flags |= FIF_FCSFAIL;
1240 if (priv->rx_conf & RTL818X_RX_CONF_CTRL)
1241 *total_flags |= FIF_CONTROL;
1242 if (priv->rx_conf & RTL818X_RX_CONF_MONITOR)
1243 *total_flags |= FIF_OTHER_BSS;
1244 if (priv->rx_conf & RTL818X_RX_CONF_MULTICAST)
1245 *total_flags |= FIF_ALLMULTI;
1246
1247 rtl818x_iowrite32(priv, &priv->map->RX_CONF, priv->rx_conf);
1248}
1249
1250static const struct ieee80211_ops rtl8180_ops = {
1251 .tx = rtl8180_tx,
1252 .start = rtl8180_start,
1253 .stop = rtl8180_stop,
1254 .add_interface = rtl8180_add_interface,
1255 .remove_interface = rtl8180_remove_interface,
1256 .config = rtl8180_config,
da81dede 1257 .bss_info_changed = rtl8180_bss_info_changed,
9069af79 1258 .conf_tx = rtl8180_conf_tx,
3ac64bee 1259 .prepare_multicast = rtl8180_prepare_multicast,
f6532111 1260 .configure_filter = rtl8180_configure_filter,
d2bb8e02 1261 .get_tsf = rtl8180_get_tsf,
f6532111
MW		 1262};
1263
1264static void rtl8180_eeprom_register_read(struct eeprom_93cx6 *eeprom)
1265{
7d4b829a 1266 struct rtl8180_priv *priv = eeprom->data;
f6532111
MW		 1267 u8 reg = rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
1268
1269 eeprom->reg_data_in = reg & RTL818X_EEPROM_CMD_WRITE;
1270 eeprom->reg_data_out = reg & RTL818X_EEPROM_CMD_READ;
1271 eeprom->reg_data_clock = reg & RTL818X_EEPROM_CMD_CK;
1272 eeprom->reg_chip_select = reg & RTL818X_EEPROM_CMD_CS;
1273}
1274
1275static void rtl8180_eeprom_register_write(struct eeprom_93cx6 *eeprom)
1276{
7d4b829a 1277 struct rtl8180_priv *priv = eeprom->data;
f6532111
MW		 1278 u8 reg = 2 << 6;
1279
1280 if (eeprom->reg_data_in)
1281 reg |= RTL818X_EEPROM_CMD_WRITE;
1282 if (eeprom->reg_data_out)
1283 reg |= RTL818X_EEPROM_CMD_READ;
1284 if (eeprom->reg_data_clock)
1285 reg |= RTL818X_EEPROM_CMD_CK;
1286 if (eeprom->reg_chip_select)
1287 reg |= RTL818X_EEPROM_CMD_CS;
1288
1289 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, reg);
1290 rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
1291 udelay(10);
1292}
1293
7d4b829a
AM		 1294static void rtl8180_eeprom_read(struct rtl8180_priv *priv)
1295{
1296 struct eeprom_93cx6 eeprom;
1297 int eeprom_cck_table_adr;
1298 u16 eeprom_val;
1299 int i;
1300
1301 eeprom.data = priv;
1302 eeprom.register_read = rtl8180_eeprom_register_read;
1303 eeprom.register_write = rtl8180_eeprom_register_write;
1304 if (rtl818x_ioread32(priv, &priv->map->RX_CONF) & (1 << 6))
1305 eeprom.width = PCI_EEPROM_WIDTH_93C66;
1306 else
1307 eeprom.width = PCI_EEPROM_WIDTH_93C46;
1308
1309 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
1310 RTL818X_EEPROM_CMD_PROGRAM);
1311 rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
1312 udelay(10);
1313
1314 eeprom_93cx6_read(&eeprom, 0x06, &eeprom_val);
1315 eeprom_val &= 0xFF;
1316 priv->rf_type = eeprom_val;
1317
1318 eeprom_93cx6_read(&eeprom, 0x17, &eeprom_val);
1319 priv->csthreshold = eeprom_val >> 8;
1320
1321 eeprom_93cx6_multiread(&eeprom, 0x7, (__le16 *)priv->mac_addr, 3);
1322
1323 eeprom_cck_table_adr = 0x10;
1324
1325 /* CCK TX power */
1326 for (i = 0; i < 14; i += 2) {
1327 u16 txpwr;
1328 eeprom_93cx6_read(&eeprom, eeprom_cck_table_adr + (i >> 1),
1329 &txpwr);
1330 priv->channels[i].hw_value = txpwr & 0xFF;
1331 priv->channels[i + 1].hw_value = txpwr >> 8;
1332 }
1333
1334 /* OFDM TX power */
1335 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180) {
1336 for (i = 0; i < 14; i += 2) {
1337 u16 txpwr;
1338 eeprom_93cx6_read(&eeprom, 0x20 + (i >> 1), &txpwr);
1339 priv->channels[i].hw_value |= (txpwr & 0xFF) << 8;
1340 priv->channels[i + 1].hw_value |= txpwr & 0xFF00;
1341 }
1342 }
1343
1344 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180) {
1345 __le32 anaparam;
1346 eeprom_93cx6_multiread(&eeprom, 0xD, (__le16 *)&anaparam, 2);
1347 priv->anaparam = le32_to_cpu(anaparam);
1348 eeprom_93cx6_read(&eeprom, 0x19, &priv->rfparam);
1349 }
1350
1351 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
1352 RTL818X_EEPROM_CMD_NORMAL);
1353}
1354
fb4e899d 1355static int rtl8180_probe(struct pci_dev *pdev,
f6532111
MW		 1356 const struct pci_device_id *id)
1357{
1358 struct ieee80211_hw *dev;
1359 struct rtl8180_priv *priv;
1360 unsigned long mem_addr, mem_len;
1361 unsigned int io_addr, io_len;
7d4b829a 1362 int err;
f6532111
MW		 1363 const char *chip_name, *rf_name = NULL;
1364 u32 reg;
f6532111
MW		 1365
1366 err = pci_enable_device(pdev);
1367 if (err) {
1368 printk(KERN_ERR "%s (rtl8180): Cannot enable new PCI device\n",
1369 pci_name(pdev));
1370 return err;
1371 }
1372
1373 err = pci_request_regions(pdev, KBUILD_MODNAME);
1374 if (err) {
1375 printk(KERN_ERR "%s (rtl8180): Cannot obtain PCI resources\n",
1376 pci_name(pdev));
1377 return err;
1378 }
1379
1380 io_addr = pci_resource_start(pdev, 0);
1381 io_len = pci_resource_len(pdev, 0);
1382 mem_addr = pci_resource_start(pdev, 1);
1383 mem_len = pci_resource_len(pdev, 1);
1384
1385 if (mem_len < sizeof(struct rtl818x_csr) ||
1386 io_len < sizeof(struct rtl818x_csr)) {
1387 printk(KERN_ERR "%s (rtl8180): Too short PCI resources\n",
1388 pci_name(pdev));
1389 err = -ENOMEM;
1390 goto err_free_reg;
1391 }
1392
9e385c56
JL		 1393 if ((err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) ||
1394 (err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))) {
f6532111
MW		 1395 printk(KERN_ERR "%s (rtl8180): No suitable DMA available\n",
1396 pci_name(pdev));
1397 goto err_free_reg;
1398 }
1399
1400 pci_set_master(pdev);
1401
1402 dev = ieee80211_alloc_hw(sizeof(*priv), &rtl8180_ops);
1403 if (!dev) {
1404 printk(KERN_ERR "%s (rtl8180): ieee80211 alloc failed\n",
1405 pci_name(pdev));
1406 err = -ENOMEM;
1407 goto err_free_reg;
1408 }
1409
1410 priv = dev->priv;
1411 priv->pdev = pdev;
1412
e6a9854b 1413 dev->max_rates = 2;
f6532111
MW		 1414 SET_IEEE80211_DEV(dev, &pdev->dev);
1415 pci_set_drvdata(pdev, dev);
1416
1417 priv->map = pci_iomap(pdev, 1, mem_len);
1418 if (!priv->map)
1419 priv->map = pci_iomap(pdev, 0, io_len);
1420
1421 if (!priv->map) {
1422 printk(KERN_ERR "%s (rtl8180): Cannot map device memory\n",
1423 pci_name(pdev));
1424 goto err_free_dev;
1425 }
1426
8318d78a
JB		 1427 BUILD_BUG_ON(sizeof(priv->channels) != sizeof(rtl818x_channels));
1428 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(rtl818x_rates));
1429
f6532111
MW		 1430 memcpy(priv->channels, rtl818x_channels, sizeof(rtl818x_channels));
1431 memcpy(priv->rates, rtl818x_rates, sizeof(rtl818x_rates));
8318d78a
JB		 1432
1433 priv->band.band = IEEE80211_BAND_2GHZ;
1434 priv->band.channels = priv->channels;
1435 priv->band.n_channels = ARRAY_SIZE(rtl818x_channels);
1436 priv->band.bitrates = priv->rates;
1437 priv->band.n_bitrates = 4;
1438 dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
1439
f6532111 1440 dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
566bfe5a
BR		 1441 IEEE80211_HW_RX_INCLUDES_FCS |
1442 IEEE80211_HW_SIGNAL_UNSPEC;
c809e86c
JL		 1443 dev->vif_data_size = sizeof(struct rtl8180_vif);
1444 dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
1445 BIT(NL80211_IFTYPE_ADHOC);
566bfe5a 1446 dev->max_signal = 65;
f6532111
MW		 1447
1448 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
1449 reg &= RTL818X_TX_CONF_HWVER_MASK;
1450 switch (reg) {
1451 case RTL818X_TX_CONF_R8180_ABCD:
1452 chip_name = "RTL8180";
6caefd12 1453 priv->chip_family = RTL818X_CHIP_FAMILY_RTL8180;
f6532111 1454 break;
6caefd12 1455
f6532111
MW		 1456 case RTL818X_TX_CONF_R8180_F:
1457 chip_name = "RTL8180vF";
6caefd12 1458 priv->chip_family = RTL818X_CHIP_FAMILY_RTL8180;
f6532111 1459 break;
6caefd12 1460
f6532111
MW		 1461 case RTL818X_TX_CONF_R8185_ABC:
1462 chip_name = "RTL8185";
6caefd12 1463 priv->chip_family = RTL818X_CHIP_FAMILY_RTL8185;
f6532111 1464 break;
6caefd12 1465
f6532111
MW		 1466 case RTL818X_TX_CONF_R8185_D:
1467 chip_name = "RTL8185vD";
6caefd12 1468 priv->chip_family = RTL818X_CHIP_FAMILY_RTL8185;
f6532111
MW		 1469 break;
1470 default:
1471 printk(KERN_ERR "%s (rtl8180): Unknown chip! (0x%x)\n",
1472 pci_name(pdev), reg >> 25);
1473 goto err_iounmap;
1474 }
1475
fd6564fc
AM		 1476 /* we declare to MAC80211 all the queues except for beacon queue
1477 * that will be eventually handled by DRV.
1478 * TX rings are arranged in such a way that lower is the IDX,
1479 * higher is the priority, in order to achieve direct mapping
1480 * with mac80211, however the beacon queue is an exception and it
1481 * is mapped on the highst tx ring IDX.
1482 */
1483 dev->queues = RTL8180_NR_TX_QUEUES - 1;
1484
6caefd12 1485 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180) {
8318d78a 1486 priv->band.n_bitrates = ARRAY_SIZE(rtl818x_rates);
f6532111
MW		 1487 pci_try_set_mwi(pdev);
1488 }
1489
7d4b829a 1490 rtl8180_eeprom_read(priv);
f6532111 1491
7d4b829a 1492 switch (priv->rf_type) {
f6532111
MW		 1493 case 1: rf_name = "Intersil";
1494 break;
1495 case 2: rf_name = "RFMD";
1496 break;
1497 case 3: priv->rf = &sa2400_rf_ops;
1498 break;
1499 case 4: priv->rf = &max2820_rf_ops;
1500 break;
1501 case 5: priv->rf = &grf5101_rf_ops;
1502 break;
1503 case 9: priv->rf = rtl8180_detect_rf(dev);
1504 break;
1505 case 10:
1506 rf_name = "RTL8255";
1507 break;
1508 default:
1509 printk(KERN_ERR "%s (rtl8180): Unknown RF! (0x%x)\n",
7d4b829a 1510 pci_name(pdev), priv->rf_type);
f6532111
MW		 1511 goto err_iounmap;
1512 }
1513
1514 if (!priv->rf) {
1515 printk(KERN_ERR "%s (rtl8180): %s RF frontend not supported!\n",
1516 pci_name(pdev), rf_name);
1517 goto err_iounmap;
1518 }
1519
7d4b829a 1520 if (!is_valid_ether_addr(priv->mac_addr)) {
f6532111
MW		 1521 printk(KERN_WARNING "%s (rtl8180): Invalid hwaddr! Using"
1522 " randomly generated MAC addr\n", pci_name(pdev));
7d4b829a 1523 eth_random_addr(priv->mac_addr);
f6532111 1524 }
7d4b829a 1525 SET_IEEE80211_PERM_ADDR(dev, priv->mac_addr);
f6532111
MW		 1526
1527 spin_lock_init(&priv->lock);
1528
1529 err = ieee80211_register_hw(dev);
1530 if (err) {
1531 printk(KERN_ERR "%s (rtl8180): Cannot register device\n",
1532 pci_name(pdev));
1533 goto err_iounmap;
1534 }
1535
c96c31e4 1536 wiphy_info(dev->wiphy, "hwaddr %pm, %s + %s\n",
7d4b829a 1537 priv->mac_addr, chip_name, priv->rf->name);
f6532111
MW		 1538
1539 return 0;
1540
1541 err_iounmap:
0269da28 1542 pci_iounmap(pdev, priv->map);
f6532111
MW		 1543
1544 err_free_dev:
f6532111
MW		 1545 ieee80211_free_hw(dev);
1546
1547 err_free_reg:
1548 pci_release_regions(pdev);
1549 pci_disable_device(pdev);
1550 return err;
1551}
1552
fb4e899d 1553static void rtl8180_remove(struct pci_dev *pdev)
f6532111
MW		 1554{
1555 struct ieee80211_hw *dev = pci_get_drvdata(pdev);
1556 struct rtl8180_priv *priv;
1557
1558 if (!dev)
1559 return;
1560
1561 ieee80211_unregister_hw(dev);
1562
1563 priv = dev->priv;
1564
1565 pci_iounmap(pdev, priv->map);
1566 pci_release_regions(pdev);
1567 pci_disable_device(pdev);
1568 ieee80211_free_hw(dev);
1569}
1570
1571#ifdef CONFIG_PM
1572static int rtl8180_suspend(struct pci_dev *pdev, pm_message_t state)
1573{
1574 pci_save_state(pdev);
1575 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1576 return 0;
1577}
1578
1579static int rtl8180_resume(struct pci_dev *pdev)
1580{
1581 pci_set_power_state(pdev, PCI_D0);
1582 pci_restore_state(pdev);
1583 return 0;
1584}
1585
1586#endif /* CONFIG_PM */
1587
1588static struct pci_driver rtl8180_driver = {
1589 .name = KBUILD_MODNAME,
1590 .id_table = rtl8180_table,
1591 .probe = rtl8180_probe,
fb4e899d 1592 .remove = rtl8180_remove,
f6532111
MW		 1593#ifdef CONFIG_PM
1594 .suspend = rtl8180_suspend,
1595 .resume = rtl8180_resume,
1596#endif /* CONFIG_PM */
1597};
1598
5b0a3b7e 1599module_pci_driver(rtl8180_driver);
Linux kernel - Deliverables
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