[deliverable/linux.git] / drivers / net / wireless / rtlwifi / debug.h

/******************************************************************************
 *
 * Copyright(c) 2009-2010  Realtek Corporation.
 *
 * Tmis program is free software; you can redistribute it and/or modify it
 * under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * Tmis program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * tmis program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
 *
 * Tme full GNU General Public License is included in this distribution in the
 * file called LICENSE.
 *
 * Contact Information:
 * wlanfae <wlanfae@realtek.com>
 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
 * Hsinchu 300, Taiwan.
 *
 * Larry Finger <Larry.Finger@lwfinger.net>
 *****************************************************************************/

#ifndef __RTL_DEBUG_H__
#define __RTL_DEBUG_H__

/*--------------------------------------------------------------
			Debug level
--------------------------------------------------------------*/
/*
 *Fatal bug.
 *For example, Tx/Rx/IO locked up,
 *memory access violation,
 *resource allocation failed,
 *unexpected HW behavior, HW BUG
 *and so on.
 */
#define DBG_EMERG			0

/*
 *Abnormal, rare, or unexpeted cases.
 *For example, Packet/IO Ctl canceled,
 *device suprisely unremoved and so on.
 */
#define	DBG_WARNING			2

/*
 *Normal case driver developer should
 *open, we can see link status like
 *assoc/AddBA/DHCP/adapter start and
 *so on basic and useful infromations.
 */
#define DBG_DMESG			3

/*
 *Normal case with useful information
 *about current SW or HW state.
 *For example, Tx/Rx descriptor to fill,
 *Tx/Rx descriptor completed status,
 *SW protocol state change, dynamic
 *mechanism state change and so on.
 */
#define DBG_LOUD			4

/*
 *Normal case with detail execution
 *flow or information.
 */
#define	DBG_TRACE			5

/*--------------------------------------------------------------
		Define the rt_trace components
--------------------------------------------------------------*/
#define COMP_ERR			BIT(0)
#define COMP_FW				BIT(1)
#define COMP_INIT			BIT(2)	/*For init/deinit */
#define COMP_RECV			BIT(3)	/*For Rx. */
#define COMP_SEND			BIT(4)	/*For Tx. */
#define COMP_MLME			BIT(5)	/*For MLME. */
#define COMP_SCAN			BIT(6)	/*For Scan. */
#define COMP_INTR			BIT(7)	/*For interrupt Related. */
#define COMP_LED			BIT(8)	/*For LED. */
#define COMP_SEC			BIT(9)	/*For sec. */
#define COMP_BEACON			BIT(10)	/*For beacon. */
#define COMP_RATE			BIT(11)	/*For rate. */
#define COMP_RXDESC			BIT(12)	/*For rx desc. */
#define COMP_DIG			BIT(13)	/*For DIG */
#define COMP_TXAGC			BIT(14)	/*For Tx power */
#define COMP_HIPWR			BIT(15)	/*For High Power Mechanism */
#define COMP_POWER			BIT(16)	/*For lps/ips/aspm. */
#define COMP_POWER_TRACKING	BIT(17)	/*For TX POWER TRACKING */
#define COMP_BB_POWERSAVING	BIT(18)
#define COMP_SWAS			BIT(19)	/*For SW Antenna Switch */
#define COMP_RF				BIT(20)	/*For RF. */
#define COMP_TURBO			BIT(21)	/*For EDCA TURBO. */
#define COMP_RATR			BIT(22)
#define COMP_CMD			BIT(23)
#define COMP_EFUSE			BIT(24)
#define COMP_QOS			BIT(25)
#define COMP_MAC80211		BIT(26)
#define COMP_REGD			BIT(27)
#define COMP_CHAN			BIT(28)
#define COMP_USB			BIT(29)

/*--------------------------------------------------------------
		Define the rt_print components
--------------------------------------------------------------*/
/* Define EEPROM and EFUSE  check module bit*/
#define EEPROM_W			BIT(0)
#define EFUSE_PG			BIT(1)
#define EFUSE_READ_ALL		BIT(2)

/* Define init check for module bit*/
#define	INIT_EEPROM			BIT(0)
#define	INIT_TxPower		BIT(1)
#define	INIT_IQK			BIT(2)
#define	INIT_RF				BIT(3)

/* Define PHY-BB/RF/MAC check module bit */
#define	PHY_BBR				BIT(0)
#define	PHY_BBW				BIT(1)
#define	PHY_RFR				BIT(2)
#define	PHY_RFW				BIT(3)
#define	PHY_MACR			BIT(4)
#define	PHY_MACW			BIT(5)
#define	PHY_ALLR			BIT(6)
#define	PHY_ALLW			BIT(7)
#define	PHY_TXPWR			BIT(8)
#define	PHY_PWRDIFF			BIT(9)

enum dbgp_flag_e {
	FQOS = 0,
	FTX = 1,
	FRX = 2,
	FSEC = 3,
	FMGNT = 4,
	FMLME = 5,
	FRESOURCE = 6,
	FBEACON = 7,
	FISR = 8,
	FPHY = 9,
	FMP = 10,
	FEEPROM = 11,
	FPWR = 12,
	FDM = 13,
	FDBGCtrl = 14,
	FC2H = 15,
	FBT = 16,
	FINIT = 17,
	FIOCTL = 18,
	DBGP_TYPE_MAX
};

#define RT_ASSERT(_exp, fmt)				\
	do {						\
		if (!(_exp)) {			\
			printk(KERN_DEBUG "%s:%s(): ", KBUILD_MODNAME, \
			__func__);			\
			printk fmt;			\
		} \
	} while (0);

#define RT_TRACE(rtlpriv, comp, level, fmt)\
	do { \
		if (unlikely(((comp) & rtlpriv->dbg.global_debugcomponents) && \
			((level) <= rtlpriv->dbg.global_debuglevel))) {\
			printk(KERN_DEBUG "%s:%s():<%lx-%x> ", KBUILD_MODNAME, \
			__func__, in_interrupt(), in_atomic());	\
			printk fmt;				\
		} \
	} while (0);

#define RTPRINT(rtlpriv, dbgtype, dbgflag, printstr)	\
	do {						\
		if (unlikely(rtlpriv->dbg.dbgp_type[dbgtype] & dbgflag)) { \
			printk(KERN_DEBUG "%s: ", KBUILD_MODNAME);	\
			printk printstr;		\
		}					\
	} while (0);

#define RT_PRINT_DATA(rtlpriv, _comp, _level, _titlestring, _hexdata, \
		_hexdatalen) \
	do {\
		if (unlikely(((_comp) & rtlpriv->dbg.global_debugcomponents) &&\
			(_level <= rtlpriv->dbg.global_debuglevel)))	{ \
			int __i;					\
			u8*	ptr = (u8 *)_hexdata;			\
			printk(KERN_DEBUG "%s: ", KBUILD_MODNAME);	\
			printk("In process \"%s\" (pid %i):", current->comm,\
					current->pid); \
			printk(_titlestring);		\
			for (__i = 0; __i < (int)_hexdatalen; __i++) {	\
				printk("%02X%s", ptr[__i], (((__i + 1) % 4)\
							== 0) ? "  " : " ");\
				if (((__i + 1) % 16) == 0)		\
					printk("\n");			\
			}				\
			printk(KERN_DEBUG "\n");			\
		} \
	} while (0);

#define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x"
#define MAC_ARG(x) \
	((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2],\
	((u8 *)(x))[3], ((u8 *)(x))[4], ((u8 *)(x))[5]

void rtl_dbgp_flag_init(struct ieee80211_hw *hw);
#endif
Commit	Line	Data
0c817338 LF	1	/******************************************************************************
	2	*
	3	* Copyright(c) 2009-2010 Realtek Corporation.
	4	*
	5	* Tmis program is free software; you can redistribute it and/or modify it
	6	* under the terms of version 2 of the GNU General Public License as
	7	* published by the Free Software Foundation.
	8	*
	9	* Tmis program is distributed in the hope that it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
	14	* You should have received a copy of the GNU General Public License along with
	15	* tmis program; if not, write to the Free Software Foundation, Inc.,
	16	* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
	17	*
	18	* Tme full GNU General Public License is included in this distribution in the
	19	* file called LICENSE.
	20	*
	21	* Contact Information:
	22	* wlanfae <wlanfae@realtek.com>
	23	* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
	24	* Hsinchu 300, Taiwan.
	25	*
	26	* Larry Finger <Larry.Finger@lwfinger.net>
	27	*****************************************************************************/
	28
	29	#ifndef __RTL_DEBUG_H__
	30	#define __RTL_DEBUG_H__
	31
	32	/*--------------------------------------------------------------
	33	Debug level
	34	--------------------------------------------------------------*/
	35	/*
	36	*Fatal bug.
	37	*For example, Tx/Rx/IO locked up,
	38	*memory access violation,
	39	*resource allocation failed,
	40	*unexpected HW behavior, HW BUG
	41	*and so on.
	42	*/
	43	#define DBG_EMERG 0
	44
	45	/*
	46	*Abnormal, rare, or unexpeted cases.
	47	*For example, Packet/IO Ctl canceled,
	48	*device suprisely unremoved and so on.
	49	*/
	50	#define DBG_WARNING 2
	51
	52	/*
	53	*Normal case driver developer should
	54	*open, we can see link status like
	55	*assoc/AddBA/DHCP/adapter start and
	56	*so on basic and useful infromations.
	57	*/
	58	#define DBG_DMESG 3
	59
	60	/*
	61	*Normal case with useful information
	62	*about current SW or HW state.
	63	*For example, Tx/Rx descriptor to fill,
	64	*Tx/Rx descriptor completed status,
65	*SW protocol state change, dynamic
66	*mechanism state change and so on.
67	*/
68	#define DBG_LOUD 4
69
70	/*
71	*Normal case with detail execution
72	*flow or information.
73	*/
74	#define DBG_TRACE 5
75
76	/*--------------------------------------------------------------
77	Define the rt_trace components
78	--------------------------------------------------------------*/
79	#define COMP_ERR BIT(0)
80	#define COMP_FW BIT(1)
81	#define COMP_INIT BIT(2) /For init/deinit /
82	#define COMP_RECV BIT(3) /For Rx. /
83	#define COMP_SEND BIT(4) /For Tx. /
84	#define COMP_MLME BIT(5) /For MLME. /
85	#define COMP_SCAN BIT(6) /For Scan. /
86	#define COMP_INTR BIT(7) /For interrupt Related. /
87	#define COMP_LED BIT(8) /For LED. /
88	#define COMP_SEC BIT(9) /For sec. /
89	#define COMP_BEACON BIT(10) /For beacon. /
90	#define COMP_RATE BIT(11) /For rate. /
91	#define COMP_RXDESC BIT(12) /For rx desc. /
92	#define COMP_DIG BIT(13) /For DIG /
93	#define COMP_TXAGC BIT(14) /For Tx power /
94	#define COMP_HIPWR BIT(15) /For High Power Mechanism /
95	#define COMP_POWER BIT(16) /For lps/ips/aspm. /
96	#define COMP_POWER_TRACKING BIT(17) /For TX POWER TRACKING /
97	#define COMP_BB_POWERSAVING BIT(18)
98	#define COMP_SWAS BIT(19) /For SW Antenna Switch /
99	#define COMP_RF BIT(20) /For RF. /
100	#define COMP_TURBO BIT(21) /For EDCA TURBO. /
101	#define COMP_RATR BIT(22)
102	#define COMP_CMD BIT(23)
103	#define COMP_EFUSE BIT(24)
104	#define COMP_QOS BIT(25)
105	#define COMP_MAC80211 BIT(26)
106	#define COMP_REGD BIT(27)
107	#define COMP_CHAN BIT(28)
62e63975	108	#define COMP_USB BIT(29)
0c817338 LF	109
	110	/*--------------------------------------------------------------
	111	Define the rt_print components
	112	--------------------------------------------------------------*/
	113	/* Define EEPROM and EFUSE check module bit*/
	114	#define EEPROM_W BIT(0)
	115	#define EFUSE_PG BIT(1)
	116	#define EFUSE_READ_ALL BIT(2)
	117
	118	/* Define init check for module bit*/
	119	#define INIT_EEPROM BIT(0)
	120	#define INIT_TxPower BIT(1)
	121	#define INIT_IQK BIT(2)
	122	#define INIT_RF BIT(3)
	123
	124	/* Define PHY-BB/RF/MAC check module bit */
	125	#define PHY_BBR BIT(0)
	126	#define PHY_BBW BIT(1)
	127	#define PHY_RFR BIT(2)
	128	#define PHY_RFW BIT(3)
	129	#define PHY_MACR BIT(4)
	130	#define PHY_MACW BIT(5)
	131	#define PHY_ALLR BIT(6)
	132	#define PHY_ALLW BIT(7)
	133	#define PHY_TXPWR BIT(8)
	134	#define PHY_PWRDIFF BIT(9)
	135
	136	enum dbgp_flag_e {
	137	FQOS = 0,
	138	FTX = 1,
	139	FRX = 2,
	140	FSEC = 3,
	141	FMGNT = 4,
	142	FMLME = 5,
	143	FRESOURCE = 6,
	144	FBEACON = 7,
	145	FISR = 8,
	146	FPHY = 9,
	147	FMP = 10,
	148	FEEPROM = 11,
	149	FPWR = 12,
	150	FDM = 13,
	151	FDBGCtrl = 14,
	152	FC2H = 15,
	153	FBT = 16,
	154	FINIT = 17,
	155	FIOCTL = 18,
	156	DBGP_TYPE_MAX
	157	};
	158
	159	#define RT_ASSERT(_exp, fmt) \
	160	do { \
	161	if (!(_exp)) { \
	162	printk(KERN_DEBUG "%s:%s(): ", KBUILD_MODNAME, \
	163	__func__); \
	164	printk fmt; \
	165	} \
	166	} while (0);
	167
	168	#define RT_TRACE(rtlpriv, comp, level, fmt)\
	169	do { \
	170	if (unlikely(((comp) & rtlpriv->dbg.global_debugcomponents) && \
	171	((level) <= rtlpriv->dbg.global_debuglevel))) {\
	172	printk(KERN_DEBUG "%s:%s():<%lx-%x> ", KBUILD_MODNAME, \
173	__func__, in_interrupt(), in_atomic()); \
174	printk fmt; \
175	} \
176	} while (0);
177
178	#define RTPRINT(rtlpriv, dbgtype, dbgflag, printstr) \
179	do { \
180	if (unlikely(rtlpriv->dbg.dbgp_type[dbgtype] & dbgflag)) { \
181	printk(KERN_DEBUG "%s: ", KBUILD_MODNAME); \
182	printk printstr; \
183	} \
184	} while (0);
185
186	#define RT_PRINT_DATA(rtlpriv, _comp, _level, _titlestring, _hexdata, \
187	_hexdatalen) \
188	do {\
189	if (unlikely(((_comp) & rtlpriv->dbg.global_debugcomponents) &&\
190	(_level <= rtlpriv->dbg.global_debuglevel))) { \
191	int __i; \
192	u8* ptr = (u8 *)_hexdata; \
193	printk(KERN_DEBUG "%s: ", KBUILD_MODNAME); \
194	printk("In process \"%s\" (pid %i):", current->comm,\
195	current->pid); \
196	printk(_titlestring); \
197	for (__i = 0; __i < (int)_hexdatalen; __i++) { \
198	printk("%02X%s", ptr[__i], (((__i + 1) % 4)\
199	== 0) ? " " : " ");\
200	if (((__i + 1) % 16) == 0) \
201	printk("\n"); \
202	} \
203	printk(KERN_DEBUG "\n"); \
204	} \
205	} while (0);
206
207	#define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x"
208	#define MAC_ARG(x) \
209	((u8 )(x))[0], ((u8 )(x))[1], ((u8 *)(x))[2],\
210	((u8 )(x))[3], ((u8 )(x))[4], ((u8 *)(x))[5]
211
212	void rtl_dbgp_flag_init(struct ieee80211_hw *hw);
213	#endif