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rt2x00: Add autowake support for USB hardware
[deliverable/linux.git] / drivers / net / wireless / rtlwifi / pci.c
CommitLineData
0c817338
LF		 1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "core.h"
31#include "wifi.h"
32#include "pci.h"
33#include "base.h"
34#include "ps.h"
c7cfe38e 35#include "efuse.h"
0c817338
LF		 36
37static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = {
38 INTEL_VENDOR_ID,
39 ATI_VENDOR_ID,
40 AMD_VENDOR_ID,
41 SIS_VENDOR_ID
42};
43
c7cfe38e
C		 44static const u8 ac_to_hwq[] = {
45 VO_QUEUE,
46 VI_QUEUE,
47 BE_QUEUE,
48 BK_QUEUE
49};
50
d3bb1429 51static u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw,
c7cfe38e
C		 52 struct sk_buff *skb)
53{
54 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
d3bb1429 55 __le16 fc = rtl_get_fc(skb);
c7cfe38e
C		 56 u8 queue_index = skb_get_queue_mapping(skb);
57
58 if (unlikely(ieee80211_is_beacon(fc)))
59 return BEACON_QUEUE;
60 if (ieee80211_is_mgmt(fc))
61 return MGNT_QUEUE;
62 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
63 if (ieee80211_is_nullfunc(fc))
64 return HIGH_QUEUE;
65
66 return ac_to_hwq[queue_index];
67}
68
0c817338
LF		 69/* Update PCI dependent default settings*/
70static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw)
71{
72 struct rtl_priv *rtlpriv = rtl_priv(hw);
73 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
74 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
75 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
76 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
c7cfe38e 77 u8 init_aspm;
0c817338
LF		 78
79 ppsc->reg_rfps_level = 0;
7ea47240 80 ppsc->support_aspm = 0;
0c817338
LF		 81
82 /*Update PCI ASPM setting */
83 ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm;
84 switch (rtlpci->const_pci_aspm) {
85 case 0:
86 /*No ASPM */
87 break;
88
89 case 1:
90 /*ASPM dynamically enabled/disable. */
91 ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM;
92 break;
93
94 case 2:
95 /*ASPM with Clock Req dynamically enabled/disable. */
96 ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM |
97 RT_RF_OFF_LEVL_CLK_REQ);
98 break;
99
100 case 3:
101 /*
102 * Always enable ASPM and Clock Req
103 * from initialization to halt.
104 * */
105 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM);
106 ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM |
107 RT_RF_OFF_LEVL_CLK_REQ);
108 break;
109
110 case 4:
111 /*
112 * Always enable ASPM without Clock Req
113 * from initialization to halt.
114 * */
115 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM |
116 RT_RF_OFF_LEVL_CLK_REQ);
117 ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM;
118 break;
119 }
120
121 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
122
123 /*Update Radio OFF setting */
124 switch (rtlpci->const_hwsw_rfoff_d3) {
125 case 1:
126 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
127 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
128 break;
129
130 case 2:
131 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
132 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
133 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
134 break;
135
136 case 3:
137 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3;
138 break;
139 }
140
141 /*Set HW definition to determine if it supports ASPM. */
142 switch (rtlpci->const_support_pciaspm) {
c7cfe38e
C		 143 case 0:{
144 /*Not support ASPM. */
145 bool support_aspm = false;
146 ppsc->support_aspm = support_aspm;
147 break;
148 }
149 case 1:{
150 /*Support ASPM. */
151 bool support_aspm = true;
152 bool support_backdoor = true;
153 ppsc->support_aspm = support_aspm;
154
155 /*if (priv->oem_id == RT_CID_TOSHIBA &&
156 !priv->ndis_adapter.amd_l1_patch)
157 support_backdoor = false; */
158
159 ppsc->support_backdoor = support_backdoor;
160
161 break;
162 }
0c817338
LF		 163 case 2:
164 /*ASPM value set by chipset. */
c7cfe38e
C		 165 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) {
166 bool support_aspm = true;
167 ppsc->support_aspm = support_aspm;
168 }
0c817338
LF		 169 break;
170 default:
171 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
172 ("switch case not process\n"));
173 break;
174 }
c7cfe38e
C		 175
176 /* toshiba aspm issue, toshiba will set aspm selfly
177 * so we should not set aspm in driver */
178 pci_read_config_byte(rtlpci->pdev, 0x80, &init_aspm);
179 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE &&
180 init_aspm == 0x43)
181 ppsc->support_aspm = false;
182}
183
0c817338
LF		 184static bool _rtl_pci_platform_switch_device_pci_aspm(
185 struct ieee80211_hw *hw,
186 u8 value)
187{
188 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
c7cfe38e
C		 189 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
190
191 if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE)
192 value |= 0x40;
0c817338 193
0c817338
LF		 194 pci_write_config_byte(rtlpci->pdev, 0x80, value);
195
32473284 196 return false;
0c817338
LF		 197}
198
199/*When we set 0x01 to enable clk request. Set 0x0 to disable clk req.*/
200static bool _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u8 value)
201{
202 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
c7cfe38e 203 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0c817338 204
0c817338 205 pci_write_config_byte(rtlpci->pdev, 0x81, value);
0c817338 206
c7cfe38e
C		 207 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
208 udelay(100);
209
32473284 210 return true;
0c817338
LF		 211}
212
213/*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/
214static void rtl_pci_disable_aspm(struct ieee80211_hw *hw)
215{
216 struct rtl_priv *rtlpriv = rtl_priv(hw);
217 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
218 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
219 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
220 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
221 u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
222 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
223 /*Retrieve original configuration settings. */
224 u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg;
225 u16 pcibridge_linkctrlreg = pcipriv->ndis_adapter.
226 pcibridge_linkctrlreg;
227 u16 aspmlevel = 0;
32473284 228 u8 tmp_u1b = 0;
0c817338 229
c7cfe38e
C		 230 if (!ppsc->support_aspm)
231 return;
232
0c817338
LF		 233 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
234 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
235 ("PCI(Bridge) UNKNOWN.\n"));
236
237 return;
238 }
239
240 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
241 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
242 _rtl_pci_switch_clk_req(hw, 0x0);
243 }
244
32473284
LF		 245 /*for promising device will in L0 state after an I/O. */
246 pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b);
0c817338
LF		 247
248 /*Set corresponding value. */
249 aspmlevel |= BIT(0) | BIT(1);
250 linkctrl_reg &= ~aspmlevel;
251 pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1));
252
253 _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg);
254 udelay(50);
255
256 /*4 Disable Pci Bridge ASPM */
257 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
258 pcicfg_addrport + (num4bytes << 2));
259 rtl_pci_raw_write_port_uchar(PCI_CONF_DATA, pcibridge_linkctrlreg);
260
261 udelay(50);
0c817338
LF		 262}
263
264/*
265 *Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for
266 *power saving We should follow the sequence to enable
267 *RTL8192SE first then enable Pci Bridge ASPM
268 *or the system will show bluescreen.
269 */
270static void rtl_pci_enable_aspm(struct ieee80211_hw *hw)
271{
272 struct rtl_priv *rtlpriv = rtl_priv(hw);
273 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
274 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
275 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
276 u8 pcibridge_busnum = pcipriv->ndis_adapter.pcibridge_busnum;
277 u8 pcibridge_devnum = pcipriv->ndis_adapter.pcibridge_devnum;
278 u8 pcibridge_funcnum = pcipriv->ndis_adapter.pcibridge_funcnum;
279 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
280 u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
281 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
282 u16 aspmlevel;
283 u8 u_pcibridge_aspmsetting;
284 u8 u_device_aspmsetting;
285
c7cfe38e
C		 286 if (!ppsc->support_aspm)
287 return;
288
0c817338
LF		 289 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
290 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
291 ("PCI(Bridge) UNKNOWN.\n"));
292 return;
293 }
294
295 /*4 Enable Pci Bridge ASPM */
296 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
297 pcicfg_addrport + (num4bytes << 2));
298
299 u_pcibridge_aspmsetting =
300 pcipriv->ndis_adapter.pcibridge_linkctrlreg |
301 rtlpci->const_hostpci_aspm_setting;
302
303 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
304 u_pcibridge_aspmsetting &= ~BIT(0);
305
306 rtl_pci_raw_write_port_uchar(PCI_CONF_DATA, u_pcibridge_aspmsetting);
307
308 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
309 ("PlatformEnableASPM():PciBridge busnumber[%x], "
310 "DevNumbe[%x], funcnumber[%x], Write reg[%x] = %x\n",
311 pcibridge_busnum, pcibridge_devnum, pcibridge_funcnum,
312 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10),
313 u_pcibridge_aspmsetting));
314
315 udelay(50);
316
317 /*Get ASPM level (with/without Clock Req) */
318 aspmlevel = rtlpci->const_devicepci_aspm_setting;
319 u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg;
320
321 /*_rtl_pci_platform_switch_device_pci_aspm(dev,*/
322 /*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */
323
324 u_device_aspmsetting |= aspmlevel;
325
326 _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting);
327
328 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
329 _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level &
330 RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0);
331 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
332 }
c7cfe38e 333 udelay(100);
0c817338
LF		 334}
335
336static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw)
337{
338 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
339 u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
340
341 bool status = false;
342 u8 offset_e0;
343 unsigned offset_e4;
344
345 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
346 pcicfg_addrport + 0xE0);
347 rtl_pci_raw_write_port_uchar(PCI_CONF_DATA, 0xA0);
348
349 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
350 pcicfg_addrport + 0xE0);
351 rtl_pci_raw_read_port_uchar(PCI_CONF_DATA, &offset_e0);
352
353 if (offset_e0 == 0xA0) {
354 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
355 pcicfg_addrport + 0xE4);
356 rtl_pci_raw_read_port_ulong(PCI_CONF_DATA, &offset_e4);
357 if (offset_e4 & BIT(23))
358 status = true;
359 }
360
361 return status;
362}
363
d3bb1429 364static void rtl_pci_get_linkcontrol_field(struct ieee80211_hw *hw)
0c817338
LF		 365{
366 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
367 u8 capabilityoffset = pcipriv->ndis_adapter.pcibridge_pciehdr_offset;
368 u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
369 u8 linkctrl_reg;
c7cfe38e 370 u8 num4bbytes;
0c817338 371
c7cfe38e 372 num4bbytes = (capabilityoffset + 0x10) / 4;
0c817338
LF		 373
374 /*Read Link Control Register */
375 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
c7cfe38e 376 pcicfg_addrport + (num4bbytes << 2));
0c817338
LF		 377 rtl_pci_raw_read_port_uchar(PCI_CONF_DATA, &linkctrl_reg);
378
379 pcipriv->ndis_adapter.pcibridge_linkctrlreg = linkctrl_reg;
380}
381
382static void rtl_pci_parse_configuration(struct pci_dev *pdev,
383 struct ieee80211_hw *hw)
384{
385 struct rtl_priv *rtlpriv = rtl_priv(hw);
386 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
387
388 u8 tmp;
389 int pos;
390 u8 linkctrl_reg;
391
392 /*Link Control Register */
393 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
394 pci_read_config_byte(pdev, pos + PCI_EXP_LNKCTL, &linkctrl_reg);
395 pcipriv->ndis_adapter.linkctrl_reg = linkctrl_reg;
396
397 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
398 ("Link Control Register =%x\n",
399 pcipriv->ndis_adapter.linkctrl_reg));
400
401 pci_read_config_byte(pdev, 0x98, &tmp);
402 tmp |= BIT(4);
403 pci_write_config_byte(pdev, 0x98, tmp);
404
405 tmp = 0x17;
406 pci_write_config_byte(pdev, 0x70f, tmp);
407}
408
c7cfe38e 409static void rtl_pci_init_aspm(struct ieee80211_hw *hw)
0c817338
LF		 410{
411 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
412
413 _rtl_pci_update_default_setting(hw);
414
415 if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) {
416 /*Always enable ASPM & Clock Req. */
417 rtl_pci_enable_aspm(hw);
418 RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM);
419 }
420
421}
422
0c817338
LF		 423static void _rtl_pci_io_handler_init(struct device *dev,
424 struct ieee80211_hw *hw)
425{
426 struct rtl_priv *rtlpriv = rtl_priv(hw);
427
428 rtlpriv->io.dev = dev;
429
430 rtlpriv->io.write8_async = pci_write8_async;
431 rtlpriv->io.write16_async = pci_write16_async;
432 rtlpriv->io.write32_async = pci_write32_async;
433
434 rtlpriv->io.read8_sync = pci_read8_sync;
435 rtlpriv->io.read16_sync = pci_read16_sync;
436 rtlpriv->io.read32_sync = pci_read32_sync;
437
438}
439
440static void _rtl_pci_io_handler_release(struct ieee80211_hw *hw)
441{
442}
443
c7cfe38e
C		 444static bool _rtl_update_earlymode_info(struct ieee80211_hw *hw,
445 struct sk_buff *skb, struct rtl_tcb_desc *tcb_desc, u8 tid)
446{
447 struct rtl_priv *rtlpriv = rtl_priv(hw);
448 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
449 u8 additionlen = FCS_LEN;
450 struct sk_buff *next_skb;
451
452 /* here open is 4, wep/tkip is 8, aes is 12*/
453 if (info->control.hw_key)
454 additionlen += info->control.hw_key->icv_len;
455
456 /* The most skb num is 6 */
457 tcb_desc->empkt_num = 0;
458 spin_lock_bh(&rtlpriv->locks.waitq_lock);
459 skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) {
460 struct ieee80211_tx_info *next_info;
461
462 next_info = IEEE80211_SKB_CB(next_skb);
463 if (next_info->flags & IEEE80211_TX_CTL_AMPDU) {
464 tcb_desc->empkt_len[tcb_desc->empkt_num] =
465 next_skb->len + additionlen;
466 tcb_desc->empkt_num++;
467 } else {
468 break;
469 }
470
471 if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid],
472 next_skb))
473 break;
474
475 if (tcb_desc->empkt_num >= 5)
476 break;
477 }
478 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
479
480 return true;
481}
482
483/* just for early mode now */
484static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw)
485{
486 struct rtl_priv *rtlpriv = rtl_priv(hw);
487 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
488 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
489 struct sk_buff *skb = NULL;
490 struct ieee80211_tx_info *info = NULL;
491 int tid; /* should be int */
492
493 if (!rtlpriv->rtlhal.earlymode_enable)
494 return;
495
496 /* we juse use em for BE/BK/VI/VO */
497 for (tid = 7; tid >= 0; tid--) {
498 u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(hw, tid)];
499 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
500 while (!mac->act_scanning &&
501 rtlpriv->psc.rfpwr_state == ERFON) {
502 struct rtl_tcb_desc tcb_desc;
503 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
504
505 spin_lock_bh(&rtlpriv->locks.waitq_lock);
506 if (!skb_queue_empty(&mac->skb_waitq[tid]) &&
507 (ring->entries - skb_queue_len(&ring->queue) > 5)) {
508 skb = skb_dequeue(&mac->skb_waitq[tid]);
509 } else {
510 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
511 break;
512 }
513 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
514
515 /* Some macaddr can't do early mode. like
516 * multicast/broadcast/no_qos data */
517 info = IEEE80211_SKB_CB(skb);
518 if (info->flags & IEEE80211_TX_CTL_AMPDU)
519 _rtl_update_earlymode_info(hw, skb,
520 &tcb_desc, tid);
521
c7cfe38e 522 rtlpriv->intf_ops->adapter_tx(hw, skb, &tcb_desc);
c7cfe38e
C		 523 }
524 }
525}
526
527
0c817338
LF		 528static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio)
529{
530 struct rtl_priv *rtlpriv = rtl_priv(hw);
531 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
532
533 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
534
535 while (skb_queue_len(&ring->queue)) {
536 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
537 struct sk_buff *skb;
538 struct ieee80211_tx_info *info;
c7cfe38e
C		 539 __le16 fc;
540 u8 tid;
0c817338
LF		 541
542 u8 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) entry, true,
543 HW_DESC_OWN);
544
545 /*
546 *beacon packet will only use the first
547 *descriptor defautly,and the own may not
548 *be cleared by the hardware
549 */
550 if (own)
551 return;
552 ring->idx = (ring->idx + 1) % ring->entries;
553
554 skb = __skb_dequeue(&ring->queue);
555 pci_unmap_single(rtlpci->pdev,
d3bb1429 556 rtlpriv->cfg->ops->
0c817338 557 get_desc((u8 *) entry, true,
d3bb1429 558 HW_DESC_TXBUFF_ADDR),
0c817338
LF		 559 skb->len, PCI_DMA_TODEVICE);
560
c7cfe38e
C		 561 /* remove early mode header */
562 if (rtlpriv->rtlhal.earlymode_enable)
563 skb_pull(skb, EM_HDR_LEN);
564
0c817338
LF		 565 RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE,
566 ("new ring->idx:%d, "
567 "free: skb_queue_len:%d, free: seq:%x\n",
568 ring->idx,
569 skb_queue_len(&ring->queue),
570 *(u16 *) (skb->data + 22)));
571
c7cfe38e
C		 572 if (prio == TXCMD_QUEUE) {
573 dev_kfree_skb(skb);
574 goto tx_status_ok;
575
576 }
577
578 /* for sw LPS, just after NULL skb send out, we can
579 * sure AP kown we are sleeped, our we should not let
580 * rf to sleep*/
581 fc = rtl_get_fc(skb);
582 if (ieee80211_is_nullfunc(fc)) {
583 if (ieee80211_has_pm(fc)) {
584 rtlpriv->mac80211.offchan_deley = true;
585 rtlpriv->psc.state_inap = 1;
586 } else {
587 rtlpriv->psc.state_inap = 0;
588 }
589 }
590
591 /* update tid tx pkt num */
592 tid = rtl_get_tid(skb);
593 if (tid <= 7)
594 rtlpriv->link_info.tidtx_inperiod[tid]++;
595
0c817338
LF		 596 info = IEEE80211_SKB_CB(skb);
597 ieee80211_tx_info_clear_status(info);
598
599 info->flags |= IEEE80211_TX_STAT_ACK;
600 /*info->status.rates[0].count = 1; */
601
602 ieee80211_tx_status_irqsafe(hw, skb);
603
604 if ((ring->entries - skb_queue_len(&ring->queue))
605 == 2) {
606
607 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
608 ("more desc left, wake"
609 "skb_queue@%d,ring->idx = %d,"
610 "skb_queue_len = 0x%d\n",
611 prio, ring->idx,
612 skb_queue_len(&ring->queue)));
613
614 ieee80211_wake_queue(hw,
615 skb_get_queue_mapping
616 (skb));
617 }
c7cfe38e 618tx_status_ok:
0c817338
LF		 619 skb = NULL;
620 }
621
622 if (((rtlpriv->link_info.num_rx_inperiod +
623 rtlpriv->link_info.num_tx_inperiod) > 8) ||
624 (rtlpriv->link_info.num_rx_inperiod > 2)) {
625 rtl_lps_leave(hw);
626 }
627}
628
629static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
630{
631 struct rtl_priv *rtlpriv = rtl_priv(hw);
632 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
633 int rx_queue_idx = RTL_PCI_RX_MPDU_QUEUE;
634
635 struct ieee80211_rx_status rx_status = { 0 };
636 unsigned int count = rtlpci->rxringcount;
637 u8 own;
638 u8 tmp_one;
639 u32 bufferaddress;
640 bool unicast = false;
641
642 struct rtl_stats stats = {
643 .signal = 0,
644 .noise = -98,
645 .rate = 0,
646 };
647
648 /*RX NORMAL PKT */
649 while (count--) {
650 /*rx descriptor */
651 struct rtl_rx_desc *pdesc = &rtlpci->rx_ring[rx_queue_idx].desc[
652 rtlpci->rx_ring[rx_queue_idx].idx];
653 /*rx pkt */
654 struct sk_buff *skb = rtlpci->rx_ring[rx_queue_idx].rx_buf[
655 rtlpci->rx_ring[rx_queue_idx].idx];
656
657 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
658 false, HW_DESC_OWN);
659
660 if (own) {
661 /*wait data to be filled by hardware */
662 return;
663 } else {
664 struct ieee80211_hdr *hdr;
17c9ac62 665 __le16 fc;
0c817338
LF		 666 struct sk_buff *new_skb = NULL;
667
668 rtlpriv->cfg->ops->query_rx_desc(hw, &stats,
669 &rx_status,
670 (u8 *) pdesc, skb);
671
672 pci_unmap_single(rtlpci->pdev,
673 *((dma_addr_t *) skb->cb),
674 rtlpci->rxbuffersize,
675 PCI_DMA_FROMDEVICE);
676
677 skb_put(skb, rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
678 false,
679 HW_DESC_RXPKT_LEN));
680 skb_reserve(skb,
681 stats.rx_drvinfo_size + stats.rx_bufshift);
682
683 /*
684 *NOTICE This can not be use for mac80211,
685 *this is done in mac80211 code,
686 *if you done here sec DHCP will fail
687 *skb_trim(skb, skb->len - 4);
688 */
689
c7cfe38e
C		 690 hdr = rtl_get_hdr(skb);
691 fc = rtl_get_fc(skb);
0c817338 692
c7cfe38e 693 if (!stats.crc || !stats.hwerror) {
0c817338
LF		 694 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status,
695 sizeof(rx_status));
696
c7cfe38e 697 if (is_broadcast_ether_addr(hdr->addr1)) {
0c817338 698 ;/*TODO*/
c7cfe38e
C		 699 } else if (is_multicast_ether_addr(hdr->addr1)) {
700 ;/*TODO*/
701 } else {
702 unicast = true;
703 rtlpriv->stats.rxbytesunicast +=
704 skb->len;
0c817338
LF		 705 }
706
707 rtl_is_special_data(hw, skb, false);
708
709 if (ieee80211_is_data(fc)) {
710 rtlpriv->cfg->ops->led_control(hw,
711 LED_CTL_RX);
712
713 if (unicast)
714 rtlpriv->link_info.
715 num_rx_inperiod++;
716 }
717
c7cfe38e
C		 718 /* for sw lps */
719 rtl_swlps_beacon(hw, (void *)skb->data,
720 skb->len);
721 rtl_recognize_peer(hw, (void *)skb->data,
722 skb->len);
723 if ((rtlpriv->mac80211.opmode ==
724 NL80211_IFTYPE_AP) &&
725 (rtlpriv->rtlhal.current_bandtype ==
726 BAND_ON_2_4G) &&
727 (ieee80211_is_beacon(fc) ||
728 ieee80211_is_probe_resp(fc))) {
0c817338 729 dev_kfree_skb_any(skb);
5c4bc1ce 730 } else {
c7cfe38e
C		 731 if (unlikely(!rtl_action_proc(hw, skb,
732 false))) {
733 dev_kfree_skb_any(skb);
734 } else {
735 struct sk_buff *uskb = NULL;
736 u8 *pdata;
737 uskb = dev_alloc_skb(skb->len
738 + 128);
739 memcpy(IEEE80211_SKB_RXCB(uskb),
740 &rx_status,
741 sizeof(rx_status));
742 pdata = (u8 *)skb_put(uskb,
743 skb->len);
744 memcpy(pdata, skb->data,
745 skb->len);
746 dev_kfree_skb_any(skb);
747
748 ieee80211_rx_irqsafe(hw, uskb);
bdc4bf65 749 }
5c4bc1ce 750 }
0c817338
LF		 751 } else {
752 dev_kfree_skb_any(skb);
753 }
754
755 if (((rtlpriv->link_info.num_rx_inperiod +
756 rtlpriv->link_info.num_tx_inperiod) > 8) ||
757 (rtlpriv->link_info.num_rx_inperiod > 2)) {
758 rtl_lps_leave(hw);
759 }
760
761 new_skb = dev_alloc_skb(rtlpci->rxbuffersize);
762 if (unlikely(!new_skb)) {
763 RT_TRACE(rtlpriv, (COMP_INTR | COMP_RECV),
c7cfe38e 764 DBG_DMESG,
0c817338
LF		 765 ("can't alloc skb for rx\n"));
766 goto done;
767 }
768 skb = new_skb;
769 /*skb->dev = dev; */
770
771 rtlpci->rx_ring[rx_queue_idx].rx_buf[rtlpci->
772 rx_ring
773 [rx_queue_idx].
774 idx] = skb;
775 *((dma_addr_t *) skb->cb) =
776 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
777 rtlpci->rxbuffersize,
778 PCI_DMA_FROMDEVICE);
779
780 }
781done:
d3bb1429 782 bufferaddress = (*((dma_addr_t *)skb->cb));
0c817338
LF		 783 tmp_one = 1;
784 rtlpriv->cfg->ops->set_desc((u8 *) pdesc, false,
785 HW_DESC_RXBUFF_ADDR,
786 (u8 *)&bufferaddress);
787 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false, HW_DESC_RXOWN,
788 (u8 *)&tmp_one);
789 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false,
790 HW_DESC_RXPKT_LEN,
791 (u8 *)&rtlpci->rxbuffersize);
792
793 if (rtlpci->rx_ring[rx_queue_idx].idx ==
794 rtlpci->rxringcount - 1)
795 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false,
796 HW_DESC_RXERO,
797 (u8 *)&tmp_one);
798
799 rtlpci->rx_ring[rx_queue_idx].idx =
800 (rtlpci->rx_ring[rx_queue_idx].idx + 1) %
801 rtlpci->rxringcount;
802 }
803
804}
805
0c817338
LF		 806static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id)
807{
808 struct ieee80211_hw *hw = dev_id;
809 struct rtl_priv *rtlpriv = rtl_priv(hw);
810 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
c7cfe38e 811 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0c817338
LF		 812 unsigned long flags;
813 u32 inta = 0;
814 u32 intb = 0;
815
816 if (rtlpci->irq_enabled == 0)
817 return IRQ_HANDLED;
818
819 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
820
821 /*read ISR: 4/8bytes */
822 rtlpriv->cfg->ops->interrupt_recognized(hw, &inta, &intb);
823
824 /*Shared IRQ or HW disappared */
825 if (!inta || inta == 0xffff)
826 goto done;
827
828 /*<1> beacon related */
829 if (inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK]) {
830 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
831 ("beacon ok interrupt!\n"));
832 }
833
834 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TBDER])) {
835 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
836 ("beacon err interrupt!\n"));
837 }
838
839 if (inta & rtlpriv->cfg->maps[RTL_IMR_BDOK]) {
840 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
841 ("beacon interrupt!\n"));
842 }
843
844 if (inta & rtlpriv->cfg->maps[RTL_IMR_BcnInt]) {
845 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
846 ("prepare beacon for interrupt!\n"));
847 tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet);
848 }
849
850 /*<3> Tx related */
851 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TXFOVW]))
852 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, ("IMR_TXFOVW!\n"));
853
854 if (inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) {
855 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
856 ("Manage ok interrupt!\n"));
857 _rtl_pci_tx_isr(hw, MGNT_QUEUE);
858 }
859
860 if (inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) {
861 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
862 ("HIGH_QUEUE ok interrupt!\n"));
863 _rtl_pci_tx_isr(hw, HIGH_QUEUE);
864 }
865
866 if (inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) {
867 rtlpriv->link_info.num_tx_inperiod++;
868
869 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
870 ("BK Tx OK interrupt!\n"));
871 _rtl_pci_tx_isr(hw, BK_QUEUE);
872 }
873
874 if (inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) {
875 rtlpriv->link_info.num_tx_inperiod++;
876
877 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
878 ("BE TX OK interrupt!\n"));
879 _rtl_pci_tx_isr(hw, BE_QUEUE);
880 }
881
882 if (inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) {
883 rtlpriv->link_info.num_tx_inperiod++;
884
885 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
886 ("VI TX OK interrupt!\n"));
887 _rtl_pci_tx_isr(hw, VI_QUEUE);
888 }
889
890 if (inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) {
891 rtlpriv->link_info.num_tx_inperiod++;
892
893 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
894 ("Vo TX OK interrupt!\n"));
895 _rtl_pci_tx_isr(hw, VO_QUEUE);
896 }
897
c7cfe38e
C		 898 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) {
899 if (inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) {
900 rtlpriv->link_info.num_tx_inperiod++;
901
902 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
903 ("CMD TX OK interrupt!\n"));
904 _rtl_pci_tx_isr(hw, TXCMD_QUEUE);
905 }
906 }
907
0c817338
LF		 908 /*<2> Rx related */
909 if (inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) {
910 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, ("Rx ok interrupt!\n"));
c7cfe38e 911 _rtl_pci_rx_interrupt(hw);
0c817338
LF		 912 }
913
914 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) {
915 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
916 ("rx descriptor unavailable!\n"));
c7cfe38e 917 _rtl_pci_rx_interrupt(hw);
0c817338
LF		 918 }
919
920 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) {
921 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, ("rx overflow !\n"));
c7cfe38e 922 _rtl_pci_rx_interrupt(hw);
0c817338
LF		 923 }
924
c7cfe38e
C		 925 if (rtlpriv->rtlhal.earlymode_enable)
926 tasklet_schedule(&rtlpriv->works.irq_tasklet);
927
0c817338
LF		 928 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
929 return IRQ_HANDLED;
930
931done:
932 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
933 return IRQ_HANDLED;
934}
935
936static void _rtl_pci_irq_tasklet(struct ieee80211_hw *hw)
937{
c7cfe38e 938 _rtl_pci_tx_chk_waitq(hw);
0c817338
LF		 939}
940
941static void _rtl_pci_prepare_bcn_tasklet(struct ieee80211_hw *hw)
942{
943 struct rtl_priv *rtlpriv = rtl_priv(hw);
944 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
945 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
c7cfe38e 946 struct rtl8192_tx_ring *ring = NULL;
0c817338
LF		 947 struct ieee80211_hdr *hdr = NULL;
948 struct ieee80211_tx_info *info = NULL;
949 struct sk_buff *pskb = NULL;
950 struct rtl_tx_desc *pdesc = NULL;
c7cfe38e 951 struct rtl_tcb_desc tcb_desc;
0c817338
LF		 952 u8 temp_one = 1;
953
c7cfe38e 954 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
0c817338
LF		 955 ring = &rtlpci->tx_ring[BEACON_QUEUE];
956 pskb = __skb_dequeue(&ring->queue);
957 if (pskb)
958 kfree_skb(pskb);
959
960 /*NB: the beacon data buffer must be 32-bit aligned. */
961 pskb = ieee80211_beacon_get(hw, mac->vif);
962 if (pskb == NULL)
963 return;
c7cfe38e 964 hdr = rtl_get_hdr(pskb);
0c817338 965 info = IEEE80211_SKB_CB(pskb);
0c817338
LF		 966 pdesc = &ring->desc[0];
967 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *) pdesc,
c7cfe38e 968 info, pskb, BEACON_QUEUE, &tcb_desc);
0c817338
LF		 969
970 __skb_queue_tail(&ring->queue, pskb);
971
972 rtlpriv->cfg->ops->set_desc((u8 *) pdesc, true, HW_DESC_OWN,
973 (u8 *)&temp_one);
974
975 return;
976}
977
978static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw)
979{
980 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
981 u8 i;
982
983 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
984 rtlpci->txringcount[i] = RT_TXDESC_NUM;
985
986 /*
987 *we just alloc 2 desc for beacon queue,
988 *because we just need first desc in hw beacon.
989 */
990 rtlpci->txringcount[BEACON_QUEUE] = 2;
991
992 /*
993 *BE queue need more descriptor for performance
994 *consideration or, No more tx desc will happen,
995 *and may cause mac80211 mem leakage.
996 */
997 rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE;
998
999 rtlpci->rxbuffersize = 9100; /*2048/1024; */
1000 rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT; /*64; */
1001}
1002
1003static void _rtl_pci_init_struct(struct ieee80211_hw *hw,
1004 struct pci_dev *pdev)
1005{
1006 struct rtl_priv *rtlpriv = rtl_priv(hw);
1007 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1008 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1009 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0c817338
LF		 1010
1011 rtlpci->up_first_time = true;
1012 rtlpci->being_init_adapter = false;
1013
1014 rtlhal->hw = hw;
1015 rtlpci->pdev = pdev;
1016
0c817338
LF		 1017 /*Tx/Rx related var */
1018 _rtl_pci_init_trx_var(hw);
1019
c7cfe38e 1020 /*IBSS*/ mac->beacon_interval = 100;
0c817338 1021
c7cfe38e
C		 1022 /*AMPDU*/
1023 mac->min_space_cfg = 0;
0c817338
LF		 1024 mac->max_mss_density = 0;
1025 /*set sane AMPDU defaults */
1026 mac->current_ampdu_density = 7;
1027 mac->current_ampdu_factor = 3;
1028
c7cfe38e
C		 1029 /*QOS*/
1030 rtlpci->acm_method = eAcmWay2_SW;
0c817338
LF		 1031
1032 /*task */
1033 tasklet_init(&rtlpriv->works.irq_tasklet,
1034 (void (*)(unsigned long))_rtl_pci_irq_tasklet,
1035 (unsigned long)hw);
1036 tasklet_init(&rtlpriv->works.irq_prepare_bcn_tasklet,
1037 (void (*)(unsigned long))_rtl_pci_prepare_bcn_tasklet,
1038 (unsigned long)hw);
1039}
1040
1041static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw,
1042 unsigned int prio, unsigned int entries)
1043{
1044 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1045 struct rtl_priv *rtlpriv = rtl_priv(hw);
1046 struct rtl_tx_desc *ring;
1047 dma_addr_t dma;
1048 u32 nextdescaddress;
1049 int i;
1050
1051 ring = pci_alloc_consistent(rtlpci->pdev,
1052 sizeof(*ring) * entries, &dma);
1053
1054 if (!ring || (unsigned long)ring & 0xFF) {
1055 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1056 ("Cannot allocate TX ring (prio = %d)\n", prio));
1057 return -ENOMEM;
1058 }
1059
1060 memset(ring, 0, sizeof(*ring) * entries);
1061 rtlpci->tx_ring[prio].desc = ring;
1062 rtlpci->tx_ring[prio].dma = dma;
1063 rtlpci->tx_ring[prio].idx = 0;
1064 rtlpci->tx_ring[prio].entries = entries;
1065 skb_queue_head_init(&rtlpci->tx_ring[prio].queue);
1066
1067 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1068 ("queue:%d, ring_addr:%p\n", prio, ring));
1069
1070 for (i = 0; i < entries; i++) {
d3bb1429 1071 nextdescaddress = (u32) dma +
c7cfe38e 1072 ((i + 11) % entries) *
d3bb1429 1073 sizeof(*ring);
0c817338
LF		 1074
1075 rtlpriv->cfg->ops->set_desc((u8 *)&(ring[i]),
1076 true, HW_DESC_TX_NEXTDESC_ADDR,
1077 (u8 *)&nextdescaddress);
1078 }
1079
1080 return 0;
1081}
1082
1083static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw)
1084{
1085 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1086 struct rtl_priv *rtlpriv = rtl_priv(hw);
1087 struct rtl_rx_desc *entry = NULL;
1088 int i, rx_queue_idx;
1089 u8 tmp_one = 1;
1090
1091 /*
1092 *rx_queue_idx 0:RX_MPDU_QUEUE
1093 *rx_queue_idx 1:RX_CMD_QUEUE
1094 */
1095 for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1096 rx_queue_idx++) {
1097 rtlpci->rx_ring[rx_queue_idx].desc =
1098 pci_alloc_consistent(rtlpci->pdev,
1099 sizeof(*rtlpci->rx_ring[rx_queue_idx].
1100 desc) * rtlpci->rxringcount,
1101 &rtlpci->rx_ring[rx_queue_idx].dma);
1102
1103 if (!rtlpci->rx_ring[rx_queue_idx].desc ||
1104 (unsigned long)rtlpci->rx_ring[rx_queue_idx].desc & 0xFF) {
1105 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1106 ("Cannot allocate RX ring\n"));
1107 return -ENOMEM;
1108 }
1109
1110 memset(rtlpci->rx_ring[rx_queue_idx].desc, 0,
1111 sizeof(*rtlpci->rx_ring[rx_queue_idx].desc) *
1112 rtlpci->rxringcount);
1113
1114 rtlpci->rx_ring[rx_queue_idx].idx = 0;
1115
1116 for (i = 0; i < rtlpci->rxringcount; i++) {
1117 struct sk_buff *skb =
1118 dev_alloc_skb(rtlpci->rxbuffersize);
1119 u32 bufferaddress;
0c817338
LF		 1120 if (!skb)
1121 return 0;
bdc4bf65 1122 entry = &rtlpci->rx_ring[rx_queue_idx].desc[i];
0c817338
LF		 1123
1124 /*skb->dev = dev; */
1125
1126 rtlpci->rx_ring[rx_queue_idx].rx_buf[i] = skb;
1127
1128 /*
1129 *just set skb->cb to mapping addr
1130 *for pci_unmap_single use
1131 */
1132 *((dma_addr_t *) skb->cb) =
1133 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
1134 rtlpci->rxbuffersize,
1135 PCI_DMA_FROMDEVICE);
1136
d3bb1429 1137 bufferaddress = (*((dma_addr_t *)skb->cb));
0c817338
LF		 1138 rtlpriv->cfg->ops->set_desc((u8 *)entry, false,
1139 HW_DESC_RXBUFF_ADDR,
1140 (u8 *)&bufferaddress);
1141 rtlpriv->cfg->ops->set_desc((u8 *)entry, false,
1142 HW_DESC_RXPKT_LEN,
1143 (u8 *)&rtlpci->
1144 rxbuffersize);
1145 rtlpriv->cfg->ops->set_desc((u8 *) entry, false,
1146 HW_DESC_RXOWN,
1147 (u8 *)&tmp_one);
1148 }
1149
1150 rtlpriv->cfg->ops->set_desc((u8 *) entry, false,
1151 HW_DESC_RXERO, (u8 *)&tmp_one);
1152 }
1153 return 0;
1154}
1155
1156static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw,
1157 unsigned int prio)
1158{
1159 struct rtl_priv *rtlpriv = rtl_priv(hw);
1160 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1161 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
1162
1163 while (skb_queue_len(&ring->queue)) {
1164 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
1165 struct sk_buff *skb = __skb_dequeue(&ring->queue);
1166
1167 pci_unmap_single(rtlpci->pdev,
d3bb1429 1168 rtlpriv->cfg->
0c817338 1169 ops->get_desc((u8 *) entry, true,
d3bb1429 1170 HW_DESC_TXBUFF_ADDR),
0c817338
LF		 1171 skb->len, PCI_DMA_TODEVICE);
1172 kfree_skb(skb);
1173 ring->idx = (ring->idx + 1) % ring->entries;
1174 }
1175
1176 pci_free_consistent(rtlpci->pdev,
1177 sizeof(*ring->desc) * ring->entries,
1178 ring->desc, ring->dma);
1179 ring->desc = NULL;
1180}
1181
1182static void _rtl_pci_free_rx_ring(struct rtl_pci *rtlpci)
1183{
1184 int i, rx_queue_idx;
1185
1186 /*rx_queue_idx 0:RX_MPDU_QUEUE */
1187 /*rx_queue_idx 1:RX_CMD_QUEUE */
1188 for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1189 rx_queue_idx++) {
1190 for (i = 0; i < rtlpci->rxringcount; i++) {
1191 struct sk_buff *skb =
1192 rtlpci->rx_ring[rx_queue_idx].rx_buf[i];
1193 if (!skb)
1194 continue;
1195
1196 pci_unmap_single(rtlpci->pdev,
1197 *((dma_addr_t *) skb->cb),
1198 rtlpci->rxbuffersize,
1199 PCI_DMA_FROMDEVICE);
1200 kfree_skb(skb);
1201 }
1202
1203 pci_free_consistent(rtlpci->pdev,
1204 sizeof(*rtlpci->rx_ring[rx_queue_idx].
1205 desc) * rtlpci->rxringcount,
1206 rtlpci->rx_ring[rx_queue_idx].desc,
1207 rtlpci->rx_ring[rx_queue_idx].dma);
1208 rtlpci->rx_ring[rx_queue_idx].desc = NULL;
1209 }
1210}
1211
1212static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw)
1213{
1214 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1215 int ret;
1216 int i;
1217
1218 ret = _rtl_pci_init_rx_ring(hw);
1219 if (ret)
1220 return ret;
1221
1222 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1223 ret = _rtl_pci_init_tx_ring(hw, i,
1224 rtlpci->txringcount[i]);
1225 if (ret)
1226 goto err_free_rings;
1227 }
1228
1229 return 0;
1230
1231err_free_rings:
1232 _rtl_pci_free_rx_ring(rtlpci);
1233
1234 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1235 if (rtlpci->tx_ring[i].desc)
1236 _rtl_pci_free_tx_ring(hw, i);
1237
1238 return 1;
1239}
1240
1241static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw)
1242{
1243 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1244 u32 i;
1245
1246 /*free rx rings */
1247 _rtl_pci_free_rx_ring(rtlpci);
1248
1249 /*free tx rings */
1250 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1251 _rtl_pci_free_tx_ring(hw, i);
1252
1253 return 0;
1254}
1255
1256int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw)
1257{
1258 struct rtl_priv *rtlpriv = rtl_priv(hw);
1259 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1260 int i, rx_queue_idx;
1261 unsigned long flags;
1262 u8 tmp_one = 1;
1263
1264 /*rx_queue_idx 0:RX_MPDU_QUEUE */
1265 /*rx_queue_idx 1:RX_CMD_QUEUE */
1266 for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1267 rx_queue_idx++) {
1268 /*
1269 *force the rx_ring[RX_MPDU_QUEUE/
1270 *RX_CMD_QUEUE].idx to the first one
1271 */
1272 if (rtlpci->rx_ring[rx_queue_idx].desc) {
1273 struct rtl_rx_desc *entry = NULL;
1274
1275 for (i = 0; i < rtlpci->rxringcount; i++) {
1276 entry = &rtlpci->rx_ring[rx_queue_idx].desc[i];
1277 rtlpriv->cfg->ops->set_desc((u8 *) entry,
1278 false,
1279 HW_DESC_RXOWN,
1280 (u8 *)&tmp_one);
1281 }
1282 rtlpci->rx_ring[rx_queue_idx].idx = 0;
1283 }
1284 }
1285
1286 /*
1287 *after reset, release previous pending packet,
1288 *and force the tx idx to the first one
1289 */
1290 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1291 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1292 if (rtlpci->tx_ring[i].desc) {
1293 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i];
1294
1295 while (skb_queue_len(&ring->queue)) {
1296 struct rtl_tx_desc *entry =
1297 &ring->desc[ring->idx];
1298 struct sk_buff *skb =
1299 __skb_dequeue(&ring->queue);
1300
1301 pci_unmap_single(rtlpci->pdev,
d3bb1429 1302 rtlpriv->cfg->ops->
0c817338
LF		 1303 get_desc((u8 *)
1304 entry,
1305 true,
d3bb1429 1306 HW_DESC_TXBUFF_ADDR),
0c817338
LF		 1307 skb->len, PCI_DMA_TODEVICE);
1308 kfree_skb(skb);
1309 ring->idx = (ring->idx + 1) % ring->entries;
1310 }
1311 ring->idx = 0;
1312 }
1313 }
1314
1315 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1316
1317 return 0;
1318}
1319
c7cfe38e
C		 1320static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw,
1321 struct sk_buff *skb)
0c817338 1322{
c7cfe38e
C		 1323 struct rtl_priv *rtlpriv = rtl_priv(hw);
1324 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1325 struct ieee80211_sta *sta = info->control.sta;
1326 struct rtl_sta_info *sta_entry = NULL;
1327 u8 tid = rtl_get_tid(skb);
1328
1329 if (!sta)
1330 return false;
1331 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1332
1333 if (!rtlpriv->rtlhal.earlymode_enable)
1334 return false;
1335 if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL)
1336 return false;
1337 if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE)
1338 return false;
1339 if (tid > 7)
1340 return false;
1341
1342 /* maybe every tid should be checked */
1343 if (!rtlpriv->link_info.higher_busytxtraffic[tid])
1344 return false;
1345
1346 spin_lock_bh(&rtlpriv->locks.waitq_lock);
1347 skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb);
1348 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
0c817338 1349
c7cfe38e 1350 return true;
0c817338
LF		 1351}
1352
d3bb1429 1353static int rtl_pci_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
c7cfe38e 1354 struct rtl_tcb_desc *ptcb_desc)
0c817338
LF		 1355{
1356 struct rtl_priv *rtlpriv = rtl_priv(hw);
c7cfe38e 1357 struct rtl_sta_info *sta_entry = NULL;
0c817338 1358 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
c7cfe38e 1359 struct ieee80211_sta *sta = info->control.sta;
0c817338
LF		 1360 struct rtl8192_tx_ring *ring;
1361 struct rtl_tx_desc *pdesc;
1362 u8 idx;
c7cfe38e 1363 u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb);
0c817338 1364 unsigned long flags;
c7cfe38e
C		 1365 struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
1366 __le16 fc = rtl_get_fc(skb);
0c817338
LF		 1367 u8 *pda_addr = hdr->addr1;
1368 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1369 /*ssn */
0c817338
LF		 1370 u8 tid = 0;
1371 u16 seq_number = 0;
1372 u8 own;
1373 u8 temp_one = 1;
1374
c7cfe38e
C		 1375 if (ieee80211_is_auth(fc)) {
1376 RT_TRACE(rtlpriv, COMP_SEND, DBG_DMESG, ("MAC80211_LINKING\n"));
1377 rtl_ips_nic_on(hw);
1378 }
1379
1380 if (rtlpriv->psc.sw_ps_enabled) {
1381 if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) &&
1382 !ieee80211_has_pm(fc))
1383 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1384 }
0c817338 1385
c7cfe38e 1386 rtl_action_proc(hw, skb, true);
0c817338
LF		 1387
1388 if (is_multicast_ether_addr(pda_addr))
1389 rtlpriv->stats.txbytesmulticast += skb->len;
1390 else if (is_broadcast_ether_addr(pda_addr))
1391 rtlpriv->stats.txbytesbroadcast += skb->len;
1392 else
1393 rtlpriv->stats.txbytesunicast += skb->len;
1394
1395 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
0c817338
LF		 1396 ring = &rtlpci->tx_ring[hw_queue];
1397 if (hw_queue != BEACON_QUEUE)
1398 idx = (ring->idx + skb_queue_len(&ring->queue)) %
1399 ring->entries;
1400 else
1401 idx = 0;
1402
1403 pdesc = &ring->desc[idx];
1404 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
1405 true, HW_DESC_OWN);
1406
1407 if ((own == 1) && (hw_queue != BEACON_QUEUE)) {
1408 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1409 ("No more TX desc@%d, ring->idx = %d,"
1410 "idx = %d, skb_queue_len = 0x%d\n",
1411 hw_queue, ring->idx, idx,
1412 skb_queue_len(&ring->queue)));
1413
1414 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1415 return skb->len;
1416 }
1417
0c817338 1418 if (ieee80211_is_data_qos(fc)) {
c7cfe38e
C		 1419 tid = rtl_get_tid(skb);
1420 if (sta) {
1421 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1422 seq_number = (le16_to_cpu(hdr->seq_ctrl) &
1423 IEEE80211_SCTL_SEQ) >> 4;
1424 seq_number += 1;
1425
1426 if (!ieee80211_has_morefrags(hdr->frame_control))
1427 sta_entry->tids[tid].seq_number = seq_number;
1428 }
0c817338
LF		 1429 }
1430
1431 if (ieee80211_is_data(fc))
1432 rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX);
1433
c7cfe38e
C		 1434 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
1435 info, skb, hw_queue, ptcb_desc);
0c817338
LF		 1436
1437 __skb_queue_tail(&ring->queue, skb);
1438
c7cfe38e 1439 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, true,
0c817338
LF		 1440 HW_DESC_OWN, (u8 *)&temp_one);
1441
0c817338
LF		 1442
1443 if ((ring->entries - skb_queue_len(&ring->queue)) < 2 &&
1444 hw_queue != BEACON_QUEUE) {
1445
1446 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
1447 ("less desc left, stop skb_queue@%d, "
1448 "ring->idx = %d,"
1449 "idx = %d, skb_queue_len = 0x%d\n",
1450 hw_queue, ring->idx, idx,
1451 skb_queue_len(&ring->queue)));
1452
1453 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
1454 }
1455
1456 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1457
1458 rtlpriv->cfg->ops->tx_polling(hw, hw_queue);
1459
1460 return 0;
1461}
1462
c7cfe38e
C		 1463static void rtl_pci_flush(struct ieee80211_hw *hw, bool drop)
1464{
1465 struct rtl_priv *rtlpriv = rtl_priv(hw);
1466 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1467 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1468 u16 i = 0;
1469 int queue_id;
1470 struct rtl8192_tx_ring *ring;
1471
1472 for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) {
1473 u32 queue_len;
1474 ring = &pcipriv->dev.tx_ring[queue_id];
1475 queue_len = skb_queue_len(&ring->queue);
1476 if (queue_len == 0 || queue_id == BEACON_QUEUE ||
1477 queue_id == TXCMD_QUEUE) {
1478 queue_id--;
1479 continue;
1480 } else {
1481 msleep(20);
1482 i++;
1483 }
1484
1485 /* we just wait 1s for all queues */
1486 if (rtlpriv->psc.rfpwr_state == ERFOFF ||
1487 is_hal_stop(rtlhal) || i >= 200)
1488 return;
1489 }
1490}
1491
d3bb1429 1492static void rtl_pci_deinit(struct ieee80211_hw *hw)
0c817338
LF		 1493{
1494 struct rtl_priv *rtlpriv = rtl_priv(hw);
1495 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1496
1497 _rtl_pci_deinit_trx_ring(hw);
1498
1499 synchronize_irq(rtlpci->pdev->irq);
1500 tasklet_kill(&rtlpriv->works.irq_tasklet);
1501
1502 flush_workqueue(rtlpriv->works.rtl_wq);
1503 destroy_workqueue(rtlpriv->works.rtl_wq);
1504
1505}
1506
d3bb1429 1507static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev)
0c817338
LF		 1508{
1509 struct rtl_priv *rtlpriv = rtl_priv(hw);
1510 int err;
1511
1512 _rtl_pci_init_struct(hw, pdev);
1513
1514 err = _rtl_pci_init_trx_ring(hw);
1515 if (err) {
1516 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1517 ("tx ring initialization failed"));
1518 return err;
1519 }
1520
1521 return 1;
1522}
1523
d3bb1429 1524static int rtl_pci_start(struct ieee80211_hw *hw)
0c817338
LF		 1525{
1526 struct rtl_priv *rtlpriv = rtl_priv(hw);
1527 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1528 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1529 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1530
1531 int err;
1532
1533 rtl_pci_reset_trx_ring(hw);
1534
1535 rtlpci->driver_is_goingto_unload = false;
1536 err = rtlpriv->cfg->ops->hw_init(hw);
1537 if (err) {
1538 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1539 ("Failed to config hardware!\n"));
1540 return err;
1541 }
1542
1543 rtlpriv->cfg->ops->enable_interrupt(hw);
1544 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("enable_interrupt OK\n"));
1545
1546 rtl_init_rx_config(hw);
1547
1548 /*should after adapter start and interrupt enable. */
1549 set_hal_start(rtlhal);
1550
1551 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1552
1553 rtlpci->up_first_time = false;
1554
1555 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("OK\n"));
1556 return 0;
1557}
1558
d3bb1429 1559static void rtl_pci_stop(struct ieee80211_hw *hw)
0c817338
LF		 1560{
1561 struct rtl_priv *rtlpriv = rtl_priv(hw);
1562 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1563 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1564 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1565 unsigned long flags;
1566 u8 RFInProgressTimeOut = 0;
1567
1568 /*
1569 *should before disable interrrupt&adapter
1570 *and will do it immediately.
1571 */
1572 set_hal_stop(rtlhal);
1573
1574 rtlpriv->cfg->ops->disable_interrupt(hw);
1575
1576 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1577 while (ppsc->rfchange_inprogress) {
1578 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1579 if (RFInProgressTimeOut > 100) {
1580 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1581 break;
1582 }
1583 mdelay(1);
1584 RFInProgressTimeOut++;
1585 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1586 }
1587 ppsc->rfchange_inprogress = true;
1588 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1589
1590 rtlpci->driver_is_goingto_unload = true;
1591 rtlpriv->cfg->ops->hw_disable(hw);
1592 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1593
1594 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1595 ppsc->rfchange_inprogress = false;
1596 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1597
1598 rtl_pci_enable_aspm(hw);
1599}
1600
1601static bool _rtl_pci_find_adapter(struct pci_dev *pdev,
1602 struct ieee80211_hw *hw)
1603{
1604 struct rtl_priv *rtlpriv = rtl_priv(hw);
1605 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1606 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1607 struct pci_dev *bridge_pdev = pdev->bus->self;
1608 u16 venderid;
1609 u16 deviceid;
c7cfe38e 1610 u8 revisionid;
0c817338
LF		 1611 u16 irqline;
1612 u8 tmp;
1613
1614 venderid = pdev->vendor;
1615 deviceid = pdev->device;
c7cfe38e 1616 pci_read_config_byte(pdev, 0x8, &revisionid);
0c817338
LF		 1617 pci_read_config_word(pdev, 0x3C, &irqline);
1618
1619 if (deviceid == RTL_PCI_8192_DID ||
1620 deviceid == RTL_PCI_0044_DID ||
1621 deviceid == RTL_PCI_0047_DID ||
1622 deviceid == RTL_PCI_8192SE_DID ||
1623 deviceid == RTL_PCI_8174_DID ||
1624 deviceid == RTL_PCI_8173_DID ||
1625 deviceid == RTL_PCI_8172_DID ||
1626 deviceid == RTL_PCI_8171_DID) {
c7cfe38e 1627 switch (revisionid) {
0c817338
LF		 1628 case RTL_PCI_REVISION_ID_8192PCIE:
1629 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1630 ("8192 PCI-E is found - "
1631 "vid/did=%x/%x\n", venderid, deviceid));
1632 rtlhal->hw_type = HARDWARE_TYPE_RTL8192E;
1633 break;
1634 case RTL_PCI_REVISION_ID_8192SE:
1635 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1636 ("8192SE is found - "
1637 "vid/did=%x/%x\n", venderid, deviceid));
1638 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1639 break;
1640 default:
1641 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1642 ("Err: Unknown device - "
1643 "vid/did=%x/%x\n", venderid, deviceid));
1644 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1645 break;
1646
1647 }
1648 } else if (deviceid == RTL_PCI_8192CET_DID ||
1649 deviceid == RTL_PCI_8192CE_DID ||
1650 deviceid == RTL_PCI_8191CE_DID ||
1651 deviceid == RTL_PCI_8188CE_DID) {
1652 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE;
1653 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1654 ("8192C PCI-E is found - "
1655 "vid/did=%x/%x\n", venderid, deviceid));
c7cfe38e
C		 1656 } else if (deviceid == RTL_PCI_8192DE_DID ||
1657 deviceid == RTL_PCI_8192DE_DID2) {
1658 rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE;
1659 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1660 ("8192D PCI-E is found - "
1661 "vid/did=%x/%x\n", venderid, deviceid));
0c817338
LF		 1662 } else {
1663 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1664 ("Err: Unknown device -"
1665 " vid/did=%x/%x\n", venderid, deviceid));
1666
1667 rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE;
1668 }
1669
c7cfe38e
C		 1670 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) {
1671 if (revisionid == 0 || revisionid == 1) {
1672 if (revisionid == 0) {
1673 RT_TRACE(rtlpriv, COMP_INIT,
1674 DBG_LOUD, ("Find 92DE MAC0.\n"));
1675 rtlhal->interfaceindex = 0;
1676 } else if (revisionid == 1) {
1677 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1678 ("Find 92DE MAC1.\n"));
1679 rtlhal->interfaceindex = 1;
1680 }
1681 } else {
1682 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1683 ("Unknown device - "
1684 "VendorID/DeviceID=%x/%x, Revision=%x\n",
1685 venderid, deviceid, revisionid));
1686 rtlhal->interfaceindex = 0;
1687 }
1688 }
0c817338
LF		 1689 /*find bus info */
1690 pcipriv->ndis_adapter.busnumber = pdev->bus->number;
1691 pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn);
1692 pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn);
1693
1694 /*find bridge info */
1695 pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor;
1696 for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) {
1697 if (bridge_pdev->vendor == pcibridge_vendors[tmp]) {
1698 pcipriv->ndis_adapter.pcibridge_vendor = tmp;
1699 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1700 ("Pci Bridge Vendor is found index: %d\n",
1701 tmp));
1702 break;
1703 }
1704 }
1705
1706 if (pcipriv->ndis_adapter.pcibridge_vendor !=
1707 PCI_BRIDGE_VENDOR_UNKNOWN) {
1708 pcipriv->ndis_adapter.pcibridge_busnum =
1709 bridge_pdev->bus->number;
1710 pcipriv->ndis_adapter.pcibridge_devnum =
1711 PCI_SLOT(bridge_pdev->devfn);
1712 pcipriv->ndis_adapter.pcibridge_funcnum =
1713 PCI_FUNC(bridge_pdev->devfn);
0c817338
LF		 1714 pcipriv->ndis_adapter.pcicfg_addrport =
1715 (pcipriv->ndis_adapter.pcibridge_busnum << 16) |
1716 (pcipriv->ndis_adapter.pcibridge_devnum << 11) |
1717 (pcipriv->ndis_adapter.pcibridge_funcnum << 8) | (1 << 31);
c7cfe38e
C		 1718 pcipriv->ndis_adapter.pcibridge_pciehdr_offset =
1719 pci_pcie_cap(bridge_pdev);
0c817338
LF		 1720 pcipriv->ndis_adapter.num4bytes =
1721 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10) / 4;
1722
1723 rtl_pci_get_linkcontrol_field(hw);
1724
1725 if (pcipriv->ndis_adapter.pcibridge_vendor ==
1726 PCI_BRIDGE_VENDOR_AMD) {
1727 pcipriv->ndis_adapter.amd_l1_patch =
1728 rtl_pci_get_amd_l1_patch(hw);
1729 }
1730 }
1731
1732 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1733 ("pcidev busnumber:devnumber:funcnumber:"
1734 "vendor:link_ctl %d:%d:%d:%x:%x\n",
1735 pcipriv->ndis_adapter.busnumber,
1736 pcipriv->ndis_adapter.devnumber,
1737 pcipriv->ndis_adapter.funcnumber,
1738 pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg));
1739
1740 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1741 ("pci_bridge busnumber:devnumber:funcnumber:vendor:"
1742 "pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n",
1743 pcipriv->ndis_adapter.pcibridge_busnum,
1744 pcipriv->ndis_adapter.pcibridge_devnum,
1745 pcipriv->ndis_adapter.pcibridge_funcnum,
1746 pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor],
1747 pcipriv->ndis_adapter.pcibridge_pciehdr_offset,
1748 pcipriv->ndis_adapter.pcibridge_linkctrlreg,
1749 pcipriv->ndis_adapter.amd_l1_patch));
1750
1751 rtl_pci_parse_configuration(pdev, hw);
1752
1753 return true;
1754}
1755
1756int __devinit rtl_pci_probe(struct pci_dev *pdev,
1757 const struct pci_device_id *id)
1758{
1759 struct ieee80211_hw *hw = NULL;
1760
1761 struct rtl_priv *rtlpriv = NULL;
1762 struct rtl_pci_priv *pcipriv = NULL;
1763 struct rtl_pci *rtlpci;
1764 unsigned long pmem_start, pmem_len, pmem_flags;
1765 int err;
1766
1767 err = pci_enable_device(pdev);
1768 if (err) {
1769 RT_ASSERT(false,
1770 ("%s : Cannot enable new PCI device\n",
1771 pci_name(pdev)));
1772 return err;
1773 }
1774
1775 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
1776 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
1777 RT_ASSERT(false, ("Unable to obtain 32bit DMA "
1778 "for consistent allocations\n"));
1779 pci_disable_device(pdev);
1780 return -ENOMEM;
1781 }
1782 }
1783
1784 pci_set_master(pdev);
1785
1786 hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) +
1787 sizeof(struct rtl_priv), &rtl_ops);
1788 if (!hw) {
1789 RT_ASSERT(false,
1790 ("%s : ieee80211 alloc failed\n", pci_name(pdev)));
1791 err = -ENOMEM;
1792 goto fail1;
1793 }
1794
1795 SET_IEEE80211_DEV(hw, &pdev->dev);
1796 pci_set_drvdata(pdev, hw);
1797
1798 rtlpriv = hw->priv;
1799 pcipriv = (void *)rtlpriv->priv;
1800 pcipriv->dev.pdev = pdev;
1801
c7cfe38e
C		 1802 /* init cfg & intf_ops */
1803 rtlpriv->rtlhal.interface = INTF_PCI;
1804 rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data);
1805 rtlpriv->intf_ops = &rtl_pci_ops;
1806
0c817338
LF		 1807 /*
1808 *init dbgp flags before all
1809 *other functions, because we will
1810 *use it in other funtions like
1811 *RT_TRACE/RT_PRINT/RTL_PRINT_DATA
1812 *you can not use these macro
1813 *before this
1814 */
1815 rtl_dbgp_flag_init(hw);
1816
1817 /* MEM map */
1818 err = pci_request_regions(pdev, KBUILD_MODNAME);
1819 if (err) {
1820 RT_ASSERT(false, ("Can't obtain PCI resources\n"));
1821 return err;
1822 }
1823
c7cfe38e
C		 1824 pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id);
1825 pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id);
1826 pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id);
0c817338
LF		 1827
1828 /*shared mem start */
1829 rtlpriv->io.pci_mem_start =
c7cfe38e
C		 1830 (unsigned long)pci_iomap(pdev,
1831 rtlpriv->cfg->bar_id, pmem_len);
0c817338
LF		 1832 if (rtlpriv->io.pci_mem_start == 0) {
1833 RT_ASSERT(false, ("Can't map PCI mem\n"));
1834 goto fail2;
1835 }
1836
1837 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1838 ("mem mapped space: start: 0x%08lx len:%08lx "
1839 "flags:%08lx, after map:0x%08lx\n",
1840 pmem_start, pmem_len, pmem_flags,
1841 rtlpriv->io.pci_mem_start));
1842
1843 /* Disable Clk Request */
1844 pci_write_config_byte(pdev, 0x81, 0);
1845 /* leave D3 mode */
1846 pci_write_config_byte(pdev, 0x44, 0);
1847 pci_write_config_byte(pdev, 0x04, 0x06);
1848 pci_write_config_byte(pdev, 0x04, 0x07);
1849
0c817338
LF		 1850 /* find adapter */
1851 _rtl_pci_find_adapter(pdev, hw);
1852
1853 /* Init IO handler */
1854 _rtl_pci_io_handler_init(&pdev->dev, hw);
1855
1856 /*like read eeprom and so on */
1857 rtlpriv->cfg->ops->read_eeprom_info(hw);
1858
1859 if (rtlpriv->cfg->ops->init_sw_vars(hw)) {
1860 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1861 ("Can't init_sw_vars.\n"));
1862 goto fail3;
1863 }
1864
1865 rtlpriv->cfg->ops->init_sw_leds(hw);
1866
1867 /*aspm */
1868 rtl_pci_init_aspm(hw);
1869
1870 /* Init mac80211 sw */
1871 err = rtl_init_core(hw);
1872 if (err) {
1873 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1874 ("Can't allocate sw for mac80211.\n"));
1875 goto fail3;
1876 }
1877
1878 /* Init PCI sw */
1879 err = !rtl_pci_init(hw, pdev);
1880 if (err) {
1881 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1882 ("Failed to init PCI.\n"));
1883 goto fail3;
1884 }
1885
1886 err = ieee80211_register_hw(hw);
1887 if (err) {
1888 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1889 ("Can't register mac80211 hw.\n"));
1890 goto fail3;
1891 } else {
1892 rtlpriv->mac80211.mac80211_registered = 1;
1893 }
1894
1895 err = sysfs_create_group(&pdev->dev.kobj, &rtl_attribute_group);
1896 if (err) {
1897 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1898 ("failed to create sysfs device attributes\n"));
1899 goto fail3;
1900 }
1901
1902 /*init rfkill */
1903 rtl_init_rfkill(hw);
1904
1905 rtlpci = rtl_pcidev(pcipriv);
1906 err = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
1907 IRQF_SHARED, KBUILD_MODNAME, hw);
1908 if (err) {
1909 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1910 ("%s: failed to register IRQ handler\n",
1911 wiphy_name(hw->wiphy)));
1912 goto fail3;
1913 } else {
1914 rtlpci->irq_alloc = 1;
1915 }
1916
1917 set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
1918 return 0;
1919
1920fail3:
1921 pci_set_drvdata(pdev, NULL);
1922 rtl_deinit_core(hw);
1923 _rtl_pci_io_handler_release(hw);
1924 ieee80211_free_hw(hw);
1925
1926 if (rtlpriv->io.pci_mem_start != 0)
62e63975 1927 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
0c817338
LF		 1928
1929fail2:
1930 pci_release_regions(pdev);
1931
1932fail1:
1933
1934 pci_disable_device(pdev);
1935
1936 return -ENODEV;
1937
1938}
1939EXPORT_SYMBOL(rtl_pci_probe);
1940
1941void rtl_pci_disconnect(struct pci_dev *pdev)
1942{
1943 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
1944 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1945 struct rtl_priv *rtlpriv = rtl_priv(hw);
1946 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
1947 struct rtl_mac *rtlmac = rtl_mac(rtlpriv);
1948
1949 clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
1950
1951 sysfs_remove_group(&pdev->dev.kobj, &rtl_attribute_group);
1952
1953 /*ieee80211_unregister_hw will call ops_stop */
1954 if (rtlmac->mac80211_registered == 1) {
1955 ieee80211_unregister_hw(hw);
1956 rtlmac->mac80211_registered = 0;
1957 } else {
1958 rtl_deinit_deferred_work(hw);
1959 rtlpriv->intf_ops->adapter_stop(hw);
1960 }
1961
1962 /*deinit rfkill */
1963 rtl_deinit_rfkill(hw);
1964
1965 rtl_pci_deinit(hw);
1966 rtl_deinit_core(hw);
0c817338
LF		 1967 _rtl_pci_io_handler_release(hw);
1968 rtlpriv->cfg->ops->deinit_sw_vars(hw);
1969
1970 if (rtlpci->irq_alloc) {
1971 free_irq(rtlpci->pdev->irq, hw);
1972 rtlpci->irq_alloc = 0;
1973 }
1974
1975 if (rtlpriv->io.pci_mem_start != 0) {
62e63975 1976 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
0c817338
LF		 1977 pci_release_regions(pdev);
1978 }
1979
1980 pci_disable_device(pdev);
c7cfe38e
C		 1981
1982 rtl_pci_disable_aspm(hw);
1983
0c817338
LF		 1984 pci_set_drvdata(pdev, NULL);
1985
1986 ieee80211_free_hw(hw);
1987}
1988EXPORT_SYMBOL(rtl_pci_disconnect);
1989
1990/***************************************
1991kernel pci power state define:
1992PCI_D0 ((pci_power_t __force) 0)
1993PCI_D1 ((pci_power_t __force) 1)
1994PCI_D2 ((pci_power_t __force) 2)
1995PCI_D3hot ((pci_power_t __force) 3)
1996PCI_D3cold ((pci_power_t __force) 4)
1997PCI_UNKNOWN ((pci_power_t __force) 5)
1998
1999This function is called when system
2000goes into suspend state mac80211 will
2001call rtl_mac_stop() from the mac80211
2002suspend function first, So there is
2003no need to call hw_disable here.
2004****************************************/
2005int rtl_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2006{
c7cfe38e
C		 2007 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2008 struct rtl_priv *rtlpriv = rtl_priv(hw);
2009
2010 rtlpriv->cfg->ops->hw_suspend(hw);
2011 rtl_deinit_rfkill(hw);
2012
0c817338
LF		 2013 pci_save_state(pdev);
2014 pci_disable_device(pdev);
2015 pci_set_power_state(pdev, PCI_D3hot);
0c817338
LF		 2016 return 0;
2017}
2018EXPORT_SYMBOL(rtl_pci_suspend);
2019
2020int rtl_pci_resume(struct pci_dev *pdev)
2021{
2022 int ret;
c7cfe38e
C		 2023 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2024 struct rtl_priv *rtlpriv = rtl_priv(hw);
0c817338
LF		 2025
2026 pci_set_power_state(pdev, PCI_D0);
2027 ret = pci_enable_device(pdev);
2028 if (ret) {
2029 RT_ASSERT(false, ("ERR: <======\n"));
2030 return ret;
2031 }
2032
2033 pci_restore_state(pdev);
2034
c7cfe38e
C		 2035 rtlpriv->cfg->ops->hw_resume(hw);
2036 rtl_init_rfkill(hw);
0c817338
LF		 2037 return 0;
2038}
2039EXPORT_SYMBOL(rtl_pci_resume);
2040
2041struct rtl_intf_ops rtl_pci_ops = {
c7cfe38e 2042 .read_efuse_byte = read_efuse_byte,
0c817338
LF		 2043 .adapter_start = rtl_pci_start,
2044 .adapter_stop = rtl_pci_stop,
2045 .adapter_tx = rtl_pci_tx,
c7cfe38e 2046 .flush = rtl_pci_flush,
0c817338 2047 .reset_trx_ring = rtl_pci_reset_trx_ring,
c7cfe38e 2048 .waitq_insert = rtl_pci_tx_chk_waitq_insert,
0c817338
LF		 2049
2050 .disable_aspm = rtl_pci_disable_aspm,
2051 .enable_aspm = rtl_pci_enable_aspm,
2052};
Linux kernel - Deliverables
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