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b43: N-PHY: implement spurious tone avoidance
[deliverable/linux.git] / drivers / net / wireless / rtlwifi / pci.c
CommitLineData
0c817338
LF		 1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
ee40fa06 30#include <linux/export.h>
0c817338
LF		 31#include "core.h"
32#include "wifi.h"
33#include "pci.h"
34#include "base.h"
35#include "ps.h"
c7cfe38e 36#include "efuse.h"
0c817338
LF		 37
38static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = {
f01dce94
JM		 39 PCI_VENDOR_ID_INTEL,
40 PCI_VENDOR_ID_ATI,
41 PCI_VENDOR_ID_AMD,
42 PCI_VENDOR_ID_SI
0c817338
LF		 43};
44
c7cfe38e
C		 45static const u8 ac_to_hwq[] = {
46 VO_QUEUE,
47 VI_QUEUE,
48 BE_QUEUE,
49 BK_QUEUE
50};
51
d3bb1429 52static u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw,
c7cfe38e
C		 53 struct sk_buff *skb)
54{
55 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
d3bb1429 56 __le16 fc = rtl_get_fc(skb);
c7cfe38e
C		 57 u8 queue_index = skb_get_queue_mapping(skb);
58
59 if (unlikely(ieee80211_is_beacon(fc)))
60 return BEACON_QUEUE;
61 if (ieee80211_is_mgmt(fc))
62 return MGNT_QUEUE;
63 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
64 if (ieee80211_is_nullfunc(fc))
65 return HIGH_QUEUE;
66
67 return ac_to_hwq[queue_index];
68}
69
0c817338
LF		 70/* Update PCI dependent default settings*/
71static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw)
72{
73 struct rtl_priv *rtlpriv = rtl_priv(hw);
74 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
75 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
76 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
77 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
c7cfe38e 78 u8 init_aspm;
0c817338
LF		 79
80 ppsc->reg_rfps_level = 0;
7ea47240 81 ppsc->support_aspm = 0;
0c817338
LF		 82
83 /*Update PCI ASPM setting */
84 ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm;
85 switch (rtlpci->const_pci_aspm) {
86 case 0:
87 /*No ASPM */
88 break;
89
90 case 1:
91 /*ASPM dynamically enabled/disable. */
92 ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM;
93 break;
94
95 case 2:
96 /*ASPM with Clock Req dynamically enabled/disable. */
97 ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM |
98 RT_RF_OFF_LEVL_CLK_REQ);
99 break;
100
101 case 3:
102 /*
103 * Always enable ASPM and Clock Req
104 * from initialization to halt.
105 * */
106 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM);
107 ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM |
108 RT_RF_OFF_LEVL_CLK_REQ);
109 break;
110
111 case 4:
112 /*
113 * Always enable ASPM without Clock Req
114 * from initialization to halt.
115 * */
116 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM |
117 RT_RF_OFF_LEVL_CLK_REQ);
118 ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM;
119 break;
120 }
121
122 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
123
124 /*Update Radio OFF setting */
125 switch (rtlpci->const_hwsw_rfoff_d3) {
126 case 1:
127 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
128 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
129 break;
130
131 case 2:
132 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
133 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
134 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
135 break;
136
137 case 3:
138 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3;
139 break;
140 }
141
142 /*Set HW definition to determine if it supports ASPM. */
143 switch (rtlpci->const_support_pciaspm) {
c7cfe38e
C		 144 case 0:{
145 /*Not support ASPM. */
146 bool support_aspm = false;
147 ppsc->support_aspm = support_aspm;
148 break;
149 }
150 case 1:{
151 /*Support ASPM. */
152 bool support_aspm = true;
153 bool support_backdoor = true;
154 ppsc->support_aspm = support_aspm;
155
156 /*if (priv->oem_id == RT_CID_TOSHIBA &&
157 !priv->ndis_adapter.amd_l1_patch)
158 support_backdoor = false; */
159
160 ppsc->support_backdoor = support_backdoor;
161
162 break;
163 }
0c817338
LF		 164 case 2:
165 /*ASPM value set by chipset. */
c7cfe38e
C		 166 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) {
167 bool support_aspm = true;
168 ppsc->support_aspm = support_aspm;
169 }
0c817338
LF		 170 break;
171 default:
172 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
173 ("switch case not process\n"));
174 break;
175 }
c7cfe38e
C		 176
177 /* toshiba aspm issue, toshiba will set aspm selfly
178 * so we should not set aspm in driver */
179 pci_read_config_byte(rtlpci->pdev, 0x80, &init_aspm);
180 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE &&
181 init_aspm == 0x43)
182 ppsc->support_aspm = false;
183}
184
0c817338
LF		 185static bool _rtl_pci_platform_switch_device_pci_aspm(
186 struct ieee80211_hw *hw,
187 u8 value)
188{
189 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
c7cfe38e
C		 190 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
191
192 if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE)
193 value |= 0x40;
0c817338 194
0c817338
LF		 195 pci_write_config_byte(rtlpci->pdev, 0x80, value);
196
32473284 197 return false;
0c817338
LF		 198}
199
200/*When we set 0x01 to enable clk request. Set 0x0 to disable clk req.*/
201static bool _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u8 value)
202{
203 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
c7cfe38e 204 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0c817338 205
0c817338 206 pci_write_config_byte(rtlpci->pdev, 0x81, value);
0c817338 207
c7cfe38e
C		 208 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
209 udelay(100);
210
32473284 211 return true;
0c817338
LF		 212}
213
214/*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/
215static void rtl_pci_disable_aspm(struct ieee80211_hw *hw)
216{
217 struct rtl_priv *rtlpriv = rtl_priv(hw);
218 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
219 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
220 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
221 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
0c817338
LF		 222 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
223 /*Retrieve original configuration settings. */
224 u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg;
225 u16 pcibridge_linkctrlreg = pcipriv->ndis_adapter.
226 pcibridge_linkctrlreg;
227 u16 aspmlevel = 0;
32473284 228 u8 tmp_u1b = 0;
0c817338 229
c7cfe38e
C		 230 if (!ppsc->support_aspm)
231 return;
232
0c817338
LF		 233 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
234 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
235 ("PCI(Bridge) UNKNOWN.\n"));
236
237 return;
238 }
239
240 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
241 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
242 _rtl_pci_switch_clk_req(hw, 0x0);
243 }
244
32473284
LF		 245 /*for promising device will in L0 state after an I/O. */
246 pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b);
0c817338
LF		 247
248 /*Set corresponding value. */
249 aspmlevel |= BIT(0) | BIT(1);
250 linkctrl_reg &= ~aspmlevel;
251 pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1));
252
253 _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg);
254 udelay(50);
255
256 /*4 Disable Pci Bridge ASPM */
886e14b6
LF		 257 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
258 pcibridge_linkctrlreg);
0c817338
LF		 259
260 udelay(50);
0c817338
LF		 261}
262
263/*
264 *Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for
265 *power saving We should follow the sequence to enable
266 *RTL8192SE first then enable Pci Bridge ASPM
267 *or the system will show bluescreen.
268 */
269static void rtl_pci_enable_aspm(struct ieee80211_hw *hw)
270{
271 struct rtl_priv *rtlpriv = rtl_priv(hw);
272 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
273 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
274 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
275 u8 pcibridge_busnum = pcipriv->ndis_adapter.pcibridge_busnum;
276 u8 pcibridge_devnum = pcipriv->ndis_adapter.pcibridge_devnum;
277 u8 pcibridge_funcnum = pcipriv->ndis_adapter.pcibridge_funcnum;
278 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
0c817338
LF		 279 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
280 u16 aspmlevel;
281 u8 u_pcibridge_aspmsetting;
282 u8 u_device_aspmsetting;
283
c7cfe38e
C		 284 if (!ppsc->support_aspm)
285 return;
286
0c817338
LF		 287 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
288 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
289 ("PCI(Bridge) UNKNOWN.\n"));
290 return;
291 }
292
293 /*4 Enable Pci Bridge ASPM */
0c817338
LF		 294
295 u_pcibridge_aspmsetting =
296 pcipriv->ndis_adapter.pcibridge_linkctrlreg |
297 rtlpci->const_hostpci_aspm_setting;
298
299 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
300 u_pcibridge_aspmsetting &= ~BIT(0);
301
886e14b6
LF		 302 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
303 u_pcibridge_aspmsetting);
0c817338
LF		 304
305 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
306 ("PlatformEnableASPM():PciBridge busnumber[%x], "
307 "DevNumbe[%x], funcnumber[%x], Write reg[%x] = %x\n",
308 pcibridge_busnum, pcibridge_devnum, pcibridge_funcnum,
309 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10),
310 u_pcibridge_aspmsetting));
311
312 udelay(50);
313
314 /*Get ASPM level (with/without Clock Req) */
315 aspmlevel = rtlpci->const_devicepci_aspm_setting;
316 u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg;
317
318 /*_rtl_pci_platform_switch_device_pci_aspm(dev,*/
319 /*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */
320
321 u_device_aspmsetting |= aspmlevel;
322
323 _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting);
324
325 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
326 _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level &
327 RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0);
328 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
329 }
c7cfe38e 330 udelay(100);
0c817338
LF		 331}
332
333static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw)
334{
886e14b6 335 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
0c817338
LF		 336
337 bool status = false;
338 u8 offset_e0;
339 unsigned offset_e4;
340
886e14b6 341 pci_write_config_byte(rtlpci->pdev, 0xe0, 0xa0);
0c817338 342
886e14b6 343 pci_read_config_byte(rtlpci->pdev, 0xe0, &offset_e0);
0c817338
LF		 344
345 if (offset_e0 == 0xA0) {
886e14b6 346 pci_read_config_dword(rtlpci->pdev, 0xe4, &offset_e4);
0c817338
LF		 347 if (offset_e4 & BIT(23))
348 status = true;
349 }
350
351 return status;
352}
353
d3bb1429 354static void rtl_pci_get_linkcontrol_field(struct ieee80211_hw *hw)
0c817338
LF		 355{
356 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
886e14b6 357 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
0c817338 358 u8 capabilityoffset = pcipriv->ndis_adapter.pcibridge_pciehdr_offset;
0c817338 359 u8 linkctrl_reg;
c7cfe38e 360 u8 num4bbytes;
0c817338 361
c7cfe38e 362 num4bbytes = (capabilityoffset + 0x10) / 4;
0c817338
LF		 363
364 /*Read Link Control Register */
886e14b6 365 pci_read_config_byte(rtlpci->pdev, (num4bbytes << 2), &linkctrl_reg);
0c817338
LF		 366
367 pcipriv->ndis_adapter.pcibridge_linkctrlreg = linkctrl_reg;
368}
369
370static void rtl_pci_parse_configuration(struct pci_dev *pdev,
371 struct ieee80211_hw *hw)
372{
373 struct rtl_priv *rtlpriv = rtl_priv(hw);
374 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
375
376 u8 tmp;
377 int pos;
378 u8 linkctrl_reg;
379
380 /*Link Control Register */
6a4ecc29 381 pos = pci_pcie_cap(pdev);
0c817338
LF		 382 pci_read_config_byte(pdev, pos + PCI_EXP_LNKCTL, &linkctrl_reg);
383 pcipriv->ndis_adapter.linkctrl_reg = linkctrl_reg;
384
385 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
386 ("Link Control Register =%x\n",
387 pcipriv->ndis_adapter.linkctrl_reg));
388
389 pci_read_config_byte(pdev, 0x98, &tmp);
390 tmp |= BIT(4);
391 pci_write_config_byte(pdev, 0x98, tmp);
392
393 tmp = 0x17;
394 pci_write_config_byte(pdev, 0x70f, tmp);
395}
396
c7cfe38e 397static void rtl_pci_init_aspm(struct ieee80211_hw *hw)
0c817338
LF		 398{
399 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
400
401 _rtl_pci_update_default_setting(hw);
402
403 if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) {
404 /*Always enable ASPM & Clock Req. */
405 rtl_pci_enable_aspm(hw);
406 RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM);
407 }
408
409}
410
0c817338
LF		 411static void _rtl_pci_io_handler_init(struct device *dev,
412 struct ieee80211_hw *hw)
413{
414 struct rtl_priv *rtlpriv = rtl_priv(hw);
415
416 rtlpriv->io.dev = dev;
417
418 rtlpriv->io.write8_async = pci_write8_async;
419 rtlpriv->io.write16_async = pci_write16_async;
420 rtlpriv->io.write32_async = pci_write32_async;
421
422 rtlpriv->io.read8_sync = pci_read8_sync;
423 rtlpriv->io.read16_sync = pci_read16_sync;
424 rtlpriv->io.read32_sync = pci_read32_sync;
425
426}
427
428static void _rtl_pci_io_handler_release(struct ieee80211_hw *hw)
429{
430}
431
c7cfe38e
C		 432static bool _rtl_update_earlymode_info(struct ieee80211_hw *hw,
433 struct sk_buff *skb, struct rtl_tcb_desc *tcb_desc, u8 tid)
434{
435 struct rtl_priv *rtlpriv = rtl_priv(hw);
436 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
437 u8 additionlen = FCS_LEN;
438 struct sk_buff *next_skb;
439
440 /* here open is 4, wep/tkip is 8, aes is 12*/
441 if (info->control.hw_key)
442 additionlen += info->control.hw_key->icv_len;
443
444 /* The most skb num is 6 */
445 tcb_desc->empkt_num = 0;
446 spin_lock_bh(&rtlpriv->locks.waitq_lock);
447 skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) {
448 struct ieee80211_tx_info *next_info;
449
450 next_info = IEEE80211_SKB_CB(next_skb);
451 if (next_info->flags & IEEE80211_TX_CTL_AMPDU) {
452 tcb_desc->empkt_len[tcb_desc->empkt_num] =
453 next_skb->len + additionlen;
454 tcb_desc->empkt_num++;
455 } else {
456 break;
457 }
458
459 if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid],
460 next_skb))
461 break;
462
463 if (tcb_desc->empkt_num >= 5)
464 break;
465 }
466 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
467
468 return true;
469}
470
471/* just for early mode now */
472static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw)
473{
474 struct rtl_priv *rtlpriv = rtl_priv(hw);
475 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
476 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
477 struct sk_buff *skb = NULL;
478 struct ieee80211_tx_info *info = NULL;
fb914ebf 479 int tid;
c7cfe38e
C		 480
481 if (!rtlpriv->rtlhal.earlymode_enable)
482 return;
483
484 /* we juse use em for BE/BK/VI/VO */
485 for (tid = 7; tid >= 0; tid--) {
486 u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(hw, tid)];
487 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
488 while (!mac->act_scanning &&
489 rtlpriv->psc.rfpwr_state == ERFON) {
490 struct rtl_tcb_desc tcb_desc;
491 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
492
493 spin_lock_bh(&rtlpriv->locks.waitq_lock);
494 if (!skb_queue_empty(&mac->skb_waitq[tid]) &&
495 (ring->entries - skb_queue_len(&ring->queue) > 5)) {
496 skb = skb_dequeue(&mac->skb_waitq[tid]);
497 } else {
498 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
499 break;
500 }
501 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
502
503 /* Some macaddr can't do early mode. like
504 * multicast/broadcast/no_qos data */
505 info = IEEE80211_SKB_CB(skb);
506 if (info->flags & IEEE80211_TX_CTL_AMPDU)
507 _rtl_update_earlymode_info(hw, skb,
508 &tcb_desc, tid);
509
c7cfe38e 510 rtlpriv->intf_ops->adapter_tx(hw, skb, &tcb_desc);
c7cfe38e
C		 511 }
512 }
513}
514
515
0c817338
LF		 516static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio)
517{
518 struct rtl_priv *rtlpriv = rtl_priv(hw);
519 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
520
521 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
522
523 while (skb_queue_len(&ring->queue)) {
524 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
525 struct sk_buff *skb;
526 struct ieee80211_tx_info *info;
c7cfe38e
C		 527 __le16 fc;
528 u8 tid;
0c817338
LF		 529
530 u8 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) entry, true,
531 HW_DESC_OWN);
532
533 /*
534 *beacon packet will only use the first
535 *descriptor defautly,and the own may not
536 *be cleared by the hardware
537 */
538 if (own)
539 return;
540 ring->idx = (ring->idx + 1) % ring->entries;
541
542 skb = __skb_dequeue(&ring->queue);
543 pci_unmap_single(rtlpci->pdev,
d3bb1429 544 rtlpriv->cfg->ops->
0c817338 545 get_desc((u8 *) entry, true,
d3bb1429 546 HW_DESC_TXBUFF_ADDR),
0c817338
LF		 547 skb->len, PCI_DMA_TODEVICE);
548
c7cfe38e
C		 549 /* remove early mode header */
550 if (rtlpriv->rtlhal.earlymode_enable)
551 skb_pull(skb, EM_HDR_LEN);
552
0c817338
LF		 553 RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE,
554 ("new ring->idx:%d, "
555 "free: skb_queue_len:%d, free: seq:%x\n",
556 ring->idx,
557 skb_queue_len(&ring->queue),
558 *(u16 *) (skb->data + 22)));
559
c7cfe38e
C		 560 if (prio == TXCMD_QUEUE) {
561 dev_kfree_skb(skb);
562 goto tx_status_ok;
563
564 }
565
566 /* for sw LPS, just after NULL skb send out, we can
567 * sure AP kown we are sleeped, our we should not let
568 * rf to sleep*/
569 fc = rtl_get_fc(skb);
570 if (ieee80211_is_nullfunc(fc)) {
571 if (ieee80211_has_pm(fc)) {
9c050440 572 rtlpriv->mac80211.offchan_delay = true;
c7cfe38e
C		 573 rtlpriv->psc.state_inap = 1;
574 } else {
575 rtlpriv->psc.state_inap = 0;
576 }
577 }
578
579 /* update tid tx pkt num */
580 tid = rtl_get_tid(skb);
581 if (tid <= 7)
582 rtlpriv->link_info.tidtx_inperiod[tid]++;
583
0c817338
LF		 584 info = IEEE80211_SKB_CB(skb);
585 ieee80211_tx_info_clear_status(info);
586
587 info->flags |= IEEE80211_TX_STAT_ACK;
588 /*info->status.rates[0].count = 1; */
589
590 ieee80211_tx_status_irqsafe(hw, skb);
591
592 if ((ring->entries - skb_queue_len(&ring->queue))
593 == 2) {
594
595 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
596 ("more desc left, wake"
597 "skb_queue@%d,ring->idx = %d,"
598 "skb_queue_len = 0x%d\n",
599 prio, ring->idx,
600 skb_queue_len(&ring->queue)));
601
602 ieee80211_wake_queue(hw,
603 skb_get_queue_mapping
604 (skb));
605 }
c7cfe38e 606tx_status_ok:
0c817338
LF		 607 skb = NULL;
608 }
609
610 if (((rtlpriv->link_info.num_rx_inperiod +
611 rtlpriv->link_info.num_tx_inperiod) > 8) ||
612 (rtlpriv->link_info.num_rx_inperiod > 2)) {
67fc6052 613 tasklet_schedule(&rtlpriv->works.ips_leave_tasklet);
0c817338
LF		 614 }
615}
616
fd854772
MM		 617static void _rtl_receive_one(struct ieee80211_hw *hw, struct sk_buff *skb,
618 struct ieee80211_rx_status rx_status)
619{
620 struct rtl_priv *rtlpriv = rtl_priv(hw);
621 struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
622 __le16 fc = rtl_get_fc(skb);
623 bool unicast = false;
624 struct sk_buff *uskb = NULL;
625 u8 *pdata;
626
627
628 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
629
630 if (is_broadcast_ether_addr(hdr->addr1)) {
631 ;/*TODO*/
632 } else if (is_multicast_ether_addr(hdr->addr1)) {
633 ;/*TODO*/
634 } else {
635 unicast = true;
636 rtlpriv->stats.rxbytesunicast += skb->len;
637 }
638
639 rtl_is_special_data(hw, skb, false);
640
641 if (ieee80211_is_data(fc)) {
642 rtlpriv->cfg->ops->led_control(hw, LED_CTL_RX);
643
644 if (unicast)
645 rtlpriv->link_info.num_rx_inperiod++;
646 }
647
648 /* for sw lps */
649 rtl_swlps_beacon(hw, (void *)skb->data, skb->len);
650 rtl_recognize_peer(hw, (void *)skb->data, skb->len);
651 if ((rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP) &&
652 (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) &&
653 (ieee80211_is_beacon(fc) || ieee80211_is_probe_resp(fc)))
654 return;
655
656 if (unlikely(!rtl_action_proc(hw, skb, false)))
657 return;
658
659 uskb = dev_alloc_skb(skb->len + 128);
660 memcpy(IEEE80211_SKB_RXCB(uskb), &rx_status, sizeof(rx_status));
661 pdata = (u8 *)skb_put(uskb, skb->len);
662 memcpy(pdata, skb->data, skb->len);
663
664 ieee80211_rx_irqsafe(hw, uskb);
665}
666
0c817338
LF		 667static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
668{
669 struct rtl_priv *rtlpriv = rtl_priv(hw);
670 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
671 int rx_queue_idx = RTL_PCI_RX_MPDU_QUEUE;
672
673 struct ieee80211_rx_status rx_status = { 0 };
674 unsigned int count = rtlpci->rxringcount;
675 u8 own;
676 u8 tmp_one;
677 u32 bufferaddress;
0c817338
LF		 678
679 struct rtl_stats stats = {
680 .signal = 0,
681 .noise = -98,
682 .rate = 0,
683 };
34ddb207 684 int index = rtlpci->rx_ring[rx_queue_idx].idx;
0c817338
LF		 685
686 /*RX NORMAL PKT */
687 while (count--) {
688 /*rx descriptor */
689 struct rtl_rx_desc *pdesc = &rtlpci->rx_ring[rx_queue_idx].desc[
34ddb207 690 index];
0c817338
LF		 691 /*rx pkt */
692 struct sk_buff *skb = rtlpci->rx_ring[rx_queue_idx].rx_buf[
34ddb207 693 index];
2c333366 694 struct sk_buff *new_skb = NULL;
0c817338
LF		 695
696 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
697 false, HW_DESC_OWN);
698
2c333366
MM		 699 /*wait data to be filled by hardware */
700 if (own)
34ddb207 701 break;
6633d649 702
2c333366
MM		 703 rtlpriv->cfg->ops->query_rx_desc(hw, &stats,
704 &rx_status,
705 (u8 *) pdesc, skb);
706
8db8ddf1
MM		 707 if (stats.crc || stats.hwerror)
708 goto done;
709
2c333366
MM		 710 new_skb = dev_alloc_skb(rtlpci->rxbuffersize);
711 if (unlikely(!new_skb)) {
712 RT_TRACE(rtlpriv, (COMP_INTR | COMP_RECV),
713 DBG_DMESG,
714 ("can't alloc skb for rx\n"));
715 goto done;
716 }
717
718 pci_unmap_single(rtlpci->pdev,
719 *((dma_addr_t *) skb->cb),
720 rtlpci->rxbuffersize,
721 PCI_DMA_FROMDEVICE);
722
723 skb_put(skb, rtlpriv->cfg->ops->get_desc((u8 *) pdesc, false,
724 HW_DESC_RXPKT_LEN));
725 skb_reserve(skb, stats.rx_drvinfo_size + stats.rx_bufshift);
726
727 /*
728 * NOTICE This can not be use for mac80211,
729 * this is done in mac80211 code,
730 * if you done here sec DHCP will fail
731 * skb_trim(skb, skb->len - 4);
732 */
733
fd854772 734 _rtl_receive_one(hw, skb, rx_status);
0c817338 735
2c333366
MM		 736 if (((rtlpriv->link_info.num_rx_inperiod +
737 rtlpriv->link_info.num_tx_inperiod) > 8) ||
738 (rtlpriv->link_info.num_rx_inperiod > 2)) {
739 tasklet_schedule(&rtlpriv->works.ips_leave_tasklet);
740 }
0c817338 741
14058add 742 dev_kfree_skb_any(skb);
2c333366 743 skb = new_skb;
0c817338 744
2c333366
MM		 745 rtlpci->rx_ring[rx_queue_idx].rx_buf[index] = skb;
746 *((dma_addr_t *) skb->cb) =
0c817338
LF		 747 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
748 rtlpci->rxbuffersize,
749 PCI_DMA_FROMDEVICE);
750
0c817338 751done:
d3bb1429 752 bufferaddress = (*((dma_addr_t *)skb->cb));
0c817338
LF		 753 tmp_one = 1;
754 rtlpriv->cfg->ops->set_desc((u8 *) pdesc, false,
755 HW_DESC_RXBUFF_ADDR,
756 (u8 *)&bufferaddress);
0c817338
LF		 757 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false,
758 HW_DESC_RXPKT_LEN,
759 (u8 *)&rtlpci->rxbuffersize);
760
34ddb207 761 if (index == rtlpci->rxringcount - 1)
0c817338
LF		 762 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false,
763 HW_DESC_RXERO,
764 (u8 *)&tmp_one);
765
febc9fe5
MM		 766 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false, HW_DESC_RXOWN,
767 (u8 *)&tmp_one);
768
34ddb207 769 index = (index + 1) % rtlpci->rxringcount;
0c817338
LF		 770 }
771
34ddb207 772 rtlpci->rx_ring[rx_queue_idx].idx = index;
0c817338
LF		 773}
774
0c817338
LF		 775static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id)
776{
777 struct ieee80211_hw *hw = dev_id;
778 struct rtl_priv *rtlpriv = rtl_priv(hw);
c7cfe38e 779 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0c817338
LF		 780 unsigned long flags;
781 u32 inta = 0;
782 u32 intb = 0;
de2e56ce 783 irqreturn_t ret = IRQ_HANDLED;
0c817338 784
0c817338
LF		 785 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
786
787 /*read ISR: 4/8bytes */
788 rtlpriv->cfg->ops->interrupt_recognized(hw, &inta, &intb);
789
790 /*Shared IRQ or HW disappared */
de2e56ce
LF		 791 if (!inta || inta == 0xffff) {
792 ret = IRQ_NONE;
0c817338 793 goto done;
de2e56ce 794 }
0c817338
LF		 795
796 /*<1> beacon related */
797 if (inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK]) {
798 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
799 ("beacon ok interrupt!\n"));
800 }
801
802 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TBDER])) {
803 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
804 ("beacon err interrupt!\n"));
805 }
806
807 if (inta & rtlpriv->cfg->maps[RTL_IMR_BDOK]) {
808 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
809 ("beacon interrupt!\n"));
810 }
811
812 if (inta & rtlpriv->cfg->maps[RTL_IMR_BcnInt]) {
813 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
814 ("prepare beacon for interrupt!\n"));
815 tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet);
816 }
817
818 /*<3> Tx related */
819 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TXFOVW]))
820 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, ("IMR_TXFOVW!\n"));
821
822 if (inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) {
823 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
824 ("Manage ok interrupt!\n"));
825 _rtl_pci_tx_isr(hw, MGNT_QUEUE);
826 }
827
828 if (inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) {
829 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
830 ("HIGH_QUEUE ok interrupt!\n"));
831 _rtl_pci_tx_isr(hw, HIGH_QUEUE);
832 }
833
834 if (inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) {
835 rtlpriv->link_info.num_tx_inperiod++;
836
837 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
838 ("BK Tx OK interrupt!\n"));
839 _rtl_pci_tx_isr(hw, BK_QUEUE);
840 }
841
842 if (inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) {
843 rtlpriv->link_info.num_tx_inperiod++;
844
845 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
846 ("BE TX OK interrupt!\n"));
847 _rtl_pci_tx_isr(hw, BE_QUEUE);
848 }
849
850 if (inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) {
851 rtlpriv->link_info.num_tx_inperiod++;
852
853 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
854 ("VI TX OK interrupt!\n"));
855 _rtl_pci_tx_isr(hw, VI_QUEUE);
856 }
857
858 if (inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) {
859 rtlpriv->link_info.num_tx_inperiod++;
860
861 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
862 ("Vo TX OK interrupt!\n"));
863 _rtl_pci_tx_isr(hw, VO_QUEUE);
864 }
865
c7cfe38e
C		 866 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) {
867 if (inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) {
868 rtlpriv->link_info.num_tx_inperiod++;
869
870 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
871 ("CMD TX OK interrupt!\n"));
872 _rtl_pci_tx_isr(hw, TXCMD_QUEUE);
873 }
874 }
875
0c817338
LF		 876 /*<2> Rx related */
877 if (inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) {
878 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, ("Rx ok interrupt!\n"));
c7cfe38e 879 _rtl_pci_rx_interrupt(hw);
0c817338
LF		 880 }
881
882 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) {
883 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
884 ("rx descriptor unavailable!\n"));
c7cfe38e 885 _rtl_pci_rx_interrupt(hw);
0c817338
LF		 886 }
887
888 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) {
889 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, ("rx overflow !\n"));
c7cfe38e 890 _rtl_pci_rx_interrupt(hw);
0c817338
LF		 891 }
892
c7cfe38e
C		 893 if (rtlpriv->rtlhal.earlymode_enable)
894 tasklet_schedule(&rtlpriv->works.irq_tasklet);
895
0c817338
LF		 896done:
897 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
de2e56ce 898 return ret;
0c817338
LF		 899}
900
901static void _rtl_pci_irq_tasklet(struct ieee80211_hw *hw)
902{
c7cfe38e 903 _rtl_pci_tx_chk_waitq(hw);
0c817338
LF		 904}
905
67fc6052
MM		 906static void _rtl_pci_ips_leave_tasklet(struct ieee80211_hw *hw)
907{
908 rtl_lps_leave(hw);
909}
910
0c817338
LF		 911static void _rtl_pci_prepare_bcn_tasklet(struct ieee80211_hw *hw)
912{
913 struct rtl_priv *rtlpriv = rtl_priv(hw);
914 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
915 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
c7cfe38e 916 struct rtl8192_tx_ring *ring = NULL;
0c817338
LF		 917 struct ieee80211_hdr *hdr = NULL;
918 struct ieee80211_tx_info *info = NULL;
919 struct sk_buff *pskb = NULL;
920 struct rtl_tx_desc *pdesc = NULL;
c7cfe38e 921 struct rtl_tcb_desc tcb_desc;
0c817338
LF		 922 u8 temp_one = 1;
923
c7cfe38e 924 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
0c817338
LF		 925 ring = &rtlpci->tx_ring[BEACON_QUEUE];
926 pskb = __skb_dequeue(&ring->queue);
927 if (pskb)
928 kfree_skb(pskb);
929
930 /*NB: the beacon data buffer must be 32-bit aligned. */
931 pskb = ieee80211_beacon_get(hw, mac->vif);
932 if (pskb == NULL)
933 return;
c7cfe38e 934 hdr = rtl_get_hdr(pskb);
0c817338 935 info = IEEE80211_SKB_CB(pskb);
0c817338
LF		 936 pdesc = &ring->desc[0];
937 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *) pdesc,
c7cfe38e 938 info, pskb, BEACON_QUEUE, &tcb_desc);
0c817338
LF		 939
940 __skb_queue_tail(&ring->queue, pskb);
941
942 rtlpriv->cfg->ops->set_desc((u8 *) pdesc, true, HW_DESC_OWN,
943 (u8 *)&temp_one);
944
945 return;
946}
947
948static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw)
949{
950 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
951 u8 i;
952
953 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
954 rtlpci->txringcount[i] = RT_TXDESC_NUM;
955
956 /*
957 *we just alloc 2 desc for beacon queue,
958 *because we just need first desc in hw beacon.
959 */
960 rtlpci->txringcount[BEACON_QUEUE] = 2;
961
962 /*
963 *BE queue need more descriptor for performance
964 *consideration or, No more tx desc will happen,
965 *and may cause mac80211 mem leakage.
966 */
967 rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE;
968
969 rtlpci->rxbuffersize = 9100; /*2048/1024; */
970 rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT; /*64; */
971}
972
973static void _rtl_pci_init_struct(struct ieee80211_hw *hw,
974 struct pci_dev *pdev)
975{
976 struct rtl_priv *rtlpriv = rtl_priv(hw);
977 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
978 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
979 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0c817338
LF		 980
981 rtlpci->up_first_time = true;
982 rtlpci->being_init_adapter = false;
983
984 rtlhal->hw = hw;
985 rtlpci->pdev = pdev;
986
0c817338
LF		 987 /*Tx/Rx related var */
988 _rtl_pci_init_trx_var(hw);
989
c7cfe38e 990 /*IBSS*/ mac->beacon_interval = 100;
0c817338 991
c7cfe38e
C		 992 /*AMPDU*/
993 mac->min_space_cfg = 0;
0c817338
LF		 994 mac->max_mss_density = 0;
995 /*set sane AMPDU defaults */
996 mac->current_ampdu_density = 7;
997 mac->current_ampdu_factor = 3;
998
c7cfe38e
C		 999 /*QOS*/
1000 rtlpci->acm_method = eAcmWay2_SW;
0c817338
LF		 1001
1002 /*task */
1003 tasklet_init(&rtlpriv->works.irq_tasklet,
1004 (void (*)(unsigned long))_rtl_pci_irq_tasklet,
1005 (unsigned long)hw);
1006 tasklet_init(&rtlpriv->works.irq_prepare_bcn_tasklet,
1007 (void (*)(unsigned long))_rtl_pci_prepare_bcn_tasklet,
1008 (unsigned long)hw);
67fc6052
MM		 1009 tasklet_init(&rtlpriv->works.ips_leave_tasklet,
1010 (void (*)(unsigned long))_rtl_pci_ips_leave_tasklet,
1011 (unsigned long)hw);
0c817338
LF		 1012}
1013
1014static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw,
1015 unsigned int prio, unsigned int entries)
1016{
1017 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1018 struct rtl_priv *rtlpriv = rtl_priv(hw);
1019 struct rtl_tx_desc *ring;
1020 dma_addr_t dma;
1021 u32 nextdescaddress;
1022 int i;
1023
1024 ring = pci_alloc_consistent(rtlpci->pdev,
1025 sizeof(*ring) * entries, &dma);
1026
1027 if (!ring || (unsigned long)ring & 0xFF) {
1028 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1029 ("Cannot allocate TX ring (prio = %d)\n", prio));
1030 return -ENOMEM;
1031 }
1032
1033 memset(ring, 0, sizeof(*ring) * entries);
1034 rtlpci->tx_ring[prio].desc = ring;
1035 rtlpci->tx_ring[prio].dma = dma;
1036 rtlpci->tx_ring[prio].idx = 0;
1037 rtlpci->tx_ring[prio].entries = entries;
1038 skb_queue_head_init(&rtlpci->tx_ring[prio].queue);
1039
1040 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1041 ("queue:%d, ring_addr:%p\n", prio, ring));
1042
1043 for (i = 0; i < entries; i++) {
d3bb1429 1044 nextdescaddress = (u32) dma +
982d96bb 1045 ((i + 1) % entries) *
d3bb1429 1046 sizeof(*ring);
0c817338
LF		 1047
1048 rtlpriv->cfg->ops->set_desc((u8 *)&(ring[i]),
1049 true, HW_DESC_TX_NEXTDESC_ADDR,
1050 (u8 *)&nextdescaddress);
1051 }
1052
1053 return 0;
1054}
1055
1056static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw)
1057{
1058 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1059 struct rtl_priv *rtlpriv = rtl_priv(hw);
1060 struct rtl_rx_desc *entry = NULL;
1061 int i, rx_queue_idx;
1062 u8 tmp_one = 1;
1063
1064 /*
1065 *rx_queue_idx 0:RX_MPDU_QUEUE
1066 *rx_queue_idx 1:RX_CMD_QUEUE
1067 */
1068 for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1069 rx_queue_idx++) {
1070 rtlpci->rx_ring[rx_queue_idx].desc =
1071 pci_alloc_consistent(rtlpci->pdev,
1072 sizeof(*rtlpci->rx_ring[rx_queue_idx].
1073 desc) * rtlpci->rxringcount,
1074 &rtlpci->rx_ring[rx_queue_idx].dma);
1075
1076 if (!rtlpci->rx_ring[rx_queue_idx].desc ||
1077 (unsigned long)rtlpci->rx_ring[rx_queue_idx].desc & 0xFF) {
1078 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1079 ("Cannot allocate RX ring\n"));
1080 return -ENOMEM;
1081 }
1082
1083 memset(rtlpci->rx_ring[rx_queue_idx].desc, 0,
1084 sizeof(*rtlpci->rx_ring[rx_queue_idx].desc) *
1085 rtlpci->rxringcount);
1086
1087 rtlpci->rx_ring[rx_queue_idx].idx = 0;
1088
0019a2c9
LF		 1089 /* If amsdu_8k is disabled, set buffersize to 4096. This
1090 * change will reduce memory fragmentation.
1091 */
1092 if (rtlpci->rxbuffersize > 4096 &&
1093 rtlpriv->rtlhal.disable_amsdu_8k)
1094 rtlpci->rxbuffersize = 4096;
1095
0c817338
LF		 1096 for (i = 0; i < rtlpci->rxringcount; i++) {
1097 struct sk_buff *skb =
1098 dev_alloc_skb(rtlpci->rxbuffersize);
1099 u32 bufferaddress;
0c817338
LF		 1100 if (!skb)
1101 return 0;
bdc4bf65 1102 entry = &rtlpci->rx_ring[rx_queue_idx].desc[i];
0c817338
LF		 1103
1104 /*skb->dev = dev; */
1105
1106 rtlpci->rx_ring[rx_queue_idx].rx_buf[i] = skb;
1107
1108 /*
1109 *just set skb->cb to mapping addr
1110 *for pci_unmap_single use
1111 */
1112 *((dma_addr_t *) skb->cb) =
1113 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
1114 rtlpci->rxbuffersize,
1115 PCI_DMA_FROMDEVICE);
1116
d3bb1429 1117 bufferaddress = (*((dma_addr_t *)skb->cb));
0c817338
LF		 1118 rtlpriv->cfg->ops->set_desc((u8 *)entry, false,
1119 HW_DESC_RXBUFF_ADDR,
1120 (u8 *)&bufferaddress);
1121 rtlpriv->cfg->ops->set_desc((u8 *)entry, false,
1122 HW_DESC_RXPKT_LEN,
1123 (u8 *)&rtlpci->
1124 rxbuffersize);
1125 rtlpriv->cfg->ops->set_desc((u8 *) entry, false,
1126 HW_DESC_RXOWN,
1127 (u8 *)&tmp_one);
1128 }
1129
1130 rtlpriv->cfg->ops->set_desc((u8 *) entry, false,
1131 HW_DESC_RXERO, (u8 *)&tmp_one);
1132 }
1133 return 0;
1134}
1135
1136static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw,
1137 unsigned int prio)
1138{
1139 struct rtl_priv *rtlpriv = rtl_priv(hw);
1140 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1141 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
1142
1143 while (skb_queue_len(&ring->queue)) {
1144 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
1145 struct sk_buff *skb = __skb_dequeue(&ring->queue);
1146
1147 pci_unmap_single(rtlpci->pdev,
d3bb1429 1148 rtlpriv->cfg->
0c817338 1149 ops->get_desc((u8 *) entry, true,
d3bb1429 1150 HW_DESC_TXBUFF_ADDR),
0c817338
LF		 1151 skb->len, PCI_DMA_TODEVICE);
1152 kfree_skb(skb);
1153 ring->idx = (ring->idx + 1) % ring->entries;
1154 }
1155
1156 pci_free_consistent(rtlpci->pdev,
1157 sizeof(*ring->desc) * ring->entries,
1158 ring->desc, ring->dma);
1159 ring->desc = NULL;
1160}
1161
1162static void _rtl_pci_free_rx_ring(struct rtl_pci *rtlpci)
1163{
1164 int i, rx_queue_idx;
1165
1166 /*rx_queue_idx 0:RX_MPDU_QUEUE */
1167 /*rx_queue_idx 1:RX_CMD_QUEUE */
1168 for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1169 rx_queue_idx++) {
1170 for (i = 0; i < rtlpci->rxringcount; i++) {
1171 struct sk_buff *skb =
1172 rtlpci->rx_ring[rx_queue_idx].rx_buf[i];
1173 if (!skb)
1174 continue;
1175
1176 pci_unmap_single(rtlpci->pdev,
1177 *((dma_addr_t *) skb->cb),
1178 rtlpci->rxbuffersize,
1179 PCI_DMA_FROMDEVICE);
1180 kfree_skb(skb);
1181 }
1182
1183 pci_free_consistent(rtlpci->pdev,
1184 sizeof(*rtlpci->rx_ring[rx_queue_idx].
1185 desc) * rtlpci->rxringcount,
1186 rtlpci->rx_ring[rx_queue_idx].desc,
1187 rtlpci->rx_ring[rx_queue_idx].dma);
1188 rtlpci->rx_ring[rx_queue_idx].desc = NULL;
1189 }
1190}
1191
1192static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw)
1193{
1194 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1195 int ret;
1196 int i;
1197
1198 ret = _rtl_pci_init_rx_ring(hw);
1199 if (ret)
1200 return ret;
1201
1202 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1203 ret = _rtl_pci_init_tx_ring(hw, i,
1204 rtlpci->txringcount[i]);
1205 if (ret)
1206 goto err_free_rings;
1207 }
1208
1209 return 0;
1210
1211err_free_rings:
1212 _rtl_pci_free_rx_ring(rtlpci);
1213
1214 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1215 if (rtlpci->tx_ring[i].desc)
1216 _rtl_pci_free_tx_ring(hw, i);
1217
1218 return 1;
1219}
1220
1221static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw)
1222{
1223 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1224 u32 i;
1225
1226 /*free rx rings */
1227 _rtl_pci_free_rx_ring(rtlpci);
1228
1229 /*free tx rings */
1230 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1231 _rtl_pci_free_tx_ring(hw, i);
1232
1233 return 0;
1234}
1235
1236int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw)
1237{
1238 struct rtl_priv *rtlpriv = rtl_priv(hw);
1239 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1240 int i, rx_queue_idx;
1241 unsigned long flags;
1242 u8 tmp_one = 1;
1243
1244 /*rx_queue_idx 0:RX_MPDU_QUEUE */
1245 /*rx_queue_idx 1:RX_CMD_QUEUE */
1246 for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1247 rx_queue_idx++) {
1248 /*
1249 *force the rx_ring[RX_MPDU_QUEUE/
1250 *RX_CMD_QUEUE].idx to the first one
1251 */
1252 if (rtlpci->rx_ring[rx_queue_idx].desc) {
1253 struct rtl_rx_desc *entry = NULL;
1254
1255 for (i = 0; i < rtlpci->rxringcount; i++) {
1256 entry = &rtlpci->rx_ring[rx_queue_idx].desc[i];
1257 rtlpriv->cfg->ops->set_desc((u8 *) entry,
1258 false,
1259 HW_DESC_RXOWN,
1260 (u8 *)&tmp_one);
1261 }
1262 rtlpci->rx_ring[rx_queue_idx].idx = 0;
1263 }
1264 }
1265
1266 /*
1267 *after reset, release previous pending packet,
1268 *and force the tx idx to the first one
1269 */
1270 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1271 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1272 if (rtlpci->tx_ring[i].desc) {
1273 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i];
1274
1275 while (skb_queue_len(&ring->queue)) {
1276 struct rtl_tx_desc *entry =
1277 &ring->desc[ring->idx];
1278 struct sk_buff *skb =
1279 __skb_dequeue(&ring->queue);
1280
1281 pci_unmap_single(rtlpci->pdev,
d3bb1429 1282 rtlpriv->cfg->ops->
0c817338
LF		 1283 get_desc((u8 *)
1284 entry,
1285 true,
d3bb1429 1286 HW_DESC_TXBUFF_ADDR),
0c817338
LF		 1287 skb->len, PCI_DMA_TODEVICE);
1288 kfree_skb(skb);
1289 ring->idx = (ring->idx + 1) % ring->entries;
1290 }
1291 ring->idx = 0;
1292 }
1293 }
1294
1295 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1296
1297 return 0;
1298}
1299
c7cfe38e
C		 1300static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw,
1301 struct sk_buff *skb)
0c817338 1302{
c7cfe38e
C		 1303 struct rtl_priv *rtlpriv = rtl_priv(hw);
1304 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1305 struct ieee80211_sta *sta = info->control.sta;
1306 struct rtl_sta_info *sta_entry = NULL;
1307 u8 tid = rtl_get_tid(skb);
1308
1309 if (!sta)
1310 return false;
1311 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1312
1313 if (!rtlpriv->rtlhal.earlymode_enable)
1314 return false;
1315 if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL)
1316 return false;
1317 if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE)
1318 return false;
1319 if (tid > 7)
1320 return false;
1321
1322 /* maybe every tid should be checked */
1323 if (!rtlpriv->link_info.higher_busytxtraffic[tid])
1324 return false;
1325
1326 spin_lock_bh(&rtlpriv->locks.waitq_lock);
1327 skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb);
1328 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
0c817338 1329
c7cfe38e 1330 return true;
0c817338
LF		 1331}
1332
d3bb1429 1333static int rtl_pci_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
c7cfe38e 1334 struct rtl_tcb_desc *ptcb_desc)
0c817338
LF		 1335{
1336 struct rtl_priv *rtlpriv = rtl_priv(hw);
c7cfe38e 1337 struct rtl_sta_info *sta_entry = NULL;
0c817338 1338 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
c7cfe38e 1339 struct ieee80211_sta *sta = info->control.sta;
0c817338
LF		 1340 struct rtl8192_tx_ring *ring;
1341 struct rtl_tx_desc *pdesc;
1342 u8 idx;
c7cfe38e 1343 u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb);
0c817338 1344 unsigned long flags;
c7cfe38e
C		 1345 struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
1346 __le16 fc = rtl_get_fc(skb);
0c817338
LF		 1347 u8 *pda_addr = hdr->addr1;
1348 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1349 /*ssn */
0c817338
LF		 1350 u8 tid = 0;
1351 u16 seq_number = 0;
1352 u8 own;
1353 u8 temp_one = 1;
1354
c7cfe38e
C		 1355 if (ieee80211_is_auth(fc)) {
1356 RT_TRACE(rtlpriv, COMP_SEND, DBG_DMESG, ("MAC80211_LINKING\n"));
1357 rtl_ips_nic_on(hw);
1358 }
1359
1360 if (rtlpriv->psc.sw_ps_enabled) {
1361 if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) &&
1362 !ieee80211_has_pm(fc))
1363 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1364 }
0c817338 1365
c7cfe38e 1366 rtl_action_proc(hw, skb, true);
0c817338
LF		 1367
1368 if (is_multicast_ether_addr(pda_addr))
1369 rtlpriv->stats.txbytesmulticast += skb->len;
1370 else if (is_broadcast_ether_addr(pda_addr))
1371 rtlpriv->stats.txbytesbroadcast += skb->len;
1372 else
1373 rtlpriv->stats.txbytesunicast += skb->len;
1374
1375 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
0c817338
LF		 1376 ring = &rtlpci->tx_ring[hw_queue];
1377 if (hw_queue != BEACON_QUEUE)
1378 idx = (ring->idx + skb_queue_len(&ring->queue)) %
1379 ring->entries;
1380 else
1381 idx = 0;
1382
1383 pdesc = &ring->desc[idx];
1384 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
1385 true, HW_DESC_OWN);
1386
1387 if ((own == 1) && (hw_queue != BEACON_QUEUE)) {
1388 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1389 ("No more TX desc@%d, ring->idx = %d,"
1390 "idx = %d, skb_queue_len = 0x%d\n",
1391 hw_queue, ring->idx, idx,
1392 skb_queue_len(&ring->queue)));
1393
1394 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1395 return skb->len;
1396 }
1397
0c817338 1398 if (ieee80211_is_data_qos(fc)) {
c7cfe38e
C		 1399 tid = rtl_get_tid(skb);
1400 if (sta) {
1401 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1402 seq_number = (le16_to_cpu(hdr->seq_ctrl) &
1403 IEEE80211_SCTL_SEQ) >> 4;
1404 seq_number += 1;
1405
1406 if (!ieee80211_has_morefrags(hdr->frame_control))
1407 sta_entry->tids[tid].seq_number = seq_number;
1408 }
0c817338
LF		 1409 }
1410
1411 if (ieee80211_is_data(fc))
1412 rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX);
1413
c7cfe38e
C		 1414 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
1415 info, skb, hw_queue, ptcb_desc);
0c817338
LF		 1416
1417 __skb_queue_tail(&ring->queue, skb);
1418
c7cfe38e 1419 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, true,
0c817338
LF		 1420 HW_DESC_OWN, (u8 *)&temp_one);
1421
0c817338
LF		 1422
1423 if ((ring->entries - skb_queue_len(&ring->queue)) < 2 &&
1424 hw_queue != BEACON_QUEUE) {
1425
1426 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
1427 ("less desc left, stop skb_queue@%d, "
1428 "ring->idx = %d,"
1429 "idx = %d, skb_queue_len = 0x%d\n",
1430 hw_queue, ring->idx, idx,
1431 skb_queue_len(&ring->queue)));
1432
1433 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
1434 }
1435
1436 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1437
1438 rtlpriv->cfg->ops->tx_polling(hw, hw_queue);
1439
1440 return 0;
1441}
1442
c7cfe38e
C		 1443static void rtl_pci_flush(struct ieee80211_hw *hw, bool drop)
1444{
1445 struct rtl_priv *rtlpriv = rtl_priv(hw);
1446 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1447 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1448 u16 i = 0;
1449 int queue_id;
1450 struct rtl8192_tx_ring *ring;
1451
1452 for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) {
1453 u32 queue_len;
1454 ring = &pcipriv->dev.tx_ring[queue_id];
1455 queue_len = skb_queue_len(&ring->queue);
1456 if (queue_len == 0 || queue_id == BEACON_QUEUE ||
1457 queue_id == TXCMD_QUEUE) {
1458 queue_id--;
1459 continue;
1460 } else {
1461 msleep(20);
1462 i++;
1463 }
1464
1465 /* we just wait 1s for all queues */
1466 if (rtlpriv->psc.rfpwr_state == ERFOFF ||
1467 is_hal_stop(rtlhal) || i >= 200)
1468 return;
1469 }
1470}
1471
d3bb1429 1472static void rtl_pci_deinit(struct ieee80211_hw *hw)
0c817338
LF		 1473{
1474 struct rtl_priv *rtlpriv = rtl_priv(hw);
1475 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1476
1477 _rtl_pci_deinit_trx_ring(hw);
1478
1479 synchronize_irq(rtlpci->pdev->irq);
1480 tasklet_kill(&rtlpriv->works.irq_tasklet);
67fc6052 1481 tasklet_kill(&rtlpriv->works.ips_leave_tasklet);
0c817338
LF		 1482
1483 flush_workqueue(rtlpriv->works.rtl_wq);
1484 destroy_workqueue(rtlpriv->works.rtl_wq);
1485
1486}
1487
d3bb1429 1488static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev)
0c817338
LF		 1489{
1490 struct rtl_priv *rtlpriv = rtl_priv(hw);
1491 int err;
1492
1493 _rtl_pci_init_struct(hw, pdev);
1494
1495 err = _rtl_pci_init_trx_ring(hw);
1496 if (err) {
1497 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1498 ("tx ring initialization failed"));
1499 return err;
1500 }
1501
1502 return 1;
1503}
1504
d3bb1429 1505static int rtl_pci_start(struct ieee80211_hw *hw)
0c817338
LF		 1506{
1507 struct rtl_priv *rtlpriv = rtl_priv(hw);
1508 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1509 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1510 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1511
1512 int err;
1513
1514 rtl_pci_reset_trx_ring(hw);
1515
1516 rtlpci->driver_is_goingto_unload = false;
1517 err = rtlpriv->cfg->ops->hw_init(hw);
1518 if (err) {
1519 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1520 ("Failed to config hardware!\n"));
1521 return err;
1522 }
1523
1524 rtlpriv->cfg->ops->enable_interrupt(hw);
1525 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("enable_interrupt OK\n"));
1526
1527 rtl_init_rx_config(hw);
1528
fb914ebf 1529 /*should be after adapter start and interrupt enable. */
0c817338
LF		 1530 set_hal_start(rtlhal);
1531
1532 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1533
1534 rtlpci->up_first_time = false;
1535
1536 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("OK\n"));
1537 return 0;
1538}
1539
d3bb1429 1540static void rtl_pci_stop(struct ieee80211_hw *hw)
0c817338
LF		 1541{
1542 struct rtl_priv *rtlpriv = rtl_priv(hw);
1543 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1544 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1545 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1546 unsigned long flags;
1547 u8 RFInProgressTimeOut = 0;
1548
1549 /*
fb914ebf 1550 *should be before disable interrupt&adapter
0c817338
LF		 1551 *and will do it immediately.
1552 */
1553 set_hal_stop(rtlhal);
1554
1555 rtlpriv->cfg->ops->disable_interrupt(hw);
67fc6052 1556 tasklet_kill(&rtlpriv->works.ips_leave_tasklet);
0c817338
LF		 1557
1558 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1559 while (ppsc->rfchange_inprogress) {
1560 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1561 if (RFInProgressTimeOut > 100) {
1562 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1563 break;
1564 }
1565 mdelay(1);
1566 RFInProgressTimeOut++;
1567 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1568 }
1569 ppsc->rfchange_inprogress = true;
1570 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1571
1572 rtlpci->driver_is_goingto_unload = true;
1573 rtlpriv->cfg->ops->hw_disable(hw);
1574 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1575
1576 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1577 ppsc->rfchange_inprogress = false;
1578 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1579
1580 rtl_pci_enable_aspm(hw);
1581}
1582
1583static bool _rtl_pci_find_adapter(struct pci_dev *pdev,
1584 struct ieee80211_hw *hw)
1585{
1586 struct rtl_priv *rtlpriv = rtl_priv(hw);
1587 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1588 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1589 struct pci_dev *bridge_pdev = pdev->bus->self;
1590 u16 venderid;
1591 u16 deviceid;
c7cfe38e 1592 u8 revisionid;
0c817338
LF		 1593 u16 irqline;
1594 u8 tmp;
1595
fc7707a4 1596 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
0c817338
LF		 1597 venderid = pdev->vendor;
1598 deviceid = pdev->device;
c7cfe38e 1599 pci_read_config_byte(pdev, 0x8, &revisionid);
0c817338
LF		 1600 pci_read_config_word(pdev, 0x3C, &irqline);
1601
fa7ccfb1
LF		 1602 /* PCI ID 0x10ec:0x8192 occurs for both RTL8192E, which uses
1603 * r8192e_pci, and RTL8192SE, which uses this driver. If the
1604 * revision ID is RTL_PCI_REVISION_ID_8192PCIE (0x01), then
1605 * the correct driver is r8192e_pci, thus this routine should
1606 * return false.
1607 */
1608 if (deviceid == RTL_PCI_8192SE_DID &&
1609 revisionid == RTL_PCI_REVISION_ID_8192PCIE)
1610 return false;
1611
0c817338
LF		 1612 if (deviceid == RTL_PCI_8192_DID ||
1613 deviceid == RTL_PCI_0044_DID ||
1614 deviceid == RTL_PCI_0047_DID ||
1615 deviceid == RTL_PCI_8192SE_DID ||
1616 deviceid == RTL_PCI_8174_DID ||
1617 deviceid == RTL_PCI_8173_DID ||
1618 deviceid == RTL_PCI_8172_DID ||
1619 deviceid == RTL_PCI_8171_DID) {
c7cfe38e 1620 switch (revisionid) {
0c817338
LF		 1621 case RTL_PCI_REVISION_ID_8192PCIE:
1622 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1623 ("8192 PCI-E is found - "
1624 "vid/did=%x/%x\n", venderid, deviceid));
1625 rtlhal->hw_type = HARDWARE_TYPE_RTL8192E;
1626 break;
1627 case RTL_PCI_REVISION_ID_8192SE:
1628 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1629 ("8192SE is found - "
1630 "vid/did=%x/%x\n", venderid, deviceid));
1631 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1632 break;
1633 default:
1634 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1635 ("Err: Unknown device - "
1636 "vid/did=%x/%x\n", venderid, deviceid));
1637 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1638 break;
1639
1640 }
1641 } else if (deviceid == RTL_PCI_8192CET_DID ||
1642 deviceid == RTL_PCI_8192CE_DID ||
1643 deviceid == RTL_PCI_8191CE_DID ||
1644 deviceid == RTL_PCI_8188CE_DID) {
1645 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE;
1646 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1647 ("8192C PCI-E is found - "
1648 "vid/did=%x/%x\n", venderid, deviceid));
c7cfe38e
C		 1649 } else if (deviceid == RTL_PCI_8192DE_DID ||
1650 deviceid == RTL_PCI_8192DE_DID2) {
1651 rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE;
1652 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1653 ("8192D PCI-E is found - "
1654 "vid/did=%x/%x\n", venderid, deviceid));
0c817338
LF		 1655 } else {
1656 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1657 ("Err: Unknown device -"
1658 " vid/did=%x/%x\n", venderid, deviceid));
1659
1660 rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE;
1661 }
1662
c7cfe38e
C		 1663 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) {
1664 if (revisionid == 0 || revisionid == 1) {
1665 if (revisionid == 0) {
1666 RT_TRACE(rtlpriv, COMP_INIT,
1667 DBG_LOUD, ("Find 92DE MAC0.\n"));
1668 rtlhal->interfaceindex = 0;
1669 } else if (revisionid == 1) {
1670 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1671 ("Find 92DE MAC1.\n"));
1672 rtlhal->interfaceindex = 1;
1673 }
1674 } else {
1675 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1676 ("Unknown device - "
1677 "VendorID/DeviceID=%x/%x, Revision=%x\n",
1678 venderid, deviceid, revisionid));
1679 rtlhal->interfaceindex = 0;
1680 }
1681 }
0c817338
LF		 1682 /*find bus info */
1683 pcipriv->ndis_adapter.busnumber = pdev->bus->number;
1684 pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn);
1685 pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn);
1686
b6b67df3
LF		 1687 if (bridge_pdev) {
1688 /*find bridge info if available */
1689 pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor;
1690 for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) {
1691 if (bridge_pdev->vendor == pcibridge_vendors[tmp]) {
1692 pcipriv->ndis_adapter.pcibridge_vendor = tmp;
1693 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1694 ("Pci Bridge Vendor is found index:"
1695 " %d\n", tmp));
1696 break;
1697 }
0c817338
LF		 1698 }
1699 }
1700
1701 if (pcipriv->ndis_adapter.pcibridge_vendor !=
1702 PCI_BRIDGE_VENDOR_UNKNOWN) {
1703 pcipriv->ndis_adapter.pcibridge_busnum =
1704 bridge_pdev->bus->number;
1705 pcipriv->ndis_adapter.pcibridge_devnum =
1706 PCI_SLOT(bridge_pdev->devfn);
1707 pcipriv->ndis_adapter.pcibridge_funcnum =
1708 PCI_FUNC(bridge_pdev->devfn);
c7cfe38e
C		 1709 pcipriv->ndis_adapter.pcibridge_pciehdr_offset =
1710 pci_pcie_cap(bridge_pdev);
0c817338
LF		 1711 pcipriv->ndis_adapter.num4bytes =
1712 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10) / 4;
1713
1714 rtl_pci_get_linkcontrol_field(hw);
1715
1716 if (pcipriv->ndis_adapter.pcibridge_vendor ==
1717 PCI_BRIDGE_VENDOR_AMD) {
1718 pcipriv->ndis_adapter.amd_l1_patch =
1719 rtl_pci_get_amd_l1_patch(hw);
1720 }
1721 }
1722
1723 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1724 ("pcidev busnumber:devnumber:funcnumber:"
1725 "vendor:link_ctl %d:%d:%d:%x:%x\n",
1726 pcipriv->ndis_adapter.busnumber,
1727 pcipriv->ndis_adapter.devnumber,
1728 pcipriv->ndis_adapter.funcnumber,
1729 pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg));
1730
1731 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1732 ("pci_bridge busnumber:devnumber:funcnumber:vendor:"
1733 "pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n",
1734 pcipriv->ndis_adapter.pcibridge_busnum,
1735 pcipriv->ndis_adapter.pcibridge_devnum,
1736 pcipriv->ndis_adapter.pcibridge_funcnum,
1737 pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor],
1738 pcipriv->ndis_adapter.pcibridge_pciehdr_offset,
1739 pcipriv->ndis_adapter.pcibridge_linkctrlreg,
1740 pcipriv->ndis_adapter.amd_l1_patch));
1741
1742 rtl_pci_parse_configuration(pdev, hw);
1743
1744 return true;
1745}
1746
1747int __devinit rtl_pci_probe(struct pci_dev *pdev,
1748 const struct pci_device_id *id)
1749{
1750 struct ieee80211_hw *hw = NULL;
1751
1752 struct rtl_priv *rtlpriv = NULL;
1753 struct rtl_pci_priv *pcipriv = NULL;
1754 struct rtl_pci *rtlpci;
1755 unsigned long pmem_start, pmem_len, pmem_flags;
1756 int err;
1757
1758 err = pci_enable_device(pdev);
1759 if (err) {
1760 RT_ASSERT(false,
1761 ("%s : Cannot enable new PCI device\n",
1762 pci_name(pdev)));
1763 return err;
1764 }
1765
1766 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
1767 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
1768 RT_ASSERT(false, ("Unable to obtain 32bit DMA "
1769 "for consistent allocations\n"));
1770 pci_disable_device(pdev);
1771 return -ENOMEM;
1772 }
1773 }
1774
1775 pci_set_master(pdev);
1776
1777 hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) +
1778 sizeof(struct rtl_priv), &rtl_ops);
1779 if (!hw) {
1780 RT_ASSERT(false,
1781 ("%s : ieee80211 alloc failed\n", pci_name(pdev)));
1782 err = -ENOMEM;
1783 goto fail1;
1784 }
1785
1786 SET_IEEE80211_DEV(hw, &pdev->dev);
1787 pci_set_drvdata(pdev, hw);
1788
1789 rtlpriv = hw->priv;
1790 pcipriv = (void *)rtlpriv->priv;
1791 pcipriv->dev.pdev = pdev;
1792
c7cfe38e
C		 1793 /* init cfg & intf_ops */
1794 rtlpriv->rtlhal.interface = INTF_PCI;
1795 rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data);
1796 rtlpriv->intf_ops = &rtl_pci_ops;
1797
0c817338
LF		 1798 /*
1799 *init dbgp flags before all
1800 *other functions, because we will
1801 *use it in other funtions like
1802 *RT_TRACE/RT_PRINT/RTL_PRINT_DATA
1803 *you can not use these macro
1804 *before this
1805 */
1806 rtl_dbgp_flag_init(hw);
1807
1808 /* MEM map */
1809 err = pci_request_regions(pdev, KBUILD_MODNAME);
1810 if (err) {
1811 RT_ASSERT(false, ("Can't obtain PCI resources\n"));
1812 return err;
1813 }
1814
c7cfe38e
C		 1815 pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id);
1816 pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id);
1817 pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id);
0c817338
LF		 1818
1819 /*shared mem start */
1820 rtlpriv->io.pci_mem_start =
c7cfe38e
C		 1821 (unsigned long)pci_iomap(pdev,
1822 rtlpriv->cfg->bar_id, pmem_len);
0c817338
LF		 1823 if (rtlpriv->io.pci_mem_start == 0) {
1824 RT_ASSERT(false, ("Can't map PCI mem\n"));
1825 goto fail2;
1826 }
1827
1828 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1829 ("mem mapped space: start: 0x%08lx len:%08lx "
1830 "flags:%08lx, after map:0x%08lx\n",
1831 pmem_start, pmem_len, pmem_flags,
1832 rtlpriv->io.pci_mem_start));
1833
1834 /* Disable Clk Request */
1835 pci_write_config_byte(pdev, 0x81, 0);
1836 /* leave D3 mode */
1837 pci_write_config_byte(pdev, 0x44, 0);
1838 pci_write_config_byte(pdev, 0x04, 0x06);
1839 pci_write_config_byte(pdev, 0x04, 0x07);
1840
0c817338 1841 /* find adapter */
fa7ccfb1
LF		 1842 if (!_rtl_pci_find_adapter(pdev, hw))
1843 goto fail3;
0c817338
LF		 1844
1845 /* Init IO handler */
1846 _rtl_pci_io_handler_init(&pdev->dev, hw);
1847
1848 /*like read eeprom and so on */
1849 rtlpriv->cfg->ops->read_eeprom_info(hw);
1850
1851 if (rtlpriv->cfg->ops->init_sw_vars(hw)) {
1852 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1853 ("Can't init_sw_vars.\n"));
1854 goto fail3;
1855 }
1856
1857 rtlpriv->cfg->ops->init_sw_leds(hw);
1858
1859 /*aspm */
1860 rtl_pci_init_aspm(hw);
1861
1862 /* Init mac80211 sw */
1863 err = rtl_init_core(hw);
1864 if (err) {
1865 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1866 ("Can't allocate sw for mac80211.\n"));
1867 goto fail3;
1868 }
1869
1870 /* Init PCI sw */
1871 err = !rtl_pci_init(hw, pdev);
1872 if (err) {
1873 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1874 ("Failed to init PCI.\n"));
1875 goto fail3;
1876 }
1877
1878 err = ieee80211_register_hw(hw);
1879 if (err) {
1880 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1881 ("Can't register mac80211 hw.\n"));
1882 goto fail3;
1883 } else {
1884 rtlpriv->mac80211.mac80211_registered = 1;
1885 }
1886
1887 err = sysfs_create_group(&pdev->dev.kobj, &rtl_attribute_group);
1888 if (err) {
1889 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1890 ("failed to create sysfs device attributes\n"));
1891 goto fail3;
1892 }
1893
1894 /*init rfkill */
1895 rtl_init_rfkill(hw);
1896
1897 rtlpci = rtl_pcidev(pcipriv);
1898 err = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
1899 IRQF_SHARED, KBUILD_MODNAME, hw);
1900 if (err) {
1901 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1902 ("%s: failed to register IRQ handler\n",
1903 wiphy_name(hw->wiphy)));
1904 goto fail3;
1905 } else {
1906 rtlpci->irq_alloc = 1;
1907 }
1908
1909 set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
1910 return 0;
1911
1912fail3:
1913 pci_set_drvdata(pdev, NULL);
1914 rtl_deinit_core(hw);
1915 _rtl_pci_io_handler_release(hw);
1916 ieee80211_free_hw(hw);
1917
1918 if (rtlpriv->io.pci_mem_start != 0)
62e63975 1919 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
0c817338
LF		 1920
1921fail2:
1922 pci_release_regions(pdev);
1923
1924fail1:
1925
1926 pci_disable_device(pdev);
1927
1928 return -ENODEV;
1929
1930}
1931EXPORT_SYMBOL(rtl_pci_probe);
1932
1933void rtl_pci_disconnect(struct pci_dev *pdev)
1934{
1935 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
1936 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1937 struct rtl_priv *rtlpriv = rtl_priv(hw);
1938 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
1939 struct rtl_mac *rtlmac = rtl_mac(rtlpriv);
1940
1941 clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
1942
1943 sysfs_remove_group(&pdev->dev.kobj, &rtl_attribute_group);
1944
1945 /*ieee80211_unregister_hw will call ops_stop */
1946 if (rtlmac->mac80211_registered == 1) {
1947 ieee80211_unregister_hw(hw);
1948 rtlmac->mac80211_registered = 0;
1949 } else {
1950 rtl_deinit_deferred_work(hw);
1951 rtlpriv->intf_ops->adapter_stop(hw);
1952 }
1953
1954 /*deinit rfkill */
1955 rtl_deinit_rfkill(hw);
1956
1957 rtl_pci_deinit(hw);
1958 rtl_deinit_core(hw);
0c817338
LF		 1959 _rtl_pci_io_handler_release(hw);
1960 rtlpriv->cfg->ops->deinit_sw_vars(hw);
1961
1962 if (rtlpci->irq_alloc) {
1963 free_irq(rtlpci->pdev->irq, hw);
1964 rtlpci->irq_alloc = 0;
1965 }
1966
1967 if (rtlpriv->io.pci_mem_start != 0) {
62e63975 1968 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
0c817338
LF		 1969 pci_release_regions(pdev);
1970 }
1971
1972 pci_disable_device(pdev);
c7cfe38e
C		 1973
1974 rtl_pci_disable_aspm(hw);
1975
0c817338
LF		 1976 pci_set_drvdata(pdev, NULL);
1977
1978 ieee80211_free_hw(hw);
1979}
1980EXPORT_SYMBOL(rtl_pci_disconnect);
1981
1982/***************************************
1983kernel pci power state define:
1984PCI_D0 ((pci_power_t __force) 0)
1985PCI_D1 ((pci_power_t __force) 1)
1986PCI_D2 ((pci_power_t __force) 2)
1987PCI_D3hot ((pci_power_t __force) 3)
1988PCI_D3cold ((pci_power_t __force) 4)
1989PCI_UNKNOWN ((pci_power_t __force) 5)
1990
1991This function is called when system
1992goes into suspend state mac80211 will
1993call rtl_mac_stop() from the mac80211
1994suspend function first, So there is
1995no need to call hw_disable here.
1996****************************************/
603be388 1997int rtl_pci_suspend(struct device *dev)
0c817338 1998{
603be388 1999 struct pci_dev *pdev = to_pci_dev(dev);
c7cfe38e
C		 2000 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2001 struct rtl_priv *rtlpriv = rtl_priv(hw);
2002
2003 rtlpriv->cfg->ops->hw_suspend(hw);
2004 rtl_deinit_rfkill(hw);
2005
0c817338
LF		 2006 return 0;
2007}
2008EXPORT_SYMBOL(rtl_pci_suspend);
2009
603be388 2010int rtl_pci_resume(struct device *dev)
0c817338 2011{
603be388 2012 struct pci_dev *pdev = to_pci_dev(dev);
c7cfe38e
C		 2013 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2014 struct rtl_priv *rtlpriv = rtl_priv(hw);
0c817338 2015
c7cfe38e
C		 2016 rtlpriv->cfg->ops->hw_resume(hw);
2017 rtl_init_rfkill(hw);
0c817338
LF		 2018 return 0;
2019}
2020EXPORT_SYMBOL(rtl_pci_resume);
2021
2022struct rtl_intf_ops rtl_pci_ops = {
c7cfe38e 2023 .read_efuse_byte = read_efuse_byte,
0c817338
LF		 2024 .adapter_start = rtl_pci_start,
2025 .adapter_stop = rtl_pci_stop,
2026 .adapter_tx = rtl_pci_tx,
c7cfe38e 2027 .flush = rtl_pci_flush,
0c817338 2028 .reset_trx_ring = rtl_pci_reset_trx_ring,
c7cfe38e 2029 .waitq_insert = rtl_pci_tx_chk_waitq_insert,
0c817338
LF		 2030
2031 .disable_aspm = rtl_pci_disable_aspm,
2032 .enable_aspm = rtl_pci_enable_aspm,
2033};
Linux kernel - Deliverables
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