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mac80211: add #ifdef CONFIG_MAC80211_VERBOSE_DEBUG for a debug printk
[deliverable/linux.git] / drivers / net / wireless / rtlwifi / pci.c
CommitLineData
0c817338
LF		 1/******************************************************************************
2 *
a8d76066 3 * Copyright(c) 2009-2012 Realtek Corporation.
0c817338
LF		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
0c817338 30#include "wifi.h"
d273bb20 31#include "core.h"
0c817338
LF		 32#include "pci.h"
33#include "base.h"
34#include "ps.h"
c7cfe38e 35#include "efuse.h"
d273bb20 36#include <linux/export.h>
0c817338
LF		 37
38static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = {
f01dce94
JM		 39 PCI_VENDOR_ID_INTEL,
40 PCI_VENDOR_ID_ATI,
41 PCI_VENDOR_ID_AMD,
42 PCI_VENDOR_ID_SI
0c817338
LF		 43};
44
c7cfe38e
C		 45static const u8 ac_to_hwq[] = {
46 VO_QUEUE,
47 VI_QUEUE,
48 BE_QUEUE,
49 BK_QUEUE
50};
51
d3bb1429 52static u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw,
c7cfe38e
C		 53 struct sk_buff *skb)
54{
55 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
d3bb1429 56 __le16 fc = rtl_get_fc(skb);
c7cfe38e
C		 57 u8 queue_index = skb_get_queue_mapping(skb);
58
59 if (unlikely(ieee80211_is_beacon(fc)))
60 return BEACON_QUEUE;
61 if (ieee80211_is_mgmt(fc))
62 return MGNT_QUEUE;
63 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
64 if (ieee80211_is_nullfunc(fc))
65 return HIGH_QUEUE;
66
67 return ac_to_hwq[queue_index];
68}
69
0c817338
LF		 70/* Update PCI dependent default settings*/
71static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw)
72{
73 struct rtl_priv *rtlpriv = rtl_priv(hw);
74 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
75 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
76 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
77 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
c7cfe38e 78 u8 init_aspm;
0c817338
LF		 79
80 ppsc->reg_rfps_level = 0;
3db1cd5c 81 ppsc->support_aspm = false;
0c817338
LF		 82
83 /*Update PCI ASPM setting */
84 ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm;
85 switch (rtlpci->const_pci_aspm) {
86 case 0:
87 /*No ASPM */
88 break;
89
90 case 1:
91 /*ASPM dynamically enabled/disable. */
92 ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM;
93 break;
94
95 case 2:
96 /*ASPM with Clock Req dynamically enabled/disable. */
97 ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM |
98 RT_RF_OFF_LEVL_CLK_REQ);
99 break;
100
101 case 3:
102 /*
103 * Always enable ASPM and Clock Req
104 * from initialization to halt.
105 * */
106 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM);
107 ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM |
108 RT_RF_OFF_LEVL_CLK_REQ);
109 break;
110
111 case 4:
112 /*
113 * Always enable ASPM without Clock Req
114 * from initialization to halt.
115 * */
116 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM |
117 RT_RF_OFF_LEVL_CLK_REQ);
118 ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM;
119 break;
120 }
121
122 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
123
124 /*Update Radio OFF setting */
125 switch (rtlpci->const_hwsw_rfoff_d3) {
126 case 1:
127 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
128 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
129 break;
130
131 case 2:
132 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
133 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
134 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
135 break;
136
137 case 3:
138 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3;
139 break;
140 }
141
142 /*Set HW definition to determine if it supports ASPM. */
143 switch (rtlpci->const_support_pciaspm) {
c7cfe38e
C		 144 case 0:{
145 /*Not support ASPM. */
146 bool support_aspm = false;
147 ppsc->support_aspm = support_aspm;
148 break;
149 }
150 case 1:{
151 /*Support ASPM. */
152 bool support_aspm = true;
153 bool support_backdoor = true;
154 ppsc->support_aspm = support_aspm;
155
156 /*if (priv->oem_id == RT_CID_TOSHIBA &&
157 !priv->ndis_adapter.amd_l1_patch)
158 support_backdoor = false; */
159
160 ppsc->support_backdoor = support_backdoor;
161
162 break;
163 }
0c817338
LF		 164 case 2:
165 /*ASPM value set by chipset. */
c7cfe38e
C		 166 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) {
167 bool support_aspm = true;
168 ppsc->support_aspm = support_aspm;
169 }
0c817338
LF		 170 break;
171 default:
172 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 173 "switch case not processed\n");
0c817338
LF		 174 break;
175 }
c7cfe38e
C		 176
177 /* toshiba aspm issue, toshiba will set aspm selfly
178 * so we should not set aspm in driver */
179 pci_read_config_byte(rtlpci->pdev, 0x80, &init_aspm);
180 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE &&
181 init_aspm == 0x43)
182 ppsc->support_aspm = false;
183}
184
0c817338
LF		 185static bool _rtl_pci_platform_switch_device_pci_aspm(
186 struct ieee80211_hw *hw,
187 u8 value)
188{
189 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
c7cfe38e
C		 190 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
191
192 if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE)
193 value |= 0x40;
0c817338 194
0c817338
LF		 195 pci_write_config_byte(rtlpci->pdev, 0x80, value);
196
32473284 197 return false;
0c817338
LF		 198}
199
200/*When we set 0x01 to enable clk request. Set 0x0 to disable clk req.*/
1d73c51a 201static void _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u8 value)
0c817338
LF		 202{
203 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
c7cfe38e 204 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0c817338 205
0c817338 206 pci_write_config_byte(rtlpci->pdev, 0x81, value);
0c817338 207
c7cfe38e
C		 208 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
209 udelay(100);
0c817338
LF		 210}
211
212/*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/
213static void rtl_pci_disable_aspm(struct ieee80211_hw *hw)
214{
215 struct rtl_priv *rtlpriv = rtl_priv(hw);
216 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
217 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
218 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
219 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
0c817338
LF		 220 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
221 /*Retrieve original configuration settings. */
222 u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg;
223 u16 pcibridge_linkctrlreg = pcipriv->ndis_adapter.
224 pcibridge_linkctrlreg;
225 u16 aspmlevel = 0;
32473284 226 u8 tmp_u1b = 0;
0c817338 227
c7cfe38e
C		 228 if (!ppsc->support_aspm)
229 return;
230
0c817338
LF		 231 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
232 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
f30d7507 233 "PCI(Bridge) UNKNOWN\n");
0c817338
LF		 234
235 return;
236 }
237
238 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
239 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
240 _rtl_pci_switch_clk_req(hw, 0x0);
241 }
242
32473284
LF		 243 /*for promising device will in L0 state after an I/O. */
244 pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b);
0c817338
LF		 245
246 /*Set corresponding value. */
247 aspmlevel |= BIT(0) | BIT(1);
248 linkctrl_reg &= ~aspmlevel;
249 pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1));
250
251 _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg);
252 udelay(50);
253
254 /*4 Disable Pci Bridge ASPM */
886e14b6
LF		 255 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
256 pcibridge_linkctrlreg);
0c817338
LF		 257
258 udelay(50);
0c817338
LF		 259}
260
261/*
262 *Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for
263 *power saving We should follow the sequence to enable
264 *RTL8192SE first then enable Pci Bridge ASPM
265 *or the system will show bluescreen.
266 */
267static void rtl_pci_enable_aspm(struct ieee80211_hw *hw)
268{
269 struct rtl_priv *rtlpriv = rtl_priv(hw);
270 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
271 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
272 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
273 u8 pcibridge_busnum = pcipriv->ndis_adapter.pcibridge_busnum;
274 u8 pcibridge_devnum = pcipriv->ndis_adapter.pcibridge_devnum;
275 u8 pcibridge_funcnum = pcipriv->ndis_adapter.pcibridge_funcnum;
276 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
0c817338
LF		 277 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
278 u16 aspmlevel;
279 u8 u_pcibridge_aspmsetting;
280 u8 u_device_aspmsetting;
281
c7cfe38e
C		 282 if (!ppsc->support_aspm)
283 return;
284
0c817338
LF		 285 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
286 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
f30d7507 287 "PCI(Bridge) UNKNOWN\n");
0c817338
LF		 288 return;
289 }
290
291 /*4 Enable Pci Bridge ASPM */
0c817338
LF		 292
293 u_pcibridge_aspmsetting =
294 pcipriv->ndis_adapter.pcibridge_linkctrlreg |
295 rtlpci->const_hostpci_aspm_setting;
296
297 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
298 u_pcibridge_aspmsetting &= ~BIT(0);
299
886e14b6
LF		 300 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
301 u_pcibridge_aspmsetting);
0c817338
LF		 302
303 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
f30d7507
JP		 304 "PlatformEnableASPM():PciBridge busnumber[%x], DevNumbe[%x], funcnumber[%x], Write reg[%x] = %x\n",
305 pcibridge_busnum, pcibridge_devnum, pcibridge_funcnum,
306 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10),
307 u_pcibridge_aspmsetting);
0c817338
LF		 308
309 udelay(50);
310
311 /*Get ASPM level (with/without Clock Req) */
312 aspmlevel = rtlpci->const_devicepci_aspm_setting;
313 u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg;
314
315 /*_rtl_pci_platform_switch_device_pci_aspm(dev,*/
316 /*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */
317
318 u_device_aspmsetting |= aspmlevel;
319
320 _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting);
321
322 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
323 _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level &
324 RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0);
325 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
326 }
c7cfe38e 327 udelay(100);
0c817338
LF		 328}
329
330static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw)
331{
886e14b6 332 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
0c817338
LF		 333
334 bool status = false;
335 u8 offset_e0;
336 unsigned offset_e4;
337
886e14b6 338 pci_write_config_byte(rtlpci->pdev, 0xe0, 0xa0);
0c817338 339
886e14b6 340 pci_read_config_byte(rtlpci->pdev, 0xe0, &offset_e0);
0c817338
LF		 341
342 if (offset_e0 == 0xA0) {
886e14b6 343 pci_read_config_dword(rtlpci->pdev, 0xe4, &offset_e4);
0c817338
LF		 344 if (offset_e4 & BIT(23))
345 status = true;
346 }
347
348 return status;
349}
350
d3bb1429 351static void rtl_pci_get_linkcontrol_field(struct ieee80211_hw *hw)
0c817338
LF		 352{
353 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
886e14b6 354 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
0c817338 355 u8 capabilityoffset = pcipriv->ndis_adapter.pcibridge_pciehdr_offset;
0c817338 356 u8 linkctrl_reg;
c7cfe38e 357 u8 num4bbytes;
0c817338 358
c7cfe38e 359 num4bbytes = (capabilityoffset + 0x10) / 4;
0c817338
LF		 360
361 /*Read Link Control Register */
886e14b6 362 pci_read_config_byte(rtlpci->pdev, (num4bbytes << 2), &linkctrl_reg);
0c817338
LF		 363
364 pcipriv->ndis_adapter.pcibridge_linkctrlreg = linkctrl_reg;
365}
366
367static void rtl_pci_parse_configuration(struct pci_dev *pdev,
368 struct ieee80211_hw *hw)
369{
370 struct rtl_priv *rtlpriv = rtl_priv(hw);
371 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
372
373 u8 tmp;
374 int pos;
375 u8 linkctrl_reg;
376
377 /*Link Control Register */
6a4ecc29 378 pos = pci_pcie_cap(pdev);
0c817338
LF		 379 pci_read_config_byte(pdev, pos + PCI_EXP_LNKCTL, &linkctrl_reg);
380 pcipriv->ndis_adapter.linkctrl_reg = linkctrl_reg;
381
f30d7507
JP		 382 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Link Control Register =%x\n",
383 pcipriv->ndis_adapter.linkctrl_reg);
0c817338
LF		 384
385 pci_read_config_byte(pdev, 0x98, &tmp);
386 tmp |= BIT(4);
387 pci_write_config_byte(pdev, 0x98, tmp);
388
389 tmp = 0x17;
390 pci_write_config_byte(pdev, 0x70f, tmp);
391}
392
c7cfe38e 393static void rtl_pci_init_aspm(struct ieee80211_hw *hw)
0c817338
LF		 394{
395 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
396
397 _rtl_pci_update_default_setting(hw);
398
399 if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) {
400 /*Always enable ASPM & Clock Req. */
401 rtl_pci_enable_aspm(hw);
402 RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM);
403 }
404
405}
406
0c817338
LF		 407static void _rtl_pci_io_handler_init(struct device *dev,
408 struct ieee80211_hw *hw)
409{
410 struct rtl_priv *rtlpriv = rtl_priv(hw);
411
412 rtlpriv->io.dev = dev;
413
414 rtlpriv->io.write8_async = pci_write8_async;
415 rtlpriv->io.write16_async = pci_write16_async;
416 rtlpriv->io.write32_async = pci_write32_async;
417
418 rtlpriv->io.read8_sync = pci_read8_sync;
419 rtlpriv->io.read16_sync = pci_read16_sync;
420 rtlpriv->io.read32_sync = pci_read32_sync;
421
422}
423
424static void _rtl_pci_io_handler_release(struct ieee80211_hw *hw)
425{
426}
427
c7cfe38e
C		 428static bool _rtl_update_earlymode_info(struct ieee80211_hw *hw,
429 struct sk_buff *skb, struct rtl_tcb_desc *tcb_desc, u8 tid)
430{
431 struct rtl_priv *rtlpriv = rtl_priv(hw);
432 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
433 u8 additionlen = FCS_LEN;
434 struct sk_buff *next_skb;
435
436 /* here open is 4, wep/tkip is 8, aes is 12*/
437 if (info->control.hw_key)
438 additionlen += info->control.hw_key->icv_len;
439
440 /* The most skb num is 6 */
441 tcb_desc->empkt_num = 0;
442 spin_lock_bh(&rtlpriv->locks.waitq_lock);
443 skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) {
444 struct ieee80211_tx_info *next_info;
445
446 next_info = IEEE80211_SKB_CB(next_skb);
447 if (next_info->flags & IEEE80211_TX_CTL_AMPDU) {
448 tcb_desc->empkt_len[tcb_desc->empkt_num] =
449 next_skb->len + additionlen;
450 tcb_desc->empkt_num++;
451 } else {
452 break;
453 }
454
455 if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid],
456 next_skb))
457 break;
458
459 if (tcb_desc->empkt_num >= 5)
460 break;
461 }
462 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
463
464 return true;
465}
466
467/* just for early mode now */
468static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw)
469{
470 struct rtl_priv *rtlpriv = rtl_priv(hw);
471 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
472 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
473 struct sk_buff *skb = NULL;
474 struct ieee80211_tx_info *info = NULL;
fb914ebf 475 int tid;
c7cfe38e
C		 476
477 if (!rtlpriv->rtlhal.earlymode_enable)
478 return;
479
480 /* we juse use em for BE/BK/VI/VO */
481 for (tid = 7; tid >= 0; tid--) {
482 u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(hw, tid)];
483 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
484 while (!mac->act_scanning &&
485 rtlpriv->psc.rfpwr_state == ERFON) {
486 struct rtl_tcb_desc tcb_desc;
487 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
488
489 spin_lock_bh(&rtlpriv->locks.waitq_lock);
490 if (!skb_queue_empty(&mac->skb_waitq[tid]) &&
491 (ring->entries - skb_queue_len(&ring->queue) > 5)) {
492 skb = skb_dequeue(&mac->skb_waitq[tid]);
493 } else {
494 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
495 break;
496 }
497 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
498
499 /* Some macaddr can't do early mode. like
500 * multicast/broadcast/no_qos data */
501 info = IEEE80211_SKB_CB(skb);
502 if (info->flags & IEEE80211_TX_CTL_AMPDU)
503 _rtl_update_earlymode_info(hw, skb,
504 &tcb_desc, tid);
505
c7cfe38e 506 rtlpriv->intf_ops->adapter_tx(hw, skb, &tcb_desc);
c7cfe38e
C		 507 }
508 }
509}
510
511
0c817338
LF		 512static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio)
513{
514 struct rtl_priv *rtlpriv = rtl_priv(hw);
515 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
516
517 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
518
519 while (skb_queue_len(&ring->queue)) {
520 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
521 struct sk_buff *skb;
522 struct ieee80211_tx_info *info;
c7cfe38e
C		 523 __le16 fc;
524 u8 tid;
0c817338
LF		 525
526 u8 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) entry, true,
527 HW_DESC_OWN);
528
529 /*
530 *beacon packet will only use the first
531 *descriptor defautly,and the own may not
532 *be cleared by the hardware
533 */
534 if (own)
535 return;
536 ring->idx = (ring->idx + 1) % ring->entries;
537
538 skb = __skb_dequeue(&ring->queue);
539 pci_unmap_single(rtlpci->pdev,
d3bb1429 540 rtlpriv->cfg->ops->
0c817338 541 get_desc((u8 *) entry, true,
d3bb1429 542 HW_DESC_TXBUFF_ADDR),
0c817338
LF		 543 skb->len, PCI_DMA_TODEVICE);
544
c7cfe38e
C		 545 /* remove early mode header */
546 if (rtlpriv->rtlhal.earlymode_enable)
547 skb_pull(skb, EM_HDR_LEN);
548
0c817338 549 RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE,
f30d7507
JP		 550 "new ring->idx:%d, free: skb_queue_len:%d, free: seq:%x\n",
551 ring->idx,
552 skb_queue_len(&ring->queue),
553 *(u16 *) (skb->data + 22));
0c817338 554
c7cfe38e
C		 555 if (prio == TXCMD_QUEUE) {
556 dev_kfree_skb(skb);
557 goto tx_status_ok;
558
559 }
560
561 /* for sw LPS, just after NULL skb send out, we can
562 * sure AP kown we are sleeped, our we should not let
563 * rf to sleep*/
564 fc = rtl_get_fc(skb);
565 if (ieee80211_is_nullfunc(fc)) {
566 if (ieee80211_has_pm(fc)) {
9c050440 567 rtlpriv->mac80211.offchan_delay = true;
3db1cd5c 568 rtlpriv->psc.state_inap = true;
c7cfe38e 569 } else {
3db1cd5c 570 rtlpriv->psc.state_inap = false;
c7cfe38e
C		 571 }
572 }
573
574 /* update tid tx pkt num */
575 tid = rtl_get_tid(skb);
576 if (tid <= 7)
577 rtlpriv->link_info.tidtx_inperiod[tid]++;
578
0c817338
LF		 579 info = IEEE80211_SKB_CB(skb);
580 ieee80211_tx_info_clear_status(info);
581
582 info->flags |= IEEE80211_TX_STAT_ACK;
583 /*info->status.rates[0].count = 1; */
584
585 ieee80211_tx_status_irqsafe(hw, skb);
586
587 if ((ring->entries - skb_queue_len(&ring->queue))
588 == 2) {
589
590 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
f30d7507
JP		 591 "more desc left, wake skb_queue@%d, ring->idx = %d, skb_queue_len = 0x%d\n",
592 prio, ring->idx,
593 skb_queue_len(&ring->queue));
0c817338
LF		 594
595 ieee80211_wake_queue(hw,
596 skb_get_queue_mapping
597 (skb));
598 }
c7cfe38e 599tx_status_ok:
0c817338
LF		 600 skb = NULL;
601 }
602
603 if (((rtlpriv->link_info.num_rx_inperiod +
604 rtlpriv->link_info.num_tx_inperiod) > 8) ||
605 (rtlpriv->link_info.num_rx_inperiod > 2)) {
41affd52 606 schedule_work(&rtlpriv->works.lps_leave_work);
0c817338
LF		 607 }
608}
609
fd854772
MM		 610static void _rtl_receive_one(struct ieee80211_hw *hw, struct sk_buff *skb,
611 struct ieee80211_rx_status rx_status)
612{
613 struct rtl_priv *rtlpriv = rtl_priv(hw);
614 struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
615 __le16 fc = rtl_get_fc(skb);
616 bool unicast = false;
617 struct sk_buff *uskb = NULL;
618 u8 *pdata;
619
620
621 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
622
623 if (is_broadcast_ether_addr(hdr->addr1)) {
624 ;/*TODO*/
625 } else if (is_multicast_ether_addr(hdr->addr1)) {
626 ;/*TODO*/
627 } else {
628 unicast = true;
629 rtlpriv->stats.rxbytesunicast += skb->len;
630 }
631
632 rtl_is_special_data(hw, skb, false);
633
634 if (ieee80211_is_data(fc)) {
635 rtlpriv->cfg->ops->led_control(hw, LED_CTL_RX);
636
637 if (unicast)
638 rtlpriv->link_info.num_rx_inperiod++;
639 }
640
641 /* for sw lps */
642 rtl_swlps_beacon(hw, (void *)skb->data, skb->len);
643 rtl_recognize_peer(hw, (void *)skb->data, skb->len);
644 if ((rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP) &&
645 (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) &&
646 (ieee80211_is_beacon(fc) || ieee80211_is_probe_resp(fc)))
647 return;
648
649 if (unlikely(!rtl_action_proc(hw, skb, false)))
650 return;
651
652 uskb = dev_alloc_skb(skb->len + 128);
76a92be5
LF		 653 if (!uskb)
654 return; /* exit if allocation failed */
fd854772
MM		 655 memcpy(IEEE80211_SKB_RXCB(uskb), &rx_status, sizeof(rx_status));
656 pdata = (u8 *)skb_put(uskb, skb->len);
657 memcpy(pdata, skb->data, skb->len);
658
659 ieee80211_rx_irqsafe(hw, uskb);
660}
661
0c817338
LF		 662static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
663{
664 struct rtl_priv *rtlpriv = rtl_priv(hw);
665 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
666 int rx_queue_idx = RTL_PCI_RX_MPDU_QUEUE;
667
668 struct ieee80211_rx_status rx_status = { 0 };
669 unsigned int count = rtlpci->rxringcount;
670 u8 own;
671 u8 tmp_one;
672 u32 bufferaddress;
0c817338
LF		 673
674 struct rtl_stats stats = {
675 .signal = 0,
676 .noise = -98,
677 .rate = 0,
678 };
34ddb207 679 int index = rtlpci->rx_ring[rx_queue_idx].idx;
0c817338
LF		 680
681 /*RX NORMAL PKT */
682 while (count--) {
683 /*rx descriptor */
684 struct rtl_rx_desc *pdesc = &rtlpci->rx_ring[rx_queue_idx].desc[
34ddb207 685 index];
0c817338
LF		 686 /*rx pkt */
687 struct sk_buff *skb = rtlpci->rx_ring[rx_queue_idx].rx_buf[
34ddb207 688 index];
2c333366 689 struct sk_buff *new_skb = NULL;
0c817338
LF		 690
691 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
692 false, HW_DESC_OWN);
693
2c333366
MM		 694 /*wait data to be filled by hardware */
695 if (own)
34ddb207 696 break;
6633d649 697
2c333366
MM		 698 rtlpriv->cfg->ops->query_rx_desc(hw, &stats,
699 &rx_status,
700 (u8 *) pdesc, skb);
701
8db8ddf1
MM		 702 if (stats.crc || stats.hwerror)
703 goto done;
704
2c333366
MM		 705 new_skb = dev_alloc_skb(rtlpci->rxbuffersize);
706 if (unlikely(!new_skb)) {
f30d7507
JP		 707 RT_TRACE(rtlpriv, (COMP_INTR | COMP_RECV), DBG_DMESG,
708 "can't alloc skb for rx\n");
2c333366
MM		 709 goto done;
710 }
711
712 pci_unmap_single(rtlpci->pdev,
713 *((dma_addr_t *) skb->cb),
714 rtlpci->rxbuffersize,
715 PCI_DMA_FROMDEVICE);
716
717 skb_put(skb, rtlpriv->cfg->ops->get_desc((u8 *) pdesc, false,
718 HW_DESC_RXPKT_LEN));
719 skb_reserve(skb, stats.rx_drvinfo_size + stats.rx_bufshift);
720
721 /*
722 * NOTICE This can not be use for mac80211,
723 * this is done in mac80211 code,
724 * if you done here sec DHCP will fail
725 * skb_trim(skb, skb->len - 4);
726 */
727
fd854772 728 _rtl_receive_one(hw, skb, rx_status);
0c817338 729
2c333366
MM		 730 if (((rtlpriv->link_info.num_rx_inperiod +
731 rtlpriv->link_info.num_tx_inperiod) > 8) ||
732 (rtlpriv->link_info.num_rx_inperiod > 2)) {
41affd52 733 schedule_work(&rtlpriv->works.lps_leave_work);
2c333366 734 }
0c817338 735
14058add 736 dev_kfree_skb_any(skb);
2c333366 737 skb = new_skb;
0c817338 738
2c333366
MM		 739 rtlpci->rx_ring[rx_queue_idx].rx_buf[index] = skb;
740 *((dma_addr_t *) skb->cb) =
0c817338
LF		 741 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
742 rtlpci->rxbuffersize,
743 PCI_DMA_FROMDEVICE);
744
0c817338 745done:
d3bb1429 746 bufferaddress = (*((dma_addr_t *)skb->cb));
0c817338
LF		 747 tmp_one = 1;
748 rtlpriv->cfg->ops->set_desc((u8 *) pdesc, false,
749 HW_DESC_RXBUFF_ADDR,
750 (u8 *)&bufferaddress);
0c817338
LF		 751 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false,
752 HW_DESC_RXPKT_LEN,
753 (u8 *)&rtlpci->rxbuffersize);
754
34ddb207 755 if (index == rtlpci->rxringcount - 1)
0c817338
LF		 756 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false,
757 HW_DESC_RXERO,
758 (u8 *)&tmp_one);
759
febc9fe5
MM		 760 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false, HW_DESC_RXOWN,
761 (u8 *)&tmp_one);
762
34ddb207 763 index = (index + 1) % rtlpci->rxringcount;
0c817338
LF		 764 }
765
34ddb207 766 rtlpci->rx_ring[rx_queue_idx].idx = index;
0c817338
LF		 767}
768
0c817338
LF		 769static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id)
770{
771 struct ieee80211_hw *hw = dev_id;
772 struct rtl_priv *rtlpriv = rtl_priv(hw);
c7cfe38e 773 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0c817338
LF		 774 unsigned long flags;
775 u32 inta = 0;
776 u32 intb = 0;
de2e56ce 777 irqreturn_t ret = IRQ_HANDLED;
0c817338 778
0c817338
LF		 779 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
780
781 /*read ISR: 4/8bytes */
782 rtlpriv->cfg->ops->interrupt_recognized(hw, &inta, &intb);
783
784 /*Shared IRQ or HW disappared */
de2e56ce
LF		 785 if (!inta || inta == 0xffff) {
786 ret = IRQ_NONE;
0c817338 787 goto done;
de2e56ce 788 }
0c817338
LF		 789
790 /*<1> beacon related */
791 if (inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK]) {
792 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
f30d7507 793 "beacon ok interrupt!\n");
0c817338
LF		 794 }
795
796 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TBDER])) {
797 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
f30d7507 798 "beacon err interrupt!\n");
0c817338
LF		 799 }
800
801 if (inta & rtlpriv->cfg->maps[RTL_IMR_BDOK]) {
f30d7507 802 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "beacon interrupt!\n");
0c817338
LF		 803 }
804
805 if (inta & rtlpriv->cfg->maps[RTL_IMR_BcnInt]) {
806 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
f30d7507 807 "prepare beacon for interrupt!\n");
0c817338
LF		 808 tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet);
809 }
810
811 /*<3> Tx related */
812 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TXFOVW]))
f30d7507 813 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "IMR_TXFOVW!\n");
0c817338
LF		 814
815 if (inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) {
816 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
f30d7507 817 "Manage ok interrupt!\n");
0c817338
LF		 818 _rtl_pci_tx_isr(hw, MGNT_QUEUE);
819 }
820
821 if (inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) {
822 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
f30d7507 823 "HIGH_QUEUE ok interrupt!\n");
0c817338
LF		 824 _rtl_pci_tx_isr(hw, HIGH_QUEUE);
825 }
826
827 if (inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) {
828 rtlpriv->link_info.num_tx_inperiod++;
829
830 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
f30d7507 831 "BK Tx OK interrupt!\n");
0c817338
LF		 832 _rtl_pci_tx_isr(hw, BK_QUEUE);
833 }
834
835 if (inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) {
836 rtlpriv->link_info.num_tx_inperiod++;
837
838 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
f30d7507 839 "BE TX OK interrupt!\n");
0c817338
LF		 840 _rtl_pci_tx_isr(hw, BE_QUEUE);
841 }
842
843 if (inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) {
844 rtlpriv->link_info.num_tx_inperiod++;
845
846 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
f30d7507 847 "VI TX OK interrupt!\n");
0c817338
LF		 848 _rtl_pci_tx_isr(hw, VI_QUEUE);
849 }
850
851 if (inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) {
852 rtlpriv->link_info.num_tx_inperiod++;
853
854 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
f30d7507 855 "Vo TX OK interrupt!\n");
0c817338
LF		 856 _rtl_pci_tx_isr(hw, VO_QUEUE);
857 }
858
c7cfe38e
C		 859 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) {
860 if (inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) {
861 rtlpriv->link_info.num_tx_inperiod++;
862
863 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
f30d7507 864 "CMD TX OK interrupt!\n");
c7cfe38e
C		 865 _rtl_pci_tx_isr(hw, TXCMD_QUEUE);
866 }
867 }
868
0c817338
LF		 869 /*<2> Rx related */
870 if (inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) {
f30d7507 871 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "Rx ok interrupt!\n");
c7cfe38e 872 _rtl_pci_rx_interrupt(hw);
0c817338
LF		 873 }
874
875 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) {
876 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
f30d7507 877 "rx descriptor unavailable!\n");
c7cfe38e 878 _rtl_pci_rx_interrupt(hw);
0c817338
LF		 879 }
880
881 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) {
f30d7507 882 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "rx overflow !\n");
c7cfe38e 883 _rtl_pci_rx_interrupt(hw);
0c817338
LF		 884 }
885
c7cfe38e
C		 886 if (rtlpriv->rtlhal.earlymode_enable)
887 tasklet_schedule(&rtlpriv->works.irq_tasklet);
888
0c817338
LF		 889done:
890 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
de2e56ce 891 return ret;
0c817338
LF		 892}
893
894static void _rtl_pci_irq_tasklet(struct ieee80211_hw *hw)
895{
c7cfe38e 896 _rtl_pci_tx_chk_waitq(hw);
0c817338
LF		 897}
898
899static void _rtl_pci_prepare_bcn_tasklet(struct ieee80211_hw *hw)
900{
901 struct rtl_priv *rtlpriv = rtl_priv(hw);
902 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
903 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
c7cfe38e 904 struct rtl8192_tx_ring *ring = NULL;
0c817338
LF		 905 struct ieee80211_hdr *hdr = NULL;
906 struct ieee80211_tx_info *info = NULL;
907 struct sk_buff *pskb = NULL;
908 struct rtl_tx_desc *pdesc = NULL;
c7cfe38e 909 struct rtl_tcb_desc tcb_desc;
0c817338
LF		 910 u8 temp_one = 1;
911
c7cfe38e 912 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
0c817338
LF		 913 ring = &rtlpci->tx_ring[BEACON_QUEUE];
914 pskb = __skb_dequeue(&ring->queue);
915 if (pskb)
916 kfree_skb(pskb);
917
918 /*NB: the beacon data buffer must be 32-bit aligned. */
919 pskb = ieee80211_beacon_get(hw, mac->vif);
920 if (pskb == NULL)
921 return;
c7cfe38e 922 hdr = rtl_get_hdr(pskb);
0c817338 923 info = IEEE80211_SKB_CB(pskb);
0c817338
LF		 924 pdesc = &ring->desc[0];
925 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *) pdesc,
c7cfe38e 926 info, pskb, BEACON_QUEUE, &tcb_desc);
0c817338
LF		 927
928 __skb_queue_tail(&ring->queue, pskb);
929
930 rtlpriv->cfg->ops->set_desc((u8 *) pdesc, true, HW_DESC_OWN,
931 (u8 *)&temp_one);
932
933 return;
934}
935
41affd52
SG		 936static void rtl_lps_leave_work_callback(struct work_struct *work)
937{
938 struct rtl_works *rtlworks =
939 container_of(work, struct rtl_works, lps_leave_work);
940 struct ieee80211_hw *hw = rtlworks->hw;
941
942 rtl_lps_leave(hw);
943}
944
0c817338
LF		 945static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw)
946{
947 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
948 u8 i;
949
950 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
951 rtlpci->txringcount[i] = RT_TXDESC_NUM;
952
953 /*
954 *we just alloc 2 desc for beacon queue,
955 *because we just need first desc in hw beacon.
956 */
957 rtlpci->txringcount[BEACON_QUEUE] = 2;
958
959 /*
960 *BE queue need more descriptor for performance
961 *consideration or, No more tx desc will happen,
962 *and may cause mac80211 mem leakage.
963 */
964 rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE;
965
966 rtlpci->rxbuffersize = 9100; /*2048/1024; */
967 rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT; /*64; */
968}
969
970static void _rtl_pci_init_struct(struct ieee80211_hw *hw,
971 struct pci_dev *pdev)
972{
973 struct rtl_priv *rtlpriv = rtl_priv(hw);
974 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
975 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
976 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0c817338
LF		 977
978 rtlpci->up_first_time = true;
979 rtlpci->being_init_adapter = false;
980
981 rtlhal->hw = hw;
982 rtlpci->pdev = pdev;
983
0c817338
LF		 984 /*Tx/Rx related var */
985 _rtl_pci_init_trx_var(hw);
986
c7cfe38e 987 /*IBSS*/ mac->beacon_interval = 100;
0c817338 988
c7cfe38e
C		 989 /*AMPDU*/
990 mac->min_space_cfg = 0;
0c817338
LF		 991 mac->max_mss_density = 0;
992 /*set sane AMPDU defaults */
993 mac->current_ampdu_density = 7;
994 mac->current_ampdu_factor = 3;
995
c7cfe38e
C		 996 /*QOS*/
997 rtlpci->acm_method = eAcmWay2_SW;
0c817338
LF		 998
999 /*task */
1000 tasklet_init(&rtlpriv->works.irq_tasklet,
1001 (void (*)(unsigned long))_rtl_pci_irq_tasklet,
1002 (unsigned long)hw);
1003 tasklet_init(&rtlpriv->works.irq_prepare_bcn_tasklet,
1004 (void (*)(unsigned long))_rtl_pci_prepare_bcn_tasklet,
1005 (unsigned long)hw);
41affd52 1006 INIT_WORK(&rtlpriv->works.lps_leave_work, rtl_lps_leave_work_callback);
0c817338
LF		 1007}
1008
1009static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw,
1010 unsigned int prio, unsigned int entries)
1011{
1012 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1013 struct rtl_priv *rtlpriv = rtl_priv(hw);
1014 struct rtl_tx_desc *ring;
1015 dma_addr_t dma;
1016 u32 nextdescaddress;
1017 int i;
1018
1019 ring = pci_alloc_consistent(rtlpci->pdev,
1020 sizeof(*ring) * entries, &dma);
1021
1022 if (!ring || (unsigned long)ring & 0xFF) {
1023 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 1024 "Cannot allocate TX ring (prio = %d)\n", prio);
0c817338
LF		 1025 return -ENOMEM;
1026 }
1027
1028 memset(ring, 0, sizeof(*ring) * entries);
1029 rtlpci->tx_ring[prio].desc = ring;
1030 rtlpci->tx_ring[prio].dma = dma;
1031 rtlpci->tx_ring[prio].idx = 0;
1032 rtlpci->tx_ring[prio].entries = entries;
1033 skb_queue_head_init(&rtlpci->tx_ring[prio].queue);
1034
f30d7507
JP		 1035 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "queue:%d, ring_addr:%p\n",
1036 prio, ring);
0c817338
LF		 1037
1038 for (i = 0; i < entries; i++) {
d3bb1429 1039 nextdescaddress = (u32) dma +
982d96bb 1040 ((i + 1) % entries) *
d3bb1429 1041 sizeof(*ring);
0c817338
LF		 1042
1043 rtlpriv->cfg->ops->set_desc((u8 *)&(ring[i]),
1044 true, HW_DESC_TX_NEXTDESC_ADDR,
1045 (u8 *)&nextdescaddress);
1046 }
1047
1048 return 0;
1049}
1050
1051static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw)
1052{
1053 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1054 struct rtl_priv *rtlpriv = rtl_priv(hw);
1055 struct rtl_rx_desc *entry = NULL;
1056 int i, rx_queue_idx;
1057 u8 tmp_one = 1;
1058
1059 /*
1060 *rx_queue_idx 0:RX_MPDU_QUEUE
1061 *rx_queue_idx 1:RX_CMD_QUEUE
1062 */
1063 for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1064 rx_queue_idx++) {
1065 rtlpci->rx_ring[rx_queue_idx].desc =
1066 pci_alloc_consistent(rtlpci->pdev,
1067 sizeof(*rtlpci->rx_ring[rx_queue_idx].
1068 desc) * rtlpci->rxringcount,
1069 &rtlpci->rx_ring[rx_queue_idx].dma);
1070
1071 if (!rtlpci->rx_ring[rx_queue_idx].desc ||
1072 (unsigned long)rtlpci->rx_ring[rx_queue_idx].desc & 0xFF) {
1073 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 1074 "Cannot allocate RX ring\n");
0c817338
LF		 1075 return -ENOMEM;
1076 }
1077
1078 memset(rtlpci->rx_ring[rx_queue_idx].desc, 0,
1079 sizeof(*rtlpci->rx_ring[rx_queue_idx].desc) *
1080 rtlpci->rxringcount);
1081
1082 rtlpci->rx_ring[rx_queue_idx].idx = 0;
1083
0019a2c9
LF		 1084 /* If amsdu_8k is disabled, set buffersize to 4096. This
1085 * change will reduce memory fragmentation.
1086 */
1087 if (rtlpci->rxbuffersize > 4096 &&
1088 rtlpriv->rtlhal.disable_amsdu_8k)
1089 rtlpci->rxbuffersize = 4096;
1090
0c817338
LF		 1091 for (i = 0; i < rtlpci->rxringcount; i++) {
1092 struct sk_buff *skb =
1093 dev_alloc_skb(rtlpci->rxbuffersize);
1094 u32 bufferaddress;
0c817338
LF		 1095 if (!skb)
1096 return 0;
bdc4bf65 1097 entry = &rtlpci->rx_ring[rx_queue_idx].desc[i];
0c817338
LF		 1098
1099 /*skb->dev = dev; */
1100
1101 rtlpci->rx_ring[rx_queue_idx].rx_buf[i] = skb;
1102
1103 /*
1104 *just set skb->cb to mapping addr
1105 *for pci_unmap_single use
1106 */
1107 *((dma_addr_t *) skb->cb) =
1108 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
1109 rtlpci->rxbuffersize,
1110 PCI_DMA_FROMDEVICE);
1111
d3bb1429 1112 bufferaddress = (*((dma_addr_t *)skb->cb));
0c817338
LF		 1113 rtlpriv->cfg->ops->set_desc((u8 *)entry, false,
1114 HW_DESC_RXBUFF_ADDR,
1115 (u8 *)&bufferaddress);
1116 rtlpriv->cfg->ops->set_desc((u8 *)entry, false,
1117 HW_DESC_RXPKT_LEN,
1118 (u8 *)&rtlpci->
1119 rxbuffersize);
1120 rtlpriv->cfg->ops->set_desc((u8 *) entry, false,
1121 HW_DESC_RXOWN,
1122 (u8 *)&tmp_one);
1123 }
1124
1125 rtlpriv->cfg->ops->set_desc((u8 *) entry, false,
1126 HW_DESC_RXERO, (u8 *)&tmp_one);
1127 }
1128 return 0;
1129}
1130
1131static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw,
1132 unsigned int prio)
1133{
1134 struct rtl_priv *rtlpriv = rtl_priv(hw);
1135 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1136 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
1137
1138 while (skb_queue_len(&ring->queue)) {
1139 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
1140 struct sk_buff *skb = __skb_dequeue(&ring->queue);
1141
1142 pci_unmap_single(rtlpci->pdev,
d3bb1429 1143 rtlpriv->cfg->
0c817338 1144 ops->get_desc((u8 *) entry, true,
d3bb1429 1145 HW_DESC_TXBUFF_ADDR),
0c817338
LF		 1146 skb->len, PCI_DMA_TODEVICE);
1147 kfree_skb(skb);
1148 ring->idx = (ring->idx + 1) % ring->entries;
1149 }
1150
1151 pci_free_consistent(rtlpci->pdev,
1152 sizeof(*ring->desc) * ring->entries,
1153 ring->desc, ring->dma);
1154 ring->desc = NULL;
1155}
1156
1157static void _rtl_pci_free_rx_ring(struct rtl_pci *rtlpci)
1158{
1159 int i, rx_queue_idx;
1160
1161 /*rx_queue_idx 0:RX_MPDU_QUEUE */
1162 /*rx_queue_idx 1:RX_CMD_QUEUE */
1163 for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1164 rx_queue_idx++) {
1165 for (i = 0; i < rtlpci->rxringcount; i++) {
1166 struct sk_buff *skb =
1167 rtlpci->rx_ring[rx_queue_idx].rx_buf[i];
1168 if (!skb)
1169 continue;
1170
1171 pci_unmap_single(rtlpci->pdev,
1172 *((dma_addr_t *) skb->cb),
1173 rtlpci->rxbuffersize,
1174 PCI_DMA_FROMDEVICE);
1175 kfree_skb(skb);
1176 }
1177
1178 pci_free_consistent(rtlpci->pdev,
1179 sizeof(*rtlpci->rx_ring[rx_queue_idx].
1180 desc) * rtlpci->rxringcount,
1181 rtlpci->rx_ring[rx_queue_idx].desc,
1182 rtlpci->rx_ring[rx_queue_idx].dma);
1183 rtlpci->rx_ring[rx_queue_idx].desc = NULL;
1184 }
1185}
1186
1187static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw)
1188{
1189 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1190 int ret;
1191 int i;
1192
1193 ret = _rtl_pci_init_rx_ring(hw);
1194 if (ret)
1195 return ret;
1196
1197 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1198 ret = _rtl_pci_init_tx_ring(hw, i,
1199 rtlpci->txringcount[i]);
1200 if (ret)
1201 goto err_free_rings;
1202 }
1203
1204 return 0;
1205
1206err_free_rings:
1207 _rtl_pci_free_rx_ring(rtlpci);
1208
1209 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1210 if (rtlpci->tx_ring[i].desc)
1211 _rtl_pci_free_tx_ring(hw, i);
1212
1213 return 1;
1214}
1215
1216static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw)
1217{
1218 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1219 u32 i;
1220
1221 /*free rx rings */
1222 _rtl_pci_free_rx_ring(rtlpci);
1223
1224 /*free tx rings */
1225 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1226 _rtl_pci_free_tx_ring(hw, i);
1227
1228 return 0;
1229}
1230
1231int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw)
1232{
1233 struct rtl_priv *rtlpriv = rtl_priv(hw);
1234 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1235 int i, rx_queue_idx;
1236 unsigned long flags;
1237 u8 tmp_one = 1;
1238
1239 /*rx_queue_idx 0:RX_MPDU_QUEUE */
1240 /*rx_queue_idx 1:RX_CMD_QUEUE */
1241 for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1242 rx_queue_idx++) {
1243 /*
1244 *force the rx_ring[RX_MPDU_QUEUE/
1245 *RX_CMD_QUEUE].idx to the first one
1246 */
1247 if (rtlpci->rx_ring[rx_queue_idx].desc) {
1248 struct rtl_rx_desc *entry = NULL;
1249
1250 for (i = 0; i < rtlpci->rxringcount; i++) {
1251 entry = &rtlpci->rx_ring[rx_queue_idx].desc[i];
1252 rtlpriv->cfg->ops->set_desc((u8 *) entry,
1253 false,
1254 HW_DESC_RXOWN,
1255 (u8 *)&tmp_one);
1256 }
1257 rtlpci->rx_ring[rx_queue_idx].idx = 0;
1258 }
1259 }
1260
1261 /*
1262 *after reset, release previous pending packet,
1263 *and force the tx idx to the first one
1264 */
1265 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1266 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1267 if (rtlpci->tx_ring[i].desc) {
1268 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i];
1269
1270 while (skb_queue_len(&ring->queue)) {
1271 struct rtl_tx_desc *entry =
1272 &ring->desc[ring->idx];
1273 struct sk_buff *skb =
1274 __skb_dequeue(&ring->queue);
1275
1276 pci_unmap_single(rtlpci->pdev,
d3bb1429 1277 rtlpriv->cfg->ops->
0c817338
LF		 1278 get_desc((u8 *)
1279 entry,
1280 true,
d3bb1429 1281 HW_DESC_TXBUFF_ADDR),
0c817338
LF		 1282 skb->len, PCI_DMA_TODEVICE);
1283 kfree_skb(skb);
1284 ring->idx = (ring->idx + 1) % ring->entries;
1285 }
1286 ring->idx = 0;
1287 }
1288 }
1289
1290 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1291
1292 return 0;
1293}
1294
c7cfe38e
C		 1295static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw,
1296 struct sk_buff *skb)
0c817338 1297{
c7cfe38e
C		 1298 struct rtl_priv *rtlpriv = rtl_priv(hw);
1299 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1300 struct ieee80211_sta *sta = info->control.sta;
1301 struct rtl_sta_info *sta_entry = NULL;
1302 u8 tid = rtl_get_tid(skb);
1303
1304 if (!sta)
1305 return false;
1306 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1307
1308 if (!rtlpriv->rtlhal.earlymode_enable)
1309 return false;
1310 if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL)
1311 return false;
1312 if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE)
1313 return false;
1314 if (tid > 7)
1315 return false;
1316
1317 /* maybe every tid should be checked */
1318 if (!rtlpriv->link_info.higher_busytxtraffic[tid])
1319 return false;
1320
1321 spin_lock_bh(&rtlpriv->locks.waitq_lock);
1322 skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb);
1323 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
0c817338 1324
c7cfe38e 1325 return true;
0c817338
LF		 1326}
1327
d3bb1429 1328static int rtl_pci_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
c7cfe38e 1329 struct rtl_tcb_desc *ptcb_desc)
0c817338
LF		 1330{
1331 struct rtl_priv *rtlpriv = rtl_priv(hw);
c7cfe38e 1332 struct rtl_sta_info *sta_entry = NULL;
0c817338 1333 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
c7cfe38e 1334 struct ieee80211_sta *sta = info->control.sta;
0c817338
LF		 1335 struct rtl8192_tx_ring *ring;
1336 struct rtl_tx_desc *pdesc;
1337 u8 idx;
c7cfe38e 1338 u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb);
0c817338 1339 unsigned long flags;
c7cfe38e
C		 1340 struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
1341 __le16 fc = rtl_get_fc(skb);
0c817338
LF		 1342 u8 *pda_addr = hdr->addr1;
1343 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1344 /*ssn */
0c817338
LF		 1345 u8 tid = 0;
1346 u16 seq_number = 0;
1347 u8 own;
1348 u8 temp_one = 1;
1349
c7cfe38e 1350 if (ieee80211_is_auth(fc)) {
f30d7507 1351 RT_TRACE(rtlpriv, COMP_SEND, DBG_DMESG, "MAC80211_LINKING\n");
c7cfe38e
C		 1352 rtl_ips_nic_on(hw);
1353 }
1354
1355 if (rtlpriv->psc.sw_ps_enabled) {
1356 if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) &&
1357 !ieee80211_has_pm(fc))
1358 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1359 }
0c817338 1360
c7cfe38e 1361 rtl_action_proc(hw, skb, true);
0c817338
LF		 1362
1363 if (is_multicast_ether_addr(pda_addr))
1364 rtlpriv->stats.txbytesmulticast += skb->len;
1365 else if (is_broadcast_ether_addr(pda_addr))
1366 rtlpriv->stats.txbytesbroadcast += skb->len;
1367 else
1368 rtlpriv->stats.txbytesunicast += skb->len;
1369
1370 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
0c817338
LF		 1371 ring = &rtlpci->tx_ring[hw_queue];
1372 if (hw_queue != BEACON_QUEUE)
1373 idx = (ring->idx + skb_queue_len(&ring->queue)) %
1374 ring->entries;
1375 else
1376 idx = 0;
1377
1378 pdesc = &ring->desc[idx];
1379 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
1380 true, HW_DESC_OWN);
1381
1382 if ((own == 1) && (hw_queue != BEACON_QUEUE)) {
1383 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
f30d7507
JP		 1384 "No more TX desc@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%d\n",
1385 hw_queue, ring->idx, idx,
1386 skb_queue_len(&ring->queue));
0c817338
LF		 1387
1388 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1389 return skb->len;
1390 }
1391
0c817338 1392 if (ieee80211_is_data_qos(fc)) {
c7cfe38e
C		 1393 tid = rtl_get_tid(skb);
1394 if (sta) {
1395 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1396 seq_number = (le16_to_cpu(hdr->seq_ctrl) &
1397 IEEE80211_SCTL_SEQ) >> 4;
1398 seq_number += 1;
1399
1400 if (!ieee80211_has_morefrags(hdr->frame_control))
1401 sta_entry->tids[tid].seq_number = seq_number;
1402 }
0c817338
LF		 1403 }
1404
1405 if (ieee80211_is_data(fc))
1406 rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX);
1407
c7cfe38e
C		 1408 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
1409 info, skb, hw_queue, ptcb_desc);
0c817338
LF		 1410
1411 __skb_queue_tail(&ring->queue, skb);
1412
c7cfe38e 1413 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, true,
0c817338
LF		 1414 HW_DESC_OWN, (u8 *)&temp_one);
1415
0c817338
LF		 1416
1417 if ((ring->entries - skb_queue_len(&ring->queue)) < 2 &&
1418 hw_queue != BEACON_QUEUE) {
1419
1420 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
f30d7507
JP		 1421 "less desc left, stop skb_queue@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%d\n",
1422 hw_queue, ring->idx, idx,
1423 skb_queue_len(&ring->queue));
0c817338
LF		 1424
1425 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
1426 }
1427
1428 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1429
1430 rtlpriv->cfg->ops->tx_polling(hw, hw_queue);
1431
1432 return 0;
1433}
1434
c7cfe38e
C		 1435static void rtl_pci_flush(struct ieee80211_hw *hw, bool drop)
1436{
1437 struct rtl_priv *rtlpriv = rtl_priv(hw);
1438 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1439 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1440 u16 i = 0;
1441 int queue_id;
1442 struct rtl8192_tx_ring *ring;
1443
1444 for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) {
1445 u32 queue_len;
1446 ring = &pcipriv->dev.tx_ring[queue_id];
1447 queue_len = skb_queue_len(&ring->queue);
1448 if (queue_len == 0 || queue_id == BEACON_QUEUE ||
1449 queue_id == TXCMD_QUEUE) {
1450 queue_id--;
1451 continue;
1452 } else {
1453 msleep(20);
1454 i++;
1455 }
1456
1457 /* we just wait 1s for all queues */
1458 if (rtlpriv->psc.rfpwr_state == ERFOFF ||
1459 is_hal_stop(rtlhal) || i >= 200)
1460 return;
1461 }
1462}
1463
d3bb1429 1464static void rtl_pci_deinit(struct ieee80211_hw *hw)
0c817338
LF		 1465{
1466 struct rtl_priv *rtlpriv = rtl_priv(hw);
1467 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1468
1469 _rtl_pci_deinit_trx_ring(hw);
1470
1471 synchronize_irq(rtlpci->pdev->irq);
1472 tasklet_kill(&rtlpriv->works.irq_tasklet);
41affd52 1473 cancel_work_sync(&rtlpriv->works.lps_leave_work);
0c817338
LF		 1474
1475 flush_workqueue(rtlpriv->works.rtl_wq);
1476 destroy_workqueue(rtlpriv->works.rtl_wq);
1477
1478}
1479
d3bb1429 1480static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev)
0c817338
LF		 1481{
1482 struct rtl_priv *rtlpriv = rtl_priv(hw);
1483 int err;
1484
1485 _rtl_pci_init_struct(hw, pdev);
1486
1487 err = _rtl_pci_init_trx_ring(hw);
1488 if (err) {
1489 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 1490 "tx ring initialization failed\n");
0c817338
LF		 1491 return err;
1492 }
1493
1494 return 1;
1495}
1496
d3bb1429 1497static int rtl_pci_start(struct ieee80211_hw *hw)
0c817338
LF		 1498{
1499 struct rtl_priv *rtlpriv = rtl_priv(hw);
1500 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1501 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1502 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1503
1504 int err;
1505
1506 rtl_pci_reset_trx_ring(hw);
1507
1508 rtlpci->driver_is_goingto_unload = false;
1509 err = rtlpriv->cfg->ops->hw_init(hw);
1510 if (err) {
1511 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
f30d7507 1512 "Failed to config hardware!\n");
0c817338
LF		 1513 return err;
1514 }
1515
1516 rtlpriv->cfg->ops->enable_interrupt(hw);
f30d7507 1517 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "enable_interrupt OK\n");
0c817338
LF		 1518
1519 rtl_init_rx_config(hw);
1520
fb914ebf 1521 /*should be after adapter start and interrupt enable. */
0c817338
LF		 1522 set_hal_start(rtlhal);
1523
1524 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1525
1526 rtlpci->up_first_time = false;
1527
f30d7507 1528 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "OK\n");
0c817338
LF		 1529 return 0;
1530}
1531
d3bb1429 1532static void rtl_pci_stop(struct ieee80211_hw *hw)
0c817338
LF		 1533{
1534 struct rtl_priv *rtlpriv = rtl_priv(hw);
1535 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1536 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1537 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1538 unsigned long flags;
1539 u8 RFInProgressTimeOut = 0;
1540
1541 /*
fb914ebf 1542 *should be before disable interrupt&adapter
0c817338
LF		 1543 *and will do it immediately.
1544 */
1545 set_hal_stop(rtlhal);
1546
1547 rtlpriv->cfg->ops->disable_interrupt(hw);
41affd52 1548 cancel_work_sync(&rtlpriv->works.lps_leave_work);
0c817338
LF		 1549
1550 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1551 while (ppsc->rfchange_inprogress) {
1552 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1553 if (RFInProgressTimeOut > 100) {
1554 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1555 break;
1556 }
1557 mdelay(1);
1558 RFInProgressTimeOut++;
1559 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1560 }
1561 ppsc->rfchange_inprogress = true;
1562 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1563
1564 rtlpci->driver_is_goingto_unload = true;
1565 rtlpriv->cfg->ops->hw_disable(hw);
b0302aba
LF		 1566 /* some things are not needed if firmware not available */
1567 if (!rtlpriv->max_fw_size)
1568 return;
0c817338
LF		 1569 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1570
1571 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1572 ppsc->rfchange_inprogress = false;
1573 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1574
1575 rtl_pci_enable_aspm(hw);
1576}
1577
1578static bool _rtl_pci_find_adapter(struct pci_dev *pdev,
1579 struct ieee80211_hw *hw)
1580{
1581 struct rtl_priv *rtlpriv = rtl_priv(hw);
1582 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1583 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1584 struct pci_dev *bridge_pdev = pdev->bus->self;
1585 u16 venderid;
1586 u16 deviceid;
c7cfe38e 1587 u8 revisionid;
0c817338
LF		 1588 u16 irqline;
1589 u8 tmp;
1590
fc7707a4 1591 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
0c817338
LF		 1592 venderid = pdev->vendor;
1593 deviceid = pdev->device;
c7cfe38e 1594 pci_read_config_byte(pdev, 0x8, &revisionid);
0c817338
LF		 1595 pci_read_config_word(pdev, 0x3C, &irqline);
1596
fa7ccfb1
LF		 1597 /* PCI ID 0x10ec:0x8192 occurs for both RTL8192E, which uses
1598 * r8192e_pci, and RTL8192SE, which uses this driver. If the
1599 * revision ID is RTL_PCI_REVISION_ID_8192PCIE (0x01), then
1600 * the correct driver is r8192e_pci, thus this routine should
1601 * return false.
1602 */
1603 if (deviceid == RTL_PCI_8192SE_DID &&
1604 revisionid == RTL_PCI_REVISION_ID_8192PCIE)
1605 return false;
1606
0c817338
LF		 1607 if (deviceid == RTL_PCI_8192_DID ||
1608 deviceid == RTL_PCI_0044_DID ||
1609 deviceid == RTL_PCI_0047_DID ||
1610 deviceid == RTL_PCI_8192SE_DID ||
1611 deviceid == RTL_PCI_8174_DID ||
1612 deviceid == RTL_PCI_8173_DID ||
1613 deviceid == RTL_PCI_8172_DID ||
1614 deviceid == RTL_PCI_8171_DID) {
c7cfe38e 1615 switch (revisionid) {
0c817338
LF		 1616 case RTL_PCI_REVISION_ID_8192PCIE:
1617 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
f30d7507
JP		 1618 "8192 PCI-E is found - vid/did=%x/%x\n",
1619 venderid, deviceid);
0c817338
LF		 1620 rtlhal->hw_type = HARDWARE_TYPE_RTL8192E;
1621 break;
1622 case RTL_PCI_REVISION_ID_8192SE:
1623 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
f30d7507
JP		 1624 "8192SE is found - vid/did=%x/%x\n",
1625 venderid, deviceid);
0c817338
LF		 1626 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1627 break;
1628 default:
1629 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
f30d7507
JP		 1630 "Err: Unknown device - vid/did=%x/%x\n",
1631 venderid, deviceid);
0c817338
LF		 1632 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1633 break;
1634
1635 }
1636 } else if (deviceid == RTL_PCI_8192CET_DID ||
1637 deviceid == RTL_PCI_8192CE_DID ||
1638 deviceid == RTL_PCI_8191CE_DID ||
1639 deviceid == RTL_PCI_8188CE_DID) {
1640 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE;
1641 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
f30d7507
JP		 1642 "8192C PCI-E is found - vid/did=%x/%x\n",
1643 venderid, deviceid);
c7cfe38e
C		 1644 } else if (deviceid == RTL_PCI_8192DE_DID ||
1645 deviceid == RTL_PCI_8192DE_DID2) {
1646 rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE;
1647 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
f30d7507
JP		 1648 "8192D PCI-E is found - vid/did=%x/%x\n",
1649 venderid, deviceid);
0c817338
LF		 1650 } else {
1651 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
f30d7507
JP		 1652 "Err: Unknown device - vid/did=%x/%x\n",
1653 venderid, deviceid);
0c817338
LF		 1654
1655 rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE;
1656 }
1657
c7cfe38e
C		 1658 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) {
1659 if (revisionid == 0 || revisionid == 1) {
1660 if (revisionid == 0) {
f30d7507
JP		 1661 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1662 "Find 92DE MAC0\n");
c7cfe38e
C		 1663 rtlhal->interfaceindex = 0;
1664 } else if (revisionid == 1) {
1665 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
f30d7507 1666 "Find 92DE MAC1\n");
c7cfe38e
C		 1667 rtlhal->interfaceindex = 1;
1668 }
1669 } else {
1670 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
f30d7507
JP		 1671 "Unknown device - VendorID/DeviceID=%x/%x, Revision=%x\n",
1672 venderid, deviceid, revisionid);
c7cfe38e
C		 1673 rtlhal->interfaceindex = 0;
1674 }
1675 }
0c817338
LF		 1676 /*find bus info */
1677 pcipriv->ndis_adapter.busnumber = pdev->bus->number;
1678 pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn);
1679 pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn);
1680
b6b67df3
LF		 1681 if (bridge_pdev) {
1682 /*find bridge info if available */
1683 pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor;
1684 for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) {
1685 if (bridge_pdev->vendor == pcibridge_vendors[tmp]) {
1686 pcipriv->ndis_adapter.pcibridge_vendor = tmp;
1687 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
f30d7507
JP		 1688 "Pci Bridge Vendor is found index: %d\n",
1689 tmp);
b6b67df3
LF		 1690 break;
1691 }
0c817338
LF		 1692 }
1693 }
1694
1695 if (pcipriv->ndis_adapter.pcibridge_vendor !=
1696 PCI_BRIDGE_VENDOR_UNKNOWN) {
1697 pcipriv->ndis_adapter.pcibridge_busnum =
1698 bridge_pdev->bus->number;
1699 pcipriv->ndis_adapter.pcibridge_devnum =
1700 PCI_SLOT(bridge_pdev->devfn);
1701 pcipriv->ndis_adapter.pcibridge_funcnum =
1702 PCI_FUNC(bridge_pdev->devfn);
c7cfe38e
C		 1703 pcipriv->ndis_adapter.pcibridge_pciehdr_offset =
1704 pci_pcie_cap(bridge_pdev);
0c817338
LF		 1705 pcipriv->ndis_adapter.num4bytes =
1706 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10) / 4;
1707
1708 rtl_pci_get_linkcontrol_field(hw);
1709
1710 if (pcipriv->ndis_adapter.pcibridge_vendor ==
1711 PCI_BRIDGE_VENDOR_AMD) {
1712 pcipriv->ndis_adapter.amd_l1_patch =
1713 rtl_pci_get_amd_l1_patch(hw);
1714 }
1715 }
1716
1717 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
f30d7507
JP		 1718 "pcidev busnumber:devnumber:funcnumber:vendor:link_ctl %d:%d:%d:%x:%x\n",
1719 pcipriv->ndis_adapter.busnumber,
1720 pcipriv->ndis_adapter.devnumber,
1721 pcipriv->ndis_adapter.funcnumber,
1722 pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg);
0c817338
LF		 1723
1724 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
f30d7507
JP		 1725 "pci_bridge busnumber:devnumber:funcnumber:vendor:pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n",
1726 pcipriv->ndis_adapter.pcibridge_busnum,
1727 pcipriv->ndis_adapter.pcibridge_devnum,
1728 pcipriv->ndis_adapter.pcibridge_funcnum,
1729 pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor],
1730 pcipriv->ndis_adapter.pcibridge_pciehdr_offset,
1731 pcipriv->ndis_adapter.pcibridge_linkctrlreg,
1732 pcipriv->ndis_adapter.amd_l1_patch);
0c817338
LF		 1733
1734 rtl_pci_parse_configuration(pdev, hw);
1735
1736 return true;
1737}
1738
1739int __devinit rtl_pci_probe(struct pci_dev *pdev,
1740 const struct pci_device_id *id)
1741{
1742 struct ieee80211_hw *hw = NULL;
1743
1744 struct rtl_priv *rtlpriv = NULL;
1745 struct rtl_pci_priv *pcipriv = NULL;
1746 struct rtl_pci *rtlpci;
1747 unsigned long pmem_start, pmem_len, pmem_flags;
1748 int err;
1749
1750 err = pci_enable_device(pdev);
1751 if (err) {
9d833ed7
JP		 1752 RT_ASSERT(false, "%s : Cannot enable new PCI device\n",
1753 pci_name(pdev));
0c817338
LF		 1754 return err;
1755 }
1756
1757 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
1758 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
9d833ed7
JP		 1759 RT_ASSERT(false,
1760 "Unable to obtain 32bit DMA for consistent allocations\n");
3d86b930
TG		 1761 err = -ENOMEM;
1762 goto fail1;
0c817338
LF		 1763 }
1764 }
1765
1766 pci_set_master(pdev);
1767
1768 hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) +
1769 sizeof(struct rtl_priv), &rtl_ops);
1770 if (!hw) {
1771 RT_ASSERT(false,
9d833ed7 1772 "%s : ieee80211 alloc failed\n", pci_name(pdev));
0c817338
LF		 1773 err = -ENOMEM;
1774 goto fail1;
1775 }
1776
1777 SET_IEEE80211_DEV(hw, &pdev->dev);
1778 pci_set_drvdata(pdev, hw);
1779
1780 rtlpriv = hw->priv;
1781 pcipriv = (void *)rtlpriv->priv;
1782 pcipriv->dev.pdev = pdev;
b0302aba 1783 init_completion(&rtlpriv->firmware_loading_complete);
0c817338 1784
c7cfe38e
C		 1785 /* init cfg & intf_ops */
1786 rtlpriv->rtlhal.interface = INTF_PCI;
1787 rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data);
1788 rtlpriv->intf_ops = &rtl_pci_ops;
1789
0c817338
LF		 1790 /*
1791 *init dbgp flags before all
1792 *other functions, because we will
1793 *use it in other funtions like
1794 *RT_TRACE/RT_PRINT/RTL_PRINT_DATA
1795 *you can not use these macro
1796 *before this
1797 */
1798 rtl_dbgp_flag_init(hw);
1799
1800 /* MEM map */
1801 err = pci_request_regions(pdev, KBUILD_MODNAME);
1802 if (err) {
9d833ed7 1803 RT_ASSERT(false, "Can't obtain PCI resources\n");
3d86b930 1804 goto fail1;
0c817338
LF		 1805 }
1806
c7cfe38e
C		 1807 pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id);
1808 pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id);
1809 pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id);
0c817338
LF		 1810
1811 /*shared mem start */
1812 rtlpriv->io.pci_mem_start =
c7cfe38e
C		 1813 (unsigned long)pci_iomap(pdev,
1814 rtlpriv->cfg->bar_id, pmem_len);
0c817338 1815 if (rtlpriv->io.pci_mem_start == 0) {
9d833ed7 1816 RT_ASSERT(false, "Can't map PCI mem\n");
3d86b930 1817 err = -ENOMEM;
0c817338
LF		 1818 goto fail2;
1819 }
1820
1821 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
f30d7507
JP		 1822 "mem mapped space: start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n",
1823 pmem_start, pmem_len, pmem_flags,
1824 rtlpriv->io.pci_mem_start);
0c817338
LF		 1825
1826 /* Disable Clk Request */
1827 pci_write_config_byte(pdev, 0x81, 0);
1828 /* leave D3 mode */
1829 pci_write_config_byte(pdev, 0x44, 0);
1830 pci_write_config_byte(pdev, 0x04, 0x06);
1831 pci_write_config_byte(pdev, 0x04, 0x07);
1832
0c817338 1833 /* find adapter */
3d86b930
TG		 1834 if (!_rtl_pci_find_adapter(pdev, hw)) {
1835 err = -ENODEV;
fa7ccfb1 1836 goto fail3;
3d86b930 1837 }
0c817338
LF		 1838
1839 /* Init IO handler */
1840 _rtl_pci_io_handler_init(&pdev->dev, hw);
1841
1842 /*like read eeprom and so on */
1843 rtlpriv->cfg->ops->read_eeprom_info(hw);
1844
1845 if (rtlpriv->cfg->ops->init_sw_vars(hw)) {
f30d7507 1846 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Can't init_sw_vars\n");
3d86b930 1847 err = -ENODEV;
0c817338
LF		 1848 goto fail3;
1849 }
1850
1851 rtlpriv->cfg->ops->init_sw_leds(hw);
1852
1853 /*aspm */
1854 rtl_pci_init_aspm(hw);
1855
1856 /* Init mac80211 sw */
1857 err = rtl_init_core(hw);
1858 if (err) {
1859 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 1860 "Can't allocate sw for mac80211\n");
0c817338
LF		 1861 goto fail3;
1862 }
1863
1864 /* Init PCI sw */
1865 err = !rtl_pci_init(hw, pdev);
1866 if (err) {
f30d7507 1867 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Failed to init PCI\n");
0c817338
LF		 1868 goto fail3;
1869 }
1870
0c817338
LF		 1871 err = sysfs_create_group(&pdev->dev.kobj, &rtl_attribute_group);
1872 if (err) {
1873 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 1874 "failed to create sysfs device attributes\n");
0c817338
LF		 1875 goto fail3;
1876 }
1877
0c817338
LF		 1878 rtlpci = rtl_pcidev(pcipriv);
1879 err = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
1880 IRQF_SHARED, KBUILD_MODNAME, hw);
1881 if (err) {
1882 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
f30d7507
JP		 1883 "%s: failed to register IRQ handler\n",
1884 wiphy_name(hw->wiphy));
0c817338 1885 goto fail3;
0c817338 1886 }
b0302aba 1887 rtlpci->irq_alloc = 1;
0c817338 1888
0c817338
LF		 1889 return 0;
1890
1891fail3:
0c817338
LF		 1892 rtl_deinit_core(hw);
1893 _rtl_pci_io_handler_release(hw);
0c817338
LF		 1894
1895 if (rtlpriv->io.pci_mem_start != 0)
62e63975 1896 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
0c817338
LF		 1897
1898fail2:
1899 pci_release_regions(pdev);
b0302aba 1900 complete(&rtlpriv->firmware_loading_complete);
0c817338
LF		 1901
1902fail1:
3d86b930
TG		 1903 if (hw)
1904 ieee80211_free_hw(hw);
1905 pci_set_drvdata(pdev, NULL);
0c817338
LF		 1906 pci_disable_device(pdev);
1907
3d86b930 1908 return err;
0c817338
LF		 1909
1910}
1911EXPORT_SYMBOL(rtl_pci_probe);
1912
1913void rtl_pci_disconnect(struct pci_dev *pdev)
1914{
1915 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
1916 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1917 struct rtl_priv *rtlpriv = rtl_priv(hw);
1918 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
1919 struct rtl_mac *rtlmac = rtl_mac(rtlpriv);
1920
b0302aba
LF		 1921 /* just in case driver is removed before firmware callback */
1922 wait_for_completion(&rtlpriv->firmware_loading_complete);
0c817338
LF		 1923 clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
1924
1925 sysfs_remove_group(&pdev->dev.kobj, &rtl_attribute_group);
1926
1927 /*ieee80211_unregister_hw will call ops_stop */
1928 if (rtlmac->mac80211_registered == 1) {
1929 ieee80211_unregister_hw(hw);
1930 rtlmac->mac80211_registered = 0;
1931 } else {
1932 rtl_deinit_deferred_work(hw);
1933 rtlpriv->intf_ops->adapter_stop(hw);
1934 }
1935
1936 /*deinit rfkill */
1937 rtl_deinit_rfkill(hw);
1938
1939 rtl_pci_deinit(hw);
1940 rtl_deinit_core(hw);
0c817338
LF		 1941 _rtl_pci_io_handler_release(hw);
1942 rtlpriv->cfg->ops->deinit_sw_vars(hw);
1943
1944 if (rtlpci->irq_alloc) {
1945 free_irq(rtlpci->pdev->irq, hw);
1946 rtlpci->irq_alloc = 0;
1947 }
1948
1949 if (rtlpriv->io.pci_mem_start != 0) {
62e63975 1950 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
0c817338
LF		 1951 pci_release_regions(pdev);
1952 }
1953
1954 pci_disable_device(pdev);
c7cfe38e
C		 1955
1956 rtl_pci_disable_aspm(hw);
1957
0c817338
LF		 1958 pci_set_drvdata(pdev, NULL);
1959
1960 ieee80211_free_hw(hw);
1961}
1962EXPORT_SYMBOL(rtl_pci_disconnect);
1963
1964/***************************************
1965kernel pci power state define:
1966PCI_D0 ((pci_power_t __force) 0)
1967PCI_D1 ((pci_power_t __force) 1)
1968PCI_D2 ((pci_power_t __force) 2)
1969PCI_D3hot ((pci_power_t __force) 3)
1970PCI_D3cold ((pci_power_t __force) 4)
1971PCI_UNKNOWN ((pci_power_t __force) 5)
1972
1973This function is called when system
1974goes into suspend state mac80211 will
1975call rtl_mac_stop() from the mac80211
1976suspend function first, So there is
1977no need to call hw_disable here.
1978****************************************/
603be388 1979int rtl_pci_suspend(struct device *dev)
0c817338 1980{
603be388 1981 struct pci_dev *pdev = to_pci_dev(dev);
c7cfe38e
C		 1982 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
1983 struct rtl_priv *rtlpriv = rtl_priv(hw);
1984
1985 rtlpriv->cfg->ops->hw_suspend(hw);
1986 rtl_deinit_rfkill(hw);
1987
0c817338
LF		 1988 return 0;
1989}
1990EXPORT_SYMBOL(rtl_pci_suspend);
1991
603be388 1992int rtl_pci_resume(struct device *dev)
0c817338 1993{
603be388 1994 struct pci_dev *pdev = to_pci_dev(dev);
c7cfe38e
C		 1995 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
1996 struct rtl_priv *rtlpriv = rtl_priv(hw);
0c817338 1997
c7cfe38e
C		 1998 rtlpriv->cfg->ops->hw_resume(hw);
1999 rtl_init_rfkill(hw);
0c817338
LF		 2000 return 0;
2001}
2002EXPORT_SYMBOL(rtl_pci_resume);
2003
2004struct rtl_intf_ops rtl_pci_ops = {
c7cfe38e 2005 .read_efuse_byte = read_efuse_byte,
0c817338
LF		 2006 .adapter_start = rtl_pci_start,
2007 .adapter_stop = rtl_pci_stop,
2008 .adapter_tx = rtl_pci_tx,
c7cfe38e 2009 .flush = rtl_pci_flush,
0c817338 2010 .reset_trx_ring = rtl_pci_reset_trx_ring,
c7cfe38e 2011 .waitq_insert = rtl_pci_tx_chk_waitq_insert,
0c817338
LF		 2012
2013 .disable_aspm = rtl_pci_disable_aspm,
2014 .enable_aspm = rtl_pci_enable_aspm,
2015};
Linux kernel - Deliverables
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