[deliverable/linux.git] / drivers / net / wireless / rtlwifi / rtl8192ce / rf.c

/******************************************************************************
 *
 * Copyright(c) 2009-2010  Realtek Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
 *
 * The full GNU General Public License is included in this distribution in the
 * file called LICENSE.
 *
 * Contact Information:
 * wlanfae <wlanfae@realtek.com>
 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
 * Hsinchu 300, Taiwan.
 *
 * Larry Finger <Larry.Finger@lwfinger.net>
 *
 *****************************************************************************/

#include "../wifi.h"
#include "reg.h"
#include "def.h"
#include "phy.h"
#include "rf.h"
#include "dm.h"

static bool _rtl92c_phy_rf6052_config_parafile(struct ieee80211_hw *hw);

void rtl92c_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth)
{
	struct rtl_priv *rtlpriv = rtl_priv(hw);
	struct rtl_phy *rtlphy = &(rtlpriv->phy);

	switch (bandwidth) {
	case HT_CHANNEL_WIDTH_20:
		rtlphy->rfreg_chnlval[0] = ((rtlphy->rfreg_chnlval[0] &
					     0xfffff3ff) | 0x0400);
		rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
			      rtlphy->rfreg_chnlval[0]);
		break;
	case HT_CHANNEL_WIDTH_20_40:
		rtlphy->rfreg_chnlval[0] = ((rtlphy->rfreg_chnlval[0] &
					     0xfffff3ff));
		rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
			      rtlphy->rfreg_chnlval[0]);
		break;
	default:
		RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
			 ("unknown bandwidth: %#X\n", bandwidth));
		break;
	}
}

void rtl92ce_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
				       u8 *ppowerlevel)
{
	struct rtl_priv *rtlpriv = rtl_priv(hw);
	struct rtl_phy *rtlphy = &(rtlpriv->phy);
	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
	u32 tx_agc[2] = {0, 0}, tmpval;
	bool turbo_scanoff = false;
	u8 idx1, idx2;
	u8 *ptr;

	if (rtlefuse->eeprom_regulatory != 0)
		turbo_scanoff = true;

	if (mac->act_scanning == true) {
		tx_agc[RF90_PATH_A] = 0x3f3f3f3f;
		tx_agc[RF90_PATH_B] = 0x3f3f3f3f;

		if (turbo_scanoff) {
			for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
				tx_agc[idx1] = ppowerlevel[idx1] |
				    (ppowerlevel[idx1] << 8) |
				    (ppowerlevel[idx1] << 16) |
				    (ppowerlevel[idx1] << 24);
			}
		}
	} else {
		for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
			tx_agc[idx1] = ppowerlevel[idx1] |
			    (ppowerlevel[idx1] << 8) |
			    (ppowerlevel[idx1] << 16) |
			    (ppowerlevel[idx1] << 24);
		}

		if (rtlefuse->eeprom_regulatory == 0) {
			tmpval =
			    (rtlphy->mcs_txpwrlevel_origoffset[0][6]) +
			    (rtlphy->mcs_txpwrlevel_origoffset[0][7] <<
			     8);
			tx_agc[RF90_PATH_A] += tmpval;

			tmpval = (rtlphy->mcs_txpwrlevel_origoffset[0][14]) +
				 (rtlphy->mcs_txpwrlevel_origoffset[0][15] <<
				 24);
			tx_agc[RF90_PATH_B] += tmpval;
		}
	}

	for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
		ptr = (u8 *) (&(tx_agc[idx1]));
		for (idx2 = 0; idx2 < 4; idx2++) {
			if (*ptr > RF6052_MAX_TX_PWR)
				*ptr = RF6052_MAX_TX_PWR;
			ptr++;
		}
	}

	tmpval = tx_agc[RF90_PATH_A] & 0xff;
	rtl_set_bbreg(hw, RTXAGC_A_CCK1_MCS32, MASKBYTE1, tmpval);

	RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
		("CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n", tmpval,
		 RTXAGC_A_CCK1_MCS32));

	tmpval = tx_agc[RF90_PATH_A] >> 8;

	if (mac->mode == WIRELESS_MODE_B)
		tmpval = tmpval & 0xff00ffff;

	rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval);

	RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
		("CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n", tmpval,
		 RTXAGC_B_CCK11_A_CCK2_11));

	tmpval = tx_agc[RF90_PATH_B] >> 24;
	rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE0, tmpval);

	RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
		("CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", tmpval,
		 RTXAGC_B_CCK11_A_CCK2_11));

	tmpval = tx_agc[RF90_PATH_B] & 0x00ffffff;
	rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, 0xffffff00, tmpval);

	RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
		("CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n", tmpval,
		 RTXAGC_B_CCK1_55_MCS32));
}

static void rtl92c_phy_get_power_base(struct ieee80211_hw *hw,
				      u8 *ppowerlevel, u8 channel,
				      u32 *ofdmbase, u32 *mcsbase)
{
	struct rtl_priv *rtlpriv = rtl_priv(hw);
	struct rtl_phy *rtlphy = &(rtlpriv->phy);
	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
	u32 powerBase0, powerBase1;
	u8 legacy_pwrdiff, ht20_pwrdiff;
	u8 i, powerlevel[2];

	for (i = 0; i < 2; i++) {
		powerlevel[i] = ppowerlevel[i];
		legacy_pwrdiff = rtlefuse->txpwr_legacyhtdiff[i][channel - 1];
		powerBase0 = powerlevel[i] + legacy_pwrdiff;

		powerBase0 = (powerBase0 << 24) | (powerBase0 << 16) |
		    (powerBase0 << 8) | powerBase0;
		*(ofdmbase + i) = powerBase0;
		RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
			(" [OFDM power base index rf(%c) = 0x%x]\n",
			 ((i == 0) ? 'A' : 'B'), *(ofdmbase + i)));
	}

	for (i = 0; i < 2; i++) {
		if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20) {
			ht20_pwrdiff = rtlefuse->txpwr_ht20diff[i][channel - 1];
			powerlevel[i] += ht20_pwrdiff;
		}
		powerBase1 = powerlevel[i];
		powerBase1 = (powerBase1 << 24) |
		    (powerBase1 << 16) | (powerBase1 << 8) | powerBase1;

		*(mcsbase + i) = powerBase1;

		RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
			(" [MCS power base index rf(%c) = 0x%x]\n",
			 ((i == 0) ? 'A' : 'B'), *(mcsbase + i)));
	}
}

static void _rtl92c_get_txpower_writeval_by_regulatory(struct ieee80211_hw *hw,
						       u8 channel, u8 index,
						       u32 *powerBase0,
						       u32 *powerBase1,
						       u32 *p_outwriteval)
{
	struct rtl_priv *rtlpriv = rtl_priv(hw);
	struct rtl_phy *rtlphy = &(rtlpriv->phy);
	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
	u8 i, chnlgroup, pwr_diff_limit[4];
	u32 writeVal, customer_limit, rf;

	for (rf = 0; rf < 2; rf++) {
		switch (rtlefuse->eeprom_regulatory) {
		case 0:
			chnlgroup = 0;

			writeVal =
			    rtlphy->mcs_txpwrlevel_origoffset[chnlgroup][index +
			    (rf ? 8 : 0)]
			    + ((index < 2) ? powerBase0[rf] : powerBase1[rf]);

			RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
				("RTK better performance, "
				 "writeVal(%c) = 0x%x\n",
				 ((rf == 0) ? 'A' : 'B'), writeVal));
			break;
		case 1:
			if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
				writeVal = ((index < 2) ? powerBase0[rf] :
					    powerBase1[rf]);

				RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
					("Realtek regulatory, 40MHz, "
					 "writeVal(%c) = 0x%x\n",
					 ((rf == 0) ? 'A' : 'B'), writeVal));
			} else {
				if (rtlphy->pwrgroup_cnt == 1)
					chnlgroup = 0;
				if (rtlphy->pwrgroup_cnt >= 3) {
					if (channel <= 3)
						chnlgroup = 0;
					else if (channel >= 4 && channel <= 9)
						chnlgroup = 1;
					else if (channel > 9)
						chnlgroup = 2;
					if (rtlphy->pwrgroup_cnt == 4)
						chnlgroup++;
				}

				writeVal =
				    rtlphy->mcs_txpwrlevel_origoffset[chnlgroup]
				    [index + (rf ? 8 : 0)] + ((index < 2) ?
							      powerBase0[rf] :
							      powerBase1[rf]);

				RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
					("Realtek regulatory, 20MHz, "
					 "writeVal(%c) = 0x%x\n",
					 ((rf == 0) ? 'A' : 'B'), writeVal));
			}
			break;
		case 2:
			writeVal =
			    ((index < 2) ? powerBase0[rf] : powerBase1[rf]);

			RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
				("Better regulatory, "
				 "writeVal(%c) = 0x%x\n",
				 ((rf == 0) ? 'A' : 'B'), writeVal));
			break;
		case 3:
			chnlgroup = 0;

			if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
				RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
					("customer's limit, 40MHz "
					 "rf(%c) = 0x%x\n",
					 ((rf == 0) ? 'A' : 'B'),
					 rtlefuse->pwrgroup_ht40[rf][channel -
								     1]));
			} else {
				RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
					("customer's limit, 20MHz "
					 "rf(%c) = 0x%x\n",
					 ((rf == 0) ? 'A' : 'B'),
					 rtlefuse->pwrgroup_ht20[rf][channel -
								     1]));
			}
			for (i = 0; i < 4; i++) {
				pwr_diff_limit[i] =
				    (u8) ((rtlphy->mcs_txpwrlevel_origoffset
					  [chnlgroup][index +
					  (rf ? 8 : 0)] & (0x7f << (i * 8))) >>
					  (i * 8));

				if (rtlphy->current_chan_bw ==
				    HT_CHANNEL_WIDTH_20_40) {
					if (pwr_diff_limit[i] >
					    rtlefuse->
					    pwrgroup_ht40[rf][channel - 1])
						pwr_diff_limit[i] =
						    rtlefuse->pwrgroup_ht40[rf]
						    [channel - 1];
				} else {
					if (pwr_diff_limit[i] >
					    rtlefuse->
					    pwrgroup_ht20[rf][channel - 1])
						pwr_diff_limit[i] =
						    rtlefuse->pwrgroup_ht20[rf]
						    [channel - 1];
				}
			}

			customer_limit = (pwr_diff_limit[3] << 24) |
			    (pwr_diff_limit[2] << 16) |
			    (pwr_diff_limit[1] << 8) | (pwr_diff_limit[0]);

			RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
				("Customer's limit rf(%c) = 0x%x\n",
				 ((rf == 0) ? 'A' : 'B'), customer_limit));

			writeVal = customer_limit +
			    ((index < 2) ? powerBase0[rf] : powerBase1[rf]);

			RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
				("Customer, writeVal rf(%c)= 0x%x\n",
				 ((rf == 0) ? 'A' : 'B'), writeVal));
			break;
		default:
			chnlgroup = 0;
			writeVal =
			    rtlphy->mcs_txpwrlevel_origoffset[chnlgroup]
			    [index + (rf ? 8 : 0)]
			    + ((index < 2) ? powerBase0[rf] : powerBase1[rf]);

			RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
				("RTK better performance, writeVal "
				 "rf(%c) = 0x%x\n",
				 ((rf == 0) ? 'A' : 'B'), writeVal));
			break;
		}

		if (rtlpriv->dm.dynamic_txhighpower_lvl == TXHIGHPWRLEVEL_BT1)
			writeVal = writeVal - 0x06060606;
		else if (rtlpriv->dm.dynamic_txhighpower_lvl ==
			 TXHIGHPWRLEVEL_BT2)
			writeVal = writeVal - 0x0c0c0c0c;
		*(p_outwriteval + rf) = writeVal;
	}
}

static void _rtl92c_write_ofdm_power_reg(struct ieee80211_hw *hw,
					 u8 index, u32 *pValue)
{
	struct rtl_priv *rtlpriv = rtl_priv(hw);
	struct rtl_phy *rtlphy = &(rtlpriv->phy);

	u16 regoffset_a[6] = {
		RTXAGC_A_RATE18_06, RTXAGC_A_RATE54_24,
		RTXAGC_A_MCS03_MCS00, RTXAGC_A_MCS07_MCS04,
		RTXAGC_A_MCS11_MCS08, RTXAGC_A_MCS15_MCS12
	};
	u16 regoffset_b[6] = {
		RTXAGC_B_RATE18_06, RTXAGC_B_RATE54_24,
		RTXAGC_B_MCS03_MCS00, RTXAGC_B_MCS07_MCS04,
		RTXAGC_B_MCS11_MCS08, RTXAGC_B_MCS15_MCS12
	};
	u8 i, rf, pwr_val[4];
	u32 writeVal;
	u16 regoffset;

	for (rf = 0; rf < 2; rf++) {
		writeVal = pValue[rf];
		for (i = 0; i < 4; i++) {
			pwr_val[i] = (u8) ((writeVal & (0x7f <<
							(i * 8))) >> (i * 8));

			if (pwr_val[i] > RF6052_MAX_TX_PWR)
				pwr_val[i] = RF6052_MAX_TX_PWR;
		}
		writeVal = (pwr_val[3] << 24) | (pwr_val[2] << 16) |
		    (pwr_val[1] << 8) | pwr_val[0];

		if (rf == 0)
			regoffset = regoffset_a[index];
		else
			regoffset = regoffset_b[index];
		rtl_set_bbreg(hw, regoffset, MASKDWORD, writeVal);

		RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
			("Set 0x%x = %08x\n", regoffset, writeVal));

		if (((get_rf_type(rtlphy) == RF_2T2R) &&
		     (regoffset == RTXAGC_A_MCS15_MCS12 ||
		      regoffset == RTXAGC_B_MCS15_MCS12)) ||
		    ((get_rf_type(rtlphy) != RF_2T2R) &&
		     (regoffset == RTXAGC_A_MCS07_MCS04 ||
		      regoffset == RTXAGC_B_MCS07_MCS04))) {

			writeVal = pwr_val[3];
			if (regoffset == RTXAGC_A_MCS15_MCS12 ||
			    regoffset == RTXAGC_A_MCS07_MCS04)
				regoffset = 0xc90;
			if (regoffset == RTXAGC_B_MCS15_MCS12 ||
			    regoffset == RTXAGC_B_MCS07_MCS04)
				regoffset = 0xc98;

			for (i = 0; i < 3; i++) {
				writeVal = (writeVal > 6) ? (writeVal - 6) : 0;
				rtl_write_byte(rtlpriv, (u32) (regoffset + i),
					       (u8) writeVal);
			}
		}
	}
}

void rtl92ce_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw,
					u8 *ppowerlevel, u8 channel)
{
	u32 writeVal[2], powerBase0[2], powerBase1[2];
	u8 index;

	rtl92c_phy_get_power_base(hw, ppowerlevel,
				  channel, &powerBase0[0], &powerBase1[0]);

	for (index = 0; index < 6; index++) {
		_rtl92c_get_txpower_writeval_by_regulatory(hw,
							   channel, index,
							   &powerBase0[0],
							   &powerBase1[0],
							   &writeVal[0]);

		_rtl92c_write_ofdm_power_reg(hw, index, &writeVal[0]);
	}
}

bool rtl92ce_phy_rf6052_config(struct ieee80211_hw *hw)
{
	struct rtl_priv *rtlpriv = rtl_priv(hw);
	struct rtl_phy *rtlphy = &(rtlpriv->phy);

	if (rtlphy->rf_type == RF_1T1R)
		rtlphy->num_total_rfpath = 1;
	else
		rtlphy->num_total_rfpath = 2;

	return _rtl92c_phy_rf6052_config_parafile(hw);
}

static bool _rtl92c_phy_rf6052_config_parafile(struct ieee80211_hw *hw)
{
	struct rtl_priv *rtlpriv = rtl_priv(hw);
	struct rtl_phy *rtlphy = &(rtlpriv->phy);
	u32 u4_regvalue;
	u8 rfpath;
	bool rtstatus;
	struct bb_reg_def *pphyreg;

	for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) {

		pphyreg = &rtlphy->phyreg_def[rfpath];

		switch (rfpath) {
		case RF90_PATH_A:
		case RF90_PATH_C:
			u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs,
						    BRFSI_RFENV);
			break;
		case RF90_PATH_B:
		case RF90_PATH_D:
			u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs,
						    BRFSI_RFENV << 16);
			break;
		}

		rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1);
		udelay(1);

		rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1);
		udelay(1);

		rtl_set_bbreg(hw, pphyreg->rfhssi_para2,
			      B3WIREADDREAALENGTH, 0x0);
		udelay(1);

		rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0);
		udelay(1);

		switch (rfpath) {
		case RF90_PATH_A:
			rtstatus = rtl92ce_phy_config_rf_with_headerfile(hw,
					(enum radio_path) rfpath);
			break;
		case RF90_PATH_B:
			rtstatus = rtl92ce_phy_config_rf_with_headerfile(hw,
					(enum radio_path) rfpath);
			break;
		case RF90_PATH_C:
			break;
		case RF90_PATH_D:
			break;
		}

		switch (rfpath) {
		case RF90_PATH_A:
		case RF90_PATH_C:
			rtl_set_bbreg(hw, pphyreg->rfintfs,
				      BRFSI_RFENV, u4_regvalue);
			break;
		case RF90_PATH_B:
		case RF90_PATH_D:
			rtl_set_bbreg(hw, pphyreg->rfintfs,
				      BRFSI_RFENV << 16, u4_regvalue);
			break;
		}

		if (rtstatus != true) {
			RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
				 ("Radio[%d] Fail!!", rfpath));
			return false;
		}

	}

	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("<---\n"));
	return rtstatus;
}
Commit	Line	Data
0c817338 LF	1	/******************************************************************************
	2	*
	3	* Copyright(c) 2009-2010 Realtek Corporation.
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of version 2 of the GNU General Public License as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
	14	* You should have received a copy of the GNU General Public License along with
	15	* this program; if not, write to the Free Software Foundation, Inc.,
	16	* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
	17	*
	18	* The full GNU General Public License is included in this distribution in the
	19	* file called LICENSE.
	20	*
	21	* Contact Information:
	22	* wlanfae <wlanfae@realtek.com>
	23	* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
	24	* Hsinchu 300, Taiwan.
	25	*
	26	* Larry Finger <Larry.Finger@lwfinger.net>
	27	*
	28	*****************************************************************************/
	29
	30	#include "../wifi.h"
5c405b5c JL	31	#include "reg.h"
	32	#include "def.h"
	33	#include "phy.h"
	34	#include "rf.h"
	35	#include "dm.h"
0c817338 LF	36
	37	static bool _rtl92c_phy_rf6052_config_parafile(struct ieee80211_hw *hw);
	38
	39	void rtl92c_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth)
	40	{
	41	struct rtl_priv *rtlpriv = rtl_priv(hw);
	42	struct rtl_phy *rtlphy = &(rtlpriv->phy);
	43
	44	switch (bandwidth) {
	45	case HT_CHANNEL_WIDTH_20:
	46	rtlphy->rfreg_chnlval[0] = ((rtlphy->rfreg_chnlval[0] &
	47	0xfffff3ff) \| 0x0400);
	48	rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
	49	rtlphy->rfreg_chnlval[0]);
	50	break;
	51	case HT_CHANNEL_WIDTH_20_40:
	52	rtlphy->rfreg_chnlval[0] = ((rtlphy->rfreg_chnlval[0] &
	53	0xfffff3ff));
	54	rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
	55	rtlphy->rfreg_chnlval[0]);
	56	break;
	57	default:
	58	RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
	59	("unknown bandwidth: %#X\n", bandwidth));
	60	break;
	61	}
	62	}
	63
1472d3a8	64	void rtl92ce_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
0c817338 LF	65	u8 *ppowerlevel)
	66	{
	67	struct rtl_priv *rtlpriv = rtl_priv(hw);
	68	struct rtl_phy *rtlphy = &(rtlpriv->phy);
	69	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
	70	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
	71	u32 tx_agc[2] = {0, 0}, tmpval;
	72	bool turbo_scanoff = false;
	73	u8 idx1, idx2;
	74	u8 *ptr;
	75
	76	if (rtlefuse->eeprom_regulatory != 0)
	77	turbo_scanoff = true;
	78
	79	if (mac->act_scanning == true) {
	80	tx_agc[RF90_PATH_A] = 0x3f3f3f3f;
	81	tx_agc[RF90_PATH_B] = 0x3f3f3f3f;
	82
	83	if (turbo_scanoff) {
	84	for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
	85	tx_agc[idx1] = ppowerlevel[idx1] \|
	86	(ppowerlevel[idx1] << 8) \|
	87	(ppowerlevel[idx1] << 16) \|
	88	(ppowerlevel[idx1] << 24);
	89	}
	90	}
	91	} else {
	92	for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
	93	tx_agc[idx1] = ppowerlevel[idx1] \|
	94	(ppowerlevel[idx1] << 8) \|
	95	(ppowerlevel[idx1] << 16) \|
	96	(ppowerlevel[idx1] << 24);
	97	}
	98
	99	if (rtlefuse->eeprom_regulatory == 0) {
	100	tmpval =
	101	(rtlphy->mcs_txpwrlevel_origoffset[0][6]) +
	102	(rtlphy->mcs_txpwrlevel_origoffset[0][7] <<
	103	8);
	104	tx_agc[RF90_PATH_A] += tmpval;
	105
	106	tmpval = (rtlphy->mcs_txpwrlevel_origoffset[0][14]) +
	107	(rtlphy->mcs_txpwrlevel_origoffset[0][15] <<
	108	24);
	109	tx_agc[RF90_PATH_B] += tmpval;
	110	}
	111	}
	112
	113	for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
	114	ptr = (u8 *) (&(tx_agc[idx1]));
	115	for (idx2 = 0; idx2 < 4; idx2++) {
	116	if (*ptr > RF6052_MAX_TX_PWR)
	117	*ptr = RF6052_MAX_TX_PWR;
	118	ptr++;
	119	}
	120	}
	121
	122	tmpval = tx_agc[RF90_PATH_A] & 0xff;
	123	rtl_set_bbreg(hw, RTXAGC_A_CCK1_MCS32, MASKBYTE1, tmpval);
	124
	125	RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
	126	("CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n", tmpval,
	127	RTXAGC_A_CCK1_MCS32));
	128
129	tmpval = tx_agc[RF90_PATH_A] >> 8;
130
131	if (mac->mode == WIRELESS_MODE_B)
132	tmpval = tmpval & 0xff00ffff;
133
134	rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval);
135
136	RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
137	("CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n", tmpval,
138	RTXAGC_B_CCK11_A_CCK2_11));
139
140	tmpval = tx_agc[RF90_PATH_B] >> 24;
141	rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE0, tmpval);
142
143	RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
144	("CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", tmpval,
145	RTXAGC_B_CCK11_A_CCK2_11));
146
147	tmpval = tx_agc[RF90_PATH_B] & 0x00ffffff;
148	rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, 0xffffff00, tmpval);
149
150	RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
151	("CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n", tmpval,
152	RTXAGC_B_CCK1_55_MCS32));
153	}
154
155	static void rtl92c_phy_get_power_base(struct ieee80211_hw *hw,
156	u8 *ppowerlevel, u8 channel,
157	u32 ofdmbase, u32 mcsbase)
158	{
159	struct rtl_priv *rtlpriv = rtl_priv(hw);
160	struct rtl_phy *rtlphy = &(rtlpriv->phy);
161	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
162	u32 powerBase0, powerBase1;
163	u8 legacy_pwrdiff, ht20_pwrdiff;
164	u8 i, powerlevel[2];
165
166	for (i = 0; i < 2; i++) {
167	powerlevel[i] = ppowerlevel[i];
168	legacy_pwrdiff = rtlefuse->txpwr_legacyhtdiff[i][channel - 1];
169	powerBase0 = powerlevel[i] + legacy_pwrdiff;
170
171	powerBase0 = (powerBase0 << 24) \| (powerBase0 << 16) \|
172	(powerBase0 << 8) \| powerBase0;
173	*(ofdmbase + i) = powerBase0;
174	RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
175	(" [OFDM power base index rf(%c) = 0x%x]\n",
176	((i == 0) ? 'A' : 'B'), *(ofdmbase + i)));
177	}
178
179	for (i = 0; i < 2; i++) {
180	if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20) {
181	ht20_pwrdiff = rtlefuse->txpwr_ht20diff[i][channel - 1];
182	powerlevel[i] += ht20_pwrdiff;
183	}
184	powerBase1 = powerlevel[i];
185	powerBase1 = (powerBase1 << 24) \|
186	(powerBase1 << 16) \| (powerBase1 << 8) \| powerBase1;
187
188	*(mcsbase + i) = powerBase1;
189
190	RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
191	(" [MCS power base index rf(%c) = 0x%x]\n",
192	((i == 0) ? 'A' : 'B'), *(mcsbase + i)));
193	}
194	}
195
196	static void _rtl92c_get_txpower_writeval_by_regulatory(struct ieee80211_hw *hw,
197	u8 channel, u8 index,
198	u32 *powerBase0,
199	u32 *powerBase1,
200	u32 *p_outwriteval)
201	{
202	struct rtl_priv *rtlpriv = rtl_priv(hw);
203	struct rtl_phy *rtlphy = &(rtlpriv->phy);
204	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
205	u8 i, chnlgroup, pwr_diff_limit[4];
206	u32 writeVal, customer_limit, rf;
207
208	for (rf = 0; rf < 2; rf++) {
209	switch (rtlefuse->eeprom_regulatory) {
210	case 0:
211	chnlgroup = 0;
212
213	writeVal =
214	rtlphy->mcs_txpwrlevel_origoffset[chnlgroup][index +
215	(rf ? 8 : 0)]
216	+ ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
217
218	RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
219	("RTK better performance, "
220	"writeVal(%c) = 0x%x\n",
221	((rf == 0) ? 'A' : 'B'), writeVal));
222	break;
223	case 1:
224	if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
225	writeVal = ((index < 2) ? powerBase0[rf] :
226	powerBase1[rf]);
227
228	RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
229	("Realtek regulatory, 40MHz, "
230	"writeVal(%c) = 0x%x\n",
231	((rf == 0) ? 'A' : 'B'), writeVal));
232	} else {
233	if (rtlphy->pwrgroup_cnt == 1)
234	chnlgroup = 0;
235	if (rtlphy->pwrgroup_cnt >= 3) {
236	if (channel <= 3)
237	chnlgroup = 0;
238	else if (channel >= 4 && channel <= 9)
239	chnlgroup = 1;
240	else if (channel > 9)
241	chnlgroup = 2;
242	if (rtlphy->pwrgroup_cnt == 4)
243	chnlgroup++;
244	}
245
246	writeVal =
247	rtlphy->mcs_txpwrlevel_origoffset[chnlgroup]
248	[index + (rf ? 8 : 0)] + ((index < 2) ?
249	powerBase0[rf] :
250	powerBase1[rf]);
251
252	RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
253	("Realtek regulatory, 20MHz, "
254	"writeVal(%c) = 0x%x\n",
255	((rf == 0) ? 'A' : 'B'), writeVal));
256	}
257	break;
258	case 2:
259	writeVal =
260	((index < 2) ? powerBase0[rf] : powerBase1[rf]);
261
262	RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
263	("Better regulatory, "
264	"writeVal(%c) = 0x%x\n",
265	((rf == 0) ? 'A' : 'B'), writeVal));
266	break;
267	case 3:
268	chnlgroup = 0;
269
270	if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
271	RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
272	("customer's limit, 40MHz "
273	"rf(%c) = 0x%x\n",
274	((rf == 0) ? 'A' : 'B'),
275	rtlefuse->pwrgroup_ht40[rf][channel -
276	1]));
277	} else {
278	RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
279	("customer's limit, 20MHz "
280	"rf(%c) = 0x%x\n",
281	((rf == 0) ? 'A' : 'B'),
282	rtlefuse->pwrgroup_ht20[rf][channel -
283	1]));
284	}
285	for (i = 0; i < 4; i++) {
286	pwr_diff_limit[i] =
287	(u8) ((rtlphy->mcs_txpwrlevel_origoffset
288	[chnlgroup][index +
289	(rf ? 8 : 0)] & (0x7f << (i * 8))) >>
290	(i * 8));
291
292	if (rtlphy->current_chan_bw ==
293	HT_CHANNEL_WIDTH_20_40) {
294	if (pwr_diff_limit[i] >
295	rtlefuse->
296	pwrgroup_ht40[rf][channel - 1])
297	pwr_diff_limit[i] =
298	rtlefuse->pwrgroup_ht40[rf]
299	[channel - 1];
300	} else {
301	if (pwr_diff_limit[i] >
302	rtlefuse->
303	pwrgroup_ht20[rf][channel - 1])
304	pwr_diff_limit[i] =
305	rtlefuse->pwrgroup_ht20[rf]
306	[channel - 1];
307	}
308	}
309
310	customer_limit = (pwr_diff_limit[3] << 24) \|
311	(pwr_diff_limit[2] << 16) \|
312	(pwr_diff_limit[1] << 8) \| (pwr_diff_limit[0]);
313
314	RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
315	("Customer's limit rf(%c) = 0x%x\n",
316	((rf == 0) ? 'A' : 'B'), customer_limit));
317
318	writeVal = customer_limit +
319	((index < 2) ? powerBase0[rf] : powerBase1[rf]);
320
321	RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
322	("Customer, writeVal rf(%c)= 0x%x\n",
323	((rf == 0) ? 'A' : 'B'), writeVal));
324	break;
325	default:
326	chnlgroup = 0;
327	writeVal =
328	rtlphy->mcs_txpwrlevel_origoffset[chnlgroup]
329	[index + (rf ? 8 : 0)]
330	+ ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
331
332	RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
333	("RTK better performance, writeVal "
334	"rf(%c) = 0x%x\n",
335	((rf == 0) ? 'A' : 'B'), writeVal));
336	break;
337	}
338
339	if (rtlpriv->dm.dynamic_txhighpower_lvl == TXHIGHPWRLEVEL_BT1)
340	writeVal = writeVal - 0x06060606;
341	else if (rtlpriv->dm.dynamic_txhighpower_lvl ==
342	TXHIGHPWRLEVEL_BT2)
343	writeVal = writeVal - 0x0c0c0c0c;
344	*(p_outwriteval + rf) = writeVal;
345	}
346	}
347
348	static void _rtl92c_write_ofdm_power_reg(struct ieee80211_hw *hw,
349	u8 index, u32 *pValue)
350	{
351	struct rtl_priv *rtlpriv = rtl_priv(hw);
352	struct rtl_phy *rtlphy = &(rtlpriv->phy);
353
354	u16 regoffset_a[6] = {
355	RTXAGC_A_RATE18_06, RTXAGC_A_RATE54_24,
356	RTXAGC_A_MCS03_MCS00, RTXAGC_A_MCS07_MCS04,
357	RTXAGC_A_MCS11_MCS08, RTXAGC_A_MCS15_MCS12
358	};
359	u16 regoffset_b[6] = {
360	RTXAGC_B_RATE18_06, RTXAGC_B_RATE54_24,
361	RTXAGC_B_MCS03_MCS00, RTXAGC_B_MCS07_MCS04,
362	RTXAGC_B_MCS11_MCS08, RTXAGC_B_MCS15_MCS12
363	};
364	u8 i, rf, pwr_val[4];
365	u32 writeVal;
366	u16 regoffset;
367
368	for (rf = 0; rf < 2; rf++) {
369	writeVal = pValue[rf];
370	for (i = 0; i < 4; i++) {
371	pwr_val[i] = (u8) ((writeVal & (0x7f <<
372	(i * 8))) >> (i * 8));
373
374	if (pwr_val[i] > RF6052_MAX_TX_PWR)
375	pwr_val[i] = RF6052_MAX_TX_PWR;
376	}
377	writeVal = (pwr_val[3] << 24) \| (pwr_val[2] << 16) \|
378	(pwr_val[1] << 8) \| pwr_val[0];
379
380	if (rf == 0)
381	regoffset = regoffset_a[index];
382	else
383	regoffset = regoffset_b[index];
384	rtl_set_bbreg(hw, regoffset, MASKDWORD, writeVal);
385
386	RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
387	("Set 0x%x = %08x\n", regoffset, writeVal));
388
389	if (((get_rf_type(rtlphy) == RF_2T2R) &&
390	(regoffset == RTXAGC_A_MCS15_MCS12 \|\|
391	regoffset == RTXAGC_B_MCS15_MCS12)) \|\|
392	((get_rf_type(rtlphy) != RF_2T2R) &&
393	(regoffset == RTXAGC_A_MCS07_MCS04 \|\|
394	regoffset == RTXAGC_B_MCS07_MCS04))) {
395
396	writeVal = pwr_val[3];
397	if (regoffset == RTXAGC_A_MCS15_MCS12 \|\|
398	regoffset == RTXAGC_A_MCS07_MCS04)
399	regoffset = 0xc90;
400	if (regoffset == RTXAGC_B_MCS15_MCS12 \|\|
401	regoffset == RTXAGC_B_MCS07_MCS04)
402	regoffset = 0xc98;
403
404	for (i = 0; i < 3; i++) {
405	writeVal = (writeVal > 6) ? (writeVal - 6) : 0;
406	rtl_write_byte(rtlpriv, (u32) (regoffset + i),
407	(u8) writeVal);
408	}
409	}
410	}
411	}
412
1472d3a8	413	void rtl92ce_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw,
0c817338 LF	414	u8 *ppowerlevel, u8 channel)
	415	{
	416	u32 writeVal[2], powerBase0[2], powerBase1[2];
	417	u8 index;
	418
	419	rtl92c_phy_get_power_base(hw, ppowerlevel,
	420	channel, &powerBase0[0], &powerBase1[0]);
	421
	422	for (index = 0; index < 6; index++) {
	423	_rtl92c_get_txpower_writeval_by_regulatory(hw,
	424	channel, index,
	425	&powerBase0[0],
	426	&powerBase1[0],
	427	&writeVal[0]);
	428
	429	_rtl92c_write_ofdm_power_reg(hw, index, &writeVal[0]);
	430	}
	431	}
	432
1472d3a8	433	bool rtl92ce_phy_rf6052_config(struct ieee80211_hw *hw)
0c817338 LF	434	{
	435	struct rtl_priv *rtlpriv = rtl_priv(hw);
	436	struct rtl_phy *rtlphy = &(rtlpriv->phy);
	437
	438	if (rtlphy->rf_type == RF_1T1R)
	439	rtlphy->num_total_rfpath = 1;
	440	else
	441	rtlphy->num_total_rfpath = 2;
	442
	443	return _rtl92c_phy_rf6052_config_parafile(hw);
	444	}
	445
	446	static bool _rtl92c_phy_rf6052_config_parafile(struct ieee80211_hw *hw)
	447	{
	448	struct rtl_priv *rtlpriv = rtl_priv(hw);
	449	struct rtl_phy *rtlphy = &(rtlpriv->phy);
	450	u32 u4_regvalue;
	451	u8 rfpath;
	452	bool rtstatus;
	453	struct bb_reg_def *pphyreg;
	454
	455	for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) {
	456
	457	pphyreg = &rtlphy->phyreg_def[rfpath];
	458
	459	switch (rfpath) {
	460	case RF90_PATH_A:
	461	case RF90_PATH_C:
	462	u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs,
	463	BRFSI_RFENV);
	464	break;
	465	case RF90_PATH_B:
	466	case RF90_PATH_D:
	467	u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs,
	468	BRFSI_RFENV << 16);
	469	break;
	470	}
	471
	472	rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1);
	473	udelay(1);
	474
	475	rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1);
	476	udelay(1);
	477
	478	rtl_set_bbreg(hw, pphyreg->rfhssi_para2,
	479	B3WIREADDREAALENGTH, 0x0);
	480	udelay(1);
	481
	482	rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0);
	483	udelay(1);
	484
	485	switch (rfpath) {
	486	case RF90_PATH_A:
1472d3a8	487	rtstatus = rtl92ce_phy_config_rf_with_headerfile(hw,
0c817338 LF	488	(enum radio_path) rfpath);
	489	break;
	490	case RF90_PATH_B:
1472d3a8	491	rtstatus = rtl92ce_phy_config_rf_with_headerfile(hw,
0c817338 LF	492	(enum radio_path) rfpath);
	493	break;
	494	case RF90_PATH_C:
	495	break;
	496	case RF90_PATH_D:
	497	break;
	498	}
	499
	500	switch (rfpath) {
	501	case RF90_PATH_A:
	502	case RF90_PATH_C:
	503	rtl_set_bbreg(hw, pphyreg->rfintfs,
	504	BRFSI_RFENV, u4_regvalue);
	505	break;
	506	case RF90_PATH_B:
	507	case RF90_PATH_D:
	508	rtl_set_bbreg(hw, pphyreg->rfintfs,
	509	BRFSI_RFENV << 16, u4_regvalue);
	510	break;
	511	}
	512
	513	if (rtstatus != true) {
	514	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
	515	("Radio[%d] Fail!!", rfpath));
	516	return false;
	517	}
	518
	519	}
	520
	521	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("<---\n"));
	522	return rtstatus;
	523	}