[deliverable/linux.git] / drivers / net / wireless / ti / wlcore / wlcore.h

/*
 * This file is part of wlcore
 *
 * Copyright (C) 2011 Texas Instruments Inc.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 *
 */

#ifndef __WLCORE_H__
#define __WLCORE_H__

#include <linux/platform_device.h>

#include "wl12xx.h"
#include "event.h"

/* The maximum number of Tx descriptors in all chip families */
#define WLCORE_MAX_TX_DESCRIPTORS 32

/* forward declaration */
struct wl1271_tx_hw_descr;
enum wl_rx_buf_align;

struct wlcore_ops {
	int (*identify_chip)(struct wl1271 *wl);
	int (*boot)(struct wl1271 *wl);
	void (*trigger_cmd)(struct wl1271 *wl, int cmd_box_addr,
			    void *buf, size_t len);
	void (*ack_event)(struct wl1271 *wl);
	u32 (*calc_tx_blocks)(struct wl1271 *wl, u32 len, u32 spare_blks);
	void (*set_tx_desc_blocks)(struct wl1271 *wl,
				   struct wl1271_tx_hw_descr *desc,
				   u32 blks, u32 spare_blks);
	void (*set_tx_desc_data_len)(struct wl1271 *wl,
				     struct wl1271_tx_hw_descr *desc,
				     struct sk_buff *skb);
	enum wl_rx_buf_align (*get_rx_buf_align)(struct wl1271 *wl,
						 u32 rx_desc);
	void (*prepare_read)(struct wl1271 *wl, u32 rx_desc, u32 len);
	u32 (*get_rx_packet_len)(struct wl1271 *wl, void *rx_data,
				 u32 data_len);
	void (*tx_delayed_compl)(struct wl1271 *wl);
	void (*tx_immediate_compl)(struct wl1271 *wl);
	int (*hw_init)(struct wl1271 *wl);
	int (*init_vif)(struct wl1271 *wl, struct wl12xx_vif *wlvif);
	u32 (*sta_get_ap_rate_mask)(struct wl1271 *wl,
				    struct wl12xx_vif *wlvif);
	s8 (*get_pg_ver)(struct wl1271 *wl);
	void (*get_mac)(struct wl1271 *wl);
};

enum wlcore_partitions {
	PART_DOWN,
	PART_WORK,
	PART_BOOT,
	PART_DRPW,
	PART_TOP_PRCM_ELP_SOC,
	PART_PHY_INIT,

	PART_TABLE_LEN,
};

struct wlcore_partition {
	u32 size;
	u32 start;
};

struct wlcore_partition_set {
	struct wlcore_partition mem;
	struct wlcore_partition reg;
	struct wlcore_partition mem2;
	struct wlcore_partition mem3;
};

enum wlcore_registers {
	/* register addresses, used with partition translation */
	REG_ECPU_CONTROL,
	REG_INTERRUPT_NO_CLEAR,
	REG_INTERRUPT_ACK,
	REG_COMMAND_MAILBOX_PTR,
	REG_EVENT_MAILBOX_PTR,
	REG_INTERRUPT_TRIG,
	REG_INTERRUPT_MASK,
	REG_PC_ON_RECOVERY,
	REG_CHIP_ID_B,
	REG_CMD_MBOX_ADDRESS,

	/* data access memory addresses, used with partition translation */
	REG_SLV_MEM_DATA,
	REG_SLV_REG_DATA,

	/* raw data access memory addresses */
	REG_RAW_FW_STATUS_ADDR,

	REG_TABLE_LEN,
};

struct wl1271 {
	struct ieee80211_hw *hw;
	bool mac80211_registered;

	struct device *dev;

	void *if_priv;

	struct wl1271_if_operations *if_ops;

	void (*set_power)(bool enable);
	int irq;
	int ref_clock;

	spinlock_t wl_lock;

	enum wl1271_state state;
	enum wl12xx_fw_type fw_type;
	bool plt;
	u8 last_vif_count;
	struct mutex mutex;

	unsigned long flags;

	struct wlcore_partition_set curr_part;

	struct wl1271_chip chip;

	int cmd_box_addr;

	u8 *fw;
	size_t fw_len;
	void *nvs;
	size_t nvs_len;

	s8 hw_pg_ver;

	/* address read from the fuse ROM */
	u32 fuse_oui_addr;
	u32 fuse_nic_addr;

	/* we have up to 2 MAC addresses */
	struct mac_address addresses[2];
	int channel;
	u8 system_hlid;

	unsigned long links_map[BITS_TO_LONGS(WL12XX_MAX_LINKS)];
	unsigned long roles_map[BITS_TO_LONGS(WL12XX_MAX_ROLES)];
	unsigned long roc_map[BITS_TO_LONGS(WL12XX_MAX_ROLES)];
	unsigned long rate_policies_map[
			BITS_TO_LONGS(WL12XX_MAX_RATE_POLICIES)];

	struct list_head wlvif_list;

	u8 sta_count;
	u8 ap_count;

	struct wl1271_acx_mem_map *target_mem_map;

	/* Accounting for allocated / available TX blocks on HW */
	u32 tx_blocks_freed;
	u32 tx_blocks_available;
	u32 tx_allocated_blocks;
	u32 tx_results_count;

	/* Accounting for allocated / available Tx packets in HW */
	u32 tx_pkts_freed[NUM_TX_QUEUES];
	u32 tx_allocated_pkts[NUM_TX_QUEUES];

	/* Transmitted TX packets counter for chipset interface */
	u32 tx_packets_count;

	/* Time-offset between host and chipset clocks */
	s64 time_offset;

	/* Frames scheduled for transmission, not handled yet */
	int tx_queue_count[NUM_TX_QUEUES];
	long stopped_queues_map;

	/* Frames received, not handled yet by mac80211 */
	struct sk_buff_head deferred_rx_queue;

	/* Frames sent, not returned yet to mac80211 */
	struct sk_buff_head deferred_tx_queue;

	struct work_struct tx_work;
	struct workqueue_struct *freezable_wq;

	/* Pending TX frames */
	unsigned long tx_frames_map[BITS_TO_LONGS(WLCORE_MAX_TX_DESCRIPTORS)];
	struct sk_buff *tx_frames[WLCORE_MAX_TX_DESCRIPTORS];
	int tx_frames_cnt;

	/* FW Rx counter */
	u32 rx_counter;

	/* Rx memory pool address */
	struct wl1271_rx_mem_pool_addr rx_mem_pool_addr;

	/* Intermediate buffer, used for packet aggregation */
	u8 *aggr_buf;

	/* Reusable dummy packet template */
	struct sk_buff *dummy_packet;

	/* Network stack work  */
	struct work_struct netstack_work;

	/* FW log buffer */
	u8 *fwlog;

	/* Number of valid bytes in the FW log buffer */
	ssize_t fwlog_size;

	/* Sysfs FW log entry readers wait queue */
	wait_queue_head_t fwlog_waitq;

	/* Hardware recovery work */
	struct work_struct recovery_work;

	/* Pointer that holds DMA-friendly block for the mailbox */
	struct event_mailbox *mbox;

	/* The mbox event mask */
	u32 event_mask;

	/* Mailbox pointers */
	u32 mbox_ptr[2];

	/* Are we currently scanning */
	struct ieee80211_vif *scan_vif;
	struct wl1271_scan scan;
	struct delayed_work scan_complete_work;

	bool sched_scanning;

	/* The current band */
	enum ieee80211_band band;

	struct completion *elp_compl;
	struct delayed_work elp_work;

	/* in dBm */
	int power_level;

	struct wl1271_stats stats;

	__le32 buffer_32;
	u32 buffer_cmd;
	u32 buffer_busyword[WL1271_BUSY_WORD_CNT];

	struct wl12xx_fw_status *fw_status;
	struct wl1271_tx_hw_res_if *tx_res_if;

	/* Current chipset configuration */
	struct wlcore_conf conf;

	bool sg_enabled;

	bool enable_11a;

	/* Most recently reported noise in dBm */
	s8 noise;

	/* bands supported by this instance of wl12xx */
	struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];

	int tcxo_clock;

	/*
	 * wowlan trigger was configured during suspend.
	 * (currently, only "ANY" trigger is supported)
	 */
	bool wow_enabled;
	bool irq_wake_enabled;

	/*
	 * AP-mode - links indexed by HLID. The global and broadcast links
	 * are always active.
	 */
	struct wl1271_link links[WL12XX_MAX_LINKS];

	/* AP-mode - a bitmap of links currently in PS mode according to FW */
	u32 ap_fw_ps_map;

	/* AP-mode - a bitmap of links currently in PS mode in mac80211 */
	unsigned long ap_ps_map;

	/* Quirks of specific hardware revisions */
	unsigned int quirks;

	/* Platform limitations */
	unsigned int platform_quirks;

	/* number of currently active RX BA sessions */
	int ba_rx_session_count;

	/* AP-mode - number of currently connected stations */
	int active_sta_count;

	/* last wlvif we transmitted from */
	struct wl12xx_vif *last_wlvif;

	/* work to fire when Tx is stuck */
	struct delayed_work tx_watchdog_work;

	struct wlcore_ops *ops;
	/* pointer to the lower driver partition table */
	const struct wlcore_partition_set *ptable;
	/* pointer to the lower driver register table */
	const int *rtable;
	/* name of the firmwares to load - for PLT, single role, multi-role */
	const char *plt_fw_name;
	const char *sr_fw_name;
	const char *mr_fw_name;

	/* per-chip-family private structure */
	void *priv;

	/* number of TX descriptors the HW supports. */
	u32 num_tx_desc;

	/* spare Tx blocks for normal/GEM operating modes */
	u32 normal_tx_spare;
	u32 gem_tx_spare;

	/* translate HW Tx rates to standard rate-indices */
	const u8 **band_rate_to_idx;

	/* size of table for HW rates that can be received from chip */
	u8 hw_tx_rate_tbl_size;

	/* this HW rate and below are considered HT rates for this chip */
	u8 hw_min_ht_rate;
};

int __devinit wlcore_probe(struct wl1271 *wl, struct platform_device *pdev);
int __devexit wlcore_remove(struct platform_device *pdev);
struct ieee80211_hw *wlcore_alloc_hw(size_t priv_size);
int wlcore_free_hw(struct wl1271 *wl);

/* Firmware image load chunk size */
#define CHUNK_SIZE	16384

/* Quirks */

/* Each RX/TX transaction requires an end-of-transaction transfer */
#define WLCORE_QUIRK_END_OF_TRANSACTION		BIT(0)

/* wl127x and SPI don't support SDIO block size alignment */
#define WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN		BIT(2)

/* means aggregated Rx packets are aligned to a SDIO block */
#define WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN		BIT(3)

/* Older firmwares did not implement the FW logger over bus feature */
#define WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED	BIT(4)

/* Older firmwares use an old NVS format */
#define WLCORE_QUIRK_LEGACY_NVS			BIT(5)

/* Some firmwares may not support ELP */
#define WLCORE_QUIRK_NO_ELP			BIT(6)

/* TODO: move to the lower drivers when all usages are abstracted */
#define CHIP_ID_1271_PG10              (0x4030101)
#define CHIP_ID_1271_PG20              (0x4030111)
#define CHIP_ID_1283_PG10              (0x05030101)
#define CHIP_ID_1283_PG20              (0x05030111)

/* TODO: move all these common registers and values elsewhere */
#define HW_ACCESS_ELP_CTRL_REG		0x1FFFC

/* ELP register commands */
#define ELPCTRL_WAKE_UP             0x1
#define ELPCTRL_WAKE_UP_WLAN_READY  0x5
#define ELPCTRL_SLEEP               0x0
/* ELP WLAN_READY bit */
#define ELPCTRL_WLAN_READY          0x2

/*************************************************************************

    Interrupt Trigger Register (Host -> WiLink)

**************************************************************************/

/* Hardware to Embedded CPU Interrupts - first 32-bit register set */

/*
 * The host sets this bit to inform the Wlan
 * FW that a TX packet is in the XFER
 * Buffer #0.
 */
#define INTR_TRIG_TX_PROC0 BIT(2)

/*
 * The host sets this bit to inform the FW
 * that it read a packet from RX XFER
 * Buffer #0.
 */
#define INTR_TRIG_RX_PROC0 BIT(3)

#define INTR_TRIG_DEBUG_ACK BIT(4)

#define INTR_TRIG_STATE_CHANGED BIT(5)

/* Hardware to Embedded CPU Interrupts - second 32-bit register set */

/*
 * The host sets this bit to inform the FW
 * that it read a packet from RX XFER
 * Buffer #1.
 */
#define INTR_TRIG_RX_PROC1 BIT(17)

/*
 * The host sets this bit to inform the Wlan
 * hardware that a TX packet is in the XFER
 * Buffer #1.
 */
#define INTR_TRIG_TX_PROC1 BIT(18)

#define ACX_SLV_SOFT_RESET_BIT	BIT(1)
#define SOFT_RESET_MAX_TIME	1000000
#define SOFT_RESET_STALL_TIME	1000

#define ECPU_CONTROL_HALT	0x00000101

#define WELP_ARM_COMMAND_VAL	0x4

#endif /* __WLCORE_H__ */
Commit	Line	Data
b2ba99ff LC	1	/*
	2	* This file is part of wlcore
	3	*
	4	* Copyright (C) 2011 Texas Instruments Inc.
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* version 2 as published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful, but
	11	* WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	13	* General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	18	* 02110-1301 USA
	19	*
	20	*/
	21
	22	#ifndef __WLCORE_H__
	23	#define __WLCORE_H__
	24
c31be25a LC	25	#include <linux/platform_device.h>
c31be25a LC	26
ffeb501c	27	#include "wl12xx.h"
c31be25a LC	28	#include "event.h"
c31be25a LC	29
72b0624f AN	30	/* The maximum number of Tx descriptors in all chip families */
	31	#define WLCORE_MAX_TX_DESCRIPTORS 32
	32
cd70f6a4 AN	33	/* forward declaration */
	34	struct wl1271_tx_hw_descr;
	35	enum wl_rx_buf_align;
4158149c	36
c31be25a	37	struct wlcore_ops {
6f7dd16c	38	int (identify_chip)(struct wl1271 wl);
dd5512eb	39	int (boot)(struct wl1271 wl);
5d10b195 AN	40	void (trigger_cmd)(struct wl1271 wl, int cmd_box_addr,
5d10b195 AN	41	void *buf, size_t len);
f16ff758	42	void (ack_event)(struct wl1271 wl);
b3b4b4b8	43	u32 (calc_tx_blocks)(struct wl1271 wl, u32 len, u32 spare_blks);
4a3b97ee AN	44	void (set_tx_desc_blocks)(struct wl1271 wl,
	45	struct wl1271_tx_hw_descr *desc,
	46	u32 blks, u32 spare_blks);
6f266e91 AN	47	void (set_tx_desc_data_len)(struct wl1271 wl,
	48	struct wl1271_tx_hw_descr *desc,
	49	struct sk_buff *skb);
cd70f6a4 AN	50	enum wl_rx_buf_align (get_rx_buf_align)(struct wl1271 wl,
cd70f6a4 AN	51	u32 rx_desc);
b14684a0	52	void (prepare_read)(struct wl1271 wl, u32 rx_desc, u32 len);
4158149c AN	53	u32 (get_rx_packet_len)(struct wl1271 wl, void *rx_data,
4158149c AN	54	u32 data_len);
53d67a50 AN	55	void (tx_delayed_compl)(struct wl1271 wl);
53d67a50 AN	56	void (tx_immediate_compl)(struct wl1271 wl);
9d68d1ee	57	int (hw_init)(struct wl1271 wl);
8a9affc0	58	int (init_vif)(struct wl1271 wl, struct wl12xx_vif *wlvif);
fa7930af AN	59	u32 (sta_get_ap_rate_mask)(struct wl1271 wl,
fa7930af AN	60	struct wl12xx_vif *wlvif);
4ded91ce	61	s8 (get_pg_ver)(struct wl1271 wl);
30d9b4a5	62	void (get_mac)(struct wl1271 wl);
c31be25a LC	63	};
c31be25a LC	64
25a43d78 LC	65	enum wlcore_partitions {
	66	PART_DOWN,
	67	PART_WORK,
	68	PART_BOOT,
	69	PART_DRPW,
	70	PART_TOP_PRCM_ELP_SOC,
	71	PART_PHY_INIT,
	72
	73	PART_TABLE_LEN,
	74	};
	75
	76	struct wlcore_partition {
	77	u32 size;
	78	u32 start;
	79	};
	80
	81	struct wlcore_partition_set {
	82	struct wlcore_partition mem;
	83	struct wlcore_partition reg;
	84	struct wlcore_partition mem2;
	85	struct wlcore_partition mem3;
	86	};
	87
00782136 LC	88	enum wlcore_registers {
	89	/* register addresses, used with partition translation */
	90	REG_ECPU_CONTROL,
	91	REG_INTERRUPT_NO_CLEAR,
	92	REG_INTERRUPT_ACK,
	93	REG_COMMAND_MAILBOX_PTR,
	94	REG_EVENT_MAILBOX_PTR,
	95	REG_INTERRUPT_TRIG,
	96	REG_INTERRUPT_MASK,
	97	REG_PC_ON_RECOVERY,
	98	REG_CHIP_ID_B,
	99	REG_CMD_MBOX_ADDRESS,
	100
	101	/* data access memory addresses, used with partition translation */
	102	REG_SLV_MEM_DATA,
	103	REG_SLV_REG_DATA,
	104
	105	/* raw data access memory addresses */
	106	REG_RAW_FW_STATUS_ADDR,
	107
	108	REG_TABLE_LEN,
	109	};
	110
c31be25a LC	111	struct wl1271 {
	112	struct ieee80211_hw *hw;
	113	bool mac80211_registered;
	114
	115	struct device *dev;
	116
	117	void *if_priv;
	118
	119	struct wl1271_if_operations *if_ops;
	120
	121	void (*set_power)(bool enable);
	122	int irq;
	123	int ref_clock;
	124
	125	spinlock_t wl_lock;
	126
	127	enum wl1271_state state;
	128	enum wl12xx_fw_type fw_type;
	129	bool plt;
	130	u8 last_vif_count;
	131	struct mutex mutex;
	132
	133	unsigned long flags;
	134
25a43d78	135	struct wlcore_partition_set curr_part;
c31be25a LC	136
	137	struct wl1271_chip chip;
	138
	139	int cmd_box_addr;
c31be25a LC	140
	141	u8 *fw;
	142	size_t fw_len;
	143	void *nvs;
	144	size_t nvs_len;
	145
	146	s8 hw_pg_ver;
	147
	148	/* address read from the fuse ROM */
	149	u32 fuse_oui_addr;
	150	u32 fuse_nic_addr;
	151
	152	/* we have up to 2 MAC addresses */
	153	struct mac_address addresses[2];
	154	int channel;
	155	u8 system_hlid;
	156
	157	unsigned long links_map[BITS_TO_LONGS(WL12XX_MAX_LINKS)];
	158	unsigned long roles_map[BITS_TO_LONGS(WL12XX_MAX_ROLES)];
	159	unsigned long roc_map[BITS_TO_LONGS(WL12XX_MAX_ROLES)];
	160	unsigned long rate_policies_map[
	161	BITS_TO_LONGS(WL12XX_MAX_RATE_POLICIES)];
	162
	163	struct list_head wlvif_list;
	164
	165	u8 sta_count;
	166	u8 ap_count;
	167
	168	struct wl1271_acx_mem_map *target_mem_map;
	169
	170	/* Accounting for allocated / available TX blocks on HW */
	171	u32 tx_blocks_freed;
	172	u32 tx_blocks_available;
	173	u32 tx_allocated_blocks;
	174	u32 tx_results_count;
	175
c31be25a LC	176	/* Accounting for allocated / available Tx packets in HW */
	177	u32 tx_pkts_freed[NUM_TX_QUEUES];
	178	u32 tx_allocated_pkts[NUM_TX_QUEUES];
	179
	180	/* Transmitted TX packets counter for chipset interface */
	181	u32 tx_packets_count;
	182
	183	/* Time-offset between host and chipset clocks */
	184	s64 time_offset;
	185
	186	/* Frames scheduled for transmission, not handled yet */
	187	int tx_queue_count[NUM_TX_QUEUES];
	188	long stopped_queues_map;
	189
	190	/* Frames received, not handled yet by mac80211 */
	191	struct sk_buff_head deferred_rx_queue;
	192
	193	/* Frames sent, not returned yet to mac80211 */
	194	struct sk_buff_head deferred_tx_queue;
	195
	196	struct work_struct tx_work;
	197	struct workqueue_struct *freezable_wq;
	198
	199	/* Pending TX frames */
72b0624f AN	200	unsigned long tx_frames_map[BITS_TO_LONGS(WLCORE_MAX_TX_DESCRIPTORS)];
72b0624f AN	201	struct sk_buff *tx_frames[WLCORE_MAX_TX_DESCRIPTORS];
c31be25a LC	202	int tx_frames_cnt;
	203
	204	/* FW Rx counter */
	205	u32 rx_counter;
	206
	207	/* Rx memory pool address */
	208	struct wl1271_rx_mem_pool_addr rx_mem_pool_addr;
	209
	210	/* Intermediate buffer, used for packet aggregation */
	211	u8 *aggr_buf;
	212
	213	/* Reusable dummy packet template */
	214	struct sk_buff *dummy_packet;
	215
	216	/* Network stack work */
	217	struct work_struct netstack_work;
	218
	219	/* FW log buffer */
	220	u8 *fwlog;
	221
	222	/* Number of valid bytes in the FW log buffer */
	223	ssize_t fwlog_size;
	224
	225	/* Sysfs FW log entry readers wait queue */
	226	wait_queue_head_t fwlog_waitq;
	227
	228	/* Hardware recovery work */
	229	struct work_struct recovery_work;
	230
	231	/* Pointer that holds DMA-friendly block for the mailbox */
	232	struct event_mailbox *mbox;
	233
	234	/* The mbox event mask */
	235	u32 event_mask;
	236
	237	/* Mailbox pointers */
	238	u32 mbox_ptr[2];
	239
	240	/* Are we currently scanning */
	241	struct ieee80211_vif *scan_vif;
	242	struct wl1271_scan scan;
	243	struct delayed_work scan_complete_work;
	244
	245	bool sched_scanning;
	246
	247	/* The current band */
	248	enum ieee80211_band band;
	249
	250	struct completion *elp_compl;
	251	struct delayed_work elp_work;
	252
	253	/* in dBm */
	254	int power_level;
	255
	256	struct wl1271_stats stats;
	257
	258	__le32 buffer_32;
	259	u32 buffer_cmd;
	260	u32 buffer_busyword[WL1271_BUSY_WORD_CNT];
	261
	262	struct wl12xx_fw_status *fw_status;
	263	struct wl1271_tx_hw_res_if *tx_res_if;
	264
	265	/* Current chipset configuration */
e87288f0	266	struct wlcore_conf conf;
c31be25a LC	267
	268	bool sg_enabled;
	269
	270	bool enable_11a;
	271
	272	/* Most recently reported noise in dBm */
	273	s8 noise;
	274
	275	/* bands supported by this instance of wl12xx */
	276	struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
	277
	278	int tcxo_clock;
	279
	280	/*
	281	* wowlan trigger was configured during suspend.
	282	* (currently, only "ANY" trigger is supported)
	283	*/
	284	bool wow_enabled;
	285	bool irq_wake_enabled;
	286
	287	/*
	288	* AP-mode - links indexed by HLID. The global and broadcast links
	289	* are always active.
	290	*/
	291	struct wl1271_link links[WL12XX_MAX_LINKS];
	292
	293	/* AP-mode - a bitmap of links currently in PS mode according to FW */
	294	u32 ap_fw_ps_map;
	295
	296	/* AP-mode - a bitmap of links currently in PS mode in mac80211 */
	297	unsigned long ap_ps_map;
	298
	299	/* Quirks of specific hardware revisions */
	300	unsigned int quirks;
	301
	302	/* Platform limitations */
	303	unsigned int platform_quirks;
	304
	305	/* number of currently active RX BA sessions */
	306	int ba_rx_session_count;
	307
	308	/* AP-mode - number of currently connected stations */
	309	int active_sta_count;
	310
	311	/* last wlvif we transmitted from */
	312	struct wl12xx_vif *last_wlvif;
	313
	314	/* work to fire when Tx is stuck */
	315	struct delayed_work tx_watchdog_work;
	316
	317	struct wlcore_ops *ops;
25a43d78 LC	318	/* pointer to the lower driver partition table */
25a43d78 LC	319	const struct wlcore_partition_set *ptable;
00782136 LC	320	/* pointer to the lower driver register table */
00782136 LC	321	const int *rtable;
6f7dd16c LC	322	/* name of the firmwares to load - for PLT, single role, multi-role */
	323	const char *plt_fw_name;
	324	const char *sr_fw_name;
	325	const char *mr_fw_name;
96e0c683 AN	326
	327	/* per-chip-family private structure */
	328	void *priv;
72b0624f AN	329
	330	/* number of TX descriptors the HW supports. */
	331	u32 num_tx_desc;
3edab305 AN	332
	333	/* spare Tx blocks for normal/GEM operating modes */
	334	u32 normal_tx_spare;
	335	u32 gem_tx_spare;
43a8bc5a AN	336
	337	/* translate HW Tx rates to standard rate-indices */
	338	const u8 **band_rate_to_idx;
	339
	340	/* size of table for HW rates that can be received from chip */
	341	u8 hw_tx_rate_tbl_size;
	342
	343	/* this HW rate and below are considered HT rates for this chip */
	344	u8 hw_min_ht_rate;
c31be25a	345	};
ffeb501c LC	346
ffeb501c LC	347	int __devinit wlcore_probe(struct wl1271 wl, struct platform_device pdev);
b2ba99ff	348	int __devexit wlcore_remove(struct platform_device *pdev);
96e0c683	349	struct ieee80211_hw *wlcore_alloc_hw(size_t priv_size);
ffeb501c LC	350	int wlcore_free_hw(struct wl1271 *wl);
ffeb501c LC	351
00782136 LC	352	/* Firmware image load chunk size */
	353	#define CHUNK_SIZE 16384
	354
6f7dd16c LC	355	/* Quirks */
	356
	357	/* Each RX/TX transaction requires an end-of-transaction transfer */
	358	#define WLCORE_QUIRK_END_OF_TRANSACTION BIT(0)
	359
	360	/* wl127x and SPI don't support SDIO block size alignment */
f83985bb	361	#define WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN BIT(2)
6f7dd16c	362
5766435e AN	363	/* means aggregated Rx packets are aligned to a SDIO block */
	364	#define WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN BIT(3)
	365
6f7dd16c LC	366	/* Older firmwares did not implement the FW logger over bus feature */
	367	#define WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED BIT(4)
	368
d203e59c LC	369	/* Older firmwares use an old NVS format */
	370	#define WLCORE_QUIRK_LEGACY_NVS BIT(5)
	371
441101f6 LC	372	/* Some firmwares may not support ELP */
	373	#define WLCORE_QUIRK_NO_ELP BIT(6)
	374
00782136 LC	375	/* TODO: move to the lower drivers when all usages are abstracted */
	376	#define CHIP_ID_1271_PG10 (0x4030101)
	377	#define CHIP_ID_1271_PG20 (0x4030111)
	378	#define CHIP_ID_1283_PG10 (0x05030101)
	379	#define CHIP_ID_1283_PG20 (0x05030111)
	380
	381	/* TODO: move all these common registers and values elsewhere */
	382	#define HW_ACCESS_ELP_CTRL_REG 0x1FFFC
	383
	384	/* ELP register commands */
	385	#define ELPCTRL_WAKE_UP 0x1
	386	#define ELPCTRL_WAKE_UP_WLAN_READY 0x5
	387	#define ELPCTRL_SLEEP 0x0
	388	/* ELP WLAN_READY bit */
	389	#define ELPCTRL_WLAN_READY 0x2
	390
	391	/*************************************************************************
	392
	393	Interrupt Trigger Register (Host -> WiLink)
	394
	395	**************************************************************************/
	396
	397	/* Hardware to Embedded CPU Interrupts - first 32-bit register set */
	398
00782136 LC	399	/*
	400	* The host sets this bit to inform the Wlan
	401	* FW that a TX packet is in the XFER
	402	* Buffer #0.
	403	*/
	404	#define INTR_TRIG_TX_PROC0 BIT(2)
	405
	406	/*
	407	* The host sets this bit to inform the FW
	408	* that it read a packet from RX XFER
	409	* Buffer #0.
	410	*/
	411	#define INTR_TRIG_RX_PROC0 BIT(3)
	412
	413	#define INTR_TRIG_DEBUG_ACK BIT(4)
	414
	415	#define INTR_TRIG_STATE_CHANGED BIT(5)
	416
	417	/* Hardware to Embedded CPU Interrupts - second 32-bit register set */
	418
	419	/*
	420	* The host sets this bit to inform the FW
	421	* that it read a packet from RX XFER
	422	* Buffer #1.
	423	*/
	424	#define INTR_TRIG_RX_PROC1 BIT(17)
	425
	426	/*
	427	* The host sets this bit to inform the Wlan
	428	* hardware that a TX packet is in the XFER
	429	* Buffer #1.
	430	*/
	431	#define INTR_TRIG_TX_PROC1 BIT(18)
	432
	433	#define ACX_SLV_SOFT_RESET_BIT BIT(1)
	434	#define SOFT_RESET_MAX_TIME 1000000
	435	#define SOFT_RESET_STALL_TIME 1000
	436
	437	#define ECPU_CONTROL_HALT 0x00000101
b2ba99ff	438
6f7dd16c LC	439	#define WELP_ARM_COMMAND_VAL 0x4
6f7dd16c LC	440
b2ba99ff	441	#endif /* __WLCORE_H__ */