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wl1271: Remove smart reflex ACX
[deliverable/linux.git] / drivers / net / wireless / wl12xx / wl1271_acx.h
CommitLineData
f5fc0f86
LC		 1/*
2 * This file is part of wl1271
3 *
4 * Copyright (C) 1998-2009 Texas Instruments. All rights reserved.
5 * Copyright (C) 2008-2009 Nokia Corporation
6 *
7 * Contact: Luciano Coelho <luciano.coelho@nokia.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21 * 02110-1301 USA
22 *
23 */
24
25#ifndef __WL1271_ACX_H__
26#define __WL1271_ACX_H__
27
28#include "wl1271.h"
29#include "wl1271_cmd.h"
30
31/*************************************************************************
32
33 Host Interrupt Register (WiLink -> Host)
34
35**************************************************************************/
36/* HW Initiated interrupt Watchdog timer expiration */
37#define WL1271_ACX_INTR_WATCHDOG BIT(0)
38/* Init sequence is done (masked interrupt, detection through polling only ) */
39#define WL1271_ACX_INTR_INIT_COMPLETE BIT(1)
40/* Event was entered to Event MBOX #A*/
41#define WL1271_ACX_INTR_EVENT_A BIT(2)
42/* Event was entered to Event MBOX #B*/
43#define WL1271_ACX_INTR_EVENT_B BIT(3)
44/* Command processing completion*/
45#define WL1271_ACX_INTR_CMD_COMPLETE BIT(4)
46/* Signaling the host on HW wakeup */
47#define WL1271_ACX_INTR_HW_AVAILABLE BIT(5)
48/* The MISC bit is used for aggregation of RX, TxComplete and TX rate update */
49#define WL1271_ACX_INTR_DATA BIT(6)
50/* Trace meassge on MBOX #A */
51#define WL1271_ACX_INTR_TRACE_A BIT(7)
52/* Trace meassge on MBOX #B */
53#define WL1271_ACX_INTR_TRACE_B BIT(8)
54
55#define WL1271_ACX_INTR_ALL 0xFFFFFFFF
56#define WL1271_ACX_ALL_EVENTS_VECTOR (WL1271_ACX_INTR_WATCHDOG | \
57 WL1271_ACX_INTR_INIT_COMPLETE | \
58 WL1271_ACX_INTR_EVENT_A | \
59 WL1271_ACX_INTR_EVENT_B | \
60 WL1271_ACX_INTR_CMD_COMPLETE | \
61 WL1271_ACX_INTR_HW_AVAILABLE | \
62 WL1271_ACX_INTR_DATA)
63
37079a83
LC		 64#define WL1271_INTR_MASK (WL1271_ACX_INTR_EVENT_A | \
65 WL1271_ACX_INTR_EVENT_B | \
66 WL1271_ACX_INTR_HW_AVAILABLE | \
f5fc0f86
LC		 67 WL1271_ACX_INTR_DATA)
68
69/* Target's information element */
70struct acx_header {
71 struct wl1271_cmd_header cmd;
72
73 /* acx (or information element) header */
d0f63b20 74 __le16 id;
f5fc0f86
LC		 75
76 /* payload length (not including headers */
d0f63b20 77 __le16 len;
0b5b72da 78} __attribute__ ((packed));
f5fc0f86
LC		 79
80struct acx_error_counter {
81 struct acx_header header;
82
83 /* The number of PLCP errors since the last time this */
84 /* information element was interrogated. This field is */
85 /* automatically cleared when it is interrogated.*/
d0f63b20 86 __le32 PLCP_error;
f5fc0f86
LC		 87
88 /* The number of FCS errors since the last time this */
89 /* information element was interrogated. This field is */
90 /* automatically cleared when it is interrogated.*/
d0f63b20 91 __le32 FCS_error;
f5fc0f86
LC		 92
93 /* The number of MPDUs without PLCP header errors received*/
94 /* since the last time this information element was interrogated. */
95 /* This field is automatically cleared when it is interrogated.*/
d0f63b20 96 __le32 valid_frame;
f5fc0f86
LC		 97
98 /* the number of missed sequence numbers in the squentially */
99 /* values of frames seq numbers */
d0f63b20 100 __le32 seq_num_miss;
f5fc0f86
LC		 101} __attribute__ ((packed));
102
103struct acx_revision {
104 struct acx_header header;
105
106 /*
107 * The WiLink firmware version, an ASCII string x.x.x.x,
108 * that uniquely identifies the current firmware.
109 * The left most digit is incremented each time a
110 * significant change is made to the firmware, such as
111 * code redesign or new platform support.
112 * The second digit is incremented when major enhancements
113 * are added or major fixes are made.
114 * The third digit is incremented for each GA release.
115 * The fourth digit is incremented for each build.
116 * The first two digits identify a firmware release version,
117 * in other words, a unique set of features.
118 * The first three digits identify a GA release.
119 */
120 char fw_version[20];
121
122 /*
123 * This 4 byte field specifies the WiLink hardware version.
124 * bits 0 - 15: Reserved.
125 * bits 16 - 23: Version ID - The WiLink version ID
126 * (1 = first spin, 2 = second spin, and so on).
127 * bits 24 - 31: Chip ID - The WiLink chip ID.
128 */
d0f63b20 129 __le32 hw_version;
f5fc0f86
LC		 130} __attribute__ ((packed));
131
132enum wl1271_psm_mode {
133 /* Active mode */
134 WL1271_PSM_CAM = 0,
135
136 /* Power save mode */
137 WL1271_PSM_PS = 1,
138
139 /* Extreme low power */
140 WL1271_PSM_ELP = 2,
141};
142
143struct acx_sleep_auth {
144 struct acx_header header;
145
146 /* The sleep level authorization of the device. */
147 /* 0 - Always active*/
148 /* 1 - Power down mode: light / fast sleep*/
149 /* 2 - ELP mode: Deep / Max sleep*/
150 u8 sleep_auth;
151 u8 padding[3];
152} __attribute__ ((packed));
153
154enum {
155 HOSTIF_PCI_MASTER_HOST_INDIRECT,
156 HOSTIF_PCI_MASTER_HOST_DIRECT,
157 HOSTIF_SLAVE,
158 HOSTIF_PKT_RING,
159 HOSTIF_DONTCARE = 0xFF
160};
161
162#define DEFAULT_UCAST_PRIORITY 0
163#define DEFAULT_RX_Q_PRIORITY 0
164#define DEFAULT_NUM_STATIONS 1
165#define DEFAULT_RXQ_PRIORITY 0 /* low 0 .. 15 high */
166#define DEFAULT_RXQ_TYPE 0x07 /* All frames, Data/Ctrl/Mgmt */
167#define TRACE_BUFFER_MAX_SIZE 256
168
169#define DP_RX_PACKET_RING_CHUNK_SIZE 1600
170#define DP_TX_PACKET_RING_CHUNK_SIZE 1600
171#define DP_RX_PACKET_RING_CHUNK_NUM 2
172#define DP_TX_PACKET_RING_CHUNK_NUM 2
173#define DP_TX_COMPLETE_TIME_OUT 20
f5fc0f86
LC		 174
175#define TX_MSDU_LIFETIME_MIN 0
176#define TX_MSDU_LIFETIME_MAX 3000
177#define TX_MSDU_LIFETIME_DEF 512
178#define RX_MSDU_LIFETIME_MIN 0
179#define RX_MSDU_LIFETIME_MAX 0xFFFFFFFF
180#define RX_MSDU_LIFETIME_DEF 512000
181
182struct acx_rx_msdu_lifetime {
183 struct acx_header header;
184
185 /*
186 * The maximum amount of time, in TU, before the
187 * firmware discards the MSDU.
188 */
d0f63b20 189 __le32 lifetime;
f5fc0f86
LC		 190} __attribute__ ((packed));
191
192/*
193 * RX Config Options Table
194 * Bit Definition
195 * === ==========
196 * 31:14 Reserved
197 * 13 Copy RX Status - when set, write three receive status words
198 * to top of rx'd MPDUs.
199 * When cleared, do not write three status words (added rev 1.5)
200 * 12 Reserved
201 * 11 RX Complete upon FCS error - when set, give rx complete
202 * interrupt for FCS errors, after the rx filtering, e.g. unicast
203 * frames not to us with FCS error will not generate an interrupt.
204 * 10 SSID Filter Enable - When set, the WiLink discards all beacon,
205 * probe request, and probe response frames with an SSID that does
206 * not match the SSID specified by the host in the START/JOIN
207 * command.
208 * When clear, the WiLink receives frames with any SSID.
209 * 9 Broadcast Filter Enable - When set, the WiLink discards all
210 * broadcast frames. When clear, the WiLink receives all received
211 * broadcast frames.
212 * 8:6 Reserved
213 * 5 BSSID Filter Enable - When set, the WiLink discards any frames
214 * with a BSSID that does not match the BSSID specified by the
215 * host.
216 * When clear, the WiLink receives frames from any BSSID.
217 * 4 MAC Addr Filter - When set, the WiLink discards any frames
218 * with a destination address that does not match the MAC address
219 * of the adaptor.
220 * When clear, the WiLink receives frames destined to any MAC
221 * address.
222 * 3 Promiscuous - When set, the WiLink receives all valid frames
223 * (i.e., all frames that pass the FCS check).
224 * When clear, only frames that pass the other filters specified
225 * are received.
226 * 2 FCS - When set, the WiLink includes the FCS with the received
227 * frame.
228 * When cleared, the FCS is discarded.
229 * 1 PLCP header - When set, write all data from baseband to frame
230 * buffer including PHY header.
231 * 0 Reserved - Always equal to 0.
232 *
233 * RX Filter Options Table
234 * Bit Definition
235 * === ==========
236 * 31:12 Reserved - Always equal to 0.
237 * 11 Association - When set, the WiLink receives all association
238 * related frames (association request/response, reassocation
239 * request/response, and disassociation). When clear, these frames
240 * are discarded.
241 * 10 Auth/De auth - When set, the WiLink receives all authentication
242 * and de-authentication frames. When clear, these frames are
243 * discarded.
244 * 9 Beacon - When set, the WiLink receives all beacon frames.
245 * When clear, these frames are discarded.
246 * 8 Contention Free - When set, the WiLink receives all contention
247 * free frames.
248 * When clear, these frames are discarded.
249 * 7 Control - When set, the WiLink receives all control frames.
250 * When clear, these frames are discarded.
251 * 6 Data - When set, the WiLink receives all data frames.
252 * When clear, these frames are discarded.
253 * 5 FCS Error - When set, the WiLink receives frames that have FCS
254 * errors.
255 * When clear, these frames are discarded.
256 * 4 Management - When set, the WiLink receives all management
257 * frames.
258 * When clear, these frames are discarded.
259 * 3 Probe Request - When set, the WiLink receives all probe request
260 * frames.
261 * When clear, these frames are discarded.
262 * 2 Probe Response - When set, the WiLink receives all probe
263 * response frames.
264 * When clear, these frames are discarded.
265 * 1 RTS/CTS/ACK - When set, the WiLink receives all RTS, CTS and ACK
266 * frames.
267 * When clear, these frames are discarded.
268 * 0 Rsvd Type/Sub Type - When set, the WiLink receives all frames
269 * that have reserved frame types and sub types as defined by the
270 * 802.11 specification.
271 * When clear, these frames are discarded.
272 */
273struct acx_rx_config {
274 struct acx_header header;
275
d0f63b20
LC		 276 __le32 config_options;
277 __le32 filter_options;
f5fc0f86
LC		 278} __attribute__ ((packed));
279
280struct acx_packet_detection {
281 struct acx_header header;
282
d0f63b20 283 __le32 threshold;
f5fc0f86
LC		 284} __attribute__ ((packed));
285
286
287enum acx_slot_type {
288 SLOT_TIME_LONG = 0,
289 SLOT_TIME_SHORT = 1,
290 DEFAULT_SLOT_TIME = SLOT_TIME_SHORT,
291 MAX_SLOT_TIMES = 0xFF
292};
293
294#define STATION_WONE_INDEX 0
295
296struct acx_slot {
297 struct acx_header header;
298
299 u8 wone_index; /* Reserved */
300 u8 slot_time;
301 u8 reserved[6];
302} __attribute__ ((packed));
303
304
c87dec9f
JO		 305#define ACX_MC_ADDRESS_GROUP_MAX (8)
306#define ADDRESS_GROUP_MAX_LEN (ETH_ALEN * ACX_MC_ADDRESS_GROUP_MAX)
f5fc0f86
LC		 307
308struct acx_dot11_grp_addr_tbl {
309 struct acx_header header;
310
311 u8 enabled;
312 u8 num_groups;
313 u8 pad[2];
314 u8 mac_table[ADDRESS_GROUP_MAX_LEN];
315} __attribute__ ((packed));
316
f5fc0f86
LC		 317struct acx_rx_timeout {
318 struct acx_header header;
319
d0f63b20
LC		 320 __le16 ps_poll_timeout;
321 __le16 upsd_timeout;
f5fc0f86
LC		 322} __attribute__ ((packed));
323
f5fc0f86
LC		 324struct acx_rts_threshold {
325 struct acx_header header;
326
d0f63b20 327 __le16 threshold;
f5fc0f86
LC		 328 u8 pad[2];
329} __attribute__ ((packed));
330
331struct acx_beacon_filter_option {
332 struct acx_header header;
333
334 u8 enable;
335
336 /*
337 * The number of beacons without the unicast TIM
338 * bit set that the firmware buffers before
339 * signaling the host about ready frames.
340 * When set to 0 and the filter is enabled, beacons
341 * without the unicast TIM bit set are dropped.
342 */
343 u8 max_num_beacons;
344 u8 pad[2];
345} __attribute__ ((packed));
346
347/*
348 * ACXBeaconFilterEntry (not 221)
349 * Byte Offset Size (Bytes) Definition
350 * =========== ============ ==========
351 * 0 1 IE identifier
352 * 1 1 Treatment bit mask
353 *
354 * ACXBeaconFilterEntry (221)
355 * Byte Offset Size (Bytes) Definition
356 * =========== ============ ==========
357 * 0 1 IE identifier
358 * 1 1 Treatment bit mask
359 * 2 3 OUI
360 * 5 1 Type
361 * 6 2 Version
362 *
363 *
364 * Treatment bit mask - The information element handling:
365 * bit 0 - The information element is compared and transferred
366 * in case of change.
367 * bit 1 - The information element is transferred to the host
368 * with each appearance or disappearance.
369 * Note that both bits can be set at the same time.
370 */
371#define BEACON_FILTER_TABLE_MAX_IE_NUM (32)
372#define BEACON_FILTER_TABLE_MAX_VENDOR_SPECIFIC_IE_NUM (6)
373#define BEACON_FILTER_TABLE_IE_ENTRY_SIZE (2)
374#define BEACON_FILTER_TABLE_EXTRA_VENDOR_SPECIFIC_IE_SIZE (6)
375#define BEACON_FILTER_TABLE_MAX_SIZE ((BEACON_FILTER_TABLE_MAX_IE_NUM * \
376 BEACON_FILTER_TABLE_IE_ENTRY_SIZE) + \
377 (BEACON_FILTER_TABLE_MAX_VENDOR_SPECIFIC_IE_NUM * \
378 BEACON_FILTER_TABLE_EXTRA_VENDOR_SPECIFIC_IE_SIZE))
379
380struct acx_beacon_filter_ie_table {
381 struct acx_header header;
382
383 u8 num_ie;
384 u8 table[BEACON_FILTER_TABLE_MAX_SIZE];
385 u8 pad[3];
386} __attribute__ ((packed));
387
34415236
JO		 388struct acx_conn_monit_params {
389 struct acx_header header;
390
d0f63b20
LC		 391 __le32 synch_fail_thold; /* number of beacons missed */
392 __le32 bss_lose_timeout; /* number of TU's from synch fail */
0b5b72da 393} __attribute__ ((packed));
34415236 394
f5fc0f86
LC		 395enum {
396 SG_ENABLE = 0,
397 SG_DISABLE,
398 SG_SENSE_NO_ACTIVITY,
399 SG_SENSE_ACTIVE
400};
401
402struct acx_bt_wlan_coex {
403 struct acx_header header;
404
405 /*
406 * 0 -> PTA enabled
407 * 1 -> PTA disabled
408 * 2 -> sense no active mode, i.e.
409 * an interrupt is sent upon
410 * BT activity.
411 * 3 -> PTA is switched on in response
412 * to the interrupt sending.
413 */
414 u8 enable;
415 u8 pad[3];
416} __attribute__ ((packed));
417
6e92b416
LC		 418struct acx_dco_itrim_params {
419 struct acx_header header;
420
421 u8 enable;
422 u8 padding[3];
423 __le32 timeout;
424} __attribute__ ((packed));
425
f5fc0f86
LC		 426#define PTA_ANTENNA_TYPE_DEF (0)
427#define PTA_BT_HP_MAXTIME_DEF (2000)
428#define PTA_WLAN_HP_MAX_TIME_DEF (5000)
429#define PTA_SENSE_DISABLE_TIMER_DEF (1350)
430#define PTA_PROTECTIVE_RX_TIME_DEF (1500)
431#define PTA_PROTECTIVE_TX_TIME_DEF (1500)
432#define PTA_TIMEOUT_NEXT_BT_LP_PACKET_DEF (3000)
433#define PTA_SIGNALING_TYPE_DEF (1)
434#define PTA_AFH_LEVERAGE_ON_DEF (0)
435#define PTA_NUMBER_QUIET_CYCLE_DEF (0)
436#define PTA_MAX_NUM_CTS_DEF (3)
437#define PTA_NUMBER_OF_WLAN_PACKETS_DEF (2)
438#define PTA_NUMBER_OF_BT_PACKETS_DEF (2)
439#define PTA_PROTECTIVE_RX_TIME_FAST_DEF (1500)
440#define PTA_PROTECTIVE_TX_TIME_FAST_DEF (3000)
441#define PTA_CYCLE_TIME_FAST_DEF (8700)
442#define PTA_RX_FOR_AVALANCHE_DEF (5)
443#define PTA_ELP_HP_DEF (0)
444#define PTA_ANTI_STARVE_PERIOD_DEF (500)
445#define PTA_ANTI_STARVE_NUM_CYCLE_DEF (4)
446#define PTA_ALLOW_PA_SD_DEF (1)
447#define PTA_TIME_BEFORE_BEACON_DEF (6300)
448#define PTA_HPDM_MAX_TIME_DEF (1600)
449#define PTA_TIME_OUT_NEXT_WLAN_DEF (2550)
450#define PTA_AUTO_MODE_NO_CTS_DEF (0)
451#define PTA_BT_HP_RESPECTED_DEF (3)
452#define PTA_WLAN_RX_MIN_RATE_DEF (24)
453#define PTA_ACK_MODE_DEF (1)
454
455struct acx_bt_wlan_coex_param {
456 struct acx_header header;
457
d0f63b20
LC		 458 __le32 per_threshold;
459 __le32 max_scan_compensation_time;
460 __le16 nfs_sample_interval;
2b60100b
JO		 461 u8 load_ratio;
462 u8 auto_ps_mode;
463 u8 probe_req_compensation;
464 u8 scan_window_compensation;
465 u8 antenna_config;
466 u8 beacon_miss_threshold;
d0f63b20 467 __le32 rate_adaptation_threshold;
2b60100b
JO		 468 s8 rate_adaptation_snr;
469 u8 padding[3];
f5fc0f86
LC		 470} __attribute__ ((packed));
471
f5fc0f86
LC		 472struct acx_energy_detection {
473 struct acx_header header;
474
475 /* The RX Clear Channel Assessment threshold in the PHY */
d0f63b20 476 __le16 rx_cca_threshold;
f5fc0f86
LC		 477 u8 tx_energy_detection;
478 u8 pad;
479} __attribute__ ((packed));
480
f5fc0f86
LC		 481struct acx_beacon_broadcast {
482 struct acx_header header;
483
d0f63b20
LC		 484 __le16 beacon_rx_timeout;
485 __le16 broadcast_timeout;
f5fc0f86
LC		 486
487 /* Enables receiving of broadcast packets in PS mode */
488 u8 rx_broadcast_in_ps;
489
490 /* Consecutive PS Poll failures before updating the host */
491 u8 ps_poll_threshold;
492 u8 pad[2];
493} __attribute__ ((packed));
494
495struct acx_event_mask {
496 struct acx_header header;
497
d0f63b20
LC		 498 __le32 event_mask;
499 __le32 high_event_mask; /* Unused */
f5fc0f86
LC		 500} __attribute__ ((packed));
501
502#define CFG_RX_FCS BIT(2)
503#define CFG_RX_ALL_GOOD BIT(3)
504#define CFG_UNI_FILTER_EN BIT(4)
505#define CFG_BSSID_FILTER_EN BIT(5)
506#define CFG_MC_FILTER_EN BIT(6)
507#define CFG_MC_ADDR0_EN BIT(7)
508#define CFG_MC_ADDR1_EN BIT(8)
509#define CFG_BC_REJECT_EN BIT(9)
510#define CFG_SSID_FILTER_EN BIT(10)
511#define CFG_RX_INT_FCS_ERROR BIT(11)
512#define CFG_RX_INT_ENCRYPTED BIT(12)
513#define CFG_RX_WR_RX_STATUS BIT(13)
514#define CFG_RX_FILTER_NULTI BIT(14)
515#define CFG_RX_RESERVE BIT(15)
516#define CFG_RX_TIMESTAMP_TSF BIT(16)
517
518#define CFG_RX_RSV_EN BIT(0)
519#define CFG_RX_RCTS_ACK BIT(1)
520#define CFG_RX_PRSP_EN BIT(2)
521#define CFG_RX_PREQ_EN BIT(3)
522#define CFG_RX_MGMT_EN BIT(4)
523#define CFG_RX_FCS_ERROR BIT(5)
524#define CFG_RX_DATA_EN BIT(6)
525#define CFG_RX_CTL_EN BIT(7)
526#define CFG_RX_CF_EN BIT(8)
527#define CFG_RX_BCN_EN BIT(9)
528#define CFG_RX_AUTH_EN BIT(10)
529#define CFG_RX_ASSOC_EN BIT(11)
530
531#define SCAN_PASSIVE BIT(0)
532#define SCAN_5GHZ_BAND BIT(1)
533#define SCAN_TRIGGERED BIT(2)
534#define SCAN_PRIORITY_HIGH BIT(3)
535
2b60100b
JO		 536/* When set, disable HW encryption */
537#define DF_ENCRYPTION_DISABLE 0x01
538#define DF_SNIFF_MODE_ENABLE 0x80
539
f5fc0f86
LC		 540struct acx_feature_config {
541 struct acx_header header;
542
d0f63b20
LC		 543 __le32 options;
544 __le32 data_flow_options;
f5fc0f86
LC		 545} __attribute__ ((packed));
546
547struct acx_current_tx_power {
548 struct acx_header header;
549
550 u8 current_tx_power;
551 u8 padding[3];
552} __attribute__ ((packed));
553
f5fc0f86
LC		 554struct acx_wake_up_condition {
555 struct acx_header header;
556
557 u8 wake_up_event; /* Only one bit can be set */
558 u8 listen_interval;
559 u8 pad[2];
560} __attribute__ ((packed));
561
562struct acx_aid {
563 struct acx_header header;
564
565 /*
566 * To be set when associated with an AP.
567 */
d0f63b20 568 __le16 aid;
f5fc0f86
LC		 569 u8 pad[2];
570} __attribute__ ((packed));
571
572enum acx_preamble_type {
573 ACX_PREAMBLE_LONG = 0,
574 ACX_PREAMBLE_SHORT = 1
575};
576
577struct acx_preamble {
578 struct acx_header header;
579
580 /*
581 * When set, the WiLink transmits the frames with a short preamble and
582 * when cleared, the WiLink transmits the frames with a long preamble.
583 */
584 u8 preamble;
585 u8 padding[3];
586} __attribute__ ((packed));
587
588enum acx_ctsprotect_type {
589 CTSPROTECT_DISABLE = 0,
590 CTSPROTECT_ENABLE = 1
591};
592
593struct acx_ctsprotect {
594 struct acx_header header;
595 u8 ctsprotect;
596 u8 padding[3];
597} __attribute__ ((packed));
598
599struct acx_tx_statistics {
d0f63b20 600 __le32 internal_desc_overflow;
f5fc0f86
LC		 601} __attribute__ ((packed));
602
603struct acx_rx_statistics {
d0f63b20
LC		 604 __le32 out_of_mem;
605 __le32 hdr_overflow;
606 __le32 hw_stuck;
607 __le32 dropped;
608 __le32 fcs_err;
609 __le32 xfr_hint_trig;
610 __le32 path_reset;
611 __le32 reset_counter;
f5fc0f86
LC		 612} __attribute__ ((packed));
613
614struct acx_dma_statistics {
d0f63b20
LC		 615 __le32 rx_requested;
616 __le32 rx_errors;
617 __le32 tx_requested;
618 __le32 tx_errors;
f5fc0f86
LC		 619} __attribute__ ((packed));
620
621struct acx_isr_statistics {
622 /* host command complete */
d0f63b20 623 __le32 cmd_cmplt;
f5fc0f86
LC		 624
625 /* fiqisr() */
d0f63b20 626 __le32 fiqs;
f5fc0f86
LC		 627
628 /* (INT_STS_ND & INT_TRIG_RX_HEADER) */
d0f63b20 629 __le32 rx_headers;
f5fc0f86
LC		 630
631 /* (INT_STS_ND & INT_TRIG_RX_CMPLT) */
d0f63b20 632 __le32 rx_completes;
f5fc0f86
LC		 633
634 /* (INT_STS_ND & INT_TRIG_NO_RX_BUF) */
d0f63b20 635 __le32 rx_mem_overflow;
f5fc0f86
LC		 636
637 /* (INT_STS_ND & INT_TRIG_S_RX_RDY) */
d0f63b20 638 __le32 rx_rdys;
f5fc0f86
LC		 639
640 /* irqisr() */
d0f63b20 641 __le32 irqs;
f5fc0f86
LC		 642
643 /* (INT_STS_ND & INT_TRIG_TX_PROC) */
d0f63b20 644 __le32 tx_procs;
f5fc0f86
LC		 645
646 /* (INT_STS_ND & INT_TRIG_DECRYPT_DONE) */
d0f63b20 647 __le32 decrypt_done;
f5fc0f86
LC		 648
649 /* (INT_STS_ND & INT_TRIG_DMA0) */
d0f63b20 650 __le32 dma0_done;
f5fc0f86
LC		 651
652 /* (INT_STS_ND & INT_TRIG_DMA1) */
d0f63b20 653 __le32 dma1_done;
f5fc0f86
LC		 654
655 /* (INT_STS_ND & INT_TRIG_TX_EXC_CMPLT) */
d0f63b20 656 __le32 tx_exch_complete;
f5fc0f86
LC		 657
658 /* (INT_STS_ND & INT_TRIG_COMMAND) */
d0f63b20 659 __le32 commands;
f5fc0f86
LC		 660
661 /* (INT_STS_ND & INT_TRIG_RX_PROC) */
d0f63b20 662 __le32 rx_procs;
f5fc0f86
LC		 663
664 /* (INT_STS_ND & INT_TRIG_PM_802) */
d0f63b20 665 __le32 hw_pm_mode_changes;
f5fc0f86
LC		 666
667 /* (INT_STS_ND & INT_TRIG_ACKNOWLEDGE) */
d0f63b20 668 __le32 host_acknowledges;
f5fc0f86
LC		 669
670 /* (INT_STS_ND & INT_TRIG_PM_PCI) */
d0f63b20 671 __le32 pci_pm;
f5fc0f86
LC		 672
673 /* (INT_STS_ND & INT_TRIG_ACM_WAKEUP) */
d0f63b20 674 __le32 wakeups;
f5fc0f86
LC		 675
676 /* (INT_STS_ND & INT_TRIG_LOW_RSSI) */
d0f63b20 677 __le32 low_rssi;
f5fc0f86
LC		 678} __attribute__ ((packed));
679
680struct acx_wep_statistics {
681 /* WEP address keys configured */
d0f63b20 682 __le32 addr_key_count;
f5fc0f86
LC		 683
684 /* default keys configured */
d0f63b20 685 __le32 default_key_count;
f5fc0f86 686
d0f63b20 687 __le32 reserved;
f5fc0f86
LC		 688
689 /* number of times that WEP key not found on lookup */
d0f63b20 690 __le32 key_not_found;
f5fc0f86
LC		 691
692 /* number of times that WEP key decryption failed */
d0f63b20 693 __le32 decrypt_fail;
f5fc0f86
LC		 694
695 /* WEP packets decrypted */
d0f63b20 696 __le32 packets;
f5fc0f86
LC		 697
698 /* WEP decrypt interrupts */
d0f63b20 699 __le32 interrupt;
f5fc0f86
LC		 700} __attribute__ ((packed));
701
702#define ACX_MISSED_BEACONS_SPREAD 10
703
704struct acx_pwr_statistics {
705 /* the amount of enters into power save mode (both PD & ELP) */
d0f63b20 706 __le32 ps_enter;
f5fc0f86
LC		 707
708 /* the amount of enters into ELP mode */
d0f63b20 709 __le32 elp_enter;
f5fc0f86
LC		 710
711 /* the amount of missing beacon interrupts to the host */
d0f63b20 712 __le32 missing_bcns;
f5fc0f86
LC		 713
714 /* the amount of wake on host-access times */
d0f63b20 715 __le32 wake_on_host;
f5fc0f86
LC		 716
717 /* the amount of wake on timer-expire */
d0f63b20 718 __le32 wake_on_timer_exp;
f5fc0f86
LC		 719
720 /* the number of packets that were transmitted with PS bit set */
d0f63b20 721 __le32 tx_with_ps;
f5fc0f86
LC		 722
723 /* the number of packets that were transmitted with PS bit clear */
d0f63b20 724 __le32 tx_without_ps;
f5fc0f86
LC		 725
726 /* the number of received beacons */
d0f63b20 727 __le32 rcvd_beacons;
f5fc0f86
LC		 728
729 /* the number of entering into PowerOn (power save off) */
d0f63b20 730 __le32 power_save_off;
f5fc0f86
LC		 731
732 /* the number of entries into power save mode */
d0f63b20 733 __le16 enable_ps;
f5fc0f86
LC		 734
735 /*
736 * the number of exits from power save, not including failed PS
737 * transitions
738 */
d0f63b20 739 __le16 disable_ps;
f5fc0f86
LC		 740
741 /*
742 * the number of times the TSF counter was adjusted because
743 * of drift
744 */
d0f63b20 745 __le32 fix_tsf_ps;
f5fc0f86
LC		 746
747 /* Gives statistics about the spread continuous missed beacons.
748 * The 16 LSB are dedicated for the PS mode.
749 * The 16 MSB are dedicated for the PS mode.
750 * cont_miss_bcns_spread[0] - single missed beacon.
751 * cont_miss_bcns_spread[1] - two continuous missed beacons.
752 * cont_miss_bcns_spread[2] - three continuous missed beacons.
753 * ...
754 * cont_miss_bcns_spread[9] - ten and more continuous missed beacons.
755 */
d0f63b20 756 __le32 cont_miss_bcns_spread[ACX_MISSED_BEACONS_SPREAD];
f5fc0f86
LC		 757
758 /* the number of beacons in awake mode */
d0f63b20 759 __le32 rcvd_awake_beacons;
f5fc0f86
LC		 760} __attribute__ ((packed));
761
762struct acx_mic_statistics {
d0f63b20
LC		 763 __le32 rx_pkts;
764 __le32 calc_failure;
f5fc0f86
LC		 765} __attribute__ ((packed));
766
767struct acx_aes_statistics {
d0f63b20
LC		 768 __le32 encrypt_fail;
769 __le32 decrypt_fail;
770 __le32 encrypt_packets;
771 __le32 decrypt_packets;
772 __le32 encrypt_interrupt;
773 __le32 decrypt_interrupt;
f5fc0f86
LC		 774} __attribute__ ((packed));
775
776struct acx_event_statistics {
d0f63b20
LC		 777 __le32 heart_beat;
778 __le32 calibration;
779 __le32 rx_mismatch;
780 __le32 rx_mem_empty;
781 __le32 rx_pool;
782 __le32 oom_late;
783 __le32 phy_transmit_error;
784 __le32 tx_stuck;
f5fc0f86
LC		 785} __attribute__ ((packed));
786
787struct acx_ps_statistics {
d0f63b20
LC		 788 __le32 pspoll_timeouts;
789 __le32 upsd_timeouts;
790 __le32 upsd_max_sptime;
791 __le32 upsd_max_apturn;
792 __le32 pspoll_max_apturn;
793 __le32 pspoll_utilization;
794 __le32 upsd_utilization;
f5fc0f86
LC		 795} __attribute__ ((packed));
796
797struct acx_rxpipe_statistics {
d0f63b20
LC		 798 __le32 rx_prep_beacon_drop;
799 __le32 descr_host_int_trig_rx_data;
800 __le32 beacon_buffer_thres_host_int_trig_rx_data;
801 __le32 missed_beacon_host_int_trig_rx_data;
802 __le32 tx_xfr_host_int_trig_rx_data;
f5fc0f86
LC		 803} __attribute__ ((packed));
804
805struct acx_statistics {
806 struct acx_header header;
807
808 struct acx_tx_statistics tx;
809 struct acx_rx_statistics rx;
810 struct acx_dma_statistics dma;
811 struct acx_isr_statistics isr;
812 struct acx_wep_statistics wep;
813 struct acx_pwr_statistics pwr;
814 struct acx_aes_statistics aes;
815 struct acx_mic_statistics mic;
816 struct acx_event_statistics event;
817 struct acx_ps_statistics ps;
818 struct acx_rxpipe_statistics rxpipe;
819} __attribute__ ((packed));
820
f5fc0f86 821struct acx_rate_class {
d0f63b20 822 __le32 enabled_rates;
f5fc0f86
LC		 823 u8 short_retry_limit;
824 u8 long_retry_limit;
825 u8 aflags;
826 u8 reserved;
827};
828
829struct acx_rate_policy {
830 struct acx_header header;
831
d0f63b20 832 __le32 rate_class_cnt;
45b531a8 833 struct acx_rate_class rate_class[CONF_TX_MAX_RATE_CLASSES];
f5fc0f86
LC		 834} __attribute__ ((packed));
835
f5fc0f86
LC		 836struct acx_ac_cfg {
837 struct acx_header header;
838 u8 ac;
839 u8 cw_min;
d0f63b20 840 __le16 cw_max;
f5fc0f86
LC		 841 u8 aifsn;
842 u8 reserved;
d0f63b20 843 __le16 tx_op_limit;
f5fc0f86
LC		 844} __attribute__ ((packed));
845
f5fc0f86
LC		 846struct acx_tid_config {
847 struct acx_header header;
848 u8 queue_id;
849 u8 channel_type;
850 u8 tsid;
851 u8 ps_scheme;
852 u8 ack_policy;
853 u8 padding[3];
d0f63b20 854 __le32 apsd_conf[2];
f5fc0f86
LC		 855} __attribute__ ((packed));
856
857struct acx_frag_threshold {
858 struct acx_header header;
d0f63b20 859 __le16 frag_threshold;
f5fc0f86
LC		 860 u8 padding[2];
861} __attribute__ ((packed));
862
f5fc0f86
LC		 863struct acx_tx_config_options {
864 struct acx_header header;
d0f63b20
LC		 865 __le16 tx_compl_timeout; /* msec */
866 __le16 tx_compl_threshold; /* number of packets */
f5fc0f86
LC		 867} __attribute__ ((packed));
868
3ed8f2c6
LC		 869#define ACX_RX_MEM_BLOCKS 70
870#define ACX_TX_MIN_MEM_BLOCKS 40
f5fc0f86
LC		 871#define ACX_TX_DESCRIPTORS 32
872#define ACX_NUM_SSID_PROFILES 1
873
874struct wl1271_acx_config_memory {
875 struct acx_header header;
876
877 u8 rx_mem_block_num;
878 u8 tx_min_mem_block_num;
879 u8 num_stations;
880 u8 num_ssid_profiles;
d0f63b20 881 __le32 total_tx_descriptors;
f5fc0f86
LC		 882} __attribute__ ((packed));
883
884struct wl1271_acx_mem_map {
885 struct acx_header header;
886
d0f63b20
LC		 887 __le32 code_start;
888 __le32 code_end;
f5fc0f86 889
d0f63b20
LC		 890 __le32 wep_defkey_start;
891 __le32 wep_defkey_end;
f5fc0f86 892
d0f63b20
LC		 893 __le32 sta_table_start;
894 __le32 sta_table_end;
f5fc0f86 895
d0f63b20
LC		 896 __le32 packet_template_start;
897 __le32 packet_template_end;
f5fc0f86
LC		 898
899 /* Address of the TX result interface (control block) */
d0f63b20
LC		 900 __le32 tx_result;
901 __le32 tx_result_queue_start;
f5fc0f86 902
d0f63b20
LC		 903 __le32 queue_memory_start;
904 __le32 queue_memory_end;
f5fc0f86 905
d0f63b20
LC		 906 __le32 packet_memory_pool_start;
907 __le32 packet_memory_pool_end;
f5fc0f86 908
d0f63b20
LC		 909 __le32 debug_buffer1_start;
910 __le32 debug_buffer1_end;
f5fc0f86 911
d0f63b20
LC		 912 __le32 debug_buffer2_start;
913 __le32 debug_buffer2_end;
f5fc0f86
LC		 914
915 /* Number of blocks FW allocated for TX packets */
d0f63b20 916 __le32 num_tx_mem_blocks;
f5fc0f86
LC		 917
918 /* Number of blocks FW allocated for RX packets */
d0f63b20 919 __le32 num_rx_mem_blocks;
f5fc0f86
LC		 920
921 /* the following 4 fields are valid in SLAVE mode only */
922 u8 *tx_cbuf;
923 u8 *rx_cbuf;
d0f63b20
LC		 924 __le32 rx_ctrl;
925 __le32 tx_ctrl;
f5fc0f86
LC		 926} __attribute__ ((packed));
927
f5fc0f86
LC		 928struct wl1271_acx_rx_config_opt {
929 struct acx_header header;
930
d0f63b20
LC		 931 __le16 mblk_threshold;
932 __le16 threshold;
933 __le16 timeout;
f5fc0f86
LC		 934 u8 queue_type;
935 u8 reserved;
936} __attribute__ ((packed));
937
11f70f97
JO		 938
939struct wl1271_acx_bet_enable {
940 struct acx_header header;
941
942 u8 enable;
943 u8 max_consecutive;
944 u8 padding[2];
945} __attribute__ ((packed));
946
01c09162
JO		 947#define ACX_IPV4_VERSION 4
948#define ACX_IPV6_VERSION 6
949#define ACX_IPV4_ADDR_SIZE 4
950struct wl1271_acx_arp_filter {
951 struct acx_header header;
952 u8 version; /* ACX_IPV4_VERSION, ACX_IPV6_VERSION */
953 u8 enable; /* 1 to enable ARP filtering, 0 to disable */
954 u8 padding[2];
955 u8 address[16]; /* The configured device IP address - all ARP
956 requests directed to this IP address will pass
957 through. For IPv4, the first four bytes are
958 used. */
959} __attribute__((packed));
960
961
f5fc0f86
LC		 962enum {
963 ACX_WAKE_UP_CONDITIONS = 0x0002,
964 ACX_MEM_CFG = 0x0003,
965 ACX_SLOT = 0x0004,
966 ACX_AC_CFG = 0x0007,
967 ACX_MEM_MAP = 0x0008,
968 ACX_AID = 0x000A,
969 /* ACX_FW_REV is missing in the ref driver, but seems to work */
970 ACX_FW_REV = 0x000D,
971 ACX_MEDIUM_USAGE = 0x000F,
972 ACX_RX_CFG = 0x0010,
973 ACX_TX_QUEUE_CFG = 0x0011, /* FIXME: only used by wl1251 */
974 ACX_STATISTICS = 0x0013, /* Debug API */
975 ACX_PWR_CONSUMPTION_STATISTICS = 0x0014,
976 ACX_FEATURE_CFG = 0x0015,
977 ACX_TID_CFG = 0x001A,
978 ACX_PS_RX_STREAMING = 0x001B,
979 ACX_BEACON_FILTER_OPT = 0x001F,
980 ACX_NOISE_HIST = 0x0021,
981 ACX_HDK_VERSION = 0x0022, /* ??? */
982 ACX_PD_THRESHOLD = 0x0023,
983 ACX_TX_CONFIG_OPT = 0x0024,
984 ACX_CCA_THRESHOLD = 0x0025,
985 ACX_EVENT_MBOX_MASK = 0x0026,
986 ACX_CONN_MONIT_PARAMS = 0x002D,
987 ACX_CONS_TX_FAILURE = 0x002F,
988 ACX_BCN_DTIM_OPTIONS = 0x0031,
989 ACX_SG_ENABLE = 0x0032,
990 ACX_SG_CFG = 0x0033,
991 ACX_BEACON_FILTER_TABLE = 0x0038,
992 ACX_ARP_IP_FILTER = 0x0039,
993 ACX_ROAMING_STATISTICS_TBL = 0x003B,
994 ACX_RATE_POLICY = 0x003D,
995 ACX_CTS_PROTECTION = 0x003E,
996 ACX_SLEEP_AUTH = 0x003F,
997 ACX_PREAMBLE_TYPE = 0x0040,
998 ACX_ERROR_CNT = 0x0041,
999 ACX_IBSS_FILTER = 0x0044,
1000 ACX_SERVICE_PERIOD_TIMEOUT = 0x0045,
1001 ACX_TSF_INFO = 0x0046,
1002 ACX_CONFIG_PS_WMM = 0x0049,
1003 ACX_ENABLE_RX_DATA_FILTER = 0x004A,
1004 ACX_SET_RX_DATA_FILTER = 0x004B,
1005 ACX_GET_DATA_FILTER_STATISTICS = 0x004C,
1006 ACX_RX_CONFIG_OPT = 0x004E,
1007 ACX_FRAG_CFG = 0x004F,
1008 ACX_BET_ENABLE = 0x0050,
1009 ACX_RSSI_SNR_TRIGGER = 0x0051,
1010 ACX_RSSI_SNR_WEIGHTS = 0x0051,
1011 ACX_KEEP_ALIVE_MODE = 0x0052,
1012 ACX_SET_KEEP_ALIVE_CONFIG = 0x0054,
1013 ACX_BA_SESSION_RESPONDER_POLICY = 0x0055,
1014 ACX_BA_SESSION_INITIATOR_POLICY = 0x0056,
1015 ACX_PEER_HT_CAP = 0x0057,
1016 ACX_HT_BSS_OPERATION = 0x0058,
1017 ACX_COEX_ACTIVITY = 0x0059,
3cfd6cf9 1018 ACX_SET_SMART_REFLEX_DEBUG = 0x005A,
6e92b416 1019 ACX_SET_DCO_ITRIM_PARAMS = 0x0061,
f5fc0f86
LC		 1020 DOT11_RX_MSDU_LIFE_TIME = 0x1004,
1021 DOT11_CUR_TX_PWR = 0x100D,
1022 DOT11_RX_DOT11_MODE = 0x1012,
1023 DOT11_RTS_THRESHOLD = 0x1013,
1024 DOT11_GROUP_ADDRESS_TBL = 0x1014,
1025
1026 MAX_DOT11_IE = DOT11_GROUP_ADDRESS_TBL,
1027
1028 MAX_IE = 0xFFFF
1029};
1030
1031
51f2be24 1032int wl1271_acx_wake_up_conditions(struct wl1271 *wl);
f5fc0f86
LC		 1033int wl1271_acx_sleep_auth(struct wl1271 *wl, u8 sleep_auth);
1034int wl1271_acx_fw_version(struct wl1271 *wl, char *buf, size_t len);
1035int wl1271_acx_tx_power(struct wl1271 *wl, int power);
1036int wl1271_acx_feature_cfg(struct wl1271 *wl);
1037int wl1271_acx_mem_map(struct wl1271 *wl,
1038 struct acx_header *mem_map, size_t len);
8793f9bb 1039int wl1271_acx_rx_msdu_life_time(struct wl1271 *wl);
f5fc0f86
LC		 1040int wl1271_acx_rx_config(struct wl1271 *wl, u32 config, u32 filter);
1041int wl1271_acx_pd_threshold(struct wl1271 *wl);
1042int wl1271_acx_slot(struct wl1271 *wl, enum acx_slot_type slot_time);
c87dec9f
JO		 1043int wl1271_acx_group_address_tbl(struct wl1271 *wl, bool enable,
1044 void *mc_list, u32 mc_list_len);
f5fc0f86
LC		 1045int wl1271_acx_service_period_timeout(struct wl1271 *wl);
1046int wl1271_acx_rts_threshold(struct wl1271 *wl, u16 rts_threshold);
6e92b416 1047int wl1271_acx_dco_itrim_params(struct wl1271 *wl);
1922167b 1048int wl1271_acx_beacon_filter_opt(struct wl1271 *wl, bool enable_filter);
f5fc0f86 1049int wl1271_acx_beacon_filter_table(struct wl1271 *wl);
34415236 1050int wl1271_acx_conn_monit_params(struct wl1271 *wl);
f5fc0f86
LC		 1051int wl1271_acx_sg_enable(struct wl1271 *wl);
1052int wl1271_acx_sg_cfg(struct wl1271 *wl);
1053int wl1271_acx_cca_threshold(struct wl1271 *wl);
1054int wl1271_acx_bcn_dtim_options(struct wl1271 *wl);
1055int wl1271_acx_aid(struct wl1271 *wl, u16 aid);
1056int wl1271_acx_event_mbox_mask(struct wl1271 *wl, u32 event_mask);
1057int wl1271_acx_set_preamble(struct wl1271 *wl, enum acx_preamble_type preamble);
1058int wl1271_acx_cts_protect(struct wl1271 *wl,
11f70f97 1059 enum acx_ctsprotect_type ctsprotect);
f5fc0f86 1060int wl1271_acx_statistics(struct wl1271 *wl, struct acx_statistics *stats);
8a5a37a6 1061int wl1271_acx_rate_policies(struct wl1271 *wl, u32 enabled_rates);
f5fc0f86
LC		 1062int wl1271_acx_ac_cfg(struct wl1271 *wl);
1063int wl1271_acx_tid_cfg(struct wl1271 *wl);
1064int wl1271_acx_frag_threshold(struct wl1271 *wl);
1065int wl1271_acx_tx_config_options(struct wl1271 *wl);
1066int wl1271_acx_mem_cfg(struct wl1271 *wl);
1067int wl1271_acx_init_mem_config(struct wl1271 *wl);
1068int wl1271_acx_init_rx_interrupt(struct wl1271 *wl);
3cfd6cf9 1069int wl1271_acx_smart_reflex(struct wl1271 *wl);
11f70f97 1070int wl1271_acx_bet_enable(struct wl1271 *wl, bool enable);
01c09162
JO		 1071int wl1271_acx_arp_ip_filter(struct wl1271 *wl, bool enable, u8 *address,
1072 u8 version);
f5fc0f86
LC		 1073
1074#endif /* __WL1271_ACX_H__ */
Linux kernel - Deliverables
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