Commit | Line | Data |
---|---|---|
f02f8aee AA |
1 | /* |
2 | * NXP LPC18xx/LPC43xx EEPROM memory NVMEM driver | |
3 | * | |
4 | * Copyright (c) 2015 Ariel D'Alessandro <ariel@vanguardiasur.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published by | |
8 | * the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/clk.h> | |
12 | #include <linux/device.h> | |
13 | #include <linux/delay.h> | |
14 | #include <linux/err.h> | |
15 | #include <linux/io.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/nvmem-provider.h> | |
18 | #include <linux/platform_device.h> | |
19 | #include <linux/regmap.h> | |
20 | #include <linux/reset.h> | |
21 | ||
22 | /* Registers */ | |
23 | #define LPC18XX_EEPROM_AUTOPROG 0x00c | |
24 | #define LPC18XX_EEPROM_AUTOPROG_WORD 0x1 | |
25 | ||
26 | #define LPC18XX_EEPROM_CLKDIV 0x014 | |
27 | ||
28 | #define LPC18XX_EEPROM_PWRDWN 0x018 | |
29 | #define LPC18XX_EEPROM_PWRDWN_NO 0x0 | |
30 | #define LPC18XX_EEPROM_PWRDWN_YES 0x1 | |
31 | ||
32 | #define LPC18XX_EEPROM_INTSTAT 0xfe0 | |
33 | #define LPC18XX_EEPROM_INTSTAT_END_OF_PROG BIT(2) | |
34 | ||
35 | #define LPC18XX_EEPROM_INTSTATCLR 0xfe8 | |
36 | #define LPC18XX_EEPROM_INTSTATCLR_PROG_CLR_ST BIT(2) | |
37 | ||
38 | /* Fixed page size (bytes) */ | |
39 | #define LPC18XX_EEPROM_PAGE_SIZE 0x80 | |
40 | ||
41 | /* EEPROM device requires a ~1500 kHz clock (min 800 kHz, max 1600 kHz) */ | |
42 | #define LPC18XX_EEPROM_CLOCK_HZ 1500000 | |
43 | ||
44 | /* EEPROM requires 3 ms of erase/program time between each writing */ | |
45 | #define LPC18XX_EEPROM_PROGRAM_TIME 3 | |
46 | ||
47 | struct lpc18xx_eeprom_dev { | |
48 | struct clk *clk; | |
49 | void __iomem *reg_base; | |
50 | void __iomem *mem_base; | |
51 | struct nvmem_device *nvmem; | |
52 | unsigned reg_bytes; | |
53 | unsigned val_bytes; | |
54 | }; | |
55 | ||
56 | static struct regmap_config lpc18xx_regmap_config = { | |
57 | .reg_bits = 32, | |
58 | .reg_stride = 4, | |
59 | .val_bits = 32, | |
60 | }; | |
61 | ||
62 | static inline void lpc18xx_eeprom_writel(struct lpc18xx_eeprom_dev *eeprom, | |
63 | u32 reg, u32 val) | |
64 | { | |
65 | writel(val, eeprom->reg_base + reg); | |
66 | } | |
67 | ||
68 | static inline u32 lpc18xx_eeprom_readl(struct lpc18xx_eeprom_dev *eeprom, | |
69 | u32 reg) | |
70 | { | |
71 | return readl(eeprom->reg_base + reg); | |
72 | } | |
73 | ||
74 | static int lpc18xx_eeprom_busywait_until_prog(struct lpc18xx_eeprom_dev *eeprom) | |
75 | { | |
76 | unsigned long end; | |
77 | u32 val; | |
78 | ||
79 | /* Wait until EEPROM program operation has finished */ | |
80 | end = jiffies + msecs_to_jiffies(LPC18XX_EEPROM_PROGRAM_TIME * 10); | |
81 | ||
82 | while (time_is_after_jiffies(end)) { | |
83 | val = lpc18xx_eeprom_readl(eeprom, LPC18XX_EEPROM_INTSTAT); | |
84 | ||
85 | if (val & LPC18XX_EEPROM_INTSTAT_END_OF_PROG) { | |
86 | lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_INTSTATCLR, | |
87 | LPC18XX_EEPROM_INTSTATCLR_PROG_CLR_ST); | |
88 | return 0; | |
89 | } | |
90 | ||
91 | usleep_range(LPC18XX_EEPROM_PROGRAM_TIME * USEC_PER_MSEC, | |
92 | (LPC18XX_EEPROM_PROGRAM_TIME + 1) * USEC_PER_MSEC); | |
93 | } | |
94 | ||
95 | return -ETIMEDOUT; | |
96 | } | |
97 | ||
98 | static int lpc18xx_eeprom_gather_write(void *context, const void *reg, | |
99 | size_t reg_size, const void *val, | |
100 | size_t val_size) | |
101 | { | |
102 | struct lpc18xx_eeprom_dev *eeprom = context; | |
103 | unsigned int offset = *(u32 *)reg; | |
104 | int ret; | |
105 | ||
106 | if (offset % lpc18xx_regmap_config.reg_stride) | |
107 | return -EINVAL; | |
108 | ||
109 | lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_PWRDWN, | |
110 | LPC18XX_EEPROM_PWRDWN_NO); | |
111 | ||
112 | /* Wait 100 us while the EEPROM wakes up */ | |
113 | usleep_range(100, 200); | |
114 | ||
115 | while (val_size) { | |
116 | writel(*(u32 *)val, eeprom->mem_base + offset); | |
117 | ret = lpc18xx_eeprom_busywait_until_prog(eeprom); | |
118 | if (ret < 0) | |
119 | return ret; | |
120 | ||
121 | val_size -= eeprom->val_bytes; | |
122 | val += eeprom->val_bytes; | |
123 | offset += eeprom->val_bytes; | |
124 | } | |
125 | ||
126 | lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_PWRDWN, | |
127 | LPC18XX_EEPROM_PWRDWN_YES); | |
128 | ||
129 | return 0; | |
130 | } | |
131 | ||
132 | static int lpc18xx_eeprom_write(void *context, const void *data, size_t count) | |
133 | { | |
134 | struct lpc18xx_eeprom_dev *eeprom = context; | |
135 | unsigned int offset = eeprom->reg_bytes; | |
136 | ||
137 | if (count <= offset) | |
138 | return -EINVAL; | |
139 | ||
140 | return lpc18xx_eeprom_gather_write(context, data, eeprom->reg_bytes, | |
141 | data + offset, count - offset); | |
142 | } | |
143 | ||
144 | static int lpc18xx_eeprom_read(void *context, const void *reg, size_t reg_size, | |
145 | void *val, size_t val_size) | |
146 | { | |
147 | struct lpc18xx_eeprom_dev *eeprom = context; | |
148 | unsigned int offset = *(u32 *)reg; | |
149 | ||
150 | lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_PWRDWN, | |
151 | LPC18XX_EEPROM_PWRDWN_NO); | |
152 | ||
153 | /* Wait 100 us while the EEPROM wakes up */ | |
154 | usleep_range(100, 200); | |
155 | ||
156 | while (val_size) { | |
157 | *(u32 *)val = readl(eeprom->mem_base + offset); | |
158 | val_size -= eeprom->val_bytes; | |
159 | val += eeprom->val_bytes; | |
160 | offset += eeprom->val_bytes; | |
161 | } | |
162 | ||
163 | lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_PWRDWN, | |
164 | LPC18XX_EEPROM_PWRDWN_YES); | |
165 | ||
166 | return 0; | |
167 | } | |
168 | ||
169 | static struct regmap_bus lpc18xx_eeprom_bus = { | |
170 | .write = lpc18xx_eeprom_write, | |
171 | .gather_write = lpc18xx_eeprom_gather_write, | |
172 | .read = lpc18xx_eeprom_read, | |
173 | .reg_format_endian_default = REGMAP_ENDIAN_NATIVE, | |
174 | .val_format_endian_default = REGMAP_ENDIAN_NATIVE, | |
175 | }; | |
176 | ||
177 | static bool lpc18xx_eeprom_writeable_reg(struct device *dev, unsigned int reg) | |
178 | { | |
179 | /* | |
180 | * The last page contains the EEPROM initialization data and is not | |
181 | * writable. | |
182 | */ | |
183 | return reg <= lpc18xx_regmap_config.max_register - | |
184 | LPC18XX_EEPROM_PAGE_SIZE; | |
185 | } | |
186 | ||
187 | static bool lpc18xx_eeprom_readable_reg(struct device *dev, unsigned int reg) | |
188 | { | |
189 | return reg <= lpc18xx_regmap_config.max_register; | |
190 | } | |
191 | ||
192 | static struct nvmem_config lpc18xx_nvmem_config = { | |
193 | .name = "lpc18xx-eeprom", | |
194 | .owner = THIS_MODULE, | |
195 | }; | |
196 | ||
197 | static int lpc18xx_eeprom_probe(struct platform_device *pdev) | |
198 | { | |
199 | struct lpc18xx_eeprom_dev *eeprom; | |
200 | struct device *dev = &pdev->dev; | |
201 | struct reset_control *rst; | |
202 | unsigned long clk_rate; | |
203 | struct regmap *regmap; | |
204 | struct resource *res; | |
205 | int ret; | |
206 | ||
207 | eeprom = devm_kzalloc(dev, sizeof(*eeprom), GFP_KERNEL); | |
208 | if (!eeprom) | |
209 | return -ENOMEM; | |
210 | ||
211 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg"); | |
212 | eeprom->reg_base = devm_ioremap_resource(dev, res); | |
213 | if (IS_ERR(eeprom->reg_base)) | |
214 | return PTR_ERR(eeprom->reg_base); | |
215 | ||
216 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem"); | |
217 | eeprom->mem_base = devm_ioremap_resource(dev, res); | |
218 | if (IS_ERR(eeprom->mem_base)) | |
219 | return PTR_ERR(eeprom->mem_base); | |
220 | ||
221 | eeprom->clk = devm_clk_get(&pdev->dev, "eeprom"); | |
222 | if (IS_ERR(eeprom->clk)) { | |
223 | dev_err(&pdev->dev, "failed to get eeprom clock\n"); | |
224 | return PTR_ERR(eeprom->clk); | |
225 | } | |
226 | ||
227 | ret = clk_prepare_enable(eeprom->clk); | |
228 | if (ret < 0) { | |
229 | dev_err(dev, "failed to prepare/enable eeprom clk: %d\n", ret); | |
230 | return ret; | |
231 | } | |
232 | ||
233 | rst = devm_reset_control_get(dev, NULL); | |
234 | if (IS_ERR(rst)) { | |
235 | dev_err(dev, "failed to get reset: %ld\n", PTR_ERR(rst)); | |
236 | ret = PTR_ERR(rst); | |
237 | goto err_clk; | |
238 | } | |
239 | ||
240 | ret = reset_control_assert(rst); | |
241 | if (ret < 0) { | |
242 | dev_err(dev, "failed to assert reset: %d\n", ret); | |
243 | goto err_clk; | |
244 | } | |
245 | ||
246 | eeprom->val_bytes = lpc18xx_regmap_config.val_bits / BITS_PER_BYTE; | |
247 | eeprom->reg_bytes = lpc18xx_regmap_config.reg_bits / BITS_PER_BYTE; | |
248 | ||
249 | /* | |
250 | * Clock rate is generated by dividing the system bus clock by the | |
251 | * division factor, contained in the divider register (minus 1 encoded). | |
252 | */ | |
253 | clk_rate = clk_get_rate(eeprom->clk); | |
254 | clk_rate = DIV_ROUND_UP(clk_rate, LPC18XX_EEPROM_CLOCK_HZ) - 1; | |
255 | lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_CLKDIV, clk_rate); | |
256 | ||
257 | /* | |
258 | * Writing a single word to the page will start the erase/program cycle | |
259 | * automatically | |
260 | */ | |
261 | lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_AUTOPROG, | |
262 | LPC18XX_EEPROM_AUTOPROG_WORD); | |
263 | ||
264 | lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_PWRDWN, | |
265 | LPC18XX_EEPROM_PWRDWN_YES); | |
266 | ||
267 | lpc18xx_regmap_config.max_register = resource_size(res) - 1; | |
268 | lpc18xx_regmap_config.writeable_reg = lpc18xx_eeprom_writeable_reg; | |
269 | lpc18xx_regmap_config.readable_reg = lpc18xx_eeprom_readable_reg; | |
270 | ||
271 | regmap = devm_regmap_init(dev, &lpc18xx_eeprom_bus, eeprom, | |
272 | &lpc18xx_regmap_config); | |
273 | if (IS_ERR(regmap)) { | |
274 | dev_err(dev, "regmap init failed: %ld\n", PTR_ERR(regmap)); | |
275 | ret = PTR_ERR(regmap); | |
276 | goto err_clk; | |
277 | } | |
278 | ||
279 | lpc18xx_nvmem_config.dev = dev; | |
280 | ||
281 | eeprom->nvmem = nvmem_register(&lpc18xx_nvmem_config); | |
282 | if (IS_ERR(eeprom->nvmem)) { | |
283 | ret = PTR_ERR(eeprom->nvmem); | |
284 | goto err_clk; | |
285 | } | |
286 | ||
287 | platform_set_drvdata(pdev, eeprom); | |
288 | ||
289 | return 0; | |
290 | ||
291 | err_clk: | |
292 | clk_disable_unprepare(eeprom->clk); | |
293 | ||
294 | return ret; | |
295 | } | |
296 | ||
297 | static int lpc18xx_eeprom_remove(struct platform_device *pdev) | |
298 | { | |
299 | struct lpc18xx_eeprom_dev *eeprom = platform_get_drvdata(pdev); | |
300 | int ret; | |
301 | ||
302 | ret = nvmem_unregister(eeprom->nvmem); | |
303 | if (ret < 0) | |
304 | return ret; | |
305 | ||
306 | clk_disable_unprepare(eeprom->clk); | |
307 | ||
308 | return 0; | |
309 | } | |
310 | ||
311 | static const struct of_device_id lpc18xx_eeprom_of_match[] = { | |
312 | { .compatible = "nxp,lpc1857-eeprom" }, | |
313 | { }, | |
314 | }; | |
315 | MODULE_DEVICE_TABLE(of, lpc18xx_eeprom_of_match); | |
316 | ||
317 | static struct platform_driver lpc18xx_eeprom_driver = { | |
318 | .probe = lpc18xx_eeprom_probe, | |
319 | .remove = lpc18xx_eeprom_remove, | |
320 | .driver = { | |
321 | .name = "lpc18xx-eeprom", | |
322 | .of_match_table = lpc18xx_eeprom_of_match, | |
323 | }, | |
324 | }; | |
325 | ||
326 | module_platform_driver(lpc18xx_eeprom_driver); | |
327 | ||
328 | MODULE_AUTHOR("Ariel D'Alessandro <ariel@vanguardiasur.com.ar>"); | |
329 | MODULE_DESCRIPTION("NXP LPC18xx EEPROM memory Driver"); | |
330 | MODULE_LICENSE("GPL v2"); |