Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* Low-level parallel-port routines for 8255-based PC-style hardware. |
3aeda9bc | 2 | * |
1da177e4 LT |
3 | * Authors: Phil Blundell <philb@gnu.org> |
4 | * Tim Waugh <tim@cyberelk.demon.co.uk> | |
5 | * Jose Renau <renau@acm.org> | |
bdca3f20 | 6 | * David Campbell |
1da177e4 LT |
7 | * Andrea Arcangeli |
8 | * | |
9 | * based on work by Grant Guenther <grant@torque.net> and Phil Blundell. | |
10 | * | |
11 | * Cleaned up include files - Russell King <linux@arm.uk.linux.org> | |
12 | * DMA support - Bert De Jonghe <bert@sophis.be> | |
13 | * Many ECP bugs fixed. Fred Barnes & Jamie Lokier, 1999 | |
3aeda9bc | 14 | * More PCI support now conditional on CONFIG_PCI, 03/2001, Paul G. |
1da177e4 LT |
15 | * Various hacks, Fred Barnes, 04/2001 |
16 | * Updated probing logic - Adam Belay <ambx1@neo.rr.com> | |
17 | */ | |
18 | ||
19 | /* This driver should work with any hardware that is broadly compatible | |
20 | * with that in the IBM PC. This applies to the majority of integrated | |
21 | * I/O chipsets that are commonly available. The expected register | |
22 | * layout is: | |
23 | * | |
24 | * base+0 data | |
25 | * base+1 status | |
26 | * base+2 control | |
27 | * | |
28 | * In addition, there are some optional registers: | |
29 | * | |
30 | * base+3 EPP address | |
31 | * base+4 EPP data | |
32 | * base+0x400 ECP config A | |
33 | * base+0x401 ECP config B | |
34 | * base+0x402 ECP control | |
35 | * | |
36 | * All registers are 8 bits wide and read/write. If your hardware differs | |
37 | * only in register addresses (eg because your registers are on 32-bit | |
38 | * word boundaries) then you can alter the constants in parport_pc.h to | |
39 | * accommodate this. | |
40 | * | |
41 | * Note that the ECP registers may not start at offset 0x400 for PCI cards, | |
42 | * but rather will start at port->base_hi. | |
43 | */ | |
44 | ||
1da177e4 LT |
45 | #include <linux/module.h> |
46 | #include <linux/init.h> | |
47 | #include <linux/sched.h> | |
48 | #include <linux/delay.h> | |
49 | #include <linux/errno.h> | |
50 | #include <linux/interrupt.h> | |
51 | #include <linux/ioport.h> | |
52 | #include <linux/kernel.h> | |
53 | #include <linux/slab.h> | |
8382d2b9 | 54 | #include <linux/dma-mapping.h> |
1da177e4 LT |
55 | #include <linux/pci.h> |
56 | #include <linux/pnp.h> | |
a7d801af | 57 | #include <linux/platform_device.h> |
1da177e4 | 58 | #include <linux/sysctl.h> |
3aeda9bc AC |
59 | #include <linux/io.h> |
60 | #include <linux/uaccess.h> | |
1da177e4 | 61 | |
1da177e4 | 62 | #include <asm/dma.h> |
1da177e4 LT |
63 | |
64 | #include <linux/parport.h> | |
65 | #include <linux/parport_pc.h> | |
66 | #include <linux/via.h> | |
67 | #include <asm/parport.h> | |
68 | ||
69 | #define PARPORT_PC_MAX_PORTS PARPORT_MAX | |
70 | ||
7fbacd52 AV |
71 | #ifdef CONFIG_ISA_DMA_API |
72 | #define HAS_DMA | |
73 | #endif | |
74 | ||
1da177e4 LT |
75 | /* ECR modes */ |
76 | #define ECR_SPP 00 | |
77 | #define ECR_PS2 01 | |
78 | #define ECR_PPF 02 | |
79 | #define ECR_ECP 03 | |
80 | #define ECR_EPP 04 | |
81 | #define ECR_VND 05 | |
82 | #define ECR_TST 06 | |
83 | #define ECR_CNF 07 | |
84 | #define ECR_MODE_MASK 0xe0 | |
3aeda9bc | 85 | #define ECR_WRITE(p, v) frob_econtrol((p), 0xff, (v)) |
1da177e4 LT |
86 | |
87 | #undef DEBUG | |
88 | ||
89 | #ifdef DEBUG | |
90 | #define DPRINTK printk | |
91 | #else | |
92 | #define DPRINTK(stuff...) | |
93 | #endif | |
94 | ||
95 | ||
96 | #define NR_SUPERIOS 3 | |
97 | static struct superio_struct { /* For Super-IO chips autodetection */ | |
98 | int io; | |
99 | int irq; | |
100 | int dma; | |
96766a3c | 101 | } superios[NR_SUPERIOS] = { {0,},}; |
1da177e4 LT |
102 | |
103 | static int user_specified; | |
104 | #if defined(CONFIG_PARPORT_PC_SUPERIO) || \ | |
105 | (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO)) | |
106 | static int verbose_probing; | |
107 | #endif | |
108 | static int pci_registered_parport; | |
109 | static int pnp_registered_parport; | |
110 | ||
111 | /* frob_control, but for ECR */ | |
3aeda9bc | 112 | static void frob_econtrol(struct parport *pb, unsigned char m, |
1da177e4 LT |
113 | unsigned char v) |
114 | { | |
115 | unsigned char ectr = 0; | |
116 | ||
117 | if (m != 0xff) | |
3aeda9bc | 118 | ectr = inb(ECONTROL(pb)); |
1da177e4 | 119 | |
3aeda9bc | 120 | DPRINTK(KERN_DEBUG "frob_econtrol(%02x,%02x): %02x -> %02x\n", |
1da177e4 LT |
121 | m, v, ectr, (ectr & ~m) ^ v); |
122 | ||
3aeda9bc | 123 | outb((ectr & ~m) ^ v, ECONTROL(pb)); |
1da177e4 LT |
124 | } |
125 | ||
3aeda9bc | 126 | static inline void frob_set_mode(struct parport *p, int mode) |
1da177e4 | 127 | { |
3aeda9bc | 128 | frob_econtrol(p, ECR_MODE_MASK, mode << 5); |
1da177e4 LT |
129 | } |
130 | ||
131 | #ifdef CONFIG_PARPORT_PC_FIFO | |
3aeda9bc | 132 | /* Safely change the mode bits in the ECR |
1da177e4 LT |
133 | Returns: |
134 | 0 : Success | |
135 | -EBUSY: Could not drain FIFO in some finite amount of time, | |
136 | mode not changed! | |
137 | */ | |
138 | static int change_mode(struct parport *p, int m) | |
139 | { | |
140 | const struct parport_pc_private *priv = p->physport->private_data; | |
141 | unsigned char oecr; | |
142 | int mode; | |
143 | ||
3aeda9bc | 144 | DPRINTK(KERN_INFO "parport change_mode ECP-ISA to mode 0x%02x\n", m); |
1da177e4 LT |
145 | |
146 | if (!priv->ecr) { | |
3aeda9bc | 147 | printk(KERN_DEBUG "change_mode: but there's no ECR!\n"); |
1da177e4 LT |
148 | return 0; |
149 | } | |
150 | ||
151 | /* Bits <7:5> contain the mode. */ | |
3aeda9bc | 152 | oecr = inb(ECONTROL(p)); |
1da177e4 | 153 | mode = (oecr >> 5) & 0x7; |
3aeda9bc AC |
154 | if (mode == m) |
155 | return 0; | |
1da177e4 LT |
156 | |
157 | if (mode >= 2 && !(priv->ctr & 0x20)) { | |
158 | /* This mode resets the FIFO, so we may | |
159 | * have to wait for it to drain first. */ | |
160 | unsigned long expire = jiffies + p->physport->cad->timeout; | |
161 | int counter; | |
162 | switch (mode) { | |
163 | case ECR_PPF: /* Parallel Port FIFO mode */ | |
164 | case ECR_ECP: /* ECP Parallel Port mode */ | |
165 | /* Busy wait for 200us */ | |
166 | for (counter = 0; counter < 40; counter++) { | |
3aeda9bc | 167 | if (inb(ECONTROL(p)) & 0x01) |
1da177e4 | 168 | break; |
3aeda9bc AC |
169 | if (signal_pending(current)) |
170 | break; | |
171 | udelay(5); | |
1da177e4 LT |
172 | } |
173 | ||
174 | /* Poll slowly. */ | |
3aeda9bc AC |
175 | while (!(inb(ECONTROL(p)) & 0x01)) { |
176 | if (time_after_eq(jiffies, expire)) | |
1da177e4 LT |
177 | /* The FIFO is stuck. */ |
178 | return -EBUSY; | |
3aeda9bc AC |
179 | schedule_timeout_interruptible( |
180 | msecs_to_jiffies(10)); | |
181 | if (signal_pending(current)) | |
1da177e4 LT |
182 | break; |
183 | } | |
184 | } | |
185 | } | |
186 | ||
187 | if (mode >= 2 && m >= 2) { | |
188 | /* We have to go through mode 001 */ | |
189 | oecr &= ~(7 << 5); | |
190 | oecr |= ECR_PS2 << 5; | |
3aeda9bc | 191 | ECR_WRITE(p, oecr); |
1da177e4 LT |
192 | } |
193 | ||
194 | /* Set the mode. */ | |
195 | oecr &= ~(7 << 5); | |
196 | oecr |= m << 5; | |
3aeda9bc | 197 | ECR_WRITE(p, oecr); |
1da177e4 LT |
198 | return 0; |
199 | } | |
200 | ||
201 | #ifdef CONFIG_PARPORT_1284 | |
202 | /* Find FIFO lossage; FIFO is reset */ | |
203 | #if 0 | |
3aeda9bc | 204 | static int get_fifo_residue(struct parport *p) |
1da177e4 LT |
205 | { |
206 | int residue; | |
207 | int cnfga; | |
208 | const struct parport_pc_private *priv = p->physport->private_data; | |
209 | ||
210 | /* Adjust for the contents of the FIFO. */ | |
211 | for (residue = priv->fifo_depth; ; residue--) { | |
3aeda9bc | 212 | if (inb(ECONTROL(p)) & 0x2) |
1da177e4 LT |
213 | /* Full up. */ |
214 | break; | |
215 | ||
3aeda9bc | 216 | outb(0, FIFO(p)); |
1da177e4 LT |
217 | } |
218 | ||
3aeda9bc | 219 | printk(KERN_DEBUG "%s: %d PWords were left in FIFO\n", p->name, |
1da177e4 LT |
220 | residue); |
221 | ||
222 | /* Reset the FIFO. */ | |
3aeda9bc | 223 | frob_set_mode(p, ECR_PS2); |
1da177e4 LT |
224 | |
225 | /* Now change to config mode and clean up. FIXME */ | |
3aeda9bc AC |
226 | frob_set_mode(p, ECR_CNF); |
227 | cnfga = inb(CONFIGA(p)); | |
228 | printk(KERN_DEBUG "%s: cnfgA contains 0x%02x\n", p->name, cnfga); | |
1da177e4 LT |
229 | |
230 | if (!(cnfga & (1<<2))) { | |
3aeda9bc | 231 | printk(KERN_DEBUG "%s: Accounting for extra byte\n", p->name); |
1da177e4 LT |
232 | residue++; |
233 | } | |
234 | ||
235 | /* Don't care about partial PWords until support is added for | |
236 | * PWord != 1 byte. */ | |
237 | ||
238 | /* Back to PS2 mode. */ | |
3aeda9bc | 239 | frob_set_mode(p, ECR_PS2); |
1da177e4 | 240 | |
3aeda9bc AC |
241 | DPRINTK(KERN_DEBUG |
242 | "*** get_fifo_residue: done residue collecting (ecr = 0x%2.2x)\n", | |
243 | inb(ECONTROL(p))); | |
1da177e4 LT |
244 | return residue; |
245 | } | |
246 | #endif /* 0 */ | |
247 | #endif /* IEEE 1284 support */ | |
248 | #endif /* FIFO support */ | |
249 | ||
250 | /* | |
251 | * Clear TIMEOUT BIT in EPP MODE | |
252 | * | |
253 | * This is also used in SPP detection. | |
254 | */ | |
255 | static int clear_epp_timeout(struct parport *pb) | |
256 | { | |
257 | unsigned char r; | |
258 | ||
259 | if (!(parport_pc_read_status(pb) & 0x01)) | |
260 | return 1; | |
261 | ||
262 | /* To clear timeout some chips require double read */ | |
263 | parport_pc_read_status(pb); | |
264 | r = parport_pc_read_status(pb); | |
3aeda9bc AC |
265 | outb(r | 0x01, STATUS(pb)); /* Some reset by writing 1 */ |
266 | outb(r & 0xfe, STATUS(pb)); /* Others by writing 0 */ | |
1da177e4 LT |
267 | r = parport_pc_read_status(pb); |
268 | ||
269 | return !(r & 0x01); | |
270 | } | |
271 | ||
272 | /* | |
273 | * Access functions. | |
274 | * | |
275 | * Most of these aren't static because they may be used by the | |
276 | * parport_xxx_yyy macros. extern __inline__ versions of several | |
277 | * of these are in parport_pc.h. | |
278 | */ | |
279 | ||
3aeda9bc AC |
280 | static void parport_pc_init_state(struct pardevice *dev, |
281 | struct parport_state *s) | |
1da177e4 LT |
282 | { |
283 | s->u.pc.ctr = 0xc; | |
284 | if (dev->irq_func && | |
285 | dev->port->irq != PARPORT_IRQ_NONE) | |
286 | /* Set ackIntEn */ | |
287 | s->u.pc.ctr |= 0x10; | |
288 | ||
289 | s->u.pc.ecr = 0x34; /* NetMos chip can cause problems 0x24; | |
290 | * D.Gruszka VScom */ | |
291 | } | |
292 | ||
293 | static void parport_pc_save_state(struct parport *p, struct parport_state *s) | |
294 | { | |
295 | const struct parport_pc_private *priv = p->physport->private_data; | |
296 | s->u.pc.ctr = priv->ctr; | |
297 | if (priv->ecr) | |
3aeda9bc | 298 | s->u.pc.ecr = inb(ECONTROL(p)); |
1da177e4 LT |
299 | } |
300 | ||
3aeda9bc AC |
301 | static void parport_pc_restore_state(struct parport *p, |
302 | struct parport_state *s) | |
1da177e4 LT |
303 | { |
304 | struct parport_pc_private *priv = p->physport->private_data; | |
305 | register unsigned char c = s->u.pc.ctr & priv->ctr_writable; | |
3aeda9bc | 306 | outb(c, CONTROL(p)); |
1da177e4 LT |
307 | priv->ctr = c; |
308 | if (priv->ecr) | |
3aeda9bc | 309 | ECR_WRITE(p, s->u.pc.ecr); |
1da177e4 LT |
310 | } |
311 | ||
312 | #ifdef CONFIG_PARPORT_1284 | |
3aeda9bc AC |
313 | static size_t parport_pc_epp_read_data(struct parport *port, void *buf, |
314 | size_t length, int flags) | |
1da177e4 LT |
315 | { |
316 | size_t got = 0; | |
317 | ||
318 | if (flags & PARPORT_W91284PIC) { | |
319 | unsigned char status; | |
320 | size_t left = length; | |
321 | ||
322 | /* use knowledge about data lines..: | |
323 | * nFault is 0 if there is at least 1 byte in the Warp's FIFO | |
324 | * pError is 1 if there are 16 bytes in the Warp's FIFO | |
325 | */ | |
3aeda9bc | 326 | status = inb(STATUS(port)); |
1da177e4 | 327 | |
3aeda9bc AC |
328 | while (!(status & 0x08) && got < length) { |
329 | if (left >= 16 && (status & 0x20) && !(status & 0x08)) { | |
1da177e4 | 330 | /* can grab 16 bytes from warp fifo */ |
3aeda9bc AC |
331 | if (!((long)buf & 0x03)) |
332 | insl(EPPDATA(port), buf, 4); | |
333 | else | |
334 | insb(EPPDATA(port), buf, 16); | |
1da177e4 LT |
335 | buf += 16; |
336 | got += 16; | |
337 | left -= 16; | |
338 | } else { | |
339 | /* grab single byte from the warp fifo */ | |
3aeda9bc | 340 | *((char *)buf) = inb(EPPDATA(port)); |
1da177e4 LT |
341 | buf++; |
342 | got++; | |
343 | left--; | |
344 | } | |
3aeda9bc | 345 | status = inb(STATUS(port)); |
1da177e4 LT |
346 | if (status & 0x01) { |
347 | /* EPP timeout should never occur... */ | |
3aeda9bc AC |
348 | printk(KERN_DEBUG |
349 | "%s: EPP timeout occurred while talking to w91284pic (should not have done)\n", port->name); | |
350 | clear_epp_timeout(port); | |
1da177e4 LT |
351 | } |
352 | } | |
353 | return got; | |
354 | } | |
355 | if ((flags & PARPORT_EPP_FAST) && (length > 1)) { | |
3aeda9bc AC |
356 | if (!(((long)buf | length) & 0x03)) |
357 | insl(EPPDATA(port), buf, (length >> 2)); | |
358 | else | |
359 | insb(EPPDATA(port), buf, length); | |
360 | if (inb(STATUS(port)) & 0x01) { | |
361 | clear_epp_timeout(port); | |
1da177e4 LT |
362 | return -EIO; |
363 | } | |
364 | return length; | |
365 | } | |
366 | for (; got < length; got++) { | |
3aeda9bc | 367 | *((char *)buf) = inb(EPPDATA(port)); |
1da177e4 | 368 | buf++; |
3aeda9bc | 369 | if (inb(STATUS(port)) & 0x01) { |
1da177e4 | 370 | /* EPP timeout */ |
3aeda9bc | 371 | clear_epp_timeout(port); |
1da177e4 LT |
372 | break; |
373 | } | |
374 | } | |
375 | ||
376 | return got; | |
377 | } | |
378 | ||
3aeda9bc AC |
379 | static size_t parport_pc_epp_write_data(struct parport *port, const void *buf, |
380 | size_t length, int flags) | |
1da177e4 LT |
381 | { |
382 | size_t written = 0; | |
383 | ||
384 | if ((flags & PARPORT_EPP_FAST) && (length > 1)) { | |
3aeda9bc AC |
385 | if (!(((long)buf | length) & 0x03)) |
386 | outsl(EPPDATA(port), buf, (length >> 2)); | |
387 | else | |
388 | outsb(EPPDATA(port), buf, length); | |
389 | if (inb(STATUS(port)) & 0x01) { | |
390 | clear_epp_timeout(port); | |
1da177e4 LT |
391 | return -EIO; |
392 | } | |
393 | return length; | |
394 | } | |
395 | for (; written < length; written++) { | |
3aeda9bc | 396 | outb(*((char *)buf), EPPDATA(port)); |
1da177e4 | 397 | buf++; |
3aeda9bc AC |
398 | if (inb(STATUS(port)) & 0x01) { |
399 | clear_epp_timeout(port); | |
1da177e4 LT |
400 | break; |
401 | } | |
402 | } | |
403 | ||
404 | return written; | |
405 | } | |
406 | ||
3aeda9bc | 407 | static size_t parport_pc_epp_read_addr(struct parport *port, void *buf, |
1da177e4 LT |
408 | size_t length, int flags) |
409 | { | |
410 | size_t got = 0; | |
411 | ||
412 | if ((flags & PARPORT_EPP_FAST) && (length > 1)) { | |
3aeda9bc AC |
413 | insb(EPPADDR(port), buf, length); |
414 | if (inb(STATUS(port)) & 0x01) { | |
415 | clear_epp_timeout(port); | |
1da177e4 LT |
416 | return -EIO; |
417 | } | |
418 | return length; | |
419 | } | |
420 | for (; got < length; got++) { | |
3aeda9bc | 421 | *((char *)buf) = inb(EPPADDR(port)); |
1da177e4 | 422 | buf++; |
3aeda9bc AC |
423 | if (inb(STATUS(port)) & 0x01) { |
424 | clear_epp_timeout(port); | |
1da177e4 LT |
425 | break; |
426 | } | |
427 | } | |
428 | ||
429 | return got; | |
430 | } | |
431 | ||
3aeda9bc | 432 | static size_t parport_pc_epp_write_addr(struct parport *port, |
1da177e4 LT |
433 | const void *buf, size_t length, |
434 | int flags) | |
435 | { | |
436 | size_t written = 0; | |
437 | ||
438 | if ((flags & PARPORT_EPP_FAST) && (length > 1)) { | |
3aeda9bc AC |
439 | outsb(EPPADDR(port), buf, length); |
440 | if (inb(STATUS(port)) & 0x01) { | |
441 | clear_epp_timeout(port); | |
1da177e4 LT |
442 | return -EIO; |
443 | } | |
444 | return length; | |
445 | } | |
446 | for (; written < length; written++) { | |
3aeda9bc | 447 | outb(*((char *)buf), EPPADDR(port)); |
1da177e4 | 448 | buf++; |
3aeda9bc AC |
449 | if (inb(STATUS(port)) & 0x01) { |
450 | clear_epp_timeout(port); | |
1da177e4 LT |
451 | break; |
452 | } | |
453 | } | |
454 | ||
455 | return written; | |
456 | } | |
457 | ||
3aeda9bc AC |
458 | static size_t parport_pc_ecpepp_read_data(struct parport *port, void *buf, |
459 | size_t length, int flags) | |
1da177e4 LT |
460 | { |
461 | size_t got; | |
462 | ||
3aeda9bc AC |
463 | frob_set_mode(port, ECR_EPP); |
464 | parport_pc_data_reverse(port); | |
465 | parport_pc_write_control(port, 0x4); | |
466 | got = parport_pc_epp_read_data(port, buf, length, flags); | |
467 | frob_set_mode(port, ECR_PS2); | |
1da177e4 LT |
468 | |
469 | return got; | |
470 | } | |
471 | ||
3aeda9bc AC |
472 | static size_t parport_pc_ecpepp_write_data(struct parport *port, |
473 | const void *buf, size_t length, | |
474 | int flags) | |
1da177e4 LT |
475 | { |
476 | size_t written; | |
477 | ||
3aeda9bc AC |
478 | frob_set_mode(port, ECR_EPP); |
479 | parport_pc_write_control(port, 0x4); | |
480 | parport_pc_data_forward(port); | |
481 | written = parport_pc_epp_write_data(port, buf, length, flags); | |
482 | frob_set_mode(port, ECR_PS2); | |
1da177e4 LT |
483 | |
484 | return written; | |
485 | } | |
486 | ||
3aeda9bc AC |
487 | static size_t parport_pc_ecpepp_read_addr(struct parport *port, void *buf, |
488 | size_t length, int flags) | |
1da177e4 LT |
489 | { |
490 | size_t got; | |
491 | ||
3aeda9bc AC |
492 | frob_set_mode(port, ECR_EPP); |
493 | parport_pc_data_reverse(port); | |
494 | parport_pc_write_control(port, 0x4); | |
495 | got = parport_pc_epp_read_addr(port, buf, length, flags); | |
496 | frob_set_mode(port, ECR_PS2); | |
1da177e4 LT |
497 | |
498 | return got; | |
499 | } | |
500 | ||
3aeda9bc | 501 | static size_t parport_pc_ecpepp_write_addr(struct parport *port, |
1da177e4 LT |
502 | const void *buf, size_t length, |
503 | int flags) | |
504 | { | |
505 | size_t written; | |
506 | ||
3aeda9bc AC |
507 | frob_set_mode(port, ECR_EPP); |
508 | parport_pc_write_control(port, 0x4); | |
509 | parport_pc_data_forward(port); | |
510 | written = parport_pc_epp_write_addr(port, buf, length, flags); | |
511 | frob_set_mode(port, ECR_PS2); | |
1da177e4 LT |
512 | |
513 | return written; | |
514 | } | |
515 | #endif /* IEEE 1284 support */ | |
516 | ||
517 | #ifdef CONFIG_PARPORT_PC_FIFO | |
3aeda9bc | 518 | static size_t parport_pc_fifo_write_block_pio(struct parport *port, |
1da177e4 LT |
519 | const void *buf, size_t length) |
520 | { | |
521 | int ret = 0; | |
522 | const unsigned char *bufp = buf; | |
523 | size_t left = length; | |
524 | unsigned long expire = jiffies + port->physport->cad->timeout; | |
3aeda9bc | 525 | const int fifo = FIFO(port); |
1da177e4 LT |
526 | int poll_for = 8; /* 80 usecs */ |
527 | const struct parport_pc_private *priv = port->physport->private_data; | |
528 | const int fifo_depth = priv->fifo_depth; | |
529 | ||
530 | port = port->physport; | |
531 | ||
532 | /* We don't want to be interrupted every character. */ | |
3aeda9bc | 533 | parport_pc_disable_irq(port); |
1da177e4 | 534 | /* set nErrIntrEn and serviceIntr */ |
3aeda9bc | 535 | frob_econtrol(port, (1<<4) | (1<<2), (1<<4) | (1<<2)); |
1da177e4 LT |
536 | |
537 | /* Forward mode. */ | |
3aeda9bc | 538 | parport_pc_data_forward(port); /* Must be in PS2 mode */ |
1da177e4 LT |
539 | |
540 | while (left) { | |
541 | unsigned char byte; | |
3aeda9bc | 542 | unsigned char ecrval = inb(ECONTROL(port)); |
1da177e4 LT |
543 | int i = 0; |
544 | ||
3aeda9bc | 545 | if (need_resched() && time_before(jiffies, expire)) |
1da177e4 | 546 | /* Can't yield the port. */ |
3aeda9bc | 547 | schedule(); |
1da177e4 LT |
548 | |
549 | /* Anyone else waiting for the port? */ | |
550 | if (port->waithead) { | |
3aeda9bc | 551 | printk(KERN_DEBUG "Somebody wants the port\n"); |
1da177e4 LT |
552 | break; |
553 | } | |
554 | ||
555 | if (ecrval & 0x02) { | |
556 | /* FIFO is full. Wait for interrupt. */ | |
557 | ||
558 | /* Clear serviceIntr */ | |
3aeda9bc AC |
559 | ECR_WRITE(port, ecrval & ~(1<<2)); |
560 | false_alarm: | |
561 | ret = parport_wait_event(port, HZ); | |
562 | if (ret < 0) | |
563 | break; | |
1da177e4 | 564 | ret = 0; |
3aeda9bc | 565 | if (!time_before(jiffies, expire)) { |
1da177e4 | 566 | /* Timed out. */ |
3aeda9bc | 567 | printk(KERN_DEBUG "FIFO write timed out\n"); |
1da177e4 LT |
568 | break; |
569 | } | |
3aeda9bc | 570 | ecrval = inb(ECONTROL(port)); |
1da177e4 LT |
571 | if (!(ecrval & (1<<2))) { |
572 | if (need_resched() && | |
3aeda9bc AC |
573 | time_before(jiffies, expire)) |
574 | schedule(); | |
1da177e4 LT |
575 | |
576 | goto false_alarm; | |
577 | } | |
578 | ||
579 | continue; | |
580 | } | |
581 | ||
582 | /* Can't fail now. */ | |
583 | expire = jiffies + port->cad->timeout; | |
584 | ||
3aeda9bc AC |
585 | poll: |
586 | if (signal_pending(current)) | |
1da177e4 LT |
587 | break; |
588 | ||
589 | if (ecrval & 0x01) { | |
590 | /* FIFO is empty. Blast it full. */ | |
591 | const int n = left < fifo_depth ? left : fifo_depth; | |
3aeda9bc | 592 | outsb(fifo, bufp, n); |
1da177e4 LT |
593 | bufp += n; |
594 | left -= n; | |
595 | ||
596 | /* Adjust the poll time. */ | |
3aeda9bc AC |
597 | if (i < (poll_for - 2)) |
598 | poll_for--; | |
1da177e4 LT |
599 | continue; |
600 | } else if (i++ < poll_for) { | |
3aeda9bc AC |
601 | udelay(10); |
602 | ecrval = inb(ECONTROL(port)); | |
1da177e4 LT |
603 | goto poll; |
604 | } | |
605 | ||
3aeda9bc | 606 | /* Half-full(call me an optimist) */ |
1da177e4 | 607 | byte = *bufp++; |
3aeda9bc | 608 | outb(byte, fifo); |
1da177e4 | 609 | left--; |
3aeda9bc AC |
610 | } |
611 | dump_parport_state("leave fifo_write_block_pio", port); | |
1da177e4 LT |
612 | return length - left; |
613 | } | |
614 | ||
7fbacd52 | 615 | #ifdef HAS_DMA |
3aeda9bc | 616 | static size_t parport_pc_fifo_write_block_dma(struct parport *port, |
1da177e4 LT |
617 | const void *buf, size_t length) |
618 | { | |
619 | int ret = 0; | |
620 | unsigned long dmaflag; | |
621 | size_t left = length; | |
622 | const struct parport_pc_private *priv = port->physport->private_data; | |
c15a3837 | 623 | struct device *dev = port->physport->dev; |
1da177e4 LT |
624 | dma_addr_t dma_addr, dma_handle; |
625 | size_t maxlen = 0x10000; /* max 64k per DMA transfer */ | |
626 | unsigned long start = (unsigned long) buf; | |
627 | unsigned long end = (unsigned long) buf + length - 1; | |
628 | ||
181bf1e8 | 629 | dump_parport_state("enter fifo_write_block_dma", port); |
1da177e4 LT |
630 | if (end < MAX_DMA_ADDRESS) { |
631 | /* If it would cross a 64k boundary, cap it at the end. */ | |
632 | if ((start ^ end) & ~0xffffUL) | |
633 | maxlen = 0x10000 - (start & 0xffff); | |
634 | ||
c15a3837 DB |
635 | dma_addr = dma_handle = dma_map_single(dev, (void *)buf, length, |
636 | DMA_TO_DEVICE); | |
3aeda9bc AC |
637 | } else { |
638 | /* above 16 MB we use a bounce buffer as ISA-DMA | |
639 | is not possible */ | |
1da177e4 LT |
640 | maxlen = PAGE_SIZE; /* sizeof(priv->dma_buf) */ |
641 | dma_addr = priv->dma_handle; | |
642 | dma_handle = 0; | |
643 | } | |
644 | ||
645 | port = port->physport; | |
646 | ||
647 | /* We don't want to be interrupted every character. */ | |
3aeda9bc | 648 | parport_pc_disable_irq(port); |
1da177e4 | 649 | /* set nErrIntrEn and serviceIntr */ |
3aeda9bc | 650 | frob_econtrol(port, (1<<4) | (1<<2), (1<<4) | (1<<2)); |
1da177e4 LT |
651 | |
652 | /* Forward mode. */ | |
3aeda9bc | 653 | parport_pc_data_forward(port); /* Must be in PS2 mode */ |
1da177e4 LT |
654 | |
655 | while (left) { | |
656 | unsigned long expire = jiffies + port->physport->cad->timeout; | |
657 | ||
658 | size_t count = left; | |
659 | ||
660 | if (count > maxlen) | |
661 | count = maxlen; | |
662 | ||
663 | if (!dma_handle) /* bounce buffer ! */ | |
664 | memcpy(priv->dma_buf, buf, count); | |
665 | ||
666 | dmaflag = claim_dma_lock(); | |
667 | disable_dma(port->dma); | |
668 | clear_dma_ff(port->dma); | |
669 | set_dma_mode(port->dma, DMA_MODE_WRITE); | |
670 | set_dma_addr(port->dma, dma_addr); | |
671 | set_dma_count(port->dma, count); | |
672 | ||
673 | /* Set DMA mode */ | |
3aeda9bc | 674 | frob_econtrol(port, 1<<3, 1<<3); |
1da177e4 LT |
675 | |
676 | /* Clear serviceIntr */ | |
3aeda9bc | 677 | frob_econtrol(port, 1<<2, 0); |
1da177e4 LT |
678 | |
679 | enable_dma(port->dma); | |
680 | release_dma_lock(dmaflag); | |
681 | ||
682 | /* assume DMA will be successful */ | |
683 | left -= count; | |
684 | buf += count; | |
3aeda9bc AC |
685 | if (dma_handle) |
686 | dma_addr += count; | |
1da177e4 LT |
687 | |
688 | /* Wait for interrupt. */ | |
3aeda9bc AC |
689 | false_alarm: |
690 | ret = parport_wait_event(port, HZ); | |
691 | if (ret < 0) | |
692 | break; | |
1da177e4 | 693 | ret = 0; |
3aeda9bc | 694 | if (!time_before(jiffies, expire)) { |
1da177e4 | 695 | /* Timed out. */ |
3aeda9bc | 696 | printk(KERN_DEBUG "DMA write timed out\n"); |
1da177e4 LT |
697 | break; |
698 | } | |
699 | /* Is serviceIntr set? */ | |
3aeda9bc | 700 | if (!(inb(ECONTROL(port)) & (1<<2))) { |
1da177e4 LT |
701 | cond_resched(); |
702 | ||
703 | goto false_alarm; | |
704 | } | |
705 | ||
706 | dmaflag = claim_dma_lock(); | |
707 | disable_dma(port->dma); | |
708 | clear_dma_ff(port->dma); | |
709 | count = get_dma_residue(port->dma); | |
710 | release_dma_lock(dmaflag); | |
711 | ||
712 | cond_resched(); /* Can't yield the port. */ | |
713 | ||
714 | /* Anyone else waiting for the port? */ | |
715 | if (port->waithead) { | |
3aeda9bc | 716 | printk(KERN_DEBUG "Somebody wants the port\n"); |
1da177e4 LT |
717 | break; |
718 | } | |
719 | ||
720 | /* update for possible DMA residue ! */ | |
721 | buf -= count; | |
722 | left += count; | |
3aeda9bc AC |
723 | if (dma_handle) |
724 | dma_addr -= count; | |
1da177e4 LT |
725 | } |
726 | ||
727 | /* Maybe got here through break, so adjust for DMA residue! */ | |
728 | dmaflag = claim_dma_lock(); | |
729 | disable_dma(port->dma); | |
730 | clear_dma_ff(port->dma); | |
731 | left += get_dma_residue(port->dma); | |
732 | release_dma_lock(dmaflag); | |
733 | ||
734 | /* Turn off DMA mode */ | |
3aeda9bc | 735 | frob_econtrol(port, 1<<3, 0); |
c15a3837 | 736 | |
1da177e4 | 737 | if (dma_handle) |
c15a3837 | 738 | dma_unmap_single(dev, dma_handle, length, DMA_TO_DEVICE); |
1da177e4 | 739 | |
181bf1e8 | 740 | dump_parport_state("leave fifo_write_block_dma", port); |
1da177e4 LT |
741 | return length - left; |
742 | } | |
7fbacd52 AV |
743 | #endif |
744 | ||
745 | static inline size_t parport_pc_fifo_write_block(struct parport *port, | |
746 | const void *buf, size_t length) | |
747 | { | |
748 | #ifdef HAS_DMA | |
749 | if (port->dma != PARPORT_DMA_NONE) | |
3aeda9bc | 750 | return parport_pc_fifo_write_block_dma(port, buf, length); |
7fbacd52 | 751 | #endif |
3aeda9bc | 752 | return parport_pc_fifo_write_block_pio(port, buf, length); |
7fbacd52 | 753 | } |
1da177e4 LT |
754 | |
755 | /* Parallel Port FIFO mode (ECP chipsets) */ | |
3aeda9bc | 756 | static size_t parport_pc_compat_write_block_pio(struct parport *port, |
1da177e4 LT |
757 | const void *buf, size_t length, |
758 | int flags) | |
759 | { | |
760 | size_t written; | |
761 | int r; | |
762 | unsigned long expire; | |
763 | const struct parport_pc_private *priv = port->physport->private_data; | |
764 | ||
765 | /* Special case: a timeout of zero means we cannot call schedule(). | |
766 | * Also if O_NONBLOCK is set then use the default implementation. */ | |
767 | if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK) | |
3aeda9bc | 768 | return parport_ieee1284_write_compat(port, buf, |
1da177e4 LT |
769 | length, flags); |
770 | ||
771 | /* Set up parallel port FIFO mode.*/ | |
3aeda9bc AC |
772 | parport_pc_data_forward(port); /* Must be in PS2 mode */ |
773 | parport_pc_frob_control(port, PARPORT_CONTROL_STROBE, 0); | |
774 | r = change_mode(port, ECR_PPF); /* Parallel port FIFO */ | |
775 | if (r) | |
776 | printk(KERN_DEBUG "%s: Warning change_mode ECR_PPF failed\n", | |
777 | port->name); | |
1da177e4 LT |
778 | |
779 | port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA; | |
780 | ||
781 | /* Write the data to the FIFO. */ | |
7fbacd52 | 782 | written = parport_pc_fifo_write_block(port, buf, length); |
1da177e4 LT |
783 | |
784 | /* Finish up. */ | |
785 | /* For some hardware we don't want to touch the mode until | |
786 | * the FIFO is empty, so allow 4 seconds for each position | |
787 | * in the fifo. | |
788 | */ | |
3aeda9bc | 789 | expire = jiffies + (priv->fifo_depth * HZ * 4); |
1da177e4 LT |
790 | do { |
791 | /* Wait for the FIFO to empty */ | |
3aeda9bc AC |
792 | r = change_mode(port, ECR_PS2); |
793 | if (r != -EBUSY) | |
1da177e4 | 794 | break; |
3aeda9bc | 795 | } while (time_before(jiffies, expire)); |
1da177e4 LT |
796 | if (r == -EBUSY) { |
797 | ||
3aeda9bc | 798 | printk(KERN_DEBUG "%s: FIFO is stuck\n", port->name); |
1da177e4 LT |
799 | |
800 | /* Prevent further data transfer. */ | |
3aeda9bc | 801 | frob_set_mode(port, ECR_TST); |
1da177e4 LT |
802 | |
803 | /* Adjust for the contents of the FIFO. */ | |
804 | for (written -= priv->fifo_depth; ; written++) { | |
3aeda9bc | 805 | if (inb(ECONTROL(port)) & 0x2) { |
1da177e4 LT |
806 | /* Full up. */ |
807 | break; | |
808 | } | |
3aeda9bc | 809 | outb(0, FIFO(port)); |
1da177e4 LT |
810 | } |
811 | ||
812 | /* Reset the FIFO and return to PS2 mode. */ | |
3aeda9bc | 813 | frob_set_mode(port, ECR_PS2); |
1da177e4 LT |
814 | } |
815 | ||
3aeda9bc | 816 | r = parport_wait_peripheral(port, |
1da177e4 LT |
817 | PARPORT_STATUS_BUSY, |
818 | PARPORT_STATUS_BUSY); | |
819 | if (r) | |
3aeda9bc AC |
820 | printk(KERN_DEBUG |
821 | "%s: BUSY timeout (%d) in compat_write_block_pio\n", | |
1da177e4 LT |
822 | port->name, r); |
823 | ||
824 | port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE; | |
825 | ||
826 | return written; | |
827 | } | |
828 | ||
829 | /* ECP */ | |
830 | #ifdef CONFIG_PARPORT_1284 | |
3aeda9bc | 831 | static size_t parport_pc_ecp_write_block_pio(struct parport *port, |
1da177e4 LT |
832 | const void *buf, size_t length, |
833 | int flags) | |
834 | { | |
835 | size_t written; | |
836 | int r; | |
837 | unsigned long expire; | |
838 | const struct parport_pc_private *priv = port->physport->private_data; | |
839 | ||
840 | /* Special case: a timeout of zero means we cannot call schedule(). | |
841 | * Also if O_NONBLOCK is set then use the default implementation. */ | |
842 | if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK) | |
3aeda9bc | 843 | return parport_ieee1284_ecp_write_data(port, buf, |
1da177e4 LT |
844 | length, flags); |
845 | ||
846 | /* Switch to forward mode if necessary. */ | |
847 | if (port->physport->ieee1284.phase != IEEE1284_PH_FWD_IDLE) { | |
848 | /* Event 47: Set nInit high. */ | |
3aeda9bc | 849 | parport_frob_control(port, |
1da177e4 LT |
850 | PARPORT_CONTROL_INIT |
851 | | PARPORT_CONTROL_AUTOFD, | |
852 | PARPORT_CONTROL_INIT | |
853 | | PARPORT_CONTROL_AUTOFD); | |
854 | ||
855 | /* Event 49: PError goes high. */ | |
3aeda9bc | 856 | r = parport_wait_peripheral(port, |
1da177e4 LT |
857 | PARPORT_STATUS_PAPEROUT, |
858 | PARPORT_STATUS_PAPEROUT); | |
859 | if (r) { | |
3aeda9bc | 860 | printk(KERN_DEBUG "%s: PError timeout (%d) " |
1da177e4 LT |
861 | "in ecp_write_block_pio\n", port->name, r); |
862 | } | |
863 | } | |
864 | ||
865 | /* Set up ECP parallel port mode.*/ | |
3aeda9bc AC |
866 | parport_pc_data_forward(port); /* Must be in PS2 mode */ |
867 | parport_pc_frob_control(port, | |
1da177e4 LT |
868 | PARPORT_CONTROL_STROBE | |
869 | PARPORT_CONTROL_AUTOFD, | |
870 | 0); | |
3aeda9bc AC |
871 | r = change_mode(port, ECR_ECP); /* ECP FIFO */ |
872 | if (r) | |
873 | printk(KERN_DEBUG "%s: Warning change_mode ECR_ECP failed\n", | |
874 | port->name); | |
1da177e4 LT |
875 | port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA; |
876 | ||
877 | /* Write the data to the FIFO. */ | |
7fbacd52 | 878 | written = parport_pc_fifo_write_block(port, buf, length); |
1da177e4 LT |
879 | |
880 | /* Finish up. */ | |
881 | /* For some hardware we don't want to touch the mode until | |
882 | * the FIFO is empty, so allow 4 seconds for each position | |
883 | * in the fifo. | |
884 | */ | |
885 | expire = jiffies + (priv->fifo_depth * (HZ * 4)); | |
886 | do { | |
887 | /* Wait for the FIFO to empty */ | |
3aeda9bc AC |
888 | r = change_mode(port, ECR_PS2); |
889 | if (r != -EBUSY) | |
1da177e4 | 890 | break; |
3aeda9bc | 891 | } while (time_before(jiffies, expire)); |
1da177e4 LT |
892 | if (r == -EBUSY) { |
893 | ||
3aeda9bc | 894 | printk(KERN_DEBUG "%s: FIFO is stuck\n", port->name); |
1da177e4 LT |
895 | |
896 | /* Prevent further data transfer. */ | |
3aeda9bc | 897 | frob_set_mode(port, ECR_TST); |
1da177e4 LT |
898 | |
899 | /* Adjust for the contents of the FIFO. */ | |
900 | for (written -= priv->fifo_depth; ; written++) { | |
3aeda9bc | 901 | if (inb(ECONTROL(port)) & 0x2) { |
1da177e4 LT |
902 | /* Full up. */ |
903 | break; | |
904 | } | |
3aeda9bc | 905 | outb(0, FIFO(port)); |
1da177e4 LT |
906 | } |
907 | ||
908 | /* Reset the FIFO and return to PS2 mode. */ | |
3aeda9bc | 909 | frob_set_mode(port, ECR_PS2); |
1da177e4 LT |
910 | |
911 | /* Host transfer recovery. */ | |
3aeda9bc AC |
912 | parport_pc_data_reverse(port); /* Must be in PS2 mode */ |
913 | udelay(5); | |
914 | parport_frob_control(port, PARPORT_CONTROL_INIT, 0); | |
915 | r = parport_wait_peripheral(port, PARPORT_STATUS_PAPEROUT, 0); | |
1da177e4 | 916 | if (r) |
3aeda9bc | 917 | printk(KERN_DEBUG "%s: PE,1 timeout (%d) " |
1da177e4 LT |
918 | "in ecp_write_block_pio\n", port->name, r); |
919 | ||
3aeda9bc | 920 | parport_frob_control(port, |
1da177e4 LT |
921 | PARPORT_CONTROL_INIT, |
922 | PARPORT_CONTROL_INIT); | |
3aeda9bc | 923 | r = parport_wait_peripheral(port, |
1da177e4 LT |
924 | PARPORT_STATUS_PAPEROUT, |
925 | PARPORT_STATUS_PAPEROUT); | |
3aeda9bc AC |
926 | if (r) |
927 | printk(KERN_DEBUG "%s: PE,2 timeout (%d) " | |
1da177e4 LT |
928 | "in ecp_write_block_pio\n", port->name, r); |
929 | } | |
930 | ||
3aeda9bc AC |
931 | r = parport_wait_peripheral(port, |
932 | PARPORT_STATUS_BUSY, | |
1da177e4 | 933 | PARPORT_STATUS_BUSY); |
3aeda9bc AC |
934 | if (r) |
935 | printk(KERN_DEBUG | |
1da177e4 LT |
936 | "%s: BUSY timeout (%d) in ecp_write_block_pio\n", |
937 | port->name, r); | |
938 | ||
939 | port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE; | |
940 | ||
941 | return written; | |
942 | } | |
943 | ||
944 | #if 0 | |
3aeda9bc | 945 | static size_t parport_pc_ecp_read_block_pio(struct parport *port, |
1da177e4 LT |
946 | void *buf, size_t length, |
947 | int flags) | |
948 | { | |
949 | size_t left = length; | |
950 | size_t fifofull; | |
951 | int r; | |
952 | const int fifo = FIFO(port); | |
953 | const struct parport_pc_private *priv = port->physport->private_data; | |
954 | const int fifo_depth = priv->fifo_depth; | |
955 | char *bufp = buf; | |
956 | ||
957 | port = port->physport; | |
181bf1e8 AC |
958 | DPRINTK(KERN_DEBUG "parport_pc: parport_pc_ecp_read_block_pio\n"); |
959 | dump_parport_state("enter fcn", port); | |
1da177e4 LT |
960 | |
961 | /* Special case: a timeout of zero means we cannot call schedule(). | |
962 | * Also if O_NONBLOCK is set then use the default implementation. */ | |
963 | if (port->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK) | |
3aeda9bc | 964 | return parport_ieee1284_ecp_read_data(port, buf, |
1da177e4 LT |
965 | length, flags); |
966 | ||
967 | if (port->ieee1284.mode == IEEE1284_MODE_ECPRLE) { | |
968 | /* If the peripheral is allowed to send RLE compressed | |
969 | * data, it is possible for a byte to expand to 128 | |
970 | * bytes in the FIFO. */ | |
971 | fifofull = 128; | |
972 | } else { | |
973 | fifofull = fifo_depth; | |
974 | } | |
975 | ||
976 | /* If the caller wants less than a full FIFO's worth of data, | |
977 | * go through software emulation. Otherwise we may have to throw | |
978 | * away data. */ | |
979 | if (length < fifofull) | |
3aeda9bc | 980 | return parport_ieee1284_ecp_read_data(port, buf, |
1da177e4 LT |
981 | length, flags); |
982 | ||
983 | if (port->ieee1284.phase != IEEE1284_PH_REV_IDLE) { | |
984 | /* change to reverse-idle phase (must be in forward-idle) */ | |
985 | ||
986 | /* Event 38: Set nAutoFd low (also make sure nStrobe is high) */ | |
3aeda9bc | 987 | parport_frob_control(port, |
1da177e4 LT |
988 | PARPORT_CONTROL_AUTOFD |
989 | | PARPORT_CONTROL_STROBE, | |
990 | PARPORT_CONTROL_AUTOFD); | |
3aeda9bc AC |
991 | parport_pc_data_reverse(port); /* Must be in PS2 mode */ |
992 | udelay(5); | |
1da177e4 | 993 | /* Event 39: Set nInit low to initiate bus reversal */ |
3aeda9bc | 994 | parport_frob_control(port, |
1da177e4 LT |
995 | PARPORT_CONTROL_INIT, |
996 | 0); | |
997 | /* Event 40: Wait for nAckReverse (PError) to go low */ | |
3aeda9bc AC |
998 | r = parport_wait_peripheral(port, PARPORT_STATUS_PAPEROUT, 0); |
999 | if (r) { | |
1000 | printk(KERN_DEBUG "%s: PE timeout Event 40 (%d) " | |
1da177e4 LT |
1001 | "in ecp_read_block_pio\n", port->name, r); |
1002 | return 0; | |
1003 | } | |
1004 | } | |
1005 | ||
1006 | /* Set up ECP FIFO mode.*/ | |
3aeda9bc | 1007 | /* parport_pc_frob_control(port, |
1da177e4 LT |
1008 | PARPORT_CONTROL_STROBE | |
1009 | PARPORT_CONTROL_AUTOFD, | |
1010 | PARPORT_CONTROL_AUTOFD); */ | |
3aeda9bc AC |
1011 | r = change_mode(port, ECR_ECP); /* ECP FIFO */ |
1012 | if (r) | |
1013 | printk(KERN_DEBUG "%s: Warning change_mode ECR_ECP failed\n", | |
1014 | port->name); | |
1da177e4 LT |
1015 | |
1016 | port->ieee1284.phase = IEEE1284_PH_REV_DATA; | |
1017 | ||
1018 | /* the first byte must be collected manually */ | |
3aeda9bc | 1019 | dump_parport_state("pre 43", port); |
1da177e4 | 1020 | /* Event 43: Wait for nAck to go low */ |
3aeda9bc | 1021 | r = parport_wait_peripheral(port, PARPORT_STATUS_ACK, 0); |
1da177e4 LT |
1022 | if (r) { |
1023 | /* timed out while reading -- no data */ | |
3aeda9bc | 1024 | printk(KERN_DEBUG "PIO read timed out (initial byte)\n"); |
1da177e4 LT |
1025 | goto out_no_data; |
1026 | } | |
1027 | /* read byte */ | |
3aeda9bc | 1028 | *bufp++ = inb(DATA(port)); |
1da177e4 | 1029 | left--; |
3aeda9bc | 1030 | dump_parport_state("43-44", port); |
1da177e4 | 1031 | /* Event 44: nAutoFd (HostAck) goes high to acknowledge */ |
3aeda9bc | 1032 | parport_pc_frob_control(port, |
1da177e4 LT |
1033 | PARPORT_CONTROL_AUTOFD, |
1034 | 0); | |
3aeda9bc | 1035 | dump_parport_state("pre 45", port); |
1da177e4 | 1036 | /* Event 45: Wait for nAck to go high */ |
3aeda9bc AC |
1037 | /* r = parport_wait_peripheral(port, PARPORT_STATUS_ACK, |
1038 | PARPORT_STATUS_ACK); */ | |
1039 | dump_parport_state("post 45", port); | |
1040 | r = 0; | |
1da177e4 LT |
1041 | if (r) { |
1042 | /* timed out while waiting for peripheral to respond to ack */ | |
3aeda9bc | 1043 | printk(KERN_DEBUG "ECP PIO read timed out (waiting for nAck)\n"); |
1da177e4 LT |
1044 | |
1045 | /* keep hold of the byte we've got already */ | |
1046 | goto out_no_data; | |
1047 | } | |
1048 | /* Event 46: nAutoFd (HostAck) goes low to accept more data */ | |
3aeda9bc | 1049 | parport_pc_frob_control(port, |
1da177e4 LT |
1050 | PARPORT_CONTROL_AUTOFD, |
1051 | PARPORT_CONTROL_AUTOFD); | |
1052 | ||
1053 | ||
3aeda9bc | 1054 | dump_parport_state("rev idle", port); |
1da177e4 LT |
1055 | /* Do the transfer. */ |
1056 | while (left > fifofull) { | |
1057 | int ret; | |
1058 | unsigned long expire = jiffies + port->cad->timeout; | |
3aeda9bc | 1059 | unsigned char ecrval = inb(ECONTROL(port)); |
1da177e4 | 1060 | |
3aeda9bc | 1061 | if (need_resched() && time_before(jiffies, expire)) |
1da177e4 | 1062 | /* Can't yield the port. */ |
3aeda9bc | 1063 | schedule(); |
1da177e4 LT |
1064 | |
1065 | /* At this point, the FIFO may already be full. In | |
3aeda9bc AC |
1066 | * that case ECP is already holding back the |
1067 | * peripheral (assuming proper design) with a delayed | |
1068 | * handshake. Work fast to avoid a peripheral | |
1069 | * timeout. */ | |
1da177e4 LT |
1070 | |
1071 | if (ecrval & 0x01) { | |
1072 | /* FIFO is empty. Wait for interrupt. */ | |
3aeda9bc | 1073 | dump_parport_state("FIFO empty", port); |
1da177e4 LT |
1074 | |
1075 | /* Anyone else waiting for the port? */ | |
1076 | if (port->waithead) { | |
3aeda9bc | 1077 | printk(KERN_DEBUG "Somebody wants the port\n"); |
1da177e4 LT |
1078 | break; |
1079 | } | |
1080 | ||
1081 | /* Clear serviceIntr */ | |
3aeda9bc AC |
1082 | ECR_WRITE(port, ecrval & ~(1<<2)); |
1083 | false_alarm: | |
1084 | dump_parport_state("waiting", port); | |
1085 | ret = parport_wait_event(port, HZ); | |
1086 | DPRINTK(KERN_DEBUG "parport_wait_event returned %d\n", | |
1087 | ret); | |
1da177e4 LT |
1088 | if (ret < 0) |
1089 | break; | |
1090 | ret = 0; | |
3aeda9bc | 1091 | if (!time_before(jiffies, expire)) { |
1da177e4 | 1092 | /* Timed out. */ |
3aeda9bc AC |
1093 | dump_parport_state("timeout", port); |
1094 | printk(KERN_DEBUG "PIO read timed out\n"); | |
1da177e4 LT |
1095 | break; |
1096 | } | |
3aeda9bc | 1097 | ecrval = inb(ECONTROL(port)); |
1da177e4 LT |
1098 | if (!(ecrval & (1<<2))) { |
1099 | if (need_resched() && | |
3aeda9bc AC |
1100 | time_before(jiffies, expire)) { |
1101 | schedule(); | |
1da177e4 LT |
1102 | } |
1103 | goto false_alarm; | |
1104 | } | |
1105 | ||
1106 | /* Depending on how the FIFO threshold was | |
3aeda9bc AC |
1107 | * set, how long interrupt service took, and |
1108 | * how fast the peripheral is, we might be | |
1109 | * lucky and have a just filled FIFO. */ | |
1da177e4 LT |
1110 | continue; |
1111 | } | |
1112 | ||
1113 | if (ecrval & 0x02) { | |
1114 | /* FIFO is full. */ | |
181bf1e8 | 1115 | dump_parport_state("FIFO full", port); |
3aeda9bc | 1116 | insb(fifo, bufp, fifo_depth); |
1da177e4 LT |
1117 | bufp += fifo_depth; |
1118 | left -= fifo_depth; | |
1119 | continue; | |
1120 | } | |
1121 | ||
181bf1e8 AC |
1122 | DPRINTK(KERN_DEBUG |
1123 | "*** ecp_read_block_pio: reading one byte from the FIFO\n"); | |
1da177e4 LT |
1124 | |
1125 | /* FIFO not filled. We will cycle this loop for a while | |
3aeda9bc AC |
1126 | * and either the peripheral will fill it faster, |
1127 | * tripping a fast empty with insb, or we empty it. */ | |
1128 | *bufp++ = inb(fifo); | |
1da177e4 LT |
1129 | left--; |
1130 | } | |
1131 | ||
1132 | /* scoop up anything left in the FIFO */ | |
3aeda9bc AC |
1133 | while (left && !(inb(ECONTROL(port) & 0x01))) { |
1134 | *bufp++ = inb(fifo); | |
1da177e4 LT |
1135 | left--; |
1136 | } | |
1137 | ||
1138 | port->ieee1284.phase = IEEE1284_PH_REV_IDLE; | |
181bf1e8 | 1139 | dump_parport_state("rev idle2", port); |
1da177e4 LT |
1140 | |
1141 | out_no_data: | |
1142 | ||
1143 | /* Go to forward idle mode to shut the peripheral up (event 47). */ | |
3aeda9bc | 1144 | parport_frob_control(port, PARPORT_CONTROL_INIT, PARPORT_CONTROL_INIT); |
1da177e4 LT |
1145 | |
1146 | /* event 49: PError goes high */ | |
3aeda9bc | 1147 | r = parport_wait_peripheral(port, |
1da177e4 LT |
1148 | PARPORT_STATUS_PAPEROUT, |
1149 | PARPORT_STATUS_PAPEROUT); | |
1150 | if (r) { | |
3aeda9bc | 1151 | printk(KERN_DEBUG |
1da177e4 LT |
1152 | "%s: PE timeout FWDIDLE (%d) in ecp_read_block_pio\n", |
1153 | port->name, r); | |
1154 | } | |
1155 | ||
1156 | port->ieee1284.phase = IEEE1284_PH_FWD_IDLE; | |
1157 | ||
1158 | /* Finish up. */ | |
1159 | { | |
3aeda9bc | 1160 | int lost = get_fifo_residue(port); |
1da177e4 LT |
1161 | if (lost) |
1162 | /* Shouldn't happen with compliant peripherals. */ | |
3aeda9bc | 1163 | printk(KERN_DEBUG "%s: DATA LOSS (%d bytes)!\n", |
1da177e4 LT |
1164 | port->name, lost); |
1165 | } | |
1166 | ||
181bf1e8 | 1167 | dump_parport_state("fwd idle", port); |
1da177e4 LT |
1168 | return length - left; |
1169 | } | |
1170 | #endif /* 0 */ | |
1171 | #endif /* IEEE 1284 support */ | |
1172 | #endif /* Allowed to use FIFO/DMA */ | |
1173 | ||
1174 | ||
1175 | /* | |
1176 | * ****************************************** | |
1177 | * INITIALISATION AND MODULE STUFF BELOW HERE | |
1178 | * ****************************************** | |
1179 | */ | |
1180 | ||
1181 | /* GCC is not inlining extern inline function later overwriten to non-inline, | |
1182 | so we use outlined_ variants here. */ | |
3aeda9bc | 1183 | static const struct parport_operations parport_pc_ops = { |
1da177e4 LT |
1184 | .write_data = parport_pc_write_data, |
1185 | .read_data = parport_pc_read_data, | |
1186 | ||
1187 | .write_control = parport_pc_write_control, | |
1188 | .read_control = parport_pc_read_control, | |
1189 | .frob_control = parport_pc_frob_control, | |
1190 | ||
1191 | .read_status = parport_pc_read_status, | |
1192 | ||
1193 | .enable_irq = parport_pc_enable_irq, | |
1194 | .disable_irq = parport_pc_disable_irq, | |
1195 | ||
1196 | .data_forward = parport_pc_data_forward, | |
1197 | .data_reverse = parport_pc_data_reverse, | |
1198 | ||
1199 | .init_state = parport_pc_init_state, | |
1200 | .save_state = parport_pc_save_state, | |
1201 | .restore_state = parport_pc_restore_state, | |
1202 | ||
1203 | .epp_write_data = parport_ieee1284_epp_write_data, | |
1204 | .epp_read_data = parport_ieee1284_epp_read_data, | |
1205 | .epp_write_addr = parport_ieee1284_epp_write_addr, | |
1206 | .epp_read_addr = parport_ieee1284_epp_read_addr, | |
1207 | ||
1208 | .ecp_write_data = parport_ieee1284_ecp_write_data, | |
1209 | .ecp_read_data = parport_ieee1284_ecp_read_data, | |
1210 | .ecp_write_addr = parport_ieee1284_ecp_write_addr, | |
1211 | ||
1212 | .compat_write_data = parport_ieee1284_write_compat, | |
1213 | .nibble_read_data = parport_ieee1284_read_nibble, | |
1214 | .byte_read_data = parport_ieee1284_read_byte, | |
1215 | ||
1216 | .owner = THIS_MODULE, | |
1217 | }; | |
1218 | ||
1219 | #ifdef CONFIG_PARPORT_PC_SUPERIO | |
181bf1e8 AC |
1220 | |
1221 | static struct superio_struct *find_free_superio(void) | |
1222 | { | |
1223 | int i; | |
1224 | for (i = 0; i < NR_SUPERIOS; i++) | |
1225 | if (superios[i].io == 0) | |
1226 | return &superios[i]; | |
1227 | return NULL; | |
1228 | } | |
1229 | ||
1230 | ||
1da177e4 LT |
1231 | /* Super-IO chipset detection, Winbond, SMSC */ |
1232 | static void __devinit show_parconfig_smsc37c669(int io, int key) | |
1233 | { | |
181bf1e8 AC |
1234 | int cr1, cr4, cra, cr23, cr26, cr27; |
1235 | struct superio_struct *s; | |
1236 | ||
3aeda9bc | 1237 | static const char *const modes[] = { |
a6767b7c MK |
1238 | "SPP and Bidirectional (PS/2)", |
1239 | "EPP and SPP", | |
1240 | "ECP", | |
1241 | "ECP and EPP" }; | |
1da177e4 | 1242 | |
3aeda9bc AC |
1243 | outb(key, io); |
1244 | outb(key, io); | |
1245 | outb(1, io); | |
1246 | cr1 = inb(io + 1); | |
1247 | outb(4, io); | |
1248 | cr4 = inb(io + 1); | |
1249 | outb(0x0a, io); | |
1250 | cra = inb(io + 1); | |
1251 | outb(0x23, io); | |
1252 | cr23 = inb(io + 1); | |
1253 | outb(0x26, io); | |
1254 | cr26 = inb(io + 1); | |
1255 | outb(0x27, io); | |
1256 | cr27 = inb(io + 1); | |
1257 | outb(0xaa, io); | |
1da177e4 LT |
1258 | |
1259 | if (verbose_probing) { | |
3aeda9bc AC |
1260 | printk(KERN_INFO |
1261 | "SMSC 37c669 LPT Config: cr_1=0x%02x, 4=0x%02x, " | |
1da177e4 | 1262 | "A=0x%2x, 23=0x%02x, 26=0x%02x, 27=0x%02x\n", |
3aeda9bc AC |
1263 | cr1, cr4, cra, cr23, cr26, cr27); |
1264 | ||
1da177e4 LT |
1265 | /* The documentation calls DMA and IRQ-Lines by letters, so |
1266 | the board maker can/will wire them | |
1267 | appropriately/randomly... G=reserved H=IDE-irq, */ | |
3aeda9bc AC |
1268 | printk(KERN_INFO |
1269 | "SMSC LPT Config: io=0x%04x, irq=%c, dma=%c, fifo threshold=%d\n", | |
1270 | cr23 * 4, | |
1271 | (cr27 & 0x0f) ? 'A' - 1 + (cr27 & 0x0f) : '-', | |
1272 | (cr26 & 0x0f) ? 'A' - 1 + (cr26 & 0x0f) : '-', | |
1273 | cra & 0x0f); | |
1da177e4 | 1274 | printk(KERN_INFO "SMSC LPT Config: enabled=%s power=%s\n", |
3aeda9bc AC |
1275 | (cr23 * 4 >= 0x100) ? "yes" : "no", |
1276 | (cr1 & 4) ? "yes" : "no"); | |
1277 | printk(KERN_INFO | |
1278 | "SMSC LPT Config: Port mode=%s, EPP version =%s\n", | |
1279 | (cr1 & 0x08) ? "Standard mode only (SPP)" | |
1280 | : modes[cr4 & 0x03], | |
1281 | (cr4 & 0x40) ? "1.7" : "1.9"); | |
1da177e4 | 1282 | } |
73e0d48b | 1283 | |
1da177e4 LT |
1284 | /* Heuristics ! BIOS setup for this mainboard device limits |
1285 | the choices to standard settings, i.e. io-address and IRQ | |
1286 | are related, however DMA can be 1 or 3, assume DMA_A=DMA1, | |
1287 | DMA_C=DMA3 (this is true e.g. for TYAN 1564D Tomcat IV) */ | |
73e0d48b | 1288 | if (cr23 * 4 >= 0x100) { /* if active */ |
181bf1e8 AC |
1289 | s = find_free_superio(); |
1290 | if (s == NULL) | |
1da177e4 | 1291 | printk(KERN_INFO "Super-IO: too many chips!\n"); |
181bf1e8 | 1292 | else { |
1da177e4 | 1293 | int d; |
3aeda9bc AC |
1294 | switch (cr23 * 4) { |
1295 | case 0x3bc: | |
181bf1e8 AC |
1296 | s->io = 0x3bc; |
1297 | s->irq = 7; | |
3aeda9bc AC |
1298 | break; |
1299 | case 0x378: | |
181bf1e8 AC |
1300 | s->io = 0x378; |
1301 | s->irq = 7; | |
3aeda9bc AC |
1302 | break; |
1303 | case 0x278: | |
181bf1e8 AC |
1304 | s->io = 0x278; |
1305 | s->irq = 5; | |
1da177e4 | 1306 | } |
3aeda9bc AC |
1307 | d = (cr26 & 0x0f); |
1308 | if (d == 1 || d == 3) | |
181bf1e8 | 1309 | s->dma = d; |
1da177e4 | 1310 | else |
181bf1e8 | 1311 | s->dma = PARPORT_DMA_NONE; |
1da177e4 | 1312 | } |
3aeda9bc | 1313 | } |
1da177e4 LT |
1314 | } |
1315 | ||
1316 | ||
1317 | static void __devinit show_parconfig_winbond(int io, int key) | |
1318 | { | |
181bf1e8 AC |
1319 | int cr30, cr60, cr61, cr70, cr74, crf0; |
1320 | struct superio_struct *s; | |
a6767b7c | 1321 | static const char *const modes[] = { |
1da177e4 LT |
1322 | "Standard (SPP) and Bidirectional(PS/2)", /* 0 */ |
1323 | "EPP-1.9 and SPP", | |
1324 | "ECP", | |
1325 | "ECP and EPP-1.9", | |
1326 | "Standard (SPP)", | |
1327 | "EPP-1.7 and SPP", /* 5 */ | |
1328 | "undefined!", | |
1329 | "ECP and EPP-1.7" }; | |
a6767b7c MK |
1330 | static char *const irqtypes[] = { |
1331 | "pulsed low, high-Z", | |
1332 | "follows nACK" }; | |
3aeda9bc | 1333 | |
1da177e4 | 1334 | /* The registers are called compatible-PnP because the |
3aeda9bc AC |
1335 | register layout is modelled after ISA-PnP, the access |
1336 | method is just another ... */ | |
1337 | outb(key, io); | |
1338 | outb(key, io); | |
1339 | outb(0x07, io); /* Register 7: Select Logical Device */ | |
1340 | outb(0x01, io + 1); /* LD1 is Parallel Port */ | |
1341 | outb(0x30, io); | |
1342 | cr30 = inb(io + 1); | |
1343 | outb(0x60, io); | |
1344 | cr60 = inb(io + 1); | |
1345 | outb(0x61, io); | |
1346 | cr61 = inb(io + 1); | |
1347 | outb(0x70, io); | |
1348 | cr70 = inb(io + 1); | |
1349 | outb(0x74, io); | |
1350 | cr74 = inb(io + 1); | |
1351 | outb(0xf0, io); | |
1352 | crf0 = inb(io + 1); | |
1353 | outb(0xaa, io); | |
1da177e4 LT |
1354 | |
1355 | if (verbose_probing) { | |
3aeda9bc AC |
1356 | printk(KERN_INFO |
1357 | "Winbond LPT Config: cr_30=%02x 60,61=%02x%02x 70=%02x 74=%02x, f0=%02x\n", | |
1358 | cr30, cr60, cr61, cr70, cr74, crf0); | |
1359 | printk(KERN_INFO "Winbond LPT Config: active=%s, io=0x%02x%02x irq=%d, ", | |
1360 | (cr30 & 0x01) ? "yes" : "no", cr60, cr61, cr70 & 0x0f); | |
1da177e4 LT |
1361 | if ((cr74 & 0x07) > 3) |
1362 | printk("dma=none\n"); | |
1363 | else | |
3aeda9bc AC |
1364 | printk("dma=%d\n", cr74 & 0x07); |
1365 | printk(KERN_INFO | |
1366 | "Winbond LPT Config: irqtype=%s, ECP fifo threshold=%d\n", | |
1367 | irqtypes[crf0>>7], (crf0>>3)&0x0f); | |
1368 | printk(KERN_INFO "Winbond LPT Config: Port mode=%s\n", | |
1369 | modes[crf0 & 0x07]); | |
1da177e4 LT |
1370 | } |
1371 | ||
73e0d48b | 1372 | if (cr30 & 0x01) { /* the settings can be interrogated later ... */ |
181bf1e8 AC |
1373 | s = find_free_superio(); |
1374 | if (s == NULL) | |
1da177e4 | 1375 | printk(KERN_INFO "Super-IO: too many chips!\n"); |
181bf1e8 AC |
1376 | else { |
1377 | s->io = (cr60 << 8) | cr61; | |
1378 | s->irq = cr70 & 0x0f; | |
1379 | s->dma = (((cr74 & 0x07) > 3) ? | |
1da177e4 LT |
1380 | PARPORT_DMA_NONE : (cr74 & 0x07)); |
1381 | } | |
1382 | } | |
1383 | } | |
1384 | ||
3aeda9bc AC |
1385 | static void __devinit decode_winbond(int efer, int key, int devid, |
1386 | int devrev, int oldid) | |
1da177e4 LT |
1387 | { |
1388 | const char *type = "unknown"; | |
3aeda9bc | 1389 | int id, progif = 2; |
1da177e4 LT |
1390 | |
1391 | if (devid == devrev) | |
1392 | /* simple heuristics, we happened to read some | |
3aeda9bc | 1393 | non-winbond register */ |
1da177e4 LT |
1394 | return; |
1395 | ||
3aeda9bc | 1396 | id = (devid << 8) | devrev; |
1da177e4 LT |
1397 | |
1398 | /* Values are from public data sheets pdf files, I can just | |
3aeda9bc AC |
1399 | confirm 83977TF is correct :-) */ |
1400 | if (id == 0x9771) | |
1401 | type = "83977F/AF"; | |
1402 | else if (id == 0x9773) | |
1403 | type = "83977TF / SMSC 97w33x/97w34x"; | |
1404 | else if (id == 0x9774) | |
1405 | type = "83977ATF"; | |
1406 | else if ((id & ~0x0f) == 0x5270) | |
1407 | type = "83977CTF / SMSC 97w36x"; | |
1408 | else if ((id & ~0x0f) == 0x52f0) | |
1409 | type = "83977EF / SMSC 97w35x"; | |
1410 | else if ((id & ~0x0f) == 0x5210) | |
1411 | type = "83627"; | |
1412 | else if ((id & ~0x0f) == 0x6010) | |
1413 | type = "83697HF"; | |
1414 | else if ((oldid & 0x0f) == 0x0a) { | |
1415 | type = "83877F"; | |
1416 | progif = 1; | |
1417 | } else if ((oldid & 0x0f) == 0x0b) { | |
1418 | type = "83877AF"; | |
1419 | progif = 1; | |
1420 | } else if ((oldid & 0x0f) == 0x0c) { | |
1421 | type = "83877TF"; | |
1422 | progif = 1; | |
1423 | } else if ((oldid & 0x0f) == 0x0d) { | |
1424 | type = "83877ATF"; | |
1425 | progif = 1; | |
1426 | } else | |
1427 | progif = 0; | |
1da177e4 LT |
1428 | |
1429 | if (verbose_probing) | |
1430 | printk(KERN_INFO "Winbond chip at EFER=0x%x key=0x%02x " | |
3aeda9bc | 1431 | "devid=%02x devrev=%02x oldid=%02x type=%s\n", |
1da177e4 LT |
1432 | efer, key, devid, devrev, oldid, type); |
1433 | ||
1434 | if (progif == 2) | |
3aeda9bc | 1435 | show_parconfig_winbond(efer, key); |
1da177e4 LT |
1436 | } |
1437 | ||
1438 | static void __devinit decode_smsc(int efer, int key, int devid, int devrev) | |
1439 | { | |
3aeda9bc | 1440 | const char *type = "unknown"; |
1da177e4 | 1441 | void (*func)(int io, int key); |
3aeda9bc | 1442 | int id; |
1da177e4 | 1443 | |
3aeda9bc | 1444 | if (devid == devrev) |
1da177e4 | 1445 | /* simple heuristics, we happened to read some |
3aeda9bc | 1446 | non-smsc register */ |
1da177e4 LT |
1447 | return; |
1448 | ||
3aeda9bc AC |
1449 | func = NULL; |
1450 | id = (devid << 8) | devrev; | |
1da177e4 | 1451 | |
3aeda9bc AC |
1452 | if (id == 0x0302) { |
1453 | type = "37c669"; | |
1454 | func = show_parconfig_smsc37c669; | |
1455 | } else if (id == 0x6582) | |
1456 | type = "37c665IR"; | |
1457 | else if (devid == 0x65) | |
1458 | type = "37c665GT"; | |
1459 | else if (devid == 0x66) | |
1460 | type = "37c666GT"; | |
1da177e4 LT |
1461 | |
1462 | if (verbose_probing) | |
1463 | printk(KERN_INFO "SMSC chip at EFER=0x%x " | |
1464 | "key=0x%02x devid=%02x devrev=%02x type=%s\n", | |
1465 | efer, key, devid, devrev, type); | |
1466 | ||
1467 | if (func) | |
3aeda9bc | 1468 | func(efer, key); |
1da177e4 LT |
1469 | } |
1470 | ||
1471 | ||
1472 | static void __devinit winbond_check(int io, int key) | |
1473 | { | |
e2434dc1 | 1474 | int origval, devid, devrev, oldid, x_devid, x_devrev, x_oldid; |
1da177e4 | 1475 | |
145980a0 | 1476 | if (!request_region(io, 3, __func__)) |
1da177e4 LT |
1477 | return; |
1478 | ||
e2434dc1 JR |
1479 | origval = inb(io); /* Save original value */ |
1480 | ||
1da177e4 | 1481 | /* First probe without key */ |
3aeda9bc AC |
1482 | outb(0x20, io); |
1483 | x_devid = inb(io + 1); | |
1484 | outb(0x21, io); | |
1485 | x_devrev = inb(io + 1); | |
1486 | outb(0x09, io); | |
1487 | x_oldid = inb(io + 1); | |
1488 | ||
1489 | outb(key, io); | |
1490 | outb(key, io); /* Write Magic Sequence to EFER, extended | |
1491 | funtion enable register */ | |
1492 | outb(0x20, io); /* Write EFIR, extended function index register */ | |
1493 | devid = inb(io + 1); /* Read EFDR, extended function data register */ | |
1494 | outb(0x21, io); | |
1495 | devrev = inb(io + 1); | |
1496 | outb(0x09, io); | |
1497 | oldid = inb(io + 1); | |
1498 | outb(0xaa, io); /* Magic Seal */ | |
1da177e4 | 1499 | |
e2434dc1 JR |
1500 | outb(origval, io); /* in case we poked some entirely different hardware */ |
1501 | ||
1da177e4 LT |
1502 | if ((x_devid == devid) && (x_devrev == devrev) && (x_oldid == oldid)) |
1503 | goto out; /* protection against false positives */ | |
1504 | ||
3aeda9bc | 1505 | decode_winbond(io, key, devid, devrev, oldid); |
1da177e4 LT |
1506 | out: |
1507 | release_region(io, 3); | |
1508 | } | |
1509 | ||
3aeda9bc | 1510 | static void __devinit winbond_check2(int io, int key) |
1da177e4 | 1511 | { |
e2434dc1 | 1512 | int origval[3], devid, devrev, oldid, x_devid, x_devrev, x_oldid; |
1da177e4 | 1513 | |
145980a0 | 1514 | if (!request_region(io, 3, __func__)) |
1da177e4 LT |
1515 | return; |
1516 | ||
e2434dc1 JR |
1517 | origval[0] = inb(io); /* Save original values */ |
1518 | origval[1] = inb(io + 1); | |
1519 | origval[2] = inb(io + 2); | |
1520 | ||
1da177e4 | 1521 | /* First probe without the key */ |
3aeda9bc AC |
1522 | outb(0x20, io + 2); |
1523 | x_devid = inb(io + 2); | |
1524 | outb(0x21, io + 1); | |
1525 | x_devrev = inb(io + 2); | |
1526 | outb(0x09, io + 1); | |
1527 | x_oldid = inb(io + 2); | |
1528 | ||
1529 | outb(key, io); /* Write Magic Byte to EFER, extended | |
1530 | funtion enable register */ | |
1531 | outb(0x20, io + 2); /* Write EFIR, extended function index register */ | |
1532 | devid = inb(io + 2); /* Read EFDR, extended function data register */ | |
1533 | outb(0x21, io + 1); | |
1534 | devrev = inb(io + 2); | |
1535 | outb(0x09, io + 1); | |
1536 | oldid = inb(io + 2); | |
1537 | outb(0xaa, io); /* Magic Seal */ | |
1538 | ||
e2434dc1 JR |
1539 | outb(origval[0], io); /* in case we poked some entirely different hardware */ |
1540 | outb(origval[1], io + 1); | |
1541 | outb(origval[2], io + 2); | |
1542 | ||
3aeda9bc | 1543 | if (x_devid == devid && x_devrev == devrev && x_oldid == oldid) |
1da177e4 LT |
1544 | goto out; /* protection against false positives */ |
1545 | ||
3aeda9bc | 1546 | decode_winbond(io, key, devid, devrev, oldid); |
1da177e4 LT |
1547 | out: |
1548 | release_region(io, 3); | |
1549 | } | |
1550 | ||
1551 | static void __devinit smsc_check(int io, int key) | |
1552 | { | |
e2434dc1 | 1553 | int origval, id, rev, oldid, oldrev, x_id, x_rev, x_oldid, x_oldrev; |
1da177e4 | 1554 | |
145980a0 | 1555 | if (!request_region(io, 3, __func__)) |
1da177e4 LT |
1556 | return; |
1557 | ||
e2434dc1 JR |
1558 | origval = inb(io); /* Save original value */ |
1559 | ||
1da177e4 | 1560 | /* First probe without the key */ |
3aeda9bc AC |
1561 | outb(0x0d, io); |
1562 | x_oldid = inb(io + 1); | |
1563 | outb(0x0e, io); | |
1564 | x_oldrev = inb(io + 1); | |
1565 | outb(0x20, io); | |
1566 | x_id = inb(io + 1); | |
1567 | outb(0x21, io); | |
1568 | x_rev = inb(io + 1); | |
1569 | ||
1570 | outb(key, io); | |
1571 | outb(key, io); /* Write Magic Sequence to EFER, extended | |
1572 | funtion enable register */ | |
1573 | outb(0x0d, io); /* Write EFIR, extended function index register */ | |
1574 | oldid = inb(io + 1); /* Read EFDR, extended function data register */ | |
1575 | outb(0x0e, io); | |
1576 | oldrev = inb(io + 1); | |
1577 | outb(0x20, io); | |
1578 | id = inb(io + 1); | |
1579 | outb(0x21, io); | |
1580 | rev = inb(io + 1); | |
1581 | outb(0xaa, io); /* Magic Seal */ | |
1582 | ||
e2434dc1 JR |
1583 | outb(origval, io); /* in case we poked some entirely different hardware */ |
1584 | ||
3aeda9bc AC |
1585 | if (x_id == id && x_oldrev == oldrev && |
1586 | x_oldid == oldid && x_rev == rev) | |
1da177e4 LT |
1587 | goto out; /* protection against false positives */ |
1588 | ||
3aeda9bc | 1589 | decode_smsc(io, key, oldid, oldrev); |
1da177e4 LT |
1590 | out: |
1591 | release_region(io, 3); | |
1592 | } | |
1593 | ||
1594 | ||
3aeda9bc AC |
1595 | static void __devinit detect_and_report_winbond(void) |
1596 | { | |
1da177e4 LT |
1597 | if (verbose_probing) |
1598 | printk(KERN_DEBUG "Winbond Super-IO detection, now testing ports 3F0,370,250,4E,2E ...\n"); | |
3aeda9bc AC |
1599 | winbond_check(0x3f0, 0x87); |
1600 | winbond_check(0x370, 0x87); | |
1601 | winbond_check(0x2e , 0x87); | |
1602 | winbond_check(0x4e , 0x87); | |
1603 | winbond_check(0x3f0, 0x86); | |
1604 | winbond_check2(0x250, 0x88); | |
1605 | winbond_check2(0x250, 0x89); | |
1da177e4 LT |
1606 | } |
1607 | ||
3aeda9bc | 1608 | static void __devinit detect_and_report_smsc(void) |
1da177e4 LT |
1609 | { |
1610 | if (verbose_probing) | |
1611 | printk(KERN_DEBUG "SMSC Super-IO detection, now testing Ports 2F0, 370 ...\n"); | |
3aeda9bc AC |
1612 | smsc_check(0x3f0, 0x55); |
1613 | smsc_check(0x370, 0x55); | |
1614 | smsc_check(0x3f0, 0x44); | |
1615 | smsc_check(0x370, 0x44); | |
1da177e4 | 1616 | } |
f63fd7e2 PC |
1617 | |
1618 | static void __devinit detect_and_report_it87(void) | |
1619 | { | |
1620 | u16 dev; | |
e2434dc1 | 1621 | u8 origval, r; |
f63fd7e2 PC |
1622 | if (verbose_probing) |
1623 | printk(KERN_DEBUG "IT8705 Super-IO detection, now testing port 2E ...\n"); | |
e2434dc1 | 1624 | if (!request_region(0x2e, 2, __func__)) |
f63fd7e2 | 1625 | return; |
e2434dc1 | 1626 | origval = inb(0x2e); /* Save original value */ |
f63fd7e2 PC |
1627 | outb(0x87, 0x2e); |
1628 | outb(0x01, 0x2e); | |
1629 | outb(0x55, 0x2e); | |
1630 | outb(0x55, 0x2e); | |
1631 | outb(0x20, 0x2e); | |
1632 | dev = inb(0x2f) << 8; | |
1633 | outb(0x21, 0x2e); | |
1634 | dev |= inb(0x2f); | |
1635 | if (dev == 0x8712 || dev == 0x8705 || dev == 0x8715 || | |
1636 | dev == 0x8716 || dev == 0x8718 || dev == 0x8726) { | |
1637 | printk(KERN_INFO "IT%04X SuperIO detected.\n", dev); | |
1638 | outb(0x07, 0x2E); /* Parallel Port */ | |
1639 | outb(0x03, 0x2F); | |
1640 | outb(0xF0, 0x2E); /* BOOT 0x80 off */ | |
1641 | r = inb(0x2f); | |
1642 | outb(0xF0, 0x2E); | |
1643 | outb(r | 8, 0x2F); | |
1644 | outb(0x02, 0x2E); /* Lock */ | |
1645 | outb(0x02, 0x2F); | |
e2434dc1 JR |
1646 | } else { |
1647 | outb(origval, 0x2e); /* Oops, sorry to disturb */ | |
f63fd7e2 | 1648 | } |
e2434dc1 | 1649 | release_region(0x2e, 2); |
f63fd7e2 | 1650 | } |
1da177e4 LT |
1651 | #endif /* CONFIG_PARPORT_PC_SUPERIO */ |
1652 | ||
181bf1e8 | 1653 | static struct superio_struct *find_superio(struct parport *p) |
1da177e4 | 1654 | { |
181bf1e8 AC |
1655 | int i; |
1656 | for (i = 0; i < NR_SUPERIOS; i++) | |
1657 | if (superios[i].io != p->base) | |
1658 | return &superios[i]; | |
1659 | return NULL; | |
1660 | } | |
73e0d48b | 1661 | |
181bf1e8 AC |
1662 | static int get_superio_dma(struct parport *p) |
1663 | { | |
1664 | struct superio_struct *s = find_superio(p); | |
1665 | if (s) | |
1666 | return s->dma; | |
1da177e4 LT |
1667 | return PARPORT_DMA_NONE; |
1668 | } | |
1669 | ||
3aeda9bc | 1670 | static int get_superio_irq(struct parport *p) |
1da177e4 | 1671 | { |
181bf1e8 AC |
1672 | struct superio_struct *s = find_superio(p); |
1673 | if (s) | |
1674 | return s->irq; | |
3aeda9bc | 1675 | return PARPORT_IRQ_NONE; |
1da177e4 | 1676 | } |
73e0d48b | 1677 | |
1da177e4 LT |
1678 | |
1679 | /* --- Mode detection ------------------------------------- */ | |
1680 | ||
1681 | /* | |
1682 | * Checks for port existence, all ports support SPP MODE | |
3aeda9bc | 1683 | * Returns: |
1da177e4 | 1684 | * 0 : No parallel port at this address |
3aeda9bc | 1685 | * PARPORT_MODE_PCSPP : SPP port detected |
1da177e4 LT |
1686 | * (if the user specified an ioport himself, |
1687 | * this shall always be the case!) | |
1688 | * | |
1689 | */ | |
96766a3c | 1690 | static int parport_SPP_supported(struct parport *pb) |
1da177e4 LT |
1691 | { |
1692 | unsigned char r, w; | |
1693 | ||
1694 | /* | |
3aeda9bc | 1695 | * first clear an eventually pending EPP timeout |
1da177e4 LT |
1696 | * I (sailer@ife.ee.ethz.ch) have an SMSC chipset |
1697 | * that does not even respond to SPP cycles if an EPP | |
1698 | * timeout is pending | |
1699 | */ | |
1700 | clear_epp_timeout(pb); | |
1701 | ||
1702 | /* Do a simple read-write test to make sure the port exists. */ | |
1703 | w = 0xc; | |
3aeda9bc | 1704 | outb(w, CONTROL(pb)); |
1da177e4 LT |
1705 | |
1706 | /* Is there a control register that we can read from? Some | |
1707 | * ports don't allow reads, so read_control just returns a | |
1708 | * software copy. Some ports _do_ allow reads, so bypass the | |
1709 | * software copy here. In addition, some bits aren't | |
1710 | * writable. */ | |
3aeda9bc | 1711 | r = inb(CONTROL(pb)); |
1da177e4 LT |
1712 | if ((r & 0xf) == w) { |
1713 | w = 0xe; | |
3aeda9bc AC |
1714 | outb(w, CONTROL(pb)); |
1715 | r = inb(CONTROL(pb)); | |
1716 | outb(0xc, CONTROL(pb)); | |
1da177e4 LT |
1717 | if ((r & 0xf) == w) |
1718 | return PARPORT_MODE_PCSPP; | |
1719 | } | |
1720 | ||
1721 | if (user_specified) | |
1722 | /* That didn't work, but the user thinks there's a | |
1723 | * port here. */ | |
3aeda9bc | 1724 | printk(KERN_INFO "parport 0x%lx (WARNING): CTR: " |
1da177e4 LT |
1725 | "wrote 0x%02x, read 0x%02x\n", pb->base, w, r); |
1726 | ||
1727 | /* Try the data register. The data lines aren't tri-stated at | |
1728 | * this stage, so we expect back what we wrote. */ | |
1729 | w = 0xaa; | |
3aeda9bc AC |
1730 | parport_pc_write_data(pb, w); |
1731 | r = parport_pc_read_data(pb); | |
1da177e4 LT |
1732 | if (r == w) { |
1733 | w = 0x55; | |
3aeda9bc AC |
1734 | parport_pc_write_data(pb, w); |
1735 | r = parport_pc_read_data(pb); | |
1da177e4 LT |
1736 | if (r == w) |
1737 | return PARPORT_MODE_PCSPP; | |
1738 | } | |
1739 | ||
1740 | if (user_specified) { | |
1741 | /* Didn't work, but the user is convinced this is the | |
1742 | * place. */ | |
3aeda9bc | 1743 | printk(KERN_INFO "parport 0x%lx (WARNING): DATA: " |
1da177e4 | 1744 | "wrote 0x%02x, read 0x%02x\n", pb->base, w, r); |
3aeda9bc | 1745 | printk(KERN_INFO "parport 0x%lx: You gave this address, " |
1da177e4 LT |
1746 | "but there is probably no parallel port there!\n", |
1747 | pb->base); | |
1748 | } | |
1749 | ||
1750 | /* It's possible that we can't read the control register or | |
1751 | * the data register. In that case just believe the user. */ | |
1752 | if (user_specified) | |
1753 | return PARPORT_MODE_PCSPP; | |
1754 | ||
1755 | return 0; | |
1756 | } | |
1757 | ||
1758 | /* Check for ECR | |
1759 | * | |
1760 | * Old style XT ports alias io ports every 0x400, hence accessing ECR | |
1761 | * on these cards actually accesses the CTR. | |
1762 | * | |
1763 | * Modern cards don't do this but reading from ECR will return 0xff | |
1764 | * regardless of what is written here if the card does NOT support | |
1765 | * ECP. | |
1766 | * | |
1767 | * We first check to see if ECR is the same as CTR. If not, the low | |
1768 | * two bits of ECR aren't writable, so we check by writing ECR and | |
1769 | * reading it back to see if it's what we expect. | |
1770 | */ | |
96766a3c | 1771 | static int parport_ECR_present(struct parport *pb) |
1da177e4 LT |
1772 | { |
1773 | struct parport_pc_private *priv = pb->private_data; | |
1774 | unsigned char r = 0xc; | |
1775 | ||
3aeda9bc AC |
1776 | outb(r, CONTROL(pb)); |
1777 | if ((inb(ECONTROL(pb)) & 0x3) == (r & 0x3)) { | |
1778 | outb(r ^ 0x2, CONTROL(pb)); /* Toggle bit 1 */ | |
1da177e4 | 1779 | |
3aeda9bc AC |
1780 | r = inb(CONTROL(pb)); |
1781 | if ((inb(ECONTROL(pb)) & 0x2) == (r & 0x2)) | |
1da177e4 LT |
1782 | goto no_reg; /* Sure that no ECR register exists */ |
1783 | } | |
3aeda9bc AC |
1784 | |
1785 | if ((inb(ECONTROL(pb)) & 0x3) != 0x1) | |
1da177e4 LT |
1786 | goto no_reg; |
1787 | ||
3aeda9bc AC |
1788 | ECR_WRITE(pb, 0x34); |
1789 | if (inb(ECONTROL(pb)) != 0x35) | |
1da177e4 LT |
1790 | goto no_reg; |
1791 | ||
1792 | priv->ecr = 1; | |
3aeda9bc AC |
1793 | outb(0xc, CONTROL(pb)); |
1794 | ||
1da177e4 | 1795 | /* Go to mode 000 */ |
3aeda9bc | 1796 | frob_set_mode(pb, ECR_SPP); |
1da177e4 LT |
1797 | |
1798 | return 1; | |
1799 | ||
1800 | no_reg: | |
3aeda9bc AC |
1801 | outb(0xc, CONTROL(pb)); |
1802 | return 0; | |
1da177e4 LT |
1803 | } |
1804 | ||
1805 | #ifdef CONFIG_PARPORT_1284 | |
1806 | /* Detect PS/2 support. | |
1807 | * | |
1808 | * Bit 5 (0x20) sets the PS/2 data direction; setting this high | |
1809 | * allows us to read data from the data lines. In theory we would get back | |
1810 | * 0xff but any peripheral attached to the port may drag some or all of the | |
1811 | * lines down to zero. So if we get back anything that isn't the contents | |
3aeda9bc | 1812 | * of the data register we deem PS/2 support to be present. |
1da177e4 LT |
1813 | * |
1814 | * Some SPP ports have "half PS/2" ability - you can't turn off the line | |
1815 | * drivers, but an external peripheral with sufficiently beefy drivers of | |
1816 | * its own can overpower them and assert its own levels onto the bus, from | |
1817 | * where they can then be read back as normal. Ports with this property | |
1818 | * and the right type of device attached are likely to fail the SPP test, | |
1819 | * (as they will appear to have stuck bits) and so the fact that they might | |
3aeda9bc | 1820 | * be misdetected here is rather academic. |
1da177e4 LT |
1821 | */ |
1822 | ||
96766a3c | 1823 | static int parport_PS2_supported(struct parport *pb) |
1da177e4 LT |
1824 | { |
1825 | int ok = 0; | |
3aeda9bc | 1826 | |
1da177e4 LT |
1827 | clear_epp_timeout(pb); |
1828 | ||
1829 | /* try to tri-state the buffer */ | |
3aeda9bc AC |
1830 | parport_pc_data_reverse(pb); |
1831 | ||
1da177e4 | 1832 | parport_pc_write_data(pb, 0x55); |
3aeda9bc AC |
1833 | if (parport_pc_read_data(pb) != 0x55) |
1834 | ok++; | |
1da177e4 LT |
1835 | |
1836 | parport_pc_write_data(pb, 0xaa); | |
3aeda9bc AC |
1837 | if (parport_pc_read_data(pb) != 0xaa) |
1838 | ok++; | |
1da177e4 LT |
1839 | |
1840 | /* cancel input mode */ | |
3aeda9bc | 1841 | parport_pc_data_forward(pb); |
1da177e4 LT |
1842 | |
1843 | if (ok) { | |
1844 | pb->modes |= PARPORT_MODE_TRISTATE; | |
1845 | } else { | |
1846 | struct parport_pc_private *priv = pb->private_data; | |
1847 | priv->ctr_writable &= ~0x20; | |
1848 | } | |
1849 | ||
1850 | return ok; | |
1851 | } | |
1852 | ||
1853 | #ifdef CONFIG_PARPORT_PC_FIFO | |
55265b00 | 1854 | static int parport_ECP_supported(struct parport *pb) |
1da177e4 LT |
1855 | { |
1856 | int i; | |
1857 | int config, configb; | |
1858 | int pword; | |
1859 | struct parport_pc_private *priv = pb->private_data; | |
3aeda9bc AC |
1860 | /* Translate ECP intrLine to ISA irq value */ |
1861 | static const int intrline[] = { 0, 7, 9, 10, 11, 14, 15, 5 }; | |
1da177e4 LT |
1862 | |
1863 | /* If there is no ECR, we have no hope of supporting ECP. */ | |
1864 | if (!priv->ecr) | |
1865 | return 0; | |
1866 | ||
1867 | /* Find out FIFO depth */ | |
3aeda9bc AC |
1868 | ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */ |
1869 | ECR_WRITE(pb, ECR_TST << 5); /* TEST FIFO */ | |
1870 | for (i = 0; i < 1024 && !(inb(ECONTROL(pb)) & 0x02); i++) | |
1871 | outb(0xaa, FIFO(pb)); | |
1da177e4 LT |
1872 | |
1873 | /* | |
1874 | * Using LGS chipset it uses ECR register, but | |
1875 | * it doesn't support ECP or FIFO MODE | |
1876 | */ | |
1877 | if (i == 1024) { | |
3aeda9bc | 1878 | ECR_WRITE(pb, ECR_SPP << 5); |
1da177e4 LT |
1879 | return 0; |
1880 | } | |
1881 | ||
1882 | priv->fifo_depth = i; | |
1883 | if (verbose_probing) | |
3aeda9bc | 1884 | printk(KERN_DEBUG "0x%lx: FIFO is %d bytes\n", pb->base, i); |
1da177e4 LT |
1885 | |
1886 | /* Find out writeIntrThreshold */ | |
3aeda9bc AC |
1887 | frob_econtrol(pb, 1<<2, 1<<2); |
1888 | frob_econtrol(pb, 1<<2, 0); | |
1da177e4 | 1889 | for (i = 1; i <= priv->fifo_depth; i++) { |
3aeda9bc AC |
1890 | inb(FIFO(pb)); |
1891 | udelay(50); | |
1892 | if (inb(ECONTROL(pb)) & (1<<2)) | |
1da177e4 LT |
1893 | break; |
1894 | } | |
1895 | ||
1896 | if (i <= priv->fifo_depth) { | |
1897 | if (verbose_probing) | |
3aeda9bc | 1898 | printk(KERN_DEBUG "0x%lx: writeIntrThreshold is %d\n", |
1da177e4 LT |
1899 | pb->base, i); |
1900 | } else | |
1901 | /* Number of bytes we know we can write if we get an | |
3aeda9bc | 1902 | interrupt. */ |
1da177e4 LT |
1903 | i = 0; |
1904 | ||
1905 | priv->writeIntrThreshold = i; | |
1906 | ||
1907 | /* Find out readIntrThreshold */ | |
3aeda9bc AC |
1908 | frob_set_mode(pb, ECR_PS2); /* Reset FIFO and enable PS2 */ |
1909 | parport_pc_data_reverse(pb); /* Must be in PS2 mode */ | |
1910 | frob_set_mode(pb, ECR_TST); /* Test FIFO */ | |
1911 | frob_econtrol(pb, 1<<2, 1<<2); | |
1912 | frob_econtrol(pb, 1<<2, 0); | |
1da177e4 | 1913 | for (i = 1; i <= priv->fifo_depth; i++) { |
3aeda9bc AC |
1914 | outb(0xaa, FIFO(pb)); |
1915 | if (inb(ECONTROL(pb)) & (1<<2)) | |
1da177e4 LT |
1916 | break; |
1917 | } | |
1918 | ||
1919 | if (i <= priv->fifo_depth) { | |
1920 | if (verbose_probing) | |
3aeda9bc | 1921 | printk(KERN_INFO "0x%lx: readIntrThreshold is %d\n", |
1da177e4 LT |
1922 | pb->base, i); |
1923 | } else | |
1924 | /* Number of bytes we can read if we get an interrupt. */ | |
1925 | i = 0; | |
1926 | ||
1927 | priv->readIntrThreshold = i; | |
1928 | ||
3aeda9bc AC |
1929 | ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */ |
1930 | ECR_WRITE(pb, 0xf4); /* Configuration mode */ | |
1931 | config = inb(CONFIGA(pb)); | |
1da177e4 LT |
1932 | pword = (config >> 4) & 0x7; |
1933 | switch (pword) { | |
1934 | case 0: | |
1935 | pword = 2; | |
3aeda9bc | 1936 | printk(KERN_WARNING "0x%lx: Unsupported pword size!\n", |
1da177e4 LT |
1937 | pb->base); |
1938 | break; | |
1939 | case 2: | |
1940 | pword = 4; | |
3aeda9bc | 1941 | printk(KERN_WARNING "0x%lx: Unsupported pword size!\n", |
1da177e4 LT |
1942 | pb->base); |
1943 | break; | |
1944 | default: | |
3aeda9bc | 1945 | printk(KERN_WARNING "0x%lx: Unknown implementation ID\n", |
1da177e4 LT |
1946 | pb->base); |
1947 | /* Assume 1 */ | |
1948 | case 1: | |
1949 | pword = 1; | |
1950 | } | |
1951 | priv->pword = pword; | |
1952 | ||
1953 | if (verbose_probing) { | |
3aeda9bc AC |
1954 | printk(KERN_DEBUG "0x%lx: PWord is %d bits\n", |
1955 | pb->base, 8 * pword); | |
1956 | ||
1957 | printk(KERN_DEBUG "0x%lx: Interrupts are ISA-%s\n", pb->base, | |
1da177e4 LT |
1958 | config & 0x80 ? "Level" : "Pulses"); |
1959 | ||
3aeda9bc AC |
1960 | configb = inb(CONFIGB(pb)); |
1961 | printk(KERN_DEBUG "0x%lx: ECP port cfgA=0x%02x cfgB=0x%02x\n", | |
1da177e4 | 1962 | pb->base, config, configb); |
3aeda9bc AC |
1963 | printk(KERN_DEBUG "0x%lx: ECP settings irq=", pb->base); |
1964 | if ((configb >> 3) & 0x07) | |
1965 | printk("%d", intrline[(configb >> 3) & 0x07]); | |
1da177e4 LT |
1966 | else |
1967 | printk("<none or set by other means>"); | |
3aeda9bc AC |
1968 | printk(" dma="); |
1969 | if ((configb & 0x03) == 0x00) | |
1da177e4 LT |
1970 | printk("<none or set by other means>\n"); |
1971 | else | |
3aeda9bc | 1972 | printk("%d\n", configb & 0x07); |
1da177e4 LT |
1973 | } |
1974 | ||
1975 | /* Go back to mode 000 */ | |
3aeda9bc | 1976 | frob_set_mode(pb, ECR_SPP); |
1da177e4 LT |
1977 | |
1978 | return 1; | |
1979 | } | |
1980 | #endif | |
1981 | ||
96766a3c | 1982 | static int parport_ECPPS2_supported(struct parport *pb) |
1da177e4 LT |
1983 | { |
1984 | const struct parport_pc_private *priv = pb->private_data; | |
1985 | int result; | |
1986 | unsigned char oecr; | |
1987 | ||
1988 | if (!priv->ecr) | |
1989 | return 0; | |
1990 | ||
3aeda9bc AC |
1991 | oecr = inb(ECONTROL(pb)); |
1992 | ECR_WRITE(pb, ECR_PS2 << 5); | |
1da177e4 | 1993 | result = parport_PS2_supported(pb); |
3aeda9bc | 1994 | ECR_WRITE(pb, oecr); |
1da177e4 LT |
1995 | return result; |
1996 | } | |
1997 | ||
1998 | /* EPP mode detection */ | |
1999 | ||
96766a3c | 2000 | static int parport_EPP_supported(struct parport *pb) |
1da177e4 LT |
2001 | { |
2002 | const struct parport_pc_private *priv = pb->private_data; | |
2003 | ||
2004 | /* | |
2005 | * Theory: | |
2006 | * Bit 0 of STR is the EPP timeout bit, this bit is 0 | |
2007 | * when EPP is possible and is set high when an EPP timeout | |
2008 | * occurs (EPP uses the HALT line to stop the CPU while it does | |
2009 | * the byte transfer, an EPP timeout occurs if the attached | |
2010 | * device fails to respond after 10 micro seconds). | |
2011 | * | |
2012 | * This bit is cleared by either reading it (National Semi) | |
2013 | * or writing a 1 to the bit (SMC, UMC, WinBond), others ??? | |
2014 | * This bit is always high in non EPP modes. | |
2015 | */ | |
2016 | ||
2017 | /* If EPP timeout bit clear then EPP available */ | |
3aeda9bc | 2018 | if (!clear_epp_timeout(pb)) |
1da177e4 | 2019 | return 0; /* No way to clear timeout */ |
1da177e4 LT |
2020 | |
2021 | /* Check for Intel bug. */ | |
2022 | if (priv->ecr) { | |
2023 | unsigned char i; | |
2024 | for (i = 0x00; i < 0x80; i += 0x20) { | |
3aeda9bc AC |
2025 | ECR_WRITE(pb, i); |
2026 | if (clear_epp_timeout(pb)) { | |
1da177e4 LT |
2027 | /* Phony EPP in ECP. */ |
2028 | return 0; | |
2029 | } | |
2030 | } | |
2031 | } | |
2032 | ||
2033 | pb->modes |= PARPORT_MODE_EPP; | |
2034 | ||
2035 | /* Set up access functions to use EPP hardware. */ | |
2036 | pb->ops->epp_read_data = parport_pc_epp_read_data; | |
2037 | pb->ops->epp_write_data = parport_pc_epp_write_data; | |
2038 | pb->ops->epp_read_addr = parport_pc_epp_read_addr; | |
2039 | pb->ops->epp_write_addr = parport_pc_epp_write_addr; | |
2040 | ||
2041 | return 1; | |
2042 | } | |
2043 | ||
96766a3c | 2044 | static int parport_ECPEPP_supported(struct parport *pb) |
1da177e4 LT |
2045 | { |
2046 | struct parport_pc_private *priv = pb->private_data; | |
2047 | int result; | |
2048 | unsigned char oecr; | |
2049 | ||
3aeda9bc | 2050 | if (!priv->ecr) |
1da177e4 | 2051 | return 0; |
1da177e4 | 2052 | |
3aeda9bc | 2053 | oecr = inb(ECONTROL(pb)); |
1da177e4 | 2054 | /* Search for SMC style EPP+ECP mode */ |
3aeda9bc AC |
2055 | ECR_WRITE(pb, 0x80); |
2056 | outb(0x04, CONTROL(pb)); | |
1da177e4 LT |
2057 | result = parport_EPP_supported(pb); |
2058 | ||
3aeda9bc | 2059 | ECR_WRITE(pb, oecr); |
1da177e4 LT |
2060 | |
2061 | if (result) { | |
2062 | /* Set up access functions to use ECP+EPP hardware. */ | |
2063 | pb->ops->epp_read_data = parport_pc_ecpepp_read_data; | |
2064 | pb->ops->epp_write_data = parport_pc_ecpepp_write_data; | |
2065 | pb->ops->epp_read_addr = parport_pc_ecpepp_read_addr; | |
2066 | pb->ops->epp_write_addr = parport_pc_ecpepp_write_addr; | |
2067 | } | |
2068 | ||
2069 | return result; | |
2070 | } | |
2071 | ||
2072 | #else /* No IEEE 1284 support */ | |
2073 | ||
2074 | /* Don't bother probing for modes we know we won't use. */ | |
2075 | static int __devinit parport_PS2_supported(struct parport *pb) { return 0; } | |
2076 | #ifdef CONFIG_PARPORT_PC_FIFO | |
3aeda9bc AC |
2077 | static int parport_ECP_supported(struct parport *pb) |
2078 | { | |
2079 | return 0; | |
2080 | } | |
1da177e4 | 2081 | #endif |
3aeda9bc AC |
2082 | static int __devinit parport_EPP_supported(struct parport *pb) |
2083 | { | |
2084 | return 0; | |
2085 | } | |
2086 | ||
2087 | static int __devinit parport_ECPEPP_supported(struct parport *pb) | |
2088 | { | |
2089 | return 0; | |
2090 | } | |
2091 | ||
2092 | static int __devinit parport_ECPPS2_supported(struct parport *pb) | |
2093 | { | |
2094 | return 0; | |
2095 | } | |
1da177e4 LT |
2096 | |
2097 | #endif /* No IEEE 1284 support */ | |
2098 | ||
2099 | /* --- IRQ detection -------------------------------------- */ | |
2100 | ||
2101 | /* Only if supports ECP mode */ | |
4438982f | 2102 | static int programmable_irq_support(struct parport *pb) |
1da177e4 LT |
2103 | { |
2104 | int irq, intrLine; | |
3aeda9bc | 2105 | unsigned char oecr = inb(ECONTROL(pb)); |
1da177e4 LT |
2106 | static const int lookup[8] = { |
2107 | PARPORT_IRQ_NONE, 7, 9, 10, 11, 14, 15, 5 | |
2108 | }; | |
2109 | ||
3aeda9bc | 2110 | ECR_WRITE(pb, ECR_CNF << 5); /* Configuration MODE */ |
1da177e4 | 2111 | |
3aeda9bc | 2112 | intrLine = (inb(CONFIGB(pb)) >> 3) & 0x07; |
1da177e4 LT |
2113 | irq = lookup[intrLine]; |
2114 | ||
3aeda9bc | 2115 | ECR_WRITE(pb, oecr); |
1da177e4 LT |
2116 | return irq; |
2117 | } | |
2118 | ||
4438982f | 2119 | static int irq_probe_ECP(struct parport *pb) |
1da177e4 LT |
2120 | { |
2121 | int i; | |
2122 | unsigned long irqs; | |
2123 | ||
2124 | irqs = probe_irq_on(); | |
3aeda9bc AC |
2125 | |
2126 | ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */ | |
2127 | ECR_WRITE(pb, (ECR_TST << 5) | 0x04); | |
2128 | ECR_WRITE(pb, ECR_TST << 5); | |
1da177e4 LT |
2129 | |
2130 | /* If Full FIFO sure that writeIntrThreshold is generated */ | |
3aeda9bc AC |
2131 | for (i = 0; i < 1024 && !(inb(ECONTROL(pb)) & 0x02) ; i++) |
2132 | outb(0xaa, FIFO(pb)); | |
2133 | ||
1da177e4 | 2134 | pb->irq = probe_irq_off(irqs); |
3aeda9bc | 2135 | ECR_WRITE(pb, ECR_SPP << 5); |
1da177e4 LT |
2136 | |
2137 | if (pb->irq <= 0) | |
2138 | pb->irq = PARPORT_IRQ_NONE; | |
2139 | ||
2140 | return pb->irq; | |
2141 | } | |
2142 | ||
2143 | /* | |
2144 | * This detection seems that only works in National Semiconductors | |
3aeda9bc | 2145 | * This doesn't work in SMC, LGS, and Winbond |
1da177e4 | 2146 | */ |
4438982f | 2147 | static int irq_probe_EPP(struct parport *pb) |
1da177e4 LT |
2148 | { |
2149 | #ifndef ADVANCED_DETECT | |
2150 | return PARPORT_IRQ_NONE; | |
2151 | #else | |
2152 | int irqs; | |
2153 | unsigned char oecr; | |
2154 | ||
2155 | if (pb->modes & PARPORT_MODE_PCECR) | |
3aeda9bc | 2156 | oecr = inb(ECONTROL(pb)); |
1da177e4 LT |
2157 | |
2158 | irqs = probe_irq_on(); | |
2159 | ||
2160 | if (pb->modes & PARPORT_MODE_PCECR) | |
3aeda9bc AC |
2161 | frob_econtrol(pb, 0x10, 0x10); |
2162 | ||
1da177e4 | 2163 | clear_epp_timeout(pb); |
3aeda9bc AC |
2164 | parport_pc_frob_control(pb, 0x20, 0x20); |
2165 | parport_pc_frob_control(pb, 0x10, 0x10); | |
1da177e4 LT |
2166 | clear_epp_timeout(pb); |
2167 | ||
2168 | /* Device isn't expecting an EPP read | |
2169 | * and generates an IRQ. | |
2170 | */ | |
2171 | parport_pc_read_epp(pb); | |
2172 | udelay(20); | |
2173 | ||
3aeda9bc | 2174 | pb->irq = probe_irq_off(irqs); |
1da177e4 | 2175 | if (pb->modes & PARPORT_MODE_PCECR) |
3aeda9bc | 2176 | ECR_WRITE(pb, oecr); |
1da177e4 LT |
2177 | parport_pc_write_control(pb, 0xc); |
2178 | ||
2179 | if (pb->irq <= 0) | |
2180 | pb->irq = PARPORT_IRQ_NONE; | |
2181 | ||
2182 | return pb->irq; | |
2183 | #endif /* Advanced detection */ | |
2184 | } | |
2185 | ||
4438982f | 2186 | static int irq_probe_SPP(struct parport *pb) |
1da177e4 LT |
2187 | { |
2188 | /* Don't even try to do this. */ | |
2189 | return PARPORT_IRQ_NONE; | |
2190 | } | |
2191 | ||
2192 | /* We will attempt to share interrupt requests since other devices | |
2193 | * such as sound cards and network cards seem to like using the | |
2194 | * printer IRQs. | |
2195 | * | |
2196 | * When ECP is available we can autoprobe for IRQs. | |
2197 | * NOTE: If we can autoprobe it, we can register the IRQ. | |
2198 | */ | |
96766a3c | 2199 | static int parport_irq_probe(struct parport *pb) |
1da177e4 LT |
2200 | { |
2201 | struct parport_pc_private *priv = pb->private_data; | |
2202 | ||
2203 | if (priv->ecr) { | |
2204 | pb->irq = programmable_irq_support(pb); | |
2205 | ||
2206 | if (pb->irq == PARPORT_IRQ_NONE) | |
2207 | pb->irq = irq_probe_ECP(pb); | |
2208 | } | |
2209 | ||
2210 | if ((pb->irq == PARPORT_IRQ_NONE) && priv->ecr && | |
2211 | (pb->modes & PARPORT_MODE_EPP)) | |
2212 | pb->irq = irq_probe_EPP(pb); | |
2213 | ||
2214 | clear_epp_timeout(pb); | |
2215 | ||
2216 | if (pb->irq == PARPORT_IRQ_NONE && (pb->modes & PARPORT_MODE_EPP)) | |
2217 | pb->irq = irq_probe_EPP(pb); | |
2218 | ||
2219 | clear_epp_timeout(pb); | |
2220 | ||
2221 | if (pb->irq == PARPORT_IRQ_NONE) | |
2222 | pb->irq = irq_probe_SPP(pb); | |
2223 | ||
2224 | if (pb->irq == PARPORT_IRQ_NONE) | |
2225 | pb->irq = get_superio_irq(pb); | |
2226 | ||
2227 | return pb->irq; | |
2228 | } | |
2229 | ||
2230 | /* --- DMA detection -------------------------------------- */ | |
2231 | ||
2232 | /* Only if chipset conforms to ECP ISA Interface Standard */ | |
3aeda9bc | 2233 | static int programmable_dma_support(struct parport *p) |
1da177e4 | 2234 | { |
3aeda9bc | 2235 | unsigned char oecr = inb(ECONTROL(p)); |
1da177e4 LT |
2236 | int dma; |
2237 | ||
3aeda9bc AC |
2238 | frob_set_mode(p, ECR_CNF); |
2239 | ||
2240 | dma = inb(CONFIGB(p)) & 0x07; | |
1da177e4 LT |
2241 | /* 000: Indicates jumpered 8-bit DMA if read-only. |
2242 | 100: Indicates jumpered 16-bit DMA if read-only. */ | |
2243 | if ((dma & 0x03) == 0) | |
2244 | dma = PARPORT_DMA_NONE; | |
2245 | ||
3aeda9bc | 2246 | ECR_WRITE(p, oecr); |
1da177e4 LT |
2247 | return dma; |
2248 | } | |
2249 | ||
3aeda9bc | 2250 | static int parport_dma_probe(struct parport *p) |
1da177e4 LT |
2251 | { |
2252 | const struct parport_pc_private *priv = p->private_data; | |
3aeda9bc AC |
2253 | if (priv->ecr) /* ask ECP chipset first */ |
2254 | p->dma = programmable_dma_support(p); | |
1da177e4 LT |
2255 | if (p->dma == PARPORT_DMA_NONE) { |
2256 | /* ask known Super-IO chips proper, although these | |
2257 | claim ECP compatible, some don't report their DMA | |
2258 | conforming to ECP standards */ | |
2259 | p->dma = get_superio_dma(p); | |
2260 | } | |
2261 | ||
2262 | return p->dma; | |
2263 | } | |
2264 | ||
2265 | /* --- Initialisation code -------------------------------- */ | |
2266 | ||
2267 | static LIST_HEAD(ports_list); | |
2268 | static DEFINE_SPINLOCK(ports_lock); | |
2269 | ||
51dcdfec AC |
2270 | struct parport *parport_pc_probe_port(unsigned long int base, |
2271 | unsigned long int base_hi, | |
2272 | int irq, int dma, | |
2273 | struct device *dev, | |
2274 | int irqflags) | |
1da177e4 LT |
2275 | { |
2276 | struct parport_pc_private *priv; | |
2277 | struct parport_operations *ops; | |
2278 | struct parport *p; | |
2279 | int probedirq = PARPORT_IRQ_NONE; | |
2280 | struct resource *base_res; | |
2281 | struct resource *ECR_res = NULL; | |
2282 | struct resource *EPP_res = NULL; | |
a7d801af JD |
2283 | struct platform_device *pdev = NULL; |
2284 | ||
2285 | if (!dev) { | |
2286 | /* We need a physical device to attach to, but none was | |
2287 | * provided. Create our own. */ | |
2288 | pdev = platform_device_register_simple("parport_pc", | |
2289 | base, NULL, 0); | |
2290 | if (IS_ERR(pdev)) | |
2291 | return NULL; | |
2292 | dev = &pdev->dev; | |
dfa7c4d8 FT |
2293 | |
2294 | dev->coherent_dma_mask = DMA_BIT_MASK(24); | |
2295 | dev->dma_mask = &dev->coherent_dma_mask; | |
a7d801af | 2296 | } |
1da177e4 | 2297 | |
51dcdfec | 2298 | ops = kmalloc(sizeof(struct parport_operations), GFP_KERNEL); |
1da177e4 LT |
2299 | if (!ops) |
2300 | goto out1; | |
2301 | ||
51dcdfec | 2302 | priv = kmalloc(sizeof(struct parport_pc_private), GFP_KERNEL); |
1da177e4 LT |
2303 | if (!priv) |
2304 | goto out2; | |
2305 | ||
2306 | /* a misnomer, actually - it's allocate and reserve parport number */ | |
2307 | p = parport_register_port(base, irq, dma, ops); | |
2308 | if (!p) | |
2309 | goto out3; | |
2310 | ||
2311 | base_res = request_region(base, 3, p->name); | |
2312 | if (!base_res) | |
2313 | goto out4; | |
2314 | ||
3aeda9bc | 2315 | memcpy(ops, &parport_pc_ops, sizeof(struct parport_operations)); |
1da177e4 LT |
2316 | priv->ctr = 0xc; |
2317 | priv->ctr_writable = ~0x10; | |
2318 | priv->ecr = 0; | |
2319 | priv->fifo_depth = 0; | |
2320 | priv->dma_buf = NULL; | |
2321 | priv->dma_handle = 0; | |
1da177e4 LT |
2322 | INIT_LIST_HEAD(&priv->list); |
2323 | priv->port = p; | |
c15a3837 DB |
2324 | |
2325 | p->dev = dev; | |
1da177e4 LT |
2326 | p->base_hi = base_hi; |
2327 | p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT; | |
2328 | p->private_data = priv; | |
2329 | ||
2330 | if (base_hi) { | |
2331 | ECR_res = request_region(base_hi, 3, p->name); | |
2332 | if (ECR_res) | |
2333 | parport_ECR_present(p); | |
2334 | } | |
2335 | ||
2336 | if (base != 0x3bc) { | |
2337 | EPP_res = request_region(base+0x3, 5, p->name); | |
2338 | if (EPP_res) | |
2339 | if (!parport_EPP_supported(p)) | |
2340 | parport_ECPEPP_supported(p); | |
2341 | } | |
3aeda9bc | 2342 | if (!parport_SPP_supported(p)) |
1da177e4 LT |
2343 | /* No port. */ |
2344 | goto out5; | |
2345 | if (priv->ecr) | |
2346 | parport_ECPPS2_supported(p); | |
2347 | else | |
2348 | parport_PS2_supported(p); | |
2349 | ||
3aeda9bc | 2350 | p->size = (p->modes & PARPORT_MODE_EPP) ? 8 : 3; |
1da177e4 LT |
2351 | |
2352 | printk(KERN_INFO "%s: PC-style at 0x%lx", p->name, p->base); | |
2353 | if (p->base_hi && priv->ecr) | |
2354 | printk(" (0x%lx)", p->base_hi); | |
2355 | if (p->irq == PARPORT_IRQ_AUTO) { | |
2356 | p->irq = PARPORT_IRQ_NONE; | |
2357 | parport_irq_probe(p); | |
2358 | } else if (p->irq == PARPORT_IRQ_PROBEONLY) { | |
2359 | p->irq = PARPORT_IRQ_NONE; | |
2360 | parport_irq_probe(p); | |
2361 | probedirq = p->irq; | |
2362 | p->irq = PARPORT_IRQ_NONE; | |
2363 | } | |
2364 | if (p->irq != PARPORT_IRQ_NONE) { | |
2365 | printk(", irq %d", p->irq); | |
2366 | priv->ctr_writable |= 0x10; | |
2367 | ||
2368 | if (p->dma == PARPORT_DMA_AUTO) { | |
2369 | p->dma = PARPORT_DMA_NONE; | |
2370 | parport_dma_probe(p); | |
2371 | } | |
2372 | } | |
2373 | if (p->dma == PARPORT_DMA_AUTO) /* To use DMA, giving the irq | |
3aeda9bc | 2374 | is mandatory (see above) */ |
1da177e4 LT |
2375 | p->dma = PARPORT_DMA_NONE; |
2376 | ||
2377 | #ifdef CONFIG_PARPORT_PC_FIFO | |
2378 | if (parport_ECP_supported(p) && | |
2379 | p->dma != PARPORT_DMA_NOFIFO && | |
2380 | priv->fifo_depth > 0 && p->irq != PARPORT_IRQ_NONE) { | |
2381 | p->modes |= PARPORT_MODE_ECP | PARPORT_MODE_COMPAT; | |
2382 | p->ops->compat_write_data = parport_pc_compat_write_block_pio; | |
2383 | #ifdef CONFIG_PARPORT_1284 | |
2384 | p->ops->ecp_write_data = parport_pc_ecp_write_block_pio; | |
2385 | /* currently broken, but working on it.. (FB) */ | |
2386 | /* p->ops->ecp_read_data = parport_pc_ecp_read_block_pio; */ | |
2387 | #endif /* IEEE 1284 support */ | |
2388 | if (p->dma != PARPORT_DMA_NONE) { | |
2389 | printk(", dma %d", p->dma); | |
2390 | p->modes |= PARPORT_MODE_DMA; | |
3aeda9bc AC |
2391 | } else |
2392 | printk(", using FIFO"); | |
2393 | } else | |
1da177e4 LT |
2394 | /* We can't use the DMA channel after all. */ |
2395 | p->dma = PARPORT_DMA_NONE; | |
2396 | #endif /* Allowed to use FIFO/DMA */ | |
2397 | ||
2398 | printk(" ["); | |
3aeda9bc AC |
2399 | |
2400 | #define printmode(x) \ | |
2401 | {\ | |
2402 | if (p->modes & PARPORT_MODE_##x) {\ | |
2403 | printk("%s%s", f ? "," : "", #x);\ | |
2404 | f++;\ | |
2405 | } \ | |
2406 | } | |
2407 | ||
1da177e4 LT |
2408 | { |
2409 | int f = 0; | |
2410 | printmode(PCSPP); | |
2411 | printmode(TRISTATE); | |
2412 | printmode(COMPAT) | |
2413 | printmode(EPP); | |
2414 | printmode(ECP); | |
2415 | printmode(DMA); | |
2416 | } | |
2417 | #undef printmode | |
2418 | #ifndef CONFIG_PARPORT_1284 | |
3aeda9bc | 2419 | printk("(,...)"); |
1da177e4 LT |
2420 | #endif /* CONFIG_PARPORT_1284 */ |
2421 | printk("]\n"); | |
3aeda9bc | 2422 | if (probedirq != PARPORT_IRQ_NONE) |
1da177e4 LT |
2423 | printk(KERN_INFO "%s: irq %d detected\n", p->name, probedirq); |
2424 | ||
2425 | /* If No ECP release the ports grabbed above. */ | |
2426 | if (ECR_res && (p->modes & PARPORT_MODE_ECP) == 0) { | |
2427 | release_region(base_hi, 3); | |
2428 | ECR_res = NULL; | |
2429 | } | |
2430 | /* Likewise for EEP ports */ | |
2431 | if (EPP_res && (p->modes & PARPORT_MODE_EPP) == 0) { | |
2432 | release_region(base+3, 5); | |
2433 | EPP_res = NULL; | |
2434 | } | |
2435 | if (p->irq != PARPORT_IRQ_NONE) { | |
51dcdfec AC |
2436 | if (request_irq(p->irq, parport_irq_handler, |
2437 | irqflags, p->name, p)) { | |
3aeda9bc | 2438 | printk(KERN_WARNING "%s: irq %d in use, " |
1da177e4 LT |
2439 | "resorting to polled operation\n", |
2440 | p->name, p->irq); | |
2441 | p->irq = PARPORT_IRQ_NONE; | |
2442 | p->dma = PARPORT_DMA_NONE; | |
2443 | } | |
2444 | ||
2445 | #ifdef CONFIG_PARPORT_PC_FIFO | |
7fbacd52 | 2446 | #ifdef HAS_DMA |
1da177e4 | 2447 | if (p->dma != PARPORT_DMA_NONE) { |
3aeda9bc AC |
2448 | if (request_dma(p->dma, p->name)) { |
2449 | printk(KERN_WARNING "%s: dma %d in use, " | |
1da177e4 LT |
2450 | "resorting to PIO operation\n", |
2451 | p->name, p->dma); | |
2452 | p->dma = PARPORT_DMA_NONE; | |
2453 | } else { | |
2454 | priv->dma_buf = | |
c15a3837 | 2455 | dma_alloc_coherent(dev, |
1da177e4 | 2456 | PAGE_SIZE, |
c15a3837 DB |
2457 | &priv->dma_handle, |
2458 | GFP_KERNEL); | |
3aeda9bc AC |
2459 | if (!priv->dma_buf) { |
2460 | printk(KERN_WARNING "%s: " | |
1da177e4 LT |
2461 | "cannot get buffer for DMA, " |
2462 | "resorting to PIO operation\n", | |
2463 | p->name); | |
2464 | free_dma(p->dma); | |
2465 | p->dma = PARPORT_DMA_NONE; | |
2466 | } | |
2467 | } | |
2468 | } | |
7fbacd52 AV |
2469 | #endif |
2470 | #endif | |
1da177e4 LT |
2471 | } |
2472 | ||
2473 | /* Done probing. Now put the port into a sensible start-up state. */ | |
2474 | if (priv->ecr) | |
2475 | /* | |
2476 | * Put the ECP detected port in PS2 mode. | |
2477 | * Do this also for ports that have ECR but don't do ECP. | |
2478 | */ | |
3aeda9bc | 2479 | ECR_WRITE(p, 0x34); |
1da177e4 LT |
2480 | |
2481 | parport_pc_write_data(p, 0); | |
3aeda9bc | 2482 | parport_pc_data_forward(p); |
1da177e4 LT |
2483 | |
2484 | /* Now that we've told the sharing engine about the port, and | |
2485 | found out its characteristics, let the high-level drivers | |
2486 | know about it. */ | |
2487 | spin_lock(&ports_lock); | |
2488 | list_add(&priv->list, &ports_list); | |
2489 | spin_unlock(&ports_lock); | |
3aeda9bc | 2490 | parport_announce_port(p); |
1da177e4 LT |
2491 | |
2492 | return p; | |
2493 | ||
2494 | out5: | |
2495 | if (ECR_res) | |
2496 | release_region(base_hi, 3); | |
2497 | if (EPP_res) | |
2498 | release_region(base+0x3, 5); | |
2499 | release_region(base, 3); | |
2500 | out4: | |
2501 | parport_put_port(p); | |
2502 | out3: | |
3aeda9bc | 2503 | kfree(priv); |
1da177e4 | 2504 | out2: |
3aeda9bc | 2505 | kfree(ops); |
1da177e4 | 2506 | out1: |
a7d801af JD |
2507 | if (pdev) |
2508 | platform_device_unregister(pdev); | |
1da177e4 LT |
2509 | return NULL; |
2510 | } | |
3aeda9bc | 2511 | EXPORT_SYMBOL(parport_pc_probe_port); |
1da177e4 | 2512 | |
3aeda9bc | 2513 | void parport_pc_unregister_port(struct parport *p) |
1da177e4 LT |
2514 | { |
2515 | struct parport_pc_private *priv = p->private_data; | |
2516 | struct parport_operations *ops = p->ops; | |
2517 | ||
2518 | parport_remove_port(p); | |
2519 | spin_lock(&ports_lock); | |
2520 | list_del_init(&priv->list); | |
2521 | spin_unlock(&ports_lock); | |
d1c4ac40 | 2522 | #if defined(CONFIG_PARPORT_PC_FIFO) && defined(HAS_DMA) |
1da177e4 LT |
2523 | if (p->dma != PARPORT_DMA_NONE) |
2524 | free_dma(p->dma); | |
d1c4ac40 | 2525 | #endif |
1da177e4 LT |
2526 | if (p->irq != PARPORT_IRQ_NONE) |
2527 | free_irq(p->irq, p); | |
2528 | release_region(p->base, 3); | |
2529 | if (p->size > 3) | |
2530 | release_region(p->base + 3, p->size - 3); | |
2531 | if (p->modes & PARPORT_MODE_ECP) | |
2532 | release_region(p->base_hi, 3); | |
d1c4ac40 | 2533 | #if defined(CONFIG_PARPORT_PC_FIFO) && defined(HAS_DMA) |
1da177e4 | 2534 | if (priv->dma_buf) |
c15a3837 | 2535 | dma_free_coherent(p->physport->dev, PAGE_SIZE, |
1da177e4 LT |
2536 | priv->dma_buf, |
2537 | priv->dma_handle); | |
7fbacd52 | 2538 | #endif |
3aeda9bc | 2539 | kfree(p->private_data); |
1da177e4 | 2540 | parport_put_port(p); |
3aeda9bc | 2541 | kfree(ops); /* hope no-one cached it */ |
1da177e4 | 2542 | } |
3aeda9bc | 2543 | EXPORT_SYMBOL(parport_pc_unregister_port); |
1da177e4 LT |
2544 | |
2545 | #ifdef CONFIG_PCI | |
2546 | ||
2547 | /* ITE support maintained by Rich Liu <richliu@poorman.org> */ | |
3aeda9bc | 2548 | static int __devinit sio_ite_8872_probe(struct pci_dev *pdev, int autoirq, |
a6767b7c MK |
2549 | int autodma, |
2550 | const struct parport_pc_via_data *via) | |
1da177e4 LT |
2551 | { |
2552 | short inta_addr[6] = { 0x2A0, 0x2C0, 0x220, 0x240, 0x1E0 }; | |
2553 | struct resource *base_res; | |
2554 | u32 ite8872set; | |
2555 | u32 ite8872_lpt, ite8872_lpthi; | |
2556 | u8 ite8872_irq, type; | |
1da177e4 LT |
2557 | int irq; |
2558 | int i; | |
2559 | ||
3aeda9bc AC |
2560 | DPRINTK(KERN_DEBUG "sio_ite_8872_probe()\n"); |
2561 | ||
2562 | /* make sure which one chip */ | |
2563 | for (i = 0; i < 5; i++) { | |
e7c310c3 | 2564 | base_res = request_region(inta_addr[i], 32, "it887x"); |
1da177e4 LT |
2565 | if (base_res) { |
2566 | int test; | |
3aeda9bc | 2567 | pci_write_config_dword(pdev, 0x60, |
e7c310c3 | 2568 | 0xe5000000 | inta_addr[i]); |
3aeda9bc | 2569 | pci_write_config_dword(pdev, 0x78, |
1da177e4 | 2570 | 0x00000000 | inta_addr[i]); |
3aeda9bc AC |
2571 | test = inb(inta_addr[i]); |
2572 | if (test != 0xff) | |
2573 | break; | |
1da177e4 LT |
2574 | release_region(inta_addr[i], 0x8); |
2575 | } | |
2576 | } | |
3aeda9bc AC |
2577 | if (i >= 5) { |
2578 | printk(KERN_INFO "parport_pc: cannot find ITE8872 INTA\n"); | |
1da177e4 LT |
2579 | return 0; |
2580 | } | |
2581 | ||
3aeda9bc | 2582 | type = inb(inta_addr[i] + 0x18); |
1da177e4 LT |
2583 | type &= 0x0f; |
2584 | ||
2585 | switch (type) { | |
2586 | case 0x2: | |
3aeda9bc | 2587 | printk(KERN_INFO "parport_pc: ITE8871 found (1P)\n"); |
1da177e4 LT |
2588 | ite8872set = 0x64200000; |
2589 | break; | |
2590 | case 0xa: | |
3aeda9bc | 2591 | printk(KERN_INFO "parport_pc: ITE8875 found (1P)\n"); |
1da177e4 LT |
2592 | ite8872set = 0x64200000; |
2593 | break; | |
2594 | case 0xe: | |
3aeda9bc | 2595 | printk(KERN_INFO "parport_pc: ITE8872 found (2S1P)\n"); |
1da177e4 LT |
2596 | ite8872set = 0x64e00000; |
2597 | break; | |
2598 | case 0x6: | |
3aeda9bc | 2599 | printk(KERN_INFO "parport_pc: ITE8873 found (1S)\n"); |
1da177e4 LT |
2600 | return 0; |
2601 | case 0x8: | |
3aeda9bc | 2602 | DPRINTK(KERN_DEBUG "parport_pc: ITE8874 found (2S)\n"); |
1da177e4 LT |
2603 | return 0; |
2604 | default: | |
3aeda9bc AC |
2605 | printk(KERN_INFO "parport_pc: unknown ITE887x\n"); |
2606 | printk(KERN_INFO "parport_pc: please mail 'lspci -nvv' " | |
1da177e4 LT |
2607 | "output to Rich.Liu@ite.com.tw\n"); |
2608 | return 0; | |
2609 | } | |
2610 | ||
3aeda9bc AC |
2611 | pci_read_config_byte(pdev, 0x3c, &ite8872_irq); |
2612 | pci_read_config_dword(pdev, 0x1c, &ite8872_lpt); | |
1da177e4 | 2613 | ite8872_lpt &= 0x0000ff00; |
3aeda9bc | 2614 | pci_read_config_dword(pdev, 0x20, &ite8872_lpthi); |
1da177e4 | 2615 | ite8872_lpthi &= 0x0000ff00; |
3aeda9bc AC |
2616 | pci_write_config_dword(pdev, 0x6c, 0xe3000000 | ite8872_lpt); |
2617 | pci_write_config_dword(pdev, 0x70, 0xe3000000 | ite8872_lpthi); | |
2618 | pci_write_config_dword(pdev, 0x80, (ite8872_lpthi<<16) | ite8872_lpt); | |
2619 | /* SET SPP&EPP , Parallel Port NO DMA , Enable All Function */ | |
2620 | /* SET Parallel IRQ */ | |
2621 | pci_write_config_dword(pdev, 0x9c, | |
1da177e4 LT |
2622 | ite8872set | (ite8872_irq * 0x11111)); |
2623 | ||
3aeda9bc AC |
2624 | DPRINTK(KERN_DEBUG "ITE887x: The IRQ is %d.\n", ite8872_irq); |
2625 | DPRINTK(KERN_DEBUG "ITE887x: The PARALLEL I/O port is 0x%x.\n", | |
1da177e4 | 2626 | ite8872_lpt); |
3aeda9bc | 2627 | DPRINTK(KERN_DEBUG "ITE887x: The PARALLEL I/O porthi is 0x%x.\n", |
1da177e4 LT |
2628 | ite8872_lpthi); |
2629 | ||
2630 | /* Let the user (or defaults) steer us away from interrupts */ | |
2631 | irq = ite8872_irq; | |
2632 | if (autoirq != PARPORT_IRQ_AUTO) | |
2633 | irq = PARPORT_IRQ_NONE; | |
2634 | ||
2635 | /* | |
2636 | * Release the resource so that parport_pc_probe_port can get it. | |
2637 | */ | |
2638 | release_resource(base_res); | |
3aeda9bc | 2639 | if (parport_pc_probe_port(ite8872_lpt, ite8872_lpthi, |
51dcdfec | 2640 | irq, PARPORT_DMA_NONE, &pdev->dev, 0)) { |
3aeda9bc | 2641 | printk(KERN_INFO |
1da177e4 | 2642 | "parport_pc: ITE 8872 parallel port: io=0x%X", |
3aeda9bc | 2643 | ite8872_lpt); |
1da177e4 | 2644 | if (irq != PARPORT_IRQ_NONE) |
3aeda9bc AC |
2645 | printk(", irq=%d", irq); |
2646 | printk("\n"); | |
1da177e4 LT |
2647 | return 1; |
2648 | } | |
2649 | ||
2650 | return 0; | |
2651 | } | |
2652 | ||
2653 | /* VIA 8231 support by Pavel Fedin <sonic_amiga@rambler.ru> | |
2654 | based on VIA 686a support code by Jeff Garzik <jgarzik@pobox.com> */ | |
3aeda9bc | 2655 | static int __devinitdata parport_init_mode; |
1da177e4 LT |
2656 | |
2657 | /* Data for two known VIA chips */ | |
2658 | static struct parport_pc_via_data via_686a_data __devinitdata = { | |
2659 | 0x51, | |
2660 | 0x50, | |
2661 | 0x85, | |
2662 | 0x02, | |
2663 | 0xE2, | |
2664 | 0xF0, | |
2665 | 0xE6 | |
2666 | }; | |
2667 | static struct parport_pc_via_data via_8231_data __devinitdata = { | |
2668 | 0x45, | |
2669 | 0x44, | |
2670 | 0x50, | |
2671 | 0x04, | |
2672 | 0xF2, | |
2673 | 0xFA, | |
2674 | 0xF6 | |
2675 | }; | |
2676 | ||
3aeda9bc | 2677 | static int __devinit sio_via_probe(struct pci_dev *pdev, int autoirq, |
a6767b7c MK |
2678 | int autodma, |
2679 | const struct parport_pc_via_data *via) | |
1da177e4 LT |
2680 | { |
2681 | u8 tmp, tmp2, siofunc; | |
2682 | u8 ppcontrol = 0; | |
2683 | int dma, irq; | |
2684 | unsigned port1, port2; | |
2685 | unsigned have_epp = 0; | |
2686 | ||
2687 | printk(KERN_DEBUG "parport_pc: VIA 686A/8231 detected\n"); | |
2688 | ||
3aeda9bc | 2689 | switch (parport_init_mode) { |
1da177e4 | 2690 | case 1: |
3aeda9bc AC |
2691 | printk(KERN_DEBUG "parport_pc: setting SPP mode\n"); |
2692 | siofunc = VIA_FUNCTION_PARPORT_SPP; | |
2693 | break; | |
1da177e4 | 2694 | case 2: |
3aeda9bc AC |
2695 | printk(KERN_DEBUG "parport_pc: setting PS/2 mode\n"); |
2696 | siofunc = VIA_FUNCTION_PARPORT_SPP; | |
2697 | ppcontrol = VIA_PARPORT_BIDIR; | |
2698 | break; | |
1da177e4 | 2699 | case 3: |
3aeda9bc AC |
2700 | printk(KERN_DEBUG "parport_pc: setting EPP mode\n"); |
2701 | siofunc = VIA_FUNCTION_PARPORT_EPP; | |
2702 | ppcontrol = VIA_PARPORT_BIDIR; | |
2703 | have_epp = 1; | |
2704 | break; | |
1da177e4 | 2705 | case 4: |
3aeda9bc AC |
2706 | printk(KERN_DEBUG "parport_pc: setting ECP mode\n"); |
2707 | siofunc = VIA_FUNCTION_PARPORT_ECP; | |
2708 | ppcontrol = VIA_PARPORT_BIDIR; | |
2709 | break; | |
1da177e4 | 2710 | case 5: |
3aeda9bc AC |
2711 | printk(KERN_DEBUG "parport_pc: setting EPP+ECP mode\n"); |
2712 | siofunc = VIA_FUNCTION_PARPORT_ECP; | |
2713 | ppcontrol = VIA_PARPORT_BIDIR|VIA_PARPORT_ECPEPP; | |
2714 | have_epp = 1; | |
2715 | break; | |
2716 | default: | |
2717 | printk(KERN_DEBUG | |
2718 | "parport_pc: probing current configuration\n"); | |
2719 | siofunc = VIA_FUNCTION_PROBE; | |
2720 | break; | |
1da177e4 LT |
2721 | } |
2722 | /* | |
2723 | * unlock super i/o configuration | |
2724 | */ | |
2725 | pci_read_config_byte(pdev, via->via_pci_superio_config_reg, &tmp); | |
2726 | tmp |= via->via_pci_superio_config_data; | |
2727 | pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp); | |
2728 | ||
2729 | /* Bits 1-0: Parallel Port Mode / Enable */ | |
2730 | outb(via->viacfg_function, VIA_CONFIG_INDEX); | |
3aeda9bc | 2731 | tmp = inb(VIA_CONFIG_DATA); |
1da177e4 LT |
2732 | /* Bit 5: EPP+ECP enable; bit 7: PS/2 bidirectional port enable */ |
2733 | outb(via->viacfg_parport_control, VIA_CONFIG_INDEX); | |
3aeda9bc AC |
2734 | tmp2 = inb(VIA_CONFIG_DATA); |
2735 | if (siofunc == VIA_FUNCTION_PROBE) { | |
2736 | siofunc = tmp & VIA_FUNCTION_PARPORT_DISABLE; | |
2737 | ppcontrol = tmp2; | |
2738 | } else { | |
2739 | tmp &= ~VIA_FUNCTION_PARPORT_DISABLE; | |
2740 | tmp |= siofunc; | |
2741 | outb(via->viacfg_function, VIA_CONFIG_INDEX); | |
2742 | outb(tmp, VIA_CONFIG_DATA); | |
2743 | tmp2 &= ~(VIA_PARPORT_BIDIR|VIA_PARPORT_ECPEPP); | |
2744 | tmp2 |= ppcontrol; | |
2745 | outb(via->viacfg_parport_control, VIA_CONFIG_INDEX); | |
2746 | outb(tmp2, VIA_CONFIG_DATA); | |
1da177e4 | 2747 | } |
3aeda9bc | 2748 | |
1da177e4 LT |
2749 | /* Parallel Port I/O Base Address, bits 9-2 */ |
2750 | outb(via->viacfg_parport_base, VIA_CONFIG_INDEX); | |
2751 | port1 = inb(VIA_CONFIG_DATA) << 2; | |
3aeda9bc AC |
2752 | |
2753 | printk(KERN_DEBUG "parport_pc: Current parallel port base: 0x%X\n", | |
2754 | port1); | |
2755 | if (port1 == 0x3BC && have_epp) { | |
2756 | outb(via->viacfg_parport_base, VIA_CONFIG_INDEX); | |
2757 | outb((0x378 >> 2), VIA_CONFIG_DATA); | |
2758 | printk(KERN_DEBUG | |
2759 | "parport_pc: Parallel port base changed to 0x378\n"); | |
2760 | port1 = 0x378; | |
1da177e4 LT |
2761 | } |
2762 | ||
2763 | /* | |
2764 | * lock super i/o configuration | |
2765 | */ | |
2766 | pci_read_config_byte(pdev, via->via_pci_superio_config_reg, &tmp); | |
2767 | tmp &= ~via->via_pci_superio_config_data; | |
2768 | pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp); | |
2769 | ||
2770 | if (siofunc == VIA_FUNCTION_PARPORT_DISABLE) { | |
2771 | printk(KERN_INFO "parport_pc: VIA parallel port disabled in BIOS\n"); | |
2772 | return 0; | |
2773 | } | |
3aeda9bc | 2774 | |
1da177e4 LT |
2775 | /* Bits 7-4: PnP Routing for Parallel Port IRQ */ |
2776 | pci_read_config_byte(pdev, via->via_pci_parport_irq_reg, &tmp); | |
2777 | irq = ((tmp & VIA_IRQCONTROL_PARALLEL) >> 4); | |
2778 | ||
3aeda9bc AC |
2779 | if (siofunc == VIA_FUNCTION_PARPORT_ECP) { |
2780 | /* Bits 3-2: PnP Routing for Parallel Port DMA */ | |
2781 | pci_read_config_byte(pdev, via->via_pci_parport_dma_reg, &tmp); | |
2782 | dma = ((tmp & VIA_DMACONTROL_PARALLEL) >> 2); | |
2783 | } else | |
2784 | /* if ECP not enabled, DMA is not enabled, assumed | |
2785 | bogus 'dma' value */ | |
2786 | dma = PARPORT_DMA_NONE; | |
1da177e4 LT |
2787 | |
2788 | /* Let the user (or defaults) steer us away from interrupts and DMA */ | |
2789 | if (autoirq == PARPORT_IRQ_NONE) { | |
3aeda9bc AC |
2790 | irq = PARPORT_IRQ_NONE; |
2791 | dma = PARPORT_DMA_NONE; | |
1da177e4 LT |
2792 | } |
2793 | if (autodma == PARPORT_DMA_NONE) | |
3aeda9bc | 2794 | dma = PARPORT_DMA_NONE; |
1da177e4 LT |
2795 | |
2796 | switch (port1) { | |
3aeda9bc AC |
2797 | case 0x3bc: |
2798 | port2 = 0x7bc; break; | |
2799 | case 0x378: | |
2800 | port2 = 0x778; break; | |
2801 | case 0x278: | |
2802 | port2 = 0x678; break; | |
1da177e4 | 2803 | default: |
3aeda9bc AC |
2804 | printk(KERN_INFO |
2805 | "parport_pc: Weird VIA parport base 0x%X, ignoring\n", | |
2806 | port1); | |
1da177e4 LT |
2807 | return 0; |
2808 | } | |
2809 | ||
2810 | /* filter bogus IRQs */ | |
2811 | switch (irq) { | |
2812 | case 0: | |
2813 | case 2: | |
2814 | case 8: | |
2815 | case 13: | |
2816 | irq = PARPORT_IRQ_NONE; | |
2817 | break; | |
2818 | ||
2819 | default: /* do nothing */ | |
2820 | break; | |
2821 | } | |
2822 | ||
2823 | /* finally, do the probe with values obtained */ | |
3aeda9bc AC |
2824 | if (parport_pc_probe_port(port1, port2, irq, dma, &pdev->dev, 0)) { |
2825 | printk(KERN_INFO | |
1da177e4 LT |
2826 | "parport_pc: VIA parallel port: io=0x%X", port1); |
2827 | if (irq != PARPORT_IRQ_NONE) | |
3aeda9bc | 2828 | printk(", irq=%d", irq); |
1da177e4 | 2829 | if (dma != PARPORT_DMA_NONE) |
3aeda9bc AC |
2830 | printk(", dma=%d", dma); |
2831 | printk("\n"); | |
1da177e4 LT |
2832 | return 1; |
2833 | } | |
3aeda9bc | 2834 | |
1da177e4 LT |
2835 | printk(KERN_WARNING "parport_pc: Strange, can't probe VIA parallel port: io=0x%X, irq=%d, dma=%d\n", |
2836 | port1, irq, dma); | |
2837 | return 0; | |
2838 | } | |
2839 | ||
2840 | ||
2841 | enum parport_pc_sio_types { | |
3aeda9bc AC |
2842 | sio_via_686a = 0, /* Via VT82C686A motherboard Super I/O */ |
2843 | sio_via_8231, /* Via VT8231 south bridge integrated Super IO */ | |
1da177e4 LT |
2844 | sio_ite_8872, |
2845 | last_sio | |
2846 | }; | |
2847 | ||
2848 | /* each element directly indexed from enum list, above */ | |
2849 | static struct parport_pc_superio { | |
a6767b7c MK |
2850 | int (*probe) (struct pci_dev *pdev, int autoirq, int autodma, |
2851 | const struct parport_pc_via_data *via); | |
2852 | const struct parport_pc_via_data *via; | |
1da177e4 LT |
2853 | } parport_pc_superio_info[] __devinitdata = { |
2854 | { sio_via_probe, &via_686a_data, }, | |
2855 | { sio_via_probe, &via_8231_data, }, | |
2856 | { sio_ite_8872_probe, NULL, }, | |
2857 | }; | |
2858 | ||
2859 | enum parport_pc_pci_cards { | |
2860 | siig_1p_10x = last_sio, | |
2861 | siig_2p_10x, | |
2862 | siig_1p_20x, | |
2863 | siig_2p_20x, | |
2864 | lava_parallel, | |
2865 | lava_parallel_dual_a, | |
2866 | lava_parallel_dual_b, | |
2867 | boca_ioppar, | |
2868 | plx_9050, | |
2869 | timedia_4078a, | |
2870 | timedia_4079h, | |
2871 | timedia_4085h, | |
2872 | timedia_4088a, | |
2873 | timedia_4089a, | |
2874 | timedia_4095a, | |
2875 | timedia_4096a, | |
2876 | timedia_4078u, | |
2877 | timedia_4079a, | |
2878 | timedia_4085u, | |
2879 | timedia_4079r, | |
2880 | timedia_4079s, | |
2881 | timedia_4079d, | |
2882 | timedia_4079e, | |
2883 | timedia_4079f, | |
2884 | timedia_9079a, | |
2885 | timedia_9079b, | |
2886 | timedia_9079c, | |
2887 | timedia_4006a, | |
2888 | timedia_4014, | |
2889 | timedia_4008a, | |
2890 | timedia_4018, | |
2891 | timedia_9018a, | |
2892 | syba_2p_epp, | |
2893 | syba_1p_ecp, | |
2894 | titan_010l, | |
85747f03 | 2895 | titan_1284p1, |
1da177e4 LT |
2896 | titan_1284p2, |
2897 | avlab_1p, | |
2898 | avlab_2p, | |
c140e110 | 2899 | oxsemi_952, |
1da177e4 LT |
2900 | oxsemi_954, |
2901 | oxsemi_840, | |
7106b4e3 | 2902 | oxsemi_pcie_pport, |
1da177e4 LT |
2903 | aks_0100, |
2904 | mobility_pp, | |
2905 | netmos_9705, | |
2906 | netmos_9715, | |
2907 | netmos_9755, | |
2908 | netmos_9805, | |
2909 | netmos_9815, | |
c4285b47 | 2910 | netmos_9901, |
dc999159 | 2911 | quatech_sppxp100, |
1da177e4 LT |
2912 | }; |
2913 | ||
2914 | ||
3aeda9bc | 2915 | /* each element directly indexed from enum list, above |
1da177e4 LT |
2916 | * (but offset by last_sio) */ |
2917 | static struct parport_pc_pci { | |
2918 | int numports; | |
2919 | struct { /* BAR (base address registers) numbers in the config | |
3aeda9bc | 2920 | space header */ |
1da177e4 | 2921 | int lo; |
3aeda9bc AC |
2922 | int hi; |
2923 | /* -1 if not there, >6 for offset-method (max BAR is 6) */ | |
1da177e4 LT |
2924 | } addr[4]; |
2925 | ||
2926 | /* If set, this is called immediately after pci_enable_device. | |
2927 | * If it returns non-zero, no probing will take place and the | |
2928 | * ports will not be used. */ | |
2929 | int (*preinit_hook) (struct pci_dev *pdev, int autoirq, int autodma); | |
2930 | ||
2931 | /* If set, this is called after probing for ports. If 'failed' | |
2932 | * is non-zero we couldn't use any of the ports. */ | |
2933 | void (*postinit_hook) (struct pci_dev *pdev, int failed); | |
96766a3c | 2934 | } cards[] = { |
1da177e4 LT |
2935 | /* siig_1p_10x */ { 1, { { 2, 3 }, } }, |
2936 | /* siig_2p_10x */ { 2, { { 2, 3 }, { 4, 5 }, } }, | |
2937 | /* siig_1p_20x */ { 1, { { 0, 1 }, } }, | |
2938 | /* siig_2p_20x */ { 2, { { 0, 1 }, { 2, 3 }, } }, | |
2939 | /* lava_parallel */ { 1, { { 0, -1 }, } }, | |
2940 | /* lava_parallel_dual_a */ { 1, { { 0, -1 }, } }, | |
2941 | /* lava_parallel_dual_b */ { 1, { { 0, -1 }, } }, | |
2942 | /* boca_ioppar */ { 1, { { 0, -1 }, } }, | |
2943 | /* plx_9050 */ { 2, { { 4, -1 }, { 5, -1 }, } }, | |
2944 | /* timedia_4078a */ { 1, { { 2, -1 }, } }, | |
2945 | /* timedia_4079h */ { 1, { { 2, 3 }, } }, | |
2946 | /* timedia_4085h */ { 2, { { 2, -1 }, { 4, -1 }, } }, | |
2947 | /* timedia_4088a */ { 2, { { 2, 3 }, { 4, 5 }, } }, | |
2948 | /* timedia_4089a */ { 2, { { 2, 3 }, { 4, 5 }, } }, | |
2949 | /* timedia_4095a */ { 2, { { 2, 3 }, { 4, 5 }, } }, | |
2950 | /* timedia_4096a */ { 2, { { 2, 3 }, { 4, 5 }, } }, | |
2951 | /* timedia_4078u */ { 1, { { 2, -1 }, } }, | |
2952 | /* timedia_4079a */ { 1, { { 2, 3 }, } }, | |
2953 | /* timedia_4085u */ { 2, { { 2, -1 }, { 4, -1 }, } }, | |
2954 | /* timedia_4079r */ { 1, { { 2, 3 }, } }, | |
2955 | /* timedia_4079s */ { 1, { { 2, 3 }, } }, | |
2956 | /* timedia_4079d */ { 1, { { 2, 3 }, } }, | |
2957 | /* timedia_4079e */ { 1, { { 2, 3 }, } }, | |
2958 | /* timedia_4079f */ { 1, { { 2, 3 }, } }, | |
2959 | /* timedia_9079a */ { 1, { { 2, 3 }, } }, | |
2960 | /* timedia_9079b */ { 1, { { 2, 3 }, } }, | |
2961 | /* timedia_9079c */ { 1, { { 2, 3 }, } }, | |
2962 | /* timedia_4006a */ { 1, { { 0, -1 }, } }, | |
2963 | /* timedia_4014 */ { 2, { { 0, -1 }, { 2, -1 }, } }, | |
2964 | /* timedia_4008a */ { 1, { { 0, 1 }, } }, | |
2965 | /* timedia_4018 */ { 2, { { 0, 1 }, { 2, 3 }, } }, | |
2966 | /* timedia_9018a */ { 2, { { 0, 1 }, { 2, 3 }, } }, | |
2967 | /* SYBA uses fixed offsets in | |
3aeda9bc | 2968 | a 1K io window */ |
1da177e4 LT |
2969 | /* syba_2p_epp AP138B */ { 2, { { 0, 0x078 }, { 0, 0x178 }, } }, |
2970 | /* syba_1p_ecp W83787 */ { 1, { { 0, 0x078 }, } }, | |
2971 | /* titan_010l */ { 1, { { 3, -1 }, } }, | |
85747f03 | 2972 | /* titan_1284p1 */ { 1, { { 0, 1 }, } }, |
1da177e4 LT |
2973 | /* titan_1284p2 */ { 2, { { 0, 1 }, { 2, 3 }, } }, |
2974 | /* avlab_1p */ { 1, { { 0, 1}, } }, | |
2975 | /* avlab_2p */ { 2, { { 0, 1}, { 2, 3 },} }, | |
2976 | /* The Oxford Semi cards are unusual: 954 doesn't support ECP, | |
2977 | * and 840 locks up if you write 1 to bit 2! */ | |
c140e110 | 2978 | /* oxsemi_952 */ { 1, { { 0, 1 }, } }, |
1da177e4 | 2979 | /* oxsemi_954 */ { 1, { { 0, -1 }, } }, |
adbd321a | 2980 | /* oxsemi_840 */ { 1, { { 0, 1 }, } }, |
7106b4e3 | 2981 | /* oxsemi_pcie_pport */ { 1, { { 0, 1 }, } }, |
1da177e4 LT |
2982 | /* aks_0100 */ { 1, { { 0, -1 }, } }, |
2983 | /* mobility_pp */ { 1, { { 0, 1 }, } }, | |
3aeda9bc AC |
2984 | |
2985 | /* The netmos entries below are untested */ | |
2986 | /* netmos_9705 */ { 1, { { 0, -1 }, } }, | |
2987 | /* netmos_9715 */ { 2, { { 0, 1 }, { 2, 3 },} }, | |
2988 | /* netmos_9755 */ { 2, { { 0, 1 }, { 2, 3 },} }, | |
2989 | /* netmos_9805 */ { 1, { { 0, -1 }, } }, | |
2990 | /* netmos_9815 */ { 2, { { 0, -1 }, { 2, -1 }, } }, | |
c4285b47 | 2991 | /* netmos_9901 */ { 1, { { 0, -1 }, } }, |
dc999159 | 2992 | /* quatech_sppxp100 */ { 1, { { 0, 1 }, } }, |
1da177e4 LT |
2993 | }; |
2994 | ||
a6767b7c | 2995 | static const struct pci_device_id parport_pc_pci_tbl[] = { |
1da177e4 LT |
2996 | /* Super-IO onboard chips */ |
2997 | { 0x1106, 0x0686, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_686a }, | |
2998 | { 0x1106, 0x8231, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_8231 }, | |
2999 | { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872, | |
3000 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_ite_8872 }, | |
3001 | ||
3002 | /* PCI cards */ | |
3003 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_10x, | |
3004 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_10x }, | |
3005 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_10x, | |
3006 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_10x }, | |
3007 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_20x, | |
3008 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_20x }, | |
3009 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_20x, | |
3010 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_20x }, | |
3011 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PARALLEL, | |
3012 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel }, | |
3013 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_A, | |
3014 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_a }, | |
3015 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_B, | |
3016 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_b }, | |
3017 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_BOCA_IOPPAR, | |
3018 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, boca_ioppar }, | |
3019 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, | |
3aeda9bc | 3020 | PCI_SUBVENDOR_ID_EXSYS, PCI_SUBDEVICE_ID_EXSYS_4014, 0, 0, plx_9050 }, |
1da177e4 LT |
3021 | /* PCI_VENDOR_ID_TIMEDIA/SUNIX has many differing cards ...*/ |
3022 | { 0x1409, 0x7168, 0x1409, 0x4078, 0, 0, timedia_4078a }, | |
3023 | { 0x1409, 0x7168, 0x1409, 0x4079, 0, 0, timedia_4079h }, | |
3024 | { 0x1409, 0x7168, 0x1409, 0x4085, 0, 0, timedia_4085h }, | |
3025 | { 0x1409, 0x7168, 0x1409, 0x4088, 0, 0, timedia_4088a }, | |
3026 | { 0x1409, 0x7168, 0x1409, 0x4089, 0, 0, timedia_4089a }, | |
3027 | { 0x1409, 0x7168, 0x1409, 0x4095, 0, 0, timedia_4095a }, | |
3028 | { 0x1409, 0x7168, 0x1409, 0x4096, 0, 0, timedia_4096a }, | |
3029 | { 0x1409, 0x7168, 0x1409, 0x5078, 0, 0, timedia_4078u }, | |
3030 | { 0x1409, 0x7168, 0x1409, 0x5079, 0, 0, timedia_4079a }, | |
3031 | { 0x1409, 0x7168, 0x1409, 0x5085, 0, 0, timedia_4085u }, | |
3032 | { 0x1409, 0x7168, 0x1409, 0x6079, 0, 0, timedia_4079r }, | |
3033 | { 0x1409, 0x7168, 0x1409, 0x7079, 0, 0, timedia_4079s }, | |
3034 | { 0x1409, 0x7168, 0x1409, 0x8079, 0, 0, timedia_4079d }, | |
3035 | { 0x1409, 0x7168, 0x1409, 0x9079, 0, 0, timedia_4079e }, | |
3036 | { 0x1409, 0x7168, 0x1409, 0xa079, 0, 0, timedia_4079f }, | |
3037 | { 0x1409, 0x7168, 0x1409, 0xb079, 0, 0, timedia_9079a }, | |
3038 | { 0x1409, 0x7168, 0x1409, 0xc079, 0, 0, timedia_9079b }, | |
3039 | { 0x1409, 0x7168, 0x1409, 0xd079, 0, 0, timedia_9079c }, | |
3040 | { 0x1409, 0x7268, 0x1409, 0x0101, 0, 0, timedia_4006a }, | |
3041 | { 0x1409, 0x7268, 0x1409, 0x0102, 0, 0, timedia_4014 }, | |
3042 | { 0x1409, 0x7268, 0x1409, 0x0103, 0, 0, timedia_4008a }, | |
3043 | { 0x1409, 0x7268, 0x1409, 0x0104, 0, 0, timedia_4018 }, | |
3044 | { 0x1409, 0x7268, 0x1409, 0x9018, 0, 0, timedia_9018a }, | |
1da177e4 LT |
3045 | { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_2P_EPP, |
3046 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_2p_epp }, | |
3047 | { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_1P_ECP, | |
3048 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_1p_ecp }, | |
3049 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_010L, | |
3050 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, titan_010l }, | |
85747f03 | 3051 | { 0x9710, 0x9805, 0x1000, 0x0010, 0, 0, titan_1284p1 }, |
1da177e4 LT |
3052 | { 0x9710, 0x9815, 0x1000, 0x0020, 0, 0, titan_1284p2 }, |
3053 | /* PCI_VENDOR_ID_AVLAB/Intek21 has another bunch of cards ...*/ | |
3aeda9bc AC |
3054 | /* AFAVLAB_TK9902 */ |
3055 | { 0x14db, 0x2120, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1p}, | |
1da177e4 | 3056 | { 0x14db, 0x2121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2p}, |
c140e110 RU |
3057 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952PP, |
3058 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_952 }, | |
1da177e4 LT |
3059 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954PP, |
3060 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_954 }, | |
3061 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_12PCI840, | |
3062 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_840 }, | |
7106b4e3 LH |
3063 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe840, |
3064 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport }, | |
3065 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe840_G, | |
3066 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport }, | |
3067 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_0, | |
3068 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport }, | |
3069 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_0_G, | |
3070 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport }, | |
3071 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1, | |
3072 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport }, | |
3073 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_G, | |
3074 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport }, | |
3075 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_U, | |
3076 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport }, | |
3077 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_GU, | |
3078 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport }, | |
1da177e4 LT |
3079 | { PCI_VENDOR_ID_AKS, PCI_DEVICE_ID_AKS_ALADDINCARD, |
3080 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, aks_0100 }, | |
7106b4e3 | 3081 | { 0x14f2, 0x0121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, mobility_pp }, |
1da177e4 LT |
3082 | /* NetMos communication controllers */ |
3083 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9705, | |
3084 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9705 }, | |
3085 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9715, | |
3086 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9715 }, | |
3087 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9755, | |
3088 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9755 }, | |
3089 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9805, | |
3090 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9805 }, | |
3091 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9815, | |
3092 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9815 }, | |
c4285b47 MB |
3093 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901, |
3094 | 0xA000, 0x2000, 0, 0, netmos_9901 }, | |
dc999159 LM |
3095 | /* Quatech SPPXP-100 Parallel port PCI ExpressCard */ |
3096 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SPPXP_100, | |
3097 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, quatech_sppxp100 }, | |
1da177e4 LT |
3098 | { 0, } /* terminate list */ |
3099 | }; | |
3aeda9bc | 3100 | MODULE_DEVICE_TABLE(pci, parport_pc_pci_tbl); |
1da177e4 LT |
3101 | |
3102 | struct pci_parport_data { | |
3103 | int num; | |
3104 | struct parport *ports[2]; | |
3105 | }; | |
3106 | ||
3aeda9bc | 3107 | static int parport_pc_pci_probe(struct pci_dev *dev, |
1da177e4 LT |
3108 | const struct pci_device_id *id) |
3109 | { | |
3110 | int err, count, n, i = id->driver_data; | |
3111 | struct pci_parport_data *data; | |
3112 | ||
3113 | if (i < last_sio) | |
3114 | /* This is an onboard Super-IO and has already been probed */ | |
3115 | return 0; | |
3116 | ||
3117 | /* This is a PCI card */ | |
3118 | i -= last_sio; | |
3119 | count = 0; | |
3aeda9bc AC |
3120 | err = pci_enable_device(dev); |
3121 | if (err) | |
1da177e4 LT |
3122 | return err; |
3123 | ||
3124 | data = kmalloc(sizeof(struct pci_parport_data), GFP_KERNEL); | |
3125 | if (!data) | |
3126 | return -ENOMEM; | |
3127 | ||
3128 | if (cards[i].preinit_hook && | |
3aeda9bc | 3129 | cards[i].preinit_hook(dev, PARPORT_IRQ_NONE, PARPORT_DMA_NONE)) { |
1da177e4 LT |
3130 | kfree(data); |
3131 | return -ENODEV; | |
3132 | } | |
3133 | ||
3134 | for (n = 0; n < cards[i].numports; n++) { | |
3135 | int lo = cards[i].addr[n].lo; | |
3136 | int hi = cards[i].addr[n].hi; | |
51dcdfec | 3137 | int irq; |
1da177e4 | 3138 | unsigned long io_lo, io_hi; |
3aeda9bc | 3139 | io_lo = pci_resource_start(dev, lo); |
1da177e4 LT |
3140 | io_hi = 0; |
3141 | if ((hi >= 0) && (hi <= 6)) | |
3aeda9bc | 3142 | io_hi = pci_resource_start(dev, hi); |
1da177e4 LT |
3143 | else if (hi > 6) |
3144 | io_lo += hi; /* Reinterpret the meaning of | |
3aeda9bc AC |
3145 | "hi" as an offset (see SYBA |
3146 | def.) */ | |
1da177e4 | 3147 | /* TODO: test if sharing interrupts works */ |
51dcdfec AC |
3148 | irq = dev->irq; |
3149 | if (irq == IRQ_NONE) { | |
3aeda9bc | 3150 | printk(KERN_DEBUG |
51dcdfec AC |
3151 | "PCI parallel port detected: %04x:%04x, I/O at %#lx(%#lx)\n", |
3152 | parport_pc_pci_tbl[i + last_sio].vendor, | |
3153 | parport_pc_pci_tbl[i + last_sio].device, | |
3154 | io_lo, io_hi); | |
3155 | irq = PARPORT_IRQ_NONE; | |
3156 | } else { | |
3aeda9bc | 3157 | printk(KERN_DEBUG |
51dcdfec AC |
3158 | "PCI parallel port detected: %04x:%04x, I/O at %#lx(%#lx), IRQ %d\n", |
3159 | parport_pc_pci_tbl[i + last_sio].vendor, | |
3160 | parport_pc_pci_tbl[i + last_sio].device, | |
3161 | io_lo, io_hi, irq); | |
3162 | } | |
1da177e4 | 3163 | data->ports[count] = |
51dcdfec AC |
3164 | parport_pc_probe_port(io_lo, io_hi, irq, |
3165 | PARPORT_DMA_NONE, &dev->dev, | |
3166 | IRQF_SHARED); | |
1da177e4 LT |
3167 | if (data->ports[count]) |
3168 | count++; | |
3169 | } | |
3170 | ||
3171 | data->num = count; | |
3172 | ||
3173 | if (cards[i].postinit_hook) | |
3aeda9bc | 3174 | cards[i].postinit_hook(dev, count == 0); |
1da177e4 LT |
3175 | |
3176 | if (count) { | |
3177 | pci_set_drvdata(dev, data); | |
3178 | return 0; | |
3179 | } | |
3180 | ||
3181 | kfree(data); | |
3182 | ||
3183 | return -ENODEV; | |
3184 | } | |
3185 | ||
3186 | static void __devexit parport_pc_pci_remove(struct pci_dev *dev) | |
3187 | { | |
3188 | struct pci_parport_data *data = pci_get_drvdata(dev); | |
3189 | int i; | |
3190 | ||
3191 | pci_set_drvdata(dev, NULL); | |
3192 | ||
3193 | if (data) { | |
3194 | for (i = data->num - 1; i >= 0; i--) | |
3195 | parport_pc_unregister_port(data->ports[i]); | |
3196 | ||
3197 | kfree(data); | |
3198 | } | |
3199 | } | |
3200 | ||
3201 | static struct pci_driver parport_pc_pci_driver = { | |
3202 | .name = "parport_pc", | |
3203 | .id_table = parport_pc_pci_tbl, | |
3204 | .probe = parport_pc_pci_probe, | |
3205 | .remove = __devexit_p(parport_pc_pci_remove), | |
3206 | }; | |
3207 | ||
3aeda9bc | 3208 | static int __init parport_pc_init_superio(int autoirq, int autodma) |
1da177e4 LT |
3209 | { |
3210 | const struct pci_device_id *id; | |
3211 | struct pci_dev *pdev = NULL; | |
3212 | int ret = 0; | |
3213 | ||
c9d8073f | 3214 | for_each_pci_dev(pdev) { |
75865858 | 3215 | id = pci_match_id(parport_pc_pci_tbl, pdev); |
1da177e4 LT |
3216 | if (id == NULL || id->driver_data >= last_sio) |
3217 | continue; | |
3218 | ||
3aeda9bc AC |
3219 | if (parport_pc_superio_info[id->driver_data].probe( |
3220 | pdev, autoirq, autodma, | |
3221 | parport_pc_superio_info[id->driver_data].via)) { | |
1da177e4 LT |
3222 | ret++; |
3223 | } | |
3224 | } | |
3225 | ||
3226 | return ret; /* number of devices found */ | |
3227 | } | |
3228 | #else | |
3229 | static struct pci_driver parport_pc_pci_driver; | |
3aeda9bc AC |
3230 | static int __init parport_pc_init_superio(int autoirq, int autodma) |
3231 | { | |
3232 | return 0; | |
3233 | } | |
1da177e4 LT |
3234 | #endif /* CONFIG_PCI */ |
3235 | ||
f2b9a396 | 3236 | #ifdef CONFIG_PNP |
1da177e4 LT |
3237 | |
3238 | static const struct pnp_device_id parport_pc_pnp_tbl[] = { | |
3239 | /* Standard LPT Printer Port */ | |
3240 | {.id = "PNP0400", .driver_data = 0}, | |
3241 | /* ECP Printer Port */ | |
3242 | {.id = "PNP0401", .driver_data = 0}, | |
3243 | { } | |
3244 | }; | |
3245 | ||
3aeda9bc | 3246 | MODULE_DEVICE_TABLE(pnp, parport_pc_pnp_tbl); |
1da177e4 | 3247 | |
3aeda9bc AC |
3248 | static int parport_pc_pnp_probe(struct pnp_dev *dev, |
3249 | const struct pnp_device_id *id) | |
1da177e4 LT |
3250 | { |
3251 | struct parport *pdata; | |
3252 | unsigned long io_lo, io_hi; | |
3253 | int dma, irq; | |
3254 | ||
3aeda9bc AC |
3255 | if (pnp_port_valid(dev, 0) && |
3256 | !(pnp_port_flags(dev, 0) & IORESOURCE_DISABLED)) { | |
3257 | io_lo = pnp_port_start(dev, 0); | |
1da177e4 LT |
3258 | } else |
3259 | return -EINVAL; | |
3260 | ||
3aeda9bc AC |
3261 | if (pnp_port_valid(dev, 1) && |
3262 | !(pnp_port_flags(dev, 1) & IORESOURCE_DISABLED)) { | |
3263 | io_hi = pnp_port_start(dev, 1); | |
1da177e4 LT |
3264 | } else |
3265 | io_hi = 0; | |
3266 | ||
3aeda9bc AC |
3267 | if (pnp_irq_valid(dev, 0) && |
3268 | !(pnp_irq_flags(dev, 0) & IORESOURCE_DISABLED)) { | |
3269 | irq = pnp_irq(dev, 0); | |
1da177e4 LT |
3270 | } else |
3271 | irq = PARPORT_IRQ_NONE; | |
3272 | ||
3aeda9bc AC |
3273 | if (pnp_dma_valid(dev, 0) && |
3274 | !(pnp_dma_flags(dev, 0) & IORESOURCE_DISABLED)) { | |
3275 | dma = pnp_dma(dev, 0); | |
1da177e4 LT |
3276 | } else |
3277 | dma = PARPORT_DMA_NONE; | |
3278 | ||
c15a3837 | 3279 | dev_info(&dev->dev, "reported by %s\n", dev->protocol->name); |
3aeda9bc AC |
3280 | pdata = parport_pc_probe_port(io_lo, io_hi, irq, dma, &dev->dev, 0); |
3281 | if (pdata == NULL) | |
1da177e4 LT |
3282 | return -ENODEV; |
3283 | ||
3aeda9bc | 3284 | pnp_set_drvdata(dev, pdata); |
1da177e4 LT |
3285 | return 0; |
3286 | } | |
3287 | ||
3288 | static void parport_pc_pnp_remove(struct pnp_dev *dev) | |
3289 | { | |
3290 | struct parport *pdata = (struct parport *)pnp_get_drvdata(dev); | |
3291 | if (!pdata) | |
3292 | return; | |
3293 | ||
3294 | parport_pc_unregister_port(pdata); | |
3295 | } | |
3296 | ||
3297 | /* we only need the pnp layer to activate the device, at least for now */ | |
3298 | static struct pnp_driver parport_pc_pnp_driver = { | |
3299 | .name = "parport_pc", | |
3300 | .id_table = parport_pc_pnp_tbl, | |
3301 | .probe = parport_pc_pnp_probe, | |
3302 | .remove = parport_pc_pnp_remove, | |
3303 | }; | |
3304 | ||
f2b9a396 BH |
3305 | #else |
3306 | static struct pnp_driver parport_pc_pnp_driver; | |
3307 | #endif /* CONFIG_PNP */ | |
1da177e4 | 3308 | |
a7d801af JD |
3309 | static int __devinit parport_pc_platform_probe(struct platform_device *pdev) |
3310 | { | |
3311 | /* Always succeed, the actual probing is done in | |
3312 | * parport_pc_probe_port(). */ | |
3313 | return 0; | |
3314 | } | |
3315 | ||
3316 | static struct platform_driver parport_pc_platform_driver = { | |
3317 | .driver = { | |
3318 | .owner = THIS_MODULE, | |
3319 | .name = "parport_pc", | |
3320 | }, | |
3321 | .probe = parport_pc_platform_probe, | |
3322 | }; | |
3323 | ||
1da177e4 LT |
3324 | /* This is called by parport_pc_find_nonpci_ports (in asm/parport.h) */ |
3325 | static int __devinit __attribute__((unused)) | |
3aeda9bc | 3326 | parport_pc_find_isa_ports(int autoirq, int autodma) |
1da177e4 LT |
3327 | { |
3328 | int count = 0; | |
3329 | ||
51dcdfec | 3330 | if (parport_pc_probe_port(0x3bc, 0x7bc, autoirq, autodma, NULL, 0)) |
1da177e4 | 3331 | count++; |
51dcdfec | 3332 | if (parport_pc_probe_port(0x378, 0x778, autoirq, autodma, NULL, 0)) |
1da177e4 | 3333 | count++; |
51dcdfec | 3334 | if (parport_pc_probe_port(0x278, 0x678, autoirq, autodma, NULL, 0)) |
1da177e4 LT |
3335 | count++; |
3336 | ||
3337 | return count; | |
3338 | } | |
3339 | ||
3340 | /* This function is called by parport_pc_init if the user didn't | |
3341 | * specify any ports to probe. Its job is to find some ports. Order | |
3342 | * is important here -- we want ISA ports to be registered first, | |
3343 | * followed by PCI cards (for least surprise), but before that we want | |
3344 | * to do chipset-specific tests for some onboard ports that we know | |
3345 | * about. | |
3346 | * | |
3347 | * autoirq is PARPORT_IRQ_NONE, PARPORT_IRQ_AUTO, or PARPORT_IRQ_PROBEONLY | |
3348 | * autodma is PARPORT_DMA_NONE or PARPORT_DMA_AUTO | |
3349 | */ | |
3aeda9bc | 3350 | static void __init parport_pc_find_ports(int autoirq, int autodma) |
1da177e4 | 3351 | { |
7597fee3 | 3352 | int count = 0, err; |
1da177e4 LT |
3353 | |
3354 | #ifdef CONFIG_PARPORT_PC_SUPERIO | |
f63fd7e2 PC |
3355 | detect_and_report_it87(); |
3356 | detect_and_report_winbond(); | |
3357 | detect_and_report_smsc(); | |
1da177e4 LT |
3358 | #endif |
3359 | ||
3360 | /* Onboard SuperIO chipsets that show themselves on the PCI bus. */ | |
f63fd7e2 | 3361 | count += parport_pc_init_superio(autoirq, autodma); |
1da177e4 LT |
3362 | |
3363 | /* PnP ports, skip detection if SuperIO already found them */ | |
3364 | if (!count) { | |
f63fd7e2 | 3365 | err = pnp_register_driver(&parport_pc_pnp_driver); |
7597fee3 | 3366 | if (!err) |
1da177e4 | 3367 | pnp_registered_parport = 1; |
1da177e4 LT |
3368 | } |
3369 | ||
3370 | /* ISA ports and whatever (see asm/parport.h). */ | |
f63fd7e2 | 3371 | parport_pc_find_nonpci_ports(autoirq, autodma); |
1da177e4 | 3372 | |
f63fd7e2 | 3373 | err = pci_register_driver(&parport_pc_pci_driver); |
7597fee3 BH |
3374 | if (!err) |
3375 | pci_registered_parport = 1; | |
1da177e4 LT |
3376 | } |
3377 | ||
3378 | /* | |
3379 | * Piles of crap below pretend to be a parser for module and kernel | |
3380 | * parameters. Say "thank you" to whoever had come up with that | |
3381 | * syntax and keep in mind that code below is a cleaned up version. | |
3382 | */ | |
3383 | ||
3aeda9bc AC |
3384 | static int __initdata io[PARPORT_PC_MAX_PORTS+1] = { |
3385 | [0 ... PARPORT_PC_MAX_PORTS] = 0 | |
3386 | }; | |
3387 | static int __initdata io_hi[PARPORT_PC_MAX_PORTS+1] = { | |
3388 | [0 ... PARPORT_PC_MAX_PORTS] = PARPORT_IOHI_AUTO | |
3389 | }; | |
3390 | static int __initdata dmaval[PARPORT_PC_MAX_PORTS] = { | |
3391 | [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_DMA_NONE | |
3392 | }; | |
3393 | static int __initdata irqval[PARPORT_PC_MAX_PORTS] = { | |
3394 | [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_IRQ_PROBEONLY | |
3395 | }; | |
1da177e4 LT |
3396 | |
3397 | static int __init parport_parse_param(const char *s, int *val, | |
3398 | int automatic, int none, int nofifo) | |
3399 | { | |
3400 | if (!s) | |
3401 | return 0; | |
3402 | if (!strncmp(s, "auto", 4)) | |
3403 | *val = automatic; | |
3404 | else if (!strncmp(s, "none", 4)) | |
3405 | *val = none; | |
3406 | else if (nofifo && !strncmp(s, "nofifo", 4)) | |
3407 | *val = nofifo; | |
3408 | else { | |
3409 | char *ep; | |
3410 | unsigned long r = simple_strtoul(s, &ep, 0); | |
3411 | if (ep != s) | |
3412 | *val = r; | |
3413 | else { | |
3414 | printk(KERN_ERR "parport: bad specifier `%s'\n", s); | |
3415 | return -1; | |
3416 | } | |
3417 | } | |
3418 | return 0; | |
3419 | } | |
3420 | ||
3421 | static int __init parport_parse_irq(const char *irqstr, int *val) | |
3422 | { | |
3423 | return parport_parse_param(irqstr, val, PARPORT_IRQ_AUTO, | |
3424 | PARPORT_IRQ_NONE, 0); | |
3425 | } | |
3426 | ||
3427 | static int __init parport_parse_dma(const char *dmastr, int *val) | |
3428 | { | |
3429 | return parport_parse_param(dmastr, val, PARPORT_DMA_AUTO, | |
3430 | PARPORT_DMA_NONE, PARPORT_DMA_NOFIFO); | |
3431 | } | |
3432 | ||
3433 | #ifdef CONFIG_PCI | |
3434 | static int __init parport_init_mode_setup(char *str) | |
3435 | { | |
3aeda9bc AC |
3436 | printk(KERN_DEBUG |
3437 | "parport_pc.c: Specified parameter parport_init_mode=%s\n", str); | |
3438 | ||
3439 | if (!strcmp(str, "spp")) | |
3440 | parport_init_mode = 1; | |
3441 | if (!strcmp(str, "ps2")) | |
3442 | parport_init_mode = 2; | |
3443 | if (!strcmp(str, "epp")) | |
3444 | parport_init_mode = 3; | |
3445 | if (!strcmp(str, "ecp")) | |
3446 | parport_init_mode = 4; | |
3447 | if (!strcmp(str, "ecpepp")) | |
3448 | parport_init_mode = 5; | |
1da177e4 LT |
3449 | return 1; |
3450 | } | |
3451 | #endif | |
3452 | ||
3453 | #ifdef MODULE | |
3454 | static const char *irq[PARPORT_PC_MAX_PORTS]; | |
3455 | static const char *dma[PARPORT_PC_MAX_PORTS]; | |
3456 | ||
3457 | MODULE_PARM_DESC(io, "Base I/O address (SPP regs)"); | |
3458 | module_param_array(io, int, NULL, 0); | |
3459 | MODULE_PARM_DESC(io_hi, "Base I/O address (ECR)"); | |
3460 | module_param_array(io_hi, int, NULL, 0); | |
3461 | MODULE_PARM_DESC(irq, "IRQ line"); | |
3462 | module_param_array(irq, charp, NULL, 0); | |
3463 | MODULE_PARM_DESC(dma, "DMA channel"); | |
3464 | module_param_array(dma, charp, NULL, 0); | |
3465 | #if defined(CONFIG_PARPORT_PC_SUPERIO) || \ | |
3466 | (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO)) | |
3467 | MODULE_PARM_DESC(verbose_probing, "Log chit-chat during initialisation"); | |
3468 | module_param(verbose_probing, int, 0644); | |
3469 | #endif | |
3470 | #ifdef CONFIG_PCI | |
3471 | static char *init_mode; | |
3aeda9bc AC |
3472 | MODULE_PARM_DESC(init_mode, |
3473 | "Initialise mode for VIA VT8231 port (spp, ps2, epp, ecp or ecpepp)"); | |
1da177e4 LT |
3474 | module_param(init_mode, charp, 0); |
3475 | #endif | |
3476 | ||
3477 | static int __init parse_parport_params(void) | |
3478 | { | |
3479 | unsigned int i; | |
3480 | int val; | |
3481 | ||
3482 | #ifdef CONFIG_PCI | |
3483 | if (init_mode) | |
3484 | parport_init_mode_setup(init_mode); | |
3485 | #endif | |
3486 | ||
3487 | for (i = 0; i < PARPORT_PC_MAX_PORTS && io[i]; i++) { | |
3488 | if (parport_parse_irq(irq[i], &val)) | |
3489 | return 1; | |
3490 | irqval[i] = val; | |
3491 | if (parport_parse_dma(dma[i], &val)) | |
3492 | return 1; | |
3493 | dmaval[i] = val; | |
3494 | } | |
3495 | if (!io[0]) { | |
3496 | /* The user can make us use any IRQs or DMAs we find. */ | |
3497 | if (irq[0] && !parport_parse_irq(irq[0], &val)) | |
3498 | switch (val) { | |
3499 | case PARPORT_IRQ_NONE: | |
3500 | case PARPORT_IRQ_AUTO: | |
3501 | irqval[0] = val; | |
3502 | break; | |
3503 | default: | |
3aeda9bc | 3504 | printk(KERN_WARNING |
1da177e4 LT |
3505 | "parport_pc: irq specified " |
3506 | "without base address. Use 'io=' " | |
3507 | "to specify one\n"); | |
3508 | } | |
3509 | ||
3510 | if (dma[0] && !parport_parse_dma(dma[0], &val)) | |
3511 | switch (val) { | |
3512 | case PARPORT_DMA_NONE: | |
3513 | case PARPORT_DMA_AUTO: | |
3514 | dmaval[0] = val; | |
3515 | break; | |
3516 | default: | |
3aeda9bc | 3517 | printk(KERN_WARNING |
1da177e4 LT |
3518 | "parport_pc: dma specified " |
3519 | "without base address. Use 'io=' " | |
3520 | "to specify one\n"); | |
3521 | } | |
3522 | } | |
3523 | return 0; | |
3524 | } | |
3525 | ||
3526 | #else | |
3527 | ||
3aeda9bc | 3528 | static int parport_setup_ptr __initdata; |
1da177e4 LT |
3529 | |
3530 | /* | |
3531 | * Acceptable parameters: | |
3532 | * | |
3533 | * parport=0 | |
3534 | * parport=auto | |
3535 | * parport=0xBASE[,IRQ[,DMA]] | |
3536 | * | |
3537 | * IRQ/DMA may be numeric or 'auto' or 'none' | |
3538 | */ | |
3aeda9bc | 3539 | static int __init parport_setup(char *str) |
1da177e4 LT |
3540 | { |
3541 | char *endptr; | |
3542 | char *sep; | |
3543 | int val; | |
3544 | ||
3545 | if (!str || !*str || (*str == '0' && !*(str+1))) { | |
3546 | /* Disable parport if "parport=0" in cmdline */ | |
3547 | io[0] = PARPORT_DISABLE; | |
3548 | return 1; | |
3549 | } | |
3550 | ||
3aeda9bc | 3551 | if (!strncmp(str, "auto", 4)) { |
1da177e4 LT |
3552 | irqval[0] = PARPORT_IRQ_AUTO; |
3553 | dmaval[0] = PARPORT_DMA_AUTO; | |
3554 | return 1; | |
3555 | } | |
3556 | ||
3aeda9bc | 3557 | val = simple_strtoul(str, &endptr, 0); |
1da177e4 | 3558 | if (endptr == str) { |
3aeda9bc | 3559 | printk(KERN_WARNING "parport=%s not understood\n", str); |
1da177e4 LT |
3560 | return 1; |
3561 | } | |
3562 | ||
3563 | if (parport_setup_ptr == PARPORT_PC_MAX_PORTS) { | |
3564 | printk(KERN_ERR "parport=%s ignored, too many ports\n", str); | |
3565 | return 1; | |
3566 | } | |
3567 | ||
3568 | io[parport_setup_ptr] = val; | |
3569 | irqval[parport_setup_ptr] = PARPORT_IRQ_NONE; | |
3570 | dmaval[parport_setup_ptr] = PARPORT_DMA_NONE; | |
3571 | ||
3572 | sep = strchr(str, ','); | |
3573 | if (sep++) { | |
3574 | if (parport_parse_irq(sep, &val)) | |
3575 | return 1; | |
3576 | irqval[parport_setup_ptr] = val; | |
3577 | sep = strchr(sep, ','); | |
3578 | if (sep++) { | |
3579 | if (parport_parse_dma(sep, &val)) | |
3580 | return 1; | |
3581 | dmaval[parport_setup_ptr] = val; | |
3582 | } | |
3583 | } | |
3584 | parport_setup_ptr++; | |
3585 | return 1; | |
3586 | } | |
3587 | ||
3588 | static int __init parse_parport_params(void) | |
3589 | { | |
3590 | return io[0] == PARPORT_DISABLE; | |
3591 | } | |
3592 | ||
3aeda9bc | 3593 | __setup("parport=", parport_setup); |
1da177e4 LT |
3594 | |
3595 | /* | |
3596 | * Acceptable parameters: | |
3597 | * | |
3598 | * parport_init_mode=[spp|ps2|epp|ecp|ecpepp] | |
3599 | */ | |
3600 | #ifdef CONFIG_PCI | |
3aeda9bc | 3601 | __setup("parport_init_mode=", parport_init_mode_setup); |
1da177e4 LT |
3602 | #endif |
3603 | #endif | |
3604 | ||
3605 | /* "Parser" ends here */ | |
3606 | ||
3607 | static int __init parport_pc_init(void) | |
3608 | { | |
a7d801af JD |
3609 | int err; |
3610 | ||
1da177e4 LT |
3611 | if (parse_parport_params()) |
3612 | return -EINVAL; | |
3613 | ||
a7d801af JD |
3614 | err = platform_driver_register(&parport_pc_platform_driver); |
3615 | if (err) | |
3616 | return err; | |
3617 | ||
1da177e4 LT |
3618 | if (io[0]) { |
3619 | int i; | |
3620 | /* Only probe the ports we were given. */ | |
3621 | user_specified = 1; | |
3622 | for (i = 0; i < PARPORT_PC_MAX_PORTS; i++) { | |
3623 | if (!io[i]) | |
3624 | break; | |
3aeda9bc AC |
3625 | if (io_hi[i] == PARPORT_IOHI_AUTO) |
3626 | io_hi[i] = 0x400 + io[i]; | |
7597fee3 | 3627 | parport_pc_probe_port(io[i], io_hi[i], |
3aeda9bc | 3628 | irqval[i], dmaval[i], NULL, 0); |
1da177e4 LT |
3629 | } |
3630 | } else | |
3aeda9bc | 3631 | parport_pc_find_ports(irqval[0], dmaval[0]); |
1da177e4 LT |
3632 | |
3633 | return 0; | |
3634 | } | |
3635 | ||
3636 | static void __exit parport_pc_exit(void) | |
3637 | { | |
3638 | if (pci_registered_parport) | |
3aeda9bc | 3639 | pci_unregister_driver(&parport_pc_pci_driver); |
1da177e4 | 3640 | if (pnp_registered_parport) |
3aeda9bc | 3641 | pnp_unregister_driver(&parport_pc_pnp_driver); |
a7d801af | 3642 | platform_driver_unregister(&parport_pc_platform_driver); |
1da177e4 | 3643 | |
1da177e4 LT |
3644 | while (!list_empty(&ports_list)) { |
3645 | struct parport_pc_private *priv; | |
3646 | struct parport *port; | |
3647 | priv = list_entry(ports_list.next, | |
3648 | struct parport_pc_private, list); | |
3649 | port = priv->port; | |
a7d801af JD |
3650 | if (port->dev && port->dev->bus == &platform_bus_type) |
3651 | platform_device_unregister( | |
3652 | to_platform_device(port->dev)); | |
1da177e4 | 3653 | parport_pc_unregister_port(port); |
1da177e4 | 3654 | } |
1da177e4 LT |
3655 | } |
3656 | ||
3657 | MODULE_AUTHOR("Phil Blundell, Tim Waugh, others"); | |
3658 | MODULE_DESCRIPTION("PC-style parallel port driver"); | |
3659 | MODULE_LICENSE("GPL"); | |
3660 | module_init(parport_pc_init) | |
3661 | module_exit(parport_pc_exit) |