Commit | Line | Data |
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1da177e4 LT |
1 | /* Low-level parallel-port routines for 8255-based PC-style hardware. |
2 | * | |
3 | * Authors: Phil Blundell <philb@gnu.org> | |
4 | * Tim Waugh <tim@cyberelk.demon.co.uk> | |
5 | * Jose Renau <renau@acm.org> | |
bdca3f20 | 6 | * David Campbell |
1da177e4 LT |
7 | * Andrea Arcangeli |
8 | * | |
9 | * based on work by Grant Guenther <grant@torque.net> and Phil Blundell. | |
10 | * | |
11 | * Cleaned up include files - Russell King <linux@arm.uk.linux.org> | |
12 | * DMA support - Bert De Jonghe <bert@sophis.be> | |
13 | * Many ECP bugs fixed. Fred Barnes & Jamie Lokier, 1999 | |
14 | * More PCI support now conditional on CONFIG_PCI, 03/2001, Paul G. | |
15 | * Various hacks, Fred Barnes, 04/2001 | |
16 | * Updated probing logic - Adam Belay <ambx1@neo.rr.com> | |
17 | */ | |
18 | ||
19 | /* This driver should work with any hardware that is broadly compatible | |
20 | * with that in the IBM PC. This applies to the majority of integrated | |
21 | * I/O chipsets that are commonly available. The expected register | |
22 | * layout is: | |
23 | * | |
24 | * base+0 data | |
25 | * base+1 status | |
26 | * base+2 control | |
27 | * | |
28 | * In addition, there are some optional registers: | |
29 | * | |
30 | * base+3 EPP address | |
31 | * base+4 EPP data | |
32 | * base+0x400 ECP config A | |
33 | * base+0x401 ECP config B | |
34 | * base+0x402 ECP control | |
35 | * | |
36 | * All registers are 8 bits wide and read/write. If your hardware differs | |
37 | * only in register addresses (eg because your registers are on 32-bit | |
38 | * word boundaries) then you can alter the constants in parport_pc.h to | |
39 | * accommodate this. | |
40 | * | |
41 | * Note that the ECP registers may not start at offset 0x400 for PCI cards, | |
42 | * but rather will start at port->base_hi. | |
43 | */ | |
44 | ||
1da177e4 LT |
45 | #include <linux/module.h> |
46 | #include <linux/init.h> | |
47 | #include <linux/sched.h> | |
48 | #include <linux/delay.h> | |
49 | #include <linux/errno.h> | |
50 | #include <linux/interrupt.h> | |
51 | #include <linux/ioport.h> | |
52 | #include <linux/kernel.h> | |
53 | #include <linux/slab.h> | |
8382d2b9 | 54 | #include <linux/dma-mapping.h> |
1da177e4 LT |
55 | #include <linux/pci.h> |
56 | #include <linux/pnp.h> | |
a7d801af | 57 | #include <linux/platform_device.h> |
1da177e4 LT |
58 | #include <linux/sysctl.h> |
59 | ||
60 | #include <asm/io.h> | |
61 | #include <asm/dma.h> | |
62 | #include <asm/uaccess.h> | |
63 | ||
64 | #include <linux/parport.h> | |
65 | #include <linux/parport_pc.h> | |
66 | #include <linux/via.h> | |
67 | #include <asm/parport.h> | |
68 | ||
69 | #define PARPORT_PC_MAX_PORTS PARPORT_MAX | |
70 | ||
7fbacd52 AV |
71 | #ifdef CONFIG_ISA_DMA_API |
72 | #define HAS_DMA | |
73 | #endif | |
74 | ||
1da177e4 LT |
75 | /* ECR modes */ |
76 | #define ECR_SPP 00 | |
77 | #define ECR_PS2 01 | |
78 | #define ECR_PPF 02 | |
79 | #define ECR_ECP 03 | |
80 | #define ECR_EPP 04 | |
81 | #define ECR_VND 05 | |
82 | #define ECR_TST 06 | |
83 | #define ECR_CNF 07 | |
84 | #define ECR_MODE_MASK 0xe0 | |
85 | #define ECR_WRITE(p,v) frob_econtrol((p),0xff,(v)) | |
86 | ||
87 | #undef DEBUG | |
88 | ||
89 | #ifdef DEBUG | |
90 | #define DPRINTK printk | |
91 | #else | |
92 | #define DPRINTK(stuff...) | |
93 | #endif | |
94 | ||
95 | ||
96 | #define NR_SUPERIOS 3 | |
97 | static struct superio_struct { /* For Super-IO chips autodetection */ | |
98 | int io; | |
99 | int irq; | |
100 | int dma; | |
96766a3c | 101 | } superios[NR_SUPERIOS] = { {0,},}; |
1da177e4 LT |
102 | |
103 | static int user_specified; | |
104 | #if defined(CONFIG_PARPORT_PC_SUPERIO) || \ | |
105 | (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO)) | |
106 | static int verbose_probing; | |
107 | #endif | |
108 | static int pci_registered_parport; | |
109 | static int pnp_registered_parport; | |
110 | ||
111 | /* frob_control, but for ECR */ | |
112 | static void frob_econtrol (struct parport *pb, unsigned char m, | |
113 | unsigned char v) | |
114 | { | |
115 | unsigned char ectr = 0; | |
116 | ||
117 | if (m != 0xff) | |
118 | ectr = inb (ECONTROL (pb)); | |
119 | ||
120 | DPRINTK (KERN_DEBUG "frob_econtrol(%02x,%02x): %02x -> %02x\n", | |
121 | m, v, ectr, (ectr & ~m) ^ v); | |
122 | ||
123 | outb ((ectr & ~m) ^ v, ECONTROL (pb)); | |
124 | } | |
125 | ||
126 | static __inline__ void frob_set_mode (struct parport *p, int mode) | |
127 | { | |
128 | frob_econtrol (p, ECR_MODE_MASK, mode << 5); | |
129 | } | |
130 | ||
131 | #ifdef CONFIG_PARPORT_PC_FIFO | |
132 | /* Safely change the mode bits in the ECR | |
133 | Returns: | |
134 | 0 : Success | |
135 | -EBUSY: Could not drain FIFO in some finite amount of time, | |
136 | mode not changed! | |
137 | */ | |
138 | static int change_mode(struct parport *p, int m) | |
139 | { | |
140 | const struct parport_pc_private *priv = p->physport->private_data; | |
141 | unsigned char oecr; | |
142 | int mode; | |
143 | ||
144 | DPRINTK(KERN_INFO "parport change_mode ECP-ISA to mode 0x%02x\n",m); | |
145 | ||
146 | if (!priv->ecr) { | |
147 | printk (KERN_DEBUG "change_mode: but there's no ECR!\n"); | |
148 | return 0; | |
149 | } | |
150 | ||
151 | /* Bits <7:5> contain the mode. */ | |
152 | oecr = inb (ECONTROL (p)); | |
153 | mode = (oecr >> 5) & 0x7; | |
154 | if (mode == m) return 0; | |
155 | ||
156 | if (mode >= 2 && !(priv->ctr & 0x20)) { | |
157 | /* This mode resets the FIFO, so we may | |
158 | * have to wait for it to drain first. */ | |
159 | unsigned long expire = jiffies + p->physport->cad->timeout; | |
160 | int counter; | |
161 | switch (mode) { | |
162 | case ECR_PPF: /* Parallel Port FIFO mode */ | |
163 | case ECR_ECP: /* ECP Parallel Port mode */ | |
164 | /* Busy wait for 200us */ | |
165 | for (counter = 0; counter < 40; counter++) { | |
166 | if (inb (ECONTROL (p)) & 0x01) | |
167 | break; | |
168 | if (signal_pending (current)) break; | |
169 | udelay (5); | |
170 | } | |
171 | ||
172 | /* Poll slowly. */ | |
173 | while (!(inb (ECONTROL (p)) & 0x01)) { | |
174 | if (time_after_eq (jiffies, expire)) | |
175 | /* The FIFO is stuck. */ | |
176 | return -EBUSY; | |
7b4ccf8d | 177 | schedule_timeout_interruptible(msecs_to_jiffies(10)); |
1da177e4 LT |
178 | if (signal_pending (current)) |
179 | break; | |
180 | } | |
181 | } | |
182 | } | |
183 | ||
184 | if (mode >= 2 && m >= 2) { | |
185 | /* We have to go through mode 001 */ | |
186 | oecr &= ~(7 << 5); | |
187 | oecr |= ECR_PS2 << 5; | |
188 | ECR_WRITE (p, oecr); | |
189 | } | |
190 | ||
191 | /* Set the mode. */ | |
192 | oecr &= ~(7 << 5); | |
193 | oecr |= m << 5; | |
194 | ECR_WRITE (p, oecr); | |
195 | return 0; | |
196 | } | |
197 | ||
198 | #ifdef CONFIG_PARPORT_1284 | |
199 | /* Find FIFO lossage; FIFO is reset */ | |
200 | #if 0 | |
201 | static int get_fifo_residue (struct parport *p) | |
202 | { | |
203 | int residue; | |
204 | int cnfga; | |
205 | const struct parport_pc_private *priv = p->physport->private_data; | |
206 | ||
207 | /* Adjust for the contents of the FIFO. */ | |
208 | for (residue = priv->fifo_depth; ; residue--) { | |
209 | if (inb (ECONTROL (p)) & 0x2) | |
210 | /* Full up. */ | |
211 | break; | |
212 | ||
213 | outb (0, FIFO (p)); | |
214 | } | |
215 | ||
216 | printk (KERN_DEBUG "%s: %d PWords were left in FIFO\n", p->name, | |
217 | residue); | |
218 | ||
219 | /* Reset the FIFO. */ | |
220 | frob_set_mode (p, ECR_PS2); | |
221 | ||
222 | /* Now change to config mode and clean up. FIXME */ | |
223 | frob_set_mode (p, ECR_CNF); | |
224 | cnfga = inb (CONFIGA (p)); | |
225 | printk (KERN_DEBUG "%s: cnfgA contains 0x%02x\n", p->name, cnfga); | |
226 | ||
227 | if (!(cnfga & (1<<2))) { | |
228 | printk (KERN_DEBUG "%s: Accounting for extra byte\n", p->name); | |
229 | residue++; | |
230 | } | |
231 | ||
232 | /* Don't care about partial PWords until support is added for | |
233 | * PWord != 1 byte. */ | |
234 | ||
235 | /* Back to PS2 mode. */ | |
236 | frob_set_mode (p, ECR_PS2); | |
237 | ||
238 | DPRINTK (KERN_DEBUG "*** get_fifo_residue: done residue collecting (ecr = 0x%2.2x)\n", inb (ECONTROL (p))); | |
239 | return residue; | |
240 | } | |
241 | #endif /* 0 */ | |
242 | #endif /* IEEE 1284 support */ | |
243 | #endif /* FIFO support */ | |
244 | ||
245 | /* | |
246 | * Clear TIMEOUT BIT in EPP MODE | |
247 | * | |
248 | * This is also used in SPP detection. | |
249 | */ | |
250 | static int clear_epp_timeout(struct parport *pb) | |
251 | { | |
252 | unsigned char r; | |
253 | ||
254 | if (!(parport_pc_read_status(pb) & 0x01)) | |
255 | return 1; | |
256 | ||
257 | /* To clear timeout some chips require double read */ | |
258 | parport_pc_read_status(pb); | |
259 | r = parport_pc_read_status(pb); | |
260 | outb (r | 0x01, STATUS (pb)); /* Some reset by writing 1 */ | |
261 | outb (r & 0xfe, STATUS (pb)); /* Others by writing 0 */ | |
262 | r = parport_pc_read_status(pb); | |
263 | ||
264 | return !(r & 0x01); | |
265 | } | |
266 | ||
267 | /* | |
268 | * Access functions. | |
269 | * | |
270 | * Most of these aren't static because they may be used by the | |
271 | * parport_xxx_yyy macros. extern __inline__ versions of several | |
272 | * of these are in parport_pc.h. | |
273 | */ | |
274 | ||
7d12e780 | 275 | static irqreturn_t parport_pc_interrupt(int irq, void *dev_id) |
1da177e4 | 276 | { |
7d12e780 | 277 | parport_generic_irq(irq, (struct parport *) dev_id); |
1da177e4 LT |
278 | /* FIXME! Was it really ours? */ |
279 | return IRQ_HANDLED; | |
280 | } | |
281 | ||
282 | static void parport_pc_init_state(struct pardevice *dev, struct parport_state *s) | |
283 | { | |
284 | s->u.pc.ctr = 0xc; | |
285 | if (dev->irq_func && | |
286 | dev->port->irq != PARPORT_IRQ_NONE) | |
287 | /* Set ackIntEn */ | |
288 | s->u.pc.ctr |= 0x10; | |
289 | ||
290 | s->u.pc.ecr = 0x34; /* NetMos chip can cause problems 0x24; | |
291 | * D.Gruszka VScom */ | |
292 | } | |
293 | ||
294 | static void parport_pc_save_state(struct parport *p, struct parport_state *s) | |
295 | { | |
296 | const struct parport_pc_private *priv = p->physport->private_data; | |
297 | s->u.pc.ctr = priv->ctr; | |
298 | if (priv->ecr) | |
299 | s->u.pc.ecr = inb (ECONTROL (p)); | |
300 | } | |
301 | ||
302 | static void parport_pc_restore_state(struct parport *p, struct parport_state *s) | |
303 | { | |
304 | struct parport_pc_private *priv = p->physport->private_data; | |
305 | register unsigned char c = s->u.pc.ctr & priv->ctr_writable; | |
306 | outb (c, CONTROL (p)); | |
307 | priv->ctr = c; | |
308 | if (priv->ecr) | |
309 | ECR_WRITE (p, s->u.pc.ecr); | |
310 | } | |
311 | ||
312 | #ifdef CONFIG_PARPORT_1284 | |
313 | static size_t parport_pc_epp_read_data (struct parport *port, void *buf, | |
314 | size_t length, int flags) | |
315 | { | |
316 | size_t got = 0; | |
317 | ||
318 | if (flags & PARPORT_W91284PIC) { | |
319 | unsigned char status; | |
320 | size_t left = length; | |
321 | ||
322 | /* use knowledge about data lines..: | |
323 | * nFault is 0 if there is at least 1 byte in the Warp's FIFO | |
324 | * pError is 1 if there are 16 bytes in the Warp's FIFO | |
325 | */ | |
326 | status = inb (STATUS (port)); | |
327 | ||
328 | while (!(status & 0x08) && (got < length)) { | |
329 | if ((left >= 16) && (status & 0x20) && !(status & 0x08)) { | |
330 | /* can grab 16 bytes from warp fifo */ | |
331 | if (!((long)buf & 0x03)) { | |
332 | insl (EPPDATA (port), buf, 4); | |
333 | } else { | |
334 | insb (EPPDATA (port), buf, 16); | |
335 | } | |
336 | buf += 16; | |
337 | got += 16; | |
338 | left -= 16; | |
339 | } else { | |
340 | /* grab single byte from the warp fifo */ | |
341 | *((char *)buf) = inb (EPPDATA (port)); | |
342 | buf++; | |
343 | got++; | |
344 | left--; | |
345 | } | |
346 | status = inb (STATUS (port)); | |
347 | if (status & 0x01) { | |
348 | /* EPP timeout should never occur... */ | |
349 | printk (KERN_DEBUG "%s: EPP timeout occurred while talking to " | |
350 | "w91284pic (should not have done)\n", port->name); | |
351 | clear_epp_timeout (port); | |
352 | } | |
353 | } | |
354 | return got; | |
355 | } | |
356 | if ((flags & PARPORT_EPP_FAST) && (length > 1)) { | |
357 | if (!(((long)buf | length) & 0x03)) { | |
358 | insl (EPPDATA (port), buf, (length >> 2)); | |
359 | } else { | |
360 | insb (EPPDATA (port), buf, length); | |
361 | } | |
362 | if (inb (STATUS (port)) & 0x01) { | |
363 | clear_epp_timeout (port); | |
364 | return -EIO; | |
365 | } | |
366 | return length; | |
367 | } | |
368 | for (; got < length; got++) { | |
369 | *((char*)buf) = inb (EPPDATA(port)); | |
370 | buf++; | |
371 | if (inb (STATUS (port)) & 0x01) { | |
372 | /* EPP timeout */ | |
373 | clear_epp_timeout (port); | |
374 | break; | |
375 | } | |
376 | } | |
377 | ||
378 | return got; | |
379 | } | |
380 | ||
381 | static size_t parport_pc_epp_write_data (struct parport *port, const void *buf, | |
382 | size_t length, int flags) | |
383 | { | |
384 | size_t written = 0; | |
385 | ||
386 | if ((flags & PARPORT_EPP_FAST) && (length > 1)) { | |
387 | if (!(((long)buf | length) & 0x03)) { | |
388 | outsl (EPPDATA (port), buf, (length >> 2)); | |
389 | } else { | |
390 | outsb (EPPDATA (port), buf, length); | |
391 | } | |
392 | if (inb (STATUS (port)) & 0x01) { | |
393 | clear_epp_timeout (port); | |
394 | return -EIO; | |
395 | } | |
396 | return length; | |
397 | } | |
398 | for (; written < length; written++) { | |
399 | outb (*((char*)buf), EPPDATA(port)); | |
400 | buf++; | |
401 | if (inb (STATUS(port)) & 0x01) { | |
402 | clear_epp_timeout (port); | |
403 | break; | |
404 | } | |
405 | } | |
406 | ||
407 | return written; | |
408 | } | |
409 | ||
410 | static size_t parport_pc_epp_read_addr (struct parport *port, void *buf, | |
411 | size_t length, int flags) | |
412 | { | |
413 | size_t got = 0; | |
414 | ||
415 | if ((flags & PARPORT_EPP_FAST) && (length > 1)) { | |
416 | insb (EPPADDR (port), buf, length); | |
417 | if (inb (STATUS (port)) & 0x01) { | |
418 | clear_epp_timeout (port); | |
419 | return -EIO; | |
420 | } | |
421 | return length; | |
422 | } | |
423 | for (; got < length; got++) { | |
424 | *((char*)buf) = inb (EPPADDR (port)); | |
425 | buf++; | |
426 | if (inb (STATUS (port)) & 0x01) { | |
427 | clear_epp_timeout (port); | |
428 | break; | |
429 | } | |
430 | } | |
431 | ||
432 | return got; | |
433 | } | |
434 | ||
435 | static size_t parport_pc_epp_write_addr (struct parport *port, | |
436 | const void *buf, size_t length, | |
437 | int flags) | |
438 | { | |
439 | size_t written = 0; | |
440 | ||
441 | if ((flags & PARPORT_EPP_FAST) && (length > 1)) { | |
442 | outsb (EPPADDR (port), buf, length); | |
443 | if (inb (STATUS (port)) & 0x01) { | |
444 | clear_epp_timeout (port); | |
445 | return -EIO; | |
446 | } | |
447 | return length; | |
448 | } | |
449 | for (; written < length; written++) { | |
450 | outb (*((char*)buf), EPPADDR (port)); | |
451 | buf++; | |
452 | if (inb (STATUS (port)) & 0x01) { | |
453 | clear_epp_timeout (port); | |
454 | break; | |
455 | } | |
456 | } | |
457 | ||
458 | return written; | |
459 | } | |
460 | ||
461 | static size_t parport_pc_ecpepp_read_data (struct parport *port, void *buf, | |
462 | size_t length, int flags) | |
463 | { | |
464 | size_t got; | |
465 | ||
466 | frob_set_mode (port, ECR_EPP); | |
467 | parport_pc_data_reverse (port); | |
468 | parport_pc_write_control (port, 0x4); | |
469 | got = parport_pc_epp_read_data (port, buf, length, flags); | |
470 | frob_set_mode (port, ECR_PS2); | |
471 | ||
472 | return got; | |
473 | } | |
474 | ||
475 | static size_t parport_pc_ecpepp_write_data (struct parport *port, | |
476 | const void *buf, size_t length, | |
477 | int flags) | |
478 | { | |
479 | size_t written; | |
480 | ||
481 | frob_set_mode (port, ECR_EPP); | |
482 | parport_pc_write_control (port, 0x4); | |
483 | parport_pc_data_forward (port); | |
484 | written = parport_pc_epp_write_data (port, buf, length, flags); | |
485 | frob_set_mode (port, ECR_PS2); | |
486 | ||
487 | return written; | |
488 | } | |
489 | ||
490 | static size_t parport_pc_ecpepp_read_addr (struct parport *port, void *buf, | |
491 | size_t length, int flags) | |
492 | { | |
493 | size_t got; | |
494 | ||
495 | frob_set_mode (port, ECR_EPP); | |
496 | parport_pc_data_reverse (port); | |
497 | parport_pc_write_control (port, 0x4); | |
498 | got = parport_pc_epp_read_addr (port, buf, length, flags); | |
499 | frob_set_mode (port, ECR_PS2); | |
500 | ||
501 | return got; | |
502 | } | |
503 | ||
504 | static size_t parport_pc_ecpepp_write_addr (struct parport *port, | |
505 | const void *buf, size_t length, | |
506 | int flags) | |
507 | { | |
508 | size_t written; | |
509 | ||
510 | frob_set_mode (port, ECR_EPP); | |
511 | parport_pc_write_control (port, 0x4); | |
512 | parport_pc_data_forward (port); | |
513 | written = parport_pc_epp_write_addr (port, buf, length, flags); | |
514 | frob_set_mode (port, ECR_PS2); | |
515 | ||
516 | return written; | |
517 | } | |
518 | #endif /* IEEE 1284 support */ | |
519 | ||
520 | #ifdef CONFIG_PARPORT_PC_FIFO | |
521 | static size_t parport_pc_fifo_write_block_pio (struct parport *port, | |
522 | const void *buf, size_t length) | |
523 | { | |
524 | int ret = 0; | |
525 | const unsigned char *bufp = buf; | |
526 | size_t left = length; | |
527 | unsigned long expire = jiffies + port->physport->cad->timeout; | |
528 | const int fifo = FIFO (port); | |
529 | int poll_for = 8; /* 80 usecs */ | |
530 | const struct parport_pc_private *priv = port->physport->private_data; | |
531 | const int fifo_depth = priv->fifo_depth; | |
532 | ||
533 | port = port->physport; | |
534 | ||
535 | /* We don't want to be interrupted every character. */ | |
536 | parport_pc_disable_irq (port); | |
537 | /* set nErrIntrEn and serviceIntr */ | |
538 | frob_econtrol (port, (1<<4) | (1<<2), (1<<4) | (1<<2)); | |
539 | ||
540 | /* Forward mode. */ | |
541 | parport_pc_data_forward (port); /* Must be in PS2 mode */ | |
542 | ||
543 | while (left) { | |
544 | unsigned char byte; | |
545 | unsigned char ecrval = inb (ECONTROL (port)); | |
546 | int i = 0; | |
547 | ||
548 | if (need_resched() && time_before (jiffies, expire)) | |
549 | /* Can't yield the port. */ | |
550 | schedule (); | |
551 | ||
552 | /* Anyone else waiting for the port? */ | |
553 | if (port->waithead) { | |
554 | printk (KERN_DEBUG "Somebody wants the port\n"); | |
555 | break; | |
556 | } | |
557 | ||
558 | if (ecrval & 0x02) { | |
559 | /* FIFO is full. Wait for interrupt. */ | |
560 | ||
561 | /* Clear serviceIntr */ | |
562 | ECR_WRITE (port, ecrval & ~(1<<2)); | |
563 | false_alarm: | |
564 | ret = parport_wait_event (port, HZ); | |
565 | if (ret < 0) break; | |
566 | ret = 0; | |
567 | if (!time_before (jiffies, expire)) { | |
568 | /* Timed out. */ | |
569 | printk (KERN_DEBUG "FIFO write timed out\n"); | |
570 | break; | |
571 | } | |
572 | ecrval = inb (ECONTROL (port)); | |
573 | if (!(ecrval & (1<<2))) { | |
574 | if (need_resched() && | |
575 | time_before (jiffies, expire)) | |
576 | schedule (); | |
577 | ||
578 | goto false_alarm; | |
579 | } | |
580 | ||
581 | continue; | |
582 | } | |
583 | ||
584 | /* Can't fail now. */ | |
585 | expire = jiffies + port->cad->timeout; | |
586 | ||
587 | poll: | |
588 | if (signal_pending (current)) | |
589 | break; | |
590 | ||
591 | if (ecrval & 0x01) { | |
592 | /* FIFO is empty. Blast it full. */ | |
593 | const int n = left < fifo_depth ? left : fifo_depth; | |
594 | outsb (fifo, bufp, n); | |
595 | bufp += n; | |
596 | left -= n; | |
597 | ||
598 | /* Adjust the poll time. */ | |
599 | if (i < (poll_for - 2)) poll_for--; | |
600 | continue; | |
601 | } else if (i++ < poll_for) { | |
602 | udelay (10); | |
603 | ecrval = inb (ECONTROL (port)); | |
604 | goto poll; | |
605 | } | |
606 | ||
607 | /* Half-full (call me an optimist) */ | |
608 | byte = *bufp++; | |
609 | outb (byte, fifo); | |
610 | left--; | |
611 | } | |
612 | ||
613 | dump_parport_state ("leave fifo_write_block_pio", port); | |
614 | return length - left; | |
615 | } | |
616 | ||
7fbacd52 | 617 | #ifdef HAS_DMA |
1da177e4 LT |
618 | static size_t parport_pc_fifo_write_block_dma (struct parport *port, |
619 | const void *buf, size_t length) | |
620 | { | |
621 | int ret = 0; | |
622 | unsigned long dmaflag; | |
623 | size_t left = length; | |
624 | const struct parport_pc_private *priv = port->physport->private_data; | |
c15a3837 | 625 | struct device *dev = port->physport->dev; |
1da177e4 LT |
626 | dma_addr_t dma_addr, dma_handle; |
627 | size_t maxlen = 0x10000; /* max 64k per DMA transfer */ | |
628 | unsigned long start = (unsigned long) buf; | |
629 | unsigned long end = (unsigned long) buf + length - 1; | |
630 | ||
631 | dump_parport_state ("enter fifo_write_block_dma", port); | |
632 | if (end < MAX_DMA_ADDRESS) { | |
633 | /* If it would cross a 64k boundary, cap it at the end. */ | |
634 | if ((start ^ end) & ~0xffffUL) | |
635 | maxlen = 0x10000 - (start & 0xffff); | |
636 | ||
c15a3837 DB |
637 | dma_addr = dma_handle = dma_map_single(dev, (void *)buf, length, |
638 | DMA_TO_DEVICE); | |
1da177e4 LT |
639 | } else { |
640 | /* above 16 MB we use a bounce buffer as ISA-DMA is not possible */ | |
641 | maxlen = PAGE_SIZE; /* sizeof(priv->dma_buf) */ | |
642 | dma_addr = priv->dma_handle; | |
643 | dma_handle = 0; | |
644 | } | |
645 | ||
646 | port = port->physport; | |
647 | ||
648 | /* We don't want to be interrupted every character. */ | |
649 | parport_pc_disable_irq (port); | |
650 | /* set nErrIntrEn and serviceIntr */ | |
651 | frob_econtrol (port, (1<<4) | (1<<2), (1<<4) | (1<<2)); | |
652 | ||
653 | /* Forward mode. */ | |
654 | parport_pc_data_forward (port); /* Must be in PS2 mode */ | |
655 | ||
656 | while (left) { | |
657 | unsigned long expire = jiffies + port->physport->cad->timeout; | |
658 | ||
659 | size_t count = left; | |
660 | ||
661 | if (count > maxlen) | |
662 | count = maxlen; | |
663 | ||
664 | if (!dma_handle) /* bounce buffer ! */ | |
665 | memcpy(priv->dma_buf, buf, count); | |
666 | ||
667 | dmaflag = claim_dma_lock(); | |
668 | disable_dma(port->dma); | |
669 | clear_dma_ff(port->dma); | |
670 | set_dma_mode(port->dma, DMA_MODE_WRITE); | |
671 | set_dma_addr(port->dma, dma_addr); | |
672 | set_dma_count(port->dma, count); | |
673 | ||
674 | /* Set DMA mode */ | |
675 | frob_econtrol (port, 1<<3, 1<<3); | |
676 | ||
677 | /* Clear serviceIntr */ | |
678 | frob_econtrol (port, 1<<2, 0); | |
679 | ||
680 | enable_dma(port->dma); | |
681 | release_dma_lock(dmaflag); | |
682 | ||
683 | /* assume DMA will be successful */ | |
684 | left -= count; | |
685 | buf += count; | |
686 | if (dma_handle) dma_addr += count; | |
687 | ||
688 | /* Wait for interrupt. */ | |
689 | false_alarm: | |
690 | ret = parport_wait_event (port, HZ); | |
691 | if (ret < 0) break; | |
692 | ret = 0; | |
693 | if (!time_before (jiffies, expire)) { | |
694 | /* Timed out. */ | |
695 | printk (KERN_DEBUG "DMA write timed out\n"); | |
696 | break; | |
697 | } | |
698 | /* Is serviceIntr set? */ | |
699 | if (!(inb (ECONTROL (port)) & (1<<2))) { | |
700 | cond_resched(); | |
701 | ||
702 | goto false_alarm; | |
703 | } | |
704 | ||
705 | dmaflag = claim_dma_lock(); | |
706 | disable_dma(port->dma); | |
707 | clear_dma_ff(port->dma); | |
708 | count = get_dma_residue(port->dma); | |
709 | release_dma_lock(dmaflag); | |
710 | ||
711 | cond_resched(); /* Can't yield the port. */ | |
712 | ||
713 | /* Anyone else waiting for the port? */ | |
714 | if (port->waithead) { | |
715 | printk (KERN_DEBUG "Somebody wants the port\n"); | |
716 | break; | |
717 | } | |
718 | ||
719 | /* update for possible DMA residue ! */ | |
720 | buf -= count; | |
721 | left += count; | |
722 | if (dma_handle) dma_addr -= count; | |
723 | } | |
724 | ||
725 | /* Maybe got here through break, so adjust for DMA residue! */ | |
726 | dmaflag = claim_dma_lock(); | |
727 | disable_dma(port->dma); | |
728 | clear_dma_ff(port->dma); | |
729 | left += get_dma_residue(port->dma); | |
730 | release_dma_lock(dmaflag); | |
731 | ||
732 | /* Turn off DMA mode */ | |
733 | frob_econtrol (port, 1<<3, 0); | |
c15a3837 | 734 | |
1da177e4 | 735 | if (dma_handle) |
c15a3837 | 736 | dma_unmap_single(dev, dma_handle, length, DMA_TO_DEVICE); |
1da177e4 LT |
737 | |
738 | dump_parport_state ("leave fifo_write_block_dma", port); | |
739 | return length - left; | |
740 | } | |
7fbacd52 AV |
741 | #endif |
742 | ||
743 | static inline size_t parport_pc_fifo_write_block(struct parport *port, | |
744 | const void *buf, size_t length) | |
745 | { | |
746 | #ifdef HAS_DMA | |
747 | if (port->dma != PARPORT_DMA_NONE) | |
748 | return parport_pc_fifo_write_block_dma (port, buf, length); | |
749 | #endif | |
750 | return parport_pc_fifo_write_block_pio (port, buf, length); | |
751 | } | |
1da177e4 LT |
752 | |
753 | /* Parallel Port FIFO mode (ECP chipsets) */ | |
754 | static size_t parport_pc_compat_write_block_pio (struct parport *port, | |
755 | const void *buf, size_t length, | |
756 | int flags) | |
757 | { | |
758 | size_t written; | |
759 | int r; | |
760 | unsigned long expire; | |
761 | const struct parport_pc_private *priv = port->physport->private_data; | |
762 | ||
763 | /* Special case: a timeout of zero means we cannot call schedule(). | |
764 | * Also if O_NONBLOCK is set then use the default implementation. */ | |
765 | if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK) | |
766 | return parport_ieee1284_write_compat (port, buf, | |
767 | length, flags); | |
768 | ||
769 | /* Set up parallel port FIFO mode.*/ | |
770 | parport_pc_data_forward (port); /* Must be in PS2 mode */ | |
771 | parport_pc_frob_control (port, PARPORT_CONTROL_STROBE, 0); | |
772 | r = change_mode (port, ECR_PPF); /* Parallel port FIFO */ | |
773 | if (r) printk (KERN_DEBUG "%s: Warning change_mode ECR_PPF failed\n", port->name); | |
774 | ||
775 | port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA; | |
776 | ||
777 | /* Write the data to the FIFO. */ | |
7fbacd52 | 778 | written = parport_pc_fifo_write_block(port, buf, length); |
1da177e4 LT |
779 | |
780 | /* Finish up. */ | |
781 | /* For some hardware we don't want to touch the mode until | |
782 | * the FIFO is empty, so allow 4 seconds for each position | |
783 | * in the fifo. | |
784 | */ | |
785 | expire = jiffies + (priv->fifo_depth * HZ * 4); | |
786 | do { | |
787 | /* Wait for the FIFO to empty */ | |
788 | r = change_mode (port, ECR_PS2); | |
789 | if (r != -EBUSY) { | |
790 | break; | |
791 | } | |
792 | } while (time_before (jiffies, expire)); | |
793 | if (r == -EBUSY) { | |
794 | ||
795 | printk (KERN_DEBUG "%s: FIFO is stuck\n", port->name); | |
796 | ||
797 | /* Prevent further data transfer. */ | |
798 | frob_set_mode (port, ECR_TST); | |
799 | ||
800 | /* Adjust for the contents of the FIFO. */ | |
801 | for (written -= priv->fifo_depth; ; written++) { | |
802 | if (inb (ECONTROL (port)) & 0x2) { | |
803 | /* Full up. */ | |
804 | break; | |
805 | } | |
806 | outb (0, FIFO (port)); | |
807 | } | |
808 | ||
809 | /* Reset the FIFO and return to PS2 mode. */ | |
810 | frob_set_mode (port, ECR_PS2); | |
811 | } | |
812 | ||
813 | r = parport_wait_peripheral (port, | |
814 | PARPORT_STATUS_BUSY, | |
815 | PARPORT_STATUS_BUSY); | |
816 | if (r) | |
817 | printk (KERN_DEBUG | |
818 | "%s: BUSY timeout (%d) in compat_write_block_pio\n", | |
819 | port->name, r); | |
820 | ||
821 | port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE; | |
822 | ||
823 | return written; | |
824 | } | |
825 | ||
826 | /* ECP */ | |
827 | #ifdef CONFIG_PARPORT_1284 | |
828 | static size_t parport_pc_ecp_write_block_pio (struct parport *port, | |
829 | const void *buf, size_t length, | |
830 | int flags) | |
831 | { | |
832 | size_t written; | |
833 | int r; | |
834 | unsigned long expire; | |
835 | const struct parport_pc_private *priv = port->physport->private_data; | |
836 | ||
837 | /* Special case: a timeout of zero means we cannot call schedule(). | |
838 | * Also if O_NONBLOCK is set then use the default implementation. */ | |
839 | if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK) | |
840 | return parport_ieee1284_ecp_write_data (port, buf, | |
841 | length, flags); | |
842 | ||
843 | /* Switch to forward mode if necessary. */ | |
844 | if (port->physport->ieee1284.phase != IEEE1284_PH_FWD_IDLE) { | |
845 | /* Event 47: Set nInit high. */ | |
846 | parport_frob_control (port, | |
847 | PARPORT_CONTROL_INIT | |
848 | | PARPORT_CONTROL_AUTOFD, | |
849 | PARPORT_CONTROL_INIT | |
850 | | PARPORT_CONTROL_AUTOFD); | |
851 | ||
852 | /* Event 49: PError goes high. */ | |
853 | r = parport_wait_peripheral (port, | |
854 | PARPORT_STATUS_PAPEROUT, | |
855 | PARPORT_STATUS_PAPEROUT); | |
856 | if (r) { | |
857 | printk (KERN_DEBUG "%s: PError timeout (%d) " | |
858 | "in ecp_write_block_pio\n", port->name, r); | |
859 | } | |
860 | } | |
861 | ||
862 | /* Set up ECP parallel port mode.*/ | |
863 | parport_pc_data_forward (port); /* Must be in PS2 mode */ | |
864 | parport_pc_frob_control (port, | |
865 | PARPORT_CONTROL_STROBE | | |
866 | PARPORT_CONTROL_AUTOFD, | |
867 | 0); | |
868 | r = change_mode (port, ECR_ECP); /* ECP FIFO */ | |
869 | if (r) printk (KERN_DEBUG "%s: Warning change_mode ECR_ECP failed\n", port->name); | |
870 | port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA; | |
871 | ||
872 | /* Write the data to the FIFO. */ | |
7fbacd52 | 873 | written = parport_pc_fifo_write_block(port, buf, length); |
1da177e4 LT |
874 | |
875 | /* Finish up. */ | |
876 | /* For some hardware we don't want to touch the mode until | |
877 | * the FIFO is empty, so allow 4 seconds for each position | |
878 | * in the fifo. | |
879 | */ | |
880 | expire = jiffies + (priv->fifo_depth * (HZ * 4)); | |
881 | do { | |
882 | /* Wait for the FIFO to empty */ | |
883 | r = change_mode (port, ECR_PS2); | |
884 | if (r != -EBUSY) { | |
885 | break; | |
886 | } | |
887 | } while (time_before (jiffies, expire)); | |
888 | if (r == -EBUSY) { | |
889 | ||
890 | printk (KERN_DEBUG "%s: FIFO is stuck\n", port->name); | |
891 | ||
892 | /* Prevent further data transfer. */ | |
893 | frob_set_mode (port, ECR_TST); | |
894 | ||
895 | /* Adjust for the contents of the FIFO. */ | |
896 | for (written -= priv->fifo_depth; ; written++) { | |
897 | if (inb (ECONTROL (port)) & 0x2) { | |
898 | /* Full up. */ | |
899 | break; | |
900 | } | |
901 | outb (0, FIFO (port)); | |
902 | } | |
903 | ||
904 | /* Reset the FIFO and return to PS2 mode. */ | |
905 | frob_set_mode (port, ECR_PS2); | |
906 | ||
907 | /* Host transfer recovery. */ | |
908 | parport_pc_data_reverse (port); /* Must be in PS2 mode */ | |
909 | udelay (5); | |
910 | parport_frob_control (port, PARPORT_CONTROL_INIT, 0); | |
911 | r = parport_wait_peripheral (port, PARPORT_STATUS_PAPEROUT, 0); | |
912 | if (r) | |
913 | printk (KERN_DEBUG "%s: PE,1 timeout (%d) " | |
914 | "in ecp_write_block_pio\n", port->name, r); | |
915 | ||
916 | parport_frob_control (port, | |
917 | PARPORT_CONTROL_INIT, | |
918 | PARPORT_CONTROL_INIT); | |
919 | r = parport_wait_peripheral (port, | |
920 | PARPORT_STATUS_PAPEROUT, | |
921 | PARPORT_STATUS_PAPEROUT); | |
922 | if (r) | |
923 | printk (KERN_DEBUG "%s: PE,2 timeout (%d) " | |
924 | "in ecp_write_block_pio\n", port->name, r); | |
925 | } | |
926 | ||
927 | r = parport_wait_peripheral (port, | |
928 | PARPORT_STATUS_BUSY, | |
929 | PARPORT_STATUS_BUSY); | |
930 | if(r) | |
931 | printk (KERN_DEBUG | |
932 | "%s: BUSY timeout (%d) in ecp_write_block_pio\n", | |
933 | port->name, r); | |
934 | ||
935 | port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE; | |
936 | ||
937 | return written; | |
938 | } | |
939 | ||
940 | #if 0 | |
941 | static size_t parport_pc_ecp_read_block_pio (struct parport *port, | |
942 | void *buf, size_t length, | |
943 | int flags) | |
944 | { | |
945 | size_t left = length; | |
946 | size_t fifofull; | |
947 | int r; | |
948 | const int fifo = FIFO(port); | |
949 | const struct parport_pc_private *priv = port->physport->private_data; | |
950 | const int fifo_depth = priv->fifo_depth; | |
951 | char *bufp = buf; | |
952 | ||
953 | port = port->physport; | |
954 | DPRINTK (KERN_DEBUG "parport_pc: parport_pc_ecp_read_block_pio\n"); | |
955 | dump_parport_state ("enter fcn", port); | |
956 | ||
957 | /* Special case: a timeout of zero means we cannot call schedule(). | |
958 | * Also if O_NONBLOCK is set then use the default implementation. */ | |
959 | if (port->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK) | |
960 | return parport_ieee1284_ecp_read_data (port, buf, | |
961 | length, flags); | |
962 | ||
963 | if (port->ieee1284.mode == IEEE1284_MODE_ECPRLE) { | |
964 | /* If the peripheral is allowed to send RLE compressed | |
965 | * data, it is possible for a byte to expand to 128 | |
966 | * bytes in the FIFO. */ | |
967 | fifofull = 128; | |
968 | } else { | |
969 | fifofull = fifo_depth; | |
970 | } | |
971 | ||
972 | /* If the caller wants less than a full FIFO's worth of data, | |
973 | * go through software emulation. Otherwise we may have to throw | |
974 | * away data. */ | |
975 | if (length < fifofull) | |
976 | return parport_ieee1284_ecp_read_data (port, buf, | |
977 | length, flags); | |
978 | ||
979 | if (port->ieee1284.phase != IEEE1284_PH_REV_IDLE) { | |
980 | /* change to reverse-idle phase (must be in forward-idle) */ | |
981 | ||
982 | /* Event 38: Set nAutoFd low (also make sure nStrobe is high) */ | |
983 | parport_frob_control (port, | |
984 | PARPORT_CONTROL_AUTOFD | |
985 | | PARPORT_CONTROL_STROBE, | |
986 | PARPORT_CONTROL_AUTOFD); | |
987 | parport_pc_data_reverse (port); /* Must be in PS2 mode */ | |
988 | udelay (5); | |
989 | /* Event 39: Set nInit low to initiate bus reversal */ | |
990 | parport_frob_control (port, | |
991 | PARPORT_CONTROL_INIT, | |
992 | 0); | |
993 | /* Event 40: Wait for nAckReverse (PError) to go low */ | |
994 | r = parport_wait_peripheral (port, PARPORT_STATUS_PAPEROUT, 0); | |
995 | if (r) { | |
996 | printk (KERN_DEBUG "%s: PE timeout Event 40 (%d) " | |
997 | "in ecp_read_block_pio\n", port->name, r); | |
998 | return 0; | |
999 | } | |
1000 | } | |
1001 | ||
1002 | /* Set up ECP FIFO mode.*/ | |
1003 | /* parport_pc_frob_control (port, | |
1004 | PARPORT_CONTROL_STROBE | | |
1005 | PARPORT_CONTROL_AUTOFD, | |
1006 | PARPORT_CONTROL_AUTOFD); */ | |
1007 | r = change_mode (port, ECR_ECP); /* ECP FIFO */ | |
1008 | if (r) printk (KERN_DEBUG "%s: Warning change_mode ECR_ECP failed\n", port->name); | |
1009 | ||
1010 | port->ieee1284.phase = IEEE1284_PH_REV_DATA; | |
1011 | ||
1012 | /* the first byte must be collected manually */ | |
1013 | dump_parport_state ("pre 43", port); | |
1014 | /* Event 43: Wait for nAck to go low */ | |
1015 | r = parport_wait_peripheral (port, PARPORT_STATUS_ACK, 0); | |
1016 | if (r) { | |
1017 | /* timed out while reading -- no data */ | |
1018 | printk (KERN_DEBUG "PIO read timed out (initial byte)\n"); | |
1019 | goto out_no_data; | |
1020 | } | |
1021 | /* read byte */ | |
1022 | *bufp++ = inb (DATA (port)); | |
1023 | left--; | |
1024 | dump_parport_state ("43-44", port); | |
1025 | /* Event 44: nAutoFd (HostAck) goes high to acknowledge */ | |
1026 | parport_pc_frob_control (port, | |
1027 | PARPORT_CONTROL_AUTOFD, | |
1028 | 0); | |
1029 | dump_parport_state ("pre 45", port); | |
1030 | /* Event 45: Wait for nAck to go high */ | |
1031 | /* r = parport_wait_peripheral (port, PARPORT_STATUS_ACK, PARPORT_STATUS_ACK); */ | |
1032 | dump_parport_state ("post 45", port); | |
1033 | r = 0; | |
1034 | if (r) { | |
1035 | /* timed out while waiting for peripheral to respond to ack */ | |
1036 | printk (KERN_DEBUG "ECP PIO read timed out (waiting for nAck)\n"); | |
1037 | ||
1038 | /* keep hold of the byte we've got already */ | |
1039 | goto out_no_data; | |
1040 | } | |
1041 | /* Event 46: nAutoFd (HostAck) goes low to accept more data */ | |
1042 | parport_pc_frob_control (port, | |
1043 | PARPORT_CONTROL_AUTOFD, | |
1044 | PARPORT_CONTROL_AUTOFD); | |
1045 | ||
1046 | ||
1047 | dump_parport_state ("rev idle", port); | |
1048 | /* Do the transfer. */ | |
1049 | while (left > fifofull) { | |
1050 | int ret; | |
1051 | unsigned long expire = jiffies + port->cad->timeout; | |
1052 | unsigned char ecrval = inb (ECONTROL (port)); | |
1053 | ||
1054 | if (need_resched() && time_before (jiffies, expire)) | |
1055 | /* Can't yield the port. */ | |
1056 | schedule (); | |
1057 | ||
1058 | /* At this point, the FIFO may already be full. In | |
1059 | * that case ECP is already holding back the | |
1060 | * peripheral (assuming proper design) with a delayed | |
1061 | * handshake. Work fast to avoid a peripheral | |
1062 | * timeout. */ | |
1063 | ||
1064 | if (ecrval & 0x01) { | |
1065 | /* FIFO is empty. Wait for interrupt. */ | |
1066 | dump_parport_state ("FIFO empty", port); | |
1067 | ||
1068 | /* Anyone else waiting for the port? */ | |
1069 | if (port->waithead) { | |
1070 | printk (KERN_DEBUG "Somebody wants the port\n"); | |
1071 | break; | |
1072 | } | |
1073 | ||
1074 | /* Clear serviceIntr */ | |
1075 | ECR_WRITE (port, ecrval & ~(1<<2)); | |
1076 | false_alarm: | |
1077 | dump_parport_state ("waiting", port); | |
1078 | ret = parport_wait_event (port, HZ); | |
1079 | DPRINTK (KERN_DEBUG "parport_wait_event returned %d\n", ret); | |
1080 | if (ret < 0) | |
1081 | break; | |
1082 | ret = 0; | |
1083 | if (!time_before (jiffies, expire)) { | |
1084 | /* Timed out. */ | |
1085 | dump_parport_state ("timeout", port); | |
1086 | printk (KERN_DEBUG "PIO read timed out\n"); | |
1087 | break; | |
1088 | } | |
1089 | ecrval = inb (ECONTROL (port)); | |
1090 | if (!(ecrval & (1<<2))) { | |
1091 | if (need_resched() && | |
1092 | time_before (jiffies, expire)) { | |
1093 | schedule (); | |
1094 | } | |
1095 | goto false_alarm; | |
1096 | } | |
1097 | ||
1098 | /* Depending on how the FIFO threshold was | |
1099 | * set, how long interrupt service took, and | |
1100 | * how fast the peripheral is, we might be | |
1101 | * lucky and have a just filled FIFO. */ | |
1102 | continue; | |
1103 | } | |
1104 | ||
1105 | if (ecrval & 0x02) { | |
1106 | /* FIFO is full. */ | |
1107 | dump_parport_state ("FIFO full", port); | |
1108 | insb (fifo, bufp, fifo_depth); | |
1109 | bufp += fifo_depth; | |
1110 | left -= fifo_depth; | |
1111 | continue; | |
1112 | } | |
1113 | ||
1114 | DPRINTK (KERN_DEBUG "*** ecp_read_block_pio: reading one byte from the FIFO\n"); | |
1115 | ||
1116 | /* FIFO not filled. We will cycle this loop for a while | |
1117 | * and either the peripheral will fill it faster, | |
1118 | * tripping a fast empty with insb, or we empty it. */ | |
1119 | *bufp++ = inb (fifo); | |
1120 | left--; | |
1121 | } | |
1122 | ||
1123 | /* scoop up anything left in the FIFO */ | |
1124 | while (left && !(inb (ECONTROL (port) & 0x01))) { | |
1125 | *bufp++ = inb (fifo); | |
1126 | left--; | |
1127 | } | |
1128 | ||
1129 | port->ieee1284.phase = IEEE1284_PH_REV_IDLE; | |
1130 | dump_parport_state ("rev idle2", port); | |
1131 | ||
1132 | out_no_data: | |
1133 | ||
1134 | /* Go to forward idle mode to shut the peripheral up (event 47). */ | |
1135 | parport_frob_control (port, PARPORT_CONTROL_INIT, PARPORT_CONTROL_INIT); | |
1136 | ||
1137 | /* event 49: PError goes high */ | |
1138 | r = parport_wait_peripheral (port, | |
1139 | PARPORT_STATUS_PAPEROUT, | |
1140 | PARPORT_STATUS_PAPEROUT); | |
1141 | if (r) { | |
1142 | printk (KERN_DEBUG | |
1143 | "%s: PE timeout FWDIDLE (%d) in ecp_read_block_pio\n", | |
1144 | port->name, r); | |
1145 | } | |
1146 | ||
1147 | port->ieee1284.phase = IEEE1284_PH_FWD_IDLE; | |
1148 | ||
1149 | /* Finish up. */ | |
1150 | { | |
1151 | int lost = get_fifo_residue (port); | |
1152 | if (lost) | |
1153 | /* Shouldn't happen with compliant peripherals. */ | |
1154 | printk (KERN_DEBUG "%s: DATA LOSS (%d bytes)!\n", | |
1155 | port->name, lost); | |
1156 | } | |
1157 | ||
1158 | dump_parport_state ("fwd idle", port); | |
1159 | return length - left; | |
1160 | } | |
1161 | #endif /* 0 */ | |
1162 | #endif /* IEEE 1284 support */ | |
1163 | #endif /* Allowed to use FIFO/DMA */ | |
1164 | ||
1165 | ||
1166 | /* | |
1167 | * ****************************************** | |
1168 | * INITIALISATION AND MODULE STUFF BELOW HERE | |
1169 | * ****************************************** | |
1170 | */ | |
1171 | ||
1172 | /* GCC is not inlining extern inline function later overwriten to non-inline, | |
1173 | so we use outlined_ variants here. */ | |
a6767b7c | 1174 | static const struct parport_operations parport_pc_ops = |
1da177e4 LT |
1175 | { |
1176 | .write_data = parport_pc_write_data, | |
1177 | .read_data = parport_pc_read_data, | |
1178 | ||
1179 | .write_control = parport_pc_write_control, | |
1180 | .read_control = parport_pc_read_control, | |
1181 | .frob_control = parport_pc_frob_control, | |
1182 | ||
1183 | .read_status = parport_pc_read_status, | |
1184 | ||
1185 | .enable_irq = parport_pc_enable_irq, | |
1186 | .disable_irq = parport_pc_disable_irq, | |
1187 | ||
1188 | .data_forward = parport_pc_data_forward, | |
1189 | .data_reverse = parport_pc_data_reverse, | |
1190 | ||
1191 | .init_state = parport_pc_init_state, | |
1192 | .save_state = parport_pc_save_state, | |
1193 | .restore_state = parport_pc_restore_state, | |
1194 | ||
1195 | .epp_write_data = parport_ieee1284_epp_write_data, | |
1196 | .epp_read_data = parport_ieee1284_epp_read_data, | |
1197 | .epp_write_addr = parport_ieee1284_epp_write_addr, | |
1198 | .epp_read_addr = parport_ieee1284_epp_read_addr, | |
1199 | ||
1200 | .ecp_write_data = parport_ieee1284_ecp_write_data, | |
1201 | .ecp_read_data = parport_ieee1284_ecp_read_data, | |
1202 | .ecp_write_addr = parport_ieee1284_ecp_write_addr, | |
1203 | ||
1204 | .compat_write_data = parport_ieee1284_write_compat, | |
1205 | .nibble_read_data = parport_ieee1284_read_nibble, | |
1206 | .byte_read_data = parport_ieee1284_read_byte, | |
1207 | ||
1208 | .owner = THIS_MODULE, | |
1209 | }; | |
1210 | ||
1211 | #ifdef CONFIG_PARPORT_PC_SUPERIO | |
1212 | /* Super-IO chipset detection, Winbond, SMSC */ | |
1213 | static void __devinit show_parconfig_smsc37c669(int io, int key) | |
1214 | { | |
1215 | int cr1,cr4,cra,cr23,cr26,cr27,i=0; | |
a6767b7c MK |
1216 | static const char *const modes[]={ |
1217 | "SPP and Bidirectional (PS/2)", | |
1218 | "EPP and SPP", | |
1219 | "ECP", | |
1220 | "ECP and EPP" }; | |
1da177e4 LT |
1221 | |
1222 | outb(key,io); | |
1223 | outb(key,io); | |
1224 | outb(1,io); | |
1225 | cr1=inb(io+1); | |
1226 | outb(4,io); | |
1227 | cr4=inb(io+1); | |
1228 | outb(0x0a,io); | |
1229 | cra=inb(io+1); | |
1230 | outb(0x23,io); | |
1231 | cr23=inb(io+1); | |
1232 | outb(0x26,io); | |
1233 | cr26=inb(io+1); | |
1234 | outb(0x27,io); | |
1235 | cr27=inb(io+1); | |
1236 | outb(0xaa,io); | |
1237 | ||
1238 | if (verbose_probing) { | |
1239 | printk (KERN_INFO "SMSC 37c669 LPT Config: cr_1=0x%02x, 4=0x%02x, " | |
1240 | "A=0x%2x, 23=0x%02x, 26=0x%02x, 27=0x%02x\n", | |
1241 | cr1,cr4,cra,cr23,cr26,cr27); | |
1242 | ||
1243 | /* The documentation calls DMA and IRQ-Lines by letters, so | |
1244 | the board maker can/will wire them | |
1245 | appropriately/randomly... G=reserved H=IDE-irq, */ | |
1246 | printk (KERN_INFO "SMSC LPT Config: io=0x%04x, irq=%c, dma=%c, " | |
1247 | "fifo threshold=%d\n", cr23*4, | |
1248 | (cr27 &0x0f) ? 'A'-1+(cr27 &0x0f): '-', | |
1249 | (cr26 &0x0f) ? 'A'-1+(cr26 &0x0f): '-', cra & 0x0f); | |
1250 | printk(KERN_INFO "SMSC LPT Config: enabled=%s power=%s\n", | |
1251 | (cr23*4 >=0x100) ?"yes":"no", (cr1 & 4) ? "yes" : "no"); | |
1252 | printk(KERN_INFO "SMSC LPT Config: Port mode=%s, EPP version =%s\n", | |
1253 | (cr1 & 0x08 ) ? "Standard mode only (SPP)" : modes[cr4 & 0x03], | |
1254 | (cr4 & 0x40) ? "1.7" : "1.9"); | |
1255 | } | |
1256 | ||
1257 | /* Heuristics ! BIOS setup for this mainboard device limits | |
1258 | the choices to standard settings, i.e. io-address and IRQ | |
1259 | are related, however DMA can be 1 or 3, assume DMA_A=DMA1, | |
1260 | DMA_C=DMA3 (this is true e.g. for TYAN 1564D Tomcat IV) */ | |
1261 | if(cr23*4 >=0x100) { /* if active */ | |
1262 | while((superios[i].io!= 0) && (i<NR_SUPERIOS)) | |
1263 | i++; | |
1264 | if(i==NR_SUPERIOS) | |
1265 | printk(KERN_INFO "Super-IO: too many chips!\n"); | |
1266 | else { | |
1267 | int d; | |
1268 | switch (cr23*4) { | |
1269 | case 0x3bc: | |
1270 | superios[i].io = 0x3bc; | |
1271 | superios[i].irq = 7; | |
1272 | break; | |
1273 | case 0x378: | |
1274 | superios[i].io = 0x378; | |
1275 | superios[i].irq = 7; | |
1276 | break; | |
1277 | case 0x278: | |
1278 | superios[i].io = 0x278; | |
1279 | superios[i].irq = 5; | |
1280 | } | |
1281 | d=(cr26 &0x0f); | |
1282 | if((d==1) || (d==3)) | |
1283 | superios[i].dma= d; | |
1284 | else | |
1285 | superios[i].dma= PARPORT_DMA_NONE; | |
1286 | } | |
1287 | } | |
1288 | } | |
1289 | ||
1290 | ||
1291 | static void __devinit show_parconfig_winbond(int io, int key) | |
1292 | { | |
1293 | int cr30,cr60,cr61,cr70,cr74,crf0,i=0; | |
a6767b7c | 1294 | static const char *const modes[] = { |
1da177e4 LT |
1295 | "Standard (SPP) and Bidirectional(PS/2)", /* 0 */ |
1296 | "EPP-1.9 and SPP", | |
1297 | "ECP", | |
1298 | "ECP and EPP-1.9", | |
1299 | "Standard (SPP)", | |
1300 | "EPP-1.7 and SPP", /* 5 */ | |
1301 | "undefined!", | |
1302 | "ECP and EPP-1.7" }; | |
a6767b7c MK |
1303 | static char *const irqtypes[] = { |
1304 | "pulsed low, high-Z", | |
1305 | "follows nACK" }; | |
1da177e4 LT |
1306 | |
1307 | /* The registers are called compatible-PnP because the | |
1308 | register layout is modelled after ISA-PnP, the access | |
1309 | method is just another ... */ | |
1310 | outb(key,io); | |
1311 | outb(key,io); | |
1312 | outb(0x07,io); /* Register 7: Select Logical Device */ | |
1313 | outb(0x01,io+1); /* LD1 is Parallel Port */ | |
1314 | outb(0x30,io); | |
1315 | cr30=inb(io+1); | |
1316 | outb(0x60,io); | |
1317 | cr60=inb(io+1); | |
1318 | outb(0x61,io); | |
1319 | cr61=inb(io+1); | |
1320 | outb(0x70,io); | |
1321 | cr70=inb(io+1); | |
1322 | outb(0x74,io); | |
1323 | cr74=inb(io+1); | |
1324 | outb(0xf0,io); | |
1325 | crf0=inb(io+1); | |
1326 | outb(0xaa,io); | |
1327 | ||
1328 | if (verbose_probing) { | |
1329 | printk(KERN_INFO "Winbond LPT Config: cr_30=%02x 60,61=%02x%02x " | |
1330 | "70=%02x 74=%02x, f0=%02x\n", cr30,cr60,cr61,cr70,cr74,crf0); | |
1331 | printk(KERN_INFO "Winbond LPT Config: active=%s, io=0x%02x%02x irq=%d, ", | |
1332 | (cr30 & 0x01) ? "yes":"no", cr60,cr61,cr70&0x0f ); | |
1333 | if ((cr74 & 0x07) > 3) | |
1334 | printk("dma=none\n"); | |
1335 | else | |
1336 | printk("dma=%d\n",cr74 & 0x07); | |
1337 | printk(KERN_INFO "Winbond LPT Config: irqtype=%s, ECP fifo threshold=%d\n", | |
1338 | irqtypes[crf0>>7], (crf0>>3)&0x0f); | |
1339 | printk(KERN_INFO "Winbond LPT Config: Port mode=%s\n", modes[crf0 & 0x07]); | |
1340 | } | |
1341 | ||
1342 | if(cr30 & 0x01) { /* the settings can be interrogated later ... */ | |
1343 | while((superios[i].io!= 0) && (i<NR_SUPERIOS)) | |
1344 | i++; | |
1345 | if(i==NR_SUPERIOS) | |
1346 | printk(KERN_INFO "Super-IO: too many chips!\n"); | |
1347 | else { | |
1348 | superios[i].io = (cr60<<8)|cr61; | |
1349 | superios[i].irq = cr70&0x0f; | |
1350 | superios[i].dma = (((cr74 & 0x07) > 3) ? | |
1351 | PARPORT_DMA_NONE : (cr74 & 0x07)); | |
1352 | } | |
1353 | } | |
1354 | } | |
1355 | ||
1356 | static void __devinit decode_winbond(int efer, int key, int devid, int devrev, int oldid) | |
1357 | { | |
1358 | const char *type = "unknown"; | |
1359 | int id,progif=2; | |
1360 | ||
1361 | if (devid == devrev) | |
1362 | /* simple heuristics, we happened to read some | |
1363 | non-winbond register */ | |
1364 | return; | |
1365 | ||
1366 | id=(devid<<8) | devrev; | |
1367 | ||
1368 | /* Values are from public data sheets pdf files, I can just | |
1369 | confirm 83977TF is correct :-) */ | |
1370 | if (id == 0x9771) type="83977F/AF"; | |
1371 | else if (id == 0x9773) type="83977TF / SMSC 97w33x/97w34x"; | |
1372 | else if (id == 0x9774) type="83977ATF"; | |
1373 | else if ((id & ~0x0f) == 0x5270) type="83977CTF / SMSC 97w36x"; | |
1374 | else if ((id & ~0x0f) == 0x52f0) type="83977EF / SMSC 97w35x"; | |
1375 | else if ((id & ~0x0f) == 0x5210) type="83627"; | |
1376 | else if ((id & ~0x0f) == 0x6010) type="83697HF"; | |
1377 | else if ((oldid &0x0f ) == 0x0a) { type="83877F"; progif=1;} | |
1378 | else if ((oldid &0x0f ) == 0x0b) { type="83877AF"; progif=1;} | |
1379 | else if ((oldid &0x0f ) == 0x0c) { type="83877TF"; progif=1;} | |
1380 | else if ((oldid &0x0f ) == 0x0d) { type="83877ATF"; progif=1;} | |
1381 | else progif=0; | |
1382 | ||
1383 | if (verbose_probing) | |
1384 | printk(KERN_INFO "Winbond chip at EFER=0x%x key=0x%02x " | |
1385 | "devid=%02x devrev=%02x oldid=%02x type=%s\n", | |
1386 | efer, key, devid, devrev, oldid, type); | |
1387 | ||
1388 | if (progif == 2) | |
1389 | show_parconfig_winbond(efer,key); | |
1390 | } | |
1391 | ||
1392 | static void __devinit decode_smsc(int efer, int key, int devid, int devrev) | |
1393 | { | |
1394 | const char *type = "unknown"; | |
1395 | void (*func)(int io, int key); | |
1396 | int id; | |
1397 | ||
1398 | if (devid == devrev) | |
1399 | /* simple heuristics, we happened to read some | |
1400 | non-smsc register */ | |
1401 | return; | |
1402 | ||
1403 | func=NULL; | |
1404 | id=(devid<<8) | devrev; | |
1405 | ||
1406 | if (id==0x0302) {type="37c669"; func=show_parconfig_smsc37c669;} | |
1407 | else if (id==0x6582) type="37c665IR"; | |
1408 | else if (devid==0x65) type="37c665GT"; | |
1409 | else if (devid==0x66) type="37c666GT"; | |
1410 | ||
1411 | if (verbose_probing) | |
1412 | printk(KERN_INFO "SMSC chip at EFER=0x%x " | |
1413 | "key=0x%02x devid=%02x devrev=%02x type=%s\n", | |
1414 | efer, key, devid, devrev, type); | |
1415 | ||
1416 | if (func) | |
1417 | func(efer,key); | |
1418 | } | |
1419 | ||
1420 | ||
1421 | static void __devinit winbond_check(int io, int key) | |
1422 | { | |
1423 | int devid,devrev,oldid,x_devid,x_devrev,x_oldid; | |
1424 | ||
1425 | if (!request_region(io, 3, __FUNCTION__)) | |
1426 | return; | |
1427 | ||
1428 | /* First probe without key */ | |
1429 | outb(0x20,io); | |
1430 | x_devid=inb(io+1); | |
1431 | outb(0x21,io); | |
1432 | x_devrev=inb(io+1); | |
1433 | outb(0x09,io); | |
1434 | x_oldid=inb(io+1); | |
1435 | ||
1436 | outb(key,io); | |
1437 | outb(key,io); /* Write Magic Sequence to EFER, extended | |
1438 | funtion enable register */ | |
1439 | outb(0x20,io); /* Write EFIR, extended function index register */ | |
1440 | devid=inb(io+1); /* Read EFDR, extended function data register */ | |
1441 | outb(0x21,io); | |
1442 | devrev=inb(io+1); | |
1443 | outb(0x09,io); | |
1444 | oldid=inb(io+1); | |
1445 | outb(0xaa,io); /* Magic Seal */ | |
1446 | ||
1447 | if ((x_devid == devid) && (x_devrev == devrev) && (x_oldid == oldid)) | |
1448 | goto out; /* protection against false positives */ | |
1449 | ||
1450 | decode_winbond(io,key,devid,devrev,oldid); | |
1451 | out: | |
1452 | release_region(io, 3); | |
1453 | } | |
1454 | ||
1455 | static void __devinit winbond_check2(int io,int key) | |
1456 | { | |
1457 | int devid,devrev,oldid,x_devid,x_devrev,x_oldid; | |
1458 | ||
1459 | if (!request_region(io, 3, __FUNCTION__)) | |
1460 | return; | |
1461 | ||
1462 | /* First probe without the key */ | |
1463 | outb(0x20,io+2); | |
1464 | x_devid=inb(io+2); | |
1465 | outb(0x21,io+1); | |
1466 | x_devrev=inb(io+2); | |
1467 | outb(0x09,io+1); | |
1468 | x_oldid=inb(io+2); | |
1469 | ||
1470 | outb(key,io); /* Write Magic Byte to EFER, extended | |
1471 | funtion enable register */ | |
1472 | outb(0x20,io+2); /* Write EFIR, extended function index register */ | |
1473 | devid=inb(io+2); /* Read EFDR, extended function data register */ | |
1474 | outb(0x21,io+1); | |
1475 | devrev=inb(io+2); | |
1476 | outb(0x09,io+1); | |
1477 | oldid=inb(io+2); | |
1478 | outb(0xaa,io); /* Magic Seal */ | |
1479 | ||
1480 | if ((x_devid == devid) && (x_devrev == devrev) && (x_oldid == oldid)) | |
1481 | goto out; /* protection against false positives */ | |
1482 | ||
1483 | decode_winbond(io,key,devid,devrev,oldid); | |
1484 | out: | |
1485 | release_region(io, 3); | |
1486 | } | |
1487 | ||
1488 | static void __devinit smsc_check(int io, int key) | |
1489 | { | |
1490 | int id,rev,oldid,oldrev,x_id,x_rev,x_oldid,x_oldrev; | |
1491 | ||
1492 | if (!request_region(io, 3, __FUNCTION__)) | |
1493 | return; | |
1494 | ||
1495 | /* First probe without the key */ | |
1496 | outb(0x0d,io); | |
1497 | x_oldid=inb(io+1); | |
1498 | outb(0x0e,io); | |
1499 | x_oldrev=inb(io+1); | |
1500 | outb(0x20,io); | |
1501 | x_id=inb(io+1); | |
1502 | outb(0x21,io); | |
1503 | x_rev=inb(io+1); | |
1504 | ||
1505 | outb(key,io); | |
1506 | outb(key,io); /* Write Magic Sequence to EFER, extended | |
1507 | funtion enable register */ | |
1508 | outb(0x0d,io); /* Write EFIR, extended function index register */ | |
1509 | oldid=inb(io+1); /* Read EFDR, extended function data register */ | |
1510 | outb(0x0e,io); | |
1511 | oldrev=inb(io+1); | |
1512 | outb(0x20,io); | |
1513 | id=inb(io+1); | |
1514 | outb(0x21,io); | |
1515 | rev=inb(io+1); | |
1516 | outb(0xaa,io); /* Magic Seal */ | |
1517 | ||
1518 | if ((x_id == id) && (x_oldrev == oldrev) && | |
1519 | (x_oldid == oldid) && (x_rev == rev)) | |
1520 | goto out; /* protection against false positives */ | |
1521 | ||
1522 | decode_smsc(io,key,oldid,oldrev); | |
1523 | out: | |
1524 | release_region(io, 3); | |
1525 | } | |
1526 | ||
1527 | ||
1528 | static void __devinit detect_and_report_winbond (void) | |
1529 | { | |
1530 | if (verbose_probing) | |
1531 | printk(KERN_DEBUG "Winbond Super-IO detection, now testing ports 3F0,370,250,4E,2E ...\n"); | |
1532 | winbond_check(0x3f0,0x87); | |
1533 | winbond_check(0x370,0x87); | |
1534 | winbond_check(0x2e ,0x87); | |
1535 | winbond_check(0x4e ,0x87); | |
1536 | winbond_check(0x3f0,0x86); | |
1537 | winbond_check2(0x250,0x88); | |
1538 | winbond_check2(0x250,0x89); | |
1539 | } | |
1540 | ||
1541 | static void __devinit detect_and_report_smsc (void) | |
1542 | { | |
1543 | if (verbose_probing) | |
1544 | printk(KERN_DEBUG "SMSC Super-IO detection, now testing Ports 2F0, 370 ...\n"); | |
1545 | smsc_check(0x3f0,0x55); | |
1546 | smsc_check(0x370,0x55); | |
1547 | smsc_check(0x3f0,0x44); | |
1548 | smsc_check(0x370,0x44); | |
1549 | } | |
1550 | #endif /* CONFIG_PARPORT_PC_SUPERIO */ | |
1551 | ||
0bb92e6c | 1552 | static int get_superio_dma (struct parport *p) |
1da177e4 LT |
1553 | { |
1554 | int i=0; | |
1555 | while( (superios[i].io != p->base) && (i<NR_SUPERIOS)) | |
1556 | i++; | |
1557 | if (i!=NR_SUPERIOS) | |
1558 | return superios[i].dma; | |
1559 | return PARPORT_DMA_NONE; | |
1560 | } | |
1561 | ||
96766a3c | 1562 | static int get_superio_irq (struct parport *p) |
1da177e4 LT |
1563 | { |
1564 | int i=0; | |
1565 | while( (superios[i].io != p->base) && (i<NR_SUPERIOS)) | |
1566 | i++; | |
1567 | if (i!=NR_SUPERIOS) | |
1568 | return superios[i].irq; | |
1569 | return PARPORT_IRQ_NONE; | |
1570 | } | |
1571 | ||
1572 | ||
1573 | /* --- Mode detection ------------------------------------- */ | |
1574 | ||
1575 | /* | |
1576 | * Checks for port existence, all ports support SPP MODE | |
1577 | * Returns: | |
1578 | * 0 : No parallel port at this address | |
1579 | * PARPORT_MODE_PCSPP : SPP port detected | |
1580 | * (if the user specified an ioport himself, | |
1581 | * this shall always be the case!) | |
1582 | * | |
1583 | */ | |
96766a3c | 1584 | static int parport_SPP_supported(struct parport *pb) |
1da177e4 LT |
1585 | { |
1586 | unsigned char r, w; | |
1587 | ||
1588 | /* | |
1589 | * first clear an eventually pending EPP timeout | |
1590 | * I (sailer@ife.ee.ethz.ch) have an SMSC chipset | |
1591 | * that does not even respond to SPP cycles if an EPP | |
1592 | * timeout is pending | |
1593 | */ | |
1594 | clear_epp_timeout(pb); | |
1595 | ||
1596 | /* Do a simple read-write test to make sure the port exists. */ | |
1597 | w = 0xc; | |
1598 | outb (w, CONTROL (pb)); | |
1599 | ||
1600 | /* Is there a control register that we can read from? Some | |
1601 | * ports don't allow reads, so read_control just returns a | |
1602 | * software copy. Some ports _do_ allow reads, so bypass the | |
1603 | * software copy here. In addition, some bits aren't | |
1604 | * writable. */ | |
1605 | r = inb (CONTROL (pb)); | |
1606 | if ((r & 0xf) == w) { | |
1607 | w = 0xe; | |
1608 | outb (w, CONTROL (pb)); | |
1609 | r = inb (CONTROL (pb)); | |
1610 | outb (0xc, CONTROL (pb)); | |
1611 | if ((r & 0xf) == w) | |
1612 | return PARPORT_MODE_PCSPP; | |
1613 | } | |
1614 | ||
1615 | if (user_specified) | |
1616 | /* That didn't work, but the user thinks there's a | |
1617 | * port here. */ | |
1618 | printk (KERN_INFO "parport 0x%lx (WARNING): CTR: " | |
1619 | "wrote 0x%02x, read 0x%02x\n", pb->base, w, r); | |
1620 | ||
1621 | /* Try the data register. The data lines aren't tri-stated at | |
1622 | * this stage, so we expect back what we wrote. */ | |
1623 | w = 0xaa; | |
1624 | parport_pc_write_data (pb, w); | |
1625 | r = parport_pc_read_data (pb); | |
1626 | if (r == w) { | |
1627 | w = 0x55; | |
1628 | parport_pc_write_data (pb, w); | |
1629 | r = parport_pc_read_data (pb); | |
1630 | if (r == w) | |
1631 | return PARPORT_MODE_PCSPP; | |
1632 | } | |
1633 | ||
1634 | if (user_specified) { | |
1635 | /* Didn't work, but the user is convinced this is the | |
1636 | * place. */ | |
1637 | printk (KERN_INFO "parport 0x%lx (WARNING): DATA: " | |
1638 | "wrote 0x%02x, read 0x%02x\n", pb->base, w, r); | |
1639 | printk (KERN_INFO "parport 0x%lx: You gave this address, " | |
1640 | "but there is probably no parallel port there!\n", | |
1641 | pb->base); | |
1642 | } | |
1643 | ||
1644 | /* It's possible that we can't read the control register or | |
1645 | * the data register. In that case just believe the user. */ | |
1646 | if (user_specified) | |
1647 | return PARPORT_MODE_PCSPP; | |
1648 | ||
1649 | return 0; | |
1650 | } | |
1651 | ||
1652 | /* Check for ECR | |
1653 | * | |
1654 | * Old style XT ports alias io ports every 0x400, hence accessing ECR | |
1655 | * on these cards actually accesses the CTR. | |
1656 | * | |
1657 | * Modern cards don't do this but reading from ECR will return 0xff | |
1658 | * regardless of what is written here if the card does NOT support | |
1659 | * ECP. | |
1660 | * | |
1661 | * We first check to see if ECR is the same as CTR. If not, the low | |
1662 | * two bits of ECR aren't writable, so we check by writing ECR and | |
1663 | * reading it back to see if it's what we expect. | |
1664 | */ | |
96766a3c | 1665 | static int parport_ECR_present(struct parport *pb) |
1da177e4 LT |
1666 | { |
1667 | struct parport_pc_private *priv = pb->private_data; | |
1668 | unsigned char r = 0xc; | |
1669 | ||
1670 | outb (r, CONTROL (pb)); | |
1671 | if ((inb (ECONTROL (pb)) & 0x3) == (r & 0x3)) { | |
1672 | outb (r ^ 0x2, CONTROL (pb)); /* Toggle bit 1 */ | |
1673 | ||
1674 | r = inb (CONTROL (pb)); | |
1675 | if ((inb (ECONTROL (pb)) & 0x2) == (r & 0x2)) | |
1676 | goto no_reg; /* Sure that no ECR register exists */ | |
1677 | } | |
1678 | ||
1679 | if ((inb (ECONTROL (pb)) & 0x3 ) != 0x1) | |
1680 | goto no_reg; | |
1681 | ||
1682 | ECR_WRITE (pb, 0x34); | |
1683 | if (inb (ECONTROL (pb)) != 0x35) | |
1684 | goto no_reg; | |
1685 | ||
1686 | priv->ecr = 1; | |
1687 | outb (0xc, CONTROL (pb)); | |
1688 | ||
1689 | /* Go to mode 000 */ | |
1690 | frob_set_mode (pb, ECR_SPP); | |
1691 | ||
1692 | return 1; | |
1693 | ||
1694 | no_reg: | |
1695 | outb (0xc, CONTROL (pb)); | |
1696 | return 0; | |
1697 | } | |
1698 | ||
1699 | #ifdef CONFIG_PARPORT_1284 | |
1700 | /* Detect PS/2 support. | |
1701 | * | |
1702 | * Bit 5 (0x20) sets the PS/2 data direction; setting this high | |
1703 | * allows us to read data from the data lines. In theory we would get back | |
1704 | * 0xff but any peripheral attached to the port may drag some or all of the | |
1705 | * lines down to zero. So if we get back anything that isn't the contents | |
1706 | * of the data register we deem PS/2 support to be present. | |
1707 | * | |
1708 | * Some SPP ports have "half PS/2" ability - you can't turn off the line | |
1709 | * drivers, but an external peripheral with sufficiently beefy drivers of | |
1710 | * its own can overpower them and assert its own levels onto the bus, from | |
1711 | * where they can then be read back as normal. Ports with this property | |
1712 | * and the right type of device attached are likely to fail the SPP test, | |
1713 | * (as they will appear to have stuck bits) and so the fact that they might | |
1714 | * be misdetected here is rather academic. | |
1715 | */ | |
1716 | ||
96766a3c | 1717 | static int parport_PS2_supported(struct parport *pb) |
1da177e4 LT |
1718 | { |
1719 | int ok = 0; | |
1720 | ||
1721 | clear_epp_timeout(pb); | |
1722 | ||
1723 | /* try to tri-state the buffer */ | |
1724 | parport_pc_data_reverse (pb); | |
1725 | ||
1726 | parport_pc_write_data(pb, 0x55); | |
1727 | if (parport_pc_read_data(pb) != 0x55) ok++; | |
1728 | ||
1729 | parport_pc_write_data(pb, 0xaa); | |
1730 | if (parport_pc_read_data(pb) != 0xaa) ok++; | |
1731 | ||
1732 | /* cancel input mode */ | |
1733 | parport_pc_data_forward (pb); | |
1734 | ||
1735 | if (ok) { | |
1736 | pb->modes |= PARPORT_MODE_TRISTATE; | |
1737 | } else { | |
1738 | struct parport_pc_private *priv = pb->private_data; | |
1739 | priv->ctr_writable &= ~0x20; | |
1740 | } | |
1741 | ||
1742 | return ok; | |
1743 | } | |
1744 | ||
1745 | #ifdef CONFIG_PARPORT_PC_FIFO | |
1746 | static int __devinit parport_ECP_supported(struct parport *pb) | |
1747 | { | |
1748 | int i; | |
1749 | int config, configb; | |
1750 | int pword; | |
1751 | struct parport_pc_private *priv = pb->private_data; | |
1752 | /* Translate ECP intrLine to ISA irq value */ | |
1753 | static const int intrline[]= { 0, 7, 9, 10, 11, 14, 15, 5 }; | |
1754 | ||
1755 | /* If there is no ECR, we have no hope of supporting ECP. */ | |
1756 | if (!priv->ecr) | |
1757 | return 0; | |
1758 | ||
1759 | /* Find out FIFO depth */ | |
1760 | ECR_WRITE (pb, ECR_SPP << 5); /* Reset FIFO */ | |
1761 | ECR_WRITE (pb, ECR_TST << 5); /* TEST FIFO */ | |
1762 | for (i=0; i < 1024 && !(inb (ECONTROL (pb)) & 0x02); i++) | |
1763 | outb (0xaa, FIFO (pb)); | |
1764 | ||
1765 | /* | |
1766 | * Using LGS chipset it uses ECR register, but | |
1767 | * it doesn't support ECP or FIFO MODE | |
1768 | */ | |
1769 | if (i == 1024) { | |
1770 | ECR_WRITE (pb, ECR_SPP << 5); | |
1771 | return 0; | |
1772 | } | |
1773 | ||
1774 | priv->fifo_depth = i; | |
1775 | if (verbose_probing) | |
1776 | printk (KERN_DEBUG "0x%lx: FIFO is %d bytes\n", pb->base, i); | |
1777 | ||
1778 | /* Find out writeIntrThreshold */ | |
1779 | frob_econtrol (pb, 1<<2, 1<<2); | |
1780 | frob_econtrol (pb, 1<<2, 0); | |
1781 | for (i = 1; i <= priv->fifo_depth; i++) { | |
1782 | inb (FIFO (pb)); | |
1783 | udelay (50); | |
1784 | if (inb (ECONTROL (pb)) & (1<<2)) | |
1785 | break; | |
1786 | } | |
1787 | ||
1788 | if (i <= priv->fifo_depth) { | |
1789 | if (verbose_probing) | |
1790 | printk (KERN_DEBUG "0x%lx: writeIntrThreshold is %d\n", | |
1791 | pb->base, i); | |
1792 | } else | |
1793 | /* Number of bytes we know we can write if we get an | |
1794 | interrupt. */ | |
1795 | i = 0; | |
1796 | ||
1797 | priv->writeIntrThreshold = i; | |
1798 | ||
1799 | /* Find out readIntrThreshold */ | |
1800 | frob_set_mode (pb, ECR_PS2); /* Reset FIFO and enable PS2 */ | |
1801 | parport_pc_data_reverse (pb); /* Must be in PS2 mode */ | |
1802 | frob_set_mode (pb, ECR_TST); /* Test FIFO */ | |
1803 | frob_econtrol (pb, 1<<2, 1<<2); | |
1804 | frob_econtrol (pb, 1<<2, 0); | |
1805 | for (i = 1; i <= priv->fifo_depth; i++) { | |
1806 | outb (0xaa, FIFO (pb)); | |
1807 | if (inb (ECONTROL (pb)) & (1<<2)) | |
1808 | break; | |
1809 | } | |
1810 | ||
1811 | if (i <= priv->fifo_depth) { | |
1812 | if (verbose_probing) | |
1813 | printk (KERN_INFO "0x%lx: readIntrThreshold is %d\n", | |
1814 | pb->base, i); | |
1815 | } else | |
1816 | /* Number of bytes we can read if we get an interrupt. */ | |
1817 | i = 0; | |
1818 | ||
1819 | priv->readIntrThreshold = i; | |
1820 | ||
1821 | ECR_WRITE (pb, ECR_SPP << 5); /* Reset FIFO */ | |
1822 | ECR_WRITE (pb, 0xf4); /* Configuration mode */ | |
1823 | config = inb (CONFIGA (pb)); | |
1824 | pword = (config >> 4) & 0x7; | |
1825 | switch (pword) { | |
1826 | case 0: | |
1827 | pword = 2; | |
1828 | printk (KERN_WARNING "0x%lx: Unsupported pword size!\n", | |
1829 | pb->base); | |
1830 | break; | |
1831 | case 2: | |
1832 | pword = 4; | |
1833 | printk (KERN_WARNING "0x%lx: Unsupported pword size!\n", | |
1834 | pb->base); | |
1835 | break; | |
1836 | default: | |
1837 | printk (KERN_WARNING "0x%lx: Unknown implementation ID\n", | |
1838 | pb->base); | |
1839 | /* Assume 1 */ | |
1840 | case 1: | |
1841 | pword = 1; | |
1842 | } | |
1843 | priv->pword = pword; | |
1844 | ||
1845 | if (verbose_probing) { | |
1846 | printk (KERN_DEBUG "0x%lx: PWord is %d bits\n", pb->base, 8 * pword); | |
1847 | ||
1848 | printk (KERN_DEBUG "0x%lx: Interrupts are ISA-%s\n", pb->base, | |
1849 | config & 0x80 ? "Level" : "Pulses"); | |
1850 | ||
1851 | configb = inb (CONFIGB (pb)); | |
1852 | printk (KERN_DEBUG "0x%lx: ECP port cfgA=0x%02x cfgB=0x%02x\n", | |
1853 | pb->base, config, configb); | |
1854 | printk (KERN_DEBUG "0x%lx: ECP settings irq=", pb->base); | |
1855 | if ((configb >>3) & 0x07) | |
1856 | printk("%d",intrline[(configb >>3) & 0x07]); | |
1857 | else | |
1858 | printk("<none or set by other means>"); | |
1859 | printk (" dma="); | |
1860 | if( (configb & 0x03 ) == 0x00) | |
1861 | printk("<none or set by other means>\n"); | |
1862 | else | |
1863 | printk("%d\n",configb & 0x07); | |
1864 | } | |
1865 | ||
1866 | /* Go back to mode 000 */ | |
1867 | frob_set_mode (pb, ECR_SPP); | |
1868 | ||
1869 | return 1; | |
1870 | } | |
1871 | #endif | |
1872 | ||
96766a3c | 1873 | static int parport_ECPPS2_supported(struct parport *pb) |
1da177e4 LT |
1874 | { |
1875 | const struct parport_pc_private *priv = pb->private_data; | |
1876 | int result; | |
1877 | unsigned char oecr; | |
1878 | ||
1879 | if (!priv->ecr) | |
1880 | return 0; | |
1881 | ||
1882 | oecr = inb (ECONTROL (pb)); | |
1883 | ECR_WRITE (pb, ECR_PS2 << 5); | |
1884 | result = parport_PS2_supported(pb); | |
1885 | ECR_WRITE (pb, oecr); | |
1886 | return result; | |
1887 | } | |
1888 | ||
1889 | /* EPP mode detection */ | |
1890 | ||
96766a3c | 1891 | static int parport_EPP_supported(struct parport *pb) |
1da177e4 LT |
1892 | { |
1893 | const struct parport_pc_private *priv = pb->private_data; | |
1894 | ||
1895 | /* | |
1896 | * Theory: | |
1897 | * Bit 0 of STR is the EPP timeout bit, this bit is 0 | |
1898 | * when EPP is possible and is set high when an EPP timeout | |
1899 | * occurs (EPP uses the HALT line to stop the CPU while it does | |
1900 | * the byte transfer, an EPP timeout occurs if the attached | |
1901 | * device fails to respond after 10 micro seconds). | |
1902 | * | |
1903 | * This bit is cleared by either reading it (National Semi) | |
1904 | * or writing a 1 to the bit (SMC, UMC, WinBond), others ??? | |
1905 | * This bit is always high in non EPP modes. | |
1906 | */ | |
1907 | ||
1908 | /* If EPP timeout bit clear then EPP available */ | |
1909 | if (!clear_epp_timeout(pb)) { | |
1910 | return 0; /* No way to clear timeout */ | |
1911 | } | |
1912 | ||
1913 | /* Check for Intel bug. */ | |
1914 | if (priv->ecr) { | |
1915 | unsigned char i; | |
1916 | for (i = 0x00; i < 0x80; i += 0x20) { | |
1917 | ECR_WRITE (pb, i); | |
1918 | if (clear_epp_timeout (pb)) { | |
1919 | /* Phony EPP in ECP. */ | |
1920 | return 0; | |
1921 | } | |
1922 | } | |
1923 | } | |
1924 | ||
1925 | pb->modes |= PARPORT_MODE_EPP; | |
1926 | ||
1927 | /* Set up access functions to use EPP hardware. */ | |
1928 | pb->ops->epp_read_data = parport_pc_epp_read_data; | |
1929 | pb->ops->epp_write_data = parport_pc_epp_write_data; | |
1930 | pb->ops->epp_read_addr = parport_pc_epp_read_addr; | |
1931 | pb->ops->epp_write_addr = parport_pc_epp_write_addr; | |
1932 | ||
1933 | return 1; | |
1934 | } | |
1935 | ||
96766a3c | 1936 | static int parport_ECPEPP_supported(struct parport *pb) |
1da177e4 LT |
1937 | { |
1938 | struct parport_pc_private *priv = pb->private_data; | |
1939 | int result; | |
1940 | unsigned char oecr; | |
1941 | ||
1942 | if (!priv->ecr) { | |
1943 | return 0; | |
1944 | } | |
1945 | ||
1946 | oecr = inb (ECONTROL (pb)); | |
1947 | /* Search for SMC style EPP+ECP mode */ | |
1948 | ECR_WRITE (pb, 0x80); | |
1949 | outb (0x04, CONTROL (pb)); | |
1950 | result = parport_EPP_supported(pb); | |
1951 | ||
1952 | ECR_WRITE (pb, oecr); | |
1953 | ||
1954 | if (result) { | |
1955 | /* Set up access functions to use ECP+EPP hardware. */ | |
1956 | pb->ops->epp_read_data = parport_pc_ecpepp_read_data; | |
1957 | pb->ops->epp_write_data = parport_pc_ecpepp_write_data; | |
1958 | pb->ops->epp_read_addr = parport_pc_ecpepp_read_addr; | |
1959 | pb->ops->epp_write_addr = parport_pc_ecpepp_write_addr; | |
1960 | } | |
1961 | ||
1962 | return result; | |
1963 | } | |
1964 | ||
1965 | #else /* No IEEE 1284 support */ | |
1966 | ||
1967 | /* Don't bother probing for modes we know we won't use. */ | |
1968 | static int __devinit parport_PS2_supported(struct parport *pb) { return 0; } | |
1969 | #ifdef CONFIG_PARPORT_PC_FIFO | |
1970 | static int __devinit parport_ECP_supported(struct parport *pb) { return 0; } | |
1971 | #endif | |
1972 | static int __devinit parport_EPP_supported(struct parport *pb) { return 0; } | |
1973 | static int __devinit parport_ECPEPP_supported(struct parport *pb){return 0;} | |
1974 | static int __devinit parport_ECPPS2_supported(struct parport *pb){return 0;} | |
1975 | ||
1976 | #endif /* No IEEE 1284 support */ | |
1977 | ||
1978 | /* --- IRQ detection -------------------------------------- */ | |
1979 | ||
1980 | /* Only if supports ECP mode */ | |
4438982f | 1981 | static int programmable_irq_support(struct parport *pb) |
1da177e4 LT |
1982 | { |
1983 | int irq, intrLine; | |
1984 | unsigned char oecr = inb (ECONTROL (pb)); | |
1985 | static const int lookup[8] = { | |
1986 | PARPORT_IRQ_NONE, 7, 9, 10, 11, 14, 15, 5 | |
1987 | }; | |
1988 | ||
1989 | ECR_WRITE (pb, ECR_CNF << 5); /* Configuration MODE */ | |
1990 | ||
1991 | intrLine = (inb (CONFIGB (pb)) >> 3) & 0x07; | |
1992 | irq = lookup[intrLine]; | |
1993 | ||
1994 | ECR_WRITE (pb, oecr); | |
1995 | return irq; | |
1996 | } | |
1997 | ||
4438982f | 1998 | static int irq_probe_ECP(struct parport *pb) |
1da177e4 LT |
1999 | { |
2000 | int i; | |
2001 | unsigned long irqs; | |
2002 | ||
2003 | irqs = probe_irq_on(); | |
2004 | ||
2005 | ECR_WRITE (pb, ECR_SPP << 5); /* Reset FIFO */ | |
2006 | ECR_WRITE (pb, (ECR_TST << 5) | 0x04); | |
2007 | ECR_WRITE (pb, ECR_TST << 5); | |
2008 | ||
2009 | /* If Full FIFO sure that writeIntrThreshold is generated */ | |
2010 | for (i=0; i < 1024 && !(inb (ECONTROL (pb)) & 0x02) ; i++) | |
2011 | outb (0xaa, FIFO (pb)); | |
2012 | ||
2013 | pb->irq = probe_irq_off(irqs); | |
2014 | ECR_WRITE (pb, ECR_SPP << 5); | |
2015 | ||
2016 | if (pb->irq <= 0) | |
2017 | pb->irq = PARPORT_IRQ_NONE; | |
2018 | ||
2019 | return pb->irq; | |
2020 | } | |
2021 | ||
2022 | /* | |
2023 | * This detection seems that only works in National Semiconductors | |
2024 | * This doesn't work in SMC, LGS, and Winbond | |
2025 | */ | |
4438982f | 2026 | static int irq_probe_EPP(struct parport *pb) |
1da177e4 LT |
2027 | { |
2028 | #ifndef ADVANCED_DETECT | |
2029 | return PARPORT_IRQ_NONE; | |
2030 | #else | |
2031 | int irqs; | |
2032 | unsigned char oecr; | |
2033 | ||
2034 | if (pb->modes & PARPORT_MODE_PCECR) | |
2035 | oecr = inb (ECONTROL (pb)); | |
2036 | ||
2037 | irqs = probe_irq_on(); | |
2038 | ||
2039 | if (pb->modes & PARPORT_MODE_PCECR) | |
2040 | frob_econtrol (pb, 0x10, 0x10); | |
2041 | ||
2042 | clear_epp_timeout(pb); | |
2043 | parport_pc_frob_control (pb, 0x20, 0x20); | |
2044 | parport_pc_frob_control (pb, 0x10, 0x10); | |
2045 | clear_epp_timeout(pb); | |
2046 | ||
2047 | /* Device isn't expecting an EPP read | |
2048 | * and generates an IRQ. | |
2049 | */ | |
2050 | parport_pc_read_epp(pb); | |
2051 | udelay(20); | |
2052 | ||
2053 | pb->irq = probe_irq_off (irqs); | |
2054 | if (pb->modes & PARPORT_MODE_PCECR) | |
2055 | ECR_WRITE (pb, oecr); | |
2056 | parport_pc_write_control(pb, 0xc); | |
2057 | ||
2058 | if (pb->irq <= 0) | |
2059 | pb->irq = PARPORT_IRQ_NONE; | |
2060 | ||
2061 | return pb->irq; | |
2062 | #endif /* Advanced detection */ | |
2063 | } | |
2064 | ||
4438982f | 2065 | static int irq_probe_SPP(struct parport *pb) |
1da177e4 LT |
2066 | { |
2067 | /* Don't even try to do this. */ | |
2068 | return PARPORT_IRQ_NONE; | |
2069 | } | |
2070 | ||
2071 | /* We will attempt to share interrupt requests since other devices | |
2072 | * such as sound cards and network cards seem to like using the | |
2073 | * printer IRQs. | |
2074 | * | |
2075 | * When ECP is available we can autoprobe for IRQs. | |
2076 | * NOTE: If we can autoprobe it, we can register the IRQ. | |
2077 | */ | |
96766a3c | 2078 | static int parport_irq_probe(struct parport *pb) |
1da177e4 LT |
2079 | { |
2080 | struct parport_pc_private *priv = pb->private_data; | |
2081 | ||
2082 | if (priv->ecr) { | |
2083 | pb->irq = programmable_irq_support(pb); | |
2084 | ||
2085 | if (pb->irq == PARPORT_IRQ_NONE) | |
2086 | pb->irq = irq_probe_ECP(pb); | |
2087 | } | |
2088 | ||
2089 | if ((pb->irq == PARPORT_IRQ_NONE) && priv->ecr && | |
2090 | (pb->modes & PARPORT_MODE_EPP)) | |
2091 | pb->irq = irq_probe_EPP(pb); | |
2092 | ||
2093 | clear_epp_timeout(pb); | |
2094 | ||
2095 | if (pb->irq == PARPORT_IRQ_NONE && (pb->modes & PARPORT_MODE_EPP)) | |
2096 | pb->irq = irq_probe_EPP(pb); | |
2097 | ||
2098 | clear_epp_timeout(pb); | |
2099 | ||
2100 | if (pb->irq == PARPORT_IRQ_NONE) | |
2101 | pb->irq = irq_probe_SPP(pb); | |
2102 | ||
2103 | if (pb->irq == PARPORT_IRQ_NONE) | |
2104 | pb->irq = get_superio_irq(pb); | |
2105 | ||
2106 | return pb->irq; | |
2107 | } | |
2108 | ||
2109 | /* --- DMA detection -------------------------------------- */ | |
2110 | ||
2111 | /* Only if chipset conforms to ECP ISA Interface Standard */ | |
0bb92e6c | 2112 | static int programmable_dma_support (struct parport *p) |
1da177e4 LT |
2113 | { |
2114 | unsigned char oecr = inb (ECONTROL (p)); | |
2115 | int dma; | |
2116 | ||
2117 | frob_set_mode (p, ECR_CNF); | |
2118 | ||
2119 | dma = inb (CONFIGB(p)) & 0x07; | |
2120 | /* 000: Indicates jumpered 8-bit DMA if read-only. | |
2121 | 100: Indicates jumpered 16-bit DMA if read-only. */ | |
2122 | if ((dma & 0x03) == 0) | |
2123 | dma = PARPORT_DMA_NONE; | |
2124 | ||
2125 | ECR_WRITE (p, oecr); | |
2126 | return dma; | |
2127 | } | |
2128 | ||
0bb92e6c | 2129 | static int parport_dma_probe (struct parport *p) |
1da177e4 LT |
2130 | { |
2131 | const struct parport_pc_private *priv = p->private_data; | |
2132 | if (priv->ecr) | |
2133 | p->dma = programmable_dma_support(p); /* ask ECP chipset first */ | |
2134 | if (p->dma == PARPORT_DMA_NONE) { | |
2135 | /* ask known Super-IO chips proper, although these | |
2136 | claim ECP compatible, some don't report their DMA | |
2137 | conforming to ECP standards */ | |
2138 | p->dma = get_superio_dma(p); | |
2139 | } | |
2140 | ||
2141 | return p->dma; | |
2142 | } | |
2143 | ||
2144 | /* --- Initialisation code -------------------------------- */ | |
2145 | ||
2146 | static LIST_HEAD(ports_list); | |
2147 | static DEFINE_SPINLOCK(ports_lock); | |
2148 | ||
2149 | struct parport *parport_pc_probe_port (unsigned long int base, | |
2150 | unsigned long int base_hi, | |
2151 | int irq, int dma, | |
c15a3837 | 2152 | struct device *dev) |
1da177e4 LT |
2153 | { |
2154 | struct parport_pc_private *priv; | |
2155 | struct parport_operations *ops; | |
2156 | struct parport *p; | |
2157 | int probedirq = PARPORT_IRQ_NONE; | |
2158 | struct resource *base_res; | |
2159 | struct resource *ECR_res = NULL; | |
2160 | struct resource *EPP_res = NULL; | |
a7d801af JD |
2161 | struct platform_device *pdev = NULL; |
2162 | ||
2163 | if (!dev) { | |
2164 | /* We need a physical device to attach to, but none was | |
2165 | * provided. Create our own. */ | |
2166 | pdev = platform_device_register_simple("parport_pc", | |
2167 | base, NULL, 0); | |
2168 | if (IS_ERR(pdev)) | |
2169 | return NULL; | |
2170 | dev = &pdev->dev; | |
2171 | } | |
1da177e4 LT |
2172 | |
2173 | ops = kmalloc(sizeof (struct parport_operations), GFP_KERNEL); | |
2174 | if (!ops) | |
2175 | goto out1; | |
2176 | ||
2177 | priv = kmalloc (sizeof (struct parport_pc_private), GFP_KERNEL); | |
2178 | if (!priv) | |
2179 | goto out2; | |
2180 | ||
2181 | /* a misnomer, actually - it's allocate and reserve parport number */ | |
2182 | p = parport_register_port(base, irq, dma, ops); | |
2183 | if (!p) | |
2184 | goto out3; | |
2185 | ||
2186 | base_res = request_region(base, 3, p->name); | |
2187 | if (!base_res) | |
2188 | goto out4; | |
2189 | ||
2190 | memcpy(ops, &parport_pc_ops, sizeof (struct parport_operations)); | |
2191 | priv->ctr = 0xc; | |
2192 | priv->ctr_writable = ~0x10; | |
2193 | priv->ecr = 0; | |
2194 | priv->fifo_depth = 0; | |
2195 | priv->dma_buf = NULL; | |
2196 | priv->dma_handle = 0; | |
1da177e4 LT |
2197 | INIT_LIST_HEAD(&priv->list); |
2198 | priv->port = p; | |
c15a3837 DB |
2199 | |
2200 | p->dev = dev; | |
1da177e4 LT |
2201 | p->base_hi = base_hi; |
2202 | p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT; | |
2203 | p->private_data = priv; | |
2204 | ||
2205 | if (base_hi) { | |
2206 | ECR_res = request_region(base_hi, 3, p->name); | |
2207 | if (ECR_res) | |
2208 | parport_ECR_present(p); | |
2209 | } | |
2210 | ||
2211 | if (base != 0x3bc) { | |
2212 | EPP_res = request_region(base+0x3, 5, p->name); | |
2213 | if (EPP_res) | |
2214 | if (!parport_EPP_supported(p)) | |
2215 | parport_ECPEPP_supported(p); | |
2216 | } | |
2217 | if (!parport_SPP_supported (p)) | |
2218 | /* No port. */ | |
2219 | goto out5; | |
2220 | if (priv->ecr) | |
2221 | parport_ECPPS2_supported(p); | |
2222 | else | |
2223 | parport_PS2_supported(p); | |
2224 | ||
2225 | p->size = (p->modes & PARPORT_MODE_EPP)?8:3; | |
2226 | ||
2227 | printk(KERN_INFO "%s: PC-style at 0x%lx", p->name, p->base); | |
2228 | if (p->base_hi && priv->ecr) | |
2229 | printk(" (0x%lx)", p->base_hi); | |
2230 | if (p->irq == PARPORT_IRQ_AUTO) { | |
2231 | p->irq = PARPORT_IRQ_NONE; | |
2232 | parport_irq_probe(p); | |
2233 | } else if (p->irq == PARPORT_IRQ_PROBEONLY) { | |
2234 | p->irq = PARPORT_IRQ_NONE; | |
2235 | parport_irq_probe(p); | |
2236 | probedirq = p->irq; | |
2237 | p->irq = PARPORT_IRQ_NONE; | |
2238 | } | |
2239 | if (p->irq != PARPORT_IRQ_NONE) { | |
2240 | printk(", irq %d", p->irq); | |
2241 | priv->ctr_writable |= 0x10; | |
2242 | ||
2243 | if (p->dma == PARPORT_DMA_AUTO) { | |
2244 | p->dma = PARPORT_DMA_NONE; | |
2245 | parport_dma_probe(p); | |
2246 | } | |
2247 | } | |
2248 | if (p->dma == PARPORT_DMA_AUTO) /* To use DMA, giving the irq | |
2249 | is mandatory (see above) */ | |
2250 | p->dma = PARPORT_DMA_NONE; | |
2251 | ||
2252 | #ifdef CONFIG_PARPORT_PC_FIFO | |
2253 | if (parport_ECP_supported(p) && | |
2254 | p->dma != PARPORT_DMA_NOFIFO && | |
2255 | priv->fifo_depth > 0 && p->irq != PARPORT_IRQ_NONE) { | |
2256 | p->modes |= PARPORT_MODE_ECP | PARPORT_MODE_COMPAT; | |
2257 | p->ops->compat_write_data = parport_pc_compat_write_block_pio; | |
2258 | #ifdef CONFIG_PARPORT_1284 | |
2259 | p->ops->ecp_write_data = parport_pc_ecp_write_block_pio; | |
2260 | /* currently broken, but working on it.. (FB) */ | |
2261 | /* p->ops->ecp_read_data = parport_pc_ecp_read_block_pio; */ | |
2262 | #endif /* IEEE 1284 support */ | |
2263 | if (p->dma != PARPORT_DMA_NONE) { | |
2264 | printk(", dma %d", p->dma); | |
2265 | p->modes |= PARPORT_MODE_DMA; | |
2266 | } | |
2267 | else printk(", using FIFO"); | |
2268 | } | |
2269 | else | |
2270 | /* We can't use the DMA channel after all. */ | |
2271 | p->dma = PARPORT_DMA_NONE; | |
2272 | #endif /* Allowed to use FIFO/DMA */ | |
2273 | ||
2274 | printk(" ["); | |
2275 | #define printmode(x) {if(p->modes&PARPORT_MODE_##x){printk("%s%s",f?",":"",#x);f++;}} | |
2276 | { | |
2277 | int f = 0; | |
2278 | printmode(PCSPP); | |
2279 | printmode(TRISTATE); | |
2280 | printmode(COMPAT) | |
2281 | printmode(EPP); | |
2282 | printmode(ECP); | |
2283 | printmode(DMA); | |
2284 | } | |
2285 | #undef printmode | |
2286 | #ifndef CONFIG_PARPORT_1284 | |
2287 | printk ("(,...)"); | |
2288 | #endif /* CONFIG_PARPORT_1284 */ | |
2289 | printk("]\n"); | |
2290 | if (probedirq != PARPORT_IRQ_NONE) | |
2291 | printk(KERN_INFO "%s: irq %d detected\n", p->name, probedirq); | |
2292 | ||
2293 | /* If No ECP release the ports grabbed above. */ | |
2294 | if (ECR_res && (p->modes & PARPORT_MODE_ECP) == 0) { | |
2295 | release_region(base_hi, 3); | |
2296 | ECR_res = NULL; | |
2297 | } | |
2298 | /* Likewise for EEP ports */ | |
2299 | if (EPP_res && (p->modes & PARPORT_MODE_EPP) == 0) { | |
2300 | release_region(base+3, 5); | |
2301 | EPP_res = NULL; | |
2302 | } | |
2303 | if (p->irq != PARPORT_IRQ_NONE) { | |
2304 | if (request_irq (p->irq, parport_pc_interrupt, | |
2305 | 0, p->name, p)) { | |
2306 | printk (KERN_WARNING "%s: irq %d in use, " | |
2307 | "resorting to polled operation\n", | |
2308 | p->name, p->irq); | |
2309 | p->irq = PARPORT_IRQ_NONE; | |
2310 | p->dma = PARPORT_DMA_NONE; | |
2311 | } | |
2312 | ||
2313 | #ifdef CONFIG_PARPORT_PC_FIFO | |
7fbacd52 | 2314 | #ifdef HAS_DMA |
1da177e4 LT |
2315 | if (p->dma != PARPORT_DMA_NONE) { |
2316 | if (request_dma (p->dma, p->name)) { | |
2317 | printk (KERN_WARNING "%s: dma %d in use, " | |
2318 | "resorting to PIO operation\n", | |
2319 | p->name, p->dma); | |
2320 | p->dma = PARPORT_DMA_NONE; | |
2321 | } else { | |
2322 | priv->dma_buf = | |
c15a3837 | 2323 | dma_alloc_coherent(dev, |
1da177e4 | 2324 | PAGE_SIZE, |
c15a3837 DB |
2325 | &priv->dma_handle, |
2326 | GFP_KERNEL); | |
1da177e4 LT |
2327 | if (! priv->dma_buf) { |
2328 | printk (KERN_WARNING "%s: " | |
2329 | "cannot get buffer for DMA, " | |
2330 | "resorting to PIO operation\n", | |
2331 | p->name); | |
2332 | free_dma(p->dma); | |
2333 | p->dma = PARPORT_DMA_NONE; | |
2334 | } | |
2335 | } | |
2336 | } | |
7fbacd52 AV |
2337 | #endif |
2338 | #endif | |
1da177e4 LT |
2339 | } |
2340 | ||
2341 | /* Done probing. Now put the port into a sensible start-up state. */ | |
2342 | if (priv->ecr) | |
2343 | /* | |
2344 | * Put the ECP detected port in PS2 mode. | |
2345 | * Do this also for ports that have ECR but don't do ECP. | |
2346 | */ | |
2347 | ECR_WRITE (p, 0x34); | |
2348 | ||
2349 | parport_pc_write_data(p, 0); | |
2350 | parport_pc_data_forward (p); | |
2351 | ||
2352 | /* Now that we've told the sharing engine about the port, and | |
2353 | found out its characteristics, let the high-level drivers | |
2354 | know about it. */ | |
2355 | spin_lock(&ports_lock); | |
2356 | list_add(&priv->list, &ports_list); | |
2357 | spin_unlock(&ports_lock); | |
2358 | parport_announce_port (p); | |
2359 | ||
2360 | return p; | |
2361 | ||
2362 | out5: | |
2363 | if (ECR_res) | |
2364 | release_region(base_hi, 3); | |
2365 | if (EPP_res) | |
2366 | release_region(base+0x3, 5); | |
2367 | release_region(base, 3); | |
2368 | out4: | |
2369 | parport_put_port(p); | |
2370 | out3: | |
2371 | kfree (priv); | |
2372 | out2: | |
2373 | kfree (ops); | |
2374 | out1: | |
a7d801af JD |
2375 | if (pdev) |
2376 | platform_device_unregister(pdev); | |
1da177e4 LT |
2377 | return NULL; |
2378 | } | |
2379 | ||
2380 | EXPORT_SYMBOL (parport_pc_probe_port); | |
2381 | ||
2382 | void parport_pc_unregister_port (struct parport *p) | |
2383 | { | |
2384 | struct parport_pc_private *priv = p->private_data; | |
2385 | struct parport_operations *ops = p->ops; | |
2386 | ||
2387 | parport_remove_port(p); | |
2388 | spin_lock(&ports_lock); | |
2389 | list_del_init(&priv->list); | |
2390 | spin_unlock(&ports_lock); | |
d1c4ac40 | 2391 | #if defined(CONFIG_PARPORT_PC_FIFO) && defined(HAS_DMA) |
1da177e4 LT |
2392 | if (p->dma != PARPORT_DMA_NONE) |
2393 | free_dma(p->dma); | |
d1c4ac40 | 2394 | #endif |
1da177e4 LT |
2395 | if (p->irq != PARPORT_IRQ_NONE) |
2396 | free_irq(p->irq, p); | |
2397 | release_region(p->base, 3); | |
2398 | if (p->size > 3) | |
2399 | release_region(p->base + 3, p->size - 3); | |
2400 | if (p->modes & PARPORT_MODE_ECP) | |
2401 | release_region(p->base_hi, 3); | |
d1c4ac40 | 2402 | #if defined(CONFIG_PARPORT_PC_FIFO) && defined(HAS_DMA) |
1da177e4 | 2403 | if (priv->dma_buf) |
c15a3837 | 2404 | dma_free_coherent(p->physport->dev, PAGE_SIZE, |
1da177e4 LT |
2405 | priv->dma_buf, |
2406 | priv->dma_handle); | |
7fbacd52 | 2407 | #endif |
1da177e4 LT |
2408 | kfree (p->private_data); |
2409 | parport_put_port(p); | |
2410 | kfree (ops); /* hope no-one cached it */ | |
2411 | } | |
2412 | ||
2413 | EXPORT_SYMBOL (parport_pc_unregister_port); | |
2414 | ||
2415 | #ifdef CONFIG_PCI | |
2416 | ||
2417 | /* ITE support maintained by Rich Liu <richliu@poorman.org> */ | |
2418 | static int __devinit sio_ite_8872_probe (struct pci_dev *pdev, int autoirq, | |
a6767b7c MK |
2419 | int autodma, |
2420 | const struct parport_pc_via_data *via) | |
1da177e4 LT |
2421 | { |
2422 | short inta_addr[6] = { 0x2A0, 0x2C0, 0x220, 0x240, 0x1E0 }; | |
2423 | struct resource *base_res; | |
2424 | u32 ite8872set; | |
2425 | u32 ite8872_lpt, ite8872_lpthi; | |
2426 | u8 ite8872_irq, type; | |
2427 | char *fake_name = "parport probe"; | |
2428 | int irq; | |
2429 | int i; | |
2430 | ||
2431 | DPRINTK (KERN_DEBUG "sio_ite_8872_probe()\n"); | |
2432 | ||
2433 | // make sure which one chip | |
2434 | for(i = 0; i < 5; i++) { | |
2435 | base_res = request_region(inta_addr[i], 0x8, fake_name); | |
2436 | if (base_res) { | |
2437 | int test; | |
2438 | pci_write_config_dword (pdev, 0x60, | |
2439 | 0xe7000000 | inta_addr[i]); | |
2440 | pci_write_config_dword (pdev, 0x78, | |
2441 | 0x00000000 | inta_addr[i]); | |
2442 | test = inb (inta_addr[i]); | |
2443 | if (test != 0xff) break; | |
2444 | release_region(inta_addr[i], 0x8); | |
2445 | } | |
2446 | } | |
2447 | if(i >= 5) { | |
2448 | printk (KERN_INFO "parport_pc: cannot find ITE8872 INTA\n"); | |
2449 | return 0; | |
2450 | } | |
2451 | ||
2452 | type = inb (inta_addr[i] + 0x18); | |
2453 | type &= 0x0f; | |
2454 | ||
2455 | switch (type) { | |
2456 | case 0x2: | |
2457 | printk (KERN_INFO "parport_pc: ITE8871 found (1P)\n"); | |
2458 | ite8872set = 0x64200000; | |
2459 | break; | |
2460 | case 0xa: | |
2461 | printk (KERN_INFO "parport_pc: ITE8875 found (1P)\n"); | |
2462 | ite8872set = 0x64200000; | |
2463 | break; | |
2464 | case 0xe: | |
2465 | printk (KERN_INFO "parport_pc: ITE8872 found (2S1P)\n"); | |
2466 | ite8872set = 0x64e00000; | |
2467 | break; | |
2468 | case 0x6: | |
2469 | printk (KERN_INFO "parport_pc: ITE8873 found (1S)\n"); | |
2470 | return 0; | |
2471 | case 0x8: | |
2472 | DPRINTK (KERN_DEBUG "parport_pc: ITE8874 found (2S)\n"); | |
2473 | return 0; | |
2474 | default: | |
2475 | printk (KERN_INFO "parport_pc: unknown ITE887x\n"); | |
2476 | printk (KERN_INFO "parport_pc: please mail 'lspci -nvv' " | |
2477 | "output to Rich.Liu@ite.com.tw\n"); | |
2478 | return 0; | |
2479 | } | |
2480 | ||
2481 | pci_read_config_byte (pdev, 0x3c, &ite8872_irq); | |
2482 | pci_read_config_dword (pdev, 0x1c, &ite8872_lpt); | |
2483 | ite8872_lpt &= 0x0000ff00; | |
2484 | pci_read_config_dword (pdev, 0x20, &ite8872_lpthi); | |
2485 | ite8872_lpthi &= 0x0000ff00; | |
2486 | pci_write_config_dword (pdev, 0x6c, 0xe3000000 | ite8872_lpt); | |
2487 | pci_write_config_dword (pdev, 0x70, 0xe3000000 | ite8872_lpthi); | |
2488 | pci_write_config_dword (pdev, 0x80, (ite8872_lpthi<<16) | ite8872_lpt); | |
2489 | // SET SPP&EPP , Parallel Port NO DMA , Enable All Function | |
2490 | // SET Parallel IRQ | |
2491 | pci_write_config_dword (pdev, 0x9c, | |
2492 | ite8872set | (ite8872_irq * 0x11111)); | |
2493 | ||
2494 | DPRINTK (KERN_DEBUG "ITE887x: The IRQ is %d.\n", ite8872_irq); | |
2495 | DPRINTK (KERN_DEBUG "ITE887x: The PARALLEL I/O port is 0x%x.\n", | |
2496 | ite8872_lpt); | |
2497 | DPRINTK (KERN_DEBUG "ITE887x: The PARALLEL I/O porthi is 0x%x.\n", | |
2498 | ite8872_lpthi); | |
2499 | ||
2500 | /* Let the user (or defaults) steer us away from interrupts */ | |
2501 | irq = ite8872_irq; | |
2502 | if (autoirq != PARPORT_IRQ_AUTO) | |
2503 | irq = PARPORT_IRQ_NONE; | |
2504 | ||
2505 | /* | |
2506 | * Release the resource so that parport_pc_probe_port can get it. | |
2507 | */ | |
2508 | release_resource(base_res); | |
2509 | if (parport_pc_probe_port (ite8872_lpt, ite8872_lpthi, | |
c15a3837 | 2510 | irq, PARPORT_DMA_NONE, &pdev->dev)) { |
1da177e4 LT |
2511 | printk (KERN_INFO |
2512 | "parport_pc: ITE 8872 parallel port: io=0x%X", | |
2513 | ite8872_lpt); | |
2514 | if (irq != PARPORT_IRQ_NONE) | |
2515 | printk (", irq=%d", irq); | |
2516 | printk ("\n"); | |
2517 | return 1; | |
2518 | } | |
2519 | ||
2520 | return 0; | |
2521 | } | |
2522 | ||
2523 | /* VIA 8231 support by Pavel Fedin <sonic_amiga@rambler.ru> | |
2524 | based on VIA 686a support code by Jeff Garzik <jgarzik@pobox.com> */ | |
2525 | static int __devinitdata parport_init_mode = 0; | |
2526 | ||
2527 | /* Data for two known VIA chips */ | |
2528 | static struct parport_pc_via_data via_686a_data __devinitdata = { | |
2529 | 0x51, | |
2530 | 0x50, | |
2531 | 0x85, | |
2532 | 0x02, | |
2533 | 0xE2, | |
2534 | 0xF0, | |
2535 | 0xE6 | |
2536 | }; | |
2537 | static struct parport_pc_via_data via_8231_data __devinitdata = { | |
2538 | 0x45, | |
2539 | 0x44, | |
2540 | 0x50, | |
2541 | 0x04, | |
2542 | 0xF2, | |
2543 | 0xFA, | |
2544 | 0xF6 | |
2545 | }; | |
2546 | ||
2547 | static int __devinit sio_via_probe (struct pci_dev *pdev, int autoirq, | |
a6767b7c MK |
2548 | int autodma, |
2549 | const struct parport_pc_via_data *via) | |
1da177e4 LT |
2550 | { |
2551 | u8 tmp, tmp2, siofunc; | |
2552 | u8 ppcontrol = 0; | |
2553 | int dma, irq; | |
2554 | unsigned port1, port2; | |
2555 | unsigned have_epp = 0; | |
2556 | ||
2557 | printk(KERN_DEBUG "parport_pc: VIA 686A/8231 detected\n"); | |
2558 | ||
2559 | switch(parport_init_mode) | |
2560 | { | |
2561 | case 1: | |
2562 | printk(KERN_DEBUG "parport_pc: setting SPP mode\n"); | |
2563 | siofunc = VIA_FUNCTION_PARPORT_SPP; | |
2564 | break; | |
2565 | case 2: | |
2566 | printk(KERN_DEBUG "parport_pc: setting PS/2 mode\n"); | |
2567 | siofunc = VIA_FUNCTION_PARPORT_SPP; | |
2568 | ppcontrol = VIA_PARPORT_BIDIR; | |
2569 | break; | |
2570 | case 3: | |
2571 | printk(KERN_DEBUG "parport_pc: setting EPP mode\n"); | |
2572 | siofunc = VIA_FUNCTION_PARPORT_EPP; | |
2573 | ppcontrol = VIA_PARPORT_BIDIR; | |
2574 | have_epp = 1; | |
2575 | break; | |
2576 | case 4: | |
2577 | printk(KERN_DEBUG "parport_pc: setting ECP mode\n"); | |
2578 | siofunc = VIA_FUNCTION_PARPORT_ECP; | |
2579 | ppcontrol = VIA_PARPORT_BIDIR; | |
2580 | break; | |
2581 | case 5: | |
2582 | printk(KERN_DEBUG "parport_pc: setting EPP+ECP mode\n"); | |
2583 | siofunc = VIA_FUNCTION_PARPORT_ECP; | |
2584 | ppcontrol = VIA_PARPORT_BIDIR|VIA_PARPORT_ECPEPP; | |
2585 | have_epp = 1; | |
2586 | break; | |
2587 | default: | |
2588 | printk(KERN_DEBUG "parport_pc: probing current configuration\n"); | |
2589 | siofunc = VIA_FUNCTION_PROBE; | |
2590 | break; | |
2591 | } | |
2592 | /* | |
2593 | * unlock super i/o configuration | |
2594 | */ | |
2595 | pci_read_config_byte(pdev, via->via_pci_superio_config_reg, &tmp); | |
2596 | tmp |= via->via_pci_superio_config_data; | |
2597 | pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp); | |
2598 | ||
2599 | /* Bits 1-0: Parallel Port Mode / Enable */ | |
2600 | outb(via->viacfg_function, VIA_CONFIG_INDEX); | |
2601 | tmp = inb (VIA_CONFIG_DATA); | |
2602 | /* Bit 5: EPP+ECP enable; bit 7: PS/2 bidirectional port enable */ | |
2603 | outb(via->viacfg_parport_control, VIA_CONFIG_INDEX); | |
2604 | tmp2 = inb (VIA_CONFIG_DATA); | |
2605 | if (siofunc == VIA_FUNCTION_PROBE) | |
2606 | { | |
2607 | siofunc = tmp & VIA_FUNCTION_PARPORT_DISABLE; | |
2608 | ppcontrol = tmp2; | |
2609 | } | |
2610 | else | |
2611 | { | |
2612 | tmp &= ~VIA_FUNCTION_PARPORT_DISABLE; | |
2613 | tmp |= siofunc; | |
2614 | outb(via->viacfg_function, VIA_CONFIG_INDEX); | |
2615 | outb(tmp, VIA_CONFIG_DATA); | |
2616 | tmp2 &= ~(VIA_PARPORT_BIDIR|VIA_PARPORT_ECPEPP); | |
2617 | tmp2 |= ppcontrol; | |
2618 | outb(via->viacfg_parport_control, VIA_CONFIG_INDEX); | |
2619 | outb(tmp2, VIA_CONFIG_DATA); | |
2620 | } | |
2621 | ||
2622 | /* Parallel Port I/O Base Address, bits 9-2 */ | |
2623 | outb(via->viacfg_parport_base, VIA_CONFIG_INDEX); | |
2624 | port1 = inb(VIA_CONFIG_DATA) << 2; | |
2625 | ||
2626 | printk (KERN_DEBUG "parport_pc: Current parallel port base: 0x%X\n",port1); | |
2627 | if ((port1 == 0x3BC) && have_epp) | |
2628 | { | |
2629 | outb(via->viacfg_parport_base, VIA_CONFIG_INDEX); | |
2630 | outb((0x378 >> 2), VIA_CONFIG_DATA); | |
2631 | printk(KERN_DEBUG "parport_pc: Parallel port base changed to 0x378\n"); | |
2632 | port1 = 0x378; | |
2633 | } | |
2634 | ||
2635 | /* | |
2636 | * lock super i/o configuration | |
2637 | */ | |
2638 | pci_read_config_byte(pdev, via->via_pci_superio_config_reg, &tmp); | |
2639 | tmp &= ~via->via_pci_superio_config_data; | |
2640 | pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp); | |
2641 | ||
2642 | if (siofunc == VIA_FUNCTION_PARPORT_DISABLE) { | |
2643 | printk(KERN_INFO "parport_pc: VIA parallel port disabled in BIOS\n"); | |
2644 | return 0; | |
2645 | } | |
2646 | ||
2647 | /* Bits 7-4: PnP Routing for Parallel Port IRQ */ | |
2648 | pci_read_config_byte(pdev, via->via_pci_parport_irq_reg, &tmp); | |
2649 | irq = ((tmp & VIA_IRQCONTROL_PARALLEL) >> 4); | |
2650 | ||
2651 | if (siofunc == VIA_FUNCTION_PARPORT_ECP) | |
2652 | { | |
2653 | /* Bits 3-2: PnP Routing for Parallel Port DMA */ | |
2654 | pci_read_config_byte(pdev, via->via_pci_parport_dma_reg, &tmp); | |
2655 | dma = ((tmp & VIA_DMACONTROL_PARALLEL) >> 2); | |
2656 | } | |
2657 | else | |
2658 | /* if ECP not enabled, DMA is not enabled, assumed bogus 'dma' value */ | |
2659 | dma = PARPORT_DMA_NONE; | |
2660 | ||
2661 | /* Let the user (or defaults) steer us away from interrupts and DMA */ | |
2662 | if (autoirq == PARPORT_IRQ_NONE) { | |
2663 | irq = PARPORT_IRQ_NONE; | |
2664 | dma = PARPORT_DMA_NONE; | |
2665 | } | |
2666 | if (autodma == PARPORT_DMA_NONE) | |
2667 | dma = PARPORT_DMA_NONE; | |
2668 | ||
2669 | switch (port1) { | |
2670 | case 0x3bc: port2 = 0x7bc; break; | |
2671 | case 0x378: port2 = 0x778; break; | |
2672 | case 0x278: port2 = 0x678; break; | |
2673 | default: | |
2674 | printk(KERN_INFO "parport_pc: Weird VIA parport base 0x%X, ignoring\n", | |
2675 | port1); | |
2676 | return 0; | |
2677 | } | |
2678 | ||
2679 | /* filter bogus IRQs */ | |
2680 | switch (irq) { | |
2681 | case 0: | |
2682 | case 2: | |
2683 | case 8: | |
2684 | case 13: | |
2685 | irq = PARPORT_IRQ_NONE; | |
2686 | break; | |
2687 | ||
2688 | default: /* do nothing */ | |
2689 | break; | |
2690 | } | |
2691 | ||
2692 | /* finally, do the probe with values obtained */ | |
c15a3837 | 2693 | if (parport_pc_probe_port (port1, port2, irq, dma, &pdev->dev)) { |
1da177e4 LT |
2694 | printk (KERN_INFO |
2695 | "parport_pc: VIA parallel port: io=0x%X", port1); | |
2696 | if (irq != PARPORT_IRQ_NONE) | |
2697 | printk (", irq=%d", irq); | |
2698 | if (dma != PARPORT_DMA_NONE) | |
2699 | printk (", dma=%d", dma); | |
2700 | printk ("\n"); | |
2701 | return 1; | |
2702 | } | |
2703 | ||
2704 | printk(KERN_WARNING "parport_pc: Strange, can't probe VIA parallel port: io=0x%X, irq=%d, dma=%d\n", | |
2705 | port1, irq, dma); | |
2706 | return 0; | |
2707 | } | |
2708 | ||
2709 | ||
2710 | enum parport_pc_sio_types { | |
2711 | sio_via_686a = 0, /* Via VT82C686A motherboard Super I/O */ | |
2712 | sio_via_8231, /* Via VT8231 south bridge integrated Super IO */ | |
2713 | sio_ite_8872, | |
2714 | last_sio | |
2715 | }; | |
2716 | ||
2717 | /* each element directly indexed from enum list, above */ | |
2718 | static struct parport_pc_superio { | |
a6767b7c MK |
2719 | int (*probe) (struct pci_dev *pdev, int autoirq, int autodma, |
2720 | const struct parport_pc_via_data *via); | |
2721 | const struct parport_pc_via_data *via; | |
1da177e4 LT |
2722 | } parport_pc_superio_info[] __devinitdata = { |
2723 | { sio_via_probe, &via_686a_data, }, | |
2724 | { sio_via_probe, &via_8231_data, }, | |
2725 | { sio_ite_8872_probe, NULL, }, | |
2726 | }; | |
2727 | ||
2728 | enum parport_pc_pci_cards { | |
2729 | siig_1p_10x = last_sio, | |
2730 | siig_2p_10x, | |
2731 | siig_1p_20x, | |
2732 | siig_2p_20x, | |
2733 | lava_parallel, | |
2734 | lava_parallel_dual_a, | |
2735 | lava_parallel_dual_b, | |
2736 | boca_ioppar, | |
2737 | plx_9050, | |
2738 | timedia_4078a, | |
2739 | timedia_4079h, | |
2740 | timedia_4085h, | |
2741 | timedia_4088a, | |
2742 | timedia_4089a, | |
2743 | timedia_4095a, | |
2744 | timedia_4096a, | |
2745 | timedia_4078u, | |
2746 | timedia_4079a, | |
2747 | timedia_4085u, | |
2748 | timedia_4079r, | |
2749 | timedia_4079s, | |
2750 | timedia_4079d, | |
2751 | timedia_4079e, | |
2752 | timedia_4079f, | |
2753 | timedia_9079a, | |
2754 | timedia_9079b, | |
2755 | timedia_9079c, | |
2756 | timedia_4006a, | |
2757 | timedia_4014, | |
2758 | timedia_4008a, | |
2759 | timedia_4018, | |
2760 | timedia_9018a, | |
2761 | syba_2p_epp, | |
2762 | syba_1p_ecp, | |
2763 | titan_010l, | |
85747f03 | 2764 | titan_1284p1, |
1da177e4 LT |
2765 | titan_1284p2, |
2766 | avlab_1p, | |
2767 | avlab_2p, | |
c140e110 | 2768 | oxsemi_952, |
1da177e4 LT |
2769 | oxsemi_954, |
2770 | oxsemi_840, | |
2771 | aks_0100, | |
2772 | mobility_pp, | |
2773 | netmos_9705, | |
2774 | netmos_9715, | |
2775 | netmos_9755, | |
2776 | netmos_9805, | |
2777 | netmos_9815, | |
1da177e4 LT |
2778 | }; |
2779 | ||
2780 | ||
2781 | /* each element directly indexed from enum list, above | |
2782 | * (but offset by last_sio) */ | |
2783 | static struct parport_pc_pci { | |
2784 | int numports; | |
2785 | struct { /* BAR (base address registers) numbers in the config | |
2786 | space header */ | |
2787 | int lo; | |
2788 | int hi; /* -1 if not there, >6 for offset-method (max | |
2789 | BAR is 6) */ | |
2790 | } addr[4]; | |
2791 | ||
2792 | /* If set, this is called immediately after pci_enable_device. | |
2793 | * If it returns non-zero, no probing will take place and the | |
2794 | * ports will not be used. */ | |
2795 | int (*preinit_hook) (struct pci_dev *pdev, int autoirq, int autodma); | |
2796 | ||
2797 | /* If set, this is called after probing for ports. If 'failed' | |
2798 | * is non-zero we couldn't use any of the ports. */ | |
2799 | void (*postinit_hook) (struct pci_dev *pdev, int failed); | |
96766a3c | 2800 | } cards[] = { |
1da177e4 LT |
2801 | /* siig_1p_10x */ { 1, { { 2, 3 }, } }, |
2802 | /* siig_2p_10x */ { 2, { { 2, 3 }, { 4, 5 }, } }, | |
2803 | /* siig_1p_20x */ { 1, { { 0, 1 }, } }, | |
2804 | /* siig_2p_20x */ { 2, { { 0, 1 }, { 2, 3 }, } }, | |
2805 | /* lava_parallel */ { 1, { { 0, -1 }, } }, | |
2806 | /* lava_parallel_dual_a */ { 1, { { 0, -1 }, } }, | |
2807 | /* lava_parallel_dual_b */ { 1, { { 0, -1 }, } }, | |
2808 | /* boca_ioppar */ { 1, { { 0, -1 }, } }, | |
2809 | /* plx_9050 */ { 2, { { 4, -1 }, { 5, -1 }, } }, | |
2810 | /* timedia_4078a */ { 1, { { 2, -1 }, } }, | |
2811 | /* timedia_4079h */ { 1, { { 2, 3 }, } }, | |
2812 | /* timedia_4085h */ { 2, { { 2, -1 }, { 4, -1 }, } }, | |
2813 | /* timedia_4088a */ { 2, { { 2, 3 }, { 4, 5 }, } }, | |
2814 | /* timedia_4089a */ { 2, { { 2, 3 }, { 4, 5 }, } }, | |
2815 | /* timedia_4095a */ { 2, { { 2, 3 }, { 4, 5 }, } }, | |
2816 | /* timedia_4096a */ { 2, { { 2, 3 }, { 4, 5 }, } }, | |
2817 | /* timedia_4078u */ { 1, { { 2, -1 }, } }, | |
2818 | /* timedia_4079a */ { 1, { { 2, 3 }, } }, | |
2819 | /* timedia_4085u */ { 2, { { 2, -1 }, { 4, -1 }, } }, | |
2820 | /* timedia_4079r */ { 1, { { 2, 3 }, } }, | |
2821 | /* timedia_4079s */ { 1, { { 2, 3 }, } }, | |
2822 | /* timedia_4079d */ { 1, { { 2, 3 }, } }, | |
2823 | /* timedia_4079e */ { 1, { { 2, 3 }, } }, | |
2824 | /* timedia_4079f */ { 1, { { 2, 3 }, } }, | |
2825 | /* timedia_9079a */ { 1, { { 2, 3 }, } }, | |
2826 | /* timedia_9079b */ { 1, { { 2, 3 }, } }, | |
2827 | /* timedia_9079c */ { 1, { { 2, 3 }, } }, | |
2828 | /* timedia_4006a */ { 1, { { 0, -1 }, } }, | |
2829 | /* timedia_4014 */ { 2, { { 0, -1 }, { 2, -1 }, } }, | |
2830 | /* timedia_4008a */ { 1, { { 0, 1 }, } }, | |
2831 | /* timedia_4018 */ { 2, { { 0, 1 }, { 2, 3 }, } }, | |
2832 | /* timedia_9018a */ { 2, { { 0, 1 }, { 2, 3 }, } }, | |
2833 | /* SYBA uses fixed offsets in | |
2834 | a 1K io window */ | |
2835 | /* syba_2p_epp AP138B */ { 2, { { 0, 0x078 }, { 0, 0x178 }, } }, | |
2836 | /* syba_1p_ecp W83787 */ { 1, { { 0, 0x078 }, } }, | |
2837 | /* titan_010l */ { 1, { { 3, -1 }, } }, | |
85747f03 | 2838 | /* titan_1284p1 */ { 1, { { 0, 1 }, } }, |
1da177e4 LT |
2839 | /* titan_1284p2 */ { 2, { { 0, 1 }, { 2, 3 }, } }, |
2840 | /* avlab_1p */ { 1, { { 0, 1}, } }, | |
2841 | /* avlab_2p */ { 2, { { 0, 1}, { 2, 3 },} }, | |
2842 | /* The Oxford Semi cards are unusual: 954 doesn't support ECP, | |
2843 | * and 840 locks up if you write 1 to bit 2! */ | |
c140e110 | 2844 | /* oxsemi_952 */ { 1, { { 0, 1 }, } }, |
1da177e4 LT |
2845 | /* oxsemi_954 */ { 1, { { 0, -1 }, } }, |
2846 | /* oxsemi_840 */ { 1, { { 0, -1 }, } }, | |
2847 | /* aks_0100 */ { 1, { { 0, -1 }, } }, | |
2848 | /* mobility_pp */ { 1, { { 0, 1 }, } }, | |
2849 | /* netmos_9705 */ { 1, { { 0, -1 }, } }, /* untested */ | |
2850 | /* netmos_9715 */ { 2, { { 0, 1 }, { 2, 3 },} }, /* untested */ | |
2851 | /* netmos_9755 */ { 2, { { 0, 1 }, { 2, 3 },} }, /* untested */ | |
2852 | /* netmos_9805 */ { 1, { { 0, -1 }, } }, /* untested */ | |
2853 | /* netmos_9815 */ { 2, { { 0, -1 }, { 2, -1 }, } }, /* untested */ | |
1da177e4 LT |
2854 | }; |
2855 | ||
a6767b7c | 2856 | static const struct pci_device_id parport_pc_pci_tbl[] = { |
1da177e4 LT |
2857 | /* Super-IO onboard chips */ |
2858 | { 0x1106, 0x0686, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_686a }, | |
2859 | { 0x1106, 0x8231, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_8231 }, | |
2860 | { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872, | |
2861 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_ite_8872 }, | |
2862 | ||
2863 | /* PCI cards */ | |
2864 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_10x, | |
2865 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_10x }, | |
2866 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_10x, | |
2867 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_10x }, | |
2868 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_20x, | |
2869 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_20x }, | |
2870 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_20x, | |
2871 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_20x }, | |
2872 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PARALLEL, | |
2873 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel }, | |
2874 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_A, | |
2875 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_a }, | |
2876 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_B, | |
2877 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_b }, | |
2878 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_BOCA_IOPPAR, | |
2879 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, boca_ioppar }, | |
2880 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, | |
2881 | PCI_SUBVENDOR_ID_EXSYS, PCI_SUBDEVICE_ID_EXSYS_4014, 0,0, plx_9050 }, | |
2882 | /* PCI_VENDOR_ID_TIMEDIA/SUNIX has many differing cards ...*/ | |
2883 | { 0x1409, 0x7168, 0x1409, 0x4078, 0, 0, timedia_4078a }, | |
2884 | { 0x1409, 0x7168, 0x1409, 0x4079, 0, 0, timedia_4079h }, | |
2885 | { 0x1409, 0x7168, 0x1409, 0x4085, 0, 0, timedia_4085h }, | |
2886 | { 0x1409, 0x7168, 0x1409, 0x4088, 0, 0, timedia_4088a }, | |
2887 | { 0x1409, 0x7168, 0x1409, 0x4089, 0, 0, timedia_4089a }, | |
2888 | { 0x1409, 0x7168, 0x1409, 0x4095, 0, 0, timedia_4095a }, | |
2889 | { 0x1409, 0x7168, 0x1409, 0x4096, 0, 0, timedia_4096a }, | |
2890 | { 0x1409, 0x7168, 0x1409, 0x5078, 0, 0, timedia_4078u }, | |
2891 | { 0x1409, 0x7168, 0x1409, 0x5079, 0, 0, timedia_4079a }, | |
2892 | { 0x1409, 0x7168, 0x1409, 0x5085, 0, 0, timedia_4085u }, | |
2893 | { 0x1409, 0x7168, 0x1409, 0x6079, 0, 0, timedia_4079r }, | |
2894 | { 0x1409, 0x7168, 0x1409, 0x7079, 0, 0, timedia_4079s }, | |
2895 | { 0x1409, 0x7168, 0x1409, 0x8079, 0, 0, timedia_4079d }, | |
2896 | { 0x1409, 0x7168, 0x1409, 0x9079, 0, 0, timedia_4079e }, | |
2897 | { 0x1409, 0x7168, 0x1409, 0xa079, 0, 0, timedia_4079f }, | |
2898 | { 0x1409, 0x7168, 0x1409, 0xb079, 0, 0, timedia_9079a }, | |
2899 | { 0x1409, 0x7168, 0x1409, 0xc079, 0, 0, timedia_9079b }, | |
2900 | { 0x1409, 0x7168, 0x1409, 0xd079, 0, 0, timedia_9079c }, | |
2901 | { 0x1409, 0x7268, 0x1409, 0x0101, 0, 0, timedia_4006a }, | |
2902 | { 0x1409, 0x7268, 0x1409, 0x0102, 0, 0, timedia_4014 }, | |
2903 | { 0x1409, 0x7268, 0x1409, 0x0103, 0, 0, timedia_4008a }, | |
2904 | { 0x1409, 0x7268, 0x1409, 0x0104, 0, 0, timedia_4018 }, | |
2905 | { 0x1409, 0x7268, 0x1409, 0x9018, 0, 0, timedia_9018a }, | |
2906 | { 0x14f2, 0x0121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, mobility_pp }, | |
2907 | { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_2P_EPP, | |
2908 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_2p_epp }, | |
2909 | { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_1P_ECP, | |
2910 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_1p_ecp }, | |
2911 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_010L, | |
2912 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, titan_010l }, | |
85747f03 | 2913 | { 0x9710, 0x9805, 0x1000, 0x0010, 0, 0, titan_1284p1 }, |
1da177e4 LT |
2914 | { 0x9710, 0x9815, 0x1000, 0x0020, 0, 0, titan_1284p2 }, |
2915 | /* PCI_VENDOR_ID_AVLAB/Intek21 has another bunch of cards ...*/ | |
2916 | { 0x14db, 0x2120, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1p}, /* AFAVLAB_TK9902 */ | |
2917 | { 0x14db, 0x2121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2p}, | |
c140e110 RU |
2918 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952PP, |
2919 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_952 }, | |
1da177e4 LT |
2920 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954PP, |
2921 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_954 }, | |
2922 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_12PCI840, | |
2923 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_840 }, | |
2924 | { PCI_VENDOR_ID_AKS, PCI_DEVICE_ID_AKS_ALADDINCARD, | |
2925 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, aks_0100 }, | |
2926 | /* NetMos communication controllers */ | |
2927 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9705, | |
2928 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9705 }, | |
2929 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9715, | |
2930 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9715 }, | |
2931 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9755, | |
2932 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9755 }, | |
2933 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9805, | |
2934 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9805 }, | |
2935 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9815, | |
2936 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9815 }, | |
1da177e4 LT |
2937 | { 0, } /* terminate list */ |
2938 | }; | |
2939 | MODULE_DEVICE_TABLE(pci,parport_pc_pci_tbl); | |
2940 | ||
2941 | struct pci_parport_data { | |
2942 | int num; | |
2943 | struct parport *ports[2]; | |
2944 | }; | |
2945 | ||
2946 | static int parport_pc_pci_probe (struct pci_dev *dev, | |
2947 | const struct pci_device_id *id) | |
2948 | { | |
2949 | int err, count, n, i = id->driver_data; | |
2950 | struct pci_parport_data *data; | |
2951 | ||
2952 | if (i < last_sio) | |
2953 | /* This is an onboard Super-IO and has already been probed */ | |
2954 | return 0; | |
2955 | ||
2956 | /* This is a PCI card */ | |
2957 | i -= last_sio; | |
2958 | count = 0; | |
2959 | if ((err = pci_enable_device (dev)) != 0) | |
2960 | return err; | |
2961 | ||
2962 | data = kmalloc(sizeof(struct pci_parport_data), GFP_KERNEL); | |
2963 | if (!data) | |
2964 | return -ENOMEM; | |
2965 | ||
2966 | if (cards[i].preinit_hook && | |
2967 | cards[i].preinit_hook (dev, PARPORT_IRQ_NONE, PARPORT_DMA_NONE)) { | |
2968 | kfree(data); | |
2969 | return -ENODEV; | |
2970 | } | |
2971 | ||
2972 | for (n = 0; n < cards[i].numports; n++) { | |
2973 | int lo = cards[i].addr[n].lo; | |
2974 | int hi = cards[i].addr[n].hi; | |
2975 | unsigned long io_lo, io_hi; | |
2976 | io_lo = pci_resource_start (dev, lo); | |
2977 | io_hi = 0; | |
2978 | if ((hi >= 0) && (hi <= 6)) | |
2979 | io_hi = pci_resource_start (dev, hi); | |
2980 | else if (hi > 6) | |
2981 | io_lo += hi; /* Reinterpret the meaning of | |
2982 | "hi" as an offset (see SYBA | |
2983 | def.) */ | |
2984 | /* TODO: test if sharing interrupts works */ | |
2985 | printk (KERN_DEBUG "PCI parallel port detected: %04x:%04x, " | |
2986 | "I/O at %#lx(%#lx)\n", | |
2987 | parport_pc_pci_tbl[i + last_sio].vendor, | |
2988 | parport_pc_pci_tbl[i + last_sio].device, io_lo, io_hi); | |
2989 | data->ports[count] = | |
2990 | parport_pc_probe_port (io_lo, io_hi, PARPORT_IRQ_NONE, | |
c15a3837 | 2991 | PARPORT_DMA_NONE, &dev->dev); |
1da177e4 LT |
2992 | if (data->ports[count]) |
2993 | count++; | |
2994 | } | |
2995 | ||
2996 | data->num = count; | |
2997 | ||
2998 | if (cards[i].postinit_hook) | |
2999 | cards[i].postinit_hook (dev, count == 0); | |
3000 | ||
3001 | if (count) { | |
3002 | pci_set_drvdata(dev, data); | |
3003 | return 0; | |
3004 | } | |
3005 | ||
3006 | kfree(data); | |
3007 | ||
3008 | return -ENODEV; | |
3009 | } | |
3010 | ||
3011 | static void __devexit parport_pc_pci_remove(struct pci_dev *dev) | |
3012 | { | |
3013 | struct pci_parport_data *data = pci_get_drvdata(dev); | |
3014 | int i; | |
3015 | ||
3016 | pci_set_drvdata(dev, NULL); | |
3017 | ||
3018 | if (data) { | |
3019 | for (i = data->num - 1; i >= 0; i--) | |
3020 | parport_pc_unregister_port(data->ports[i]); | |
3021 | ||
3022 | kfree(data); | |
3023 | } | |
3024 | } | |
3025 | ||
3026 | static struct pci_driver parport_pc_pci_driver = { | |
3027 | .name = "parport_pc", | |
3028 | .id_table = parport_pc_pci_tbl, | |
3029 | .probe = parport_pc_pci_probe, | |
3030 | .remove = __devexit_p(parport_pc_pci_remove), | |
3031 | }; | |
3032 | ||
3033 | static int __init parport_pc_init_superio (int autoirq, int autodma) | |
3034 | { | |
3035 | const struct pci_device_id *id; | |
3036 | struct pci_dev *pdev = NULL; | |
3037 | int ret = 0; | |
3038 | ||
c9d8073f | 3039 | for_each_pci_dev(pdev) { |
75865858 | 3040 | id = pci_match_id(parport_pc_pci_tbl, pdev); |
1da177e4 LT |
3041 | if (id == NULL || id->driver_data >= last_sio) |
3042 | continue; | |
3043 | ||
3044 | if (parport_pc_superio_info[id->driver_data].probe | |
3045 | (pdev, autoirq, autodma,parport_pc_superio_info[id->driver_data].via)) { | |
3046 | ret++; | |
3047 | } | |
3048 | } | |
3049 | ||
3050 | return ret; /* number of devices found */ | |
3051 | } | |
3052 | #else | |
3053 | static struct pci_driver parport_pc_pci_driver; | |
3054 | static int __init parport_pc_init_superio(int autoirq, int autodma) {return 0;} | |
3055 | #endif /* CONFIG_PCI */ | |
3056 | ||
3057 | ||
3058 | static const struct pnp_device_id parport_pc_pnp_tbl[] = { | |
3059 | /* Standard LPT Printer Port */ | |
3060 | {.id = "PNP0400", .driver_data = 0}, | |
3061 | /* ECP Printer Port */ | |
3062 | {.id = "PNP0401", .driver_data = 0}, | |
3063 | { } | |
3064 | }; | |
3065 | ||
3066 | MODULE_DEVICE_TABLE(pnp,parport_pc_pnp_tbl); | |
3067 | ||
3068 | static int parport_pc_pnp_probe(struct pnp_dev *dev, const struct pnp_device_id *id) | |
3069 | { | |
3070 | struct parport *pdata; | |
3071 | unsigned long io_lo, io_hi; | |
3072 | int dma, irq; | |
3073 | ||
3074 | if (pnp_port_valid(dev,0) && | |
3075 | !(pnp_port_flags(dev,0) & IORESOURCE_DISABLED)) { | |
3076 | io_lo = pnp_port_start(dev,0); | |
3077 | } else | |
3078 | return -EINVAL; | |
3079 | ||
3080 | if (pnp_port_valid(dev,1) && | |
3081 | !(pnp_port_flags(dev,1) & IORESOURCE_DISABLED)) { | |
3082 | io_hi = pnp_port_start(dev,1); | |
3083 | } else | |
3084 | io_hi = 0; | |
3085 | ||
3086 | if (pnp_irq_valid(dev,0) && | |
3087 | !(pnp_irq_flags(dev,0) & IORESOURCE_DISABLED)) { | |
3088 | irq = pnp_irq(dev,0); | |
3089 | } else | |
3090 | irq = PARPORT_IRQ_NONE; | |
3091 | ||
3092 | if (pnp_dma_valid(dev,0) && | |
3093 | !(pnp_dma_flags(dev,0) & IORESOURCE_DISABLED)) { | |
3094 | dma = pnp_dma(dev,0); | |
3095 | } else | |
3096 | dma = PARPORT_DMA_NONE; | |
3097 | ||
c15a3837 DB |
3098 | dev_info(&dev->dev, "reported by %s\n", dev->protocol->name); |
3099 | if (!(pdata = parport_pc_probe_port (io_lo, io_hi, irq, dma, &dev->dev))) | |
1da177e4 LT |
3100 | return -ENODEV; |
3101 | ||
3102 | pnp_set_drvdata(dev,pdata); | |
3103 | return 0; | |
3104 | } | |
3105 | ||
3106 | static void parport_pc_pnp_remove(struct pnp_dev *dev) | |
3107 | { | |
3108 | struct parport *pdata = (struct parport *)pnp_get_drvdata(dev); | |
3109 | if (!pdata) | |
3110 | return; | |
3111 | ||
3112 | parport_pc_unregister_port(pdata); | |
3113 | } | |
3114 | ||
3115 | /* we only need the pnp layer to activate the device, at least for now */ | |
3116 | static struct pnp_driver parport_pc_pnp_driver = { | |
3117 | .name = "parport_pc", | |
3118 | .id_table = parport_pc_pnp_tbl, | |
3119 | .probe = parport_pc_pnp_probe, | |
3120 | .remove = parport_pc_pnp_remove, | |
3121 | }; | |
3122 | ||
3123 | ||
a7d801af JD |
3124 | static int __devinit parport_pc_platform_probe(struct platform_device *pdev) |
3125 | { | |
3126 | /* Always succeed, the actual probing is done in | |
3127 | * parport_pc_probe_port(). */ | |
3128 | return 0; | |
3129 | } | |
3130 | ||
3131 | static struct platform_driver parport_pc_platform_driver = { | |
3132 | .driver = { | |
3133 | .owner = THIS_MODULE, | |
3134 | .name = "parport_pc", | |
3135 | }, | |
3136 | .probe = parport_pc_platform_probe, | |
3137 | }; | |
3138 | ||
1da177e4 LT |
3139 | /* This is called by parport_pc_find_nonpci_ports (in asm/parport.h) */ |
3140 | static int __devinit __attribute__((unused)) | |
3141 | parport_pc_find_isa_ports (int autoirq, int autodma) | |
3142 | { | |
3143 | int count = 0; | |
3144 | ||
3145 | if (parport_pc_probe_port(0x3bc, 0x7bc, autoirq, autodma, NULL)) | |
3146 | count++; | |
3147 | if (parport_pc_probe_port(0x378, 0x778, autoirq, autodma, NULL)) | |
3148 | count++; | |
3149 | if (parport_pc_probe_port(0x278, 0x678, autoirq, autodma, NULL)) | |
3150 | count++; | |
3151 | ||
3152 | return count; | |
3153 | } | |
3154 | ||
3155 | /* This function is called by parport_pc_init if the user didn't | |
3156 | * specify any ports to probe. Its job is to find some ports. Order | |
3157 | * is important here -- we want ISA ports to be registered first, | |
3158 | * followed by PCI cards (for least surprise), but before that we want | |
3159 | * to do chipset-specific tests for some onboard ports that we know | |
3160 | * about. | |
3161 | * | |
3162 | * autoirq is PARPORT_IRQ_NONE, PARPORT_IRQ_AUTO, or PARPORT_IRQ_PROBEONLY | |
3163 | * autodma is PARPORT_DMA_NONE or PARPORT_DMA_AUTO | |
3164 | */ | |
7597fee3 | 3165 | static void __init parport_pc_find_ports (int autoirq, int autodma) |
1da177e4 | 3166 | { |
7597fee3 | 3167 | int count = 0, err; |
1da177e4 LT |
3168 | |
3169 | #ifdef CONFIG_PARPORT_PC_SUPERIO | |
3170 | detect_and_report_winbond (); | |
3171 | detect_and_report_smsc (); | |
3172 | #endif | |
3173 | ||
3174 | /* Onboard SuperIO chipsets that show themselves on the PCI bus. */ | |
3175 | count += parport_pc_init_superio (autoirq, autodma); | |
3176 | ||
3177 | /* PnP ports, skip detection if SuperIO already found them */ | |
3178 | if (!count) { | |
7597fee3 BH |
3179 | err = pnp_register_driver (&parport_pc_pnp_driver); |
3180 | if (!err) | |
1da177e4 | 3181 | pnp_registered_parport = 1; |
1da177e4 LT |
3182 | } |
3183 | ||
3184 | /* ISA ports and whatever (see asm/parport.h). */ | |
7597fee3 | 3185 | parport_pc_find_nonpci_ports (autoirq, autodma); |
1da177e4 | 3186 | |
7597fee3 BH |
3187 | err = pci_register_driver (&parport_pc_pci_driver); |
3188 | if (!err) | |
3189 | pci_registered_parport = 1; | |
1da177e4 LT |
3190 | } |
3191 | ||
3192 | /* | |
3193 | * Piles of crap below pretend to be a parser for module and kernel | |
3194 | * parameters. Say "thank you" to whoever had come up with that | |
3195 | * syntax and keep in mind that code below is a cleaned up version. | |
3196 | */ | |
3197 | ||
3198 | static int __initdata io[PARPORT_PC_MAX_PORTS+1] = { [0 ... PARPORT_PC_MAX_PORTS] = 0 }; | |
3199 | static int __initdata io_hi[PARPORT_PC_MAX_PORTS+1] = | |
3200 | { [0 ... PARPORT_PC_MAX_PORTS] = PARPORT_IOHI_AUTO }; | |
3201 | static int __initdata dmaval[PARPORT_PC_MAX_PORTS] = { [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_DMA_NONE }; | |
3202 | static int __initdata irqval[PARPORT_PC_MAX_PORTS] = { [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_IRQ_PROBEONLY }; | |
3203 | ||
3204 | static int __init parport_parse_param(const char *s, int *val, | |
3205 | int automatic, int none, int nofifo) | |
3206 | { | |
3207 | if (!s) | |
3208 | return 0; | |
3209 | if (!strncmp(s, "auto", 4)) | |
3210 | *val = automatic; | |
3211 | else if (!strncmp(s, "none", 4)) | |
3212 | *val = none; | |
3213 | else if (nofifo && !strncmp(s, "nofifo", 4)) | |
3214 | *val = nofifo; | |
3215 | else { | |
3216 | char *ep; | |
3217 | unsigned long r = simple_strtoul(s, &ep, 0); | |
3218 | if (ep != s) | |
3219 | *val = r; | |
3220 | else { | |
3221 | printk(KERN_ERR "parport: bad specifier `%s'\n", s); | |
3222 | return -1; | |
3223 | } | |
3224 | } | |
3225 | return 0; | |
3226 | } | |
3227 | ||
3228 | static int __init parport_parse_irq(const char *irqstr, int *val) | |
3229 | { | |
3230 | return parport_parse_param(irqstr, val, PARPORT_IRQ_AUTO, | |
3231 | PARPORT_IRQ_NONE, 0); | |
3232 | } | |
3233 | ||
3234 | static int __init parport_parse_dma(const char *dmastr, int *val) | |
3235 | { | |
3236 | return parport_parse_param(dmastr, val, PARPORT_DMA_AUTO, | |
3237 | PARPORT_DMA_NONE, PARPORT_DMA_NOFIFO); | |
3238 | } | |
3239 | ||
3240 | #ifdef CONFIG_PCI | |
3241 | static int __init parport_init_mode_setup(char *str) | |
3242 | { | |
3243 | printk(KERN_DEBUG "parport_pc.c: Specified parameter parport_init_mode=%s\n", str); | |
3244 | ||
3245 | if (!strcmp (str, "spp")) | |
3246 | parport_init_mode=1; | |
3247 | if (!strcmp (str, "ps2")) | |
3248 | parport_init_mode=2; | |
3249 | if (!strcmp (str, "epp")) | |
3250 | parport_init_mode=3; | |
3251 | if (!strcmp (str, "ecp")) | |
3252 | parport_init_mode=4; | |
3253 | if (!strcmp (str, "ecpepp")) | |
3254 | parport_init_mode=5; | |
3255 | return 1; | |
3256 | } | |
3257 | #endif | |
3258 | ||
3259 | #ifdef MODULE | |
3260 | static const char *irq[PARPORT_PC_MAX_PORTS]; | |
3261 | static const char *dma[PARPORT_PC_MAX_PORTS]; | |
3262 | ||
3263 | MODULE_PARM_DESC(io, "Base I/O address (SPP regs)"); | |
3264 | module_param_array(io, int, NULL, 0); | |
3265 | MODULE_PARM_DESC(io_hi, "Base I/O address (ECR)"); | |
3266 | module_param_array(io_hi, int, NULL, 0); | |
3267 | MODULE_PARM_DESC(irq, "IRQ line"); | |
3268 | module_param_array(irq, charp, NULL, 0); | |
3269 | MODULE_PARM_DESC(dma, "DMA channel"); | |
3270 | module_param_array(dma, charp, NULL, 0); | |
3271 | #if defined(CONFIG_PARPORT_PC_SUPERIO) || \ | |
3272 | (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO)) | |
3273 | MODULE_PARM_DESC(verbose_probing, "Log chit-chat during initialisation"); | |
3274 | module_param(verbose_probing, int, 0644); | |
3275 | #endif | |
3276 | #ifdef CONFIG_PCI | |
3277 | static char *init_mode; | |
3278 | MODULE_PARM_DESC(init_mode, "Initialise mode for VIA VT8231 port (spp, ps2, epp, ecp or ecpepp)"); | |
3279 | module_param(init_mode, charp, 0); | |
3280 | #endif | |
3281 | ||
3282 | static int __init parse_parport_params(void) | |
3283 | { | |
3284 | unsigned int i; | |
3285 | int val; | |
3286 | ||
3287 | #ifdef CONFIG_PCI | |
3288 | if (init_mode) | |
3289 | parport_init_mode_setup(init_mode); | |
3290 | #endif | |
3291 | ||
3292 | for (i = 0; i < PARPORT_PC_MAX_PORTS && io[i]; i++) { | |
3293 | if (parport_parse_irq(irq[i], &val)) | |
3294 | return 1; | |
3295 | irqval[i] = val; | |
3296 | if (parport_parse_dma(dma[i], &val)) | |
3297 | return 1; | |
3298 | dmaval[i] = val; | |
3299 | } | |
3300 | if (!io[0]) { | |
3301 | /* The user can make us use any IRQs or DMAs we find. */ | |
3302 | if (irq[0] && !parport_parse_irq(irq[0], &val)) | |
3303 | switch (val) { | |
3304 | case PARPORT_IRQ_NONE: | |
3305 | case PARPORT_IRQ_AUTO: | |
3306 | irqval[0] = val; | |
3307 | break; | |
3308 | default: | |
3309 | printk (KERN_WARNING | |
3310 | "parport_pc: irq specified " | |
3311 | "without base address. Use 'io=' " | |
3312 | "to specify one\n"); | |
3313 | } | |
3314 | ||
3315 | if (dma[0] && !parport_parse_dma(dma[0], &val)) | |
3316 | switch (val) { | |
3317 | case PARPORT_DMA_NONE: | |
3318 | case PARPORT_DMA_AUTO: | |
3319 | dmaval[0] = val; | |
3320 | break; | |
3321 | default: | |
3322 | printk (KERN_WARNING | |
3323 | "parport_pc: dma specified " | |
3324 | "without base address. Use 'io=' " | |
3325 | "to specify one\n"); | |
3326 | } | |
3327 | } | |
3328 | return 0; | |
3329 | } | |
3330 | ||
3331 | #else | |
3332 | ||
3333 | static int parport_setup_ptr __initdata = 0; | |
3334 | ||
3335 | /* | |
3336 | * Acceptable parameters: | |
3337 | * | |
3338 | * parport=0 | |
3339 | * parport=auto | |
3340 | * parport=0xBASE[,IRQ[,DMA]] | |
3341 | * | |
3342 | * IRQ/DMA may be numeric or 'auto' or 'none' | |
3343 | */ | |
3344 | static int __init parport_setup (char *str) | |
3345 | { | |
3346 | char *endptr; | |
3347 | char *sep; | |
3348 | int val; | |
3349 | ||
3350 | if (!str || !*str || (*str == '0' && !*(str+1))) { | |
3351 | /* Disable parport if "parport=0" in cmdline */ | |
3352 | io[0] = PARPORT_DISABLE; | |
3353 | return 1; | |
3354 | } | |
3355 | ||
3356 | if (!strncmp (str, "auto", 4)) { | |
3357 | irqval[0] = PARPORT_IRQ_AUTO; | |
3358 | dmaval[0] = PARPORT_DMA_AUTO; | |
3359 | return 1; | |
3360 | } | |
3361 | ||
3362 | val = simple_strtoul (str, &endptr, 0); | |
3363 | if (endptr == str) { | |
3364 | printk (KERN_WARNING "parport=%s not understood\n", str); | |
3365 | return 1; | |
3366 | } | |
3367 | ||
3368 | if (parport_setup_ptr == PARPORT_PC_MAX_PORTS) { | |
3369 | printk(KERN_ERR "parport=%s ignored, too many ports\n", str); | |
3370 | return 1; | |
3371 | } | |
3372 | ||
3373 | io[parport_setup_ptr] = val; | |
3374 | irqval[parport_setup_ptr] = PARPORT_IRQ_NONE; | |
3375 | dmaval[parport_setup_ptr] = PARPORT_DMA_NONE; | |
3376 | ||
3377 | sep = strchr(str, ','); | |
3378 | if (sep++) { | |
3379 | if (parport_parse_irq(sep, &val)) | |
3380 | return 1; | |
3381 | irqval[parport_setup_ptr] = val; | |
3382 | sep = strchr(sep, ','); | |
3383 | if (sep++) { | |
3384 | if (parport_parse_dma(sep, &val)) | |
3385 | return 1; | |
3386 | dmaval[parport_setup_ptr] = val; | |
3387 | } | |
3388 | } | |
3389 | parport_setup_ptr++; | |
3390 | return 1; | |
3391 | } | |
3392 | ||
3393 | static int __init parse_parport_params(void) | |
3394 | { | |
3395 | return io[0] == PARPORT_DISABLE; | |
3396 | } | |
3397 | ||
3398 | __setup ("parport=", parport_setup); | |
3399 | ||
3400 | /* | |
3401 | * Acceptable parameters: | |
3402 | * | |
3403 | * parport_init_mode=[spp|ps2|epp|ecp|ecpepp] | |
3404 | */ | |
3405 | #ifdef CONFIG_PCI | |
3406 | __setup("parport_init_mode=",parport_init_mode_setup); | |
3407 | #endif | |
3408 | #endif | |
3409 | ||
3410 | /* "Parser" ends here */ | |
3411 | ||
3412 | static int __init parport_pc_init(void) | |
3413 | { | |
a7d801af JD |
3414 | int err; |
3415 | ||
1da177e4 LT |
3416 | if (parse_parport_params()) |
3417 | return -EINVAL; | |
3418 | ||
a7d801af JD |
3419 | err = platform_driver_register(&parport_pc_platform_driver); |
3420 | if (err) | |
3421 | return err; | |
3422 | ||
1da177e4 LT |
3423 | if (io[0]) { |
3424 | int i; | |
3425 | /* Only probe the ports we were given. */ | |
3426 | user_specified = 1; | |
3427 | for (i = 0; i < PARPORT_PC_MAX_PORTS; i++) { | |
3428 | if (!io[i]) | |
3429 | break; | |
3430 | if ((io_hi[i]) == PARPORT_IOHI_AUTO) | |
3431 | io_hi[i] = 0x400 + io[i]; | |
7597fee3 BH |
3432 | parport_pc_probe_port(io[i], io_hi[i], |
3433 | irqval[i], dmaval[i], NULL); | |
1da177e4 LT |
3434 | } |
3435 | } else | |
7597fee3 | 3436 | parport_pc_find_ports (irqval[0], dmaval[0]); |
1da177e4 LT |
3437 | |
3438 | return 0; | |
3439 | } | |
3440 | ||
3441 | static void __exit parport_pc_exit(void) | |
3442 | { | |
3443 | if (pci_registered_parport) | |
3444 | pci_unregister_driver (&parport_pc_pci_driver); | |
3445 | if (pnp_registered_parport) | |
3446 | pnp_unregister_driver (&parport_pc_pnp_driver); | |
a7d801af | 3447 | platform_driver_unregister(&parport_pc_platform_driver); |
1da177e4 LT |
3448 | |
3449 | spin_lock(&ports_lock); | |
3450 | while (!list_empty(&ports_list)) { | |
3451 | struct parport_pc_private *priv; | |
3452 | struct parport *port; | |
3453 | priv = list_entry(ports_list.next, | |
3454 | struct parport_pc_private, list); | |
3455 | port = priv->port; | |
a7d801af JD |
3456 | if (port->dev && port->dev->bus == &platform_bus_type) |
3457 | platform_device_unregister( | |
3458 | to_platform_device(port->dev)); | |
1da177e4 LT |
3459 | spin_unlock(&ports_lock); |
3460 | parport_pc_unregister_port(port); | |
3461 | spin_lock(&ports_lock); | |
3462 | } | |
3463 | spin_unlock(&ports_lock); | |
3464 | } | |
3465 | ||
3466 | MODULE_AUTHOR("Phil Blundell, Tim Waugh, others"); | |
3467 | MODULE_DESCRIPTION("PC-style parallel port driver"); | |
3468 | MODULE_LICENSE("GPL"); | |
3469 | module_init(parport_pc_init) | |
3470 | module_exit(parport_pc_exit) |