Commit | Line | Data |
---|---|---|
94e61088 | 1 | #include <linux/delay.h> |
1da177e4 LT |
2 | #include <linux/pci.h> |
3 | #include <linux/module.h> | |
f6a57033 | 4 | #include <linux/sched.h> |
1da177e4 | 5 | #include <linux/ioport.h> |
7ea7e98f | 6 | #include <linux/wait.h> |
1da177e4 | 7 | |
48b19148 AB |
8 | #include "pci.h" |
9 | ||
1da177e4 LT |
10 | /* |
11 | * This interrupt-safe spinlock protects all accesses to PCI | |
12 | * configuration space. | |
13 | */ | |
14 | ||
15 | static DEFINE_SPINLOCK(pci_lock); | |
16 | ||
17 | /* | |
18 | * Wrappers for all PCI configuration access functions. They just check | |
19 | * alignment, do locking and call the low-level functions pointed to | |
20 | * by pci_dev->ops. | |
21 | */ | |
22 | ||
23 | #define PCI_byte_BAD 0 | |
24 | #define PCI_word_BAD (pos & 1) | |
25 | #define PCI_dword_BAD (pos & 3) | |
26 | ||
27 | #define PCI_OP_READ(size,type,len) \ | |
28 | int pci_bus_read_config_##size \ | |
29 | (struct pci_bus *bus, unsigned int devfn, int pos, type *value) \ | |
30 | { \ | |
31 | int res; \ | |
32 | unsigned long flags; \ | |
33 | u32 data = 0; \ | |
34 | if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \ | |
35 | spin_lock_irqsave(&pci_lock, flags); \ | |
36 | res = bus->ops->read(bus, devfn, pos, len, &data); \ | |
37 | *value = (type)data; \ | |
38 | spin_unlock_irqrestore(&pci_lock, flags); \ | |
39 | return res; \ | |
40 | } | |
41 | ||
42 | #define PCI_OP_WRITE(size,type,len) \ | |
43 | int pci_bus_write_config_##size \ | |
44 | (struct pci_bus *bus, unsigned int devfn, int pos, type value) \ | |
45 | { \ | |
46 | int res; \ | |
47 | unsigned long flags; \ | |
48 | if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \ | |
49 | spin_lock_irqsave(&pci_lock, flags); \ | |
50 | res = bus->ops->write(bus, devfn, pos, len, value); \ | |
51 | spin_unlock_irqrestore(&pci_lock, flags); \ | |
52 | return res; \ | |
53 | } | |
54 | ||
55 | PCI_OP_READ(byte, u8, 1) | |
56 | PCI_OP_READ(word, u16, 2) | |
57 | PCI_OP_READ(dword, u32, 4) | |
58 | PCI_OP_WRITE(byte, u8, 1) | |
59 | PCI_OP_WRITE(word, u16, 2) | |
60 | PCI_OP_WRITE(dword, u32, 4) | |
61 | ||
62 | EXPORT_SYMBOL(pci_bus_read_config_byte); | |
63 | EXPORT_SYMBOL(pci_bus_read_config_word); | |
64 | EXPORT_SYMBOL(pci_bus_read_config_dword); | |
65 | EXPORT_SYMBOL(pci_bus_write_config_byte); | |
66 | EXPORT_SYMBOL(pci_bus_write_config_word); | |
67 | EXPORT_SYMBOL(pci_bus_write_config_dword); | |
e04b0ea2 | 68 | |
a72b46c3 HY |
69 | /** |
70 | * pci_bus_set_ops - Set raw operations of pci bus | |
71 | * @bus: pci bus struct | |
72 | * @ops: new raw operations | |
73 | * | |
74 | * Return previous raw operations | |
75 | */ | |
76 | struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops) | |
77 | { | |
78 | struct pci_ops *old_ops; | |
79 | unsigned long flags; | |
80 | ||
81 | spin_lock_irqsave(&pci_lock, flags); | |
82 | old_ops = bus->ops; | |
83 | bus->ops = ops; | |
84 | spin_unlock_irqrestore(&pci_lock, flags); | |
85 | return old_ops; | |
86 | } | |
87 | EXPORT_SYMBOL(pci_bus_set_ops); | |
287d19ce SH |
88 | |
89 | /** | |
90 | * pci_read_vpd - Read one entry from Vital Product Data | |
91 | * @dev: pci device struct | |
92 | * @pos: offset in vpd space | |
93 | * @count: number of bytes to read | |
94 | * @buf: pointer to where to store result | |
95 | * | |
96 | */ | |
97 | ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf) | |
98 | { | |
99 | if (!dev->vpd || !dev->vpd->ops) | |
100 | return -ENODEV; | |
101 | return dev->vpd->ops->read(dev, pos, count, buf); | |
102 | } | |
103 | EXPORT_SYMBOL(pci_read_vpd); | |
104 | ||
105 | /** | |
106 | * pci_write_vpd - Write entry to Vital Product Data | |
107 | * @dev: pci device struct | |
108 | * @pos: offset in vpd space | |
cffb2faf RD |
109 | * @count: number of bytes to write |
110 | * @buf: buffer containing write data | |
287d19ce SH |
111 | * |
112 | */ | |
113 | ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf) | |
114 | { | |
115 | if (!dev->vpd || !dev->vpd->ops) | |
116 | return -ENODEV; | |
117 | return dev->vpd->ops->write(dev, pos, count, buf); | |
118 | } | |
119 | EXPORT_SYMBOL(pci_write_vpd); | |
120 | ||
7ea7e98f MW |
121 | /* |
122 | * The following routines are to prevent the user from accessing PCI config | |
123 | * space when it's unsafe to do so. Some devices require this during BIST and | |
124 | * we're required to prevent it during D-state transitions. | |
125 | * | |
126 | * We have a bit per device to indicate it's blocked and a global wait queue | |
127 | * for callers to sleep on until devices are unblocked. | |
128 | */ | |
129 | static DECLARE_WAIT_QUEUE_HEAD(pci_ucfg_wait); | |
e04b0ea2 | 130 | |
7ea7e98f MW |
131 | static noinline void pci_wait_ucfg(struct pci_dev *dev) |
132 | { | |
133 | DECLARE_WAITQUEUE(wait, current); | |
134 | ||
135 | __add_wait_queue(&pci_ucfg_wait, &wait); | |
136 | do { | |
137 | set_current_state(TASK_UNINTERRUPTIBLE); | |
138 | spin_unlock_irq(&pci_lock); | |
139 | schedule(); | |
140 | spin_lock_irq(&pci_lock); | |
141 | } while (dev->block_ucfg_access); | |
142 | __remove_wait_queue(&pci_ucfg_wait, &wait); | |
e04b0ea2 BK |
143 | } |
144 | ||
145 | #define PCI_USER_READ_CONFIG(size,type) \ | |
146 | int pci_user_read_config_##size \ | |
147 | (struct pci_dev *dev, int pos, type *val) \ | |
148 | { \ | |
e04b0ea2 BK |
149 | int ret = 0; \ |
150 | u32 data = -1; \ | |
151 | if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \ | |
7ea7e98f MW |
152 | spin_lock_irq(&pci_lock); \ |
153 | if (unlikely(dev->block_ucfg_access)) pci_wait_ucfg(dev); \ | |
154 | ret = dev->bus->ops->read(dev->bus, dev->devfn, \ | |
e04b0ea2 | 155 | pos, sizeof(type), &data); \ |
7ea7e98f | 156 | spin_unlock_irq(&pci_lock); \ |
e04b0ea2 BK |
157 | *val = (type)data; \ |
158 | return ret; \ | |
159 | } | |
160 | ||
161 | #define PCI_USER_WRITE_CONFIG(size,type) \ | |
162 | int pci_user_write_config_##size \ | |
163 | (struct pci_dev *dev, int pos, type val) \ | |
164 | { \ | |
e04b0ea2 BK |
165 | int ret = -EIO; \ |
166 | if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \ | |
7ea7e98f MW |
167 | spin_lock_irq(&pci_lock); \ |
168 | if (unlikely(dev->block_ucfg_access)) pci_wait_ucfg(dev); \ | |
169 | ret = dev->bus->ops->write(dev->bus, dev->devfn, \ | |
e04b0ea2 | 170 | pos, sizeof(type), val); \ |
7ea7e98f | 171 | spin_unlock_irq(&pci_lock); \ |
e04b0ea2 BK |
172 | return ret; \ |
173 | } | |
174 | ||
175 | PCI_USER_READ_CONFIG(byte, u8) | |
176 | PCI_USER_READ_CONFIG(word, u16) | |
177 | PCI_USER_READ_CONFIG(dword, u32) | |
178 | PCI_USER_WRITE_CONFIG(byte, u8) | |
179 | PCI_USER_WRITE_CONFIG(word, u16) | |
180 | PCI_USER_WRITE_CONFIG(dword, u32) | |
181 | ||
94e61088 BH |
182 | /* VPD access through PCI 2.2+ VPD capability */ |
183 | ||
184 | #define PCI_VPD_PCI22_SIZE (PCI_VPD_ADDR_MASK + 1) | |
185 | ||
186 | struct pci_vpd_pci22 { | |
187 | struct pci_vpd base; | |
1120f8b8 SH |
188 | struct mutex lock; |
189 | u16 flag; | |
94e61088 | 190 | bool busy; |
1120f8b8 | 191 | u8 cap; |
94e61088 BH |
192 | }; |
193 | ||
1120f8b8 SH |
194 | /* |
195 | * Wait for last operation to complete. | |
196 | * This code has to spin since there is no other notification from the PCI | |
197 | * hardware. Since the VPD is often implemented by serial attachment to an | |
198 | * EEPROM, it may take many milliseconds to complete. | |
199 | */ | |
94e61088 BH |
200 | static int pci_vpd_pci22_wait(struct pci_dev *dev) |
201 | { | |
202 | struct pci_vpd_pci22 *vpd = | |
203 | container_of(dev->vpd, struct pci_vpd_pci22, base); | |
1120f8b8 SH |
204 | unsigned long timeout = jiffies + HZ/20 + 2; |
205 | u16 status; | |
94e61088 BH |
206 | int ret; |
207 | ||
208 | if (!vpd->busy) | |
209 | return 0; | |
210 | ||
94e61088 | 211 | for (;;) { |
1120f8b8 | 212 | ret = pci_user_read_config_word(dev, vpd->cap + PCI_VPD_ADDR, |
94e61088 | 213 | &status); |
1120f8b8 | 214 | if (ret) |
94e61088 | 215 | return ret; |
1120f8b8 SH |
216 | |
217 | if ((status & PCI_VPD_ADDR_F) == vpd->flag) { | |
94e61088 BH |
218 | vpd->busy = false; |
219 | return 0; | |
220 | } | |
1120f8b8 SH |
221 | |
222 | if (time_after(jiffies, timeout)) | |
94e61088 | 223 | return -ETIMEDOUT; |
1120f8b8 SH |
224 | if (fatal_signal_pending(current)) |
225 | return -EINTR; | |
226 | if (!cond_resched()) | |
227 | udelay(10); | |
94e61088 BH |
228 | } |
229 | } | |
230 | ||
287d19ce SH |
231 | static ssize_t pci_vpd_pci22_read(struct pci_dev *dev, loff_t pos, size_t count, |
232 | void *arg) | |
94e61088 BH |
233 | { |
234 | struct pci_vpd_pci22 *vpd = | |
235 | container_of(dev->vpd, struct pci_vpd_pci22, base); | |
287d19ce SH |
236 | int ret; |
237 | loff_t end = pos + count; | |
238 | u8 *buf = arg; | |
94e61088 | 239 | |
287d19ce | 240 | if (pos < 0 || pos > vpd->base.len || end > vpd->base.len) |
94e61088 | 241 | return -EINVAL; |
94e61088 | 242 | |
1120f8b8 SH |
243 | if (mutex_lock_killable(&vpd->lock)) |
244 | return -EINTR; | |
245 | ||
94e61088 BH |
246 | ret = pci_vpd_pci22_wait(dev); |
247 | if (ret < 0) | |
248 | goto out; | |
1120f8b8 | 249 | |
287d19ce SH |
250 | while (pos < end) { |
251 | u32 val; | |
252 | unsigned int i, skip; | |
253 | ||
254 | ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR, | |
255 | pos & ~3); | |
256 | if (ret < 0) | |
257 | break; | |
258 | vpd->busy = true; | |
259 | vpd->flag = PCI_VPD_ADDR_F; | |
260 | ret = pci_vpd_pci22_wait(dev); | |
261 | if (ret < 0) | |
262 | break; | |
263 | ||
264 | ret = pci_user_read_config_dword(dev, vpd->cap + PCI_VPD_DATA, &val); | |
265 | if (ret < 0) | |
266 | break; | |
267 | ||
268 | skip = pos & 3; | |
269 | for (i = 0; i < sizeof(u32); i++) { | |
270 | if (i >= skip) { | |
271 | *buf++ = val; | |
272 | if (++pos == end) | |
273 | break; | |
274 | } | |
275 | val >>= 8; | |
276 | } | |
277 | } | |
94e61088 | 278 | out: |
1120f8b8 | 279 | mutex_unlock(&vpd->lock); |
287d19ce | 280 | return ret ? ret : count; |
94e61088 BH |
281 | } |
282 | ||
287d19ce SH |
283 | static ssize_t pci_vpd_pci22_write(struct pci_dev *dev, loff_t pos, size_t count, |
284 | const void *arg) | |
94e61088 BH |
285 | { |
286 | struct pci_vpd_pci22 *vpd = | |
287 | container_of(dev->vpd, struct pci_vpd_pci22, base); | |
287d19ce SH |
288 | const u8 *buf = arg; |
289 | loff_t end = pos + count; | |
1120f8b8 | 290 | int ret = 0; |
94e61088 | 291 | |
287d19ce | 292 | if (pos < 0 || (pos & 3) || (count & 3) || end > vpd->base.len) |
94e61088 BH |
293 | return -EINVAL; |
294 | ||
1120f8b8 SH |
295 | if (mutex_lock_killable(&vpd->lock)) |
296 | return -EINTR; | |
287d19ce | 297 | |
94e61088 BH |
298 | ret = pci_vpd_pci22_wait(dev); |
299 | if (ret < 0) | |
300 | goto out; | |
287d19ce SH |
301 | |
302 | while (pos < end) { | |
303 | u32 val; | |
304 | ||
305 | val = *buf++; | |
306 | val |= *buf++ << 8; | |
307 | val |= *buf++ << 16; | |
308 | val |= *buf++ << 24; | |
309 | ||
310 | ret = pci_user_write_config_dword(dev, vpd->cap + PCI_VPD_DATA, val); | |
311 | if (ret < 0) | |
312 | break; | |
313 | ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR, | |
314 | pos | PCI_VPD_ADDR_F); | |
315 | if (ret < 0) | |
316 | break; | |
317 | ||
318 | vpd->busy = true; | |
319 | vpd->flag = 0; | |
320 | ret = pci_vpd_pci22_wait(dev); | |
321 | ||
322 | pos += sizeof(u32); | |
323 | } | |
94e61088 | 324 | out: |
1120f8b8 | 325 | mutex_unlock(&vpd->lock); |
287d19ce | 326 | return ret ? ret : count; |
94e61088 BH |
327 | } |
328 | ||
94e61088 BH |
329 | static void pci_vpd_pci22_release(struct pci_dev *dev) |
330 | { | |
331 | kfree(container_of(dev->vpd, struct pci_vpd_pci22, base)); | |
332 | } | |
333 | ||
287d19ce | 334 | static const struct pci_vpd_ops pci_vpd_pci22_ops = { |
94e61088 BH |
335 | .read = pci_vpd_pci22_read, |
336 | .write = pci_vpd_pci22_write, | |
94e61088 BH |
337 | .release = pci_vpd_pci22_release, |
338 | }; | |
339 | ||
340 | int pci_vpd_pci22_init(struct pci_dev *dev) | |
341 | { | |
342 | struct pci_vpd_pci22 *vpd; | |
343 | u8 cap; | |
344 | ||
345 | cap = pci_find_capability(dev, PCI_CAP_ID_VPD); | |
346 | if (!cap) | |
347 | return -ENODEV; | |
348 | vpd = kzalloc(sizeof(*vpd), GFP_ATOMIC); | |
349 | if (!vpd) | |
350 | return -ENOMEM; | |
351 | ||
99cb233d | 352 | vpd->base.len = PCI_VPD_PCI22_SIZE; |
94e61088 | 353 | vpd->base.ops = &pci_vpd_pci22_ops; |
1120f8b8 | 354 | mutex_init(&vpd->lock); |
94e61088 BH |
355 | vpd->cap = cap; |
356 | vpd->busy = false; | |
357 | dev->vpd = &vpd->base; | |
358 | return 0; | |
359 | } | |
360 | ||
db567943 SH |
361 | /** |
362 | * pci_vpd_truncate - Set available Vital Product Data size | |
363 | * @dev: pci device struct | |
364 | * @size: available memory in bytes | |
365 | * | |
366 | * Adjust size of available VPD area. | |
367 | */ | |
368 | int pci_vpd_truncate(struct pci_dev *dev, size_t size) | |
369 | { | |
370 | if (!dev->vpd) | |
371 | return -EINVAL; | |
372 | ||
373 | /* limited by the access method */ | |
374 | if (size > dev->vpd->len) | |
375 | return -EINVAL; | |
376 | ||
377 | dev->vpd->len = size; | |
d407e32e AV |
378 | if (dev->vpd->attr) |
379 | dev->vpd->attr->size = size; | |
db567943 SH |
380 | |
381 | return 0; | |
382 | } | |
383 | EXPORT_SYMBOL(pci_vpd_truncate); | |
384 | ||
e04b0ea2 BK |
385 | /** |
386 | * pci_block_user_cfg_access - Block userspace PCI config reads/writes | |
387 | * @dev: pci device struct | |
388 | * | |
7ea7e98f MW |
389 | * When user access is blocked, any reads or writes to config space will |
390 | * sleep until access is unblocked again. We don't allow nesting of | |
391 | * block/unblock calls. | |
392 | */ | |
e04b0ea2 BK |
393 | void pci_block_user_cfg_access(struct pci_dev *dev) |
394 | { | |
395 | unsigned long flags; | |
7ea7e98f | 396 | int was_blocked; |
e04b0ea2 | 397 | |
e04b0ea2 | 398 | spin_lock_irqsave(&pci_lock, flags); |
7ea7e98f | 399 | was_blocked = dev->block_ucfg_access; |
e04b0ea2 BK |
400 | dev->block_ucfg_access = 1; |
401 | spin_unlock_irqrestore(&pci_lock, flags); | |
7ea7e98f MW |
402 | |
403 | /* If we BUG() inside the pci_lock, we're guaranteed to hose | |
404 | * the machine */ | |
405 | BUG_ON(was_blocked); | |
e04b0ea2 BK |
406 | } |
407 | EXPORT_SYMBOL_GPL(pci_block_user_cfg_access); | |
408 | ||
409 | /** | |
410 | * pci_unblock_user_cfg_access - Unblock userspace PCI config reads/writes | |
411 | * @dev: pci device struct | |
412 | * | |
413 | * This function allows userspace PCI config accesses to resume. | |
7ea7e98f | 414 | */ |
e04b0ea2 BK |
415 | void pci_unblock_user_cfg_access(struct pci_dev *dev) |
416 | { | |
417 | unsigned long flags; | |
418 | ||
e04b0ea2 | 419 | spin_lock_irqsave(&pci_lock, flags); |
7ea7e98f MW |
420 | |
421 | /* This indicates a problem in the caller, but we don't need | |
422 | * to kill them, unlike a double-block above. */ | |
423 | WARN_ON(!dev->block_ucfg_access); | |
424 | ||
e04b0ea2 | 425 | dev->block_ucfg_access = 0; |
7ea7e98f | 426 | wake_up_all(&pci_ucfg_wait); |
e04b0ea2 BK |
427 | spin_unlock_irqrestore(&pci_lock, flags); |
428 | } | |
429 | EXPORT_SYMBOL_GPL(pci_unblock_user_cfg_access); |