Commit | Line | Data |
---|---|---|
db3c33c6 JR |
1 | /* |
2 | * drivers/pci/ats.c | |
3 | * | |
4 | * Copyright (C) 2009 Intel Corporation, Yu Zhao <yu.zhao@intel.com> | |
c320b976 | 5 | * Copyright (C) 2011 Advanced Micro Devices, |
db3c33c6 JR |
6 | * |
7 | * PCI Express I/O Virtualization (IOV) support. | |
8 | * Address Translation Service 1.0 | |
c320b976 | 9 | * Page Request Interface added by Joerg Roedel <joerg.roedel@amd.com> |
086ac11f | 10 | * PASID support added by Joerg Roedel <joerg.roedel@amd.com> |
db3c33c6 JR |
11 | */ |
12 | ||
363c75db | 13 | #include <linux/export.h> |
db3c33c6 JR |
14 | #include <linux/pci-ats.h> |
15 | #include <linux/pci.h> | |
8c451945 | 16 | #include <linux/slab.h> |
db3c33c6 JR |
17 | |
18 | #include "pci.h" | |
19 | ||
afdd596c | 20 | void pci_ats_init(struct pci_dev *dev) |
db3c33c6 JR |
21 | { |
22 | int pos; | |
db3c33c6 JR |
23 | |
24 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ATS); | |
25 | if (!pos) | |
edc90fee | 26 | return; |
db3c33c6 | 27 | |
d544d75a | 28 | dev->ats_cap = pos; |
db3c33c6 JR |
29 | } |
30 | ||
31 | /** | |
32 | * pci_enable_ats - enable the ATS capability | |
33 | * @dev: the PCI device | |
34 | * @ps: the IOMMU page shift | |
35 | * | |
36 | * Returns 0 on success, or negative on failure. | |
37 | */ | |
38 | int pci_enable_ats(struct pci_dev *dev, int ps) | |
39 | { | |
db3c33c6 | 40 | u16 ctrl; |
c39127db | 41 | struct pci_dev *pdev; |
db3c33c6 | 42 | |
d544d75a | 43 | if (!dev->ats_cap) |
edc90fee BH |
44 | return -EINVAL; |
45 | ||
f7ef1340 | 46 | if (WARN_ON(dev->ats_enabled)) |
a021f301 BH |
47 | return -EBUSY; |
48 | ||
db3c33c6 JR |
49 | if (ps < PCI_ATS_MIN_STU) |
50 | return -EINVAL; | |
51 | ||
edc90fee BH |
52 | /* |
53 | * Note that enabling ATS on a VF fails unless it's already enabled | |
54 | * with the same STU on the PF. | |
55 | */ | |
56 | ctrl = PCI_ATS_CTRL_ENABLE; | |
57 | if (dev->is_virtfn) { | |
c39127db | 58 | pdev = pci_physfn(dev); |
d544d75a | 59 | if (pdev->ats_stu != ps) |
edc90fee | 60 | return -EINVAL; |
db3c33c6 | 61 | |
d544d75a | 62 | atomic_inc(&pdev->ats_ref_cnt); /* count enabled VFs */ |
edc90fee | 63 | } else { |
d544d75a BH |
64 | dev->ats_stu = ps; |
65 | ctrl |= PCI_ATS_CTRL_STU(dev->ats_stu - PCI_ATS_MIN_STU); | |
db3c33c6 | 66 | } |
d544d75a | 67 | pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl); |
db3c33c6 | 68 | |
d544d75a | 69 | dev->ats_enabled = 1; |
db3c33c6 JR |
70 | return 0; |
71 | } | |
d4c0636c | 72 | EXPORT_SYMBOL_GPL(pci_enable_ats); |
db3c33c6 JR |
73 | |
74 | /** | |
75 | * pci_disable_ats - disable the ATS capability | |
76 | * @dev: the PCI device | |
77 | */ | |
78 | void pci_disable_ats(struct pci_dev *dev) | |
79 | { | |
c39127db | 80 | struct pci_dev *pdev; |
db3c33c6 JR |
81 | u16 ctrl; |
82 | ||
f7ef1340 | 83 | if (WARN_ON(!dev->ats_enabled)) |
a021f301 | 84 | return; |
db3c33c6 | 85 | |
d544d75a | 86 | if (atomic_read(&dev->ats_ref_cnt)) |
edc90fee BH |
87 | return; /* VFs still enabled */ |
88 | ||
89 | if (dev->is_virtfn) { | |
c39127db | 90 | pdev = pci_physfn(dev); |
d544d75a | 91 | atomic_dec(&pdev->ats_ref_cnt); |
edc90fee BH |
92 | } |
93 | ||
d544d75a | 94 | pci_read_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, &ctrl); |
db3c33c6 | 95 | ctrl &= ~PCI_ATS_CTRL_ENABLE; |
d544d75a | 96 | pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl); |
db3c33c6 | 97 | |
d544d75a | 98 | dev->ats_enabled = 0; |
db3c33c6 | 99 | } |
d4c0636c | 100 | EXPORT_SYMBOL_GPL(pci_disable_ats); |
db3c33c6 | 101 | |
1900ca13 HX |
102 | void pci_restore_ats_state(struct pci_dev *dev) |
103 | { | |
104 | u16 ctrl; | |
105 | ||
f7ef1340 | 106 | if (!dev->ats_enabled) |
1900ca13 | 107 | return; |
1900ca13 HX |
108 | |
109 | ctrl = PCI_ATS_CTRL_ENABLE; | |
110 | if (!dev->is_virtfn) | |
d544d75a BH |
111 | ctrl |= PCI_ATS_CTRL_STU(dev->ats_stu - PCI_ATS_MIN_STU); |
112 | pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl); | |
1900ca13 HX |
113 | } |
114 | EXPORT_SYMBOL_GPL(pci_restore_ats_state); | |
115 | ||
db3c33c6 JR |
116 | /** |
117 | * pci_ats_queue_depth - query the ATS Invalidate Queue Depth | |
118 | * @dev: the PCI device | |
119 | * | |
120 | * Returns the queue depth on success, or negative on failure. | |
121 | * | |
122 | * The ATS spec uses 0 in the Invalidate Queue Depth field to | |
123 | * indicate that the function can accept 32 Invalidate Request. | |
124 | * But here we use the `real' values (i.e. 1~32) for the Queue | |
125 | * Depth; and 0 indicates the function shares the Queue with | |
126 | * other functions (doesn't exclusively own a Queue). | |
127 | */ | |
128 | int pci_ats_queue_depth(struct pci_dev *dev) | |
129 | { | |
a71f938f BH |
130 | u16 cap; |
131 | ||
3c765399 BH |
132 | if (!dev->ats_cap) |
133 | return -EINVAL; | |
134 | ||
db3c33c6 JR |
135 | if (dev->is_virtfn) |
136 | return 0; | |
137 | ||
a71f938f BH |
138 | pci_read_config_word(dev, dev->ats_cap + PCI_ATS_CAP, &cap); |
139 | return PCI_ATS_CAP_QDEP(cap) ? PCI_ATS_CAP_QDEP(cap) : PCI_ATS_MAX_QDEP; | |
db3c33c6 | 140 | } |
d4c0636c | 141 | EXPORT_SYMBOL_GPL(pci_ats_queue_depth); |
c320b976 JR |
142 | |
143 | #ifdef CONFIG_PCI_PRI | |
144 | /** | |
145 | * pci_enable_pri - Enable PRI capability | |
146 | * @ pdev: PCI device structure | |
147 | * | |
148 | * Returns 0 on success, negative value on error | |
149 | */ | |
150 | int pci_enable_pri(struct pci_dev *pdev, u32 reqs) | |
151 | { | |
152 | u16 control, status; | |
153 | u32 max_requests; | |
154 | int pos; | |
155 | ||
69166fbf | 156 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
c320b976 JR |
157 | if (!pos) |
158 | return -EINVAL; | |
159 | ||
91f57d5e AW |
160 | pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control); |
161 | pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status); | |
162 | if ((control & PCI_PRI_CTRL_ENABLE) || | |
163 | !(status & PCI_PRI_STATUS_STOPPED)) | |
c320b976 JR |
164 | return -EBUSY; |
165 | ||
91f57d5e | 166 | pci_read_config_dword(pdev, pos + PCI_PRI_MAX_REQ, &max_requests); |
c320b976 | 167 | reqs = min(max_requests, reqs); |
91f57d5e | 168 | pci_write_config_dword(pdev, pos + PCI_PRI_ALLOC_REQ, reqs); |
c320b976 | 169 | |
91f57d5e AW |
170 | control |= PCI_PRI_CTRL_ENABLE; |
171 | pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control); | |
c320b976 JR |
172 | |
173 | return 0; | |
174 | } | |
175 | EXPORT_SYMBOL_GPL(pci_enable_pri); | |
176 | ||
177 | /** | |
178 | * pci_disable_pri - Disable PRI capability | |
179 | * @pdev: PCI device structure | |
180 | * | |
181 | * Only clears the enabled-bit, regardless of its former value | |
182 | */ | |
183 | void pci_disable_pri(struct pci_dev *pdev) | |
184 | { | |
185 | u16 control; | |
186 | int pos; | |
187 | ||
69166fbf | 188 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
c320b976 JR |
189 | if (!pos) |
190 | return; | |
191 | ||
91f57d5e AW |
192 | pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control); |
193 | control &= ~PCI_PRI_CTRL_ENABLE; | |
194 | pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control); | |
c320b976 JR |
195 | } |
196 | EXPORT_SYMBOL_GPL(pci_disable_pri); | |
197 | ||
c320b976 JR |
198 | /** |
199 | * pci_reset_pri - Resets device's PRI state | |
200 | * @pdev: PCI device structure | |
201 | * | |
202 | * The PRI capability must be disabled before this function is called. | |
203 | * Returns 0 on success, negative value on error. | |
204 | */ | |
205 | int pci_reset_pri(struct pci_dev *pdev) | |
206 | { | |
207 | u16 control; | |
208 | int pos; | |
209 | ||
69166fbf | 210 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
c320b976 JR |
211 | if (!pos) |
212 | return -EINVAL; | |
213 | ||
91f57d5e AW |
214 | pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control); |
215 | if (control & PCI_PRI_CTRL_ENABLE) | |
c320b976 JR |
216 | return -EBUSY; |
217 | ||
91f57d5e | 218 | control |= PCI_PRI_CTRL_RESET; |
c320b976 | 219 | |
91f57d5e | 220 | pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control); |
c320b976 JR |
221 | |
222 | return 0; | |
223 | } | |
224 | EXPORT_SYMBOL_GPL(pci_reset_pri); | |
c320b976 | 225 | #endif /* CONFIG_PCI_PRI */ |
086ac11f JR |
226 | |
227 | #ifdef CONFIG_PCI_PASID | |
228 | /** | |
229 | * pci_enable_pasid - Enable the PASID capability | |
230 | * @pdev: PCI device structure | |
231 | * @features: Features to enable | |
232 | * | |
233 | * Returns 0 on success, negative value on error. This function checks | |
234 | * whether the features are actually supported by the device and returns | |
235 | * an error if not. | |
236 | */ | |
237 | int pci_enable_pasid(struct pci_dev *pdev, int features) | |
238 | { | |
239 | u16 control, supported; | |
240 | int pos; | |
241 | ||
69166fbf | 242 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID); |
086ac11f JR |
243 | if (!pos) |
244 | return -EINVAL; | |
245 | ||
91f57d5e AW |
246 | pci_read_config_word(pdev, pos + PCI_PASID_CTRL, &control); |
247 | pci_read_config_word(pdev, pos + PCI_PASID_CAP, &supported); | |
086ac11f | 248 | |
91f57d5e | 249 | if (control & PCI_PASID_CTRL_ENABLE) |
086ac11f JR |
250 | return -EINVAL; |
251 | ||
91f57d5e | 252 | supported &= PCI_PASID_CAP_EXEC | PCI_PASID_CAP_PRIV; |
086ac11f JR |
253 | |
254 | /* User wants to enable anything unsupported? */ | |
255 | if ((supported & features) != features) | |
256 | return -EINVAL; | |
257 | ||
91f57d5e | 258 | control = PCI_PASID_CTRL_ENABLE | features; |
086ac11f | 259 | |
91f57d5e | 260 | pci_write_config_word(pdev, pos + PCI_PASID_CTRL, control); |
086ac11f JR |
261 | |
262 | return 0; | |
263 | } | |
264 | EXPORT_SYMBOL_GPL(pci_enable_pasid); | |
265 | ||
266 | /** | |
267 | * pci_disable_pasid - Disable the PASID capability | |
268 | * @pdev: PCI device structure | |
269 | * | |
270 | */ | |
271 | void pci_disable_pasid(struct pci_dev *pdev) | |
272 | { | |
273 | u16 control = 0; | |
274 | int pos; | |
275 | ||
69166fbf | 276 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID); |
086ac11f JR |
277 | if (!pos) |
278 | return; | |
279 | ||
91f57d5e | 280 | pci_write_config_word(pdev, pos + PCI_PASID_CTRL, control); |
086ac11f JR |
281 | } |
282 | EXPORT_SYMBOL_GPL(pci_disable_pasid); | |
283 | ||
284 | /** | |
285 | * pci_pasid_features - Check which PASID features are supported | |
286 | * @pdev: PCI device structure | |
287 | * | |
288 | * Returns a negative value when no PASI capability is present. | |
289 | * Otherwise is returns a bitmask with supported features. Current | |
290 | * features reported are: | |
91f57d5e | 291 | * PCI_PASID_CAP_EXEC - Execute permission supported |
f7625980 | 292 | * PCI_PASID_CAP_PRIV - Privileged mode supported |
086ac11f JR |
293 | */ |
294 | int pci_pasid_features(struct pci_dev *pdev) | |
295 | { | |
296 | u16 supported; | |
297 | int pos; | |
298 | ||
69166fbf | 299 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID); |
086ac11f JR |
300 | if (!pos) |
301 | return -EINVAL; | |
302 | ||
91f57d5e | 303 | pci_read_config_word(pdev, pos + PCI_PASID_CAP, &supported); |
086ac11f | 304 | |
91f57d5e | 305 | supported &= PCI_PASID_CAP_EXEC | PCI_PASID_CAP_PRIV; |
086ac11f JR |
306 | |
307 | return supported; | |
308 | } | |
309 | EXPORT_SYMBOL_GPL(pci_pasid_features); | |
310 | ||
311 | #define PASID_NUMBER_SHIFT 8 | |
312 | #define PASID_NUMBER_MASK (0x1f << PASID_NUMBER_SHIFT) | |
313 | /** | |
314 | * pci_max_pasid - Get maximum number of PASIDs supported by device | |
315 | * @pdev: PCI device structure | |
316 | * | |
317 | * Returns negative value when PASID capability is not present. | |
318 | * Otherwise it returns the numer of supported PASIDs. | |
319 | */ | |
320 | int pci_max_pasids(struct pci_dev *pdev) | |
321 | { | |
322 | u16 supported; | |
323 | int pos; | |
324 | ||
69166fbf | 325 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID); |
086ac11f JR |
326 | if (!pos) |
327 | return -EINVAL; | |
328 | ||
91f57d5e | 329 | pci_read_config_word(pdev, pos + PCI_PASID_CAP, &supported); |
086ac11f JR |
330 | |
331 | supported = (supported & PASID_NUMBER_MASK) >> PASID_NUMBER_SHIFT; | |
332 | ||
333 | return (1 << supported); | |
334 | } | |
335 | EXPORT_SYMBOL_GPL(pci_max_pasids); | |
336 | #endif /* CONFIG_PCI_PASID */ |