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Merge tag 'renesas-fixes-for-v3.11' of git://git.kernel.org/pub/scm/linux/kernel...
[deliverable/linux.git] / drivers / pci / host / pci-mvebu.c
CommitLineData
45361a4f
TP		 1/*
2 * PCIe driver for Marvell Armada 370 and Armada XP SoCs
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#include <linux/kernel.h>
10#include <linux/pci.h>
11#include <linux/clk.h>
12#include <linux/module.h>
13#include <linux/mbus.h>
14#include <linux/slab.h>
15#include <linux/platform_device.h>
16#include <linux/of_address.h>
17#include <linux/of_pci.h>
18#include <linux/of_irq.h>
19#include <linux/of_platform.h>
20
21/*
22 * PCIe unit register offsets.
23 */
24#define PCIE_DEV_ID_OFF 0x0000
25#define PCIE_CMD_OFF 0x0004
26#define PCIE_DEV_REV_OFF 0x0008
27#define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3))
28#define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3))
29#define PCIE_HEADER_LOG_4_OFF 0x0128
30#define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4))
31#define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4))
32#define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4))
33#define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4))
34#define PCIE_WIN5_CTRL_OFF 0x1880
35#define PCIE_WIN5_BASE_OFF 0x1884
36#define PCIE_WIN5_REMAP_OFF 0x188c
37#define PCIE_CONF_ADDR_OFF 0x18f8
38#define PCIE_CONF_ADDR_EN 0x80000000
39#define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc))
40#define PCIE_CONF_BUS(b) (((b) & 0xff) << 16)
41#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11)
42#define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8)
43#define PCIE_CONF_ADDR(bus, devfn, where) \
44 (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \
45 PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where) | \
46 PCIE_CONF_ADDR_EN)
47#define PCIE_CONF_DATA_OFF 0x18fc
48#define PCIE_MASK_OFF 0x1910
49#define PCIE_MASK_ENABLE_INTS 0x0f000000
50#define PCIE_CTRL_OFF 0x1a00
51#define PCIE_CTRL_X1_MODE 0x0001
52#define PCIE_STAT_OFF 0x1a04
53#define PCIE_STAT_BUS 0xff00
f4ac9901 54#define PCIE_STAT_DEV 0x1f0000
45361a4f
TP		 55#define PCIE_STAT_LINK_DOWN BIT(0)
56#define PCIE_DEBUG_CTRL 0x1a60
57#define PCIE_DEBUG_SOFT_RESET BIT(20)
58
59/*
60 * This product ID is registered by Marvell, and used when the Marvell
61 * SoC is not the root complex, but an endpoint on the PCIe bus. It is
62 * therefore safe to re-use this PCI ID for our emulated PCI-to-PCI
63 * bridge.
64 */
65#define MARVELL_EMULATED_PCI_PCI_BRIDGE_ID 0x7846
66
67/* PCI configuration space of a PCI-to-PCI bridge */
68struct mvebu_sw_pci_bridge {
69 u16 vendor;
70 u16 device;
71 u16 command;
45361a4f
TP		 72 u16 class;
73 u8 interface;
74 u8 revision;
75 u8 bist;
76 u8 header_type;
77 u8 latency_timer;
78 u8 cache_line_size;
79 u32 bar[2];
80 u8 primary_bus;
81 u8 secondary_bus;
82 u8 subordinate_bus;
83 u8 secondary_latency_timer;
84 u8 iobase;
85 u8 iolimit;
86 u16 secondary_status;
87 u16 membase;
88 u16 memlimit;
89 u16 prefmembase;
90 u16 prefmemlimit;
91 u32 prefbaseupper;
92 u32 preflimitupper;
93 u16 iobaseupper;
94 u16 iolimitupper;
95 u8 cappointer;
96 u8 reserved1;
97 u16 reserved2;
98 u32 romaddr;
99 u8 intline;
100 u8 intpin;
101 u16 bridgectrl;
102};
103
104struct mvebu_pcie_port;
105
106/* Structure representing all PCIe interfaces */
107struct mvebu_pcie {
108 struct platform_device *pdev;
109 struct mvebu_pcie_port *ports;
110 struct resource io;
111 struct resource realio;
112 struct resource mem;
113 struct resource busn;
114 int nports;
115};
116
117/* Structure representing one PCIe interface */
118struct mvebu_pcie_port {
119 char *name;
120 void __iomem *base;
121 spinlock_t conf_lock;
122 int haslink;
123 u32 port;
124 u32 lane;
125 int devfn;
126 struct clk *clk;
127 struct mvebu_sw_pci_bridge bridge;
128 struct device_node *dn;
129 struct mvebu_pcie *pcie;
130 phys_addr_t memwin_base;
131 size_t memwin_size;
132 phys_addr_t iowin_base;
133 size_t iowin_size;
134};
135
136static bool mvebu_pcie_link_up(struct mvebu_pcie_port *port)
137{
138 return !(readl(port->base + PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);
139}
140
141static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port *port, int nr)
142{
143 u32 stat;
144
145 stat = readl(port->base + PCIE_STAT_OFF);
146 stat &= ~PCIE_STAT_BUS;
147 stat |= nr << 8;
148 writel(stat, port->base + PCIE_STAT_OFF);
149}
150
f4ac9901
TP		 151static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr)
152{
153 u32 stat;
154
155 stat = readl(port->base + PCIE_STAT_OFF);
156 stat &= ~PCIE_STAT_DEV;
157 stat |= nr << 16;
158 writel(stat, port->base + PCIE_STAT_OFF);
159}
160
45361a4f
TP		 161/*
162 * Setup PCIE BARs and Address Decode Wins:
163 * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
164 * WIN[0-3] -> DRAM bank[0-3]
165 */
166static void __init mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)
167{
168 const struct mbus_dram_target_info *dram;
169 u32 size;
170 int i;
171
172 dram = mv_mbus_dram_info();
173
174 /* First, disable and clear BARs and windows. */
175 for (i = 1; i < 3; i++) {
176 writel(0, port->base + PCIE_BAR_CTRL_OFF(i));
177 writel(0, port->base + PCIE_BAR_LO_OFF(i));
178 writel(0, port->base + PCIE_BAR_HI_OFF(i));
179 }
180
181 for (i = 0; i < 5; i++) {
182 writel(0, port->base + PCIE_WIN04_CTRL_OFF(i));
183 writel(0, port->base + PCIE_WIN04_BASE_OFF(i));
184 writel(0, port->base + PCIE_WIN04_REMAP_OFF(i));
185 }
186
187 writel(0, port->base + PCIE_WIN5_CTRL_OFF);
188 writel(0, port->base + PCIE_WIN5_BASE_OFF);
189 writel(0, port->base + PCIE_WIN5_REMAP_OFF);
190
191 /* Setup windows for DDR banks. Count total DDR size on the fly. */
192 size = 0;
193 for (i = 0; i < dram->num_cs; i++) {
194 const struct mbus_dram_window *cs = dram->cs + i;
195
196 writel(cs->base & 0xffff0000,
197 port->base + PCIE_WIN04_BASE_OFF(i));
198 writel(0, port->base + PCIE_WIN04_REMAP_OFF(i));
199 writel(((cs->size - 1) & 0xffff0000) |
200 (cs->mbus_attr << 8) |
201 (dram->mbus_dram_target_id << 4) | 1,
202 port->base + PCIE_WIN04_CTRL_OFF(i));
203
204 size += cs->size;
205 }
206
207 /* Round up 'size' to the nearest power of two. */
208 if ((size & (size - 1)) != 0)
209 size = 1 << fls(size);
210
211 /* Setup BAR[1] to all DRAM banks. */
212 writel(dram->cs[0].base, port->base + PCIE_BAR_LO_OFF(1));
213 writel(0, port->base + PCIE_BAR_HI_OFF(1));
214 writel(((size - 1) & 0xffff0000) | 1,
215 port->base + PCIE_BAR_CTRL_OFF(1));
216}
217
218static void __init mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)
219{
220 u16 cmd;
221 u32 mask;
222
223 /* Point PCIe unit MBUS decode windows to DRAM space. */
224 mvebu_pcie_setup_wins(port);
225
226 /* Master + slave enable. */
227 cmd = readw(port->base + PCIE_CMD_OFF);
228 cmd |= PCI_COMMAND_IO;
229 cmd |= PCI_COMMAND_MEMORY;
230 cmd |= PCI_COMMAND_MASTER;
231 writew(cmd, port->base + PCIE_CMD_OFF);
232
233 /* Enable interrupt lines A-D. */
234 mask = readl(port->base + PCIE_MASK_OFF);
235 mask |= PCIE_MASK_ENABLE_INTS;
236 writel(mask, port->base + PCIE_MASK_OFF);
237}
238
239static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port,
240 struct pci_bus *bus,
241 u32 devfn, int where, int size, u32 *val)
242{
243 writel(PCIE_CONF_ADDR(bus->number, devfn, where),
244 port->base + PCIE_CONF_ADDR_OFF);
245
246 *val = readl(port->base + PCIE_CONF_DATA_OFF);
247
248 if (size == 1)
249 *val = (*val >> (8 * (where & 3))) & 0xff;
250 else if (size == 2)
251 *val = (*val >> (8 * (where & 3))) & 0xffff;
252
253 return PCIBIOS_SUCCESSFUL;
254}
255
256static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port,
257 struct pci_bus *bus,
258 u32 devfn, int where, int size, u32 val)
259{
260 int ret = PCIBIOS_SUCCESSFUL;
261
262 writel(PCIE_CONF_ADDR(bus->number, devfn, where),
263 port->base + PCIE_CONF_ADDR_OFF);
264
265 if (size == 4)
266 writel(val, port->base + PCIE_CONF_DATA_OFF);
267 else if (size == 2)
268 writew(val, port->base + PCIE_CONF_DATA_OFF + (where & 3));
269 else if (size == 1)
270 writeb(val, port->base + PCIE_CONF_DATA_OFF + (where & 3));
271 else
272 ret = PCIBIOS_BAD_REGISTER_NUMBER;
273
274 return ret;
275}
276
277static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
278{
279 phys_addr_t iobase;
280
281 /* Are the new iobase/iolimit values invalid? */
282 if (port->bridge.iolimit < port->bridge.iobase ||
283 port->bridge.iolimitupper < port->bridge.iobaseupper) {
284
285 /* If a window was configured, remove it */
286 if (port->iowin_base) {
287 mvebu_mbus_del_window(port->iowin_base,
288 port->iowin_size);
289 port->iowin_base = 0;
290 port->iowin_size = 0;
291 }
292
293 return;
294 }
295
296 /*
297 * We read the PCI-to-PCI bridge emulated registers, and
298 * calculate the base address and size of the address decoding
299 * window to setup, according to the PCI-to-PCI bridge
300 * specifications. iobase is the bus address, port->iowin_base
301 * is the CPU address.
302 */
303 iobase = ((port->bridge.iobase & 0xF0) << 8) |
304 (port->bridge.iobaseupper << 16);
305 port->iowin_base = port->pcie->io.start + iobase;
306 port->iowin_size = ((0xFFF | ((port->bridge.iolimit & 0xF0) << 8) |
307 (port->bridge.iolimitupper << 16)) -
308 iobase);
309
310 mvebu_mbus_add_window_remap_flags(port->name, port->iowin_base,
311 port->iowin_size,
312 iobase,
313 MVEBU_MBUS_PCI_IO);
314
315 pci_ioremap_io(iobase, port->iowin_base);
316}
317
318static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
319{
320 /* Are the new membase/memlimit values invalid? */
321 if (port->bridge.memlimit < port->bridge.membase) {
322
323 /* If a window was configured, remove it */
324 if (port->memwin_base) {
325 mvebu_mbus_del_window(port->memwin_base,
326 port->memwin_size);
327 port->memwin_base = 0;
328 port->memwin_size = 0;
329 }
330
331 return;
332 }
333
334 /*
335 * We read the PCI-to-PCI bridge emulated registers, and
336 * calculate the base address and size of the address decoding
337 * window to setup, according to the PCI-to-PCI bridge
338 * specifications.
339 */
340 port->memwin_base = ((port->bridge.membase & 0xFFF0) << 16);
341 port->memwin_size =
342 (((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) -
343 port->memwin_base;
344
345 mvebu_mbus_add_window_remap_flags(port->name, port->memwin_base,
346 port->memwin_size,
347 MVEBU_MBUS_NO_REMAP,
348 MVEBU_MBUS_PCI_MEM);
349}
350
351/*
352 * Initialize the configuration space of the PCI-to-PCI bridge
353 * associated with the given PCIe interface.
354 */
355static void mvebu_sw_pci_bridge_init(struct mvebu_pcie_port *port)
356{
357 struct mvebu_sw_pci_bridge *bridge = &port->bridge;
358
359 memset(bridge, 0, sizeof(struct mvebu_sw_pci_bridge));
360
45361a4f
TP		 361 bridge->class = PCI_CLASS_BRIDGE_PCI;
362 bridge->vendor = PCI_VENDOR_ID_MARVELL;
363 bridge->device = MARVELL_EMULATED_PCI_PCI_BRIDGE_ID;
364 bridge->header_type = PCI_HEADER_TYPE_BRIDGE;
365 bridge->cache_line_size = 0x10;
366
367 /* We support 32 bits I/O addressing */
368 bridge->iobase = PCI_IO_RANGE_TYPE_32;
369 bridge->iolimit = PCI_IO_RANGE_TYPE_32;
370}
371
372/*
373 * Read the configuration space of the PCI-to-PCI bridge associated to
374 * the given PCIe interface.
375 */
376static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port,
377 unsigned int where, int size, u32 *value)
378{
379 struct mvebu_sw_pci_bridge *bridge = &port->bridge;
380
381 switch (where & ~3) {
382 case PCI_VENDOR_ID:
383 *value = bridge->device << 16 | bridge->vendor;
384 break;
385
386 case PCI_COMMAND:
6eb237c4 387 *value = bridge->command;
45361a4f
TP		 388 break;
389
390 case PCI_CLASS_REVISION:
391 *value = bridge->class << 16 | bridge->interface << 8 |
392 bridge->revision;
393 break;
394
395 case PCI_CACHE_LINE_SIZE:
396 *value = bridge->bist << 24 | bridge->header_type << 16 |
397 bridge->latency_timer << 8 | bridge->cache_line_size;
398 break;
399
400 case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
401 *value = bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4];
402 break;
403
404 case PCI_PRIMARY_BUS:
405 *value = (bridge->secondary_latency_timer << 24 |
406 bridge->subordinate_bus << 16 |
407 bridge->secondary_bus << 8 |
408 bridge->primary_bus);
409 break;
410
411 case PCI_IO_BASE:
412 *value = (bridge->secondary_status << 16 |
413 bridge->iolimit << 8 |
414 bridge->iobase);
415 break;
416
417 case PCI_MEMORY_BASE:
418 *value = (bridge->memlimit << 16 | bridge->membase);
419 break;
420
421 case PCI_PREF_MEMORY_BASE:
422 *value = (bridge->prefmemlimit << 16 | bridge->prefmembase);
423 break;
424
425 case PCI_PREF_BASE_UPPER32:
426 *value = bridge->prefbaseupper;
427 break;
428
429 case PCI_PREF_LIMIT_UPPER32:
430 *value = bridge->preflimitupper;
431 break;
432
433 case PCI_IO_BASE_UPPER16:
434 *value = (bridge->iolimitupper << 16 | bridge->iobaseupper);
435 break;
436
437 case PCI_ROM_ADDRESS1:
438 *value = 0;
439 break;
440
441 default:
442 *value = 0xffffffff;
443 return PCIBIOS_BAD_REGISTER_NUMBER;
444 }
445
446 if (size == 2)
447 *value = (*value >> (8 * (where & 3))) & 0xffff;
448 else if (size == 1)
449 *value = (*value >> (8 * (where & 3))) & 0xff;
450
451 return PCIBIOS_SUCCESSFUL;
452}
453
454/* Write to the PCI-to-PCI bridge configuration space */
455static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
456 unsigned int where, int size, u32 value)
457{
458 struct mvebu_sw_pci_bridge *bridge = &port->bridge;
459 u32 mask, reg;
460 int err;
461
462 if (size == 4)
463 mask = 0x0;
464 else if (size == 2)
465 mask = ~(0xffff << ((where & 3) * 8));
466 else if (size == 1)
467 mask = ~(0xff << ((where & 3) * 8));
468 else
469 return PCIBIOS_BAD_REGISTER_NUMBER;
470
471 err = mvebu_sw_pci_bridge_read(port, where & ~3, 4, &reg);
472 if (err)
473 return err;
474
475 value = (reg & mask) | value << ((where & 3) * 8);
476
477 switch (where & ~3) {
478 case PCI_COMMAND:
479 bridge->command = value & 0xffff;
45361a4f
TP		 480 break;
481
482 case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
483 bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4] = value;
484 break;
485
486 case PCI_IO_BASE:
487 /*
488 * We also keep bit 1 set, it is a read-only bit that
489 * indicates we support 32 bits addressing for the
490 * I/O
491 */
492 bridge->iobase = (value & 0xff) | PCI_IO_RANGE_TYPE_32;
493 bridge->iolimit = ((value >> 8) & 0xff) | PCI_IO_RANGE_TYPE_32;
494 bridge->secondary_status = value >> 16;
495 mvebu_pcie_handle_iobase_change(port);
496 break;
497
498 case PCI_MEMORY_BASE:
499 bridge->membase = value & 0xffff;
500 bridge->memlimit = value >> 16;
501 mvebu_pcie_handle_membase_change(port);
502 break;
503
504 case PCI_PREF_MEMORY_BASE:
505 bridge->prefmembase = value & 0xffff;
506 bridge->prefmemlimit = value >> 16;
507 break;
508
509 case PCI_PREF_BASE_UPPER32:
510 bridge->prefbaseupper = value;
511 break;
512
513 case PCI_PREF_LIMIT_UPPER32:
514 bridge->preflimitupper = value;
515 break;
516
517 case PCI_IO_BASE_UPPER16:
518 bridge->iobaseupper = value & 0xffff;
519 bridge->iolimitupper = value >> 16;
520 mvebu_pcie_handle_iobase_change(port);
521 break;
522
523 case PCI_PRIMARY_BUS:
524 bridge->primary_bus = value & 0xff;
525 bridge->secondary_bus = (value >> 8) & 0xff;
526 bridge->subordinate_bus = (value >> 16) & 0xff;
527 bridge->secondary_latency_timer = (value >> 24) & 0xff;
528 mvebu_pcie_set_local_bus_nr(port, bridge->secondary_bus);
529 break;
530
531 default:
532 break;
533 }
534
535 return PCIBIOS_SUCCESSFUL;
536}
537
538static inline struct mvebu_pcie *sys_to_pcie(struct pci_sys_data *sys)
539{
540 return sys->private_data;
541}
542
543static struct mvebu_pcie_port *
544mvebu_pcie_find_port(struct mvebu_pcie *pcie, struct pci_bus *bus,
545 int devfn)
546{
547 int i;
548
549 for (i = 0; i < pcie->nports; i++) {
550 struct mvebu_pcie_port *port = &pcie->ports[i];
551 if (bus->number == 0 && port->devfn == devfn)
552 return port;
553 if (bus->number != 0 &&
197fc226
TP		 554 bus->number >= port->bridge.secondary_bus &&
555 bus->number <= port->bridge.subordinate_bus)
45361a4f
TP		 556 return port;
557 }
558
559 return NULL;
560}
561
562/* PCI configuration space write function */
563static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
564 int where, int size, u32 val)
565{
566 struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
567 struct mvebu_pcie_port *port;
568 unsigned long flags;
569 int ret;
570
571 port = mvebu_pcie_find_port(pcie, bus, devfn);
572 if (!port)
573 return PCIBIOS_DEVICE_NOT_FOUND;
574
575 /* Access the emulated PCI-to-PCI bridge */
576 if (bus->number == 0)
577 return mvebu_sw_pci_bridge_write(port, where, size, val);
578
197fc226
TP		 579 if (!port->haslink)
580 return PCIBIOS_DEVICE_NOT_FOUND;
581
582 /*
583 * On the secondary bus, we don't want to expose any other
584 * device than the device physically connected in the PCIe
585 * slot, visible in slot 0. In slot 1, there's a special
586 * Marvell device that only makes sense when the Armada is
587 * used as a PCIe endpoint.
588 */
589 if (bus->number == port->bridge.secondary_bus &&
590 PCI_SLOT(devfn) != 0)
45361a4f
TP		 591 return PCIBIOS_DEVICE_NOT_FOUND;
592
593 /* Access the real PCIe interface */
594 spin_lock_irqsave(&port->conf_lock, flags);
f4ac9901 595 ret = mvebu_pcie_hw_wr_conf(port, bus, devfn,
45361a4f
TP		 596 where, size, val);
597 spin_unlock_irqrestore(&port->conf_lock, flags);
598
599 return ret;
600}
601
602/* PCI configuration space read function */
603static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
604 int size, u32 *val)
605{
606 struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
607 struct mvebu_pcie_port *port;
608 unsigned long flags;
609 int ret;
610
611 port = mvebu_pcie_find_port(pcie, bus, devfn);
612 if (!port) {
613 *val = 0xffffffff;
614 return PCIBIOS_DEVICE_NOT_FOUND;
615 }
616
617 /* Access the emulated PCI-to-PCI bridge */
618 if (bus->number == 0)
619 return mvebu_sw_pci_bridge_read(port, where, size, val);
620
197fc226
TP		 621 if (!port->haslink) {
622 *val = 0xffffffff;
623 return PCIBIOS_DEVICE_NOT_FOUND;
624 }
625
626 /*
627 * On the secondary bus, we don't want to expose any other
628 * device than the device physically connected in the PCIe
629 * slot, visible in slot 0. In slot 1, there's a special
630 * Marvell device that only makes sense when the Armada is
631 * used as a PCIe endpoint.
632 */
633 if (bus->number == port->bridge.secondary_bus &&
634 PCI_SLOT(devfn) != 0) {
45361a4f
TP		 635 *val = 0xffffffff;
636 return PCIBIOS_DEVICE_NOT_FOUND;
637 }
638
639 /* Access the real PCIe interface */
640 spin_lock_irqsave(&port->conf_lock, flags);
f4ac9901 641 ret = mvebu_pcie_hw_rd_conf(port, bus, devfn,
45361a4f
TP		 642 where, size, val);
643 spin_unlock_irqrestore(&port->conf_lock, flags);
644
645 return ret;
646}
647
648static struct pci_ops mvebu_pcie_ops = {
649 .read = mvebu_pcie_rd_conf,
650 .write = mvebu_pcie_wr_conf,
651};
652
653static int __init mvebu_pcie_setup(int nr, struct pci_sys_data *sys)
654{
655 struct mvebu_pcie *pcie = sys_to_pcie(sys);
656 int i;
657
658 pci_add_resource_offset(&sys->resources, &pcie->realio, sys->io_offset);
659 pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset);
660 pci_add_resource(&sys->resources, &pcie->busn);
661
662 for (i = 0; i < pcie->nports; i++) {
663 struct mvebu_pcie_port *port = &pcie->ports[i];
664 mvebu_pcie_setup_hw(port);
665 }
666
667 return 1;
668}
669
670static int __init mvebu_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
671{
672 struct of_irq oirq;
673 int ret;
674
675 ret = of_irq_map_pci(dev, &oirq);
676 if (ret)
677 return ret;
678
679 return irq_create_of_mapping(oirq.controller, oirq.specifier,
680 oirq.size);
681}
682
683static struct pci_bus *mvebu_pcie_scan_bus(int nr, struct pci_sys_data *sys)
684{
685 struct mvebu_pcie *pcie = sys_to_pcie(sys);
686 struct pci_bus *bus;
687
688 bus = pci_create_root_bus(&pcie->pdev->dev, sys->busnr,
689 &mvebu_pcie_ops, sys, &sys->resources);
690 if (!bus)
691 return NULL;
692
693 pci_scan_child_bus(bus);
694
695 return bus;
696}
697
698resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev,
699 const struct resource *res,
700 resource_size_t start,
701 resource_size_t size,
702 resource_size_t align)
703{
704 if (dev->bus->number != 0)
705 return start;
706
707 /*
708 * On the PCI-to-PCI bridge side, the I/O windows must have at
709 * least a 64 KB size and be aligned on their size, and the
710 * memory windows must have at least a 1 MB size and be
711 * aligned on their size
712 */
713 if (res->flags & IORESOURCE_IO)
714 return round_up(start, max((resource_size_t)SZ_64K, size));
715 else if (res->flags & IORESOURCE_MEM)
716 return round_up(start, max((resource_size_t)SZ_1M, size));
717 else
718 return start;
719}
720
721static void __init mvebu_pcie_enable(struct mvebu_pcie *pcie)
722{
723 struct hw_pci hw;
724
725 memset(&hw, 0, sizeof(hw));
726
727 hw.nr_controllers = 1;
728 hw.private_data = (void **)&pcie;
729 hw.setup = mvebu_pcie_setup;
730 hw.scan = mvebu_pcie_scan_bus;
731 hw.map_irq = mvebu_pcie_map_irq;
732 hw.ops = &mvebu_pcie_ops;
733 hw.align_resource = mvebu_pcie_align_resource;
734
735 pci_common_init(&hw);
736}
737
738/*
739 * Looks up the list of register addresses encoded into the reg =
740 * <...> property for one that matches the given port/lane. Once
741 * found, maps it.
742 */
743static void __iomem * __init
744mvebu_pcie_map_registers(struct platform_device *pdev,
745 struct device_node *np,
746 struct mvebu_pcie_port *port)
747{
748 struct resource regs;
749 int ret = 0;
750
751 ret = of_address_to_resource(np, 0, &regs);
752 if (ret)
753 return NULL;
754
755 return devm_request_and_ioremap(&pdev->dev, &regs);
756}
757
758static int __init mvebu_pcie_probe(struct platform_device *pdev)
759{
760 struct mvebu_pcie *pcie;
761 struct device_node *np = pdev->dev.of_node;
762 struct of_pci_range range;
763 struct of_pci_range_parser parser;
764 struct device_node *child;
765 int i, ret;
766
767 pcie = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pcie),
768 GFP_KERNEL);
769 if (!pcie)
770 return -ENOMEM;
771
772 pcie->pdev = pdev;
773
774 if (of_pci_range_parser_init(&parser, np))
775 return -EINVAL;
776
777 /* Get the I/O and memory ranges from DT */
778 for_each_of_pci_range(&parser, &range) {
779 unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
780 if (restype == IORESOURCE_IO) {
781 of_pci_range_to_resource(&range, np, &pcie->io);
782 of_pci_range_to_resource(&range, np, &pcie->realio);
783 pcie->io.name = "I/O";
784 pcie->realio.start = max_t(resource_size_t,
785 PCIBIOS_MIN_IO,
786 range.pci_addr);
787 pcie->realio.end = min_t(resource_size_t,
788 IO_SPACE_LIMIT,
789 range.pci_addr + range.size);
790 }
791 if (restype == IORESOURCE_MEM) {
792 of_pci_range_to_resource(&range, np, &pcie->mem);
793 pcie->mem.name = "MEM";
794 }
795 }
796
797 /* Get the bus range */
798 ret = of_pci_parse_bus_range(np, &pcie->busn);
799 if (ret) {
800 dev_err(&pdev->dev, "failed to parse bus-range property: %d\n",
801 ret);
802 return ret;
803 }
804
805 for_each_child_of_node(pdev->dev.of_node, child) {
806 if (!of_device_is_available(child))
807 continue;
808 pcie->nports++;
809 }
810
811 pcie->ports = devm_kzalloc(&pdev->dev, pcie->nports *
812 sizeof(struct mvebu_pcie_port),
813 GFP_KERNEL);
814 if (!pcie->ports)
815 return -ENOMEM;
816
817 i = 0;
818 for_each_child_of_node(pdev->dev.of_node, child) {
819 struct mvebu_pcie_port *port = &pcie->ports[i];
820
821 if (!of_device_is_available(child))
822 continue;
823
824 port->pcie = pcie;
825
826 if (of_property_read_u32(child, "marvell,pcie-port",
827 &port->port)) {
828 dev_warn(&pdev->dev,
829 "ignoring PCIe DT node, missing pcie-port property\n");
830 continue;
831 }
832
833 if (of_property_read_u32(child, "marvell,pcie-lane",
834 &port->lane))
835 port->lane = 0;
836
837 port->name = kasprintf(GFP_KERNEL, "pcie%d.%d",
838 port->port, port->lane);
839
840 port->devfn = of_pci_get_devfn(child);
841 if (port->devfn < 0)
842 continue;
843
844 port->base = mvebu_pcie_map_registers(pdev, child, port);
845 if (!port->base) {
846 dev_err(&pdev->dev, "PCIe%d.%d: cannot map registers\n",
847 port->port, port->lane);
848 continue;
849 }
850
f4ac9901
TP		 851 mvebu_pcie_set_local_dev_nr(port, 1);
852
45361a4f
TP		 853 if (mvebu_pcie_link_up(port)) {
854 port->haslink = 1;
855 dev_info(&pdev->dev, "PCIe%d.%d: link up\n",
856 port->port, port->lane);
857 } else {
858 port->haslink = 0;
859 dev_info(&pdev->dev, "PCIe%d.%d: link down\n",
860 port->port, port->lane);
861 }
862
863 port->clk = of_clk_get_by_name(child, NULL);
3d9939c9 864 if (IS_ERR(port->clk)) {
45361a4f
TP		 865 dev_err(&pdev->dev, "PCIe%d.%d: cannot get clock\n",
866 port->port, port->lane);
867 iounmap(port->base);
868 port->haslink = 0;
869 continue;
870 }
871
872 port->dn = child;
873
874 clk_prepare_enable(port->clk);
875 spin_lock_init(&port->conf_lock);
876
877 mvebu_sw_pci_bridge_init(port);
878
879 i++;
880 }
881
882 mvebu_pcie_enable(pcie);
883
884 return 0;
885}
886
887static const struct of_device_id mvebu_pcie_of_match_table[] = {
888 { .compatible = "marvell,armada-xp-pcie", },
889 { .compatible = "marvell,armada-370-pcie", },
005625fc 890 { .compatible = "marvell,kirkwood-pcie", },
45361a4f
TP		 891 {},
892};
893MODULE_DEVICE_TABLE(of, mvebu_pcie_of_match_table);
894
895static struct platform_driver mvebu_pcie_driver = {
896 .driver = {
897 .owner = THIS_MODULE,
898 .name = "mvebu-pcie",
899 .of_match_table =
900 of_match_ptr(mvebu_pcie_of_match_table),
901 },
902};
903
904static int __init mvebu_pcie_init(void)
905{
906 return platform_driver_probe(&mvebu_pcie_driver,
907 mvebu_pcie_probe);
908}
909
910subsys_initcall(mvebu_pcie_init);
911
912MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
913MODULE_DESCRIPTION("Marvell EBU PCIe driver");
914MODULE_LICENSE("GPLv2");
Linux kernel - Deliverables
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