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Merge tag 'regulator-v3.13' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie...
[deliverable/linux.git] / drivers / pci / host / pci-mvebu.c
CommitLineData
45361a4f
TP		 1/*
2 * PCIe driver for Marvell Armada 370 and Armada XP SoCs
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#include <linux/kernel.h>
10#include <linux/pci.h>
11#include <linux/clk.h>
52ba992e
SH		 12#include <linux/delay.h>
13#include <linux/gpio.h>
45361a4f
TP		 14#include <linux/module.h>
15#include <linux/mbus.h>
5b4deb65 16#include <linux/msi.h>
45361a4f
TP		 17#include <linux/slab.h>
18#include <linux/platform_device.h>
19#include <linux/of_address.h>
45361a4f 20#include <linux/of_irq.h>
52ba992e
SH		 21#include <linux/of_gpio.h>
22#include <linux/of_pci.h>
45361a4f
TP		 23#include <linux/of_platform.h>
24
25/*
26 * PCIe unit register offsets.
27 */
28#define PCIE_DEV_ID_OFF 0x0000
29#define PCIE_CMD_OFF 0x0004
30#define PCIE_DEV_REV_OFF 0x0008
31#define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3))
32#define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3))
33#define PCIE_HEADER_LOG_4_OFF 0x0128
34#define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4))
35#define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4))
36#define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4))
37#define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4))
38#define PCIE_WIN5_CTRL_OFF 0x1880
39#define PCIE_WIN5_BASE_OFF 0x1884
40#define PCIE_WIN5_REMAP_OFF 0x188c
41#define PCIE_CONF_ADDR_OFF 0x18f8
42#define PCIE_CONF_ADDR_EN 0x80000000
43#define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc))
44#define PCIE_CONF_BUS(b) (((b) & 0xff) << 16)
45#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11)
46#define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8)
47#define PCIE_CONF_ADDR(bus, devfn, where) \
48 (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \
49 PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where) | \
50 PCIE_CONF_ADDR_EN)
51#define PCIE_CONF_DATA_OFF 0x18fc
52#define PCIE_MASK_OFF 0x1910
53#define PCIE_MASK_ENABLE_INTS 0x0f000000
54#define PCIE_CTRL_OFF 0x1a00
55#define PCIE_CTRL_X1_MODE 0x0001
56#define PCIE_STAT_OFF 0x1a04
57#define PCIE_STAT_BUS 0xff00
f4ac9901 58#define PCIE_STAT_DEV 0x1f0000
45361a4f
TP		 59#define PCIE_STAT_LINK_DOWN BIT(0)
60#define PCIE_DEBUG_CTRL 0x1a60
61#define PCIE_DEBUG_SOFT_RESET BIT(20)
62
63/*
64 * This product ID is registered by Marvell, and used when the Marvell
65 * SoC is not the root complex, but an endpoint on the PCIe bus. It is
66 * therefore safe to re-use this PCI ID for our emulated PCI-to-PCI
67 * bridge.
68 */
69#define MARVELL_EMULATED_PCI_PCI_BRIDGE_ID 0x7846
70
71/* PCI configuration space of a PCI-to-PCI bridge */
72struct mvebu_sw_pci_bridge {
73 u16 vendor;
74 u16 device;
75 u16 command;
45361a4f
TP		 76 u16 class;
77 u8 interface;
78 u8 revision;
79 u8 bist;
80 u8 header_type;
81 u8 latency_timer;
82 u8 cache_line_size;
83 u32 bar[2];
84 u8 primary_bus;
85 u8 secondary_bus;
86 u8 subordinate_bus;
87 u8 secondary_latency_timer;
88 u8 iobase;
89 u8 iolimit;
90 u16 secondary_status;
91 u16 membase;
92 u16 memlimit;
45361a4f
TP		 93 u16 iobaseupper;
94 u16 iolimitupper;
95 u8 cappointer;
96 u8 reserved1;
97 u16 reserved2;
98 u32 romaddr;
99 u8 intline;
100 u8 intpin;
101 u16 bridgectrl;
102};
103
104struct mvebu_pcie_port;
105
106/* Structure representing all PCIe interfaces */
107struct mvebu_pcie {
108 struct platform_device *pdev;
109 struct mvebu_pcie_port *ports;
5b4deb65 110 struct msi_chip *msi;
45361a4f
TP		 111 struct resource io;
112 struct resource realio;
113 struct resource mem;
114 struct resource busn;
115 int nports;
116};
117
118/* Structure representing one PCIe interface */
119struct mvebu_pcie_port {
120 char *name;
121 void __iomem *base;
122 spinlock_t conf_lock;
45361a4f
TP		 123 u32 port;
124 u32 lane;
125 int devfn;
11be6547
TP		 126 unsigned int mem_target;
127 unsigned int mem_attr;
128 unsigned int io_target;
129 unsigned int io_attr;
45361a4f 130 struct clk *clk;
52ba992e
SH		 131 int reset_gpio;
132 int reset_active_low;
133 char *reset_name;
45361a4f
TP		 134 struct mvebu_sw_pci_bridge bridge;
135 struct device_node *dn;
136 struct mvebu_pcie *pcie;
137 phys_addr_t memwin_base;
138 size_t memwin_size;
139 phys_addr_t iowin_base;
140 size_t iowin_size;
141};
142
032b4c0c
SJ		 143static inline void mvebu_writel(struct mvebu_pcie_port *port, u32 val, u32 reg)
144{
145 writel(val, port->base + reg);
146}
147
148static inline u32 mvebu_readl(struct mvebu_pcie_port *port, u32 reg)
149{
150 return readl(port->base + reg);
151}
152
45361a4f
TP		 153static bool mvebu_pcie_link_up(struct mvebu_pcie_port *port)
154{
032b4c0c 155 return !(mvebu_readl(port, PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);
45361a4f
TP		 156}
157
158static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port *port, int nr)
159{
160 u32 stat;
161
032b4c0c 162 stat = mvebu_readl(port, PCIE_STAT_OFF);
45361a4f
TP		 163 stat &= ~PCIE_STAT_BUS;
164 stat |= nr << 8;
032b4c0c 165 mvebu_writel(port, stat, PCIE_STAT_OFF);
45361a4f
TP		 166}
167
f4ac9901
TP		 168static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr)
169{
170 u32 stat;
171
032b4c0c 172 stat = mvebu_readl(port, PCIE_STAT_OFF);
f4ac9901
TP		 173 stat &= ~PCIE_STAT_DEV;
174 stat |= nr << 16;
032b4c0c 175 mvebu_writel(port, stat, PCIE_STAT_OFF);
f4ac9901
TP		 176}
177
45361a4f
TP		 178/*
179 * Setup PCIE BARs and Address Decode Wins:
180 * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
181 * WIN[0-3] -> DRAM bank[0-3]
182 */
e5615c30 183static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)
45361a4f
TP		 184{
185 const struct mbus_dram_target_info *dram;
186 u32 size;
187 int i;
188
189 dram = mv_mbus_dram_info();
190
191 /* First, disable and clear BARs and windows. */
192 for (i = 1; i < 3; i++) {
032b4c0c
SJ		 193 mvebu_writel(port, 0, PCIE_BAR_CTRL_OFF(i));
194 mvebu_writel(port, 0, PCIE_BAR_LO_OFF(i));
195 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(i));
45361a4f
TP		 196 }
197
198 for (i = 0; i < 5; i++) {
032b4c0c
SJ		 199 mvebu_writel(port, 0, PCIE_WIN04_CTRL_OFF(i));
200 mvebu_writel(port, 0, PCIE_WIN04_BASE_OFF(i));
201 mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i));
45361a4f
TP		 202 }
203
032b4c0c
SJ		 204 mvebu_writel(port, 0, PCIE_WIN5_CTRL_OFF);
205 mvebu_writel(port, 0, PCIE_WIN5_BASE_OFF);
206 mvebu_writel(port, 0, PCIE_WIN5_REMAP_OFF);
45361a4f
TP		 207
208 /* Setup windows for DDR banks. Count total DDR size on the fly. */
209 size = 0;
210 for (i = 0; i < dram->num_cs; i++) {
211 const struct mbus_dram_window *cs = dram->cs + i;
212
032b4c0c
SJ		 213 mvebu_writel(port, cs->base & 0xffff0000,
214 PCIE_WIN04_BASE_OFF(i));
215 mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i));
216 mvebu_writel(port,
217 ((cs->size - 1) & 0xffff0000) |
218 (cs->mbus_attr << 8) |
219 (dram->mbus_dram_target_id << 4) | 1,
220 PCIE_WIN04_CTRL_OFF(i));
45361a4f
TP		 221
222 size += cs->size;
223 }
224
225 /* Round up 'size' to the nearest power of two. */
226 if ((size & (size - 1)) != 0)
227 size = 1 << fls(size);
228
229 /* Setup BAR[1] to all DRAM banks. */
032b4c0c
SJ		 230 mvebu_writel(port, dram->cs[0].base, PCIE_BAR_LO_OFF(1));
231 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(1));
232 mvebu_writel(port, ((size - 1) & 0xffff0000) | 1,
233 PCIE_BAR_CTRL_OFF(1));
45361a4f
TP		 234}
235
e5615c30 236static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)
45361a4f 237{
032b4c0c 238 u32 cmd, mask;
45361a4f
TP		 239
240 /* Point PCIe unit MBUS decode windows to DRAM space. */
241 mvebu_pcie_setup_wins(port);
242
243 /* Master + slave enable. */
032b4c0c 244 cmd = mvebu_readl(port, PCIE_CMD_OFF);
45361a4f
TP		 245 cmd |= PCI_COMMAND_IO;
246 cmd |= PCI_COMMAND_MEMORY;
247 cmd |= PCI_COMMAND_MASTER;
032b4c0c 248 mvebu_writel(port, cmd, PCIE_CMD_OFF);
45361a4f
TP		 249
250 /* Enable interrupt lines A-D. */
032b4c0c 251 mask = mvebu_readl(port, PCIE_MASK_OFF);
45361a4f 252 mask |= PCIE_MASK_ENABLE_INTS;
032b4c0c 253 mvebu_writel(port, mask, PCIE_MASK_OFF);
45361a4f
TP		 254}
255
256static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port,
257 struct pci_bus *bus,
258 u32 devfn, int where, int size, u32 *val)
259{
032b4c0c
SJ		 260 mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where),
261 PCIE_CONF_ADDR_OFF);
45361a4f 262
032b4c0c 263 *val = mvebu_readl(port, PCIE_CONF_DATA_OFF);
45361a4f
TP		 264
265 if (size == 1)
266 *val = (*val >> (8 * (where & 3))) & 0xff;
267 else if (size == 2)
268 *val = (*val >> (8 * (where & 3))) & 0xffff;
269
270 return PCIBIOS_SUCCESSFUL;
271}
272
273static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port,
274 struct pci_bus *bus,
275 u32 devfn, int where, int size, u32 val)
276{
032b4c0c 277 u32 _val, shift = 8 * (where & 3);
45361a4f 278
032b4c0c
SJ		 279 mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where),
280 PCIE_CONF_ADDR_OFF);
281 _val = mvebu_readl(port, PCIE_CONF_DATA_OFF);
45361a4f
TP		 282
283 if (size == 4)
032b4c0c 284 _val = val;
45361a4f 285 else if (size == 2)
032b4c0c 286 _val = (_val & ~(0xffff << shift)) | ((val & 0xffff) << shift);
45361a4f 287 else if (size == 1)
032b4c0c 288 _val = (_val & ~(0xff << shift)) | ((val & 0xff) << shift);
45361a4f 289 else
032b4c0c 290 return PCIBIOS_BAD_REGISTER_NUMBER;
45361a4f 291
032b4c0c
SJ		 292 mvebu_writel(port, _val, PCIE_CONF_DATA_OFF);
293
294 return PCIBIOS_SUCCESSFUL;
45361a4f
TP		 295}
296
297static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
298{
299 phys_addr_t iobase;
300
301 /* Are the new iobase/iolimit values invalid? */
302 if (port->bridge.iolimit < port->bridge.iobase ||
303 port->bridge.iolimitupper < port->bridge.iobaseupper) {
304
305 /* If a window was configured, remove it */
306 if (port->iowin_base) {
307 mvebu_mbus_del_window(port->iowin_base,
308 port->iowin_size);
309 port->iowin_base = 0;
310 port->iowin_size = 0;
311 }
312
313 return;
314 }
315
316 /*
317 * We read the PCI-to-PCI bridge emulated registers, and
318 * calculate the base address and size of the address decoding
319 * window to setup, according to the PCI-to-PCI bridge
320 * specifications. iobase is the bus address, port->iowin_base
321 * is the CPU address.
322 */
323 iobase = ((port->bridge.iobase & 0xF0) << 8) |
324 (port->bridge.iobaseupper << 16);
325 port->iowin_base = port->pcie->io.start + iobase;
326 port->iowin_size = ((0xFFF | ((port->bridge.iolimit & 0xF0) << 8) |
327 (port->bridge.iolimitupper << 16)) -
328 iobase);
329
11be6547
TP		 330 mvebu_mbus_add_window_remap_by_id(port->io_target, port->io_attr,
331 port->iowin_base, port->iowin_size,
332 iobase);
45361a4f
TP		 333
334 pci_ioremap_io(iobase, port->iowin_base);
335}
336
337static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
338{
339 /* Are the new membase/memlimit values invalid? */
340 if (port->bridge.memlimit < port->bridge.membase) {
341
342 /* If a window was configured, remove it */
343 if (port->memwin_base) {
344 mvebu_mbus_del_window(port->memwin_base,
345 port->memwin_size);
346 port->memwin_base = 0;
347 port->memwin_size = 0;
348 }
349
350 return;
351 }
352
353 /*
354 * We read the PCI-to-PCI bridge emulated registers, and
355 * calculate the base address and size of the address decoding
356 * window to setup, according to the PCI-to-PCI bridge
357 * specifications.
358 */
359 port->memwin_base = ((port->bridge.membase & 0xFFF0) << 16);
360 port->memwin_size =
361 (((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) -
362 port->memwin_base;
363
11be6547
TP		 364 mvebu_mbus_add_window_by_id(port->mem_target, port->mem_attr,
365 port->memwin_base, port->memwin_size);
45361a4f
TP		 366}
367
368/*
369 * Initialize the configuration space of the PCI-to-PCI bridge
370 * associated with the given PCIe interface.
371 */
372static void mvebu_sw_pci_bridge_init(struct mvebu_pcie_port *port)
373{
374 struct mvebu_sw_pci_bridge *bridge = &port->bridge;
375
376 memset(bridge, 0, sizeof(struct mvebu_sw_pci_bridge));
377
45361a4f
TP		 378 bridge->class = PCI_CLASS_BRIDGE_PCI;
379 bridge->vendor = PCI_VENDOR_ID_MARVELL;
380 bridge->device = MARVELL_EMULATED_PCI_PCI_BRIDGE_ID;
381 bridge->header_type = PCI_HEADER_TYPE_BRIDGE;
382 bridge->cache_line_size = 0x10;
383
384 /* We support 32 bits I/O addressing */
385 bridge->iobase = PCI_IO_RANGE_TYPE_32;
386 bridge->iolimit = PCI_IO_RANGE_TYPE_32;
387}
388
389/*
390 * Read the configuration space of the PCI-to-PCI bridge associated to
391 * the given PCIe interface.
392 */
393static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port,
394 unsigned int where, int size, u32 *value)
395{
396 struct mvebu_sw_pci_bridge *bridge = &port->bridge;
397
398 switch (where & ~3) {
399 case PCI_VENDOR_ID:
400 *value = bridge->device << 16 | bridge->vendor;
401 break;
402
403 case PCI_COMMAND:
6eb237c4 404 *value = bridge->command;
45361a4f
TP		 405 break;
406
407 case PCI_CLASS_REVISION:
408 *value = bridge->class << 16 | bridge->interface << 8 |
409 bridge->revision;
410 break;
411
412 case PCI_CACHE_LINE_SIZE:
413 *value = bridge->bist << 24 | bridge->header_type << 16 |
414 bridge->latency_timer << 8 | bridge->cache_line_size;
415 break;
416
417 case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
418 *value = bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4];
419 break;
420
421 case PCI_PRIMARY_BUS:
422 *value = (bridge->secondary_latency_timer << 24 |
423 bridge->subordinate_bus << 16 |
424 bridge->secondary_bus << 8 |
425 bridge->primary_bus);
426 break;
427
428 case PCI_IO_BASE:
429 *value = (bridge->secondary_status << 16 |
430 bridge->iolimit << 8 |
431 bridge->iobase);
432 break;
433
434 case PCI_MEMORY_BASE:
435 *value = (bridge->memlimit << 16 | bridge->membase);
436 break;
437
438 case PCI_PREF_MEMORY_BASE:
36dd1f3e 439 *value = 0;
45361a4f
TP		 440 break;
441
442 case PCI_IO_BASE_UPPER16:
443 *value = (bridge->iolimitupper << 16 | bridge->iobaseupper);
444 break;
445
446 case PCI_ROM_ADDRESS1:
447 *value = 0;
448 break;
449
450 default:
451 *value = 0xffffffff;
452 return PCIBIOS_BAD_REGISTER_NUMBER;
453 }
454
455 if (size == 2)
456 *value = (*value >> (8 * (where & 3))) & 0xffff;
457 else if (size == 1)
458 *value = (*value >> (8 * (where & 3))) & 0xff;
459
460 return PCIBIOS_SUCCESSFUL;
461}
462
463/* Write to the PCI-to-PCI bridge configuration space */
464static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
465 unsigned int where, int size, u32 value)
466{
467 struct mvebu_sw_pci_bridge *bridge = &port->bridge;
468 u32 mask, reg;
469 int err;
470
471 if (size == 4)
472 mask = 0x0;
473 else if (size == 2)
474 mask = ~(0xffff << ((where & 3) * 8));
475 else if (size == 1)
476 mask = ~(0xff << ((where & 3) * 8));
477 else
478 return PCIBIOS_BAD_REGISTER_NUMBER;
479
480 err = mvebu_sw_pci_bridge_read(port, where & ~3, 4, &reg);
481 if (err)
482 return err;
483
484 value = (reg & mask) | value << ((where & 3) * 8);
485
486 switch (where & ~3) {
487 case PCI_COMMAND:
488 bridge->command = value & 0xffff;
45361a4f
TP		 489 break;
490
491 case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
492 bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4] = value;
493 break;
494
495 case PCI_IO_BASE:
496 /*
497 * We also keep bit 1 set, it is a read-only bit that
498 * indicates we support 32 bits addressing for the
499 * I/O
500 */
501 bridge->iobase = (value & 0xff) | PCI_IO_RANGE_TYPE_32;
502 bridge->iolimit = ((value >> 8) & 0xff) | PCI_IO_RANGE_TYPE_32;
503 bridge->secondary_status = value >> 16;
504 mvebu_pcie_handle_iobase_change(port);
505 break;
506
507 case PCI_MEMORY_BASE:
508 bridge->membase = value & 0xffff;
509 bridge->memlimit = value >> 16;
510 mvebu_pcie_handle_membase_change(port);
511 break;
512
45361a4f
TP		 513 case PCI_IO_BASE_UPPER16:
514 bridge->iobaseupper = value & 0xffff;
515 bridge->iolimitupper = value >> 16;
516 mvebu_pcie_handle_iobase_change(port);
517 break;
518
519 case PCI_PRIMARY_BUS:
520 bridge->primary_bus = value & 0xff;
521 bridge->secondary_bus = (value >> 8) & 0xff;
522 bridge->subordinate_bus = (value >> 16) & 0xff;
523 bridge->secondary_latency_timer = (value >> 24) & 0xff;
524 mvebu_pcie_set_local_bus_nr(port, bridge->secondary_bus);
525 break;
526
527 default:
528 break;
529 }
530
531 return PCIBIOS_SUCCESSFUL;
532}
533
534static inline struct mvebu_pcie *sys_to_pcie(struct pci_sys_data *sys)
535{
536 return sys->private_data;
537}
538
539static struct mvebu_pcie_port *
540mvebu_pcie_find_port(struct mvebu_pcie *pcie, struct pci_bus *bus,
541 int devfn)
542{
543 int i;
544
545 for (i = 0; i < pcie->nports; i++) {
546 struct mvebu_pcie_port *port = &pcie->ports[i];
547 if (bus->number == 0 && port->devfn == devfn)
548 return port;
549 if (bus->number != 0 &&
197fc226
TP		 550 bus->number >= port->bridge.secondary_bus &&
551 bus->number <= port->bridge.subordinate_bus)
45361a4f
TP		 552 return port;
553 }
554
555 return NULL;
556}
557
558/* PCI configuration space write function */
559static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
560 int where, int size, u32 val)
561{
562 struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
563 struct mvebu_pcie_port *port;
564 unsigned long flags;
565 int ret;
566
567 port = mvebu_pcie_find_port(pcie, bus, devfn);
568 if (!port)
569 return PCIBIOS_DEVICE_NOT_FOUND;
570
571 /* Access the emulated PCI-to-PCI bridge */
572 if (bus->number == 0)
573 return mvebu_sw_pci_bridge_write(port, where, size, val);
574
9f352f0e 575 if (!mvebu_pcie_link_up(port))
197fc226
TP		 576 return PCIBIOS_DEVICE_NOT_FOUND;
577
578 /*
579 * On the secondary bus, we don't want to expose any other
580 * device than the device physically connected in the PCIe
581 * slot, visible in slot 0. In slot 1, there's a special
582 * Marvell device that only makes sense when the Armada is
583 * used as a PCIe endpoint.
584 */
585 if (bus->number == port->bridge.secondary_bus &&
586 PCI_SLOT(devfn) != 0)
45361a4f
TP		 587 return PCIBIOS_DEVICE_NOT_FOUND;
588
589 /* Access the real PCIe interface */
590 spin_lock_irqsave(&port->conf_lock, flags);
f4ac9901 591 ret = mvebu_pcie_hw_wr_conf(port, bus, devfn,
45361a4f
TP		 592 where, size, val);
593 spin_unlock_irqrestore(&port->conf_lock, flags);
594
595 return ret;
596}
597
598/* PCI configuration space read function */
599static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
600 int size, u32 *val)
601{
602 struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
603 struct mvebu_pcie_port *port;
604 unsigned long flags;
605 int ret;
606
607 port = mvebu_pcie_find_port(pcie, bus, devfn);
608 if (!port) {
609 *val = 0xffffffff;
610 return PCIBIOS_DEVICE_NOT_FOUND;
611 }
612
613 /* Access the emulated PCI-to-PCI bridge */
614 if (bus->number == 0)
615 return mvebu_sw_pci_bridge_read(port, where, size, val);
616
9f352f0e 617 if (!mvebu_pcie_link_up(port)) {
197fc226
TP		 618 *val = 0xffffffff;
619 return PCIBIOS_DEVICE_NOT_FOUND;
620 }
621
622 /*
623 * On the secondary bus, we don't want to expose any other
624 * device than the device physically connected in the PCIe
625 * slot, visible in slot 0. In slot 1, there's a special
626 * Marvell device that only makes sense when the Armada is
627 * used as a PCIe endpoint.
628 */
629 if (bus->number == port->bridge.secondary_bus &&
630 PCI_SLOT(devfn) != 0) {
45361a4f
TP		 631 *val = 0xffffffff;
632 return PCIBIOS_DEVICE_NOT_FOUND;
633 }
634
635 /* Access the real PCIe interface */
636 spin_lock_irqsave(&port->conf_lock, flags);
f4ac9901 637 ret = mvebu_pcie_hw_rd_conf(port, bus, devfn,
45361a4f
TP		 638 where, size, val);
639 spin_unlock_irqrestore(&port->conf_lock, flags);
640
641 return ret;
642}
643
644static struct pci_ops mvebu_pcie_ops = {
645 .read = mvebu_pcie_rd_conf,
646 .write = mvebu_pcie_wr_conf,
647};
648
e5615c30 649static int mvebu_pcie_setup(int nr, struct pci_sys_data *sys)
45361a4f
TP		 650{
651 struct mvebu_pcie *pcie = sys_to_pcie(sys);
652 int i;
653
654 pci_add_resource_offset(&sys->resources, &pcie->realio, sys->io_offset);
655 pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset);
656 pci_add_resource(&sys->resources, &pcie->busn);
657
658 for (i = 0; i < pcie->nports; i++) {
659 struct mvebu_pcie_port *port = &pcie->ports[i];
b22503a9
EG		 660 if (!port->base)
661 continue;
45361a4f
TP		 662 mvebu_pcie_setup_hw(port);
663 }
664
665 return 1;
666}
667
e5615c30 668static int mvebu_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
45361a4f
TP		 669{
670 struct of_irq oirq;
671 int ret;
672
673 ret = of_irq_map_pci(dev, &oirq);
674 if (ret)
675 return ret;
676
677 return irq_create_of_mapping(oirq.controller, oirq.specifier,
678 oirq.size);
679}
680
681static struct pci_bus *mvebu_pcie_scan_bus(int nr, struct pci_sys_data *sys)
682{
683 struct mvebu_pcie *pcie = sys_to_pcie(sys);
684 struct pci_bus *bus;
685
686 bus = pci_create_root_bus(&pcie->pdev->dev, sys->busnr,
687 &mvebu_pcie_ops, sys, &sys->resources);
688 if (!bus)
689 return NULL;
690
691 pci_scan_child_bus(bus);
692
693 return bus;
694}
695
f5072dfb 696static void mvebu_pcie_add_bus(struct pci_bus *bus)
5b4deb65
TP		 697{
698 struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
699 bus->msi = pcie->msi;
700}
701
f5072dfb
JH		 702static resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev,
703 const struct resource *res,
704 resource_size_t start,
705 resource_size_t size,
706 resource_size_t align)
45361a4f
TP		 707{
708 if (dev->bus->number != 0)
709 return start;
710
711 /*
712 * On the PCI-to-PCI bridge side, the I/O windows must have at
713 * least a 64 KB size and be aligned on their size, and the
714 * memory windows must have at least a 1 MB size and be
715 * aligned on their size
716 */
717 if (res->flags & IORESOURCE_IO)
718 return round_up(start, max((resource_size_t)SZ_64K, size));
719 else if (res->flags & IORESOURCE_MEM)
720 return round_up(start, max((resource_size_t)SZ_1M, size));
721 else
722 return start;
723}
724
e5615c30 725static void mvebu_pcie_enable(struct mvebu_pcie *pcie)
45361a4f
TP		 726{
727 struct hw_pci hw;
728
729 memset(&hw, 0, sizeof(hw));
730
731 hw.nr_controllers = 1;
732 hw.private_data = (void **)&pcie;
733 hw.setup = mvebu_pcie_setup;
734 hw.scan = mvebu_pcie_scan_bus;
735 hw.map_irq = mvebu_pcie_map_irq;
736 hw.ops = &mvebu_pcie_ops;
737 hw.align_resource = mvebu_pcie_align_resource;
5b4deb65 738 hw.add_bus = mvebu_pcie_add_bus;
45361a4f
TP		 739
740 pci_common_init(&hw);
741}
742
743/*
744 * Looks up the list of register addresses encoded into the reg =
745 * <...> property for one that matches the given port/lane. Once
746 * found, maps it.
747 */
e5615c30
SH		 748static void __iomem *mvebu_pcie_map_registers(struct platform_device *pdev,
749 struct device_node *np, struct mvebu_pcie_port *port)
45361a4f
TP		 750{
751 struct resource regs;
752 int ret = 0;
753
754 ret = of_address_to_resource(np, 0, &regs);
755 if (ret)
f48fbf9c 756 return ERR_PTR(ret);
45361a4f 757
f48fbf9c 758 return devm_ioremap_resource(&pdev->dev, &regs);
45361a4f
TP		 759}
760
11be6547
TP		 761#define DT_FLAGS_TO_TYPE(flags) (((flags) >> 24) & 0x03)
762#define DT_TYPE_IO 0x1
763#define DT_TYPE_MEM32 0x2
764#define DT_CPUADDR_TO_TARGET(cpuaddr) (((cpuaddr) >> 56) & 0xFF)
765#define DT_CPUADDR_TO_ATTR(cpuaddr) (((cpuaddr) >> 48) & 0xFF)
766
767static int mvebu_get_tgt_attr(struct device_node *np, int devfn,
768 unsigned long type, int *tgt, int *attr)
769{
770 const int na = 3, ns = 2;
771 const __be32 *range;
772 int rlen, nranges, rangesz, pna, i;
773
774 range = of_get_property(np, "ranges", &rlen);
775 if (!range)
776 return -EINVAL;
777
778 pna = of_n_addr_cells(np);
779 rangesz = pna + na + ns;
780 nranges = rlen / sizeof(__be32) / rangesz;
781
782 for (i = 0; i < nranges; i++) {
783 u32 flags = of_read_number(range, 1);
784 u32 slot = of_read_number(range, 2);
785 u64 cpuaddr = of_read_number(range + na, pna);
786 unsigned long rtype;
787
788 if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_IO)
789 rtype = IORESOURCE_IO;
790 else if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_MEM32)
791 rtype = IORESOURCE_MEM;
792
793 if (slot == PCI_SLOT(devfn) && type == rtype) {
794 *tgt = DT_CPUADDR_TO_TARGET(cpuaddr);
795 *attr = DT_CPUADDR_TO_ATTR(cpuaddr);
796 return 0;
797 }
798
799 range += rangesz;
800 }
801
802 return -ENOENT;
803}
804
e5615c30 805static void mvebu_pcie_msi_enable(struct mvebu_pcie *pcie)
5b4deb65
TP		 806{
807 struct device_node *msi_node;
808
809 msi_node = of_parse_phandle(pcie->pdev->dev.of_node,
810 "msi-parent", 0);
811 if (!msi_node)
812 return;
813
814 pcie->msi = of_pci_find_msi_chip_by_node(msi_node);
815
816 if (pcie->msi)
817 pcie->msi->dev = &pcie->pdev->dev;
818}
819
e5615c30 820static int mvebu_pcie_probe(struct platform_device *pdev)
45361a4f
TP		 821{
822 struct mvebu_pcie *pcie;
823 struct device_node *np = pdev->dev.of_node;
45361a4f
TP		 824 struct device_node *child;
825 int i, ret;
826
827 pcie = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pcie),
828 GFP_KERNEL);
829 if (!pcie)
830 return -ENOMEM;
831
832 pcie->pdev = pdev;
e5615c30 833 platform_set_drvdata(pdev, pcie);
45361a4f 834
11be6547
TP		 835 /* Get the PCIe memory and I/O aperture */
836 mvebu_mbus_get_pcie_mem_aperture(&pcie->mem);
837 if (resource_size(&pcie->mem) == 0) {
838 dev_err(&pdev->dev, "invalid memory aperture size\n");
45361a4f 839 return -EINVAL;
11be6547 840 }
45361a4f 841
11be6547
TP		 842 mvebu_mbus_get_pcie_io_aperture(&pcie->io);
843 if (resource_size(&pcie->io) == 0) {
844 dev_err(&pdev->dev, "invalid I/O aperture size\n");
845 return -EINVAL;
45361a4f
TP		 846 }
847
11be6547
TP		 848 pcie->realio.flags = pcie->io.flags;
849 pcie->realio.start = PCIBIOS_MIN_IO;
850 pcie->realio.end = min_t(resource_size_t,
851 IO_SPACE_LIMIT,
852 resource_size(&pcie->io));
853
45361a4f
TP		 854 /* Get the bus range */
855 ret = of_pci_parse_bus_range(np, &pcie->busn);
856 if (ret) {
857 dev_err(&pdev->dev, "failed to parse bus-range property: %d\n",
858 ret);
859 return ret;
860 }
861
bf09b6ae 862 i = 0;
45361a4f
TP		 863 for_each_child_of_node(pdev->dev.of_node, child) {
864 if (!of_device_is_available(child))
865 continue;
bf09b6ae 866 i++;
45361a4f
TP		 867 }
868
bf09b6ae 869 pcie->ports = devm_kzalloc(&pdev->dev, i *
45361a4f
TP		 870 sizeof(struct mvebu_pcie_port),
871 GFP_KERNEL);
872 if (!pcie->ports)
873 return -ENOMEM;
874
875 i = 0;
876 for_each_child_of_node(pdev->dev.of_node, child) {
877 struct mvebu_pcie_port *port = &pcie->ports[i];
52ba992e 878 enum of_gpio_flags flags;
45361a4f
TP		 879
880 if (!of_device_is_available(child))
881 continue;
882
883 port->pcie = pcie;
884
885 if (of_property_read_u32(child, "marvell,pcie-port",
886 &port->port)) {
887 dev_warn(&pdev->dev,
888 "ignoring PCIe DT node, missing pcie-port property\n");
889 continue;
890 }
891
892 if (of_property_read_u32(child, "marvell,pcie-lane",
893 &port->lane))
894 port->lane = 0;
895
896 port->name = kasprintf(GFP_KERNEL, "pcie%d.%d",
897 port->port, port->lane);
898
899 port->devfn = of_pci_get_devfn(child);
900 if (port->devfn < 0)
901 continue;
902
11be6547
TP		 903 ret = mvebu_get_tgt_attr(np, port->devfn, IORESOURCE_MEM,
904 &port->mem_target, &port->mem_attr);
905 if (ret < 0) {
906 dev_err(&pdev->dev, "PCIe%d.%d: cannot get tgt/attr for mem window\n",
907 port->port, port->lane);
908 continue;
909 }
910
911 ret = mvebu_get_tgt_attr(np, port->devfn, IORESOURCE_IO,
912 &port->io_target, &port->io_attr);
913 if (ret < 0) {
914 dev_err(&pdev->dev, "PCIe%d.%d: cannot get tgt/attr for io window\n",
915 port->port, port->lane);
916 continue;
917 }
918
52ba992e
SH		 919 port->reset_gpio = of_get_named_gpio_flags(child,
920 "reset-gpios", 0, &flags);
921 if (gpio_is_valid(port->reset_gpio)) {
922 u32 reset_udelay = 20000;
923
924 port->reset_active_low = flags & OF_GPIO_ACTIVE_LOW;
925 port->reset_name = kasprintf(GFP_KERNEL,
926 "pcie%d.%d-reset", port->port, port->lane);
927 of_property_read_u32(child, "reset-delay-us",
928 &reset_udelay);
929
930 ret = devm_gpio_request_one(&pdev->dev,
931 port->reset_gpio, GPIOF_DIR_OUT, port->reset_name);
932 if (ret) {
933 if (ret == -EPROBE_DEFER)
934 return ret;
935 continue;
936 }
937
938 gpio_set_value(port->reset_gpio,
939 (port->reset_active_low) ? 1 : 0);
940 msleep(reset_udelay/1000);
941 }
942
b42285f6
SH		 943 port->clk = of_clk_get_by_name(child, NULL);
944 if (IS_ERR(port->clk)) {
945 dev_err(&pdev->dev, "PCIe%d.%d: cannot get clock\n",
946 port->port, port->lane);
947 continue;
948 }
949
950 ret = clk_prepare_enable(port->clk);
951 if (ret)
952 continue;
953
45361a4f 954 port->base = mvebu_pcie_map_registers(pdev, child, port);
f48fbf9c 955 if (IS_ERR(port->base)) {
45361a4f
TP		 956 dev_err(&pdev->dev, "PCIe%d.%d: cannot map registers\n",
957 port->port, port->lane);
f48fbf9c 958 port->base = NULL;
b42285f6 959 clk_disable_unprepare(port->clk);
45361a4f
TP		 960 continue;
961 }
962
f4ac9901
TP		 963 mvebu_pcie_set_local_dev_nr(port, 1);
964
9f352f0e
JG		 965 port->clk = of_clk_get_by_name(child, NULL);
966 if (IS_ERR(port->clk)) {
967 dev_err(&pdev->dev, "PCIe%d.%d: cannot get clock\n",
968 port->port, port->lane);
969 iounmap(port->base);
970 continue;
45361a4f
TP		 971 }
972
45361a4f 973 port->dn = child;
45361a4f 974 spin_lock_init(&port->conf_lock);
45361a4f 975 mvebu_sw_pci_bridge_init(port);
45361a4f
TP		 976 i++;
977 }
978
bf09b6ae 979 pcie->nports = i;
5b4deb65 980 mvebu_pcie_msi_enable(pcie);
45361a4f
TP		 981 mvebu_pcie_enable(pcie);
982
983 return 0;
984}
985
986static const struct of_device_id mvebu_pcie_of_match_table[] = {
987 { .compatible = "marvell,armada-xp-pcie", },
988 { .compatible = "marvell,armada-370-pcie", },
cc54ccd9 989 { .compatible = "marvell,dove-pcie", },
005625fc 990 { .compatible = "marvell,kirkwood-pcie", },
45361a4f
TP		 991 {},
992};
993MODULE_DEVICE_TABLE(of, mvebu_pcie_of_match_table);
994
995static struct platform_driver mvebu_pcie_driver = {
996 .driver = {
997 .owner = THIS_MODULE,
998 .name = "mvebu-pcie",
999 .of_match_table =
1000 of_match_ptr(mvebu_pcie_of_match_table),
e5615c30
SH		 1001 /* driver unloading/unbinding currently not supported */
1002 .suppress_bind_attrs = true,
45361a4f 1003 },
e5615c30 1004 .probe = mvebu_pcie_probe,
45361a4f 1005};
e5615c30 1006module_platform_driver(mvebu_pcie_driver);
45361a4f
TP		 1007
1008MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
1009MODULE_DESCRIPTION("Marvell EBU PCIe driver");
1010MODULE_LICENSE("GPLv2");
Linux kernel - Deliverables
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