Commit | Line | Data |
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d1523b52 | 1 | /* |
94716cdd | 2 | * PCIe host controller driver for Tegra SoCs |
d1523b52 TR |
3 | * |
4 | * Copyright (c) 2010, CompuLab, Ltd. | |
5 | * Author: Mike Rapoport <mike@compulab.co.il> | |
6 | * | |
7 | * Based on NVIDIA PCIe driver | |
8 | * Copyright (c) 2008-2009, NVIDIA Corporation. | |
9 | * | |
10 | * Bits taken from arch/arm/mach-dove/pcie.c | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
18 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
19 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
20 | * more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License along | |
23 | * with this program; if not, write to the Free Software Foundation, Inc., | |
24 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. | |
25 | */ | |
26 | ||
27 | #include <linux/clk.h> | |
2cb989f6 | 28 | #include <linux/debugfs.h> |
d1523b52 TR |
29 | #include <linux/delay.h> |
30 | #include <linux/export.h> | |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/irq.h> | |
33 | #include <linux/irqdomain.h> | |
34 | #include <linux/kernel.h> | |
35 | #include <linux/module.h> | |
36 | #include <linux/msi.h> | |
37 | #include <linux/of_address.h> | |
38 | #include <linux/of_pci.h> | |
39 | #include <linux/of_platform.h> | |
40 | #include <linux/pci.h> | |
7f1f054b | 41 | #include <linux/phy/phy.h> |
d1523b52 | 42 | #include <linux/platform_device.h> |
3127a6b2 | 43 | #include <linux/reset.h> |
d1523b52 TR |
44 | #include <linux/sizes.h> |
45 | #include <linux/slab.h> | |
d1523b52 TR |
46 | #include <linux/vmalloc.h> |
47 | #include <linux/regulator/consumer.h> | |
48 | ||
306a7f91 | 49 | #include <soc/tegra/cpuidle.h> |
7232398a | 50 | #include <soc/tegra/pmc.h> |
306a7f91 | 51 | |
d1523b52 TR |
52 | #include <asm/mach/irq.h> |
53 | #include <asm/mach/map.h> | |
54 | #include <asm/mach/pci.h> | |
55 | ||
56 | #define INT_PCI_MSI_NR (8 * 32) | |
d1523b52 TR |
57 | |
58 | /* register definitions */ | |
59 | ||
60 | #define AFI_AXI_BAR0_SZ 0x00 | |
61 | #define AFI_AXI_BAR1_SZ 0x04 | |
62 | #define AFI_AXI_BAR2_SZ 0x08 | |
63 | #define AFI_AXI_BAR3_SZ 0x0c | |
64 | #define AFI_AXI_BAR4_SZ 0x10 | |
65 | #define AFI_AXI_BAR5_SZ 0x14 | |
66 | ||
67 | #define AFI_AXI_BAR0_START 0x18 | |
68 | #define AFI_AXI_BAR1_START 0x1c | |
69 | #define AFI_AXI_BAR2_START 0x20 | |
70 | #define AFI_AXI_BAR3_START 0x24 | |
71 | #define AFI_AXI_BAR4_START 0x28 | |
72 | #define AFI_AXI_BAR5_START 0x2c | |
73 | ||
74 | #define AFI_FPCI_BAR0 0x30 | |
75 | #define AFI_FPCI_BAR1 0x34 | |
76 | #define AFI_FPCI_BAR2 0x38 | |
77 | #define AFI_FPCI_BAR3 0x3c | |
78 | #define AFI_FPCI_BAR4 0x40 | |
79 | #define AFI_FPCI_BAR5 0x44 | |
80 | ||
81 | #define AFI_CACHE_BAR0_SZ 0x48 | |
82 | #define AFI_CACHE_BAR0_ST 0x4c | |
83 | #define AFI_CACHE_BAR1_SZ 0x50 | |
84 | #define AFI_CACHE_BAR1_ST 0x54 | |
85 | ||
86 | #define AFI_MSI_BAR_SZ 0x60 | |
87 | #define AFI_MSI_FPCI_BAR_ST 0x64 | |
88 | #define AFI_MSI_AXI_BAR_ST 0x68 | |
89 | ||
90 | #define AFI_MSI_VEC0 0x6c | |
91 | #define AFI_MSI_VEC1 0x70 | |
92 | #define AFI_MSI_VEC2 0x74 | |
93 | #define AFI_MSI_VEC3 0x78 | |
94 | #define AFI_MSI_VEC4 0x7c | |
95 | #define AFI_MSI_VEC5 0x80 | |
96 | #define AFI_MSI_VEC6 0x84 | |
97 | #define AFI_MSI_VEC7 0x88 | |
98 | ||
99 | #define AFI_MSI_EN_VEC0 0x8c | |
100 | #define AFI_MSI_EN_VEC1 0x90 | |
101 | #define AFI_MSI_EN_VEC2 0x94 | |
102 | #define AFI_MSI_EN_VEC3 0x98 | |
103 | #define AFI_MSI_EN_VEC4 0x9c | |
104 | #define AFI_MSI_EN_VEC5 0xa0 | |
105 | #define AFI_MSI_EN_VEC6 0xa4 | |
106 | #define AFI_MSI_EN_VEC7 0xa8 | |
107 | ||
108 | #define AFI_CONFIGURATION 0xac | |
109 | #define AFI_CONFIGURATION_EN_FPCI (1 << 0) | |
110 | ||
111 | #define AFI_FPCI_ERROR_MASKS 0xb0 | |
112 | ||
113 | #define AFI_INTR_MASK 0xb4 | |
114 | #define AFI_INTR_MASK_INT_MASK (1 << 0) | |
115 | #define AFI_INTR_MASK_MSI_MASK (1 << 8) | |
116 | ||
117 | #define AFI_INTR_CODE 0xb8 | |
118 | #define AFI_INTR_CODE_MASK 0xf | |
7f1f054b TR |
119 | #define AFI_INTR_INI_SLAVE_ERROR 1 |
120 | #define AFI_INTR_INI_DECODE_ERROR 2 | |
d1523b52 TR |
121 | #define AFI_INTR_TARGET_ABORT 3 |
122 | #define AFI_INTR_MASTER_ABORT 4 | |
123 | #define AFI_INTR_INVALID_WRITE 5 | |
124 | #define AFI_INTR_LEGACY 6 | |
125 | #define AFI_INTR_FPCI_DECODE_ERROR 7 | |
7f1f054b TR |
126 | #define AFI_INTR_AXI_DECODE_ERROR 8 |
127 | #define AFI_INTR_FPCI_TIMEOUT 9 | |
128 | #define AFI_INTR_PE_PRSNT_SENSE 10 | |
129 | #define AFI_INTR_PE_CLKREQ_SENSE 11 | |
130 | #define AFI_INTR_CLKCLAMP_SENSE 12 | |
131 | #define AFI_INTR_RDY4PD_SENSE 13 | |
132 | #define AFI_INTR_P2P_ERROR 14 | |
d1523b52 TR |
133 | |
134 | #define AFI_INTR_SIGNATURE 0xbc | |
135 | #define AFI_UPPER_FPCI_ADDRESS 0xc0 | |
136 | #define AFI_SM_INTR_ENABLE 0xc4 | |
137 | #define AFI_SM_INTR_INTA_ASSERT (1 << 0) | |
138 | #define AFI_SM_INTR_INTB_ASSERT (1 << 1) | |
139 | #define AFI_SM_INTR_INTC_ASSERT (1 << 2) | |
140 | #define AFI_SM_INTR_INTD_ASSERT (1 << 3) | |
141 | #define AFI_SM_INTR_INTA_DEASSERT (1 << 4) | |
142 | #define AFI_SM_INTR_INTB_DEASSERT (1 << 5) | |
143 | #define AFI_SM_INTR_INTC_DEASSERT (1 << 6) | |
144 | #define AFI_SM_INTR_INTD_DEASSERT (1 << 7) | |
145 | ||
146 | #define AFI_AFI_INTR_ENABLE 0xc8 | |
147 | #define AFI_INTR_EN_INI_SLVERR (1 << 0) | |
148 | #define AFI_INTR_EN_INI_DECERR (1 << 1) | |
149 | #define AFI_INTR_EN_TGT_SLVERR (1 << 2) | |
150 | #define AFI_INTR_EN_TGT_DECERR (1 << 3) | |
151 | #define AFI_INTR_EN_TGT_WRERR (1 << 4) | |
152 | #define AFI_INTR_EN_DFPCI_DECERR (1 << 5) | |
153 | #define AFI_INTR_EN_AXI_DECERR (1 << 6) | |
154 | #define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7) | |
94716cdd | 155 | #define AFI_INTR_EN_PRSNT_SENSE (1 << 8) |
d1523b52 TR |
156 | |
157 | #define AFI_PCIE_CONFIG 0x0f8 | |
158 | #define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1)) | |
159 | #define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL 0xe | |
160 | #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20) | |
161 | #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE (0x0 << 20) | |
94716cdd | 162 | #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420 (0x0 << 20) |
7f1f054b | 163 | #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1 (0x0 << 20) |
d1523b52 | 164 | #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL (0x1 << 20) |
94716cdd | 165 | #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222 (0x1 << 20) |
7f1f054b | 166 | #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1 (0x1 << 20) |
94716cdd | 167 | #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411 (0x2 << 20) |
d1523b52 TR |
168 | |
169 | #define AFI_FUSE 0x104 | |
170 | #define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2) | |
171 | ||
172 | #define AFI_PEX0_CTRL 0x110 | |
173 | #define AFI_PEX1_CTRL 0x118 | |
94716cdd | 174 | #define AFI_PEX2_CTRL 0x128 |
d1523b52 | 175 | #define AFI_PEX_CTRL_RST (1 << 0) |
94716cdd | 176 | #define AFI_PEX_CTRL_CLKREQ_EN (1 << 1) |
d1523b52 | 177 | #define AFI_PEX_CTRL_REFCLK_EN (1 << 3) |
7f1f054b TR |
178 | #define AFI_PEX_CTRL_OVERRIDE_EN (1 << 4) |
179 | ||
180 | #define AFI_PLLE_CONTROL 0x160 | |
181 | #define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL (1 << 9) | |
182 | #define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN (1 << 1) | |
d1523b52 | 183 | |
94716cdd JA |
184 | #define AFI_PEXBIAS_CTRL_0 0x168 |
185 | ||
d1523b52 TR |
186 | #define RP_VEND_XP 0x00000F00 |
187 | #define RP_VEND_XP_DL_UP (1 << 30) | |
188 | ||
7f1f054b TR |
189 | #define RP_PRIV_MISC 0x00000FE0 |
190 | #define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xE << 0) | |
191 | #define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xF << 0) | |
192 | ||
d1523b52 TR |
193 | #define RP_LINK_CONTROL_STATUS 0x00000090 |
194 | #define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000 | |
195 | #define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000 | |
196 | ||
197 | #define PADS_CTL_SEL 0x0000009C | |
198 | ||
199 | #define PADS_CTL 0x000000A0 | |
200 | #define PADS_CTL_IDDQ_1L (1 << 0) | |
201 | #define PADS_CTL_TX_DATA_EN_1L (1 << 6) | |
202 | #define PADS_CTL_RX_DATA_EN_1L (1 << 10) | |
203 | ||
94716cdd JA |
204 | #define PADS_PLL_CTL_TEGRA20 0x000000B8 |
205 | #define PADS_PLL_CTL_TEGRA30 0x000000B4 | |
d1523b52 TR |
206 | #define PADS_PLL_CTL_RST_B4SM (1 << 1) |
207 | #define PADS_PLL_CTL_LOCKDET (1 << 8) | |
208 | #define PADS_PLL_CTL_REFCLK_MASK (0x3 << 16) | |
209 | #define PADS_PLL_CTL_REFCLK_INTERNAL_CML (0 << 16) | |
210 | #define PADS_PLL_CTL_REFCLK_INTERNAL_CMOS (1 << 16) | |
211 | #define PADS_PLL_CTL_REFCLK_EXTERNAL (2 << 16) | |
212 | #define PADS_PLL_CTL_TXCLKREF_MASK (0x1 << 20) | |
213 | #define PADS_PLL_CTL_TXCLKREF_DIV10 (0 << 20) | |
214 | #define PADS_PLL_CTL_TXCLKREF_DIV5 (1 << 20) | |
94716cdd JA |
215 | #define PADS_PLL_CTL_TXCLKREF_BUF_EN (1 << 22) |
216 | ||
217 | #define PADS_REFCLK_CFG0 0x000000C8 | |
218 | #define PADS_REFCLK_CFG1 0x000000CC | |
7f1f054b | 219 | #define PADS_REFCLK_BIAS 0x000000D0 |
d1523b52 | 220 | |
b02b07ad SW |
221 | /* |
222 | * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit | |
223 | * entries, one entry per PCIe port. These field definitions and desired | |
224 | * values aren't in the TRM, but do come from NVIDIA. | |
225 | */ | |
226 | #define PADS_REFCLK_CFG_TERM_SHIFT 2 /* 6:2 */ | |
227 | #define PADS_REFCLK_CFG_E_TERM_SHIFT 7 | |
228 | #define PADS_REFCLK_CFG_PREDI_SHIFT 8 /* 11:8 */ | |
229 | #define PADS_REFCLK_CFG_DRVI_SHIFT 12 /* 15:12 */ | |
230 | ||
231 | /* Default value provided by HW engineering is 0xfa5c */ | |
232 | #define PADS_REFCLK_CFG_VALUE \ | |
233 | ( \ | |
234 | (0x17 << PADS_REFCLK_CFG_TERM_SHIFT) | \ | |
235 | (0 << PADS_REFCLK_CFG_E_TERM_SHIFT) | \ | |
236 | (0xa << PADS_REFCLK_CFG_PREDI_SHIFT) | \ | |
237 | (0xf << PADS_REFCLK_CFG_DRVI_SHIFT) \ | |
238 | ) | |
239 | ||
d1523b52 | 240 | struct tegra_msi { |
c2791b80 | 241 | struct msi_controller chip; |
d1523b52 TR |
242 | DECLARE_BITMAP(used, INT_PCI_MSI_NR); |
243 | struct irq_domain *domain; | |
244 | unsigned long pages; | |
245 | struct mutex lock; | |
246 | int irq; | |
247 | }; | |
248 | ||
94716cdd JA |
249 | /* used to differentiate between Tegra SoC generations */ |
250 | struct tegra_pcie_soc_data { | |
251 | unsigned int num_ports; | |
252 | unsigned int msi_base_shift; | |
253 | u32 pads_pll_ctl; | |
254 | u32 tx_ref_sel; | |
255 | bool has_pex_clkreq_en; | |
256 | bool has_pex_bias_ctrl; | |
257 | bool has_intr_prsnt_sense; | |
94716cdd | 258 | bool has_cml_clk; |
7f1f054b | 259 | bool has_gen2; |
94716cdd JA |
260 | }; |
261 | ||
c2791b80 | 262 | static inline struct tegra_msi *to_tegra_msi(struct msi_controller *chip) |
d1523b52 TR |
263 | { |
264 | return container_of(chip, struct tegra_msi, chip); | |
265 | } | |
266 | ||
267 | struct tegra_pcie { | |
268 | struct device *dev; | |
269 | ||
270 | void __iomem *pads; | |
271 | void __iomem *afi; | |
272 | int irq; | |
273 | ||
f7625980 | 274 | struct list_head buses; |
d1523b52 TR |
275 | struct resource *cs; |
276 | ||
41534e53 | 277 | struct resource all; |
d1523b52 | 278 | struct resource io; |
5106787a | 279 | struct resource pio; |
d1523b52 TR |
280 | struct resource mem; |
281 | struct resource prefetch; | |
282 | struct resource busn; | |
283 | ||
56e75e2a TR |
284 | struct { |
285 | resource_size_t mem; | |
286 | resource_size_t io; | |
287 | } offset; | |
288 | ||
d1523b52 TR |
289 | struct clk *pex_clk; |
290 | struct clk *afi_clk; | |
d1523b52 | 291 | struct clk *pll_e; |
94716cdd | 292 | struct clk *cml_clk; |
d1523b52 | 293 | |
3127a6b2 SW |
294 | struct reset_control *pex_rst; |
295 | struct reset_control *afi_rst; | |
296 | struct reset_control *pcie_xrst; | |
297 | ||
7f1f054b TR |
298 | struct phy *phy; |
299 | ||
d1523b52 TR |
300 | struct tegra_msi msi; |
301 | ||
302 | struct list_head ports; | |
d1523b52 TR |
303 | u32 xbar_config; |
304 | ||
077fb158 TR |
305 | struct regulator_bulk_data *supplies; |
306 | unsigned int num_supplies; | |
94716cdd JA |
307 | |
308 | const struct tegra_pcie_soc_data *soc_data; | |
2cb989f6 | 309 | struct dentry *debugfs; |
d1523b52 TR |
310 | }; |
311 | ||
312 | struct tegra_pcie_port { | |
313 | struct tegra_pcie *pcie; | |
314 | struct list_head list; | |
315 | struct resource regs; | |
316 | void __iomem *base; | |
317 | unsigned int index; | |
318 | unsigned int lanes; | |
319 | }; | |
320 | ||
321 | struct tegra_pcie_bus { | |
322 | struct vm_struct *area; | |
323 | struct list_head list; | |
324 | unsigned int nr; | |
325 | }; | |
326 | ||
327 | static inline struct tegra_pcie *sys_to_pcie(struct pci_sys_data *sys) | |
328 | { | |
329 | return sys->private_data; | |
330 | } | |
331 | ||
332 | static inline void afi_writel(struct tegra_pcie *pcie, u32 value, | |
333 | unsigned long offset) | |
334 | { | |
335 | writel(value, pcie->afi + offset); | |
336 | } | |
337 | ||
338 | static inline u32 afi_readl(struct tegra_pcie *pcie, unsigned long offset) | |
339 | { | |
340 | return readl(pcie->afi + offset); | |
341 | } | |
342 | ||
343 | static inline void pads_writel(struct tegra_pcie *pcie, u32 value, | |
344 | unsigned long offset) | |
345 | { | |
346 | writel(value, pcie->pads + offset); | |
347 | } | |
348 | ||
349 | static inline u32 pads_readl(struct tegra_pcie *pcie, unsigned long offset) | |
350 | { | |
351 | return readl(pcie->pads + offset); | |
352 | } | |
353 | ||
354 | /* | |
355 | * The configuration space mapping on Tegra is somewhat similar to the ECAM | |
356 | * defined by PCIe. However it deviates a bit in how the 4 bits for extended | |
357 | * register accesses are mapped: | |
358 | * | |
359 | * [27:24] extended register number | |
360 | * [23:16] bus number | |
361 | * [15:11] device number | |
362 | * [10: 8] function number | |
363 | * [ 7: 0] register number | |
364 | * | |
365 | * Mapping the whole extended configuration space would require 256 MiB of | |
366 | * virtual address space, only a small part of which will actually be used. | |
367 | * To work around this, a 1 MiB of virtual addresses are allocated per bus | |
368 | * when the bus is first accessed. When the physical range is mapped, the | |
369 | * the bus number bits are hidden so that the extended register number bits | |
370 | * appear as bits [19:16]. Therefore the virtual mapping looks like this: | |
371 | * | |
372 | * [19:16] extended register number | |
373 | * [15:11] device number | |
374 | * [10: 8] function number | |
375 | * [ 7: 0] register number | |
376 | * | |
377 | * This is achieved by stitching together 16 chunks of 64 KiB of physical | |
378 | * address space via the MMU. | |
379 | */ | |
380 | static unsigned long tegra_pcie_conf_offset(unsigned int devfn, int where) | |
381 | { | |
382 | return ((where & 0xf00) << 8) | (PCI_SLOT(devfn) << 11) | | |
383 | (PCI_FUNC(devfn) << 8) | (where & 0xfc); | |
384 | } | |
385 | ||
386 | static struct tegra_pcie_bus *tegra_pcie_bus_alloc(struct tegra_pcie *pcie, | |
387 | unsigned int busnr) | |
388 | { | |
512ee2fd AB |
389 | pgprot_t prot = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | |
390 | L_PTE_XN | L_PTE_MT_DEV_SHARED | L_PTE_SHARED); | |
d1523b52 TR |
391 | phys_addr_t cs = pcie->cs->start; |
392 | struct tegra_pcie_bus *bus; | |
393 | unsigned int i; | |
394 | int err; | |
395 | ||
396 | bus = kzalloc(sizeof(*bus), GFP_KERNEL); | |
397 | if (!bus) | |
398 | return ERR_PTR(-ENOMEM); | |
399 | ||
400 | INIT_LIST_HEAD(&bus->list); | |
401 | bus->nr = busnr; | |
402 | ||
403 | /* allocate 1 MiB of virtual addresses */ | |
404 | bus->area = get_vm_area(SZ_1M, VM_IOREMAP); | |
405 | if (!bus->area) { | |
406 | err = -ENOMEM; | |
407 | goto free; | |
408 | } | |
409 | ||
410 | /* map each of the 16 chunks of 64 KiB each */ | |
411 | for (i = 0; i < 16; i++) { | |
412 | unsigned long virt = (unsigned long)bus->area->addr + | |
413 | i * SZ_64K; | |
8d41794c | 414 | phys_addr_t phys = cs + i * SZ_16M + busnr * SZ_64K; |
d1523b52 TR |
415 | |
416 | err = ioremap_page_range(virt, virt + SZ_64K, phys, prot); | |
417 | if (err < 0) { | |
418 | dev_err(pcie->dev, "ioremap_page_range() failed: %d\n", | |
419 | err); | |
420 | goto unmap; | |
421 | } | |
422 | } | |
423 | ||
424 | return bus; | |
425 | ||
426 | unmap: | |
427 | vunmap(bus->area->addr); | |
428 | free: | |
429 | kfree(bus); | |
430 | return ERR_PTR(err); | |
431 | } | |
432 | ||
b4d18d71 | 433 | static int tegra_pcie_add_bus(struct pci_bus *bus) |
d1523b52 | 434 | { |
b4d18d71 TR |
435 | struct tegra_pcie *pcie = sys_to_pcie(bus->sysdata); |
436 | struct tegra_pcie_bus *b; | |
d1523b52 | 437 | |
b4d18d71 TR |
438 | b = tegra_pcie_bus_alloc(pcie, bus->number); |
439 | if (IS_ERR(b)) | |
440 | return PTR_ERR(b); | |
d1523b52 | 441 | |
b4d18d71 | 442 | list_add_tail(&b->list, &pcie->buses); |
d1523b52 | 443 | |
b4d18d71 TR |
444 | return 0; |
445 | } | |
d1523b52 | 446 | |
b4d18d71 TR |
447 | static void tegra_pcie_remove_bus(struct pci_bus *child) |
448 | { | |
449 | struct tegra_pcie *pcie = sys_to_pcie(child->sysdata); | |
450 | struct tegra_pcie_bus *bus, *tmp; | |
451 | ||
452 | list_for_each_entry_safe(bus, tmp, &pcie->buses, list) { | |
453 | if (bus->nr == child->number) { | |
454 | vunmap(bus->area->addr); | |
455 | list_del(&bus->list); | |
456 | kfree(bus); | |
457 | break; | |
458 | } | |
459 | } | |
d1523b52 TR |
460 | } |
461 | ||
b4d18d71 TR |
462 | static void __iomem *tegra_pcie_map_bus(struct pci_bus *bus, |
463 | unsigned int devfn, | |
464 | int where) | |
d1523b52 TR |
465 | { |
466 | struct tegra_pcie *pcie = sys_to_pcie(bus->sysdata); | |
467 | void __iomem *addr = NULL; | |
468 | ||
469 | if (bus->number == 0) { | |
470 | unsigned int slot = PCI_SLOT(devfn); | |
471 | struct tegra_pcie_port *port; | |
472 | ||
473 | list_for_each_entry(port, &pcie->ports, list) { | |
474 | if (port->index + 1 == slot) { | |
475 | addr = port->base + (where & ~3); | |
476 | break; | |
477 | } | |
478 | } | |
479 | } else { | |
b4d18d71 TR |
480 | struct tegra_pcie_bus *b; |
481 | ||
482 | list_for_each_entry(b, &pcie->buses, list) | |
483 | if (b->nr == bus->number) | |
484 | addr = (void __iomem *)b->area->addr; | |
485 | ||
d1523b52 TR |
486 | if (!addr) { |
487 | dev_err(pcie->dev, | |
488 | "failed to map cfg. space for bus %u\n", | |
489 | bus->number); | |
490 | return NULL; | |
491 | } | |
492 | ||
493 | addr += tegra_pcie_conf_offset(devfn, where); | |
494 | } | |
495 | ||
496 | return addr; | |
497 | } | |
498 | ||
d1523b52 | 499 | static struct pci_ops tegra_pcie_ops = { |
b4d18d71 TR |
500 | .add_bus = tegra_pcie_add_bus, |
501 | .remove_bus = tegra_pcie_remove_bus, | |
502 | .map_bus = tegra_pcie_map_bus, | |
0e7ac8de RH |
503 | .read = pci_generic_config_read32, |
504 | .write = pci_generic_config_write32, | |
d1523b52 TR |
505 | }; |
506 | ||
507 | static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port) | |
508 | { | |
509 | unsigned long ret = 0; | |
510 | ||
511 | switch (port->index) { | |
512 | case 0: | |
513 | ret = AFI_PEX0_CTRL; | |
514 | break; | |
515 | ||
516 | case 1: | |
517 | ret = AFI_PEX1_CTRL; | |
518 | break; | |
94716cdd JA |
519 | |
520 | case 2: | |
521 | ret = AFI_PEX2_CTRL; | |
522 | break; | |
d1523b52 TR |
523 | } |
524 | ||
525 | return ret; | |
526 | } | |
527 | ||
528 | static void tegra_pcie_port_reset(struct tegra_pcie_port *port) | |
529 | { | |
530 | unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port); | |
531 | unsigned long value; | |
532 | ||
533 | /* pulse reset signal */ | |
534 | value = afi_readl(port->pcie, ctrl); | |
535 | value &= ~AFI_PEX_CTRL_RST; | |
536 | afi_writel(port->pcie, value, ctrl); | |
537 | ||
538 | usleep_range(1000, 2000); | |
539 | ||
540 | value = afi_readl(port->pcie, ctrl); | |
541 | value |= AFI_PEX_CTRL_RST; | |
542 | afi_writel(port->pcie, value, ctrl); | |
543 | } | |
544 | ||
545 | static void tegra_pcie_port_enable(struct tegra_pcie_port *port) | |
546 | { | |
94716cdd | 547 | const struct tegra_pcie_soc_data *soc = port->pcie->soc_data; |
d1523b52 TR |
548 | unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port); |
549 | unsigned long value; | |
550 | ||
551 | /* enable reference clock */ | |
552 | value = afi_readl(port->pcie, ctrl); | |
553 | value |= AFI_PEX_CTRL_REFCLK_EN; | |
94716cdd JA |
554 | |
555 | if (soc->has_pex_clkreq_en) | |
556 | value |= AFI_PEX_CTRL_CLKREQ_EN; | |
557 | ||
7f1f054b TR |
558 | value |= AFI_PEX_CTRL_OVERRIDE_EN; |
559 | ||
d1523b52 TR |
560 | afi_writel(port->pcie, value, ctrl); |
561 | ||
562 | tegra_pcie_port_reset(port); | |
563 | } | |
564 | ||
565 | static void tegra_pcie_port_disable(struct tegra_pcie_port *port) | |
566 | { | |
0d20d621 | 567 | const struct tegra_pcie_soc_data *soc = port->pcie->soc_data; |
d1523b52 TR |
568 | unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port); |
569 | unsigned long value; | |
570 | ||
571 | /* assert port reset */ | |
572 | value = afi_readl(port->pcie, ctrl); | |
573 | value &= ~AFI_PEX_CTRL_RST; | |
574 | afi_writel(port->pcie, value, ctrl); | |
575 | ||
576 | /* disable reference clock */ | |
577 | value = afi_readl(port->pcie, ctrl); | |
0d20d621 TR |
578 | |
579 | if (soc->has_pex_clkreq_en) | |
580 | value &= ~AFI_PEX_CTRL_CLKREQ_EN; | |
581 | ||
d1523b52 TR |
582 | value &= ~AFI_PEX_CTRL_REFCLK_EN; |
583 | afi_writel(port->pcie, value, ctrl); | |
584 | } | |
585 | ||
586 | static void tegra_pcie_port_free(struct tegra_pcie_port *port) | |
587 | { | |
588 | struct tegra_pcie *pcie = port->pcie; | |
589 | ||
590 | devm_iounmap(pcie->dev, port->base); | |
591 | devm_release_mem_region(pcie->dev, port->regs.start, | |
592 | resource_size(&port->regs)); | |
593 | list_del(&port->list); | |
594 | devm_kfree(pcie->dev, port); | |
595 | } | |
596 | ||
d1523b52 TR |
597 | /* Tegra PCIE root complex wrongly reports device class */ |
598 | static void tegra_pcie_fixup_class(struct pci_dev *dev) | |
599 | { | |
600 | dev->class = PCI_CLASS_BRIDGE_PCI << 8; | |
601 | } | |
602 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0, tegra_pcie_fixup_class); | |
603 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1, tegra_pcie_fixup_class); | |
94716cdd JA |
604 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c, tegra_pcie_fixup_class); |
605 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d, tegra_pcie_fixup_class); | |
d1523b52 TR |
606 | |
607 | /* Tegra PCIE requires relaxed ordering */ | |
608 | static void tegra_pcie_relax_enable(struct pci_dev *dev) | |
609 | { | |
610 | pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN); | |
611 | } | |
612 | DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_relax_enable); | |
613 | ||
614 | static int tegra_pcie_setup(int nr, struct pci_sys_data *sys) | |
615 | { | |
616 | struct tegra_pcie *pcie = sys_to_pcie(sys); | |
41534e53 TR |
617 | int err; |
618 | ||
56e75e2a TR |
619 | sys->mem_offset = pcie->offset.mem; |
620 | sys->io_offset = pcie->offset.io; | |
621 | ||
622 | err = devm_request_resource(pcie->dev, &pcie->all, &pcie->io); | |
623 | if (err < 0) | |
624 | return err; | |
625 | ||
626 | err = devm_request_resource(pcie->dev, &ioport_resource, &pcie->pio); | |
627 | if (err < 0) | |
628 | return err; | |
629 | ||
41534e53 TR |
630 | err = devm_request_resource(pcie->dev, &pcie->all, &pcie->mem); |
631 | if (err < 0) | |
632 | return err; | |
633 | ||
634 | err = devm_request_resource(pcie->dev, &pcie->all, &pcie->prefetch); | |
635 | if (err) | |
636 | return err; | |
d1523b52 | 637 | |
56e75e2a | 638 | pci_add_resource_offset(&sys->resources, &pcie->pio, sys->io_offset); |
d1523b52 TR |
639 | pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset); |
640 | pci_add_resource_offset(&sys->resources, &pcie->prefetch, | |
641 | sys->mem_offset); | |
642 | pci_add_resource(&sys->resources, &pcie->busn); | |
643 | ||
5106787a | 644 | pci_ioremap_io(pcie->pio.start, pcie->io.start); |
d1523b52 TR |
645 | |
646 | return 1; | |
647 | } | |
648 | ||
649 | static int tegra_pcie_map_irq(const struct pci_dev *pdev, u8 slot, u8 pin) | |
650 | { | |
651 | struct tegra_pcie *pcie = sys_to_pcie(pdev->bus->sysdata); | |
f5d3352b | 652 | int irq; |
d1523b52 | 653 | |
b4f17375 SW |
654 | tegra_cpuidle_pcie_irqs_in_use(); |
655 | ||
f5d3352b LS |
656 | irq = of_irq_parse_and_map_pci(pdev, slot, pin); |
657 | if (!irq) | |
658 | irq = pcie->irq; | |
659 | ||
660 | return irq; | |
d1523b52 TR |
661 | } |
662 | ||
d1523b52 TR |
663 | static irqreturn_t tegra_pcie_isr(int irq, void *arg) |
664 | { | |
665 | const char *err_msg[] = { | |
666 | "Unknown", | |
667 | "AXI slave error", | |
668 | "AXI decode error", | |
669 | "Target abort", | |
670 | "Master abort", | |
671 | "Invalid write", | |
7f1f054b | 672 | "Legacy interrupt", |
d1523b52 TR |
673 | "Response decoding error", |
674 | "AXI response decoding error", | |
675 | "Transaction timeout", | |
7f1f054b TR |
676 | "Slot present pin change", |
677 | "Slot clock request change", | |
678 | "TMS clock ramp change", | |
679 | "TMS ready for power down", | |
680 | "Peer2Peer error", | |
d1523b52 TR |
681 | }; |
682 | struct tegra_pcie *pcie = arg; | |
683 | u32 code, signature; | |
684 | ||
685 | code = afi_readl(pcie, AFI_INTR_CODE) & AFI_INTR_CODE_MASK; | |
686 | signature = afi_readl(pcie, AFI_INTR_SIGNATURE); | |
687 | afi_writel(pcie, 0, AFI_INTR_CODE); | |
688 | ||
689 | if (code == AFI_INTR_LEGACY) | |
690 | return IRQ_NONE; | |
691 | ||
692 | if (code >= ARRAY_SIZE(err_msg)) | |
693 | code = 0; | |
694 | ||
695 | /* | |
696 | * do not pollute kernel log with master abort reports since they | |
697 | * happen a lot during enumeration | |
698 | */ | |
699 | if (code == AFI_INTR_MASTER_ABORT) | |
700 | dev_dbg(pcie->dev, "%s, signature: %08x\n", err_msg[code], | |
701 | signature); | |
702 | else | |
703 | dev_err(pcie->dev, "%s, signature: %08x\n", err_msg[code], | |
704 | signature); | |
705 | ||
706 | if (code == AFI_INTR_TARGET_ABORT || code == AFI_INTR_MASTER_ABORT || | |
707 | code == AFI_INTR_FPCI_DECODE_ERROR) { | |
708 | u32 fpci = afi_readl(pcie, AFI_UPPER_FPCI_ADDRESS) & 0xff; | |
709 | u64 address = (u64)fpci << 32 | (signature & 0xfffffffc); | |
710 | ||
711 | if (code == AFI_INTR_MASTER_ABORT) | |
712 | dev_dbg(pcie->dev, " FPCI address: %10llx\n", address); | |
713 | else | |
714 | dev_err(pcie->dev, " FPCI address: %10llx\n", address); | |
715 | } | |
716 | ||
717 | return IRQ_HANDLED; | |
718 | } | |
719 | ||
720 | /* | |
721 | * FPCI map is as follows: | |
722 | * - 0xfdfc000000: I/O space | |
723 | * - 0xfdfe000000: type 0 configuration space | |
724 | * - 0xfdff000000: type 1 configuration space | |
725 | * - 0xfe00000000: type 0 extended configuration space | |
726 | * - 0xfe10000000: type 1 extended configuration space | |
727 | */ | |
728 | static void tegra_pcie_setup_translations(struct tegra_pcie *pcie) | |
729 | { | |
730 | u32 fpci_bar, size, axi_address; | |
731 | ||
732 | /* Bar 0: type 1 extended configuration space */ | |
733 | fpci_bar = 0xfe100000; | |
734 | size = resource_size(pcie->cs); | |
735 | axi_address = pcie->cs->start; | |
736 | afi_writel(pcie, axi_address, AFI_AXI_BAR0_START); | |
737 | afi_writel(pcie, size >> 12, AFI_AXI_BAR0_SZ); | |
738 | afi_writel(pcie, fpci_bar, AFI_FPCI_BAR0); | |
739 | ||
740 | /* Bar 1: downstream IO bar */ | |
741 | fpci_bar = 0xfdfc0000; | |
742 | size = resource_size(&pcie->io); | |
5106787a | 743 | axi_address = pcie->io.start; |
d1523b52 TR |
744 | afi_writel(pcie, axi_address, AFI_AXI_BAR1_START); |
745 | afi_writel(pcie, size >> 12, AFI_AXI_BAR1_SZ); | |
746 | afi_writel(pcie, fpci_bar, AFI_FPCI_BAR1); | |
747 | ||
748 | /* Bar 2: prefetchable memory BAR */ | |
749 | fpci_bar = (((pcie->prefetch.start >> 12) & 0x0fffffff) << 4) | 0x1; | |
750 | size = resource_size(&pcie->prefetch); | |
751 | axi_address = pcie->prefetch.start; | |
752 | afi_writel(pcie, axi_address, AFI_AXI_BAR2_START); | |
753 | afi_writel(pcie, size >> 12, AFI_AXI_BAR2_SZ); | |
754 | afi_writel(pcie, fpci_bar, AFI_FPCI_BAR2); | |
755 | ||
756 | /* Bar 3: non prefetchable memory BAR */ | |
757 | fpci_bar = (((pcie->mem.start >> 12) & 0x0fffffff) << 4) | 0x1; | |
758 | size = resource_size(&pcie->mem); | |
759 | axi_address = pcie->mem.start; | |
760 | afi_writel(pcie, axi_address, AFI_AXI_BAR3_START); | |
761 | afi_writel(pcie, size >> 12, AFI_AXI_BAR3_SZ); | |
762 | afi_writel(pcie, fpci_bar, AFI_FPCI_BAR3); | |
763 | ||
764 | /* NULL out the remaining BARs as they are not used */ | |
765 | afi_writel(pcie, 0, AFI_AXI_BAR4_START); | |
766 | afi_writel(pcie, 0, AFI_AXI_BAR4_SZ); | |
767 | afi_writel(pcie, 0, AFI_FPCI_BAR4); | |
768 | ||
769 | afi_writel(pcie, 0, AFI_AXI_BAR5_START); | |
770 | afi_writel(pcie, 0, AFI_AXI_BAR5_SZ); | |
771 | afi_writel(pcie, 0, AFI_FPCI_BAR5); | |
772 | ||
773 | /* map all upstream transactions as uncached */ | |
774 | afi_writel(pcie, PHYS_OFFSET, AFI_CACHE_BAR0_ST); | |
775 | afi_writel(pcie, 0, AFI_CACHE_BAR0_SZ); | |
776 | afi_writel(pcie, 0, AFI_CACHE_BAR1_ST); | |
777 | afi_writel(pcie, 0, AFI_CACHE_BAR1_SZ); | |
778 | ||
779 | /* MSI translations are setup only when needed */ | |
780 | afi_writel(pcie, 0, AFI_MSI_FPCI_BAR_ST); | |
781 | afi_writel(pcie, 0, AFI_MSI_BAR_SZ); | |
782 | afi_writel(pcie, 0, AFI_MSI_AXI_BAR_ST); | |
783 | afi_writel(pcie, 0, AFI_MSI_BAR_SZ); | |
784 | } | |
785 | ||
7f1f054b | 786 | static int tegra_pcie_pll_wait(struct tegra_pcie *pcie, unsigned long timeout) |
d1523b52 | 787 | { |
94716cdd | 788 | const struct tegra_pcie_soc_data *soc = pcie->soc_data; |
7f1f054b | 789 | u32 value; |
d1523b52 | 790 | |
7f1f054b | 791 | timeout = jiffies + msecs_to_jiffies(timeout); |
94716cdd | 792 | |
7f1f054b TR |
793 | while (time_before(jiffies, timeout)) { |
794 | value = pads_readl(pcie, soc->pads_pll_ctl); | |
795 | if (value & PADS_PLL_CTL_LOCKDET) | |
796 | return 0; | |
797 | } | |
d1523b52 | 798 | |
7f1f054b TR |
799 | return -ETIMEDOUT; |
800 | } | |
d1523b52 | 801 | |
7f1f054b TR |
802 | static int tegra_pcie_phy_enable(struct tegra_pcie *pcie) |
803 | { | |
804 | const struct tegra_pcie_soc_data *soc = pcie->soc_data; | |
805 | u32 value; | |
806 | int err; | |
d1523b52 | 807 | |
f7625980 | 808 | /* initialize internal PHY, enable up to 16 PCIE lanes */ |
d1523b52 TR |
809 | pads_writel(pcie, 0x0, PADS_CTL_SEL); |
810 | ||
811 | /* override IDDQ to 1 on all 4 lanes */ | |
812 | value = pads_readl(pcie, PADS_CTL); | |
813 | value |= PADS_CTL_IDDQ_1L; | |
814 | pads_writel(pcie, value, PADS_CTL); | |
815 | ||
816 | /* | |
817 | * Set up PHY PLL inputs select PLLE output as refclock, | |
818 | * set TX ref sel to div10 (not div5). | |
819 | */ | |
94716cdd | 820 | value = pads_readl(pcie, soc->pads_pll_ctl); |
d1523b52 | 821 | value &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK); |
94716cdd JA |
822 | value |= PADS_PLL_CTL_REFCLK_INTERNAL_CML | soc->tx_ref_sel; |
823 | pads_writel(pcie, value, soc->pads_pll_ctl); | |
d1523b52 | 824 | |
ec732762 EY |
825 | /* reset PLL */ |
826 | value = pads_readl(pcie, soc->pads_pll_ctl); | |
827 | value &= ~PADS_PLL_CTL_RST_B4SM; | |
828 | pads_writel(pcie, value, soc->pads_pll_ctl); | |
829 | ||
830 | usleep_range(20, 100); | |
831 | ||
d1523b52 | 832 | /* take PLL out of reset */ |
94716cdd | 833 | value = pads_readl(pcie, soc->pads_pll_ctl); |
d1523b52 | 834 | value |= PADS_PLL_CTL_RST_B4SM; |
94716cdd | 835 | pads_writel(pcie, value, soc->pads_pll_ctl); |
d1523b52 | 836 | |
b02b07ad SW |
837 | /* Configure the reference clock driver */ |
838 | value = PADS_REFCLK_CFG_VALUE | (PADS_REFCLK_CFG_VALUE << 16); | |
839 | pads_writel(pcie, value, PADS_REFCLK_CFG0); | |
840 | if (soc->num_ports > 2) | |
841 | pads_writel(pcie, PADS_REFCLK_CFG_VALUE, PADS_REFCLK_CFG1); | |
d1523b52 TR |
842 | |
843 | /* wait for the PLL to lock */ | |
7f1f054b TR |
844 | err = tegra_pcie_pll_wait(pcie, 500); |
845 | if (err < 0) { | |
846 | dev_err(pcie->dev, "PLL failed to lock: %d\n", err); | |
847 | return err; | |
848 | } | |
d1523b52 TR |
849 | |
850 | /* turn off IDDQ override */ | |
851 | value = pads_readl(pcie, PADS_CTL); | |
852 | value &= ~PADS_CTL_IDDQ_1L; | |
853 | pads_writel(pcie, value, PADS_CTL); | |
854 | ||
855 | /* enable TX/RX data */ | |
856 | value = pads_readl(pcie, PADS_CTL); | |
857 | value |= PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L; | |
858 | pads_writel(pcie, value, PADS_CTL); | |
859 | ||
7f1f054b TR |
860 | return 0; |
861 | } | |
862 | ||
863 | static int tegra_pcie_enable_controller(struct tegra_pcie *pcie) | |
864 | { | |
865 | const struct tegra_pcie_soc_data *soc = pcie->soc_data; | |
866 | struct tegra_pcie_port *port; | |
867 | unsigned long value; | |
868 | int err; | |
869 | ||
870 | /* enable PLL power down */ | |
871 | if (pcie->phy) { | |
872 | value = afi_readl(pcie, AFI_PLLE_CONTROL); | |
873 | value &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL; | |
874 | value |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN; | |
875 | afi_writel(pcie, value, AFI_PLLE_CONTROL); | |
876 | } | |
877 | ||
878 | /* power down PCIe slot clock bias pad */ | |
879 | if (soc->has_pex_bias_ctrl) | |
880 | afi_writel(pcie, 0, AFI_PEXBIAS_CTRL_0); | |
881 | ||
882 | /* configure mode and disable all ports */ | |
883 | value = afi_readl(pcie, AFI_PCIE_CONFIG); | |
884 | value &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK; | |
885 | value |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL | pcie->xbar_config; | |
886 | ||
887 | list_for_each_entry(port, &pcie->ports, list) | |
888 | value &= ~AFI_PCIE_CONFIG_PCIE_DISABLE(port->index); | |
889 | ||
890 | afi_writel(pcie, value, AFI_PCIE_CONFIG); | |
891 | ||
892 | if (soc->has_gen2) { | |
893 | value = afi_readl(pcie, AFI_FUSE); | |
894 | value &= ~AFI_FUSE_PCIE_T0_GEN2_DIS; | |
895 | afi_writel(pcie, value, AFI_FUSE); | |
896 | } else { | |
897 | value = afi_readl(pcie, AFI_FUSE); | |
898 | value |= AFI_FUSE_PCIE_T0_GEN2_DIS; | |
899 | afi_writel(pcie, value, AFI_FUSE); | |
900 | } | |
901 | ||
902 | if (!pcie->phy) | |
903 | err = tegra_pcie_phy_enable(pcie); | |
904 | else | |
905 | err = phy_power_on(pcie->phy); | |
906 | ||
907 | if (err < 0) { | |
908 | dev_err(pcie->dev, "failed to power on PHY: %d\n", err); | |
909 | return err; | |
910 | } | |
911 | ||
d1523b52 | 912 | /* take the PCIe interface module out of reset */ |
3127a6b2 | 913 | reset_control_deassert(pcie->pcie_xrst); |
d1523b52 TR |
914 | |
915 | /* finally enable PCIe */ | |
916 | value = afi_readl(pcie, AFI_CONFIGURATION); | |
917 | value |= AFI_CONFIGURATION_EN_FPCI; | |
918 | afi_writel(pcie, value, AFI_CONFIGURATION); | |
919 | ||
920 | value = AFI_INTR_EN_INI_SLVERR | AFI_INTR_EN_INI_DECERR | | |
921 | AFI_INTR_EN_TGT_SLVERR | AFI_INTR_EN_TGT_DECERR | | |
922 | AFI_INTR_EN_TGT_WRERR | AFI_INTR_EN_DFPCI_DECERR; | |
94716cdd JA |
923 | |
924 | if (soc->has_intr_prsnt_sense) | |
925 | value |= AFI_INTR_EN_PRSNT_SENSE; | |
926 | ||
d1523b52 TR |
927 | afi_writel(pcie, value, AFI_AFI_INTR_ENABLE); |
928 | afi_writel(pcie, 0xffffffff, AFI_SM_INTR_ENABLE); | |
929 | ||
930 | /* don't enable MSI for now, only when needed */ | |
931 | afi_writel(pcie, AFI_INTR_MASK_INT_MASK, AFI_INTR_MASK); | |
932 | ||
933 | /* disable all exceptions */ | |
934 | afi_writel(pcie, 0, AFI_FPCI_ERROR_MASKS); | |
935 | ||
936 | return 0; | |
937 | } | |
938 | ||
939 | static void tegra_pcie_power_off(struct tegra_pcie *pcie) | |
940 | { | |
941 | int err; | |
942 | ||
943 | /* TODO: disable and unprepare clocks? */ | |
944 | ||
7f1f054b TR |
945 | err = phy_power_off(pcie->phy); |
946 | if (err < 0) | |
947 | dev_warn(pcie->dev, "failed to power off PHY: %d\n", err); | |
948 | ||
3127a6b2 SW |
949 | reset_control_assert(pcie->pcie_xrst); |
950 | reset_control_assert(pcie->afi_rst); | |
951 | reset_control_assert(pcie->pex_rst); | |
d1523b52 TR |
952 | |
953 | tegra_powergate_power_off(TEGRA_POWERGATE_PCIE); | |
954 | ||
077fb158 | 955 | err = regulator_bulk_disable(pcie->num_supplies, pcie->supplies); |
d1523b52 | 956 | if (err < 0) |
077fb158 | 957 | dev_warn(pcie->dev, "failed to disable regulators: %d\n", err); |
d1523b52 TR |
958 | } |
959 | ||
960 | static int tegra_pcie_power_on(struct tegra_pcie *pcie) | |
961 | { | |
94716cdd | 962 | const struct tegra_pcie_soc_data *soc = pcie->soc_data; |
d1523b52 TR |
963 | int err; |
964 | ||
3127a6b2 SW |
965 | reset_control_assert(pcie->pcie_xrst); |
966 | reset_control_assert(pcie->afi_rst); | |
967 | reset_control_assert(pcie->pex_rst); | |
d1523b52 TR |
968 | |
969 | tegra_powergate_power_off(TEGRA_POWERGATE_PCIE); | |
970 | ||
971 | /* enable regulators */ | |
077fb158 TR |
972 | err = regulator_bulk_enable(pcie->num_supplies, pcie->supplies); |
973 | if (err < 0) | |
974 | dev_err(pcie->dev, "failed to enable regulators: %d\n", err); | |
94716cdd | 975 | |
d1523b52 | 976 | err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE, |
80b28791 SW |
977 | pcie->pex_clk, |
978 | pcie->pex_rst); | |
d1523b52 TR |
979 | if (err) { |
980 | dev_err(pcie->dev, "powerup sequence failed: %d\n", err); | |
981 | return err; | |
982 | } | |
983 | ||
3127a6b2 | 984 | reset_control_deassert(pcie->afi_rst); |
d1523b52 TR |
985 | |
986 | err = clk_prepare_enable(pcie->afi_clk); | |
987 | if (err < 0) { | |
988 | dev_err(pcie->dev, "failed to enable AFI clock: %d\n", err); | |
989 | return err; | |
990 | } | |
991 | ||
94716cdd JA |
992 | if (soc->has_cml_clk) { |
993 | err = clk_prepare_enable(pcie->cml_clk); | |
994 | if (err < 0) { | |
995 | dev_err(pcie->dev, "failed to enable CML clock: %d\n", | |
996 | err); | |
997 | return err; | |
998 | } | |
999 | } | |
1000 | ||
d1523b52 TR |
1001 | err = clk_prepare_enable(pcie->pll_e); |
1002 | if (err < 0) { | |
1003 | dev_err(pcie->dev, "failed to enable PLLE clock: %d\n", err); | |
1004 | return err; | |
1005 | } | |
1006 | ||
1007 | return 0; | |
1008 | } | |
1009 | ||
1010 | static int tegra_pcie_clocks_get(struct tegra_pcie *pcie) | |
1011 | { | |
94716cdd JA |
1012 | const struct tegra_pcie_soc_data *soc = pcie->soc_data; |
1013 | ||
d1523b52 TR |
1014 | pcie->pex_clk = devm_clk_get(pcie->dev, "pex"); |
1015 | if (IS_ERR(pcie->pex_clk)) | |
1016 | return PTR_ERR(pcie->pex_clk); | |
1017 | ||
1018 | pcie->afi_clk = devm_clk_get(pcie->dev, "afi"); | |
1019 | if (IS_ERR(pcie->afi_clk)) | |
1020 | return PTR_ERR(pcie->afi_clk); | |
1021 | ||
d1523b52 TR |
1022 | pcie->pll_e = devm_clk_get(pcie->dev, "pll_e"); |
1023 | if (IS_ERR(pcie->pll_e)) | |
1024 | return PTR_ERR(pcie->pll_e); | |
1025 | ||
94716cdd JA |
1026 | if (soc->has_cml_clk) { |
1027 | pcie->cml_clk = devm_clk_get(pcie->dev, "cml"); | |
1028 | if (IS_ERR(pcie->cml_clk)) | |
1029 | return PTR_ERR(pcie->cml_clk); | |
1030 | } | |
1031 | ||
d1523b52 TR |
1032 | return 0; |
1033 | } | |
1034 | ||
3127a6b2 SW |
1035 | static int tegra_pcie_resets_get(struct tegra_pcie *pcie) |
1036 | { | |
1037 | pcie->pex_rst = devm_reset_control_get(pcie->dev, "pex"); | |
1038 | if (IS_ERR(pcie->pex_rst)) | |
1039 | return PTR_ERR(pcie->pex_rst); | |
1040 | ||
1041 | pcie->afi_rst = devm_reset_control_get(pcie->dev, "afi"); | |
1042 | if (IS_ERR(pcie->afi_rst)) | |
1043 | return PTR_ERR(pcie->afi_rst); | |
1044 | ||
1045 | pcie->pcie_xrst = devm_reset_control_get(pcie->dev, "pcie_x"); | |
1046 | if (IS_ERR(pcie->pcie_xrst)) | |
1047 | return PTR_ERR(pcie->pcie_xrst); | |
1048 | ||
1049 | return 0; | |
1050 | } | |
1051 | ||
d1523b52 TR |
1052 | static int tegra_pcie_get_resources(struct tegra_pcie *pcie) |
1053 | { | |
1054 | struct platform_device *pdev = to_platform_device(pcie->dev); | |
1055 | struct resource *pads, *afi, *res; | |
1056 | int err; | |
1057 | ||
1058 | err = tegra_pcie_clocks_get(pcie); | |
1059 | if (err) { | |
1060 | dev_err(&pdev->dev, "failed to get clocks: %d\n", err); | |
1061 | return err; | |
1062 | } | |
1063 | ||
3127a6b2 SW |
1064 | err = tegra_pcie_resets_get(pcie); |
1065 | if (err) { | |
1066 | dev_err(&pdev->dev, "failed to get resets: %d\n", err); | |
1067 | return err; | |
1068 | } | |
1069 | ||
7f1f054b TR |
1070 | pcie->phy = devm_phy_optional_get(pcie->dev, "pcie"); |
1071 | if (IS_ERR(pcie->phy)) { | |
1072 | err = PTR_ERR(pcie->phy); | |
1073 | dev_err(&pdev->dev, "failed to get PHY: %d\n", err); | |
1074 | return err; | |
1075 | } | |
1076 | ||
1077 | err = phy_init(pcie->phy); | |
1078 | if (err < 0) { | |
1079 | dev_err(&pdev->dev, "failed to initialize PHY: %d\n", err); | |
1080 | return err; | |
1081 | } | |
1082 | ||
d1523b52 TR |
1083 | err = tegra_pcie_power_on(pcie); |
1084 | if (err) { | |
1085 | dev_err(&pdev->dev, "failed to power up: %d\n", err); | |
1086 | return err; | |
1087 | } | |
1088 | ||
d1523b52 | 1089 | pads = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pads"); |
dc05ee32 JL |
1090 | pcie->pads = devm_ioremap_resource(&pdev->dev, pads); |
1091 | if (IS_ERR(pcie->pads)) { | |
1092 | err = PTR_ERR(pcie->pads); | |
d1523b52 TR |
1093 | goto poweroff; |
1094 | } | |
1095 | ||
1096 | afi = platform_get_resource_byname(pdev, IORESOURCE_MEM, "afi"); | |
dc05ee32 JL |
1097 | pcie->afi = devm_ioremap_resource(&pdev->dev, afi); |
1098 | if (IS_ERR(pcie->afi)) { | |
1099 | err = PTR_ERR(pcie->afi); | |
d1523b52 TR |
1100 | goto poweroff; |
1101 | } | |
1102 | ||
dc05ee32 | 1103 | /* request configuration space, but remap later, on demand */ |
d1523b52 TR |
1104 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cs"); |
1105 | if (!res) { | |
1106 | err = -EADDRNOTAVAIL; | |
1107 | goto poweroff; | |
1108 | } | |
1109 | ||
1110 | pcie->cs = devm_request_mem_region(pcie->dev, res->start, | |
1111 | resource_size(res), res->name); | |
1112 | if (!pcie->cs) { | |
1113 | err = -EADDRNOTAVAIL; | |
1114 | goto poweroff; | |
1115 | } | |
1116 | ||
1117 | /* request interrupt */ | |
1118 | err = platform_get_irq_byname(pdev, "intr"); | |
1119 | if (err < 0) { | |
1120 | dev_err(&pdev->dev, "failed to get IRQ: %d\n", err); | |
1121 | goto poweroff; | |
1122 | } | |
1123 | ||
1124 | pcie->irq = err; | |
1125 | ||
1126 | err = request_irq(pcie->irq, tegra_pcie_isr, IRQF_SHARED, "PCIE", pcie); | |
1127 | if (err) { | |
1128 | dev_err(&pdev->dev, "failed to register IRQ: %d\n", err); | |
1129 | goto poweroff; | |
1130 | } | |
1131 | ||
1132 | return 0; | |
1133 | ||
1134 | poweroff: | |
1135 | tegra_pcie_power_off(pcie); | |
1136 | return err; | |
1137 | } | |
1138 | ||
1139 | static int tegra_pcie_put_resources(struct tegra_pcie *pcie) | |
1140 | { | |
7f1f054b TR |
1141 | int err; |
1142 | ||
d1523b52 TR |
1143 | if (pcie->irq > 0) |
1144 | free_irq(pcie->irq, pcie); | |
1145 | ||
1146 | tegra_pcie_power_off(pcie); | |
7f1f054b TR |
1147 | |
1148 | err = phy_exit(pcie->phy); | |
1149 | if (err < 0) | |
1150 | dev_err(pcie->dev, "failed to teardown PHY: %d\n", err); | |
1151 | ||
d1523b52 TR |
1152 | return 0; |
1153 | } | |
1154 | ||
1155 | static int tegra_msi_alloc(struct tegra_msi *chip) | |
1156 | { | |
1157 | int msi; | |
1158 | ||
1159 | mutex_lock(&chip->lock); | |
1160 | ||
1161 | msi = find_first_zero_bit(chip->used, INT_PCI_MSI_NR); | |
1162 | if (msi < INT_PCI_MSI_NR) | |
1163 | set_bit(msi, chip->used); | |
1164 | else | |
1165 | msi = -ENOSPC; | |
1166 | ||
1167 | mutex_unlock(&chip->lock); | |
1168 | ||
1169 | return msi; | |
1170 | } | |
1171 | ||
1172 | static void tegra_msi_free(struct tegra_msi *chip, unsigned long irq) | |
1173 | { | |
1174 | struct device *dev = chip->chip.dev; | |
1175 | ||
1176 | mutex_lock(&chip->lock); | |
1177 | ||
1178 | if (!test_bit(irq, chip->used)) | |
1179 | dev_err(dev, "trying to free unused MSI#%lu\n", irq); | |
1180 | else | |
1181 | clear_bit(irq, chip->used); | |
1182 | ||
1183 | mutex_unlock(&chip->lock); | |
1184 | } | |
1185 | ||
1186 | static irqreturn_t tegra_pcie_msi_irq(int irq, void *data) | |
1187 | { | |
1188 | struct tegra_pcie *pcie = data; | |
1189 | struct tegra_msi *msi = &pcie->msi; | |
1190 | unsigned int i, processed = 0; | |
1191 | ||
1192 | for (i = 0; i < 8; i++) { | |
1193 | unsigned long reg = afi_readl(pcie, AFI_MSI_VEC0 + i * 4); | |
1194 | ||
1195 | while (reg) { | |
1196 | unsigned int offset = find_first_bit(®, 32); | |
1197 | unsigned int index = i * 32 + offset; | |
1198 | unsigned int irq; | |
1199 | ||
1200 | /* clear the interrupt */ | |
1201 | afi_writel(pcie, 1 << offset, AFI_MSI_VEC0 + i * 4); | |
1202 | ||
1203 | irq = irq_find_mapping(msi->domain, index); | |
1204 | if (irq) { | |
1205 | if (test_bit(index, msi->used)) | |
1206 | generic_handle_irq(irq); | |
1207 | else | |
1208 | dev_info(pcie->dev, "unhandled MSI\n"); | |
1209 | } else { | |
1210 | /* | |
1211 | * that's weird who triggered this? | |
1212 | * just clear it | |
1213 | */ | |
1214 | dev_info(pcie->dev, "unexpected MSI\n"); | |
1215 | } | |
1216 | ||
1217 | /* see if there's any more pending in this vector */ | |
1218 | reg = afi_readl(pcie, AFI_MSI_VEC0 + i * 4); | |
1219 | ||
1220 | processed++; | |
1221 | } | |
1222 | } | |
1223 | ||
1224 | return processed > 0 ? IRQ_HANDLED : IRQ_NONE; | |
1225 | } | |
1226 | ||
c2791b80 YW |
1227 | static int tegra_msi_setup_irq(struct msi_controller *chip, |
1228 | struct pci_dev *pdev, struct msi_desc *desc) | |
d1523b52 TR |
1229 | { |
1230 | struct tegra_msi *msi = to_tegra_msi(chip); | |
1231 | struct msi_msg msg; | |
1232 | unsigned int irq; | |
1233 | int hwirq; | |
1234 | ||
1235 | hwirq = tegra_msi_alloc(msi); | |
1236 | if (hwirq < 0) | |
1237 | return hwirq; | |
1238 | ||
1239 | irq = irq_create_mapping(msi->domain, hwirq); | |
019fa46e JZ |
1240 | if (!irq) { |
1241 | tegra_msi_free(msi, hwirq); | |
d1523b52 | 1242 | return -EINVAL; |
019fa46e | 1243 | } |
d1523b52 TR |
1244 | |
1245 | irq_set_msi_desc(irq, desc); | |
1246 | ||
1247 | msg.address_lo = virt_to_phys((void *)msi->pages); | |
1248 | /* 32 bit address only */ | |
1249 | msg.address_hi = 0; | |
1250 | msg.data = hwirq; | |
1251 | ||
83a18912 | 1252 | pci_write_msi_msg(irq, &msg); |
d1523b52 TR |
1253 | |
1254 | return 0; | |
1255 | } | |
1256 | ||
c2791b80 YW |
1257 | static void tegra_msi_teardown_irq(struct msi_controller *chip, |
1258 | unsigned int irq) | |
d1523b52 TR |
1259 | { |
1260 | struct tegra_msi *msi = to_tegra_msi(chip); | |
1261 | struct irq_data *d = irq_get_irq_data(irq); | |
019fa46e | 1262 | irq_hw_number_t hwirq = irqd_to_hwirq(d); |
d1523b52 | 1263 | |
019fa46e JZ |
1264 | irq_dispose_mapping(irq); |
1265 | tegra_msi_free(msi, hwirq); | |
d1523b52 TR |
1266 | } |
1267 | ||
1268 | static struct irq_chip tegra_msi_irq_chip = { | |
1269 | .name = "Tegra PCIe MSI", | |
280510f1 TG |
1270 | .irq_enable = pci_msi_unmask_irq, |
1271 | .irq_disable = pci_msi_mask_irq, | |
1272 | .irq_mask = pci_msi_mask_irq, | |
1273 | .irq_unmask = pci_msi_unmask_irq, | |
d1523b52 TR |
1274 | }; |
1275 | ||
1276 | static int tegra_msi_map(struct irq_domain *domain, unsigned int irq, | |
1277 | irq_hw_number_t hwirq) | |
1278 | { | |
1279 | irq_set_chip_and_handler(irq, &tegra_msi_irq_chip, handle_simple_irq); | |
1280 | irq_set_chip_data(irq, domain->host_data); | |
d1523b52 | 1281 | |
b4f17375 SW |
1282 | tegra_cpuidle_pcie_irqs_in_use(); |
1283 | ||
d1523b52 TR |
1284 | return 0; |
1285 | } | |
1286 | ||
1287 | static const struct irq_domain_ops msi_domain_ops = { | |
1288 | .map = tegra_msi_map, | |
1289 | }; | |
1290 | ||
1291 | static int tegra_pcie_enable_msi(struct tegra_pcie *pcie) | |
1292 | { | |
1293 | struct platform_device *pdev = to_platform_device(pcie->dev); | |
94716cdd | 1294 | const struct tegra_pcie_soc_data *soc = pcie->soc_data; |
d1523b52 TR |
1295 | struct tegra_msi *msi = &pcie->msi; |
1296 | unsigned long base; | |
1297 | int err; | |
1298 | u32 reg; | |
1299 | ||
1300 | mutex_init(&msi->lock); | |
1301 | ||
1302 | msi->chip.dev = pcie->dev; | |
1303 | msi->chip.setup_irq = tegra_msi_setup_irq; | |
1304 | msi->chip.teardown_irq = tegra_msi_teardown_irq; | |
1305 | ||
1306 | msi->domain = irq_domain_add_linear(pcie->dev->of_node, INT_PCI_MSI_NR, | |
1307 | &msi_domain_ops, &msi->chip); | |
1308 | if (!msi->domain) { | |
1309 | dev_err(&pdev->dev, "failed to create IRQ domain\n"); | |
1310 | return -ENOMEM; | |
1311 | } | |
1312 | ||
1313 | err = platform_get_irq_byname(pdev, "msi"); | |
1314 | if (err < 0) { | |
1315 | dev_err(&pdev->dev, "failed to get IRQ: %d\n", err); | |
1316 | goto err; | |
1317 | } | |
1318 | ||
1319 | msi->irq = err; | |
1320 | ||
8ff0ef99 | 1321 | err = request_irq(msi->irq, tegra_pcie_msi_irq, IRQF_NO_THREAD, |
d1523b52 TR |
1322 | tegra_msi_irq_chip.name, pcie); |
1323 | if (err < 0) { | |
1324 | dev_err(&pdev->dev, "failed to request IRQ: %d\n", err); | |
1325 | goto err; | |
1326 | } | |
1327 | ||
1328 | /* setup AFI/FPCI range */ | |
1329 | msi->pages = __get_free_pages(GFP_KERNEL, 0); | |
1330 | base = virt_to_phys((void *)msi->pages); | |
1331 | ||
94716cdd | 1332 | afi_writel(pcie, base >> soc->msi_base_shift, AFI_MSI_FPCI_BAR_ST); |
d1523b52 TR |
1333 | afi_writel(pcie, base, AFI_MSI_AXI_BAR_ST); |
1334 | /* this register is in 4K increments */ | |
1335 | afi_writel(pcie, 1, AFI_MSI_BAR_SZ); | |
1336 | ||
1337 | /* enable all MSI vectors */ | |
1338 | afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC0); | |
1339 | afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC1); | |
1340 | afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC2); | |
1341 | afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC3); | |
1342 | afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC4); | |
1343 | afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC5); | |
1344 | afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC6); | |
1345 | afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC7); | |
1346 | ||
1347 | /* and unmask the MSI interrupt */ | |
1348 | reg = afi_readl(pcie, AFI_INTR_MASK); | |
1349 | reg |= AFI_INTR_MASK_MSI_MASK; | |
1350 | afi_writel(pcie, reg, AFI_INTR_MASK); | |
1351 | ||
1352 | return 0; | |
1353 | ||
1354 | err: | |
1355 | irq_domain_remove(msi->domain); | |
1356 | return err; | |
1357 | } | |
1358 | ||
1359 | static int tegra_pcie_disable_msi(struct tegra_pcie *pcie) | |
1360 | { | |
1361 | struct tegra_msi *msi = &pcie->msi; | |
1362 | unsigned int i, irq; | |
1363 | u32 value; | |
1364 | ||
1365 | /* mask the MSI interrupt */ | |
1366 | value = afi_readl(pcie, AFI_INTR_MASK); | |
1367 | value &= ~AFI_INTR_MASK_MSI_MASK; | |
1368 | afi_writel(pcie, value, AFI_INTR_MASK); | |
1369 | ||
1370 | /* disable all MSI vectors */ | |
1371 | afi_writel(pcie, 0, AFI_MSI_EN_VEC0); | |
1372 | afi_writel(pcie, 0, AFI_MSI_EN_VEC1); | |
1373 | afi_writel(pcie, 0, AFI_MSI_EN_VEC2); | |
1374 | afi_writel(pcie, 0, AFI_MSI_EN_VEC3); | |
1375 | afi_writel(pcie, 0, AFI_MSI_EN_VEC4); | |
1376 | afi_writel(pcie, 0, AFI_MSI_EN_VEC5); | |
1377 | afi_writel(pcie, 0, AFI_MSI_EN_VEC6); | |
1378 | afi_writel(pcie, 0, AFI_MSI_EN_VEC7); | |
1379 | ||
1380 | free_pages(msi->pages, 0); | |
1381 | ||
1382 | if (msi->irq > 0) | |
1383 | free_irq(msi->irq, pcie); | |
1384 | ||
1385 | for (i = 0; i < INT_PCI_MSI_NR; i++) { | |
1386 | irq = irq_find_mapping(msi->domain, i); | |
1387 | if (irq > 0) | |
1388 | irq_dispose_mapping(irq); | |
1389 | } | |
1390 | ||
1391 | irq_domain_remove(msi->domain); | |
1392 | ||
1393 | return 0; | |
1394 | } | |
1395 | ||
1396 | static int tegra_pcie_get_xbar_config(struct tegra_pcie *pcie, u32 lanes, | |
1397 | u32 *xbar) | |
1398 | { | |
1399 | struct device_node *np = pcie->dev->of_node; | |
1400 | ||
7f1f054b TR |
1401 | if (of_device_is_compatible(np, "nvidia,tegra124-pcie")) { |
1402 | switch (lanes) { | |
1403 | case 0x0000104: | |
1404 | dev_info(pcie->dev, "4x1, 1x1 configuration\n"); | |
1405 | *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1; | |
1406 | return 0; | |
1407 | ||
1408 | case 0x0000102: | |
1409 | dev_info(pcie->dev, "2x1, 1x1 configuration\n"); | |
1410 | *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1; | |
1411 | return 0; | |
1412 | } | |
1413 | } else if (of_device_is_compatible(np, "nvidia,tegra30-pcie")) { | |
94716cdd JA |
1414 | switch (lanes) { |
1415 | case 0x00000204: | |
1416 | dev_info(pcie->dev, "4x1, 2x1 configuration\n"); | |
1417 | *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420; | |
1418 | return 0; | |
1419 | ||
1420 | case 0x00020202: | |
1421 | dev_info(pcie->dev, "2x3 configuration\n"); | |
1422 | *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222; | |
1423 | return 0; | |
1424 | ||
1425 | case 0x00010104: | |
1426 | dev_info(pcie->dev, "4x1, 1x2 configuration\n"); | |
1427 | *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411; | |
1428 | return 0; | |
1429 | } | |
1430 | } else if (of_device_is_compatible(np, "nvidia,tegra20-pcie")) { | |
1431 | switch (lanes) { | |
1432 | case 0x00000004: | |
1433 | dev_info(pcie->dev, "single-mode configuration\n"); | |
1434 | *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE; | |
1435 | return 0; | |
1436 | ||
1437 | case 0x00000202: | |
1438 | dev_info(pcie->dev, "dual-mode configuration\n"); | |
1439 | *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL; | |
1440 | return 0; | |
1441 | } | |
d1523b52 TR |
1442 | } |
1443 | ||
1444 | return -EINVAL; | |
1445 | } | |
1446 | ||
077fb158 TR |
1447 | /* |
1448 | * Check whether a given set of supplies is available in a device tree node. | |
1449 | * This is used to check whether the new or the legacy device tree bindings | |
1450 | * should be used. | |
1451 | */ | |
1452 | static bool of_regulator_bulk_available(struct device_node *np, | |
1453 | struct regulator_bulk_data *supplies, | |
1454 | unsigned int num_supplies) | |
1455 | { | |
1456 | char property[32]; | |
1457 | unsigned int i; | |
1458 | ||
1459 | for (i = 0; i < num_supplies; i++) { | |
1460 | snprintf(property, 32, "%s-supply", supplies[i].supply); | |
1461 | ||
1462 | if (of_find_property(np, property, NULL) == NULL) | |
1463 | return false; | |
1464 | } | |
1465 | ||
1466 | return true; | |
1467 | } | |
1468 | ||
1469 | /* | |
1470 | * Old versions of the device tree binding for this device used a set of power | |
1471 | * supplies that didn't match the hardware inputs. This happened to work for a | |
1472 | * number of cases but is not future proof. However to preserve backwards- | |
1473 | * compatibility with old device trees, this function will try to use the old | |
1474 | * set of supplies. | |
1475 | */ | |
1476 | static int tegra_pcie_get_legacy_regulators(struct tegra_pcie *pcie) | |
1477 | { | |
1478 | struct device_node *np = pcie->dev->of_node; | |
1479 | ||
1480 | if (of_device_is_compatible(np, "nvidia,tegra30-pcie")) | |
1481 | pcie->num_supplies = 3; | |
1482 | else if (of_device_is_compatible(np, "nvidia,tegra20-pcie")) | |
1483 | pcie->num_supplies = 2; | |
1484 | ||
1485 | if (pcie->num_supplies == 0) { | |
1486 | dev_err(pcie->dev, "device %s not supported in legacy mode\n", | |
1487 | np->full_name); | |
1488 | return -ENODEV; | |
1489 | } | |
1490 | ||
1491 | pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies, | |
1492 | sizeof(*pcie->supplies), | |
1493 | GFP_KERNEL); | |
1494 | if (!pcie->supplies) | |
1495 | return -ENOMEM; | |
1496 | ||
1497 | pcie->supplies[0].supply = "pex-clk"; | |
1498 | pcie->supplies[1].supply = "vdd"; | |
1499 | ||
1500 | if (pcie->num_supplies > 2) | |
1501 | pcie->supplies[2].supply = "avdd"; | |
1502 | ||
1503 | return devm_regulator_bulk_get(pcie->dev, pcie->num_supplies, | |
1504 | pcie->supplies); | |
1505 | } | |
1506 | ||
1507 | /* | |
1508 | * Obtains the list of regulators required for a particular generation of the | |
1509 | * IP block. | |
1510 | * | |
1511 | * This would've been nice to do simply by providing static tables for use | |
1512 | * with the regulator_bulk_*() API, but unfortunately Tegra30 is a bit quirky | |
1513 | * in that it has two pairs or AVDD_PEX and VDD_PEX supplies (PEXA and PEXB) | |
1514 | * and either seems to be optional depending on which ports are being used. | |
1515 | */ | |
1516 | static int tegra_pcie_get_regulators(struct tegra_pcie *pcie, u32 lane_mask) | |
1517 | { | |
1518 | struct device_node *np = pcie->dev->of_node; | |
1519 | unsigned int i = 0; | |
1520 | ||
7f1f054b TR |
1521 | if (of_device_is_compatible(np, "nvidia,tegra124-pcie")) { |
1522 | pcie->num_supplies = 7; | |
1523 | ||
1524 | pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies, | |
1525 | sizeof(*pcie->supplies), | |
1526 | GFP_KERNEL); | |
1527 | if (!pcie->supplies) | |
1528 | return -ENOMEM; | |
1529 | ||
1530 | pcie->supplies[i++].supply = "avddio-pex"; | |
1531 | pcie->supplies[i++].supply = "dvddio-pex"; | |
1532 | pcie->supplies[i++].supply = "avdd-pex-pll"; | |
1533 | pcie->supplies[i++].supply = "hvdd-pex"; | |
1534 | pcie->supplies[i++].supply = "hvdd-pex-pll-e"; | |
1535 | pcie->supplies[i++].supply = "vddio-pex-ctl"; | |
1536 | pcie->supplies[i++].supply = "avdd-pll-erefe"; | |
1537 | } else if (of_device_is_compatible(np, "nvidia,tegra30-pcie")) { | |
077fb158 TR |
1538 | bool need_pexa = false, need_pexb = false; |
1539 | ||
1540 | /* VDD_PEXA and AVDD_PEXA supply lanes 0 to 3 */ | |
1541 | if (lane_mask & 0x0f) | |
1542 | need_pexa = true; | |
1543 | ||
1544 | /* VDD_PEXB and AVDD_PEXB supply lanes 4 to 5 */ | |
1545 | if (lane_mask & 0x30) | |
1546 | need_pexb = true; | |
1547 | ||
1548 | pcie->num_supplies = 4 + (need_pexa ? 2 : 0) + | |
1549 | (need_pexb ? 2 : 0); | |
1550 | ||
1551 | pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies, | |
1552 | sizeof(*pcie->supplies), | |
1553 | GFP_KERNEL); | |
1554 | if (!pcie->supplies) | |
1555 | return -ENOMEM; | |
1556 | ||
1557 | pcie->supplies[i++].supply = "avdd-pex-pll"; | |
1558 | pcie->supplies[i++].supply = "hvdd-pex"; | |
1559 | pcie->supplies[i++].supply = "vddio-pex-ctl"; | |
1560 | pcie->supplies[i++].supply = "avdd-plle"; | |
1561 | ||
1562 | if (need_pexa) { | |
1563 | pcie->supplies[i++].supply = "avdd-pexa"; | |
1564 | pcie->supplies[i++].supply = "vdd-pexa"; | |
1565 | } | |
1566 | ||
1567 | if (need_pexb) { | |
1568 | pcie->supplies[i++].supply = "avdd-pexb"; | |
1569 | pcie->supplies[i++].supply = "vdd-pexb"; | |
1570 | } | |
1571 | } else if (of_device_is_compatible(np, "nvidia,tegra20-pcie")) { | |
1572 | pcie->num_supplies = 5; | |
1573 | ||
1574 | pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies, | |
1575 | sizeof(*pcie->supplies), | |
1576 | GFP_KERNEL); | |
1577 | if (!pcie->supplies) | |
1578 | return -ENOMEM; | |
1579 | ||
1580 | pcie->supplies[0].supply = "avdd-pex"; | |
1581 | pcie->supplies[1].supply = "vdd-pex"; | |
1582 | pcie->supplies[2].supply = "avdd-pex-pll"; | |
1583 | pcie->supplies[3].supply = "avdd-plle"; | |
1584 | pcie->supplies[4].supply = "vddio-pex-clk"; | |
1585 | } | |
1586 | ||
1587 | if (of_regulator_bulk_available(pcie->dev->of_node, pcie->supplies, | |
1588 | pcie->num_supplies)) | |
1589 | return devm_regulator_bulk_get(pcie->dev, pcie->num_supplies, | |
1590 | pcie->supplies); | |
1591 | ||
1592 | /* | |
1593 | * If not all regulators are available for this new scheme, assume | |
1594 | * that the device tree complies with an older version of the device | |
1595 | * tree binding. | |
1596 | */ | |
1597 | dev_info(pcie->dev, "using legacy DT binding for power supplies\n"); | |
1598 | ||
1599 | devm_kfree(pcie->dev, pcie->supplies); | |
1600 | pcie->num_supplies = 0; | |
1601 | ||
1602 | return tegra_pcie_get_legacy_regulators(pcie); | |
1603 | } | |
1604 | ||
d1523b52 TR |
1605 | static int tegra_pcie_parse_dt(struct tegra_pcie *pcie) |
1606 | { | |
94716cdd | 1607 | const struct tegra_pcie_soc_data *soc = pcie->soc_data; |
d1523b52 TR |
1608 | struct device_node *np = pcie->dev->of_node, *port; |
1609 | struct of_pci_range_parser parser; | |
1610 | struct of_pci_range range; | |
077fb158 TR |
1611 | u32 lanes = 0, mask = 0; |
1612 | unsigned int lane = 0; | |
d1523b52 | 1613 | struct resource res; |
d1523b52 TR |
1614 | int err; |
1615 | ||
41534e53 TR |
1616 | memset(&pcie->all, 0, sizeof(pcie->all)); |
1617 | pcie->all.flags = IORESOURCE_MEM; | |
1618 | pcie->all.name = np->full_name; | |
1619 | pcie->all.start = ~0; | |
1620 | pcie->all.end = 0; | |
1621 | ||
d1523b52 TR |
1622 | if (of_pci_range_parser_init(&parser, np)) { |
1623 | dev_err(pcie->dev, "missing \"ranges\" property\n"); | |
1624 | return -EINVAL; | |
1625 | } | |
1626 | ||
d1523b52 | 1627 | for_each_of_pci_range(&parser, &range) { |
0b0b0893 LD |
1628 | err = of_pci_range_to_resource(&range, np, &res); |
1629 | if (err < 0) | |
1630 | return err; | |
d1523b52 TR |
1631 | |
1632 | switch (res.flags & IORESOURCE_TYPE_BITS) { | |
1633 | case IORESOURCE_IO: | |
56e75e2a TR |
1634 | /* Track the bus -> CPU I/O mapping offset. */ |
1635 | pcie->offset.io = res.start - range.pci_addr; | |
1636 | ||
5106787a TR |
1637 | memcpy(&pcie->pio, &res, sizeof(res)); |
1638 | pcie->pio.name = np->full_name; | |
1639 | ||
1640 | /* | |
1641 | * The Tegra PCIe host bridge uses this to program the | |
1642 | * mapping of the I/O space to the physical address, | |
1643 | * so we override the .start and .end fields here that | |
1644 | * of_pci_range_to_resource() converted to I/O space. | |
1645 | * We also set the IORESOURCE_MEM type to clarify that | |
1646 | * the resource is in the physical memory space. | |
1647 | */ | |
1648 | pcie->io.start = range.cpu_addr; | |
1649 | pcie->io.end = range.cpu_addr + range.size - 1; | |
1650 | pcie->io.flags = IORESOURCE_MEM; | |
1651 | pcie->io.name = "I/O"; | |
1652 | ||
1653 | memcpy(&res, &pcie->io, sizeof(res)); | |
d1523b52 TR |
1654 | break; |
1655 | ||
1656 | case IORESOURCE_MEM: | |
56e75e2a TR |
1657 | /* |
1658 | * Track the bus -> CPU memory mapping offset. This | |
1659 | * assumes that the prefetchable and non-prefetchable | |
1660 | * regions will be the last of type IORESOURCE_MEM in | |
1661 | * the ranges property. | |
1662 | * */ | |
1663 | pcie->offset.mem = res.start - range.pci_addr; | |
1664 | ||
d1523b52 TR |
1665 | if (res.flags & IORESOURCE_PREFETCH) { |
1666 | memcpy(&pcie->prefetch, &res, sizeof(res)); | |
41534e53 | 1667 | pcie->prefetch.name = "prefetchable"; |
d1523b52 TR |
1668 | } else { |
1669 | memcpy(&pcie->mem, &res, sizeof(res)); | |
41534e53 | 1670 | pcie->mem.name = "non-prefetchable"; |
d1523b52 TR |
1671 | } |
1672 | break; | |
1673 | } | |
41534e53 TR |
1674 | |
1675 | if (res.start <= pcie->all.start) | |
1676 | pcie->all.start = res.start; | |
1677 | ||
1678 | if (res.end >= pcie->all.end) | |
1679 | pcie->all.end = res.end; | |
d1523b52 TR |
1680 | } |
1681 | ||
41534e53 TR |
1682 | err = devm_request_resource(pcie->dev, &iomem_resource, &pcie->all); |
1683 | if (err < 0) | |
1684 | return err; | |
1685 | ||
d1523b52 TR |
1686 | err = of_pci_parse_bus_range(np, &pcie->busn); |
1687 | if (err < 0) { | |
1688 | dev_err(pcie->dev, "failed to parse ranges property: %d\n", | |
1689 | err); | |
1690 | pcie->busn.name = np->name; | |
1691 | pcie->busn.start = 0; | |
1692 | pcie->busn.end = 0xff; | |
1693 | pcie->busn.flags = IORESOURCE_BUS; | |
1694 | } | |
1695 | ||
1696 | /* parse root ports */ | |
1697 | for_each_child_of_node(np, port) { | |
1698 | struct tegra_pcie_port *rp; | |
1699 | unsigned int index; | |
1700 | u32 value; | |
1701 | ||
1702 | err = of_pci_get_devfn(port); | |
1703 | if (err < 0) { | |
1704 | dev_err(pcie->dev, "failed to parse address: %d\n", | |
1705 | err); | |
1706 | return err; | |
1707 | } | |
1708 | ||
1709 | index = PCI_SLOT(err); | |
1710 | ||
94716cdd | 1711 | if (index < 1 || index > soc->num_ports) { |
d1523b52 TR |
1712 | dev_err(pcie->dev, "invalid port number: %d\n", index); |
1713 | return -EINVAL; | |
1714 | } | |
1715 | ||
1716 | index--; | |
1717 | ||
1718 | err = of_property_read_u32(port, "nvidia,num-lanes", &value); | |
1719 | if (err < 0) { | |
1720 | dev_err(pcie->dev, "failed to parse # of lanes: %d\n", | |
1721 | err); | |
1722 | return err; | |
1723 | } | |
1724 | ||
1725 | if (value > 16) { | |
1726 | dev_err(pcie->dev, "invalid # of lanes: %u\n", value); | |
1727 | return -EINVAL; | |
1728 | } | |
1729 | ||
1730 | lanes |= value << (index << 3); | |
1731 | ||
077fb158 TR |
1732 | if (!of_device_is_available(port)) { |
1733 | lane += value; | |
d1523b52 | 1734 | continue; |
077fb158 TR |
1735 | } |
1736 | ||
1737 | mask |= ((1 << value) - 1) << lane; | |
1738 | lane += value; | |
d1523b52 TR |
1739 | |
1740 | rp = devm_kzalloc(pcie->dev, sizeof(*rp), GFP_KERNEL); | |
1741 | if (!rp) | |
1742 | return -ENOMEM; | |
1743 | ||
1744 | err = of_address_to_resource(port, 0, &rp->regs); | |
1745 | if (err < 0) { | |
1746 | dev_err(pcie->dev, "failed to parse address: %d\n", | |
1747 | err); | |
1748 | return err; | |
1749 | } | |
1750 | ||
1751 | INIT_LIST_HEAD(&rp->list); | |
1752 | rp->index = index; | |
1753 | rp->lanes = value; | |
1754 | rp->pcie = pcie; | |
1755 | ||
dc05ee32 JL |
1756 | rp->base = devm_ioremap_resource(pcie->dev, &rp->regs); |
1757 | if (IS_ERR(rp->base)) | |
1758 | return PTR_ERR(rp->base); | |
d1523b52 TR |
1759 | |
1760 | list_add_tail(&rp->list, &pcie->ports); | |
1761 | } | |
1762 | ||
1763 | err = tegra_pcie_get_xbar_config(pcie, lanes, &pcie->xbar_config); | |
1764 | if (err < 0) { | |
1765 | dev_err(pcie->dev, "invalid lane configuration\n"); | |
1766 | return err; | |
1767 | } | |
1768 | ||
077fb158 TR |
1769 | err = tegra_pcie_get_regulators(pcie, mask); |
1770 | if (err < 0) | |
1771 | return err; | |
1772 | ||
d1523b52 TR |
1773 | return 0; |
1774 | } | |
1775 | ||
1776 | /* | |
1777 | * FIXME: If there are no PCIe cards attached, then calling this function | |
1778 | * can result in the increase of the bootup time as there are big timeout | |
1779 | * loops. | |
1780 | */ | |
1781 | #define TEGRA_PCIE_LINKUP_TIMEOUT 200 /* up to 1.2 seconds */ | |
1782 | static bool tegra_pcie_port_check_link(struct tegra_pcie_port *port) | |
1783 | { | |
1784 | unsigned int retries = 3; | |
1785 | unsigned long value; | |
1786 | ||
7f1f054b TR |
1787 | /* override presence detection */ |
1788 | value = readl(port->base + RP_PRIV_MISC); | |
1789 | value &= ~RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT; | |
1790 | value |= RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT; | |
1791 | writel(value, port->base + RP_PRIV_MISC); | |
1792 | ||
d1523b52 TR |
1793 | do { |
1794 | unsigned int timeout = TEGRA_PCIE_LINKUP_TIMEOUT; | |
1795 | ||
1796 | do { | |
1797 | value = readl(port->base + RP_VEND_XP); | |
1798 | ||
1799 | if (value & RP_VEND_XP_DL_UP) | |
1800 | break; | |
1801 | ||
1802 | usleep_range(1000, 2000); | |
1803 | } while (--timeout); | |
1804 | ||
1805 | if (!timeout) { | |
1806 | dev_err(port->pcie->dev, "link %u down, retrying\n", | |
1807 | port->index); | |
1808 | goto retry; | |
1809 | } | |
1810 | ||
1811 | timeout = TEGRA_PCIE_LINKUP_TIMEOUT; | |
1812 | ||
1813 | do { | |
1814 | value = readl(port->base + RP_LINK_CONTROL_STATUS); | |
1815 | ||
1816 | if (value & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE) | |
1817 | return true; | |
1818 | ||
1819 | usleep_range(1000, 2000); | |
1820 | } while (--timeout); | |
1821 | ||
1822 | retry: | |
1823 | tegra_pcie_port_reset(port); | |
1824 | } while (--retries); | |
1825 | ||
1826 | return false; | |
1827 | } | |
1828 | ||
1829 | static int tegra_pcie_enable(struct tegra_pcie *pcie) | |
1830 | { | |
1831 | struct tegra_pcie_port *port, *tmp; | |
1832 | struct hw_pci hw; | |
1833 | ||
1834 | list_for_each_entry_safe(port, tmp, &pcie->ports, list) { | |
1835 | dev_info(pcie->dev, "probing port %u, using %u lanes\n", | |
1836 | port->index, port->lanes); | |
1837 | ||
1838 | tegra_pcie_port_enable(port); | |
1839 | ||
1840 | if (tegra_pcie_port_check_link(port)) | |
1841 | continue; | |
1842 | ||
1843 | dev_info(pcie->dev, "link %u down, ignoring\n", port->index); | |
1844 | ||
1845 | tegra_pcie_port_disable(port); | |
1846 | tegra_pcie_port_free(port); | |
1847 | } | |
1848 | ||
1849 | memset(&hw, 0, sizeof(hw)); | |
1850 | ||
7ec725b2 YW |
1851 | #ifdef CONFIG_PCI_MSI |
1852 | hw.msi_ctrl = &pcie->msi.chip; | |
1853 | #endif | |
1854 | ||
d1523b52 TR |
1855 | hw.nr_controllers = 1; |
1856 | hw.private_data = (void **)&pcie; | |
1857 | hw.setup = tegra_pcie_setup; | |
1858 | hw.map_irq = tegra_pcie_map_irq; | |
d1523b52 TR |
1859 | hw.ops = &tegra_pcie_ops; |
1860 | ||
1861 | pci_common_init_dev(pcie->dev, &hw); | |
1862 | ||
1863 | return 0; | |
1864 | } | |
1865 | ||
94716cdd JA |
1866 | static const struct tegra_pcie_soc_data tegra20_pcie_data = { |
1867 | .num_ports = 2, | |
1868 | .msi_base_shift = 0, | |
1869 | .pads_pll_ctl = PADS_PLL_CTL_TEGRA20, | |
1870 | .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10, | |
1871 | .has_pex_clkreq_en = false, | |
1872 | .has_pex_bias_ctrl = false, | |
1873 | .has_intr_prsnt_sense = false, | |
94716cdd | 1874 | .has_cml_clk = false, |
7f1f054b | 1875 | .has_gen2 = false, |
94716cdd JA |
1876 | }; |
1877 | ||
1878 | static const struct tegra_pcie_soc_data tegra30_pcie_data = { | |
1879 | .num_ports = 3, | |
1880 | .msi_base_shift = 8, | |
1881 | .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, | |
1882 | .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, | |
1883 | .has_pex_clkreq_en = true, | |
1884 | .has_pex_bias_ctrl = true, | |
1885 | .has_intr_prsnt_sense = true, | |
94716cdd | 1886 | .has_cml_clk = true, |
7f1f054b TR |
1887 | .has_gen2 = false, |
1888 | }; | |
1889 | ||
1890 | static const struct tegra_pcie_soc_data tegra124_pcie_data = { | |
1891 | .num_ports = 2, | |
1892 | .msi_base_shift = 8, | |
1893 | .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, | |
1894 | .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, | |
1895 | .has_pex_clkreq_en = true, | |
1896 | .has_pex_bias_ctrl = true, | |
1897 | .has_intr_prsnt_sense = true, | |
1898 | .has_cml_clk = true, | |
1899 | .has_gen2 = true, | |
94716cdd JA |
1900 | }; |
1901 | ||
1902 | static const struct of_device_id tegra_pcie_of_match[] = { | |
7f1f054b | 1903 | { .compatible = "nvidia,tegra124-pcie", .data = &tegra124_pcie_data }, |
94716cdd JA |
1904 | { .compatible = "nvidia,tegra30-pcie", .data = &tegra30_pcie_data }, |
1905 | { .compatible = "nvidia,tegra20-pcie", .data = &tegra20_pcie_data }, | |
1906 | { }, | |
1907 | }; | |
1908 | MODULE_DEVICE_TABLE(of, tegra_pcie_of_match); | |
1909 | ||
2cb989f6 TR |
1910 | static void *tegra_pcie_ports_seq_start(struct seq_file *s, loff_t *pos) |
1911 | { | |
1912 | struct tegra_pcie *pcie = s->private; | |
1913 | ||
1914 | if (list_empty(&pcie->ports)) | |
1915 | return NULL; | |
1916 | ||
1917 | seq_printf(s, "Index Status\n"); | |
1918 | ||
1919 | return seq_list_start(&pcie->ports, *pos); | |
1920 | } | |
1921 | ||
1922 | static void *tegra_pcie_ports_seq_next(struct seq_file *s, void *v, loff_t *pos) | |
1923 | { | |
1924 | struct tegra_pcie *pcie = s->private; | |
1925 | ||
1926 | return seq_list_next(v, &pcie->ports, pos); | |
1927 | } | |
1928 | ||
1929 | static void tegra_pcie_ports_seq_stop(struct seq_file *s, void *v) | |
1930 | { | |
1931 | } | |
1932 | ||
1933 | static int tegra_pcie_ports_seq_show(struct seq_file *s, void *v) | |
1934 | { | |
1935 | bool up = false, active = false; | |
1936 | struct tegra_pcie_port *port; | |
1937 | unsigned int value; | |
1938 | ||
1939 | port = list_entry(v, struct tegra_pcie_port, list); | |
1940 | ||
1941 | value = readl(port->base + RP_VEND_XP); | |
1942 | ||
1943 | if (value & RP_VEND_XP_DL_UP) | |
1944 | up = true; | |
1945 | ||
1946 | value = readl(port->base + RP_LINK_CONTROL_STATUS); | |
1947 | ||
1948 | if (value & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE) | |
1949 | active = true; | |
1950 | ||
1951 | seq_printf(s, "%2u ", port->index); | |
1952 | ||
1953 | if (up) | |
1954 | seq_printf(s, "up"); | |
1955 | ||
1956 | if (active) { | |
1957 | if (up) | |
1958 | seq_printf(s, ", "); | |
1959 | ||
1960 | seq_printf(s, "active"); | |
1961 | } | |
1962 | ||
1963 | seq_printf(s, "\n"); | |
1964 | return 0; | |
1965 | } | |
1966 | ||
1967 | static const struct seq_operations tegra_pcie_ports_seq_ops = { | |
1968 | .start = tegra_pcie_ports_seq_start, | |
1969 | .next = tegra_pcie_ports_seq_next, | |
1970 | .stop = tegra_pcie_ports_seq_stop, | |
1971 | .show = tegra_pcie_ports_seq_show, | |
1972 | }; | |
1973 | ||
1974 | static int tegra_pcie_ports_open(struct inode *inode, struct file *file) | |
1975 | { | |
1976 | struct tegra_pcie *pcie = inode->i_private; | |
1977 | struct seq_file *s; | |
1978 | int err; | |
1979 | ||
1980 | err = seq_open(file, &tegra_pcie_ports_seq_ops); | |
1981 | if (err) | |
1982 | return err; | |
1983 | ||
1984 | s = file->private_data; | |
1985 | s->private = pcie; | |
1986 | ||
1987 | return 0; | |
1988 | } | |
1989 | ||
1990 | static const struct file_operations tegra_pcie_ports_ops = { | |
1991 | .owner = THIS_MODULE, | |
1992 | .open = tegra_pcie_ports_open, | |
1993 | .read = seq_read, | |
1994 | .llseek = seq_lseek, | |
1995 | .release = seq_release, | |
1996 | }; | |
1997 | ||
1998 | static int tegra_pcie_debugfs_init(struct tegra_pcie *pcie) | |
1999 | { | |
2000 | struct dentry *file; | |
2001 | ||
2002 | pcie->debugfs = debugfs_create_dir("pcie", NULL); | |
2003 | if (!pcie->debugfs) | |
2004 | return -ENOMEM; | |
2005 | ||
2006 | file = debugfs_create_file("ports", S_IFREG | S_IRUGO, pcie->debugfs, | |
2007 | pcie, &tegra_pcie_ports_ops); | |
2008 | if (!file) | |
2009 | goto remove; | |
2010 | ||
2011 | return 0; | |
2012 | ||
2013 | remove: | |
2014 | debugfs_remove_recursive(pcie->debugfs); | |
2015 | pcie->debugfs = NULL; | |
2016 | return -ENOMEM; | |
2017 | } | |
2018 | ||
d1523b52 TR |
2019 | static int tegra_pcie_probe(struct platform_device *pdev) |
2020 | { | |
94716cdd | 2021 | const struct of_device_id *match; |
d1523b52 TR |
2022 | struct tegra_pcie *pcie; |
2023 | int err; | |
2024 | ||
94716cdd JA |
2025 | match = of_match_device(tegra_pcie_of_match, &pdev->dev); |
2026 | if (!match) | |
2027 | return -ENODEV; | |
2028 | ||
d1523b52 TR |
2029 | pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL); |
2030 | if (!pcie) | |
2031 | return -ENOMEM; | |
2032 | ||
f7625980 | 2033 | INIT_LIST_HEAD(&pcie->buses); |
d1523b52 | 2034 | INIT_LIST_HEAD(&pcie->ports); |
94716cdd | 2035 | pcie->soc_data = match->data; |
d1523b52 TR |
2036 | pcie->dev = &pdev->dev; |
2037 | ||
2038 | err = tegra_pcie_parse_dt(pcie); | |
2039 | if (err < 0) | |
2040 | return err; | |
2041 | ||
2042 | pcibios_min_mem = 0; | |
2043 | ||
2044 | err = tegra_pcie_get_resources(pcie); | |
2045 | if (err < 0) { | |
2046 | dev_err(&pdev->dev, "failed to request resources: %d\n", err); | |
2047 | return err; | |
2048 | } | |
2049 | ||
2050 | err = tegra_pcie_enable_controller(pcie); | |
2051 | if (err) | |
2052 | goto put_resources; | |
2053 | ||
2054 | /* setup the AFI address translations */ | |
2055 | tegra_pcie_setup_translations(pcie); | |
2056 | ||
2057 | if (IS_ENABLED(CONFIG_PCI_MSI)) { | |
2058 | err = tegra_pcie_enable_msi(pcie); | |
2059 | if (err < 0) { | |
2060 | dev_err(&pdev->dev, | |
2061 | "failed to enable MSI support: %d\n", | |
2062 | err); | |
2063 | goto put_resources; | |
2064 | } | |
2065 | } | |
2066 | ||
2067 | err = tegra_pcie_enable(pcie); | |
2068 | if (err < 0) { | |
2069 | dev_err(&pdev->dev, "failed to enable PCIe ports: %d\n", err); | |
2070 | goto disable_msi; | |
2071 | } | |
2072 | ||
2cb989f6 TR |
2073 | if (IS_ENABLED(CONFIG_DEBUG_FS)) { |
2074 | err = tegra_pcie_debugfs_init(pcie); | |
2075 | if (err < 0) | |
2076 | dev_err(&pdev->dev, "failed to setup debugfs: %d\n", | |
2077 | err); | |
2078 | } | |
2079 | ||
d1523b52 TR |
2080 | platform_set_drvdata(pdev, pcie); |
2081 | return 0; | |
2082 | ||
2083 | disable_msi: | |
2084 | if (IS_ENABLED(CONFIG_PCI_MSI)) | |
2085 | tegra_pcie_disable_msi(pcie); | |
2086 | put_resources: | |
2087 | tegra_pcie_put_resources(pcie); | |
2088 | return err; | |
2089 | } | |
2090 | ||
d1523b52 TR |
2091 | static struct platform_driver tegra_pcie_driver = { |
2092 | .driver = { | |
2093 | .name = "tegra-pcie", | |
d1523b52 TR |
2094 | .of_match_table = tegra_pcie_of_match, |
2095 | .suppress_bind_attrs = true, | |
2096 | }, | |
2097 | .probe = tegra_pcie_probe, | |
2098 | }; | |
2099 | module_platform_driver(tegra_pcie_driver); | |
2100 | ||
2101 | MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); | |
2102 | MODULE_DESCRIPTION("NVIDIA Tegra PCIe driver"); | |
d975cb57 | 2103 | MODULE_LICENSE("GPL v2"); |