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340cba60 JH |
1 | /* |
2 | * PCIe host controller driver for Samsung EXYNOS SoCs | |
3 | * | |
4 | * Copyright (C) 2013 Samsung Electronics Co., Ltd. | |
5 | * http://www.samsung.com | |
6 | * | |
7 | * Author: Jingoo Han <jg1.han@samsung.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #include <linux/clk.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/gpio.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/kernel.h> | |
19 | #include <linux/list.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/of.h> | |
22 | #include <linux/of_address.h> | |
23 | #include <linux/of_gpio.h> | |
24 | #include <linux/of_pci.h> | |
25 | #include <linux/pci.h> | |
26 | #include <linux/pci_regs.h> | |
27 | #include <linux/platform_device.h> | |
28 | #include <linux/resource.h> | |
29 | #include <linux/signal.h> | |
30 | #include <linux/slab.h> | |
31 | #include <linux/types.h> | |
32 | ||
33 | struct pcie_port_info { | |
34 | u32 cfg0_size; | |
35 | u32 cfg1_size; | |
36 | u32 io_size; | |
37 | u32 mem_size; | |
38 | phys_addr_t io_bus_addr; | |
39 | phys_addr_t mem_bus_addr; | |
40 | }; | |
41 | ||
42 | struct pcie_port { | |
43 | struct device *dev; | |
44 | u8 controller; | |
45 | u8 root_bus_nr; | |
46 | void __iomem *dbi_base; | |
47 | void __iomem *elbi_base; | |
48 | void __iomem *phy_base; | |
49 | void __iomem *purple_base; | |
50 | u64 cfg0_base; | |
51 | void __iomem *va_cfg0_base; | |
52 | u64 cfg1_base; | |
53 | void __iomem *va_cfg1_base; | |
54 | u64 io_base; | |
55 | u64 mem_base; | |
56 | spinlock_t conf_lock; | |
57 | struct resource cfg; | |
58 | struct resource io; | |
59 | struct resource mem; | |
60 | struct pcie_port_info config; | |
61 | struct clk *clk; | |
62 | struct clk *bus_clk; | |
63 | int irq; | |
64 | int reset_gpio; | |
65 | }; | |
66 | ||
67 | /* | |
68 | * Exynos PCIe IP consists of Synopsys specific part and Exynos | |
69 | * specific part. Only core block is a Synopsys designware part; | |
70 | * other parts are Exynos specific. | |
71 | */ | |
72 | ||
73 | /* Synopsis specific PCIE configuration registers */ | |
74 | #define PCIE_PORT_LINK_CONTROL 0x710 | |
75 | #define PORT_LINK_MODE_MASK (0x3f << 16) | |
76 | #define PORT_LINK_MODE_4_LANES (0x7 << 16) | |
77 | ||
78 | #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C | |
79 | #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17) | |
80 | #define PORT_LOGIC_LINK_WIDTH_MASK (0x1ff << 8) | |
81 | #define PORT_LOGIC_LINK_WIDTH_4_LANES (0x7 << 8) | |
82 | ||
83 | #define PCIE_MSI_ADDR_LO 0x820 | |
84 | #define PCIE_MSI_ADDR_HI 0x824 | |
85 | #define PCIE_MSI_INTR0_ENABLE 0x828 | |
86 | #define PCIE_MSI_INTR0_MASK 0x82C | |
87 | #define PCIE_MSI_INTR0_STATUS 0x830 | |
88 | ||
89 | #define PCIE_ATU_VIEWPORT 0x900 | |
90 | #define PCIE_ATU_REGION_INBOUND (0x1 << 31) | |
91 | #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31) | |
92 | #define PCIE_ATU_REGION_INDEX1 (0x1 << 0) | |
93 | #define PCIE_ATU_REGION_INDEX0 (0x0 << 0) | |
94 | #define PCIE_ATU_CR1 0x904 | |
95 | #define PCIE_ATU_TYPE_MEM (0x0 << 0) | |
96 | #define PCIE_ATU_TYPE_IO (0x2 << 0) | |
97 | #define PCIE_ATU_TYPE_CFG0 (0x4 << 0) | |
98 | #define PCIE_ATU_TYPE_CFG1 (0x5 << 0) | |
99 | #define PCIE_ATU_CR2 0x908 | |
100 | #define PCIE_ATU_ENABLE (0x1 << 31) | |
101 | #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30) | |
102 | #define PCIE_ATU_LOWER_BASE 0x90C | |
103 | #define PCIE_ATU_UPPER_BASE 0x910 | |
104 | #define PCIE_ATU_LIMIT 0x914 | |
105 | #define PCIE_ATU_LOWER_TARGET 0x918 | |
106 | #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24) | |
107 | #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19) | |
108 | #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) | |
109 | #define PCIE_ATU_UPPER_TARGET 0x91C | |
110 | ||
111 | /* Exynos specific PCIE configuration registers */ | |
112 | ||
113 | /* PCIe ELBI registers */ | |
114 | #define PCIE_IRQ_PULSE 0x000 | |
115 | #define IRQ_INTA_ASSERT (0x1 << 0) | |
116 | #define IRQ_INTB_ASSERT (0x1 << 2) | |
117 | #define IRQ_INTC_ASSERT (0x1 << 4) | |
118 | #define IRQ_INTD_ASSERT (0x1 << 6) | |
119 | #define PCIE_IRQ_LEVEL 0x004 | |
120 | #define PCIE_IRQ_SPECIAL 0x008 | |
121 | #define PCIE_IRQ_EN_PULSE 0x00c | |
122 | #define PCIE_IRQ_EN_LEVEL 0x010 | |
123 | #define PCIE_IRQ_EN_SPECIAL 0x014 | |
124 | #define PCIE_PWR_RESET 0x018 | |
125 | #define PCIE_CORE_RESET 0x01c | |
126 | #define PCIE_CORE_RESET_ENABLE (0x1 << 0) | |
127 | #define PCIE_STICKY_RESET 0x020 | |
128 | #define PCIE_NONSTICKY_RESET 0x024 | |
129 | #define PCIE_APP_INIT_RESET 0x028 | |
130 | #define PCIE_APP_LTSSM_ENABLE 0x02c | |
131 | #define PCIE_ELBI_RDLH_LINKUP 0x064 | |
132 | #define PCIE_ELBI_LTSSM_ENABLE 0x1 | |
133 | #define PCIE_ELBI_SLV_AWMISC 0x11c | |
134 | #define PCIE_ELBI_SLV_ARMISC 0x120 | |
135 | #define PCIE_ELBI_SLV_DBI_ENABLE (0x1 << 21) | |
136 | ||
137 | /* PCIe Purple registers */ | |
138 | #define PCIE_PHY_GLOBAL_RESET 0x000 | |
139 | #define PCIE_PHY_COMMON_RESET 0x004 | |
140 | #define PCIE_PHY_CMN_REG 0x008 | |
141 | #define PCIE_PHY_MAC_RESET 0x00c | |
142 | #define PCIE_PHY_PLL_LOCKED 0x010 | |
143 | #define PCIE_PHY_TRSVREG_RESET 0x020 | |
144 | #define PCIE_PHY_TRSV_RESET 0x024 | |
145 | ||
146 | /* PCIe PHY registers */ | |
147 | #define PCIE_PHY_IMPEDANCE 0x004 | |
148 | #define PCIE_PHY_PLL_DIV_0 0x008 | |
149 | #define PCIE_PHY_PLL_BIAS 0x00c | |
150 | #define PCIE_PHY_DCC_FEEDBACK 0x014 | |
151 | #define PCIE_PHY_PLL_DIV_1 0x05c | |
152 | #define PCIE_PHY_TRSV0_EMP_LVL 0x084 | |
153 | #define PCIE_PHY_TRSV0_DRV_LVL 0x088 | |
154 | #define PCIE_PHY_TRSV0_RXCDR 0x0ac | |
155 | #define PCIE_PHY_TRSV0_LVCC 0x0dc | |
156 | #define PCIE_PHY_TRSV1_EMP_LVL 0x144 | |
157 | #define PCIE_PHY_TRSV1_RXCDR 0x16c | |
158 | #define PCIE_PHY_TRSV1_LVCC 0x19c | |
159 | #define PCIE_PHY_TRSV2_EMP_LVL 0x204 | |
160 | #define PCIE_PHY_TRSV2_RXCDR 0x22c | |
161 | #define PCIE_PHY_TRSV2_LVCC 0x25c | |
162 | #define PCIE_PHY_TRSV3_EMP_LVL 0x2c4 | |
163 | #define PCIE_PHY_TRSV3_RXCDR 0x2ec | |
164 | #define PCIE_PHY_TRSV3_LVCC 0x31c | |
165 | ||
166 | static struct hw_pci exynos_pci; | |
167 | ||
168 | static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys) | |
169 | { | |
170 | return sys->private_data; | |
171 | } | |
172 | ||
173 | static inline int cfg_read(void *addr, int where, int size, u32 *val) | |
174 | { | |
175 | *val = readl(addr); | |
176 | ||
177 | if (size == 1) | |
178 | *val = (*val >> (8 * (where & 3))) & 0xff; | |
179 | else if (size == 2) | |
180 | *val = (*val >> (8 * (where & 3))) & 0xffff; | |
181 | else if (size != 4) | |
182 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
183 | ||
184 | return PCIBIOS_SUCCESSFUL; | |
185 | } | |
186 | ||
187 | static inline int cfg_write(void *addr, int where, int size, u32 val) | |
188 | { | |
189 | if (size == 4) | |
190 | writel(val, addr); | |
191 | else if (size == 2) | |
192 | writew(val, addr + (where & 2)); | |
193 | else if (size == 1) | |
194 | writeb(val, addr + (where & 3)); | |
195 | else | |
196 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
197 | ||
198 | return PCIBIOS_SUCCESSFUL; | |
199 | } | |
200 | ||
201 | static void exynos_pcie_sideband_dbi_w_mode(struct pcie_port *pp, bool on) | |
202 | { | |
203 | u32 val; | |
204 | ||
205 | if (on) { | |
206 | val = readl(pp->elbi_base + PCIE_ELBI_SLV_AWMISC); | |
207 | val |= PCIE_ELBI_SLV_DBI_ENABLE; | |
208 | writel(val, pp->elbi_base + PCIE_ELBI_SLV_AWMISC); | |
209 | } else { | |
210 | val = readl(pp->elbi_base + PCIE_ELBI_SLV_AWMISC); | |
211 | val &= ~PCIE_ELBI_SLV_DBI_ENABLE; | |
212 | writel(val, pp->elbi_base + PCIE_ELBI_SLV_AWMISC); | |
213 | } | |
214 | } | |
215 | ||
216 | static void exynos_pcie_sideband_dbi_r_mode(struct pcie_port *pp, bool on) | |
217 | { | |
218 | u32 val; | |
219 | ||
220 | if (on) { | |
221 | val = readl(pp->elbi_base + PCIE_ELBI_SLV_ARMISC); | |
222 | val |= PCIE_ELBI_SLV_DBI_ENABLE; | |
223 | writel(val, pp->elbi_base + PCIE_ELBI_SLV_ARMISC); | |
224 | } else { | |
225 | val = readl(pp->elbi_base + PCIE_ELBI_SLV_ARMISC); | |
226 | val &= ~PCIE_ELBI_SLV_DBI_ENABLE; | |
227 | writel(val, pp->elbi_base + PCIE_ELBI_SLV_ARMISC); | |
228 | } | |
229 | } | |
230 | ||
231 | static inline void readl_rc(struct pcie_port *pp, void *dbi_base, u32 *val) | |
232 | { | |
233 | exynos_pcie_sideband_dbi_r_mode(pp, true); | |
234 | *val = readl(dbi_base); | |
235 | exynos_pcie_sideband_dbi_r_mode(pp, false); | |
236 | return; | |
237 | } | |
238 | ||
239 | static inline void writel_rc(struct pcie_port *pp, u32 val, void *dbi_base) | |
240 | { | |
241 | exynos_pcie_sideband_dbi_w_mode(pp, true); | |
242 | writel(val, dbi_base); | |
243 | exynos_pcie_sideband_dbi_w_mode(pp, false); | |
244 | return; | |
245 | } | |
246 | ||
247 | static int exynos_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, | |
248 | u32 *val) | |
249 | { | |
250 | int ret; | |
251 | ||
252 | exynos_pcie_sideband_dbi_r_mode(pp, true); | |
253 | ret = cfg_read(pp->dbi_base + (where & ~0x3), where, size, val); | |
254 | exynos_pcie_sideband_dbi_r_mode(pp, false); | |
255 | return ret; | |
256 | } | |
257 | ||
258 | static int exynos_pcie_wr_own_conf(struct pcie_port *pp, int where, int size, | |
259 | u32 val) | |
260 | { | |
261 | int ret; | |
262 | ||
263 | exynos_pcie_sideband_dbi_w_mode(pp, true); | |
264 | ret = cfg_write(pp->dbi_base + (where & ~0x3), where, size, val); | |
265 | exynos_pcie_sideband_dbi_w_mode(pp, false); | |
266 | return ret; | |
267 | } | |
268 | ||
269 | static void exynos_pcie_prog_viewport_cfg0(struct pcie_port *pp, u32 busdev) | |
270 | { | |
271 | u32 val; | |
272 | void __iomem *dbi_base = pp->dbi_base; | |
273 | ||
274 | /* Program viewport 0 : OUTBOUND : CFG0 */ | |
275 | val = PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0; | |
276 | writel_rc(pp, val, dbi_base + PCIE_ATU_VIEWPORT); | |
277 | writel_rc(pp, pp->cfg0_base, dbi_base + PCIE_ATU_LOWER_BASE); | |
278 | writel_rc(pp, (pp->cfg0_base >> 32), dbi_base + PCIE_ATU_UPPER_BASE); | |
279 | writel_rc(pp, pp->cfg0_base + pp->config.cfg0_size - 1, | |
280 | dbi_base + PCIE_ATU_LIMIT); | |
281 | writel_rc(pp, busdev, dbi_base + PCIE_ATU_LOWER_TARGET); | |
282 | writel_rc(pp, 0, dbi_base + PCIE_ATU_UPPER_TARGET); | |
283 | writel_rc(pp, PCIE_ATU_TYPE_CFG0, dbi_base + PCIE_ATU_CR1); | |
284 | val = PCIE_ATU_ENABLE; | |
285 | writel_rc(pp, val, dbi_base + PCIE_ATU_CR2); | |
286 | } | |
287 | ||
288 | static void exynos_pcie_prog_viewport_cfg1(struct pcie_port *pp, u32 busdev) | |
289 | { | |
290 | u32 val; | |
291 | void __iomem *dbi_base = pp->dbi_base; | |
292 | ||
293 | /* Program viewport 1 : OUTBOUND : CFG1 */ | |
294 | val = PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1; | |
295 | writel_rc(pp, val, dbi_base + PCIE_ATU_VIEWPORT); | |
296 | writel_rc(pp, PCIE_ATU_TYPE_CFG1, dbi_base + PCIE_ATU_CR1); | |
297 | val = PCIE_ATU_ENABLE; | |
298 | writel_rc(pp, val, dbi_base + PCIE_ATU_CR2); | |
299 | writel_rc(pp, pp->cfg1_base, dbi_base + PCIE_ATU_LOWER_BASE); | |
300 | writel_rc(pp, (pp->cfg1_base >> 32), dbi_base + PCIE_ATU_UPPER_BASE); | |
301 | writel_rc(pp, pp->cfg1_base + pp->config.cfg1_size - 1, | |
302 | dbi_base + PCIE_ATU_LIMIT); | |
303 | writel_rc(pp, busdev, dbi_base + PCIE_ATU_LOWER_TARGET); | |
304 | writel_rc(pp, 0, dbi_base + PCIE_ATU_UPPER_TARGET); | |
305 | } | |
306 | ||
307 | static void exynos_pcie_prog_viewport_mem_outbound(struct pcie_port *pp) | |
308 | { | |
309 | u32 val; | |
310 | void __iomem *dbi_base = pp->dbi_base; | |
311 | ||
312 | /* Program viewport 0 : OUTBOUND : MEM */ | |
313 | val = PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0; | |
314 | writel_rc(pp, val, dbi_base + PCIE_ATU_VIEWPORT); | |
315 | writel_rc(pp, PCIE_ATU_TYPE_MEM, dbi_base + PCIE_ATU_CR1); | |
316 | val = PCIE_ATU_ENABLE; | |
317 | writel_rc(pp, val, dbi_base + PCIE_ATU_CR2); | |
318 | writel_rc(pp, pp->mem_base, dbi_base + PCIE_ATU_LOWER_BASE); | |
319 | writel_rc(pp, (pp->mem_base >> 32), dbi_base + PCIE_ATU_UPPER_BASE); | |
320 | writel_rc(pp, pp->mem_base + pp->config.mem_size - 1, | |
321 | dbi_base + PCIE_ATU_LIMIT); | |
322 | writel_rc(pp, pp->config.mem_bus_addr, | |
323 | dbi_base + PCIE_ATU_LOWER_TARGET); | |
324 | writel_rc(pp, upper_32_bits(pp->config.mem_bus_addr), | |
325 | dbi_base + PCIE_ATU_UPPER_TARGET); | |
326 | } | |
327 | ||
328 | static void exynos_pcie_prog_viewport_io_outbound(struct pcie_port *pp) | |
329 | { | |
330 | u32 val; | |
331 | void __iomem *dbi_base = pp->dbi_base; | |
332 | ||
333 | /* Program viewport 1 : OUTBOUND : IO */ | |
334 | val = PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1; | |
335 | writel_rc(pp, val, dbi_base + PCIE_ATU_VIEWPORT); | |
336 | writel_rc(pp, PCIE_ATU_TYPE_IO, dbi_base + PCIE_ATU_CR1); | |
337 | val = PCIE_ATU_ENABLE; | |
338 | writel_rc(pp, val, dbi_base + PCIE_ATU_CR2); | |
339 | writel_rc(pp, pp->io_base, dbi_base + PCIE_ATU_LOWER_BASE); | |
340 | writel_rc(pp, (pp->io_base >> 32), dbi_base + PCIE_ATU_UPPER_BASE); | |
341 | writel_rc(pp, pp->io_base + pp->config.io_size - 1, | |
342 | dbi_base + PCIE_ATU_LIMIT); | |
343 | writel_rc(pp, pp->config.io_bus_addr, | |
344 | dbi_base + PCIE_ATU_LOWER_TARGET); | |
345 | writel_rc(pp, upper_32_bits(pp->config.io_bus_addr), | |
346 | dbi_base + PCIE_ATU_UPPER_TARGET); | |
347 | } | |
348 | ||
349 | static int exynos_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, | |
350 | u32 devfn, int where, int size, u32 *val) | |
351 | { | |
352 | int ret = PCIBIOS_SUCCESSFUL; | |
353 | u32 address, busdev; | |
354 | ||
355 | busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) | | |
356 | PCIE_ATU_FUNC(PCI_FUNC(devfn)); | |
357 | address = where & ~0x3; | |
358 | ||
359 | if (bus->parent->number == pp->root_bus_nr) { | |
360 | exynos_pcie_prog_viewport_cfg0(pp, busdev); | |
361 | ret = cfg_read(pp->va_cfg0_base + address, where, size, val); | |
362 | exynos_pcie_prog_viewport_mem_outbound(pp); | |
363 | } else { | |
364 | exynos_pcie_prog_viewport_cfg1(pp, busdev); | |
365 | ret = cfg_read(pp->va_cfg1_base + address, where, size, val); | |
366 | exynos_pcie_prog_viewport_io_outbound(pp); | |
367 | } | |
368 | ||
369 | return ret; | |
370 | } | |
371 | ||
372 | static int exynos_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, | |
373 | u32 devfn, int where, int size, u32 val) | |
374 | { | |
375 | int ret = PCIBIOS_SUCCESSFUL; | |
376 | u32 address, busdev; | |
377 | ||
378 | busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) | | |
379 | PCIE_ATU_FUNC(PCI_FUNC(devfn)); | |
380 | address = where & ~0x3; | |
381 | ||
382 | if (bus->parent->number == pp->root_bus_nr) { | |
383 | exynos_pcie_prog_viewport_cfg0(pp, busdev); | |
384 | ret = cfg_write(pp->va_cfg0_base + address, where, size, val); | |
385 | exynos_pcie_prog_viewport_mem_outbound(pp); | |
386 | } else { | |
387 | exynos_pcie_prog_viewport_cfg1(pp, busdev); | |
388 | ret = cfg_write(pp->va_cfg1_base + address, where, size, val); | |
389 | exynos_pcie_prog_viewport_io_outbound(pp); | |
390 | } | |
391 | ||
392 | return ret; | |
393 | } | |
394 | ||
395 | static unsigned long global_io_offset; | |
396 | ||
397 | static int exynos_pcie_setup(int nr, struct pci_sys_data *sys) | |
398 | { | |
399 | struct pcie_port *pp; | |
400 | ||
401 | pp = sys_to_pcie(sys); | |
402 | ||
403 | if (!pp) | |
404 | return 0; | |
405 | ||
406 | if (global_io_offset < SZ_1M && pp->config.io_size > 0) { | |
407 | sys->io_offset = global_io_offset - pp->config.io_bus_addr; | |
408 | pci_ioremap_io(sys->io_offset, pp->io.start); | |
409 | global_io_offset += SZ_64K; | |
410 | pci_add_resource_offset(&sys->resources, &pp->io, | |
411 | sys->io_offset); | |
412 | } | |
413 | ||
414 | sys->mem_offset = pp->mem.start - pp->config.mem_bus_addr; | |
415 | pci_add_resource_offset(&sys->resources, &pp->mem, sys->mem_offset); | |
416 | ||
417 | return 1; | |
418 | } | |
419 | ||
420 | static int exynos_pcie_link_up(struct pcie_port *pp) | |
421 | { | |
422 | u32 val = readl(pp->elbi_base + PCIE_ELBI_RDLH_LINKUP); | |
423 | ||
424 | if (val == PCIE_ELBI_LTSSM_ENABLE) | |
425 | return 1; | |
426 | ||
427 | return 0; | |
428 | } | |
429 | ||
430 | static int exynos_pcie_valid_config(struct pcie_port *pp, | |
431 | struct pci_bus *bus, int dev) | |
432 | { | |
433 | /* If there is no link, then there is no device */ | |
434 | if (bus->number != pp->root_bus_nr) { | |
435 | if (!exynos_pcie_link_up(pp)) | |
436 | return 0; | |
437 | } | |
438 | ||
439 | /* access only one slot on each root port */ | |
440 | if (bus->number == pp->root_bus_nr && dev > 0) | |
441 | return 0; | |
442 | ||
443 | /* | |
444 | * do not read more than one device on the bus directly attached | |
445 | * to RC's (Virtual Bridge's) DS side. | |
446 | */ | |
447 | if (bus->primary == pp->root_bus_nr && dev > 0) | |
448 | return 0; | |
449 | ||
450 | return 1; | |
451 | } | |
452 | ||
453 | static int exynos_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, | |
454 | int size, u32 *val) | |
455 | { | |
456 | struct pcie_port *pp = sys_to_pcie(bus->sysdata); | |
457 | unsigned long flags; | |
458 | int ret; | |
459 | ||
460 | if (!pp) { | |
461 | BUG(); | |
462 | return -EINVAL; | |
463 | } | |
464 | ||
465 | if (exynos_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) { | |
466 | *val = 0xffffffff; | |
467 | return PCIBIOS_DEVICE_NOT_FOUND; | |
468 | } | |
469 | ||
470 | spin_lock_irqsave(&pp->conf_lock, flags); | |
471 | if (bus->number != pp->root_bus_nr) | |
472 | ret = exynos_pcie_rd_other_conf(pp, bus, devfn, | |
473 | where, size, val); | |
474 | else | |
475 | ret = exynos_pcie_rd_own_conf(pp, where, size, val); | |
476 | spin_unlock_irqrestore(&pp->conf_lock, flags); | |
477 | ||
478 | return ret; | |
479 | } | |
480 | ||
481 | static int exynos_pcie_wr_conf(struct pci_bus *bus, u32 devfn, | |
482 | int where, int size, u32 val) | |
483 | { | |
484 | struct pcie_port *pp = sys_to_pcie(bus->sysdata); | |
485 | unsigned long flags; | |
486 | int ret; | |
487 | ||
488 | if (!pp) { | |
489 | BUG(); | |
490 | return -EINVAL; | |
491 | } | |
492 | ||
493 | if (exynos_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) | |
494 | return PCIBIOS_DEVICE_NOT_FOUND; | |
495 | ||
496 | spin_lock_irqsave(&pp->conf_lock, flags); | |
497 | if (bus->number != pp->root_bus_nr) | |
498 | ret = exynos_pcie_wr_other_conf(pp, bus, devfn, | |
499 | where, size, val); | |
500 | else | |
501 | ret = exynos_pcie_wr_own_conf(pp, where, size, val); | |
502 | spin_unlock_irqrestore(&pp->conf_lock, flags); | |
503 | ||
504 | return ret; | |
505 | } | |
506 | ||
507 | static struct pci_ops exynos_pcie_ops = { | |
508 | .read = exynos_pcie_rd_conf, | |
509 | .write = exynos_pcie_wr_conf, | |
510 | }; | |
511 | ||
512 | static struct pci_bus *exynos_pcie_scan_bus(int nr, | |
513 | struct pci_sys_data *sys) | |
514 | { | |
515 | struct pci_bus *bus; | |
516 | struct pcie_port *pp = sys_to_pcie(sys); | |
517 | ||
518 | if (pp) { | |
519 | pp->root_bus_nr = sys->busnr; | |
520 | bus = pci_scan_root_bus(NULL, sys->busnr, &exynos_pcie_ops, | |
521 | sys, &sys->resources); | |
522 | } else { | |
523 | bus = NULL; | |
524 | BUG(); | |
525 | } | |
526 | ||
527 | return bus; | |
528 | } | |
529 | ||
530 | static int exynos_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) | |
531 | { | |
532 | struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata); | |
533 | ||
534 | return pp->irq; | |
535 | } | |
536 | ||
537 | static struct hw_pci exynos_pci = { | |
538 | .setup = exynos_pcie_setup, | |
539 | .scan = exynos_pcie_scan_bus, | |
540 | .map_irq = exynos_pcie_map_irq, | |
541 | }; | |
542 | ||
543 | static void exynos_pcie_setup_rc(struct pcie_port *pp) | |
544 | { | |
545 | struct pcie_port_info *config = &pp->config; | |
546 | void __iomem *dbi_base = pp->dbi_base; | |
547 | u32 val; | |
548 | u32 membase; | |
549 | u32 memlimit; | |
550 | ||
551 | /* set the number of lines as 4 */ | |
552 | readl_rc(pp, dbi_base + PCIE_PORT_LINK_CONTROL, &val); | |
553 | val &= ~PORT_LINK_MODE_MASK; | |
554 | val |= PORT_LINK_MODE_4_LANES; | |
555 | writel_rc(pp, val, dbi_base + PCIE_PORT_LINK_CONTROL); | |
556 | ||
557 | /* set link width speed control register */ | |
558 | readl_rc(pp, dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL, &val); | |
559 | val &= ~PORT_LOGIC_LINK_WIDTH_MASK; | |
560 | val |= PORT_LOGIC_LINK_WIDTH_4_LANES; | |
561 | writel_rc(pp, val, dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); | |
562 | ||
563 | /* setup RC BARs */ | |
564 | writel_rc(pp, 0x00000004, dbi_base + PCI_BASE_ADDRESS_0); | |
565 | writel_rc(pp, 0x00000004, dbi_base + PCI_BASE_ADDRESS_1); | |
566 | ||
567 | /* setup interrupt pins */ | |
568 | readl_rc(pp, dbi_base + PCI_INTERRUPT_LINE, &val); | |
569 | val &= 0xffff00ff; | |
570 | val |= 0x00000100; | |
571 | writel_rc(pp, val, dbi_base + PCI_INTERRUPT_LINE); | |
572 | ||
573 | /* setup bus numbers */ | |
574 | readl_rc(pp, dbi_base + PCI_PRIMARY_BUS, &val); | |
575 | val &= 0xff000000; | |
576 | val |= 0x00010100; | |
577 | writel_rc(pp, val, dbi_base + PCI_PRIMARY_BUS); | |
578 | ||
579 | /* setup memory base, memory limit */ | |
580 | membase = ((u32)pp->mem_base & 0xfff00000) >> 16; | |
581 | memlimit = (config->mem_size + (u32)pp->mem_base) & 0xfff00000; | |
582 | val = memlimit | membase; | |
583 | writel_rc(pp, val, dbi_base + PCI_MEMORY_BASE); | |
584 | ||
585 | /* setup command register */ | |
586 | readl_rc(pp, dbi_base + PCI_COMMAND, &val); | |
587 | val &= 0xffff0000; | |
588 | val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | | |
589 | PCI_COMMAND_MASTER | PCI_COMMAND_SERR; | |
590 | writel_rc(pp, val, dbi_base + PCI_COMMAND); | |
591 | } | |
592 | ||
593 | static void exynos_pcie_assert_core_reset(struct pcie_port *pp) | |
594 | { | |
595 | u32 val; | |
596 | void __iomem *elbi_base = pp->elbi_base; | |
597 | ||
598 | val = readl(elbi_base + PCIE_CORE_RESET); | |
599 | val &= ~PCIE_CORE_RESET_ENABLE; | |
600 | writel(val, elbi_base + PCIE_CORE_RESET); | |
601 | writel(0, elbi_base + PCIE_PWR_RESET); | |
602 | writel(0, elbi_base + PCIE_STICKY_RESET); | |
603 | writel(0, elbi_base + PCIE_NONSTICKY_RESET); | |
604 | } | |
605 | ||
606 | static void exynos_pcie_deassert_core_reset(struct pcie_port *pp) | |
607 | { | |
608 | u32 val; | |
609 | void __iomem *elbi_base = pp->elbi_base; | |
610 | void __iomem *purple_base = pp->purple_base; | |
611 | ||
612 | val = readl(elbi_base + PCIE_CORE_RESET); | |
613 | val |= PCIE_CORE_RESET_ENABLE; | |
614 | writel(val, elbi_base + PCIE_CORE_RESET); | |
615 | writel(1, elbi_base + PCIE_STICKY_RESET); | |
616 | writel(1, elbi_base + PCIE_NONSTICKY_RESET); | |
617 | writel(1, elbi_base + PCIE_APP_INIT_RESET); | |
618 | writel(0, elbi_base + PCIE_APP_INIT_RESET); | |
619 | writel(1, purple_base + PCIE_PHY_MAC_RESET); | |
620 | } | |
621 | ||
622 | static void exynos_pcie_assert_phy_reset(struct pcie_port *pp) | |
623 | { | |
624 | void __iomem *purple_base = pp->purple_base; | |
625 | ||
626 | writel(0, purple_base + PCIE_PHY_MAC_RESET); | |
627 | writel(1, purple_base + PCIE_PHY_GLOBAL_RESET); | |
628 | } | |
629 | ||
630 | static void exynos_pcie_deassert_phy_reset(struct pcie_port *pp) | |
631 | { | |
632 | void __iomem *elbi_base = pp->elbi_base; | |
633 | void __iomem *purple_base = pp->purple_base; | |
634 | ||
635 | writel(0, purple_base + PCIE_PHY_GLOBAL_RESET); | |
636 | writel(1, elbi_base + PCIE_PWR_RESET); | |
637 | writel(0, purple_base + PCIE_PHY_COMMON_RESET); | |
638 | writel(0, purple_base + PCIE_PHY_CMN_REG); | |
639 | writel(0, purple_base + PCIE_PHY_TRSVREG_RESET); | |
640 | writel(0, purple_base + PCIE_PHY_TRSV_RESET); | |
641 | } | |
642 | ||
643 | static void exynos_pcie_init_phy(struct pcie_port *pp) | |
644 | { | |
645 | void __iomem *phy_base = pp->phy_base; | |
646 | ||
647 | /* DCC feedback control off */ | |
648 | writel(0x29, phy_base + PCIE_PHY_DCC_FEEDBACK); | |
649 | ||
650 | /* set TX/RX impedance */ | |
651 | writel(0xd5, phy_base + PCIE_PHY_IMPEDANCE); | |
652 | ||
653 | /* set 50Mhz PHY clock */ | |
654 | writel(0x14, phy_base + PCIE_PHY_PLL_DIV_0); | |
655 | writel(0x12, phy_base + PCIE_PHY_PLL_DIV_1); | |
656 | ||
657 | /* set TX Differential output for lane 0 */ | |
658 | writel(0x7f, phy_base + PCIE_PHY_TRSV0_DRV_LVL); | |
659 | ||
660 | /* set TX Pre-emphasis Level Control for lane 0 to minimum */ | |
661 | writel(0x0, phy_base + PCIE_PHY_TRSV0_EMP_LVL); | |
662 | ||
663 | /* set RX clock and data recovery bandwidth */ | |
664 | writel(0xe7, phy_base + PCIE_PHY_PLL_BIAS); | |
665 | writel(0x82, phy_base + PCIE_PHY_TRSV0_RXCDR); | |
666 | writel(0x82, phy_base + PCIE_PHY_TRSV1_RXCDR); | |
667 | writel(0x82, phy_base + PCIE_PHY_TRSV2_RXCDR); | |
668 | writel(0x82, phy_base + PCIE_PHY_TRSV3_RXCDR); | |
669 | ||
670 | /* change TX Pre-emphasis Level Control for lanes */ | |
671 | writel(0x39, phy_base + PCIE_PHY_TRSV0_EMP_LVL); | |
672 | writel(0x39, phy_base + PCIE_PHY_TRSV1_EMP_LVL); | |
673 | writel(0x39, phy_base + PCIE_PHY_TRSV2_EMP_LVL); | |
674 | writel(0x39, phy_base + PCIE_PHY_TRSV3_EMP_LVL); | |
675 | ||
676 | /* set LVCC */ | |
677 | writel(0x20, phy_base + PCIE_PHY_TRSV0_LVCC); | |
678 | writel(0xa0, phy_base + PCIE_PHY_TRSV1_LVCC); | |
679 | writel(0xa0, phy_base + PCIE_PHY_TRSV2_LVCC); | |
680 | writel(0xa0, phy_base + PCIE_PHY_TRSV3_LVCC); | |
681 | } | |
682 | ||
683 | static void exynos_pcie_assert_reset(struct pcie_port *pp) | |
684 | { | |
685 | if (pp->reset_gpio >= 0) | |
686 | devm_gpio_request_one(pp->dev, pp->reset_gpio, | |
687 | GPIOF_OUT_INIT_HIGH, "RESET"); | |
688 | return; | |
689 | } | |
690 | ||
691 | static int exynos_pcie_establish_link(struct pcie_port *pp) | |
692 | { | |
693 | u32 val; | |
694 | int count = 0; | |
695 | void __iomem *elbi_base = pp->elbi_base; | |
696 | void __iomem *purple_base = pp->purple_base; | |
697 | void __iomem *phy_base = pp->phy_base; | |
698 | ||
699 | if (exynos_pcie_link_up(pp)) { | |
700 | dev_err(pp->dev, "Link already up\n"); | |
701 | return 0; | |
702 | } | |
703 | ||
704 | /* assert reset signals */ | |
705 | exynos_pcie_assert_core_reset(pp); | |
706 | exynos_pcie_assert_phy_reset(pp); | |
707 | ||
708 | /* de-assert phy reset */ | |
709 | exynos_pcie_deassert_phy_reset(pp); | |
710 | ||
711 | /* initialize phy */ | |
712 | exynos_pcie_init_phy(pp); | |
713 | ||
714 | /* pulse for common reset */ | |
715 | writel(1, purple_base + PCIE_PHY_COMMON_RESET); | |
716 | udelay(500); | |
717 | writel(0, purple_base + PCIE_PHY_COMMON_RESET); | |
718 | ||
719 | /* de-assert core reset */ | |
720 | exynos_pcie_deassert_core_reset(pp); | |
721 | ||
722 | /* setup root complex */ | |
723 | exynos_pcie_setup_rc(pp); | |
724 | ||
725 | /* assert reset signal */ | |
726 | exynos_pcie_assert_reset(pp); | |
727 | ||
728 | /* assert LTSSM enable */ | |
729 | writel(PCIE_ELBI_LTSSM_ENABLE, elbi_base + PCIE_APP_LTSSM_ENABLE); | |
730 | ||
731 | /* check if the link is up or not */ | |
732 | while (!exynos_pcie_link_up(pp)) { | |
733 | mdelay(100); | |
734 | count++; | |
735 | if (count == 10) { | |
736 | while (readl(phy_base + PCIE_PHY_PLL_LOCKED) == 0) { | |
737 | val = readl(purple_base + PCIE_PHY_PLL_LOCKED); | |
738 | dev_info(pp->dev, "PLL Locked: 0x%x\n", val); | |
739 | } | |
740 | dev_err(pp->dev, "PCIe Link Fail\n"); | |
741 | return -EINVAL; | |
742 | } | |
743 | } | |
744 | ||
745 | dev_info(pp->dev, "Link up\n"); | |
746 | ||
747 | return 0; | |
748 | } | |
749 | ||
750 | static void exynos_pcie_clear_irq_pulse(struct pcie_port *pp) | |
751 | { | |
752 | u32 val; | |
753 | void __iomem *elbi_base = pp->elbi_base; | |
754 | ||
755 | val = readl(elbi_base + PCIE_IRQ_PULSE); | |
756 | writel(val, elbi_base + PCIE_IRQ_PULSE); | |
757 | return; | |
758 | } | |
759 | ||
760 | static void exynos_pcie_enable_irq_pulse(struct pcie_port *pp) | |
761 | { | |
762 | u32 val; | |
763 | void __iomem *elbi_base = pp->elbi_base; | |
764 | ||
765 | /* enable INTX interrupt */ | |
766 | val = IRQ_INTA_ASSERT | IRQ_INTB_ASSERT | | |
767 | IRQ_INTC_ASSERT | IRQ_INTD_ASSERT, | |
768 | writel(val, elbi_base + PCIE_IRQ_EN_PULSE); | |
769 | return; | |
770 | } | |
771 | ||
772 | static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg) | |
773 | { | |
774 | struct pcie_port *pp = arg; | |
775 | ||
776 | exynos_pcie_clear_irq_pulse(pp); | |
777 | return IRQ_HANDLED; | |
778 | } | |
779 | ||
780 | static void exynos_pcie_enable_interrupts(struct pcie_port *pp) | |
781 | { | |
782 | exynos_pcie_enable_irq_pulse(pp); | |
783 | return; | |
784 | } | |
785 | ||
786 | static void exynos_pcie_host_init(struct pcie_port *pp) | |
787 | { | |
788 | struct pcie_port_info *config = &pp->config; | |
789 | u32 val; | |
790 | ||
791 | /* Keep first 64K for IO */ | |
792 | pp->cfg0_base = pp->cfg.start; | |
793 | pp->cfg1_base = pp->cfg.start + config->cfg0_size; | |
794 | pp->io_base = pp->io.start; | |
795 | pp->mem_base = pp->mem.start; | |
796 | ||
797 | /* enable link */ | |
798 | exynos_pcie_establish_link(pp); | |
799 | ||
800 | exynos_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0); | |
801 | ||
802 | /* program correct class for RC */ | |
803 | exynos_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI); | |
804 | ||
805 | exynos_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val); | |
806 | val |= PORT_LOGIC_SPEED_CHANGE; | |
807 | exynos_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val); | |
808 | ||
809 | exynos_pcie_enable_interrupts(pp); | |
810 | } | |
811 | ||
812 | static int add_pcie_port(struct pcie_port *pp, struct platform_device *pdev) | |
813 | { | |
814 | struct resource *elbi_base; | |
815 | struct resource *phy_base; | |
816 | struct resource *purple_base; | |
817 | int ret; | |
818 | ||
819 | elbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
820 | if (!elbi_base) { | |
821 | dev_err(&pdev->dev, "couldn't get elbi base resource\n"); | |
822 | return -EINVAL; | |
823 | } | |
824 | pp->elbi_base = devm_ioremap_resource(&pdev->dev, elbi_base); | |
825 | if (IS_ERR(pp->elbi_base)) | |
826 | return PTR_ERR(pp->elbi_base); | |
827 | ||
828 | phy_base = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
829 | if (!phy_base) { | |
830 | dev_err(&pdev->dev, "couldn't get phy base resource\n"); | |
831 | return -EINVAL; | |
832 | } | |
833 | pp->phy_base = devm_ioremap_resource(&pdev->dev, phy_base); | |
834 | if (IS_ERR(pp->phy_base)) | |
835 | return PTR_ERR(pp->phy_base); | |
836 | ||
837 | purple_base = platform_get_resource(pdev, IORESOURCE_MEM, 2); | |
838 | if (!purple_base) { | |
839 | dev_err(&pdev->dev, "couldn't get purple base resource\n"); | |
840 | return -EINVAL; | |
841 | } | |
842 | pp->purple_base = devm_ioremap_resource(&pdev->dev, purple_base); | |
843 | if (IS_ERR(pp->purple_base)) | |
844 | return PTR_ERR(pp->purple_base); | |
845 | ||
846 | pp->irq = platform_get_irq(pdev, 1); | |
847 | if (!pp->irq) { | |
848 | dev_err(&pdev->dev, "failed to get irq\n"); | |
849 | return -ENODEV; | |
850 | } | |
851 | ret = devm_request_irq(&pdev->dev, pp->irq, exynos_pcie_irq_handler, | |
852 | IRQF_SHARED, "exynos-pcie", pp); | |
853 | if (ret) { | |
854 | dev_err(&pdev->dev, "failed to request irq\n"); | |
855 | return ret; | |
856 | } | |
857 | ||
858 | pp->dbi_base = devm_ioremap(&pdev->dev, pp->cfg.start, | |
859 | resource_size(&pp->cfg)); | |
860 | if (!pp->dbi_base) { | |
861 | dev_err(&pdev->dev, "error with ioremap\n"); | |
862 | return -ENOMEM; | |
863 | } | |
864 | ||
865 | pp->root_bus_nr = -1; | |
866 | ||
867 | spin_lock_init(&pp->conf_lock); | |
868 | exynos_pcie_host_init(pp); | |
869 | pp->va_cfg0_base = devm_ioremap(&pdev->dev, pp->cfg0_base, | |
870 | pp->config.cfg0_size); | |
871 | if (!pp->va_cfg0_base) { | |
872 | dev_err(pp->dev, "error with ioremap in function\n"); | |
873 | return -ENOMEM; | |
874 | } | |
875 | pp->va_cfg1_base = devm_ioremap(&pdev->dev, pp->cfg1_base, | |
876 | pp->config.cfg1_size); | |
877 | if (!pp->va_cfg1_base) { | |
878 | dev_err(pp->dev, "error with ioremap\n"); | |
879 | return -ENOMEM; | |
880 | } | |
881 | ||
882 | return 0; | |
883 | } | |
884 | ||
885 | static int __init exynos_pcie_probe(struct platform_device *pdev) | |
886 | { | |
887 | struct pcie_port *pp; | |
888 | struct device_node *np = pdev->dev.of_node; | |
889 | struct of_pci_range range; | |
890 | struct of_pci_range_parser parser; | |
891 | int ret; | |
892 | ||
893 | pp = devm_kzalloc(&pdev->dev, sizeof(*pp), GFP_KERNEL); | |
894 | if (!pp) { | |
895 | dev_err(&pdev->dev, "no memory for pcie port\n"); | |
896 | return -ENOMEM; | |
897 | } | |
898 | ||
899 | pp->dev = &pdev->dev; | |
900 | ||
901 | if (of_pci_range_parser_init(&parser, np)) { | |
902 | dev_err(&pdev->dev, "missing ranges property\n"); | |
903 | return -EINVAL; | |
904 | } | |
905 | ||
906 | /* Get the I/O and memory ranges from DT */ | |
907 | for_each_of_pci_range(&parser, &range) { | |
908 | unsigned long restype = range.flags & IORESOURCE_TYPE_BITS; | |
909 | if (restype == IORESOURCE_IO) { | |
910 | of_pci_range_to_resource(&range, np, &pp->io); | |
911 | pp->io.name = "I/O"; | |
912 | pp->io.start = max_t(resource_size_t, | |
913 | PCIBIOS_MIN_IO, | |
914 | range.pci_addr + global_io_offset); | |
915 | pp->io.end = min_t(resource_size_t, | |
916 | IO_SPACE_LIMIT, | |
917 | range.pci_addr + range.size | |
918 | + global_io_offset); | |
919 | pp->config.io_size = resource_size(&pp->io); | |
920 | pp->config.io_bus_addr = range.pci_addr; | |
921 | } | |
922 | if (restype == IORESOURCE_MEM) { | |
923 | of_pci_range_to_resource(&range, np, &pp->mem); | |
924 | pp->mem.name = "MEM"; | |
925 | pp->config.mem_size = resource_size(&pp->mem); | |
926 | pp->config.mem_bus_addr = range.pci_addr; | |
927 | } | |
928 | if (restype == 0) { | |
929 | of_pci_range_to_resource(&range, np, &pp->cfg); | |
930 | pp->config.cfg0_size = resource_size(&pp->cfg)/2; | |
931 | pp->config.cfg1_size = resource_size(&pp->cfg)/2; | |
932 | } | |
933 | } | |
934 | ||
935 | pp->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0); | |
936 | ||
937 | pp->clk = devm_clk_get(&pdev->dev, "pcie"); | |
938 | if (IS_ERR(pp->clk)) { | |
939 | dev_err(&pdev->dev, "Failed to get pcie rc clock\n"); | |
940 | return PTR_ERR(pp->clk); | |
941 | } | |
942 | ret = clk_prepare_enable(pp->clk); | |
943 | if (ret) | |
944 | return ret; | |
945 | ||
946 | pp->bus_clk = devm_clk_get(&pdev->dev, "pcie_bus"); | |
947 | if (IS_ERR(pp->bus_clk)) { | |
948 | dev_err(&pdev->dev, "Failed to get pcie bus clock\n"); | |
949 | ret = PTR_ERR(pp->bus_clk); | |
950 | goto fail_clk; | |
951 | } | |
952 | ret = clk_prepare_enable(pp->bus_clk); | |
953 | if (ret) | |
954 | goto fail_clk; | |
955 | ||
956 | ret = add_pcie_port(pp, pdev); | |
957 | if (ret < 0) | |
958 | goto fail_bus_clk; | |
959 | ||
960 | pp->controller = exynos_pci.nr_controllers; | |
961 | exynos_pci.nr_controllers = 1; | |
962 | exynos_pci.private_data = (void **)&pp; | |
963 | ||
964 | pci_common_init(&exynos_pci); | |
965 | pci_assign_unassigned_resources(); | |
966 | #ifdef CONFIG_PCI_DOMAINS | |
967 | exynos_pci.domain++; | |
968 | #endif | |
969 | ||
970 | platform_set_drvdata(pdev, pp); | |
971 | return 0; | |
972 | ||
973 | fail_bus_clk: | |
974 | clk_disable_unprepare(pp->bus_clk); | |
975 | fail_clk: | |
976 | clk_disable_unprepare(pp->clk); | |
977 | return ret; | |
978 | } | |
979 | ||
980 | static int __exit exynos_pcie_remove(struct platform_device *pdev) | |
981 | { | |
982 | struct pcie_port *pp = platform_get_drvdata(pdev); | |
983 | ||
984 | clk_disable_unprepare(pp->bus_clk); | |
985 | clk_disable_unprepare(pp->clk); | |
986 | ||
987 | return 0; | |
988 | } | |
989 | ||
990 | static const struct of_device_id exynos_pcie_of_match[] = { | |
991 | { .compatible = "samsung,exynos5440-pcie", }, | |
992 | {}, | |
993 | }; | |
994 | MODULE_DEVICE_TABLE(of, exynos_pcie_of_match); | |
995 | ||
996 | static struct platform_driver exynos_pcie_driver = { | |
997 | .remove = __exit_p(exynos_pcie_remove), | |
998 | .driver = { | |
999 | .name = "exynos-pcie", | |
1000 | .owner = THIS_MODULE, | |
1001 | .of_match_table = of_match_ptr(exynos_pcie_of_match), | |
1002 | }, | |
1003 | }; | |
1004 | ||
1005 | static int exynos_pcie_abort(unsigned long addr, unsigned int fsr, | |
1006 | struct pt_regs *regs) | |
1007 | { | |
1008 | unsigned long pc = instruction_pointer(regs); | |
1009 | unsigned long instr = *(unsigned long *)pc; | |
1010 | ||
1011 | WARN_ONCE(1, "pcie abort\n"); | |
1012 | ||
1013 | /* | |
1014 | * If the instruction being executed was a read, | |
1015 | * make it look like it read all-ones. | |
1016 | */ | |
1017 | if ((instr & 0x0c100000) == 0x04100000) { | |
1018 | int reg = (instr >> 12) & 15; | |
1019 | unsigned long val; | |
1020 | ||
1021 | if (instr & 0x00400000) | |
1022 | val = 255; | |
1023 | else | |
1024 | val = -1; | |
1025 | ||
1026 | regs->uregs[reg] = val; | |
1027 | regs->ARM_pc += 4; | |
1028 | return 0; | |
1029 | } | |
1030 | ||
1031 | if ((instr & 0x0e100090) == 0x00100090) { | |
1032 | int reg = (instr >> 12) & 15; | |
1033 | ||
1034 | regs->uregs[reg] = -1; | |
1035 | regs->ARM_pc += 4; | |
1036 | return 0; | |
1037 | } | |
1038 | ||
1039 | return 1; | |
1040 | } | |
1041 | ||
1042 | /* Exynos PCIe driver does not allow module unload */ | |
1043 | ||
1044 | static int __init pcie_init(void) | |
1045 | { | |
1046 | hook_fault_code(16 + 6, exynos_pcie_abort, SIGBUS, 0, | |
1047 | "imprecise external abort"); | |
1048 | ||
1049 | platform_driver_probe(&exynos_pcie_driver, exynos_pcie_probe); | |
1050 | ||
1051 | return 0; | |
1052 | } | |
1053 | subsys_initcall(pcie_init); | |
1054 | ||
1055 | MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>"); | |
1056 | MODULE_DESCRIPTION("Samsung PCIe host controller driver"); | |
1057 | MODULE_LICENSE("GPL v2"); |