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1da177e4 LT |
1 | /* |
2 | * PCI Express Hot Plug Controller Driver | |
3 | * | |
4 | * Copyright (C) 1995,2001 Compaq Computer Corporation | |
5 | * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) | |
6 | * Copyright (C) 2001 IBM Corp. | |
7 | * Copyright (C) 2003-2004 Intel Corporation | |
8 | * | |
9 | * All rights reserved. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or (at | |
14 | * your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
19 | * NON INFRINGEMENT. See the GNU General Public License for more | |
20 | * details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * | |
8cf4c195 | 26 | * Send feedback to <greg@kroah.com>, <kristen.c.accardi@intel.com> |
1da177e4 LT |
27 | * |
28 | */ | |
29 | #ifndef _PCIEHP_H | |
30 | #define _PCIEHP_H | |
31 | ||
32 | #include <linux/types.h> | |
33 | #include <linux/pci.h> | |
7a54f25c | 34 | #include <linux/pci_hotplug.h> |
1da177e4 | 35 | #include <linux/delay.h> |
de25968c | 36 | #include <linux/sched.h> /* signal_pending() */ |
1da177e4 | 37 | #include <linux/pcieport_if.h> |
6aa4cdd0 | 38 | #include <linux/mutex.h> |
1da177e4 LT |
39 | |
40 | #define MY_NAME "pciehp" | |
41 | ||
42 | extern int pciehp_poll_mode; | |
43 | extern int pciehp_poll_time; | |
44 | extern int pciehp_debug; | |
a3a45ec8 | 45 | extern int pciehp_force; |
1da177e4 LT |
46 | |
47 | /*#define dbg(format, arg...) do { if (pciehp_debug) printk(KERN_DEBUG "%s: " format, MY_NAME , ## arg); } while (0)*/ | |
48 | #define dbg(format, arg...) do { if (pciehp_debug) printk("%s: " format, MY_NAME , ## arg); } while (0) | |
49 | #define err(format, arg...) printk(KERN_ERR "%s: " format, MY_NAME , ## arg) | |
50 | #define info(format, arg...) printk(KERN_INFO "%s: " format, MY_NAME , ## arg) | |
51 | #define warn(format, arg...) printk(KERN_WARNING "%s: " format, MY_NAME , ## arg) | |
52 | ||
a8a2be94 | 53 | |
1da177e4 LT |
54 | struct slot { |
55 | struct slot *next; | |
56 | u8 bus; | |
57 | u8 device; | |
58 | u32 number; | |
1da177e4 | 59 | u8 state; |
1da177e4 LT |
60 | struct timer_list task_event; |
61 | u8 hp_slot; | |
62 | struct controller *ctrl; | |
63 | struct hpc_ops *hpc_ops; | |
64 | struct hotplug_slot *hotplug_slot; | |
65 | struct list_head slot_list; | |
66 | }; | |
67 | ||
1da177e4 LT |
68 | struct event_info { |
69 | u32 event_type; | |
70 | u8 hp_slot; | |
71 | }; | |
72 | ||
ed6cbcf2 | 73 | typedef u8(*php_intr_callback_t) (u8 hp_slot, void *instance_id); |
74 | ||
75 | struct php_ctlr_state_s { | |
76 | struct php_ctlr_state_s *pnext; | |
77 | struct pci_dev *pci_dev; | |
78 | unsigned int irq; | |
79 | unsigned long flags; /* spinlock's */ | |
80 | u32 slot_device_offset; | |
81 | u32 num_slots; | |
82 | struct timer_list int_poll_timer; /* Added for poll event */ | |
83 | php_intr_callback_t attention_button_callback; | |
84 | php_intr_callback_t switch_change_callback; | |
85 | php_intr_callback_t presence_change_callback; | |
86 | php_intr_callback_t power_fault_callback; | |
87 | void *callback_instance_id; | |
88 | struct ctrl_reg *creg; /* Ptr to controller register space */ | |
89 | }; | |
90 | ||
91 | #define MAX_EVENTS 10 | |
1da177e4 LT |
92 | struct controller { |
93 | struct controller *next; | |
6aa4cdd0 | 94 | struct mutex crit_sect; /* critical section mutex */ |
dd5619cb | 95 | struct mutex ctrl_lock; /* controller lock */ |
ed6cbcf2 | 96 | struct php_ctlr_state_s *hpc_ctlr_handle; /* HPC controller handle */ |
1da177e4 LT |
97 | int num_slots; /* Number of slots on ctlr */ |
98 | int slot_num_inc; /* 1 or -1 */ | |
1da177e4 LT |
99 | struct pci_dev *pci_dev; |
100 | struct pci_bus *pci_bus; | |
ed6cbcf2 | 101 | struct event_info event_queue[MAX_EVENTS]; |
1da177e4 LT |
102 | struct slot *slot; |
103 | struct hpc_ops *hpc_ops; | |
104 | wait_queue_head_t queue; /* sleep & wake process */ | |
105 | u8 next_event; | |
1da177e4 LT |
106 | u8 bus; |
107 | u8 device; | |
108 | u8 function; | |
1da177e4 | 109 | u8 slot_device_offset; |
1da177e4 LT |
110 | u32 first_slot; /* First physical slot number */ /* PCIE only has 1 slot */ |
111 | u8 slot_bus; /* Bus where the slots handled by this controller sit */ | |
112 | u8 ctrlcap; | |
113 | u16 vendor_id; | |
8b245e45 | 114 | u8 cap_base; |
1da177e4 LT |
115 | }; |
116 | ||
1da177e4 LT |
117 | #define INT_BUTTON_IGNORE 0 |
118 | #define INT_PRESENCE_ON 1 | |
119 | #define INT_PRESENCE_OFF 2 | |
120 | #define INT_SWITCH_CLOSE 3 | |
121 | #define INT_SWITCH_OPEN 4 | |
122 | #define INT_POWER_FAULT 5 | |
123 | #define INT_POWER_FAULT_CLEAR 6 | |
124 | #define INT_BUTTON_PRESS 7 | |
125 | #define INT_BUTTON_RELEASE 8 | |
126 | #define INT_BUTTON_CANCEL 9 | |
127 | ||
128 | #define STATIC_STATE 0 | |
129 | #define BLINKINGON_STATE 1 | |
130 | #define BLINKINGOFF_STATE 2 | |
131 | #define POWERON_STATE 3 | |
132 | #define POWEROFF_STATE 4 | |
133 | ||
134 | #define PCI_TO_PCI_BRIDGE_CLASS 0x00060400 | |
135 | ||
136 | /* Error messages */ | |
137 | #define INTERLOCK_OPEN 0x00000002 | |
138 | #define ADD_NOT_SUPPORTED 0x00000003 | |
139 | #define CARD_FUNCTIONING 0x00000005 | |
140 | #define ADAPTER_NOT_SAME 0x00000006 | |
141 | #define NO_ADAPTER_PRESENT 0x00000009 | |
142 | #define NOT_ENOUGH_RESOURCES 0x0000000B | |
143 | #define DEVICE_TYPE_NOT_SUPPORTED 0x0000000C | |
144 | #define WRONG_BUS_FREQUENCY 0x0000000D | |
145 | #define POWER_FAILURE 0x0000000E | |
146 | ||
147 | #define REMOVE_NOT_SUPPORTED 0x00000003 | |
148 | ||
149 | #define DISABLE_CARD 1 | |
150 | ||
151 | /* Field definitions in Slot Capabilities Register */ | |
152 | #define ATTN_BUTTN_PRSN 0x00000001 | |
153 | #define PWR_CTRL_PRSN 0x00000002 | |
154 | #define MRL_SENS_PRSN 0x00000004 | |
155 | #define ATTN_LED_PRSN 0x00000008 | |
156 | #define PWR_LED_PRSN 0x00000010 | |
157 | #define HP_SUPR_RM_SUP 0x00000020 | |
158 | ||
159 | #define ATTN_BUTTN(cap) (cap & ATTN_BUTTN_PRSN) | |
160 | #define POWER_CTRL(cap) (cap & PWR_CTRL_PRSN) | |
161 | #define MRL_SENS(cap) (cap & MRL_SENS_PRSN) | |
162 | #define ATTN_LED(cap) (cap & ATTN_LED_PRSN) | |
163 | #define PWR_LED(cap) (cap & PWR_LED_PRSN) | |
164 | #define HP_SUPR_RM(cap) (cap & HP_SUPR_RM_SUP) | |
165 | ||
166 | /* | |
167 | * error Messages | |
168 | */ | |
169 | #define msg_initialization_err "Initialization failure, error=%d\n" | |
49ed2b49 KK |
170 | #define msg_button_on "PCI slot #%s - powering on due to button press.\n" |
171 | #define msg_button_off "PCI slot #%s - powering off due to button press.\n" | |
172 | #define msg_button_cancel "PCI slot #%s - action canceled due to button press.\n" | |
173 | #define msg_button_ignore "PCI slot #%s - button press ignored. (action in progress...)\n" | |
1da177e4 LT |
174 | |
175 | /* controller functions */ | |
1da177e4 LT |
176 | extern int pciehp_event_start_thread (void); |
177 | extern void pciehp_event_stop_thread (void); | |
1da177e4 LT |
178 | extern int pciehp_enable_slot (struct slot *slot); |
179 | extern int pciehp_disable_slot (struct slot *slot); | |
180 | ||
181 | extern u8 pciehp_handle_attention_button (u8 hp_slot, void *inst_id); | |
182 | extern u8 pciehp_handle_switch_change (u8 hp_slot, void *inst_id); | |
183 | extern u8 pciehp_handle_presence_change (u8 hp_slot, void *inst_id); | |
184 | extern u8 pciehp_handle_power_fault (u8 hp_slot, void *inst_id); | |
185 | /* extern void long_delay (int delay); */ | |
186 | ||
1da177e4 | 187 | /* pci functions */ |
ca22a5e4 | 188 | extern int pciehp_configure_device (struct slot *p_slot); |
189 | extern int pciehp_unconfigure_device (struct slot *p_slot); | |
a8a2be94 | 190 | |
1da177e4 LT |
191 | |
192 | ||
193 | /* Global variables */ | |
194 | extern struct controller *pciehp_ctrl_list; | |
1da177e4 LT |
195 | |
196 | /* Inline functions */ | |
197 | ||
198 | static inline struct slot *pciehp_find_slot(struct controller *ctrl, u8 device) | |
199 | { | |
200 | struct slot *p_slot, *tmp_slot = NULL; | |
201 | ||
202 | p_slot = ctrl->slot; | |
203 | ||
1da177e4 LT |
204 | while (p_slot && (p_slot->device != device)) { |
205 | tmp_slot = p_slot; | |
206 | p_slot = p_slot->next; | |
1da177e4 LT |
207 | } |
208 | if (p_slot == NULL) { | |
209 | err("ERROR: pciehp_find_slot device=0x%x\n", device); | |
210 | p_slot = tmp_slot; | |
211 | } | |
212 | ||
213 | return p_slot; | |
214 | } | |
215 | ||
216 | static inline int wait_for_ctrl_irq(struct controller *ctrl) | |
217 | { | |
218 | int retval = 0; | |
219 | ||
220 | DECLARE_WAITQUEUE(wait, current); | |
221 | ||
1da177e4 LT |
222 | add_wait_queue(&ctrl->queue, &wait); |
223 | if (!pciehp_poll_mode) | |
224 | /* Sleep for up to 1 second */ | |
225 | msleep_interruptible(1000); | |
226 | else | |
227 | msleep_interruptible(2500); | |
228 | ||
229 | remove_wait_queue(&ctrl->queue, &wait); | |
230 | if (signal_pending(current)) | |
231 | retval = -EINTR; | |
232 | ||
1da177e4 LT |
233 | return retval; |
234 | } | |
235 | ||
1da177e4 LT |
236 | #define SLOT_NAME_SIZE 10 |
237 | ||
238 | static inline void make_slot_name(char *buffer, int buffer_size, struct slot *slot) | |
239 | { | |
1248d636 | 240 | snprintf(buffer, buffer_size, "%04d_%04d", slot->bus, slot->number); |
1da177e4 LT |
241 | } |
242 | ||
243 | enum php_ctlr_type { | |
244 | PCI, | |
245 | ISA, | |
246 | ACPI | |
247 | }; | |
248 | ||
ed6cbcf2 | 249 | int pcie_init(struct controller *ctrl, struct pcie_device *dev); |
1da177e4 LT |
250 | |
251 | /* This has no meaning for PCI Express, as there is only 1 slot per port */ | |
252 | int pcie_get_ctlr_slot_config(struct controller *ctrl, | |
253 | int *num_ctlr_slots, | |
254 | int *first_device_num, | |
255 | int *physical_slot_num, | |
256 | u8 *ctrlcap); | |
257 | ||
258 | struct hpc_ops { | |
259 | int (*power_on_slot) (struct slot *slot); | |
260 | int (*power_off_slot) (struct slot *slot); | |
261 | int (*get_power_status) (struct slot *slot, u8 *status); | |
262 | int (*get_attention_status) (struct slot *slot, u8 *status); | |
263 | int (*set_attention_status) (struct slot *slot, u8 status); | |
264 | int (*get_latch_status) (struct slot *slot, u8 *status); | |
265 | int (*get_adapter_status) (struct slot *slot, u8 *status); | |
266 | ||
267 | int (*get_max_bus_speed) (struct slot *slot, enum pci_bus_speed *speed); | |
268 | int (*get_cur_bus_speed) (struct slot *slot, enum pci_bus_speed *speed); | |
269 | ||
270 | int (*get_max_lnk_width) (struct slot *slot, enum pcie_link_width *value); | |
271 | int (*get_cur_lnk_width) (struct slot *slot, enum pcie_link_width *value); | |
272 | ||
273 | int (*query_power_fault) (struct slot *slot); | |
274 | void (*green_led_on) (struct slot *slot); | |
275 | void (*green_led_off) (struct slot *slot); | |
276 | void (*green_led_blink) (struct slot *slot); | |
277 | void (*release_ctlr) (struct controller *ctrl); | |
278 | int (*check_lnk_status) (struct controller *ctrl); | |
279 | }; | |
280 | ||
783c49fc KA |
281 | |
282 | #ifdef CONFIG_ACPI | |
e50d1088 KCA |
283 | #include <acpi/acpi.h> |
284 | #include <acpi/acpi_bus.h> | |
285 | #include <acpi/actypes.h> | |
286 | #include <linux/pci-acpi.h> | |
287 | ||
783c49fc KA |
288 | #define pciehp_get_hp_hw_control_from_firmware(dev) \ |
289 | pciehp_acpi_get_hp_hw_control_from_firmware(dev) | |
290 | static inline int pciehp_get_hp_params_from_firmware(struct pci_dev *dev, | |
291 | struct hotplug_params *hpp) | |
292 | { | |
7430e34c | 293 | if (ACPI_FAILURE(acpi_get_hp_params_from_firmware(dev->bus, hpp))) |
783c49fc KA |
294 | return -ENODEV; |
295 | return 0; | |
296 | } | |
297 | #else | |
298 | #define pciehp_get_hp_hw_control_from_firmware(dev) 0 | |
299 | #define pciehp_get_hp_params_from_firmware(dev, hpp) (-ENODEV) | |
300 | #endif /* CONFIG_ACPI */ | |
1da177e4 | 301 | #endif /* _PCIEHP_H */ |