Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * PCI Express PCI Hot Plug Driver | |
3 | * | |
4 | * Copyright (C) 1995,2001 Compaq Computer Corporation | |
5 | * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) | |
6 | * Copyright (C) 2001 IBM Corp. | |
7 | * Copyright (C) 2003-2004 Intel Corporation | |
8 | * | |
9 | * All rights reserved. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or (at | |
14 | * your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
19 | * NON INFRINGEMENT. See the GNU General Public License for more | |
20 | * details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * | |
8cf4c195 | 26 | * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> |
1da177e4 LT |
27 | * |
28 | */ | |
29 | ||
1da177e4 LT |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
32 | #include <linux/types.h> | |
de25968c TS |
33 | #include <linux/signal.h> |
34 | #include <linux/jiffies.h> | |
35 | #include <linux/timer.h> | |
1da177e4 | 36 | #include <linux/pci.h> |
5d1b8c9e | 37 | #include <linux/interrupt.h> |
34d03419 | 38 | #include <linux/time.h> |
5a0e3ad6 | 39 | #include <linux/slab.h> |
5d1b8c9e | 40 | |
1da177e4 LT |
41 | #include "../pci.h" |
42 | #include "pciehp.h" | |
1da177e4 | 43 | |
cd84d340 | 44 | static inline struct pci_dev *ctrl_dev(struct controller *ctrl) |
a0f018da | 45 | { |
cd84d340 | 46 | return ctrl->pcie->port; |
a0f018da | 47 | } |
1da177e4 | 48 | |
48fe3915 KK |
49 | static irqreturn_t pcie_isr(int irq, void *dev_id); |
50 | static void start_int_poll_timer(struct controller *ctrl, int sec); | |
1da177e4 LT |
51 | |
52 | /* This is the interrupt polling timeout function. */ | |
48fe3915 | 53 | static void int_poll_timeout(unsigned long data) |
1da177e4 | 54 | { |
48fe3915 | 55 | struct controller *ctrl = (struct controller *)data; |
1da177e4 | 56 | |
1da177e4 | 57 | /* Poll for interrupt events. regs == NULL => polling */ |
48fe3915 | 58 | pcie_isr(0, ctrl); |
1da177e4 | 59 | |
48fe3915 | 60 | init_timer(&ctrl->poll_timer); |
1da177e4 | 61 | if (!pciehp_poll_time) |
40730d10 | 62 | pciehp_poll_time = 2; /* default polling interval is 2 sec */ |
1da177e4 | 63 | |
48fe3915 | 64 | start_int_poll_timer(ctrl, pciehp_poll_time); |
1da177e4 LT |
65 | } |
66 | ||
67 | /* This function starts the interrupt polling timer. */ | |
48fe3915 | 68 | static void start_int_poll_timer(struct controller *ctrl, int sec) |
1da177e4 | 69 | { |
48fe3915 KK |
70 | /* Clamp to sane value */ |
71 | if ((sec <= 0) || (sec > 60)) | |
f7625980 | 72 | sec = 2; |
48fe3915 KK |
73 | |
74 | ctrl->poll_timer.function = &int_poll_timeout; | |
75 | ctrl->poll_timer.data = (unsigned long)ctrl; | |
76 | ctrl->poll_timer.expires = jiffies + sec * HZ; | |
77 | add_timer(&ctrl->poll_timer); | |
1da177e4 LT |
78 | } |
79 | ||
2aeeef11 KK |
80 | static inline int pciehp_request_irq(struct controller *ctrl) |
81 | { | |
f7a10e32 | 82 | int retval, irq = ctrl->pcie->irq; |
2aeeef11 KK |
83 | |
84 | /* Install interrupt polling timer. Start with 10 sec delay */ | |
85 | if (pciehp_poll_mode) { | |
86 | init_timer(&ctrl->poll_timer); | |
87 | start_int_poll_timer(ctrl, 10); | |
88 | return 0; | |
89 | } | |
90 | ||
91 | /* Installs the interrupt handler */ | |
92 | retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl); | |
93 | if (retval) | |
7f2feec1 TI |
94 | ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n", |
95 | irq); | |
2aeeef11 KK |
96 | return retval; |
97 | } | |
98 | ||
99 | static inline void pciehp_free_irq(struct controller *ctrl) | |
100 | { | |
101 | if (pciehp_poll_mode) | |
102 | del_timer_sync(&ctrl->poll_timer); | |
103 | else | |
f7a10e32 | 104 | free_irq(ctrl->pcie->irq, ctrl); |
2aeeef11 KK |
105 | } |
106 | ||
40b96083 | 107 | static int pcie_poll_cmd(struct controller *ctrl, int timeout) |
6592e02a | 108 | { |
cd84d340 | 109 | struct pci_dev *pdev = ctrl_dev(ctrl); |
6592e02a | 110 | u16 slot_status; |
6592e02a | 111 | |
ac10836b | 112 | while (true) { |
1a84b99c | 113 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); |
1469d17d JW |
114 | if (slot_status == (u16) ~0) { |
115 | ctrl_info(ctrl, "%s: no response from device\n", | |
116 | __func__); | |
117 | return 0; | |
118 | } | |
119 | ||
1a84b99c | 120 | if (slot_status & PCI_EXP_SLTSTA_CC) { |
cd84d340 BH |
121 | pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, |
122 | PCI_EXP_SLTSTA_CC); | |
322162a7 | 123 | return 1; |
820943b6 | 124 | } |
ac10836b YW |
125 | if (timeout < 0) |
126 | break; | |
127 | msleep(10); | |
128 | timeout -= 10; | |
6592e02a KK |
129 | } |
130 | return 0; /* timeout */ | |
6592e02a KK |
131 | } |
132 | ||
4283c70e | 133 | static void pcie_wait_cmd(struct controller *ctrl) |
44ef4cef | 134 | { |
262303fe | 135 | unsigned int msecs = pciehp_poll_mode ? 2500 : 1000; |
40b96083 BH |
136 | unsigned long duration = msecs_to_jiffies(msecs); |
137 | unsigned long cmd_timeout = ctrl->cmd_started + duration; | |
138 | unsigned long now, timeout; | |
262303fe KK |
139 | int rc; |
140 | ||
4283c70e BH |
141 | /* |
142 | * If the controller does not generate notifications for command | |
143 | * completions, we never need to wait between writes. | |
144 | */ | |
6c1a32e0 | 145 | if (NO_CMD_CMPL(ctrl)) |
4283c70e BH |
146 | return; |
147 | ||
148 | if (!ctrl->cmd_busy) | |
149 | return; | |
150 | ||
40b96083 BH |
151 | /* |
152 | * Even if the command has already timed out, we want to call | |
153 | * pcie_poll_cmd() so it can clear PCI_EXP_SLTSTA_CC. | |
154 | */ | |
155 | now = jiffies; | |
156 | if (time_before_eq(cmd_timeout, now)) | |
157 | timeout = 1; | |
158 | else | |
159 | timeout = cmd_timeout - now; | |
160 | ||
4283c70e BH |
161 | if (ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE && |
162 | ctrl->slot_ctrl & PCI_EXP_SLTCTL_CCIE) | |
d737bdc1 | 163 | rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout); |
4283c70e | 164 | else |
7cbeb9f9 | 165 | rc = pcie_poll_cmd(ctrl, jiffies_to_msecs(timeout)); |
40b96083 BH |
166 | |
167 | /* | |
168 | * Controllers with errata like Intel CF118 don't generate | |
169 | * completion notifications unless the power/indicator/interlock | |
170 | * control bits are changed. On such controllers, we'll emit this | |
171 | * timeout message when we wait for completion of commands that | |
172 | * don't change those bits, e.g., commands that merely enable | |
173 | * interrupts. | |
174 | */ | |
262303fe | 175 | if (!rc) |
d537a3ab | 176 | ctrl_info(ctrl, "Timeout on hotplug command %#06x (issued %u msec ago)\n", |
40b96083 | 177 | ctrl->slot_ctrl, |
d433889c | 178 | jiffies_to_msecs(jiffies - ctrl->cmd_started)); |
44ef4cef KK |
179 | } |
180 | ||
a5dd4b4b AW |
181 | static void pcie_do_write_cmd(struct controller *ctrl, u16 cmd, |
182 | u16 mask, bool wait) | |
1da177e4 | 183 | { |
cd84d340 | 184 | struct pci_dev *pdev = ctrl_dev(ctrl); |
f4778364 | 185 | u16 slot_ctrl; |
1da177e4 | 186 | |
44ef4cef KK |
187 | mutex_lock(&ctrl->ctrl_lock); |
188 | ||
a5dd4b4b AW |
189 | /* |
190 | * Always wait for any previous command that might still be in progress | |
191 | */ | |
3461a068 BH |
192 | pcie_wait_cmd(ctrl); |
193 | ||
1a84b99c | 194 | pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); |
1469d17d JW |
195 | if (slot_ctrl == (u16) ~0) { |
196 | ctrl_info(ctrl, "%s: no response from device\n", __func__); | |
197 | goto out; | |
198 | } | |
199 | ||
f4778364 | 200 | slot_ctrl &= ~mask; |
b7aa1f16 | 201 | slot_ctrl |= (cmd & mask); |
f4778364 | 202 | ctrl->cmd_busy = 1; |
2d32a9ae | 203 | smp_mb(); |
1a84b99c | 204 | pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl); |
40b96083 | 205 | ctrl->cmd_started = jiffies; |
4283c70e | 206 | ctrl->slot_ctrl = slot_ctrl; |
f4778364 | 207 | |
a5dd4b4b AW |
208 | /* |
209 | * Optionally wait for the hardware to be ready for a new command, | |
210 | * indicating completion of the above issued command. | |
211 | */ | |
212 | if (wait) | |
213 | pcie_wait_cmd(ctrl); | |
214 | ||
1469d17d | 215 | out: |
44ef4cef | 216 | mutex_unlock(&ctrl->ctrl_lock); |
1da177e4 LT |
217 | } |
218 | ||
a5dd4b4b AW |
219 | /** |
220 | * pcie_write_cmd - Issue controller command | |
221 | * @ctrl: controller to which the command is issued | |
222 | * @cmd: command value written to slot control register | |
223 | * @mask: bitmask of slot control register to be modified | |
224 | */ | |
225 | static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask) | |
226 | { | |
227 | pcie_do_write_cmd(ctrl, cmd, mask, true); | |
228 | } | |
229 | ||
230 | /* Same as above without waiting for the hardware to latch */ | |
231 | static void pcie_write_cmd_nowait(struct controller *ctrl, u16 cmd, u16 mask) | |
232 | { | |
233 | pcie_do_write_cmd(ctrl, cmd, mask, false); | |
234 | } | |
235 | ||
4703389f | 236 | bool pciehp_check_link_active(struct controller *ctrl) |
f18e9625 | 237 | { |
cd84d340 | 238 | struct pci_dev *pdev = ctrl_dev(ctrl); |
4e2ce405 | 239 | u16 lnk_status; |
1a84b99c | 240 | bool ret; |
f18e9625 | 241 | |
1a84b99c | 242 | pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status); |
4e2ce405 YL |
243 | ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA); |
244 | ||
245 | if (ret) | |
246 | ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status); | |
247 | ||
248 | return ret; | |
f18e9625 KK |
249 | } |
250 | ||
bffe4f72 | 251 | static void __pcie_wait_link_active(struct controller *ctrl, bool active) |
f18e9625 KK |
252 | { |
253 | int timeout = 1000; | |
254 | ||
4703389f | 255 | if (pciehp_check_link_active(ctrl) == active) |
f18e9625 KK |
256 | return; |
257 | while (timeout > 0) { | |
258 | msleep(10); | |
259 | timeout -= 10; | |
4703389f | 260 | if (pciehp_check_link_active(ctrl) == active) |
f18e9625 KK |
261 | return; |
262 | } | |
bffe4f72 YL |
263 | ctrl_dbg(ctrl, "Data Link Layer Link Active not %s in 1000 msec\n", |
264 | active ? "set" : "cleared"); | |
265 | } | |
266 | ||
267 | static void pcie_wait_link_active(struct controller *ctrl) | |
268 | { | |
269 | __pcie_wait_link_active(ctrl, true); | |
270 | } | |
271 | ||
2f5d8e4f YL |
272 | static bool pci_bus_check_dev(struct pci_bus *bus, int devfn) |
273 | { | |
274 | u32 l; | |
275 | int count = 0; | |
276 | int delay = 1000, step = 20; | |
277 | bool found = false; | |
278 | ||
279 | do { | |
280 | found = pci_bus_read_dev_vendor_id(bus, devfn, &l, 0); | |
281 | count++; | |
282 | ||
283 | if (found) | |
284 | break; | |
285 | ||
286 | msleep(step); | |
287 | delay -= step; | |
288 | } while (delay > 0); | |
289 | ||
290 | if (count > 1 && pciehp_debug) | |
291 | printk(KERN_DEBUG "pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n", | |
292 | pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), | |
293 | PCI_FUNC(devfn), count, step, l); | |
294 | ||
295 | return found; | |
296 | } | |
297 | ||
82a9e79e | 298 | int pciehp_check_link_status(struct controller *ctrl) |
1da177e4 | 299 | { |
cd84d340 | 300 | struct pci_dev *pdev = ctrl_dev(ctrl); |
1a84b99c | 301 | bool found; |
1da177e4 | 302 | u16 lnk_status; |
1da177e4 | 303 | |
3c78bc61 RD |
304 | /* |
305 | * Data Link Layer Link Active Reporting must be capable for | |
306 | * hot-plug capable downstream port. But old controller might | |
307 | * not implement it. In this case, we wait for 1000 ms. | |
308 | */ | |
309 | if (ctrl->link_active_reporting) | |
310 | pcie_wait_link_active(ctrl); | |
311 | else | |
312 | msleep(1000); | |
f18e9625 | 313 | |
2f5d8e4f YL |
314 | /* wait 100ms before read pci conf, and try in 1s */ |
315 | msleep(100); | |
316 | found = pci_bus_check_dev(ctrl->pcie->port->subordinate, | |
317 | PCI_DEVFN(0, 0)); | |
0027cb3e | 318 | |
1a84b99c | 319 | pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status); |
7f2feec1 | 320 | ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status); |
322162a7 KK |
321 | if ((lnk_status & PCI_EXP_LNKSTA_LT) || |
322 | !(lnk_status & PCI_EXP_LNKSTA_NLW)) { | |
3784e0c6 BH |
323 | ctrl_err(ctrl, "link training error: status %#06x\n", |
324 | lnk_status); | |
1a84b99c | 325 | return -1; |
1da177e4 LT |
326 | } |
327 | ||
fdbd3ce9 YL |
328 | pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status); |
329 | ||
1a84b99c BH |
330 | if (!found) |
331 | return -1; | |
2f5d8e4f | 332 | |
1a84b99c | 333 | return 0; |
1da177e4 LT |
334 | } |
335 | ||
7f822999 YL |
336 | static int __pciehp_link_set(struct controller *ctrl, bool enable) |
337 | { | |
cd84d340 | 338 | struct pci_dev *pdev = ctrl_dev(ctrl); |
7f822999 | 339 | u16 lnk_ctrl; |
7f822999 | 340 | |
1a84b99c | 341 | pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &lnk_ctrl); |
7f822999 YL |
342 | |
343 | if (enable) | |
344 | lnk_ctrl &= ~PCI_EXP_LNKCTL_LD; | |
345 | else | |
346 | lnk_ctrl |= PCI_EXP_LNKCTL_LD; | |
347 | ||
1a84b99c | 348 | pcie_capability_write_word(pdev, PCI_EXP_LNKCTL, lnk_ctrl); |
7f822999 | 349 | ctrl_dbg(ctrl, "%s: lnk_ctrl = %x\n", __func__, lnk_ctrl); |
1a84b99c | 350 | return 0; |
7f822999 YL |
351 | } |
352 | ||
353 | static int pciehp_link_enable(struct controller *ctrl) | |
354 | { | |
355 | return __pciehp_link_set(ctrl, true); | |
356 | } | |
357 | ||
6dae6202 | 358 | void pciehp_get_attention_status(struct slot *slot, u8 *status) |
1da177e4 | 359 | { |
48fe3915 | 360 | struct controller *ctrl = slot->ctrl; |
cd84d340 | 361 | struct pci_dev *pdev = ctrl_dev(ctrl); |
1da177e4 | 362 | u16 slot_ctrl; |
1da177e4 | 363 | |
1a84b99c | 364 | pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); |
1518c17a KK |
365 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__, |
366 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); | |
1da177e4 | 367 | |
e7b4f0d7 BH |
368 | switch (slot_ctrl & PCI_EXP_SLTCTL_AIC) { |
369 | case PCI_EXP_SLTCTL_ATTN_IND_ON: | |
1da177e4 LT |
370 | *status = 1; /* On */ |
371 | break; | |
e7b4f0d7 | 372 | case PCI_EXP_SLTCTL_ATTN_IND_BLINK: |
1da177e4 LT |
373 | *status = 2; /* Blink */ |
374 | break; | |
e7b4f0d7 | 375 | case PCI_EXP_SLTCTL_ATTN_IND_OFF: |
1da177e4 LT |
376 | *status = 0; /* Off */ |
377 | break; | |
378 | default: | |
379 | *status = 0xFF; | |
380 | break; | |
381 | } | |
1da177e4 LT |
382 | } |
383 | ||
6dae6202 | 384 | void pciehp_get_power_status(struct slot *slot, u8 *status) |
1da177e4 | 385 | { |
48fe3915 | 386 | struct controller *ctrl = slot->ctrl; |
cd84d340 | 387 | struct pci_dev *pdev = ctrl_dev(ctrl); |
1da177e4 | 388 | u16 slot_ctrl; |
1da177e4 | 389 | |
1a84b99c | 390 | pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); |
1518c17a KK |
391 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__, |
392 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); | |
1da177e4 | 393 | |
e7b4f0d7 BH |
394 | switch (slot_ctrl & PCI_EXP_SLTCTL_PCC) { |
395 | case PCI_EXP_SLTCTL_PWR_ON: | |
396 | *status = 1; /* On */ | |
1da177e4 | 397 | break; |
e7b4f0d7 BH |
398 | case PCI_EXP_SLTCTL_PWR_OFF: |
399 | *status = 0; /* Off */ | |
1da177e4 LT |
400 | break; |
401 | default: | |
402 | *status = 0xFF; | |
403 | break; | |
404 | } | |
1da177e4 LT |
405 | } |
406 | ||
6dae6202 | 407 | void pciehp_get_latch_status(struct slot *slot, u8 *status) |
1da177e4 | 408 | { |
1a84b99c | 409 | struct pci_dev *pdev = ctrl_dev(slot->ctrl); |
1da177e4 | 410 | u16 slot_status; |
1da177e4 | 411 | |
1a84b99c | 412 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); |
322162a7 | 413 | *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS); |
1da177e4 LT |
414 | } |
415 | ||
6dae6202 | 416 | void pciehp_get_adapter_status(struct slot *slot, u8 *status) |
1da177e4 | 417 | { |
1a84b99c | 418 | struct pci_dev *pdev = ctrl_dev(slot->ctrl); |
1da177e4 | 419 | u16 slot_status; |
1da177e4 | 420 | |
1a84b99c | 421 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); |
322162a7 | 422 | *status = !!(slot_status & PCI_EXP_SLTSTA_PDS); |
1da177e4 LT |
423 | } |
424 | ||
82a9e79e | 425 | int pciehp_query_power_fault(struct slot *slot) |
1da177e4 | 426 | { |
1a84b99c | 427 | struct pci_dev *pdev = ctrl_dev(slot->ctrl); |
1da177e4 | 428 | u16 slot_status; |
1da177e4 | 429 | |
1a84b99c | 430 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); |
322162a7 | 431 | return !!(slot_status & PCI_EXP_SLTSTA_PFD); |
1da177e4 LT |
432 | } |
433 | ||
6dae6202 | 434 | void pciehp_set_attention_status(struct slot *slot, u8 value) |
1da177e4 | 435 | { |
48fe3915 | 436 | struct controller *ctrl = slot->ctrl; |
f4778364 | 437 | u16 slot_cmd; |
1da177e4 | 438 | |
af9ab791 BH |
439 | if (!ATTN_LED(ctrl)) |
440 | return; | |
441 | ||
1da177e4 | 442 | switch (value) { |
3c78bc61 | 443 | case 0: /* turn off */ |
e7b4f0d7 | 444 | slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_OFF; |
445f7985 KK |
445 | break; |
446 | case 1: /* turn on */ | |
e7b4f0d7 | 447 | slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_ON; |
445f7985 KK |
448 | break; |
449 | case 2: /* turn blink */ | |
e7b4f0d7 | 450 | slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_BLINK; |
445f7985 KK |
451 | break; |
452 | default: | |
6dae6202 | 453 | return; |
1da177e4 | 454 | } |
a5dd4b4b | 455 | pcie_write_cmd_nowait(ctrl, slot_cmd, PCI_EXP_SLTCTL_AIC); |
1518c17a KK |
456 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
457 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); | |
1da177e4 LT |
458 | } |
459 | ||
82a9e79e | 460 | void pciehp_green_led_on(struct slot *slot) |
1da177e4 | 461 | { |
48fe3915 | 462 | struct controller *ctrl = slot->ctrl; |
71ad556d | 463 | |
af9ab791 BH |
464 | if (!PWR_LED(ctrl)) |
465 | return; | |
466 | ||
a5dd4b4b AW |
467 | pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_ON, |
468 | PCI_EXP_SLTCTL_PIC); | |
1518c17a | 469 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
e7b4f0d7 BH |
470 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, |
471 | PCI_EXP_SLTCTL_PWR_IND_ON); | |
1da177e4 LT |
472 | } |
473 | ||
82a9e79e | 474 | void pciehp_green_led_off(struct slot *slot) |
1da177e4 | 475 | { |
48fe3915 | 476 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 477 | |
af9ab791 BH |
478 | if (!PWR_LED(ctrl)) |
479 | return; | |
480 | ||
a5dd4b4b AW |
481 | pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF, |
482 | PCI_EXP_SLTCTL_PIC); | |
1518c17a | 483 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
e7b4f0d7 BH |
484 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, |
485 | PCI_EXP_SLTCTL_PWR_IND_OFF); | |
1da177e4 LT |
486 | } |
487 | ||
82a9e79e | 488 | void pciehp_green_led_blink(struct slot *slot) |
1da177e4 | 489 | { |
48fe3915 | 490 | struct controller *ctrl = slot->ctrl; |
71ad556d | 491 | |
af9ab791 BH |
492 | if (!PWR_LED(ctrl)) |
493 | return; | |
494 | ||
a5dd4b4b AW |
495 | pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_BLINK, |
496 | PCI_EXP_SLTCTL_PIC); | |
1518c17a | 497 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
e7b4f0d7 BH |
498 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, |
499 | PCI_EXP_SLTCTL_PWR_IND_BLINK); | |
1da177e4 LT |
500 | } |
501 | ||
3c78bc61 | 502 | int pciehp_power_on_slot(struct slot *slot) |
1da177e4 | 503 | { |
48fe3915 | 504 | struct controller *ctrl = slot->ctrl; |
cd84d340 | 505 | struct pci_dev *pdev = ctrl_dev(ctrl); |
f4778364 | 506 | u16 slot_status; |
1a84b99c | 507 | int retval; |
1da177e4 | 508 | |
5a49f203 | 509 | /* Clear sticky power-fault bit from previous power failures */ |
1a84b99c | 510 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); |
2f2ed41c BH |
511 | if (slot_status & PCI_EXP_SLTSTA_PFD) |
512 | pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, | |
513 | PCI_EXP_SLTSTA_PFD); | |
5651c48c | 514 | ctrl->power_fault_detected = 0; |
1da177e4 | 515 | |
e7b4f0d7 | 516 | pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_ON, PCI_EXP_SLTCTL_PCC); |
1518c17a | 517 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
e7b4f0d7 BH |
518 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, |
519 | PCI_EXP_SLTCTL_PWR_ON); | |
1da177e4 | 520 | |
2debd928 YL |
521 | retval = pciehp_link_enable(ctrl); |
522 | if (retval) | |
523 | ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__); | |
524 | ||
1da177e4 LT |
525 | return retval; |
526 | } | |
527 | ||
3c78bc61 | 528 | void pciehp_power_off_slot(struct slot *slot) |
1da177e4 | 529 | { |
48fe3915 | 530 | struct controller *ctrl = slot->ctrl; |
f1050a35 | 531 | |
e7b4f0d7 | 532 | pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_OFF, PCI_EXP_SLTCTL_PCC); |
1518c17a | 533 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
e7b4f0d7 BH |
534 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, |
535 | PCI_EXP_SLTCTL_PWR_OFF); | |
1da177e4 LT |
536 | } |
537 | ||
48fe3915 | 538 | static irqreturn_t pcie_isr(int irq, void *dev_id) |
1da177e4 | 539 | { |
48fe3915 | 540 | struct controller *ctrl = (struct controller *)dev_id; |
cd84d340 | 541 | struct pci_dev *pdev = ctrl_dev(ctrl); |
b440bde7 BH |
542 | struct pci_bus *subordinate = pdev->subordinate; |
543 | struct pci_dev *dev; | |
8720d27d | 544 | struct slot *slot = ctrl->slot; |
c6b069e9 | 545 | u16 detected, intr_loc; |
2db0f71f | 546 | u8 present; |
4f092fec | 547 | bool link; |
1da177e4 | 548 | |
c6b069e9 KK |
549 | /* |
550 | * In order to guarantee that all interrupt events are | |
551 | * serviced, we need to re-inspect Slot Status register after | |
552 | * clearing what is presumed to be the last pending interrupt. | |
553 | */ | |
554 | intr_loc = 0; | |
555 | do { | |
1a84b99c | 556 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &detected); |
1469d17d JW |
557 | if (detected == (u16) ~0) { |
558 | ctrl_info(ctrl, "%s: no response from device\n", | |
559 | __func__); | |
560 | return IRQ_HANDLED; | |
561 | } | |
1da177e4 | 562 | |
322162a7 | 563 | detected &= (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD | |
2db0f71f | 564 | PCI_EXP_SLTSTA_PDC | |
e48f1b67 | 565 | PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC); |
81b840cd | 566 | detected &= ~intr_loc; |
c6b069e9 KK |
567 | intr_loc |= detected; |
568 | if (!intr_loc) | |
1da177e4 | 569 | return IRQ_NONE; |
1a84b99c BH |
570 | if (detected) |
571 | pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, | |
572 | intr_loc); | |
c6b069e9 | 573 | } while (detected); |
71ad556d | 574 | |
3784e0c6 | 575 | ctrl_dbg(ctrl, "pending interrupts %#06x from Slot Status\n", intr_loc); |
71ad556d | 576 | |
c6b069e9 | 577 | /* Check Command Complete Interrupt Pending */ |
322162a7 | 578 | if (intr_loc & PCI_EXP_SLTSTA_CC) { |
262303fe | 579 | ctrl->cmd_busy = 0; |
2d32a9ae | 580 | smp_mb(); |
d737bdc1 | 581 | wake_up(&ctrl->queue); |
1da177e4 LT |
582 | } |
583 | ||
b440bde7 BH |
584 | if (subordinate) { |
585 | list_for_each_entry(dev, &subordinate->devices, bus_list) { | |
586 | if (dev->ignore_hotplug) { | |
587 | ctrl_dbg(ctrl, "ignoring hotplug event %#06x (%s requested no hotplug)\n", | |
588 | intr_loc, pci_name(dev)); | |
589 | return IRQ_HANDLED; | |
590 | } | |
591 | } | |
592 | } | |
593 | ||
322162a7 | 594 | if (!(intr_loc & ~PCI_EXP_SLTSTA_CC)) |
dbd79aed KK |
595 | return IRQ_HANDLED; |
596 | ||
c6b069e9 | 597 | /* Check Attention Button Pressed */ |
4f092fec BH |
598 | if (intr_loc & PCI_EXP_SLTSTA_ABP) { |
599 | ctrl_info(ctrl, "Button pressed on Slot(%s)\n", | |
600 | slot_name(slot)); | |
601 | pciehp_queue_interrupt_event(slot, INT_BUTTON_PRESS); | |
602 | } | |
48fe3915 | 603 | |
c6b069e9 | 604 | /* Check Presence Detect Changed */ |
4f092fec BH |
605 | if (intr_loc & PCI_EXP_SLTSTA_PDC) { |
606 | pciehp_get_adapter_status(slot, &present); | |
607 | ctrl_info(ctrl, "Card %spresent on Slot(%s)\n", | |
608 | present ? "" : "not ", slot_name(slot)); | |
609 | pciehp_queue_interrupt_event(slot, present ? INT_PRESENCE_ON : | |
610 | INT_PRESENCE_OFF); | |
611 | } | |
48fe3915 | 612 | |
c6b069e9 | 613 | /* Check Power Fault Detected */ |
99f0169c KK |
614 | if ((intr_loc & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) { |
615 | ctrl->power_fault_detected = 1; | |
4f092fec BH |
616 | ctrl_err(ctrl, "Power fault on slot %s\n", slot_name(slot)); |
617 | pciehp_queue_interrupt_event(slot, INT_POWER_FAULT); | |
99f0169c | 618 | } |
e48f1b67 | 619 | |
4f092fec BH |
620 | if (intr_loc & PCI_EXP_SLTSTA_DLLSC) { |
621 | link = pciehp_check_link_active(ctrl); | |
622 | ctrl_info(ctrl, "slot(%s): Link %s event\n", | |
623 | slot_name(slot), link ? "Up" : "Down"); | |
624 | pciehp_queue_interrupt_event(slot, link ? INT_LINK_UP : | |
625 | INT_LINK_DOWN); | |
626 | } | |
e48f1b67 | 627 | |
1da177e4 LT |
628 | return IRQ_HANDLED; |
629 | } | |
630 | ||
6dae6202 | 631 | void pcie_enable_notification(struct controller *ctrl) |
ecdde939 | 632 | { |
c27fb883 | 633 | u16 cmd, mask; |
1da177e4 | 634 | |
5651c48c KK |
635 | /* |
636 | * TBD: Power fault detected software notification support. | |
637 | * | |
638 | * Power fault detected software notification is not enabled | |
639 | * now, because it caused power fault detected interrupt storm | |
640 | * on some machines. On those machines, power fault detected | |
641 | * bit in the slot status register was set again immediately | |
642 | * when it is cleared in the interrupt service routine, and | |
643 | * next power fault detected interrupt was notified again. | |
644 | */ | |
4f854f2a RJ |
645 | |
646 | /* | |
647 | * Always enable link events: thus link-up and link-down shall | |
648 | * always be treated as hotplug and unplug respectively. Enable | |
649 | * presence detect only if Attention Button is not present. | |
650 | */ | |
651 | cmd = PCI_EXP_SLTCTL_DLLSCE; | |
ae416e6b | 652 | if (ATTN_BUTTN(ctrl)) |
322162a7 | 653 | cmd |= PCI_EXP_SLTCTL_ABPE; |
4f854f2a RJ |
654 | else |
655 | cmd |= PCI_EXP_SLTCTL_PDCE; | |
c27fb883 | 656 | if (!pciehp_poll_mode) |
322162a7 | 657 | cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE; |
c27fb883 | 658 | |
322162a7 | 659 | mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | |
2db0f71f | 660 | PCI_EXP_SLTCTL_PFDE | |
4f854f2a RJ |
661 | PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE | |
662 | PCI_EXP_SLTCTL_DLLSCE); | |
c27fb883 | 663 | |
a5dd4b4b | 664 | pcie_write_cmd_nowait(ctrl, cmd, mask); |
cf8d7b58 YL |
665 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
666 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd); | |
c4635eb0 KK |
667 | } |
668 | ||
669 | static void pcie_disable_notification(struct controller *ctrl) | |
670 | { | |
671 | u16 mask; | |
6dae6202 | 672 | |
322162a7 KK |
673 | mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | |
674 | PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE | | |
f22daf1f KK |
675 | PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE | |
676 | PCI_EXP_SLTCTL_DLLSCE); | |
6dae6202 | 677 | pcie_write_cmd(ctrl, 0, mask); |
cf8d7b58 YL |
678 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
679 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0); | |
c4635eb0 KK |
680 | } |
681 | ||
2e35afae AW |
682 | /* |
683 | * pciehp has a 1:1 bus:slot relationship so we ultimately want a secondary | |
2b3940b6 RJ |
684 | * bus reset of the bridge, but at the same time we want to ensure that it is |
685 | * not seen as a hot-unplug, followed by the hot-plug of the device. Thus, | |
686 | * disable link state notification and presence detection change notification | |
687 | * momentarily, if we see that they could interfere. Also, clear any spurious | |
2e35afae AW |
688 | * events after. |
689 | */ | |
690 | int pciehp_reset_slot(struct slot *slot, int probe) | |
691 | { | |
692 | struct controller *ctrl = slot->ctrl; | |
cd84d340 | 693 | struct pci_dev *pdev = ctrl_dev(ctrl); |
06a8d89a | 694 | u16 stat_mask = 0, ctrl_mask = 0; |
2e35afae AW |
695 | |
696 | if (probe) | |
697 | return 0; | |
698 | ||
2b3940b6 | 699 | if (!ATTN_BUTTN(ctrl)) { |
06a8d89a RJ |
700 | ctrl_mask |= PCI_EXP_SLTCTL_PDCE; |
701 | stat_mask |= PCI_EXP_SLTSTA_PDC; | |
2e35afae | 702 | } |
06a8d89a RJ |
703 | ctrl_mask |= PCI_EXP_SLTCTL_DLLSCE; |
704 | stat_mask |= PCI_EXP_SLTSTA_DLLSC; | |
705 | ||
706 | pcie_write_cmd(ctrl, 0, ctrl_mask); | |
cf8d7b58 YL |
707 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
708 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0); | |
06a8d89a RJ |
709 | if (pciehp_poll_mode) |
710 | del_timer_sync(&ctrl->poll_timer); | |
2e35afae AW |
711 | |
712 | pci_reset_bridge_secondary_bus(ctrl->pcie->port); | |
713 | ||
06a8d89a | 714 | pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, stat_mask); |
a5dd4b4b | 715 | pcie_write_cmd_nowait(ctrl, ctrl_mask, ctrl_mask); |
cf8d7b58 YL |
716 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
717 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, ctrl_mask); | |
06a8d89a RJ |
718 | if (pciehp_poll_mode) |
719 | int_poll_timeout(ctrl->poll_timer.data); | |
2e35afae AW |
720 | |
721 | return 0; | |
722 | } | |
723 | ||
dbc7e1e5 | 724 | int pcie_init_notification(struct controller *ctrl) |
c4635eb0 KK |
725 | { |
726 | if (pciehp_request_irq(ctrl)) | |
727 | return -1; | |
6dae6202 | 728 | pcie_enable_notification(ctrl); |
dbc7e1e5 | 729 | ctrl->notification_enabled = 1; |
c4635eb0 KK |
730 | return 0; |
731 | } | |
732 | ||
733 | static void pcie_shutdown_notification(struct controller *ctrl) | |
734 | { | |
dbc7e1e5 EB |
735 | if (ctrl->notification_enabled) { |
736 | pcie_disable_notification(ctrl); | |
737 | pciehp_free_irq(ctrl); | |
738 | ctrl->notification_enabled = 0; | |
739 | } | |
c4635eb0 KK |
740 | } |
741 | ||
c4635eb0 KK |
742 | static int pcie_init_slot(struct controller *ctrl) |
743 | { | |
744 | struct slot *slot; | |
745 | ||
746 | slot = kzalloc(sizeof(*slot), GFP_KERNEL); | |
747 | if (!slot) | |
748 | return -ENOMEM; | |
749 | ||
d8537548 | 750 | slot->wq = alloc_workqueue("pciehp-%u", 0, 0, PSN(ctrl)); |
c2be6f93 YW |
751 | if (!slot->wq) |
752 | goto abort; | |
753 | ||
c4635eb0 | 754 | slot->ctrl = ctrl; |
c4635eb0 | 755 | mutex_init(&slot->lock); |
50b52fde | 756 | mutex_init(&slot->hotplug_lock); |
c4635eb0 | 757 | INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work); |
8720d27d | 758 | ctrl->slot = slot; |
1da177e4 | 759 | return 0; |
c2be6f93 YW |
760 | abort: |
761 | kfree(slot); | |
762 | return -ENOMEM; | |
1da177e4 | 763 | } |
08e7a7d2 | 764 | |
c4635eb0 KK |
765 | static void pcie_cleanup_slot(struct controller *ctrl) |
766 | { | |
8720d27d | 767 | struct slot *slot = ctrl->slot; |
c4635eb0 | 768 | cancel_delayed_work(&slot->work); |
c2be6f93 | 769 | destroy_workqueue(slot->wq); |
c4635eb0 KK |
770 | kfree(slot); |
771 | } | |
772 | ||
2aeeef11 | 773 | static inline void dbg_ctrl(struct controller *ctrl) |
08e7a7d2 | 774 | { |
385e2491 | 775 | struct pci_dev *pdev = ctrl->pcie->port; |
3784e0c6 | 776 | u16 reg16; |
08e7a7d2 | 777 | |
2aeeef11 KK |
778 | if (!pciehp_debug) |
779 | return; | |
08e7a7d2 | 780 | |
7f2feec1 | 781 | ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap); |
cd84d340 | 782 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, ®16); |
7f2feec1 | 783 | ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16); |
cd84d340 | 784 | pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, ®16); |
7f2feec1 | 785 | ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16); |
2aeeef11 | 786 | } |
08e7a7d2 | 787 | |
3c78bc61 | 788 | #define FLAG(x, y) (((x) & (y)) ? '+' : '-') |
afe2478f | 789 | |
c4635eb0 | 790 | struct controller *pcie_init(struct pcie_device *dev) |
2aeeef11 | 791 | { |
c4635eb0 | 792 | struct controller *ctrl; |
f18e9625 | 793 | u32 slot_cap, link_cap; |
2aeeef11 | 794 | struct pci_dev *pdev = dev->port; |
08e7a7d2 | 795 | |
c4635eb0 KK |
796 | ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); |
797 | if (!ctrl) { | |
18b341b7 | 798 | dev_err(&dev->device, "%s: Out of memory\n", __func__); |
c4635eb0 KK |
799 | goto abort; |
800 | } | |
f7a10e32 | 801 | ctrl->pcie = dev; |
1a84b99c | 802 | pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap); |
2aeeef11 | 803 | ctrl->slot_cap = slot_cap; |
08e7a7d2 | 804 | mutex_init(&ctrl->ctrl_lock); |
08e7a7d2 | 805 | init_waitqueue_head(&ctrl->queue); |
2aeeef11 | 806 | dbg_ctrl(ctrl); |
2cc56f30 | 807 | |
3c78bc61 RD |
808 | /* Check if Data Link Layer Link Active Reporting is implemented */ |
809 | pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap); | |
3784e0c6 | 810 | if (link_cap & PCI_EXP_LNKCAP_DLLLARC) |
3c78bc61 | 811 | ctrl->link_active_reporting = 1; |
f18e9625 | 812 | |
c4635eb0 | 813 | /* Clear all remaining event bits in Slot Status register */ |
df72648c BH |
814 | pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, |
815 | PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD | | |
816 | PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC | | |
0d25d35c | 817 | PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC); |
08e7a7d2 | 818 | |
3784e0c6 | 819 | ctrl_info(ctrl, "Slot #%d AttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c Interlock%c NoCompl%c LLActRep%c\n", |
afe2478f BH |
820 | (slot_cap & PCI_EXP_SLTCAP_PSN) >> 19, |
821 | FLAG(slot_cap, PCI_EXP_SLTCAP_ABP), | |
afe2478f BH |
822 | FLAG(slot_cap, PCI_EXP_SLTCAP_PCP), |
823 | FLAG(slot_cap, PCI_EXP_SLTCAP_MRLSP), | |
3784e0c6 BH |
824 | FLAG(slot_cap, PCI_EXP_SLTCAP_AIP), |
825 | FLAG(slot_cap, PCI_EXP_SLTCAP_PIP), | |
826 | FLAG(slot_cap, PCI_EXP_SLTCAP_HPC), | |
827 | FLAG(slot_cap, PCI_EXP_SLTCAP_HPS), | |
afe2478f BH |
828 | FLAG(slot_cap, PCI_EXP_SLTCAP_EIP), |
829 | FLAG(slot_cap, PCI_EXP_SLTCAP_NCCS), | |
830 | FLAG(link_cap, PCI_EXP_LNKCAP_DLLLARC)); | |
c4635eb0 KK |
831 | |
832 | if (pcie_init_slot(ctrl)) | |
833 | goto abort_ctrl; | |
2aeeef11 | 834 | |
c4635eb0 KK |
835 | return ctrl; |
836 | ||
c4635eb0 KK |
837 | abort_ctrl: |
838 | kfree(ctrl); | |
08e7a7d2 | 839 | abort: |
c4635eb0 KK |
840 | return NULL; |
841 | } | |
842 | ||
82a9e79e | 843 | void pciehp_release_ctrl(struct controller *ctrl) |
c4635eb0 KK |
844 | { |
845 | pcie_shutdown_notification(ctrl); | |
846 | pcie_cleanup_slot(ctrl); | |
c4635eb0 | 847 | kfree(ctrl); |
08e7a7d2 | 848 | } |