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[deliverable/linux.git] / drivers / pci / hotplug / pciehp_hpc.c
CommitLineData
1da177e4
LT		 1/*
2 * PCI Express PCI Hot Plug Driver
3 *
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
8 *
9 * All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
20 * details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
8cf4c195 26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
1da177e4
LT		 27 *
28 */
29
1da177e4
LT		 30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/types.h>
de25968c
TS		 33#include <linux/signal.h>
34#include <linux/jiffies.h>
35#include <linux/timer.h>
1da177e4 36#include <linux/pci.h>
5d1b8c9e 37#include <linux/interrupt.h>
34d03419 38#include <linux/time.h>
5d1b8c9e 39
1da177e4
LT		 40#include "../pci.h"
41#include "pciehp.h"
1da177e4 42
5d386e1a
KK		 43static atomic_t pciehp_num_controllers = ATOMIC_INIT(0);
44
1da177e4
LT		 45struct ctrl_reg {
46 u8 cap_id;
47 u8 nxt_ptr;
48 u16 cap_reg;
49 u32 dev_cap;
50 u16 dev_ctrl;
51 u16 dev_status;
52 u32 lnk_cap;
53 u16 lnk_ctrl;
54 u16 lnk_status;
55 u32 slot_cap;
56 u16 slot_ctrl;
57 u16 slot_status;
58 u16 root_ctrl;
59 u16 rsvp;
60 u32 root_status;
61} __attribute__ ((packed));
62
63/* offsets to the controller registers based on the above structure layout */
64enum ctrl_offsets {
65 PCIECAPID = offsetof(struct ctrl_reg, cap_id),
66 NXTCAPPTR = offsetof(struct ctrl_reg, nxt_ptr),
67 CAPREG = offsetof(struct ctrl_reg, cap_reg),
68 DEVCAP = offsetof(struct ctrl_reg, dev_cap),
69 DEVCTRL = offsetof(struct ctrl_reg, dev_ctrl),
70 DEVSTATUS = offsetof(struct ctrl_reg, dev_status),
71 LNKCAP = offsetof(struct ctrl_reg, lnk_cap),
72 LNKCTRL = offsetof(struct ctrl_reg, lnk_ctrl),
73 LNKSTATUS = offsetof(struct ctrl_reg, lnk_status),
74 SLOTCAP = offsetof(struct ctrl_reg, slot_cap),
75 SLOTCTRL = offsetof(struct ctrl_reg, slot_ctrl),
76 SLOTSTATUS = offsetof(struct ctrl_reg, slot_status),
77 ROOTCTRL = offsetof(struct ctrl_reg, root_ctrl),
78 ROOTSTATUS = offsetof(struct ctrl_reg, root_status),
79};
1da177e4 80
a0f018da
KK		 81static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value)
82{
83 struct pci_dev *dev = ctrl->pci_dev;
84 return pci_read_config_word(dev, ctrl->cap_base + reg, value);
85}
86
87static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value)
88{
89 struct pci_dev *dev = ctrl->pci_dev;
90 return pci_read_config_dword(dev, ctrl->cap_base + reg, value);
91}
92
93static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value)
94{
95 struct pci_dev *dev = ctrl->pci_dev;
96 return pci_write_config_word(dev, ctrl->cap_base + reg, value);
97}
98
99static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value)
100{
101 struct pci_dev *dev = ctrl->pci_dev;
102 return pci_write_config_dword(dev, ctrl->cap_base + reg, value);
103}
1da177e4
LT		 104
105/* Field definitions in PCI Express Capabilities Register */
106#define CAP_VER 0x000F
107#define DEV_PORT_TYPE 0x00F0
108#define SLOT_IMPL 0x0100
109#define MSG_NUM 0x3E00
110
111/* Device or Port Type */
112#define NAT_ENDPT 0x00
113#define LEG_ENDPT 0x01
114#define ROOT_PORT 0x04
115#define UP_STREAM 0x05
116#define DN_STREAM 0x06
117#define PCIE_PCI_BRDG 0x07
118#define PCI_PCIE_BRDG 0x10
119
120/* Field definitions in Device Capabilities Register */
121#define DATTN_BUTTN_PRSN 0x1000
122#define DATTN_LED_PRSN 0x2000
123#define DPWR_LED_PRSN 0x4000
124
125/* Field definitions in Link Capabilities Register */
126#define MAX_LNK_SPEED 0x000F
127#define MAX_LNK_WIDTH 0x03F0
f18e9625 128#define LINK_ACTIVE_REPORTING 0x00100000
1da177e4
LT		 129
130/* Link Width Encoding */
131#define LNK_X1 0x01
132#define LNK_X2 0x02
71ad556d 133#define LNK_X4 0x04
1da177e4
LT		 134#define LNK_X8 0x08
135#define LNK_X12 0x0C
71ad556d 136#define LNK_X16 0x10
1da177e4
LT		 137#define LNK_X32 0x20
138
139/*Field definitions of Link Status Register */
140#define LNK_SPEED 0x000F
141#define NEG_LINK_WD 0x03F0
142#define LNK_TRN_ERR 0x0400
143#define LNK_TRN 0x0800
144#define SLOT_CLK_CONF 0x1000
f18e9625 145#define LINK_ACTIVE 0x2000
1da177e4
LT		 146
147/* Field definitions in Slot Capabilities Register */
148#define ATTN_BUTTN_PRSN 0x00000001
149#define PWR_CTRL_PRSN 0x00000002
150#define MRL_SENS_PRSN 0x00000004
151#define ATTN_LED_PRSN 0x00000008
152#define PWR_LED_PRSN 0x00000010
153#define HP_SUPR_RM_SUP 0x00000020
154#define HP_CAP 0x00000040
155#define SLOT_PWR_VALUE 0x000003F8
156#define SLOT_PWR_LIMIT 0x00000C00
157#define PSN 0xFFF80000 /* PSN: Physical Slot Number */
158
159/* Field definitions in Slot Control Register */
160#define ATTN_BUTTN_ENABLE 0x0001
161#define PWR_FAULT_DETECT_ENABLE 0x0002
162#define MRL_DETECT_ENABLE 0x0004
163#define PRSN_DETECT_ENABLE 0x0008
164#define CMD_CMPL_INTR_ENABLE 0x0010
165#define HP_INTR_ENABLE 0x0020
166#define ATTN_LED_CTRL 0x00C0
167#define PWR_LED_CTRL 0x0300
168#define PWR_CTRL 0x0400
34d03419 169#define EMI_CTRL 0x0800
1da177e4
LT		 170
171/* Attention indicator and Power indicator states */
172#define LED_ON 0x01
173#define LED_BLINK 0x10
174#define LED_OFF 0x11
175
176/* Power Control Command */
177#define POWER_ON 0
178#define POWER_OFF 0x0400
179
34d03419
KCA		 180/* EMI Status defines */
181#define EMI_DISENGAGED 0
182#define EMI_ENGAGED 1
183
1da177e4
LT		 184/* Field definitions in Slot Status Register */
185#define ATTN_BUTTN_PRESSED 0x0001
186#define PWR_FAULT_DETECTED 0x0002
187#define MRL_SENS_CHANGED 0x0004
188#define PRSN_DETECT_CHANGED 0x0008
189#define CMD_COMPLETED 0x0010
190#define MRL_STATE 0x0020
191#define PRSN_STATE 0x0040
34d03419
KCA		 192#define EMI_STATE 0x0080
193#define EMI_STATUS_BIT 7
1da177e4 194
48fe3915
KK		 195static irqreturn_t pcie_isr(int irq, void *dev_id);
196static void start_int_poll_timer(struct controller *ctrl, int sec);
1da177e4
LT		 197
198/* This is the interrupt polling timeout function. */
48fe3915 199static void int_poll_timeout(unsigned long data)
1da177e4 200{
48fe3915 201 struct controller *ctrl = (struct controller *)data;
1da177e4 202
1da177e4 203 /* Poll for interrupt events. regs == NULL => polling */
48fe3915 204 pcie_isr(0, ctrl);
1da177e4 205
48fe3915 206 init_timer(&ctrl->poll_timer);
1da177e4 207 if (!pciehp_poll_time)
40730d10 208 pciehp_poll_time = 2; /* default polling interval is 2 sec */
1da177e4 209
48fe3915 210 start_int_poll_timer(ctrl, pciehp_poll_time);
1da177e4
LT		 211}
212
213/* This function starts the interrupt polling timer. */
48fe3915 214static void start_int_poll_timer(struct controller *ctrl, int sec)
1da177e4 215{
48fe3915
KK		 216 /* Clamp to sane value */
217 if ((sec <= 0) || (sec > 60))
218 sec = 2;
219
220 ctrl->poll_timer.function = &int_poll_timeout;
221 ctrl->poll_timer.data = (unsigned long)ctrl;
222 ctrl->poll_timer.expires = jiffies + sec * HZ;
223 add_timer(&ctrl->poll_timer);
1da177e4
LT		 224}
225
2aeeef11
KK		 226static inline int pciehp_request_irq(struct controller *ctrl)
227{
f7a10e32 228 int retval, irq = ctrl->pcie->irq;
2aeeef11
KK		 229
230 /* Install interrupt polling timer. Start with 10 sec delay */
231 if (pciehp_poll_mode) {
232 init_timer(&ctrl->poll_timer);
233 start_int_poll_timer(ctrl, 10);
234 return 0;
235 }
236
237 /* Installs the interrupt handler */
238 retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl);
239 if (retval)
7f2feec1
TI		 240 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
241 irq);
2aeeef11
KK		 242 return retval;
243}
244
245static inline void pciehp_free_irq(struct controller *ctrl)
246{
247 if (pciehp_poll_mode)
248 del_timer_sync(&ctrl->poll_timer);
249 else
f7a10e32 250 free_irq(ctrl->pcie->irq, ctrl);
2aeeef11
KK		 251}
252
563f1190 253static int pcie_poll_cmd(struct controller *ctrl)
6592e02a
KK		 254{
255 u16 slot_status;
256 int timeout = 1000;
257
820943b6
KK		 258 if (!pciehp_readw(ctrl, SLOTSTATUS, &slot_status)) {
259 if (slot_status & CMD_COMPLETED) {
260 pciehp_writew(ctrl, SLOTSTATUS, CMD_COMPLETED);
261 return 1;
262 }
263 }
a5827f40 264 while (timeout > 0) {
66618bad
KK		 265 msleep(10);
266 timeout -= 10;
820943b6
KK		 267 if (!pciehp_readw(ctrl, SLOTSTATUS, &slot_status)) {
268 if (slot_status & CMD_COMPLETED) {
269 pciehp_writew(ctrl, SLOTSTATUS, CMD_COMPLETED);
270 return 1;
271 }
272 }
6592e02a
KK		 273 }
274 return 0; /* timeout */
6592e02a
KK		 275}
276
563f1190 277static void pcie_wait_cmd(struct controller *ctrl, int poll)
44ef4cef 278{
262303fe
KK		 279 unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
280 unsigned long timeout = msecs_to_jiffies(msecs);
281 int rc;
282
6592e02a
KK		 283 if (poll)
284 rc = pcie_poll_cmd(ctrl);
285 else
d737bdc1 286 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
262303fe 287 if (!rc)
7f2feec1 288 ctrl_dbg(ctrl, "Command not completed in 1000 msec\n");
44ef4cef
KK		 289}
290
f4778364
KK		 291/**
292 * pcie_write_cmd - Issue controller command
c27fb883 293 * @ctrl: controller to which the command is issued
f4778364
KK		 294 * @cmd: command value written to slot control register
295 * @mask: bitmask of slot control register to be modified
296 */
c27fb883 297static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
1da177e4 298{
1da177e4
LT		 299 int retval = 0;
300 u16 slot_status;
f4778364 301 u16 slot_ctrl;
1da177e4 302
44ef4cef
KK		 303 mutex_lock(&ctrl->ctrl_lock);
304
a0f018da 305 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
1da177e4 306 if (retval) {
7f2feec1
TI		 307 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
308 __func__);
44ef4cef 309 goto out;
a0f018da
KK		 310 }
311
5808639b
KK		 312 if (slot_status & CMD_COMPLETED) {
313 if (!ctrl->no_cmd_complete) {
314 /*
315 * After 1 sec and CMD_COMPLETED still not set, just
316 * proceed forward to issue the next command according
317 * to spec. Just print out the error message.
318 */
18b341b7 319 ctrl_dbg(ctrl, "CMD_COMPLETED not clear after 1 sec\n");
5808639b
KK		 320 } else if (!NO_CMD_CMPL(ctrl)) {
321 /*
322 * This controller semms to notify of command completed
323 * event even though it supports none of power
324 * controller, attention led, power led and EMI.
325 */
18b341b7
TI		 326 ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Need to "
327 "wait for command completed event.\n");
5808639b
KK		 328 ctrl->no_cmd_complete = 0;
329 } else {
18b341b7
TI		 330 ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Maybe "
331 "the controller is broken.\n");
5808639b 332 }
1da177e4
LT		 333 }
334
f4778364 335 retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
1da177e4 336 if (retval) {
7f2feec1 337 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
c6b069e9 338 goto out;
1da177e4 339 }
1da177e4 340
f4778364 341 slot_ctrl &= ~mask;
b7aa1f16 342 slot_ctrl |= (cmd & mask);
f4778364 343 ctrl->cmd_busy = 1;
2d32a9ae 344 smp_mb();
f4778364
KK		 345 retval = pciehp_writew(ctrl, SLOTCTRL, slot_ctrl);
346 if (retval)
18b341b7 347 ctrl_err(ctrl, "Cannot write to SLOTCTRL register\n");
f4778364 348
44ef4cef
KK		 349 /*
350 * Wait for command completion.
351 */
6592e02a
KK		 352 if (!retval && !ctrl->no_cmd_complete) {
353 int poll = 0;
354 /*
355 * if hotplug interrupt is not enabled or command
356 * completed interrupt is not enabled, we need to poll
357 * command completed event.
358 */
359 if (!(slot_ctrl & HP_INTR_ENABLE) ||
360 !(slot_ctrl & CMD_CMPL_INTR_ENABLE))
361 poll = 1;
d737bdc1 362 pcie_wait_cmd(ctrl, poll);
6592e02a 363 }
44ef4cef
KK		 364 out:
365 mutex_unlock(&ctrl->ctrl_lock);
1da177e4
LT		 366 return retval;
367}
368
f18e9625
KK		 369static inline int check_link_active(struct controller *ctrl)
370{
371 u16 link_status;
372
373 if (pciehp_readw(ctrl, LNKSTATUS, &link_status))
374 return 0;
375 return !!(link_status & LINK_ACTIVE);
376}
377
378static void pcie_wait_link_active(struct controller *ctrl)
379{
380 int timeout = 1000;
381
382 if (check_link_active(ctrl))
383 return;
384 while (timeout > 0) {
385 msleep(10);
386 timeout -= 10;
387 if (check_link_active(ctrl))
388 return;
389 }
390 ctrl_dbg(ctrl, "Data Link Layer Link Active not set in 1000 msec\n");
391}
392
1da177e4
LT		 393static int hpc_check_lnk_status(struct controller *ctrl)
394{
1da177e4
LT		 395 u16 lnk_status;
396 int retval = 0;
397
f18e9625
KK		 398 /*
399 * Data Link Layer Link Active Reporting must be capable for
400 * hot-plug capable downstream port. But old controller might
401 * not implement it. In this case, we wait for 1000 ms.
402 */
403 if (ctrl->link_active_reporting){
404 /* Wait for Data Link Layer Link Active bit to be set */
405 pcie_wait_link_active(ctrl);
406 /*
407 * We must wait for 100 ms after the Data Link Layer
408 * Link Active bit reads 1b before initiating a
409 * configuration access to the hot added device.
410 */
411 msleep(100);
412 } else
413 msleep(1000);
414
a0f018da 415 retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
1da177e4 416 if (retval) {
18b341b7 417 ctrl_err(ctrl, "Cannot read LNKSTATUS register\n");
1da177e4
LT		 418 return retval;
419 }
420
7f2feec1 421 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
71ad556d 422 if ( (lnk_status & LNK_TRN) || (lnk_status & LNK_TRN_ERR) ||
1da177e4 423 !(lnk_status & NEG_LINK_WD)) {
18b341b7 424 ctrl_err(ctrl, "Link Training Error occurs \n");
1da177e4
LT		 425 retval = -1;
426 return retval;
427 }
428
1da177e4
LT		 429 return retval;
430}
431
1da177e4
LT		 432static int hpc_get_attention_status(struct slot *slot, u8 *status)
433{
48fe3915 434 struct controller *ctrl = slot->ctrl;
1da177e4
LT		 435 u16 slot_ctrl;
436 u8 atten_led_state;
437 int retval = 0;
1da177e4 438
a0f018da 439 retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
1da177e4 440 if (retval) {
7f2feec1 441 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
1da177e4
LT		 442 return retval;
443 }
444
7f2feec1
TI		 445 ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n",
446 __func__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
1da177e4
LT		 447
448 atten_led_state = (slot_ctrl & ATTN_LED_CTRL) >> 6;
449
450 switch (atten_led_state) {
451 case 0:
452 *status = 0xFF; /* Reserved */
453 break;
454 case 1:
455 *status = 1; /* On */
456 break;
457 case 2:
458 *status = 2; /* Blink */
459 break;
460 case 3:
461 *status = 0; /* Off */
462 break;
463 default:
464 *status = 0xFF;
465 break;
466 }
467
1da177e4
LT		 468 return 0;
469}
470
48fe3915 471static int hpc_get_power_status(struct slot *slot, u8 *status)
1da177e4 472{
48fe3915 473 struct controller *ctrl = slot->ctrl;
1da177e4
LT		 474 u16 slot_ctrl;
475 u8 pwr_state;
476 int retval = 0;
1da177e4 477
a0f018da 478 retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
1da177e4 479 if (retval) {
7f2feec1 480 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
1da177e4
LT		 481 return retval;
482 }
7f2feec1
TI		 483 ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n",
484 __func__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
1da177e4
LT		 485
486 pwr_state = (slot_ctrl & PWR_CTRL) >> 10;
487
488 switch (pwr_state) {
489 case 0:
490 *status = 1;
491 break;
492 case 1:
71ad556d 493 *status = 0;
1da177e4
LT		 494 break;
495 default:
496 *status = 0xFF;
497 break;
498 }
499
1da177e4
LT		 500 return retval;
501}
502
1da177e4
LT		 503static int hpc_get_latch_status(struct slot *slot, u8 *status)
504{
48fe3915 505 struct controller *ctrl = slot->ctrl;
1da177e4
LT		 506 u16 slot_status;
507 int retval = 0;
508
a0f018da 509 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
1da177e4 510 if (retval) {
7f2feec1
TI		 511 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
512 __func__);
1da177e4
LT		 513 return retval;
514 }
515
71ad556d 516 *status = (((slot_status & MRL_STATE) >> 5) == 0) ? 0 : 1;
1da177e4 517
1da177e4
LT		 518 return 0;
519}
520
521static int hpc_get_adapter_status(struct slot *slot, u8 *status)
522{
48fe3915 523 struct controller *ctrl = slot->ctrl;
1da177e4
LT		 524 u16 slot_status;
525 u8 card_state;
526 int retval = 0;
527
a0f018da 528 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
1da177e4 529 if (retval) {
7f2feec1
TI		 530 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
531 __func__);
1da177e4
LT		 532 return retval;
533 }
534 card_state = (u8)((slot_status & PRSN_STATE) >> 6);
535 *status = (card_state == 1) ? 1 : 0;
536
1da177e4
LT		 537 return 0;
538}
539
48fe3915 540static int hpc_query_power_fault(struct slot *slot)
1da177e4 541{
48fe3915 542 struct controller *ctrl = slot->ctrl;
1da177e4
LT		 543 u16 slot_status;
544 u8 pwr_fault;
545 int retval = 0;
1da177e4 546
a0f018da 547 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
1da177e4 548 if (retval) {
18b341b7 549 ctrl_err(ctrl, "Cannot check for power fault\n");
1da177e4
LT		 550 return retval;
551 }
552 pwr_fault = (u8)((slot_status & PWR_FAULT_DETECTED) >> 1);
71ad556d 553
8239def1 554 return pwr_fault;
1da177e4
LT		 555}
556
34d03419
KCA		 557static int hpc_get_emi_status(struct slot *slot, u8 *status)
558{
559 struct controller *ctrl = slot->ctrl;
560 u16 slot_status;
561 int retval = 0;
562
34d03419
KCA		 563 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
564 if (retval) {
18b341b7 565 ctrl_err(ctrl, "Cannot check EMI status\n");
34d03419
KCA		 566 return retval;
567 }
568 *status = (slot_status & EMI_STATE) >> EMI_STATUS_BIT;
569
34d03419
KCA		 570 return retval;
571}
572
573static int hpc_toggle_emi(struct slot *slot)
574{
f4778364
KK		 575 u16 slot_cmd;
576 u16 cmd_mask;
577 int rc;
34d03419 578
f4778364
KK		 579 slot_cmd = EMI_CTRL;
580 cmd_mask = EMI_CTRL;
c27fb883 581 rc = pcie_write_cmd(slot->ctrl, slot_cmd, cmd_mask);
34d03419 582 slot->last_emi_toggle = get_seconds();
c8426483 583
34d03419
KCA		 584 return rc;
585}
586
1da177e4
LT		 587static int hpc_set_attention_status(struct slot *slot, u8 value)
588{
48fe3915 589 struct controller *ctrl = slot->ctrl;
f4778364
KK		 590 u16 slot_cmd;
591 u16 cmd_mask;
592 int rc;
1da177e4 593
f4778364 594 cmd_mask = ATTN_LED_CTRL;
1da177e4
LT		 595 switch (value) {
596 case 0 : /* turn off */
f4778364 597 slot_cmd = 0x00C0;
1da177e4
LT		 598 break;
599 case 1: /* turn on */
f4778364 600 slot_cmd = 0x0040;
1da177e4
LT		 601 break;
602 case 2: /* turn blink */
f4778364 603 slot_cmd = 0x0080;
1da177e4
LT		 604 break;
605 default:
606 return -1;
607 }
c27fb883 608 rc = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
7f2feec1
TI		 609 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
610 __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
71ad556d 611
1da177e4
LT		 612 return rc;
613}
614
1da177e4
LT		 615static void hpc_set_green_led_on(struct slot *slot)
616{
48fe3915 617 struct controller *ctrl = slot->ctrl;
1da177e4 618 u16 slot_cmd;
f4778364 619 u16 cmd_mask;
71ad556d 620
f4778364
KK		 621 slot_cmd = 0x0100;
622 cmd_mask = PWR_LED_CTRL;
c27fb883 623 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
7f2feec1
TI		 624 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
625 __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
1da177e4
LT		 626}
627
628static void hpc_set_green_led_off(struct slot *slot)
629{
48fe3915 630 struct controller *ctrl = slot->ctrl;
1da177e4 631 u16 slot_cmd;
f4778364 632 u16 cmd_mask;
1da177e4 633
f4778364
KK		 634 slot_cmd = 0x0300;
635 cmd_mask = PWR_LED_CTRL;
c27fb883 636 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
7f2feec1
TI		 637 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
638 __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
1da177e4
LT		 639}
640
641static void hpc_set_green_led_blink(struct slot *slot)
642{
48fe3915 643 struct controller *ctrl = slot->ctrl;
1da177e4 644 u16 slot_cmd;
f4778364 645 u16 cmd_mask;
71ad556d 646
f4778364
KK		 647 slot_cmd = 0x0200;
648 cmd_mask = PWR_LED_CTRL;
c27fb883 649 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
7f2feec1
TI		 650 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
651 __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
1da177e4
LT		 652}
653
1da177e4
LT		 654static int hpc_power_on_slot(struct slot * slot)
655{
48fe3915 656 struct controller *ctrl = slot->ctrl;
1da177e4 657 u16 slot_cmd;
f4778364
KK		 658 u16 cmd_mask;
659 u16 slot_status;
1da177e4
LT		 660 int retval = 0;
661
7f2feec1 662 ctrl_dbg(ctrl, "%s: slot->hp_slot %x\n", __func__, slot->hp_slot);
1da177e4 663
5a49f203 664 /* Clear sticky power-fault bit from previous power failures */
a0f018da
KK		 665 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
666 if (retval) {
7f2feec1
TI		 667 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
668 __func__);
a0f018da
KK		 669 return retval;
670 }
5a49f203 671 slot_status &= PWR_FAULT_DETECTED;
a0f018da
KK		 672 if (slot_status) {
673 retval = pciehp_writew(ctrl, SLOTSTATUS, slot_status);
674 if (retval) {
7f2feec1
TI		 675 ctrl_err(ctrl,
676 "%s: Cannot write to SLOTSTATUS register\n",
677 __func__);
a0f018da
KK		 678 return retval;
679 }
680 }
1da177e4 681
f4778364
KK		 682 slot_cmd = POWER_ON;
683 cmd_mask = PWR_CTRL;
c7ab337f 684 /* Enable detection that we turned off at slot power-off time */
f4778364 685 if (!pciehp_poll_mode) {
cff00654
KK		 686 slot_cmd |= (PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE |
687 PRSN_DETECT_ENABLE);
688 cmd_mask |= (PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE |
689 PRSN_DETECT_ENABLE);
f4778364 690 }
1da177e4 691
c27fb883 692 retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
1da177e4
LT		 693
694 if (retval) {
18b341b7 695 ctrl_err(ctrl, "Write %x command failed!\n", slot_cmd);
1da177e4
LT		 696 return -1;
697 }
7f2feec1
TI		 698 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
699 __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
1da177e4 700
1da177e4
LT		 701 return retval;
702}
703
f1050a35
KK		 704static inline int pcie_mask_bad_dllp(struct controller *ctrl)
705{
706 struct pci_dev *dev = ctrl->pci_dev;
707 int pos;
708 u32 reg;
709
710 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
711 if (!pos)
712 return 0;
713 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &reg);
714 if (reg & PCI_ERR_COR_BAD_DLLP)
715 return 0;
716 reg |= PCI_ERR_COR_BAD_DLLP;
717 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg);
718 return 1;
719}
720
721static inline void pcie_unmask_bad_dllp(struct controller *ctrl)
722{
723 struct pci_dev *dev = ctrl->pci_dev;
724 u32 reg;
725 int pos;
726
727 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
728 if (!pos)
729 return;
730 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &reg);
731 if (!(reg & PCI_ERR_COR_BAD_DLLP))
732 return;
733 reg &= ~PCI_ERR_COR_BAD_DLLP;
734 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg);
735}
736
1da177e4
LT		 737static int hpc_power_off_slot(struct slot * slot)
738{
48fe3915 739 struct controller *ctrl = slot->ctrl;
1da177e4 740 u16 slot_cmd;
f4778364 741 u16 cmd_mask;
1da177e4 742 int retval = 0;
f1050a35 743 int changed;
1da177e4 744
7f2feec1 745 ctrl_dbg(ctrl, "%s: slot->hp_slot %x\n", __func__, slot->hp_slot);
1da177e4 746
f1050a35
KK		 747 /*
748 * Set Bad DLLP Mask bit in Correctable Error Mask
749 * Register. This is the workaround against Bad DLLP error
750 * that sometimes happens during turning power off the slot
751 * which conforms to PCI Express 1.0a spec.
752 */
753 changed = pcie_mask_bad_dllp(ctrl);
754
f4778364
KK		 755 slot_cmd = POWER_OFF;
756 cmd_mask = PWR_CTRL;
c7ab337f
TS		 757 /*
758 * If we get MRL or presence detect interrupts now, the isr
759 * will notice the sticky power-fault bit too and issue power
760 * indicator change commands. This will lead to an endless loop
761 * of command completions, since the power-fault bit remains on
762 * till the slot is powered on again.
763 */
f4778364 764 if (!pciehp_poll_mode) {
cff00654
KK		 765 slot_cmd &= ~(PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE |
766 PRSN_DETECT_ENABLE);
767 cmd_mask |= (PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE |
768 PRSN_DETECT_ENABLE);
f4778364 769 }
1da177e4 770
c27fb883 771 retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
1da177e4 772 if (retval) {
18b341b7 773 ctrl_err(ctrl, "Write command failed!\n");
c1ef5cbd
KK		 774 retval = -1;
775 goto out;
1da177e4 776 }
7f2feec1
TI		 777 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
778 __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
c1ef5cbd 779 out:
f1050a35
KK		 780 if (changed)
781 pcie_unmask_bad_dllp(ctrl);
782
1da177e4
LT		 783 return retval;
784}
785
48fe3915 786static irqreturn_t pcie_isr(int irq, void *dev_id)
1da177e4 787{
48fe3915 788 struct controller *ctrl = (struct controller *)dev_id;
c6b069e9 789 u16 detected, intr_loc;
dbd79aed 790 struct slot *p_slot;
1da177e4 791
c6b069e9
KK		 792 /*
793 * In order to guarantee that all interrupt events are
794 * serviced, we need to re-inspect Slot Status register after
795 * clearing what is presumed to be the last pending interrupt.
796 */
797 intr_loc = 0;
798 do {
799 if (pciehp_readw(ctrl, SLOTSTATUS, &detected)) {
7f2feec1
TI		 800 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS\n",
801 __func__);
1da177e4
LT		 802 return IRQ_NONE;
803 }
804
c6b069e9
KK		 805 detected &= (ATTN_BUTTN_PRESSED | PWR_FAULT_DETECTED |
806 MRL_SENS_CHANGED | PRSN_DETECT_CHANGED |
807 CMD_COMPLETED);
808 intr_loc |= detected;
809 if (!intr_loc)
1da177e4 810 return IRQ_NONE;
6a3f0849 811 if (detected && pciehp_writew(ctrl, SLOTSTATUS, detected)) {
7f2feec1
TI		 812 ctrl_err(ctrl, "%s: Cannot write to SLOTSTATUS\n",
813 __func__);
1da177e4
LT		 814 return IRQ_NONE;
815 }
c6b069e9 816 } while (detected);
71ad556d 817
7f2feec1 818 ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc);
71ad556d 819
c6b069e9 820 /* Check Command Complete Interrupt Pending */
1da177e4 821 if (intr_loc & CMD_COMPLETED) {
262303fe 822 ctrl->cmd_busy = 0;
2d32a9ae 823 smp_mb();
d737bdc1 824 wake_up(&ctrl->queue);
1da177e4
LT		 825 }
826
dbd79aed
KK		 827 if (!(intr_loc & ~CMD_COMPLETED))
828 return IRQ_HANDLED;
829
dbd79aed 830 p_slot = pciehp_find_slot(ctrl, ctrl->slot_device_offset);
dbd79aed 831
c6b069e9 832 /* Check MRL Sensor Changed */
48fe3915 833 if (intr_loc & MRL_SENS_CHANGED)
dbd79aed 834 pciehp_handle_switch_change(p_slot);
48fe3915 835
c6b069e9 836 /* Check Attention Button Pressed */
48fe3915 837 if (intr_loc & ATTN_BUTTN_PRESSED)
dbd79aed 838 pciehp_handle_attention_button(p_slot);
48fe3915 839
c6b069e9 840 /* Check Presence Detect Changed */
48fe3915 841 if (intr_loc & PRSN_DETECT_CHANGED)
dbd79aed 842 pciehp_handle_presence_change(p_slot);
48fe3915 843
c6b069e9 844 /* Check Power Fault Detected */
48fe3915 845 if (intr_loc & PWR_FAULT_DETECTED)
dbd79aed 846 pciehp_handle_power_fault(p_slot);
71ad556d 847
1da177e4
LT		 848 return IRQ_HANDLED;
849}
850
40730d10 851static int hpc_get_max_lnk_speed(struct slot *slot, enum pci_bus_speed *value)
1da177e4 852{
48fe3915 853 struct controller *ctrl = slot->ctrl;
1da177e4
LT		 854 enum pcie_link_speed lnk_speed;
855 u32 lnk_cap;
856 int retval = 0;
857
a0f018da 858 retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap);
1da177e4 859 if (retval) {
7f2feec1 860 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__);
1da177e4
LT		 861 return retval;
862 }
863
864 switch (lnk_cap & 0x000F) {
865 case 1:
866 lnk_speed = PCIE_2PT5GB;
867 break;
868 default:
869 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
870 break;
871 }
872
873 *value = lnk_speed;
7f2feec1 874 ctrl_dbg(ctrl, "Max link speed = %d\n", lnk_speed);
c8426483 875
1da177e4
LT		 876 return retval;
877}
878
40730d10
KK		 879static int hpc_get_max_lnk_width(struct slot *slot,
880 enum pcie_link_width *value)
1da177e4 881{
48fe3915 882 struct controller *ctrl = slot->ctrl;
1da177e4
LT		 883 enum pcie_link_width lnk_wdth;
884 u32 lnk_cap;
885 int retval = 0;
886
a0f018da 887 retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap);
1da177e4 888 if (retval) {
7f2feec1 889 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__);
1da177e4
LT		 890 return retval;
891 }
892
893 switch ((lnk_cap & 0x03F0) >> 4){
894 case 0:
895 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
896 break;
897 case 1:
898 lnk_wdth = PCIE_LNK_X1;
899 break;
900 case 2:
901 lnk_wdth = PCIE_LNK_X2;
902 break;
903 case 4:
904 lnk_wdth = PCIE_LNK_X4;
905 break;
906 case 8:
907 lnk_wdth = PCIE_LNK_X8;
908 break;
909 case 12:
910 lnk_wdth = PCIE_LNK_X12;
911 break;
912 case 16:
913 lnk_wdth = PCIE_LNK_X16;
914 break;
915 case 32:
916 lnk_wdth = PCIE_LNK_X32;
917 break;
918 default:
919 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
920 break;
921 }
922
923 *value = lnk_wdth;
7f2feec1 924 ctrl_dbg(ctrl, "Max link width = %d\n", lnk_wdth);
c8426483 925
1da177e4
LT		 926 return retval;
927}
928
40730d10 929static int hpc_get_cur_lnk_speed(struct slot *slot, enum pci_bus_speed *value)
1da177e4 930{
48fe3915 931 struct controller *ctrl = slot->ctrl;
1da177e4
LT		 932 enum pcie_link_speed lnk_speed = PCI_SPEED_UNKNOWN;
933 int retval = 0;
934 u16 lnk_status;
935
a0f018da 936 retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
1da177e4 937 if (retval) {
7f2feec1
TI		 938 ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n",
939 __func__);
1da177e4
LT		 940 return retval;
941 }
942
943 switch (lnk_status & 0x0F) {
944 case 1:
945 lnk_speed = PCIE_2PT5GB;
946 break;
947 default:
948 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
949 break;
950 }
951
952 *value = lnk_speed;
7f2feec1 953 ctrl_dbg(ctrl, "Current link speed = %d\n", lnk_speed);
c8426483 954
1da177e4
LT		 955 return retval;
956}
957
40730d10
KK		 958static int hpc_get_cur_lnk_width(struct slot *slot,
959 enum pcie_link_width *value)
1da177e4 960{
48fe3915 961 struct controller *ctrl = slot->ctrl;
1da177e4
LT		 962 enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
963 int retval = 0;
964 u16 lnk_status;
965
a0f018da 966 retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
1da177e4 967 if (retval) {
7f2feec1
TI		 968 ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n",
969 __func__);
1da177e4
LT		 970 return retval;
971 }
71ad556d 972
1da177e4
LT		 973 switch ((lnk_status & 0x03F0) >> 4){
974 case 0:
975 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
976 break;
977 case 1:
978 lnk_wdth = PCIE_LNK_X1;
979 break;
980 case 2:
981 lnk_wdth = PCIE_LNK_X2;
982 break;
983 case 4:
984 lnk_wdth = PCIE_LNK_X4;
985 break;
986 case 8:
987 lnk_wdth = PCIE_LNK_X8;
988 break;
989 case 12:
990 lnk_wdth = PCIE_LNK_X12;
991 break;
992 case 16:
993 lnk_wdth = PCIE_LNK_X16;
994 break;
995 case 32:
996 lnk_wdth = PCIE_LNK_X32;
997 break;
998 default:
999 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
1000 break;
1001 }
1002
1003 *value = lnk_wdth;
7f2feec1 1004 ctrl_dbg(ctrl, "Current link width = %d\n", lnk_wdth);
c8426483 1005
1da177e4
LT		 1006 return retval;
1007}
1008
c4635eb0 1009static void pcie_release_ctrl(struct controller *ctrl);
1da177e4
LT		 1010static struct hpc_ops pciehp_hpc_ops = {
1011 .power_on_slot = hpc_power_on_slot,
1012 .power_off_slot = hpc_power_off_slot,
1013 .set_attention_status = hpc_set_attention_status,
1014 .get_power_status = hpc_get_power_status,
1015 .get_attention_status = hpc_get_attention_status,
1016 .get_latch_status = hpc_get_latch_status,
1017 .get_adapter_status = hpc_get_adapter_status,
34d03419
KCA		 1018 .get_emi_status = hpc_get_emi_status,
1019 .toggle_emi = hpc_toggle_emi,
1da177e4
LT		 1020
1021 .get_max_bus_speed = hpc_get_max_lnk_speed,
1022 .get_cur_bus_speed = hpc_get_cur_lnk_speed,
1023 .get_max_lnk_width = hpc_get_max_lnk_width,
1024 .get_cur_lnk_width = hpc_get_cur_lnk_width,
71ad556d 1025
1da177e4
LT		 1026 .query_power_fault = hpc_query_power_fault,
1027 .green_led_on = hpc_set_green_led_on,
1028 .green_led_off = hpc_set_green_led_off,
1029 .green_led_blink = hpc_set_green_led_blink,
71ad556d 1030
c4635eb0 1031 .release_ctlr = pcie_release_ctrl,
1da177e4
LT		 1032 .check_lnk_status = hpc_check_lnk_status,
1033};
1034
c4635eb0 1035int pcie_enable_notification(struct controller *ctrl)
ecdde939 1036{
c27fb883 1037 u16 cmd, mask;
1da177e4 1038
c27fb883 1039 cmd = PRSN_DETECT_ENABLE;
ae416e6b 1040 if (ATTN_BUTTN(ctrl))
c27fb883 1041 cmd |= ATTN_BUTTN_ENABLE;
ae416e6b 1042 if (POWER_CTRL(ctrl))
c27fb883 1043 cmd |= PWR_FAULT_DETECT_ENABLE;
ae416e6b 1044 if (MRL_SENS(ctrl))
c27fb883
KK		 1045 cmd |= MRL_DETECT_ENABLE;
1046 if (!pciehp_poll_mode)
3aa50c44 1047 cmd |= HP_INTR_ENABLE | CMD_CMPL_INTR_ENABLE;
c27fb883 1048
3aa50c44
KK		 1049 mask = PRSN_DETECT_ENABLE | ATTN_BUTTN_ENABLE | MRL_DETECT_ENABLE |
1050 PWR_FAULT_DETECT_ENABLE | HP_INTR_ENABLE | CMD_CMPL_INTR_ENABLE;
c27fb883
KK		 1051
1052 if (pcie_write_cmd(ctrl, cmd, mask)) {
18b341b7 1053 ctrl_err(ctrl, "Cannot enable software notification\n");
125c39f7 1054 return -1;
1da177e4 1055 }
c4635eb0
KK		 1056 return 0;
1057}
1058
1059static void pcie_disable_notification(struct controller *ctrl)
1060{
1061 u16 mask;
1062 mask = PRSN_DETECT_ENABLE | ATTN_BUTTN_ENABLE | MRL_DETECT_ENABLE |
1063 PWR_FAULT_DETECT_ENABLE | HP_INTR_ENABLE | CMD_CMPL_INTR_ENABLE;
1064 if (pcie_write_cmd(ctrl, 0, mask))
18b341b7 1065 ctrl_warn(ctrl, "Cannot disable software notification\n");
c4635eb0
KK		 1066}
1067
1068static int pcie_init_notification(struct controller *ctrl)
1069{
1070 if (pciehp_request_irq(ctrl))
1071 return -1;
1072 if (pcie_enable_notification(ctrl)) {
1073 pciehp_free_irq(ctrl);
1074 return -1;
1075 }
1076 return 0;
1077}
1078
1079static void pcie_shutdown_notification(struct controller *ctrl)
1080{
1081 pcie_disable_notification(ctrl);
1082 pciehp_free_irq(ctrl);
1083}
1084
c4635eb0
KK		 1085static int pcie_init_slot(struct controller *ctrl)
1086{
1087 struct slot *slot;
1088
1089 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
1090 if (!slot)
1091 return -ENOMEM;
1092
1093 slot->hp_slot = 0;
1094 slot->ctrl = ctrl;
1095 slot->bus = ctrl->pci_dev->subordinate->number;
1096 slot->device = ctrl->slot_device_offset + slot->hp_slot;
1097 slot->hpc_ops = ctrl->hpc_ops;
1098 slot->number = ctrl->first_slot;
c4635eb0
KK		 1099 mutex_init(&slot->lock);
1100 INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work);
1101 list_add(&slot->slot_list, &ctrl->slot_list);
1da177e4 1102 return 0;
1da177e4 1103}
08e7a7d2 1104
c4635eb0
KK		 1105static void pcie_cleanup_slot(struct controller *ctrl)
1106{
1107 struct slot *slot;
1108 slot = list_first_entry(&ctrl->slot_list, struct slot, slot_list);
1109 list_del(&slot->slot_list);
1110 cancel_delayed_work(&slot->work);
1111 flush_scheduled_work();
1112 flush_workqueue(pciehp_wq);
1113 kfree(slot);
1114}
1115
2aeeef11 1116static inline void dbg_ctrl(struct controller *ctrl)
08e7a7d2 1117{
2aeeef11
KK		 1118 int i;
1119 u16 reg16;
1120 struct pci_dev *pdev = ctrl->pci_dev;
08e7a7d2 1121
2aeeef11
KK		 1122 if (!pciehp_debug)
1123 return;
08e7a7d2 1124
7f2feec1
TI		 1125 ctrl_info(ctrl, "Hotplug Controller:\n");
1126 ctrl_info(ctrl, " Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n",
1127 pci_name(pdev), pdev->irq);
1128 ctrl_info(ctrl, " Vendor ID : 0x%04x\n", pdev->vendor);
1129 ctrl_info(ctrl, " Device ID : 0x%04x\n", pdev->device);
1130 ctrl_info(ctrl, " Subsystem ID : 0x%04x\n",
1131 pdev->subsystem_device);
1132 ctrl_info(ctrl, " Subsystem Vendor ID : 0x%04x\n",
1133 pdev->subsystem_vendor);
1134 ctrl_info(ctrl, " PCIe Cap offset : 0x%02x\n", ctrl->cap_base);
2aeeef11
KK		 1135 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1136 if (!pci_resource_len(pdev, i))
1137 continue;
7f2feec1
TI		 1138 ctrl_info(ctrl, " PCI resource [%d] : 0x%llx@0x%llx\n",
1139 i, (unsigned long long)pci_resource_len(pdev, i),
1140 (unsigned long long)pci_resource_start(pdev, i));
08e7a7d2 1141 }
7f2feec1
TI		 1142 ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap);
1143 ctrl_info(ctrl, " Physical Slot Number : %d\n", ctrl->first_slot);
1144 ctrl_info(ctrl, " Attention Button : %3s\n",
1145 ATTN_BUTTN(ctrl) ? "yes" : "no");
1146 ctrl_info(ctrl, " Power Controller : %3s\n",
1147 POWER_CTRL(ctrl) ? "yes" : "no");
1148 ctrl_info(ctrl, " MRL Sensor : %3s\n",
1149 MRL_SENS(ctrl) ? "yes" : "no");
1150 ctrl_info(ctrl, " Attention Indicator : %3s\n",
1151 ATTN_LED(ctrl) ? "yes" : "no");
1152 ctrl_info(ctrl, " Power Indicator : %3s\n",
1153 PWR_LED(ctrl) ? "yes" : "no");
1154 ctrl_info(ctrl, " Hot-Plug Surprise : %3s\n",
1155 HP_SUPR_RM(ctrl) ? "yes" : "no");
1156 ctrl_info(ctrl, " EMI Present : %3s\n",
1157 EMI(ctrl) ? "yes" : "no");
1158 ctrl_info(ctrl, " Command Completed : %3s\n",
1159 NO_CMD_CMPL(ctrl) ? "no" : "yes");
2aeeef11 1160 pciehp_readw(ctrl, SLOTSTATUS, &reg16);
7f2feec1 1161 ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16);
d8b23e8f 1162 pciehp_readw(ctrl, SLOTCTRL, &reg16);
7f2feec1 1163 ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16);
2aeeef11 1164}
08e7a7d2 1165
c4635eb0 1166struct controller *pcie_init(struct pcie_device *dev)
2aeeef11 1167{
c4635eb0 1168 struct controller *ctrl;
f18e9625 1169 u32 slot_cap, link_cap;
2aeeef11 1170 struct pci_dev *pdev = dev->port;
08e7a7d2 1171
c4635eb0
KK		 1172 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
1173 if (!ctrl) {
18b341b7 1174 dev_err(&dev->device, "%s: Out of memory\n", __func__);
c4635eb0
KK		 1175 goto abort;
1176 }
1177 INIT_LIST_HEAD(&ctrl->slot_list);
1178
f7a10e32 1179 ctrl->pcie = dev;
2aeeef11
KK		 1180 ctrl->pci_dev = pdev;
1181 ctrl->cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1182 if (!ctrl->cap_base) {
18b341b7 1183 ctrl_err(ctrl, "Cannot find PCI Express capability\n");
b84346ef 1184 goto abort_ctrl;
08e7a7d2 1185 }
2aeeef11 1186 if (pciehp_readl(ctrl, SLOTCAP, &slot_cap)) {
18b341b7 1187 ctrl_err(ctrl, "Cannot read SLOTCAP register\n");
b84346ef 1188 goto abort_ctrl;
08e7a7d2 1189 }
08e7a7d2 1190
2aeeef11
KK		 1191 ctrl->slot_cap = slot_cap;
1192 ctrl->first_slot = slot_cap >> 19;
1193 ctrl->slot_device_offset = 0;
1194 ctrl->num_slots = 1;
1195 ctrl->hpc_ops = &pciehp_hpc_ops;
08e7a7d2
ML		 1196 mutex_init(&ctrl->crit_sect);
1197 mutex_init(&ctrl->ctrl_lock);
08e7a7d2 1198 init_waitqueue_head(&ctrl->queue);
2aeeef11 1199 dbg_ctrl(ctrl);
5808639b
KK		 1200 /*
1201 * Controller doesn't notify of command completion if the "No
1202 * Command Completed Support" bit is set in Slot Capability
1203 * register or the controller supports none of power
1204 * controller, attention led, power led and EMI.
1205 */
1206 if (NO_CMD_CMPL(ctrl) ||
1207 !(POWER_CTRL(ctrl) | ATTN_LED(ctrl) | PWR_LED(ctrl) | EMI(ctrl)))
1208 ctrl->no_cmd_complete = 1;
08e7a7d2 1209
f18e9625
KK		 1210 /* Check if Data Link Layer Link Active Reporting is implemented */
1211 if (pciehp_readl(ctrl, LNKCAP, &link_cap)) {
1212 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__);
1213 goto abort_ctrl;
1214 }
1215 if (link_cap & LINK_ACTIVE_REPORTING) {
1216 ctrl_dbg(ctrl, "Link Active Reporting supported\n");
1217 ctrl->link_active_reporting = 1;
1218 }
1219
c4635eb0
KK		 1220 /* Clear all remaining event bits in Slot Status register */
1221 if (pciehp_writew(ctrl, SLOTSTATUS, 0x1f))
1222 goto abort_ctrl;
08e7a7d2 1223
c4635eb0
KK		 1224 /* Disable sotfware notification */
1225 pcie_disable_notification(ctrl);
ecdde939
ML		 1226
1227 /*
1228 * If this is the first controller to be initialized,
1229 * initialize the pciehp work queue
1230 */
1231 if (atomic_add_return(1, &pciehp_num_controllers) == 1) {
1232 pciehp_wq = create_singlethread_workqueue("pciehpd");
c4635eb0
KK		 1233 if (!pciehp_wq)
1234 goto abort_ctrl;
ecdde939
ML		 1235 }
1236
7f2feec1
TI		 1237 ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",
1238 pdev->vendor, pdev->device, pdev->subsystem_vendor,
1239 pdev->subsystem_device);
c4635eb0
KK		 1240
1241 if (pcie_init_slot(ctrl))
1242 goto abort_ctrl;
2aeeef11 1243
c4635eb0
KK		 1244 if (pcie_init_notification(ctrl))
1245 goto abort_slot;
2aeeef11 1246
c4635eb0
KK		 1247 return ctrl;
1248
1249abort_slot:
1250 pcie_cleanup_slot(ctrl);
1251abort_ctrl:
1252 kfree(ctrl);
08e7a7d2 1253abort:
c4635eb0
KK		 1254 return NULL;
1255}
1256
1257void pcie_release_ctrl(struct controller *ctrl)
1258{
1259 pcie_shutdown_notification(ctrl);
1260 pcie_cleanup_slot(ctrl);
1261 /*
1262 * If this is the last controller to be released, destroy the
1263 * pciehp work queue
1264 */
1265 if (atomic_dec_and_test(&pciehp_num_controllers))
1266 destroy_workqueue(pciehp_wq);
1267 kfree(ctrl);
08e7a7d2 1268}
Linux kernel - Deliverables
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