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pcnet-cs: declare MODULE_FIRMWARE
[deliverable/linux.git] / drivers / pci / intel-iommu.c
CommitLineData
ba395927
KA		 1/*
2 * Copyright (c) 2006, Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
15 * Place - Suite 330, Boston, MA 02111-1307 USA.
16 *
98bcef56 17 * Copyright (C) 2006-2008 Intel Corporation
18 * Author: Ashok Raj <ashok.raj@intel.com>
19 * Author: Shaohua Li <shaohua.li@intel.com>
20 * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
5b6985ce 21 * Author: Fenghua Yu <fenghua.yu@intel.com>
ba395927
KA		 22 */
23
24#include <linux/init.h>
25#include <linux/bitmap.h>
5e0d2a6f 26#include <linux/debugfs.h>
ba395927
KA		 27#include <linux/slab.h>
28#include <linux/irq.h>
29#include <linux/interrupt.h>
ba395927
KA		 30#include <linux/spinlock.h>
31#include <linux/pci.h>
32#include <linux/dmar.h>
33#include <linux/dma-mapping.h>
34#include <linux/mempool.h>
5e0d2a6f 35#include <linux/timer.h>
38717946 36#include <linux/iova.h>
5d450806 37#include <linux/iommu.h>
38717946 38#include <linux/intel-iommu.h>
f59c7b69 39#include <linux/sysdev.h>
69575d38 40#include <linux/tboot.h>
adb2fe02 41#include <linux/dmi.h>
ba395927 42#include <asm/cacheflush.h>
46a7fa27 43#include <asm/iommu.h>
ba395927
KA		 44#include "pci.h"
45
5b6985ce
FY		 46#define ROOT_SIZE VTD_PAGE_SIZE
47#define CONTEXT_SIZE VTD_PAGE_SIZE
48
ba395927
KA		 49#define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
50#define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
51
52#define IOAPIC_RANGE_START (0xfee00000)
53#define IOAPIC_RANGE_END (0xfeefffff)
54#define IOVA_START_ADDR (0x1000)
55
56#define DEFAULT_DOMAIN_ADDRESS_WIDTH 48
57
4ed0d3e6
FY		 58#define MAX_AGAW_WIDTH 64
59
2ebe3151
DW		 60#define __DOMAIN_MAX_PFN(gaw) ((((uint64_t)1) << (gaw-VTD_PAGE_SHIFT)) - 1)
61#define __DOMAIN_MAX_ADDR(gaw) ((((uint64_t)1) << gaw) - 1)
62
63/* We limit DOMAIN_MAX_PFN to fit in an unsigned long, and DOMAIN_MAX_ADDR
64 to match. That way, we can use 'unsigned long' for PFNs with impunity. */
65#define DOMAIN_MAX_PFN(gaw) ((unsigned long) min_t(uint64_t, \
66 __DOMAIN_MAX_PFN(gaw), (unsigned long)-1))
67#define DOMAIN_MAX_ADDR(gaw) (((uint64_t)__DOMAIN_MAX_PFN(gaw)) << VTD_PAGE_SHIFT)
ba395927 68
f27be03b 69#define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
284901a9 70#define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32))
6a35528a 71#define DMA_64BIT_PFN IOVA_PFN(DMA_BIT_MASK(64))
5e0d2a6f 72
fd18de50 73
dd4e8319
DW		 74/* VT-d pages must always be _smaller_ than MM pages. Otherwise things
75 are never going to work. */
76static inline unsigned long dma_to_mm_pfn(unsigned long dma_pfn)
77{
78 return dma_pfn >> (PAGE_SHIFT - VTD_PAGE_SHIFT);
79}
80
81static inline unsigned long mm_to_dma_pfn(unsigned long mm_pfn)
82{
83 return mm_pfn << (PAGE_SHIFT - VTD_PAGE_SHIFT);
84}
85static inline unsigned long page_to_dma_pfn(struct page *pg)
86{
87 return mm_to_dma_pfn(page_to_pfn(pg));
88}
89static inline unsigned long virt_to_dma_pfn(void *p)
90{
91 return page_to_dma_pfn(virt_to_page(p));
92}
93
d9630fe9
WH		 94/* global iommu list, set NULL for ignored DMAR units */
95static struct intel_iommu **g_iommus;
96
9af88143
DW		 97static int rwbf_quirk;
98
46b08e1a
MM		 99/*
100 * 0: Present
101 * 1-11: Reserved
102 * 12-63: Context Ptr (12 - (haw-1))
103 * 64-127: Reserved
104 */
105struct root_entry {
106 u64 val;
107 u64 rsvd1;
108};
109#define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry))
110static inline bool root_present(struct root_entry *root)
111{
112 return (root->val & 1);
113}
114static inline void set_root_present(struct root_entry *root)
115{
116 root->val |= 1;
117}
118static inline void set_root_value(struct root_entry *root, unsigned long value)
119{
120 root->val |= value & VTD_PAGE_MASK;
121}
122
123static inline struct context_entry *
124get_context_addr_from_root(struct root_entry *root)
125{
126 return (struct context_entry *)
127 (root_present(root)?phys_to_virt(
128 root->val & VTD_PAGE_MASK) :
129 NULL);
130}
131
7a8fc25e
MM		 132/*
133 * low 64 bits:
134 * 0: present
135 * 1: fault processing disable
136 * 2-3: translation type
137 * 12-63: address space root
138 * high 64 bits:
139 * 0-2: address width
140 * 3-6: aval
141 * 8-23: domain id
142 */
143struct context_entry {
144 u64 lo;
145 u64 hi;
146};
c07e7d21
MM		 147
148static inline bool context_present(struct context_entry *context)
149{
150 return (context->lo & 1);
151}
152static inline void context_set_present(struct context_entry *context)
153{
154 context->lo |= 1;
155}
156
157static inline void context_set_fault_enable(struct context_entry *context)
158{
159 context->lo &= (((u64)-1) << 2) | 1;
160}
161
c07e7d21
MM		 162static inline void context_set_translation_type(struct context_entry *context,
163 unsigned long value)
164{
165 context->lo &= (((u64)-1) << 4) | 3;
166 context->lo |= (value & 3) << 2;
167}
168
169static inline void context_set_address_root(struct context_entry *context,
170 unsigned long value)
171{
172 context->lo |= value & VTD_PAGE_MASK;
173}
174
175static inline void context_set_address_width(struct context_entry *context,
176 unsigned long value)
177{
178 context->hi |= value & 7;
179}
180
181static inline void context_set_domain_id(struct context_entry *context,
182 unsigned long value)
183{
184 context->hi |= (value & ((1 << 16) - 1)) << 8;
185}
186
187static inline void context_clear_entry(struct context_entry *context)
188{
189 context->lo = 0;
190 context->hi = 0;
191}
7a8fc25e 192
622ba12a
MM		 193/*
194 * 0: readable
195 * 1: writable
196 * 2-6: reserved
197 * 7: super page
9cf06697
SY		 198 * 8-10: available
199 * 11: snoop behavior
622ba12a
MM		 200 * 12-63: Host physcial address
201 */
202struct dma_pte {
203 u64 val;
204};
622ba12a 205
19c239ce
MM		 206static inline void dma_clear_pte(struct dma_pte *pte)
207{
208 pte->val = 0;
209}
210
211static inline void dma_set_pte_readable(struct dma_pte *pte)
212{
213 pte->val |= DMA_PTE_READ;
214}
215
216static inline void dma_set_pte_writable(struct dma_pte *pte)
217{
218 pte->val |= DMA_PTE_WRITE;
219}
220
9cf06697
SY		 221static inline void dma_set_pte_snp(struct dma_pte *pte)
222{
223 pte->val |= DMA_PTE_SNP;
224}
225
19c239ce
MM		 226static inline void dma_set_pte_prot(struct dma_pte *pte, unsigned long prot)
227{
228 pte->val = (pte->val & ~3) | (prot & 3);
229}
230
231static inline u64 dma_pte_addr(struct dma_pte *pte)
232{
c85994e4
DW		 233#ifdef CONFIG_64BIT
234 return pte->val & VTD_PAGE_MASK;
235#else
236 /* Must have a full atomic 64-bit read */
237 return __cmpxchg64(pte, 0ULL, 0ULL) & VTD_PAGE_MASK;
238#endif
19c239ce
MM		 239}
240
dd4e8319 241static inline void dma_set_pte_pfn(struct dma_pte *pte, unsigned long pfn)
19c239ce 242{
dd4e8319 243 pte->val |= (uint64_t)pfn << VTD_PAGE_SHIFT;
19c239ce
MM		 244}
245
246static inline bool dma_pte_present(struct dma_pte *pte)
247{
248 return (pte->val & 3) != 0;
249}
622ba12a 250
75e6bf96
DW		 251static inline int first_pte_in_page(struct dma_pte *pte)
252{
253 return !((unsigned long)pte & ~VTD_PAGE_MASK);
254}
255
2c2e2c38
FY		 256/*
257 * This domain is a statically identity mapping domain.
258 * 1. This domain creats a static 1:1 mapping to all usable memory.
259 * 2. It maps to each iommu if successful.
260 * 3. Each iommu mapps to this domain if successful.
261 */
19943b0e
DW		 262static struct dmar_domain *si_domain;
263static int hw_pass_through = 1;
2c2e2c38 264
3b5410e7 265/* devices under the same p2p bridge are owned in one domain */
cdc7b837 266#define DOMAIN_FLAG_P2P_MULTIPLE_DEVICES (1 << 0)
3b5410e7 267
1ce28feb
WH		 268/* domain represents a virtual machine, more than one devices
269 * across iommus may be owned in one domain, e.g. kvm guest.
270 */
271#define DOMAIN_FLAG_VIRTUAL_MACHINE (1 << 1)
272
2c2e2c38
FY		 273/* si_domain contains mulitple devices */
274#define DOMAIN_FLAG_STATIC_IDENTITY (1 << 2)
275
99126f7c
MM		 276struct dmar_domain {
277 int id; /* domain id */
8c11e798 278 unsigned long iommu_bmp; /* bitmap of iommus this domain uses*/
99126f7c
MM		 279
280 struct list_head devices; /* all devices' list */
281 struct iova_domain iovad; /* iova's that belong to this domain */
282
283 struct dma_pte *pgd; /* virtual address */
99126f7c
MM		 284 int gaw; /* max guest address width */
285
286 /* adjusted guest address width, 0 is level 2 30-bit */
287 int agaw;
288
3b5410e7 289 int flags; /* flags to find out type of domain */
8e604097
WH		 290
291 int iommu_coherency;/* indicate coherency of iommu access */
58c610bd 292 int iommu_snooping; /* indicate snooping control feature*/
c7151a8d
WH		 293 int iommu_count; /* reference count of iommu */
294 spinlock_t iommu_lock; /* protect iommu set in domain */
fe40f1e0 295 u64 max_addr; /* maximum mapped address */
99126f7c
MM		 296};
297
a647dacb
MM		 298/* PCI domain-device relationship */
299struct device_domain_info {
300 struct list_head link; /* link to domain siblings */
301 struct list_head global; /* link to global list */
276dbf99
DW		 302 int segment; /* PCI domain */
303 u8 bus; /* PCI bus number */
a647dacb
MM		 304 u8 devfn; /* PCI devfn number */
305 struct pci_dev *dev; /* it's NULL for PCIE-to-PCI bridge */
93a23a72 306 struct intel_iommu *iommu; /* IOMMU used by this device */
a647dacb
MM		 307 struct dmar_domain *domain; /* pointer to domain */
308};
309
5e0d2a6f 310static void flush_unmaps_timeout(unsigned long data);
311
312DEFINE_TIMER(unmap_timer, flush_unmaps_timeout, 0, 0);
313
80b20dd8 314#define HIGH_WATER_MARK 250
315struct deferred_flush_tables {
316 int next;
317 struct iova *iova[HIGH_WATER_MARK];
318 struct dmar_domain *domain[HIGH_WATER_MARK];
319};
320
321static struct deferred_flush_tables *deferred_flush;
322
5e0d2a6f 323/* bitmap for indexing intel_iommus */
5e0d2a6f 324static int g_num_of_iommus;
325
326static DEFINE_SPINLOCK(async_umap_flush_lock);
327static LIST_HEAD(unmaps_to_do);
328
329static int timer_on;
330static long list_size;
5e0d2a6f 331
ba395927
KA		 332static void domain_remove_dev_info(struct dmar_domain *domain);
333
0cd5c3c8
KM		 334#ifdef CONFIG_DMAR_DEFAULT_ON
335int dmar_disabled = 0;
336#else
337int dmar_disabled = 1;
338#endif /*CONFIG_DMAR_DEFAULT_ON*/
339
ba395927 340static int __initdata dmar_map_gfx = 1;
7d3b03ce 341static int dmar_forcedac;
5e0d2a6f 342static int intel_iommu_strict;
ba395927
KA		 343
344#define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1))
345static DEFINE_SPINLOCK(device_domain_lock);
346static LIST_HEAD(device_domain_list);
347
a8bcbb0d
JR		 348static struct iommu_ops intel_iommu_ops;
349
ba395927
KA		 350static int __init intel_iommu_setup(char *str)
351{
352 if (!str)
353 return -EINVAL;
354 while (*str) {
0cd5c3c8
KM		 355 if (!strncmp(str, "on", 2)) {
356 dmar_disabled = 0;
357 printk(KERN_INFO "Intel-IOMMU: enabled\n");
358 } else if (!strncmp(str, "off", 3)) {
ba395927 359 dmar_disabled = 1;
0cd5c3c8 360 printk(KERN_INFO "Intel-IOMMU: disabled\n");
ba395927
KA		 361 } else if (!strncmp(str, "igfx_off", 8)) {
362 dmar_map_gfx = 0;
363 printk(KERN_INFO
364 "Intel-IOMMU: disable GFX device mapping\n");
7d3b03ce 365 } else if (!strncmp(str, "forcedac", 8)) {
5e0d2a6f 366 printk(KERN_INFO
7d3b03ce
KA		 367 "Intel-IOMMU: Forcing DAC for PCI devices\n");
368 dmar_forcedac = 1;
5e0d2a6f 369 } else if (!strncmp(str, "strict", 6)) {
370 printk(KERN_INFO
371 "Intel-IOMMU: disable batched IOTLB flush\n");
372 intel_iommu_strict = 1;
ba395927
KA		 373 }
374
375 str += strcspn(str, ",");
376 while (*str == ',')
377 str++;
378 }
379 return 0;
380}
381__setup("intel_iommu=", intel_iommu_setup);
382
383static struct kmem_cache *iommu_domain_cache;
384static struct kmem_cache *iommu_devinfo_cache;
385static struct kmem_cache *iommu_iova_cache;
386
eb3fa7cb
KA		 387static inline void *iommu_kmem_cache_alloc(struct kmem_cache *cachep)
388{
389 unsigned int flags;
390 void *vaddr;
391
392 /* trying to avoid low memory issues */
393 flags = current->flags & PF_MEMALLOC;
394 current->flags |= PF_MEMALLOC;
395 vaddr = kmem_cache_alloc(cachep, GFP_ATOMIC);
396 current->flags &= (~PF_MEMALLOC | flags);
397 return vaddr;
398}
399
400
ba395927
KA		 401static inline void *alloc_pgtable_page(void)
402{
eb3fa7cb
KA		 403 unsigned int flags;
404 void *vaddr;
405
406 /* trying to avoid low memory issues */
407 flags = current->flags & PF_MEMALLOC;
408 current->flags |= PF_MEMALLOC;
409 vaddr = (void *)get_zeroed_page(GFP_ATOMIC);
410 current->flags &= (~PF_MEMALLOC | flags);
411 return vaddr;
ba395927
KA		 412}
413
414static inline void free_pgtable_page(void *vaddr)
415{
416 free_page((unsigned long)vaddr);
417}
418
419static inline void *alloc_domain_mem(void)
420{
eb3fa7cb 421 return iommu_kmem_cache_alloc(iommu_domain_cache);
ba395927
KA		 422}
423
38717946 424static void free_domain_mem(void *vaddr)
ba395927
KA		 425{
426 kmem_cache_free(iommu_domain_cache, vaddr);
427}
428
429static inline void * alloc_devinfo_mem(void)
430{
eb3fa7cb 431 return iommu_kmem_cache_alloc(iommu_devinfo_cache);
ba395927
KA		 432}
433
434static inline void free_devinfo_mem(void *vaddr)
435{
436 kmem_cache_free(iommu_devinfo_cache, vaddr);
437}
438
439struct iova *alloc_iova_mem(void)
440{
eb3fa7cb 441 return iommu_kmem_cache_alloc(iommu_iova_cache);
ba395927
KA		 442}
443
444void free_iova_mem(struct iova *iova)
445{
446 kmem_cache_free(iommu_iova_cache, iova);
447}
448
1b573683
WH		 449
450static inline int width_to_agaw(int width);
451
4ed0d3e6 452static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw)
1b573683
WH		 453{
454 unsigned long sagaw;
455 int agaw = -1;
456
457 sagaw = cap_sagaw(iommu->cap);
4ed0d3e6 458 for (agaw = width_to_agaw(max_gaw);
1b573683
WH		 459 agaw >= 0; agaw--) {
460 if (test_bit(agaw, &sagaw))
461 break;
462 }
463
464 return agaw;
465}
466
4ed0d3e6
FY		 467/*
468 * Calculate max SAGAW for each iommu.
469 */
470int iommu_calculate_max_sagaw(struct intel_iommu *iommu)
471{
472 return __iommu_calculate_agaw(iommu, MAX_AGAW_WIDTH);
473}
474
475/*
476 * calculate agaw for each iommu.
477 * "SAGAW" may be different across iommus, use a default agaw, and
478 * get a supported less agaw for iommus that don't support the default agaw.
479 */
480int iommu_calculate_agaw(struct intel_iommu *iommu)
481{
482 return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH);
483}
484
2c2e2c38 485/* This functionin only returns single iommu in a domain */
8c11e798
WH		 486static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain)
487{
488 int iommu_id;
489
2c2e2c38 490 /* si_domain and vm domain should not get here. */
1ce28feb 491 BUG_ON(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE);
2c2e2c38 492 BUG_ON(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY);
1ce28feb 493
8c11e798
WH		 494 iommu_id = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
495 if (iommu_id < 0 || iommu_id >= g_num_of_iommus)
496 return NULL;
497
498 return g_iommus[iommu_id];
499}
500
8e604097
WH		 501static void domain_update_iommu_coherency(struct dmar_domain *domain)
502{
503 int i;
504
505 domain->iommu_coherency = 1;
506
507 i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
508 for (; i < g_num_of_iommus; ) {
509 if (!ecap_coherent(g_iommus[i]->ecap)) {
510 domain->iommu_coherency = 0;
511 break;
512 }
513 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
514 }
515}
516
58c610bd
SY		 517static void domain_update_iommu_snooping(struct dmar_domain *domain)
518{
519 int i;
520
521 domain->iommu_snooping = 1;
522
523 i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
524 for (; i < g_num_of_iommus; ) {
525 if (!ecap_sc_support(g_iommus[i]->ecap)) {
526 domain->iommu_snooping = 0;
527 break;
528 }
529 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
530 }
531}
532
533/* Some capabilities may be different across iommus */
534static void domain_update_iommu_cap(struct dmar_domain *domain)
535{
536 domain_update_iommu_coherency(domain);
537 domain_update_iommu_snooping(domain);
538}
539
276dbf99 540static struct intel_iommu *device_to_iommu(int segment, u8 bus, u8 devfn)
c7151a8d
WH		 541{
542 struct dmar_drhd_unit *drhd = NULL;
543 int i;
544
545 for_each_drhd_unit(drhd) {
546 if (drhd->ignored)
547 continue;
276dbf99
DW		 548 if (segment != drhd->segment)
549 continue;
c7151a8d 550
924b6231 551 for (i = 0; i < drhd->devices_cnt; i++) {
288e4877
DH		 552 if (drhd->devices[i] &&
553 drhd->devices[i]->bus->number == bus &&
c7151a8d
WH		 554 drhd->devices[i]->devfn == devfn)
555 return drhd->iommu;
4958c5dc
DW		 556 if (drhd->devices[i] &&
557 drhd->devices[i]->subordinate &&
924b6231
DW		 558 drhd->devices[i]->subordinate->number <= bus &&
559 drhd->devices[i]->subordinate->subordinate >= bus)
560 return drhd->iommu;
561 }
c7151a8d
WH		 562
563 if (drhd->include_all)
564 return drhd->iommu;
565 }
566
567 return NULL;
568}
569
5331fe6f
WH		 570static void domain_flush_cache(struct dmar_domain *domain,
571 void *addr, int size)
572{
573 if (!domain->iommu_coherency)
574 clflush_cache_range(addr, size);
575}
576
ba395927
KA		 577/* Gets context entry for a given bus and devfn */
578static struct context_entry * device_to_context_entry(struct intel_iommu *iommu,
579 u8 bus, u8 devfn)
580{
581 struct root_entry *root;
582 struct context_entry *context;
583 unsigned long phy_addr;
584 unsigned long flags;
585
586 spin_lock_irqsave(&iommu->lock, flags);
587 root = &iommu->root_entry[bus];
588 context = get_context_addr_from_root(root);
589 if (!context) {
590 context = (struct context_entry *)alloc_pgtable_page();
591 if (!context) {
592 spin_unlock_irqrestore(&iommu->lock, flags);
593 return NULL;
594 }
5b6985ce 595 __iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE);
ba395927
KA		 596 phy_addr = virt_to_phys((void *)context);
597 set_root_value(root, phy_addr);
598 set_root_present(root);
599 __iommu_flush_cache(iommu, root, sizeof(*root));
600 }
601 spin_unlock_irqrestore(&iommu->lock, flags);
602 return &context[devfn];
603}
604
605static int device_context_mapped(struct intel_iommu *iommu, u8 bus, u8 devfn)
606{
607 struct root_entry *root;
608 struct context_entry *context;
609 int ret;
610 unsigned long flags;
611
612 spin_lock_irqsave(&iommu->lock, flags);
613 root = &iommu->root_entry[bus];
614 context = get_context_addr_from_root(root);
615 if (!context) {
616 ret = 0;
617 goto out;
618 }
c07e7d21 619 ret = context_present(&context[devfn]);
ba395927
KA		 620out:
621 spin_unlock_irqrestore(&iommu->lock, flags);
622 return ret;
623}
624
625static void clear_context_table(struct intel_iommu *iommu, u8 bus, u8 devfn)
626{
627 struct root_entry *root;
628 struct context_entry *context;
629 unsigned long flags;
630
631 spin_lock_irqsave(&iommu->lock, flags);
632 root = &iommu->root_entry[bus];
633 context = get_context_addr_from_root(root);
634 if (context) {
c07e7d21 635 context_clear_entry(&context[devfn]);
ba395927
KA		 636 __iommu_flush_cache(iommu, &context[devfn], \
637 sizeof(*context));
638 }
639 spin_unlock_irqrestore(&iommu->lock, flags);
640}
641
642static void free_context_table(struct intel_iommu *iommu)
643{
644 struct root_entry *root;
645 int i;
646 unsigned long flags;
647 struct context_entry *context;
648
649 spin_lock_irqsave(&iommu->lock, flags);
650 if (!iommu->root_entry) {
651 goto out;
652 }
653 for (i = 0; i < ROOT_ENTRY_NR; i++) {
654 root = &iommu->root_entry[i];
655 context = get_context_addr_from_root(root);
656 if (context)
657 free_pgtable_page(context);
658 }
659 free_pgtable_page(iommu->root_entry);
660 iommu->root_entry = NULL;
661out:
662 spin_unlock_irqrestore(&iommu->lock, flags);
663}
664
665/* page table handling */
666#define LEVEL_STRIDE (9)
667#define LEVEL_MASK (((u64)1 << LEVEL_STRIDE) - 1)
668
669static inline int agaw_to_level(int agaw)
670{
671 return agaw + 2;
672}
673
674static inline int agaw_to_width(int agaw)
675{
676 return 30 + agaw * LEVEL_STRIDE;
677
678}
679
680static inline int width_to_agaw(int width)
681{
682 return (width - 30) / LEVEL_STRIDE;
683}
684
685static inline unsigned int level_to_offset_bits(int level)
686{
6660c63a 687 return (level - 1) * LEVEL_STRIDE;
ba395927
KA		 688}
689
77dfa56c 690static inline int pfn_level_offset(unsigned long pfn, int level)
ba395927 691{
6660c63a 692 return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK;
ba395927
KA		 693}
694
6660c63a 695static inline unsigned long level_mask(int level)
ba395927 696{
6660c63a 697 return -1UL << level_to_offset_bits(level);
ba395927
KA		 698}
699
6660c63a 700static inline unsigned long level_size(int level)
ba395927 701{
6660c63a 702 return 1UL << level_to_offset_bits(level);
ba395927
KA		 703}
704
6660c63a 705static inline unsigned long align_to_level(unsigned long pfn, int level)
ba395927 706{
6660c63a 707 return (pfn + level_size(level) - 1) & level_mask(level);
ba395927
KA		 708}
709
b026fd28
DW		 710static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain,
711 unsigned long pfn)
ba395927 712{
b026fd28 713 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
ba395927
KA		 714 struct dma_pte *parent, *pte = NULL;
715 int level = agaw_to_level(domain->agaw);
716 int offset;
ba395927
KA		 717
718 BUG_ON(!domain->pgd);
b026fd28 719 BUG_ON(addr_width < BITS_PER_LONG && pfn >> addr_width);
ba395927
KA		 720 parent = domain->pgd;
721
ba395927
KA		 722 while (level > 0) {
723 void *tmp_page;
724
b026fd28 725 offset = pfn_level_offset(pfn, level);
ba395927
KA		 726 pte = &parent[offset];
727 if (level == 1)
728 break;
729
19c239ce 730 if (!dma_pte_present(pte)) {
c85994e4
DW		 731 uint64_t pteval;
732
ba395927
KA		 733 tmp_page = alloc_pgtable_page();
734
206a73c1 735 if (!tmp_page)
ba395927 736 return NULL;
206a73c1 737
c85994e4 738 domain_flush_cache(domain, tmp_page, VTD_PAGE_SIZE);
64de5af0 739 pteval = ((uint64_t)virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE;
c85994e4
DW		 740 if (cmpxchg64(&pte->val, 0ULL, pteval)) {
741 /* Someone else set it while we were thinking; use theirs. */
742 free_pgtable_page(tmp_page);
743 } else {
744 dma_pte_addr(pte);
745 domain_flush_cache(domain, pte, sizeof(*pte));
746 }
ba395927 747 }
19c239ce 748 parent = phys_to_virt(dma_pte_addr(pte));
ba395927
KA		 749 level--;
750 }
751
ba395927
KA		 752 return pte;
753}
754
755/* return address's pte at specific level */
90dcfb5e
DW		 756static struct dma_pte *dma_pfn_level_pte(struct dmar_domain *domain,
757 unsigned long pfn,
758 int level)
ba395927
KA		 759{
760 struct dma_pte *parent, *pte = NULL;
761 int total = agaw_to_level(domain->agaw);
762 int offset;
763
764 parent = domain->pgd;
765 while (level <= total) {
90dcfb5e 766 offset = pfn_level_offset(pfn, total);
ba395927
KA		 767 pte = &parent[offset];
768 if (level == total)
769 return pte;
770
19c239ce 771 if (!dma_pte_present(pte))
ba395927 772 break;
19c239ce 773 parent = phys_to_virt(dma_pte_addr(pte));
ba395927
KA		 774 total--;
775 }
776 return NULL;
777}
778
ba395927 779/* clear last level pte, a tlb flush should be followed */
595badf5
DW		 780static void dma_pte_clear_range(struct dmar_domain *domain,
781 unsigned long start_pfn,
782 unsigned long last_pfn)
ba395927 783{
04b18e65 784 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
310a5ab9 785 struct dma_pte *first_pte, *pte;
66eae846 786
04b18e65 787 BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
595badf5 788 BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
59c36286 789 BUG_ON(start_pfn > last_pfn);
ba395927 790
04b18e65 791 /* we don't need lock here; nobody else touches the iova range */
59c36286 792 do {
310a5ab9
DW		 793 first_pte = pte = dma_pfn_level_pte(domain, start_pfn, 1);
794 if (!pte) {
795 start_pfn = align_to_level(start_pfn + 1, 2);
796 continue;
797 }
75e6bf96 798 do {
310a5ab9
DW		 799 dma_clear_pte(pte);
800 start_pfn++;
801 pte++;
75e6bf96
DW		 802 } while (start_pfn <= last_pfn && !first_pte_in_page(pte));
803
310a5ab9
DW		 804 domain_flush_cache(domain, first_pte,
805 (void *)pte - (void *)first_pte);
59c36286
DW		 806
807 } while (start_pfn && start_pfn <= last_pfn);
ba395927
KA		 808}
809
810/* free page table pages. last level pte should already be cleared */
811static void dma_pte_free_pagetable(struct dmar_domain *domain,
d794dc9b
DW		 812 unsigned long start_pfn,
813 unsigned long last_pfn)
ba395927 814{
6660c63a 815 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
f3a0a52f 816 struct dma_pte *first_pte, *pte;
ba395927
KA		 817 int total = agaw_to_level(domain->agaw);
818 int level;
6660c63a 819 unsigned long tmp;
ba395927 820
6660c63a
DW		 821 BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
822 BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
59c36286 823 BUG_ON(start_pfn > last_pfn);
ba395927 824
f3a0a52f 825 /* We don't need lock here; nobody else touches the iova range */
ba395927
KA		 826 level = 2;
827 while (level <= total) {
6660c63a
DW		 828 tmp = align_to_level(start_pfn, level);
829
f3a0a52f 830 /* If we can't even clear one PTE at this level, we're done */
6660c63a 831 if (tmp + level_size(level) - 1 > last_pfn)
ba395927
KA		 832 return;
833
59c36286 834 do {
f3a0a52f
DW		 835 first_pte = pte = dma_pfn_level_pte(domain, tmp, level);
836 if (!pte) {
837 tmp = align_to_level(tmp + 1, level + 1);
838 continue;
839 }
75e6bf96 840 do {
6a43e574
DW		 841 if (dma_pte_present(pte)) {
842 free_pgtable_page(phys_to_virt(dma_pte_addr(pte)));
843 dma_clear_pte(pte);
844 }
f3a0a52f
DW		 845 pte++;
846 tmp += level_size(level);
75e6bf96
DW		 847 } while (!first_pte_in_page(pte) &&
848 tmp + level_size(level) - 1 <= last_pfn);
849
f3a0a52f
DW		 850 domain_flush_cache(domain, first_pte,
851 (void *)pte - (void *)first_pte);
852
59c36286 853 } while (tmp && tmp + level_size(level) - 1 <= last_pfn);
ba395927
KA		 854 level++;
855 }
856 /* free pgd */
d794dc9b 857 if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) {
ba395927
KA		 858 free_pgtable_page(domain->pgd);
859 domain->pgd = NULL;
860 }
861}
862
863/* iommu handling */
864static int iommu_alloc_root_entry(struct intel_iommu *iommu)
865{
866 struct root_entry *root;
867 unsigned long flags;
868
869 root = (struct root_entry *)alloc_pgtable_page();
870 if (!root)
871 return -ENOMEM;
872
5b6985ce 873 __iommu_flush_cache(iommu, root, ROOT_SIZE);
ba395927
KA		 874
875 spin_lock_irqsave(&iommu->lock, flags);
876 iommu->root_entry = root;
877 spin_unlock_irqrestore(&iommu->lock, flags);
878
879 return 0;
880}
881
ba395927
KA		 882static void iommu_set_root_entry(struct intel_iommu *iommu)
883{
884 void *addr;
c416daa9 885 u32 sts;
ba395927
KA		 886 unsigned long flag;
887
888 addr = iommu->root_entry;
889
890 spin_lock_irqsave(&iommu->register_lock, flag);
891 dmar_writeq(iommu->reg + DMAR_RTADDR_REG, virt_to_phys(addr));
892
c416daa9 893 writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG);
ba395927
KA		 894
895 /* Make sure hardware complete it */
896 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 897 readl, (sts & DMA_GSTS_RTPS), sts);
ba395927
KA		 898
899 spin_unlock_irqrestore(&iommu->register_lock, flag);
900}
901
902static void iommu_flush_write_buffer(struct intel_iommu *iommu)
903{
904 u32 val;
905 unsigned long flag;
906
9af88143 907 if (!rwbf_quirk && !cap_rwbf(iommu->cap))
ba395927 908 return;
ba395927
KA		 909
910 spin_lock_irqsave(&iommu->register_lock, flag);
462b60f6 911 writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG);
ba395927
KA		 912
913 /* Make sure hardware complete it */
914 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 915 readl, (!(val & DMA_GSTS_WBFS)), val);
ba395927
KA		 916
917 spin_unlock_irqrestore(&iommu->register_lock, flag);
918}
919
920/* return value determine if we need a write buffer flush */
4c25a2c1
DW		 921static void __iommu_flush_context(struct intel_iommu *iommu,
922 u16 did, u16 source_id, u8 function_mask,
923 u64 type)
ba395927
KA		 924{
925 u64 val = 0;
926 unsigned long flag;
927
ba395927
KA		 928 switch (type) {
929 case DMA_CCMD_GLOBAL_INVL:
930 val = DMA_CCMD_GLOBAL_INVL;
931 break;
932 case DMA_CCMD_DOMAIN_INVL:
933 val = DMA_CCMD_DOMAIN_INVL|DMA_CCMD_DID(did);
934 break;
935 case DMA_CCMD_DEVICE_INVL:
936 val = DMA_CCMD_DEVICE_INVL|DMA_CCMD_DID(did)
937 | DMA_CCMD_SID(source_id) | DMA_CCMD_FM(function_mask);
938 break;
939 default:
940 BUG();
941 }
942 val |= DMA_CCMD_ICC;
943
944 spin_lock_irqsave(&iommu->register_lock, flag);
945 dmar_writeq(iommu->reg + DMAR_CCMD_REG, val);
946
947 /* Make sure hardware complete it */
948 IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG,
949 dmar_readq, (!(val & DMA_CCMD_ICC)), val);
950
951 spin_unlock_irqrestore(&iommu->register_lock, flag);
ba395927
KA		 952}
953
ba395927 954/* return value determine if we need a write buffer flush */
1f0ef2aa
DW		 955static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did,
956 u64 addr, unsigned int size_order, u64 type)
ba395927
KA		 957{
958 int tlb_offset = ecap_iotlb_offset(iommu->ecap);
959 u64 val = 0, val_iva = 0;
960 unsigned long flag;
961
ba395927
KA		 962 switch (type) {
963 case DMA_TLB_GLOBAL_FLUSH:
964 /* global flush doesn't need set IVA_REG */
965 val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT;
966 break;
967 case DMA_TLB_DSI_FLUSH:
968 val = DMA_TLB_DSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
969 break;
970 case DMA_TLB_PSI_FLUSH:
971 val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
972 /* Note: always flush non-leaf currently */
973 val_iva = size_order | addr;
974 break;
975 default:
976 BUG();
977 }
978 /* Note: set drain read/write */
979#if 0
980 /*
981 * This is probably to be super secure.. Looks like we can
982 * ignore it without any impact.
983 */
984 if (cap_read_drain(iommu->cap))
985 val |= DMA_TLB_READ_DRAIN;
986#endif
987 if (cap_write_drain(iommu->cap))
988 val |= DMA_TLB_WRITE_DRAIN;
989
990 spin_lock_irqsave(&iommu->register_lock, flag);
991 /* Note: Only uses first TLB reg currently */
992 if (val_iva)
993 dmar_writeq(iommu->reg + tlb_offset, val_iva);
994 dmar_writeq(iommu->reg + tlb_offset + 8, val);
995
996 /* Make sure hardware complete it */
997 IOMMU_WAIT_OP(iommu, tlb_offset + 8,
998 dmar_readq, (!(val & DMA_TLB_IVT)), val);
999
1000 spin_unlock_irqrestore(&iommu->register_lock, flag);
1001
1002 /* check IOTLB invalidation granularity */
1003 if (DMA_TLB_IAIG(val) == 0)
1004 printk(KERN_ERR"IOMMU: flush IOTLB failed\n");
1005 if (DMA_TLB_IAIG(val) != DMA_TLB_IIRG(type))
1006 pr_debug("IOMMU: tlb flush request %Lx, actual %Lx\n",
5b6985ce
FY		 1007 (unsigned long long)DMA_TLB_IIRG(type),
1008 (unsigned long long)DMA_TLB_IAIG(val));
ba395927
KA		 1009}
1010
93a23a72
YZ		 1011static struct device_domain_info *iommu_support_dev_iotlb(
1012 struct dmar_domain *domain, int segment, u8 bus, u8 devfn)
1013{
1014 int found = 0;
1015 unsigned long flags;
1016 struct device_domain_info *info;
1017 struct intel_iommu *iommu = device_to_iommu(segment, bus, devfn);
1018
1019 if (!ecap_dev_iotlb_support(iommu->ecap))
1020 return NULL;
1021
1022 if (!iommu->qi)
1023 return NULL;
1024
1025 spin_lock_irqsave(&device_domain_lock, flags);
1026 list_for_each_entry(info, &domain->devices, link)
1027 if (info->bus == bus && info->devfn == devfn) {
1028 found = 1;
1029 break;
1030 }
1031 spin_unlock_irqrestore(&device_domain_lock, flags);
1032
1033 if (!found || !info->dev)
1034 return NULL;
1035
1036 if (!pci_find_ext_capability(info->dev, PCI_EXT_CAP_ID_ATS))
1037 return NULL;
1038
1039 if (!dmar_find_matched_atsr_unit(info->dev))
1040 return NULL;
1041
1042 info->iommu = iommu;
1043
1044 return info;
1045}
1046
1047static void iommu_enable_dev_iotlb(struct device_domain_info *info)
ba395927 1048{
93a23a72
YZ		 1049 if (!info)
1050 return;
1051
1052 pci_enable_ats(info->dev, VTD_PAGE_SHIFT);
1053}
1054
1055static void iommu_disable_dev_iotlb(struct device_domain_info *info)
1056{
1057 if (!info->dev || !pci_ats_enabled(info->dev))
1058 return;
1059
1060 pci_disable_ats(info->dev);
1061}
1062
1063static void iommu_flush_dev_iotlb(struct dmar_domain *domain,
1064 u64 addr, unsigned mask)
1065{
1066 u16 sid, qdep;
1067 unsigned long flags;
1068 struct device_domain_info *info;
1069
1070 spin_lock_irqsave(&device_domain_lock, flags);
1071 list_for_each_entry(info, &domain->devices, link) {
1072 if (!info->dev || !pci_ats_enabled(info->dev))
1073 continue;
1074
1075 sid = info->bus << 8 | info->devfn;
1076 qdep = pci_ats_queue_depth(info->dev);
1077 qi_flush_dev_iotlb(info->iommu, sid, qdep, addr, mask);
1078 }
1079 spin_unlock_irqrestore(&device_domain_lock, flags);
1080}
1081
1f0ef2aa 1082static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, u16 did,
03d6a246 1083 unsigned long pfn, unsigned int pages)
ba395927 1084{
9dd2fe89 1085 unsigned int mask = ilog2(__roundup_pow_of_two(pages));
03d6a246 1086 uint64_t addr = (uint64_t)pfn << VTD_PAGE_SHIFT;
ba395927 1087
ba395927
KA		 1088 BUG_ON(pages == 0);
1089
ba395927 1090 /*
9dd2fe89
YZ		 1091 * Fallback to domain selective flush if no PSI support or the size is
1092 * too big.
ba395927
KA		 1093 * PSI requires page size to be 2 ^ x, and the base address is naturally
1094 * aligned to the size
1095 */
9dd2fe89
YZ		 1096 if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap))
1097 iommu->flush.flush_iotlb(iommu, did, 0, 0,
1f0ef2aa 1098 DMA_TLB_DSI_FLUSH);
9dd2fe89
YZ		 1099 else
1100 iommu->flush.flush_iotlb(iommu, did, addr, mask,
1101 DMA_TLB_PSI_FLUSH);
bf92df30
YZ		 1102
1103 /*
1104 * In caching mode, domain ID 0 is reserved for non-present to present
1105 * mapping flush. Device IOTLB doesn't need to be flushed in this case.
1106 */
1107 if (!cap_caching_mode(iommu->cap) || did)
93a23a72 1108 iommu_flush_dev_iotlb(iommu->domains[did], addr, mask);
ba395927
KA		 1109}
1110
f8bab735 1111static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu)
1112{
1113 u32 pmen;
1114 unsigned long flags;
1115
1116 spin_lock_irqsave(&iommu->register_lock, flags);
1117 pmen = readl(iommu->reg + DMAR_PMEN_REG);
1118 pmen &= ~DMA_PMEN_EPM;
1119 writel(pmen, iommu->reg + DMAR_PMEN_REG);
1120
1121 /* wait for the protected region status bit to clear */
1122 IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG,
1123 readl, !(pmen & DMA_PMEN_PRS), pmen);
1124
1125 spin_unlock_irqrestore(&iommu->register_lock, flags);
1126}
1127
ba395927
KA		 1128static int iommu_enable_translation(struct intel_iommu *iommu)
1129{
1130 u32 sts;
1131 unsigned long flags;
1132
1133 spin_lock_irqsave(&iommu->register_lock, flags);
c416daa9
DW		 1134 iommu->gcmd |= DMA_GCMD_TE;
1135 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
ba395927
KA		 1136
1137 /* Make sure hardware complete it */
1138 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 1139 readl, (sts & DMA_GSTS_TES), sts);
ba395927 1140
ba395927
KA		 1141 spin_unlock_irqrestore(&iommu->register_lock, flags);
1142 return 0;
1143}
1144
1145static int iommu_disable_translation(struct intel_iommu *iommu)
1146{
1147 u32 sts;
1148 unsigned long flag;
1149
1150 spin_lock_irqsave(&iommu->register_lock, flag);
1151 iommu->gcmd &= ~DMA_GCMD_TE;
1152 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1153
1154 /* Make sure hardware complete it */
1155 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 1156 readl, (!(sts & DMA_GSTS_TES)), sts);
ba395927
KA		 1157
1158 spin_unlock_irqrestore(&iommu->register_lock, flag);
1159 return 0;
1160}
1161
3460a6d9 1162
ba395927
KA		 1163static int iommu_init_domains(struct intel_iommu *iommu)
1164{
1165 unsigned long ndomains;
1166 unsigned long nlongs;
1167
1168 ndomains = cap_ndoms(iommu->cap);
1169 pr_debug("Number of Domains supportd <%ld>\n", ndomains);
1170 nlongs = BITS_TO_LONGS(ndomains);
1171
94a91b50
DD		 1172 spin_lock_init(&iommu->lock);
1173
ba395927
KA		 1174 /* TBD: there might be 64K domains,
1175 * consider other allocation for future chip
1176 */
1177 iommu->domain_ids = kcalloc(nlongs, sizeof(unsigned long), GFP_KERNEL);
1178 if (!iommu->domain_ids) {
1179 printk(KERN_ERR "Allocating domain id array failed\n");
1180 return -ENOMEM;
1181 }
1182 iommu->domains = kcalloc(ndomains, sizeof(struct dmar_domain *),
1183 GFP_KERNEL);
1184 if (!iommu->domains) {
1185 printk(KERN_ERR "Allocating domain array failed\n");
ba395927
KA		 1186 return -ENOMEM;
1187 }
1188
1189 /*
1190 * if Caching mode is set, then invalid translations are tagged
1191 * with domainid 0. Hence we need to pre-allocate it.
1192 */
1193 if (cap_caching_mode(iommu->cap))
1194 set_bit(0, iommu->domain_ids);
1195 return 0;
1196}
ba395927 1197
ba395927
KA		 1198
1199static void domain_exit(struct dmar_domain *domain);
5e98c4b1 1200static void vm_domain_exit(struct dmar_domain *domain);
e61d98d8
SS		 1201
1202void free_dmar_iommu(struct intel_iommu *iommu)
ba395927
KA		 1203{
1204 struct dmar_domain *domain;
1205 int i;
c7151a8d 1206 unsigned long flags;
ba395927 1207
94a91b50
DD		 1208 if ((iommu->domains) && (iommu->domain_ids)) {
1209 i = find_first_bit(iommu->domain_ids, cap_ndoms(iommu->cap));
1210 for (; i < cap_ndoms(iommu->cap); ) {
1211 domain = iommu->domains[i];
1212 clear_bit(i, iommu->domain_ids);
1213
1214 spin_lock_irqsave(&domain->iommu_lock, flags);
1215 if (--domain->iommu_count == 0) {
1216 if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE)
1217 vm_domain_exit(domain);
1218 else
1219 domain_exit(domain);
1220 }
1221 spin_unlock_irqrestore(&domain->iommu_lock, flags);
c7151a8d 1222
94a91b50
DD		 1223 i = find_next_bit(iommu->domain_ids,
1224 cap_ndoms(iommu->cap), i+1);
5e98c4b1 1225 }
ba395927
KA		 1226 }
1227
1228 if (iommu->gcmd & DMA_GCMD_TE)
1229 iommu_disable_translation(iommu);
1230
1231 if (iommu->irq) {
1232 set_irq_data(iommu->irq, NULL);
1233 /* This will mask the irq */
1234 free_irq(iommu->irq, iommu);
1235 destroy_irq(iommu->irq);
1236 }
1237
1238 kfree(iommu->domains);
1239 kfree(iommu->domain_ids);
1240
d9630fe9
WH		 1241 g_iommus[iommu->seq_id] = NULL;
1242
1243 /* if all iommus are freed, free g_iommus */
1244 for (i = 0; i < g_num_of_iommus; i++) {
1245 if (g_iommus[i])
1246 break;
1247 }
1248
1249 if (i == g_num_of_iommus)
1250 kfree(g_iommus);
1251
ba395927
KA		 1252 /* free context mapping */
1253 free_context_table(iommu);
ba395927
KA		 1254}
1255
2c2e2c38 1256static struct dmar_domain *alloc_domain(void)
ba395927 1257{
ba395927 1258 struct dmar_domain *domain;
ba395927
KA		 1259
1260 domain = alloc_domain_mem();
1261 if (!domain)
1262 return NULL;
1263
2c2e2c38
FY		 1264 memset(&domain->iommu_bmp, 0, sizeof(unsigned long));
1265 domain->flags = 0;
1266
1267 return domain;
1268}
1269
1270static int iommu_attach_domain(struct dmar_domain *domain,
1271 struct intel_iommu *iommu)
1272{
1273 int num;
1274 unsigned long ndomains;
1275 unsigned long flags;
1276
ba395927
KA		 1277 ndomains = cap_ndoms(iommu->cap);
1278
1279 spin_lock_irqsave(&iommu->lock, flags);
2c2e2c38 1280
ba395927
KA		 1281 num = find_first_zero_bit(iommu->domain_ids, ndomains);
1282 if (num >= ndomains) {
1283 spin_unlock_irqrestore(&iommu->lock, flags);
ba395927 1284 printk(KERN_ERR "IOMMU: no free domain ids\n");
2c2e2c38 1285 return -ENOMEM;
ba395927
KA		 1286 }
1287
ba395927 1288 domain->id = num;
2c2e2c38 1289 set_bit(num, iommu->domain_ids);
8c11e798 1290 set_bit(iommu->seq_id, &domain->iommu_bmp);
ba395927
KA		 1291 iommu->domains[num] = domain;
1292 spin_unlock_irqrestore(&iommu->lock, flags);
1293
2c2e2c38 1294 return 0;
ba395927
KA		 1295}
1296
2c2e2c38
FY		 1297static void iommu_detach_domain(struct dmar_domain *domain,
1298 struct intel_iommu *iommu)
ba395927
KA		 1299{
1300 unsigned long flags;
2c2e2c38
FY		 1301 int num, ndomains;
1302 int found = 0;
ba395927 1303
8c11e798 1304 spin_lock_irqsave(&iommu->lock, flags);
2c2e2c38
FY		 1305 ndomains = cap_ndoms(iommu->cap);
1306 num = find_first_bit(iommu->domain_ids, ndomains);
1307 for (; num < ndomains; ) {
1308 if (iommu->domains[num] == domain) {
1309 found = 1;
1310 break;
1311 }
1312 num = find_next_bit(iommu->domain_ids,
1313 cap_ndoms(iommu->cap), num+1);
1314 }
1315
1316 if (found) {
1317 clear_bit(num, iommu->domain_ids);
1318 clear_bit(iommu->seq_id, &domain->iommu_bmp);
1319 iommu->domains[num] = NULL;
1320 }
8c11e798 1321 spin_unlock_irqrestore(&iommu->lock, flags);
ba395927
KA		 1322}
1323
1324static struct iova_domain reserved_iova_list;
8a443df4 1325static struct lock_class_key reserved_rbtree_key;
ba395927
KA		 1326
1327static void dmar_init_reserved_ranges(void)
1328{
1329 struct pci_dev *pdev = NULL;
1330 struct iova *iova;
1331 int i;
ba395927 1332
f661197e 1333 init_iova_domain(&reserved_iova_list, DMA_32BIT_PFN);
ba395927 1334
8a443df4
MG		 1335 lockdep_set_class(&reserved_iova_list.iova_rbtree_lock,
1336 &reserved_rbtree_key);
1337
ba395927
KA		 1338 /* IOAPIC ranges shouldn't be accessed by DMA */
1339 iova = reserve_iova(&reserved_iova_list, IOVA_PFN(IOAPIC_RANGE_START),
1340 IOVA_PFN(IOAPIC_RANGE_END));
1341 if (!iova)
1342 printk(KERN_ERR "Reserve IOAPIC range failed\n");
1343
1344 /* Reserve all PCI MMIO to avoid peer-to-peer access */
1345 for_each_pci_dev(pdev) {
1346 struct resource *r;
1347
1348 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1349 r = &pdev->resource[i];
1350 if (!r->flags || !(r->flags & IORESOURCE_MEM))
1351 continue;
1a4a4551
DW		 1352 iova = reserve_iova(&reserved_iova_list,
1353 IOVA_PFN(r->start),
1354 IOVA_PFN(r->end));
ba395927
KA		 1355 if (!iova)
1356 printk(KERN_ERR "Reserve iova failed\n");
1357 }
1358 }
1359
1360}
1361
1362static void domain_reserve_special_ranges(struct dmar_domain *domain)
1363{
1364 copy_reserved_iova(&reserved_iova_list, &domain->iovad);
1365}
1366
1367static inline int guestwidth_to_adjustwidth(int gaw)
1368{
1369 int agaw;
1370 int r = (gaw - 12) % 9;
1371
1372 if (r == 0)
1373 agaw = gaw;
1374 else
1375 agaw = gaw + 9 - r;
1376 if (agaw > 64)
1377 agaw = 64;
1378 return agaw;
1379}
1380
1381static int domain_init(struct dmar_domain *domain, int guest_width)
1382{
1383 struct intel_iommu *iommu;
1384 int adjust_width, agaw;
1385 unsigned long sagaw;
1386
f661197e 1387 init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
c7151a8d 1388 spin_lock_init(&domain->iommu_lock);
ba395927
KA		 1389
1390 domain_reserve_special_ranges(domain);
1391
1392 /* calculate AGAW */
8c11e798 1393 iommu = domain_get_iommu(domain);
ba395927
KA		 1394 if (guest_width > cap_mgaw(iommu->cap))
1395 guest_width = cap_mgaw(iommu->cap);
1396 domain->gaw = guest_width;
1397 adjust_width = guestwidth_to_adjustwidth(guest_width);
1398 agaw = width_to_agaw(adjust_width);
1399 sagaw = cap_sagaw(iommu->cap);
1400 if (!test_bit(agaw, &sagaw)) {
1401 /* hardware doesn't support it, choose a bigger one */
1402 pr_debug("IOMMU: hardware doesn't support agaw %d\n", agaw);
1403 agaw = find_next_bit(&sagaw, 5, agaw);
1404 if (agaw >= 5)
1405 return -ENODEV;
1406 }
1407 domain->agaw = agaw;
1408 INIT_LIST_HEAD(&domain->devices);
1409
8e604097
WH		 1410 if (ecap_coherent(iommu->ecap))
1411 domain->iommu_coherency = 1;
1412 else
1413 domain->iommu_coherency = 0;
1414
58c610bd
SY		 1415 if (ecap_sc_support(iommu->ecap))
1416 domain->iommu_snooping = 1;
1417 else
1418 domain->iommu_snooping = 0;
1419
c7151a8d
WH		 1420 domain->iommu_count = 1;
1421
ba395927
KA		 1422 /* always allocate the top pgd */
1423 domain->pgd = (struct dma_pte *)alloc_pgtable_page();
1424 if (!domain->pgd)
1425 return -ENOMEM;
5b6985ce 1426 __iommu_flush_cache(iommu, domain->pgd, PAGE_SIZE);
ba395927
KA		 1427 return 0;
1428}
1429
1430static void domain_exit(struct dmar_domain *domain)
1431{
2c2e2c38
FY		 1432 struct dmar_drhd_unit *drhd;
1433 struct intel_iommu *iommu;
ba395927
KA		 1434
1435 /* Domain 0 is reserved, so dont process it */
1436 if (!domain)
1437 return;
1438
1439 domain_remove_dev_info(domain);
1440 /* destroy iovas */
1441 put_iova_domain(&domain->iovad);
ba395927
KA		 1442
1443 /* clear ptes */
595badf5 1444 dma_pte_clear_range(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
ba395927
KA		 1445
1446 /* free page tables */
d794dc9b 1447 dma_pte_free_pagetable(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
ba395927 1448
2c2e2c38
FY		 1449 for_each_active_iommu(iommu, drhd)
1450 if (test_bit(iommu->seq_id, &domain->iommu_bmp))
1451 iommu_detach_domain(domain, iommu);
1452
ba395927
KA		 1453 free_domain_mem(domain);
1454}
1455
4ed0d3e6
FY		 1456static int domain_context_mapping_one(struct dmar_domain *domain, int segment,
1457 u8 bus, u8 devfn, int translation)
ba395927
KA		 1458{
1459 struct context_entry *context;
ba395927 1460 unsigned long flags;
5331fe6f 1461 struct intel_iommu *iommu;
ea6606b0
WH		 1462 struct dma_pte *pgd;
1463 unsigned long num;
1464 unsigned long ndomains;
1465 int id;
1466 int agaw;
93a23a72 1467 struct device_domain_info *info = NULL;
ba395927
KA		 1468
1469 pr_debug("Set context mapping for %02x:%02x.%d\n",
1470 bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
4ed0d3e6 1471
ba395927 1472 BUG_ON(!domain->pgd);
4ed0d3e6
FY		 1473 BUG_ON(translation != CONTEXT_TT_PASS_THROUGH &&
1474 translation != CONTEXT_TT_MULTI_LEVEL);
5331fe6f 1475
276dbf99 1476 iommu = device_to_iommu(segment, bus, devfn);
5331fe6f
WH		 1477 if (!iommu)
1478 return -ENODEV;
1479
ba395927
KA		 1480 context = device_to_context_entry(iommu, bus, devfn);
1481 if (!context)
1482 return -ENOMEM;
1483 spin_lock_irqsave(&iommu->lock, flags);
c07e7d21 1484 if (context_present(context)) {
ba395927
KA		 1485 spin_unlock_irqrestore(&iommu->lock, flags);
1486 return 0;
1487 }
1488
ea6606b0
WH		 1489 id = domain->id;
1490 pgd = domain->pgd;
1491
2c2e2c38
FY		 1492 if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
1493 domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) {
ea6606b0
WH		 1494 int found = 0;
1495
1496 /* find an available domain id for this device in iommu */
1497 ndomains = cap_ndoms(iommu->cap);
1498 num = find_first_bit(iommu->domain_ids, ndomains);
1499 for (; num < ndomains; ) {
1500 if (iommu->domains[num] == domain) {
1501 id = num;
1502 found = 1;
1503 break;
1504 }
1505 num = find_next_bit(iommu->domain_ids,
1506 cap_ndoms(iommu->cap), num+1);
1507 }
1508
1509 if (found == 0) {
1510 num = find_first_zero_bit(iommu->domain_ids, ndomains);
1511 if (num >= ndomains) {
1512 spin_unlock_irqrestore(&iommu->lock, flags);
1513 printk(KERN_ERR "IOMMU: no free domain ids\n");
1514 return -EFAULT;
1515 }
1516
1517 set_bit(num, iommu->domain_ids);
1518 iommu->domains[num] = domain;
1519 id = num;
1520 }
1521
1522 /* Skip top levels of page tables for
1523 * iommu which has less agaw than default.
1524 */
1525 for (agaw = domain->agaw; agaw != iommu->agaw; agaw--) {
1526 pgd = phys_to_virt(dma_pte_addr(pgd));
1527 if (!dma_pte_present(pgd)) {
1528 spin_unlock_irqrestore(&iommu->lock, flags);
1529 return -ENOMEM;
1530 }
1531 }
1532 }
1533
1534 context_set_domain_id(context, id);
4ed0d3e6 1535
93a23a72
YZ		 1536 if (translation != CONTEXT_TT_PASS_THROUGH) {
1537 info = iommu_support_dev_iotlb(domain, segment, bus, devfn);
1538 translation = info ? CONTEXT_TT_DEV_IOTLB :
1539 CONTEXT_TT_MULTI_LEVEL;
1540 }
4ed0d3e6
FY		 1541 /*
1542 * In pass through mode, AW must be programmed to indicate the largest
1543 * AGAW value supported by hardware. And ASR is ignored by hardware.
1544 */
93a23a72 1545 if (unlikely(translation == CONTEXT_TT_PASS_THROUGH))
4ed0d3e6 1546 context_set_address_width(context, iommu->msagaw);
93a23a72
YZ		 1547 else {
1548 context_set_address_root(context, virt_to_phys(pgd));
1549 context_set_address_width(context, iommu->agaw);
1550 }
4ed0d3e6
FY		 1551
1552 context_set_translation_type(context, translation);
c07e7d21
MM		 1553 context_set_fault_enable(context);
1554 context_set_present(context);
5331fe6f 1555 domain_flush_cache(domain, context, sizeof(*context));
ba395927 1556
4c25a2c1
DW		 1557 /*
1558 * It's a non-present to present mapping. If hardware doesn't cache
1559 * non-present entry we only need to flush the write-buffer. If the
1560 * _does_ cache non-present entries, then it does so in the special
1561 * domain #0, which we have to flush:
1562 */
1563 if (cap_caching_mode(iommu->cap)) {
1564 iommu->flush.flush_context(iommu, 0,
1565 (((u16)bus) << 8) | devfn,
1566 DMA_CCMD_MASK_NOBIT,
1567 DMA_CCMD_DEVICE_INVL);
1f0ef2aa 1568 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_DSI_FLUSH);
4c25a2c1 1569 } else {
ba395927 1570 iommu_flush_write_buffer(iommu);
4c25a2c1 1571 }
93a23a72 1572 iommu_enable_dev_iotlb(info);
ba395927 1573 spin_unlock_irqrestore(&iommu->lock, flags);
c7151a8d
WH		 1574
1575 spin_lock_irqsave(&domain->iommu_lock, flags);
1576 if (!test_and_set_bit(iommu->seq_id, &domain->iommu_bmp)) {
1577 domain->iommu_count++;
58c610bd 1578 domain_update_iommu_cap(domain);
c7151a8d
WH		 1579 }
1580 spin_unlock_irqrestore(&domain->iommu_lock, flags);
ba395927
KA		 1581 return 0;
1582}
1583
1584static int
4ed0d3e6
FY		 1585domain_context_mapping(struct dmar_domain *domain, struct pci_dev *pdev,
1586 int translation)
ba395927
KA		 1587{
1588 int ret;
1589 struct pci_dev *tmp, *parent;
1590
276dbf99 1591 ret = domain_context_mapping_one(domain, pci_domain_nr(pdev->bus),
4ed0d3e6
FY		 1592 pdev->bus->number, pdev->devfn,
1593 translation);
ba395927
KA		 1594 if (ret)
1595 return ret;
1596
1597 /* dependent device mapping */
1598 tmp = pci_find_upstream_pcie_bridge(pdev);
1599 if (!tmp)
1600 return 0;
1601 /* Secondary interface's bus number and devfn 0 */
1602 parent = pdev->bus->self;
1603 while (parent != tmp) {
276dbf99
DW		 1604 ret = domain_context_mapping_one(domain,
1605 pci_domain_nr(parent->bus),
1606 parent->bus->number,
4ed0d3e6 1607 parent->devfn, translation);
ba395927
KA		 1608 if (ret)
1609 return ret;
1610 parent = parent->bus->self;
1611 }
1612 if (tmp->is_pcie) /* this is a PCIE-to-PCI bridge */
1613 return domain_context_mapping_one(domain,
276dbf99 1614 pci_domain_nr(tmp->subordinate),
4ed0d3e6
FY		 1615 tmp->subordinate->number, 0,
1616 translation);
ba395927
KA		 1617 else /* this is a legacy PCI bridge */
1618 return domain_context_mapping_one(domain,
276dbf99
DW		 1619 pci_domain_nr(tmp->bus),
1620 tmp->bus->number,
4ed0d3e6
FY		 1621 tmp->devfn,
1622 translation);
ba395927
KA		 1623}
1624
5331fe6f 1625static int domain_context_mapped(struct pci_dev *pdev)
ba395927
KA		 1626{
1627 int ret;
1628 struct pci_dev *tmp, *parent;
5331fe6f
WH		 1629 struct intel_iommu *iommu;
1630
276dbf99
DW		 1631 iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
1632 pdev->devfn);
5331fe6f
WH		 1633 if (!iommu)
1634 return -ENODEV;
ba395927 1635
276dbf99 1636 ret = device_context_mapped(iommu, pdev->bus->number, pdev->devfn);
ba395927
KA		 1637 if (!ret)
1638 return ret;
1639 /* dependent device mapping */
1640 tmp = pci_find_upstream_pcie_bridge(pdev);
1641 if (!tmp)
1642 return ret;
1643 /* Secondary interface's bus number and devfn 0 */
1644 parent = pdev->bus->self;
1645 while (parent != tmp) {
8c11e798 1646 ret = device_context_mapped(iommu, parent->bus->number,
276dbf99 1647 parent->devfn);
ba395927
KA		 1648 if (!ret)
1649 return ret;
1650 parent = parent->bus->self;
1651 }
1652 if (tmp->is_pcie)
276dbf99
DW		 1653 return device_context_mapped(iommu, tmp->subordinate->number,
1654 0);
ba395927 1655 else
276dbf99
DW		 1656 return device_context_mapped(iommu, tmp->bus->number,
1657 tmp->devfn);
ba395927
KA		 1658}
1659
f532959b
FY		 1660/* Returns a number of VTD pages, but aligned to MM page size */
1661static inline unsigned long aligned_nrpages(unsigned long host_addr,
1662 size_t size)
1663{
1664 host_addr &= ~PAGE_MASK;
1665 return PAGE_ALIGN(host_addr + size) >> VTD_PAGE_SHIFT;
1666}
1667
9051aa02
DW		 1668static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1669 struct scatterlist *sg, unsigned long phys_pfn,
1670 unsigned long nr_pages, int prot)
e1605495
DW		 1671{
1672 struct dma_pte *first_pte = NULL, *pte = NULL;
9051aa02 1673 phys_addr_t uninitialized_var(pteval);
e1605495 1674 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
9051aa02 1675 unsigned long sg_res;
e1605495
DW		 1676
1677 BUG_ON(addr_width < BITS_PER_LONG && (iov_pfn + nr_pages - 1) >> addr_width);
1678
1679 if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0)
1680 return -EINVAL;
1681
1682 prot &= DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP;
1683
9051aa02
DW		 1684 if (sg)
1685 sg_res = 0;
1686 else {
1687 sg_res = nr_pages + 1;
1688 pteval = ((phys_addr_t)phys_pfn << VTD_PAGE_SHIFT) | prot;
1689 }
1690
e1605495 1691 while (nr_pages--) {
c85994e4
DW		 1692 uint64_t tmp;
1693
e1605495 1694 if (!sg_res) {
f532959b 1695 sg_res = aligned_nrpages(sg->offset, sg->length);
e1605495
DW		 1696 sg->dma_address = ((dma_addr_t)iov_pfn << VTD_PAGE_SHIFT) + sg->offset;
1697 sg->dma_length = sg->length;
1698 pteval = page_to_phys(sg_page(sg)) | prot;
1699 }
1700 if (!pte) {
1701 first_pte = pte = pfn_to_dma_pte(domain, iov_pfn);
1702 if (!pte)
1703 return -ENOMEM;
1704 }
1705 /* We don't need lock here, nobody else
1706 * touches the iova range
1707 */
7766a3fb 1708 tmp = cmpxchg64_local(&pte->val, 0ULL, pteval);
c85994e4 1709 if (tmp) {
1bf20f0d 1710 static int dumps = 5;
c85994e4
DW		 1711 printk(KERN_CRIT "ERROR: DMA PTE for vPFN 0x%lx already set (to %llx not %llx)\n",
1712 iov_pfn, tmp, (unsigned long long)pteval);
1bf20f0d
DW		 1713 if (dumps) {
1714 dumps--;
1715 debug_dma_dump_mappings(NULL);
1716 }
1717 WARN_ON(1);
1718 }
e1605495 1719 pte++;
75e6bf96 1720 if (!nr_pages || first_pte_in_page(pte)) {
e1605495
DW		 1721 domain_flush_cache(domain, first_pte,
1722 (void *)pte - (void *)first_pte);
1723 pte = NULL;
1724 }
1725 iov_pfn++;
1726 pteval += VTD_PAGE_SIZE;
1727 sg_res--;
1728 if (!sg_res)
1729 sg = sg_next(sg);
1730 }
1731 return 0;
1732}
1733
9051aa02
DW		 1734static inline int domain_sg_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1735 struct scatterlist *sg, unsigned long nr_pages,
1736 int prot)
ba395927 1737{
9051aa02
DW		 1738 return __domain_mapping(domain, iov_pfn, sg, 0, nr_pages, prot);
1739}
6f6a00e4 1740
9051aa02
DW		 1741static inline int domain_pfn_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1742 unsigned long phys_pfn, unsigned long nr_pages,
1743 int prot)
1744{
1745 return __domain_mapping(domain, iov_pfn, NULL, phys_pfn, nr_pages, prot);
ba395927
KA		 1746}
1747
c7151a8d 1748static void iommu_detach_dev(struct intel_iommu *iommu, u8 bus, u8 devfn)
ba395927 1749{
c7151a8d
WH		 1750 if (!iommu)
1751 return;
8c11e798
WH		 1752
1753 clear_context_table(iommu, bus, devfn);
1754 iommu->flush.flush_context(iommu, 0, 0, 0,
4c25a2c1 1755 DMA_CCMD_GLOBAL_INVL);
1f0ef2aa 1756 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
ba395927
KA		 1757}
1758
1759static void domain_remove_dev_info(struct dmar_domain *domain)
1760{
1761 struct device_domain_info *info;
1762 unsigned long flags;
c7151a8d 1763 struct intel_iommu *iommu;
ba395927
KA		 1764
1765 spin_lock_irqsave(&device_domain_lock, flags);
1766 while (!list_empty(&domain->devices)) {
1767 info = list_entry(domain->devices.next,
1768 struct device_domain_info, link);
1769 list_del(&info->link);
1770 list_del(&info->global);
1771 if (info->dev)
358dd8ac 1772 info->dev->dev.archdata.iommu = NULL;
ba395927
KA		 1773 spin_unlock_irqrestore(&device_domain_lock, flags);
1774
93a23a72 1775 iommu_disable_dev_iotlb(info);
276dbf99 1776 iommu = device_to_iommu(info->segment, info->bus, info->devfn);
c7151a8d 1777 iommu_detach_dev(iommu, info->bus, info->devfn);
ba395927
KA		 1778 free_devinfo_mem(info);
1779
1780 spin_lock_irqsave(&device_domain_lock, flags);
1781 }
1782 spin_unlock_irqrestore(&device_domain_lock, flags);
1783}
1784
1785/*
1786 * find_domain
358dd8ac 1787 * Note: we use struct pci_dev->dev.archdata.iommu stores the info
ba395927 1788 */
38717946 1789static struct dmar_domain *
ba395927
KA		 1790find_domain(struct pci_dev *pdev)
1791{
1792 struct device_domain_info *info;
1793
1794 /* No lock here, assumes no domain exit in normal case */
358dd8ac 1795 info = pdev->dev.archdata.iommu;
ba395927
KA		 1796 if (info)
1797 return info->domain;
1798 return NULL;
1799}
1800
ba395927
KA		 1801/* domain is initialized */
1802static struct dmar_domain *get_domain_for_dev(struct pci_dev *pdev, int gaw)
1803{
1804 struct dmar_domain *domain, *found = NULL;
1805 struct intel_iommu *iommu;
1806 struct dmar_drhd_unit *drhd;
1807 struct device_domain_info *info, *tmp;
1808 struct pci_dev *dev_tmp;
1809 unsigned long flags;
1810 int bus = 0, devfn = 0;
276dbf99 1811 int segment;
2c2e2c38 1812 int ret;
ba395927
KA		 1813
1814 domain = find_domain(pdev);
1815 if (domain)
1816 return domain;
1817
276dbf99
DW		 1818 segment = pci_domain_nr(pdev->bus);
1819
ba395927
KA		 1820 dev_tmp = pci_find_upstream_pcie_bridge(pdev);
1821 if (dev_tmp) {
1822 if (dev_tmp->is_pcie) {
1823 bus = dev_tmp->subordinate->number;
1824 devfn = 0;
1825 } else {
1826 bus = dev_tmp->bus->number;
1827 devfn = dev_tmp->devfn;
1828 }
1829 spin_lock_irqsave(&device_domain_lock, flags);
1830 list_for_each_entry(info, &device_domain_list, global) {
276dbf99
DW		 1831 if (info->segment == segment &&
1832 info->bus == bus && info->devfn == devfn) {
ba395927
KA		 1833 found = info->domain;
1834 break;
1835 }
1836 }
1837 spin_unlock_irqrestore(&device_domain_lock, flags);
1838 /* pcie-pci bridge already has a domain, uses it */
1839 if (found) {
1840 domain = found;
1841 goto found_domain;
1842 }
1843 }
1844
2c2e2c38
FY		 1845 domain = alloc_domain();
1846 if (!domain)
1847 goto error;
1848
ba395927
KA		 1849 /* Allocate new domain for the device */
1850 drhd = dmar_find_matched_drhd_unit(pdev);
1851 if (!drhd) {
1852 printk(KERN_ERR "IOMMU: can't find DMAR for device %s\n",
1853 pci_name(pdev));
1854 return NULL;
1855 }
1856 iommu = drhd->iommu;
1857
2c2e2c38
FY		 1858 ret = iommu_attach_domain(domain, iommu);
1859 if (ret) {
1860 domain_exit(domain);
ba395927 1861 goto error;
2c2e2c38 1862 }
ba395927
KA		 1863
1864 if (domain_init(domain, gaw)) {
1865 domain_exit(domain);
1866 goto error;
1867 }
1868
1869 /* register pcie-to-pci device */
1870 if (dev_tmp) {
1871 info = alloc_devinfo_mem();
1872 if (!info) {
1873 domain_exit(domain);
1874 goto error;
1875 }
276dbf99 1876 info->segment = segment;
ba395927
KA		 1877 info->bus = bus;
1878 info->devfn = devfn;
1879 info->dev = NULL;
1880 info->domain = domain;
1881 /* This domain is shared by devices under p2p bridge */
3b5410e7 1882 domain->flags |= DOMAIN_FLAG_P2P_MULTIPLE_DEVICES;
ba395927
KA		 1883
1884 /* pcie-to-pci bridge already has a domain, uses it */
1885 found = NULL;
1886 spin_lock_irqsave(&device_domain_lock, flags);
1887 list_for_each_entry(tmp, &device_domain_list, global) {
276dbf99
DW		 1888 if (tmp->segment == segment &&
1889 tmp->bus == bus && tmp->devfn == devfn) {
ba395927
KA		 1890 found = tmp->domain;
1891 break;
1892 }
1893 }
1894 if (found) {
1895 free_devinfo_mem(info);
1896 domain_exit(domain);
1897 domain = found;
1898 } else {
1899 list_add(&info->link, &domain->devices);
1900 list_add(&info->global, &device_domain_list);
1901 }
1902 spin_unlock_irqrestore(&device_domain_lock, flags);
1903 }
1904
1905found_domain:
1906 info = alloc_devinfo_mem();
1907 if (!info)
1908 goto error;
276dbf99 1909 info->segment = segment;
ba395927
KA		 1910 info->bus = pdev->bus->number;
1911 info->devfn = pdev->devfn;
1912 info->dev = pdev;
1913 info->domain = domain;
1914 spin_lock_irqsave(&device_domain_lock, flags);
1915 /* somebody is fast */
1916 found = find_domain(pdev);
1917 if (found != NULL) {
1918 spin_unlock_irqrestore(&device_domain_lock, flags);
1919 if (found != domain) {
1920 domain_exit(domain);
1921 domain = found;
1922 }
1923 free_devinfo_mem(info);
1924 return domain;
1925 }
1926 list_add(&info->link, &domain->devices);
1927 list_add(&info->global, &device_domain_list);
358dd8ac 1928 pdev->dev.archdata.iommu = info;
ba395927
KA		 1929 spin_unlock_irqrestore(&device_domain_lock, flags);
1930 return domain;
1931error:
1932 /* recheck it here, maybe others set it */
1933 return find_domain(pdev);
1934}
1935
2c2e2c38
FY		 1936static int iommu_identity_mapping;
1937
b213203e
DW		 1938static int iommu_domain_identity_map(struct dmar_domain *domain,
1939 unsigned long long start,
1940 unsigned long long end)
ba395927 1941{
c5395d5c
DW		 1942 unsigned long first_vpfn = start >> VTD_PAGE_SHIFT;
1943 unsigned long last_vpfn = end >> VTD_PAGE_SHIFT;
1944
1945 if (!reserve_iova(&domain->iovad, dma_to_mm_pfn(first_vpfn),
1946 dma_to_mm_pfn(last_vpfn))) {
ba395927 1947 printk(KERN_ERR "IOMMU: reserve iova failed\n");
b213203e 1948 return -ENOMEM;
ba395927
KA		 1949 }
1950
c5395d5c
DW		 1951 pr_debug("Mapping reserved region %llx-%llx for domain %d\n",
1952 start, end, domain->id);
ba395927
KA		 1953 /*
1954 * RMRR range might have overlap with physical memory range,
1955 * clear it first
1956 */
c5395d5c 1957 dma_pte_clear_range(domain, first_vpfn, last_vpfn);
ba395927 1958
c5395d5c
DW		 1959 return domain_pfn_mapping(domain, first_vpfn, first_vpfn,
1960 last_vpfn - first_vpfn + 1,
61df7443 1961 DMA_PTE_READ|DMA_PTE_WRITE);
b213203e
DW		 1962}
1963
1964static int iommu_prepare_identity_map(struct pci_dev *pdev,
1965 unsigned long long start,
1966 unsigned long long end)
1967{
1968 struct dmar_domain *domain;
1969 int ret;
1970
c7ab48d2 1971 domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
b213203e
DW		 1972 if (!domain)
1973 return -ENOMEM;
1974
19943b0e
DW		 1975 /* For _hardware_ passthrough, don't bother. But for software
1976 passthrough, we do it anyway -- it may indicate a memory
1977 range which is reserved in E820, so which didn't get set
1978 up to start with in si_domain */
1979 if (domain == si_domain && hw_pass_through) {
1980 printk("Ignoring identity map for HW passthrough device %s [0x%Lx - 0x%Lx]\n",
1981 pci_name(pdev), start, end);
1982 return 0;
1983 }
1984
1985 printk(KERN_INFO
1986 "IOMMU: Setting identity map for device %s [0x%Lx - 0x%Lx]\n",
1987 pci_name(pdev), start, end);
2ff729f5
DW		 1988
1989 if (end >> agaw_to_width(domain->agaw)) {
1990 WARN(1, "Your BIOS is broken; RMRR exceeds permitted address width (%d bits)\n"
1991 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
1992 agaw_to_width(domain->agaw),
1993 dmi_get_system_info(DMI_BIOS_VENDOR),
1994 dmi_get_system_info(DMI_BIOS_VERSION),
1995 dmi_get_system_info(DMI_PRODUCT_VERSION));
1996 ret = -EIO;
1997 goto error;
1998 }
19943b0e 1999
b213203e 2000 ret = iommu_domain_identity_map(domain, start, end);
ba395927
KA		 2001 if (ret)
2002 goto error;
2003
2004 /* context entry init */
4ed0d3e6 2005 ret = domain_context_mapping(domain, pdev, CONTEXT_TT_MULTI_LEVEL);
b213203e
DW		 2006 if (ret)
2007 goto error;
2008
2009 return 0;
2010
2011 error:
ba395927
KA		 2012 domain_exit(domain);
2013 return ret;
ba395927
KA		 2014}
2015
2016static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit *rmrr,
2017 struct pci_dev *pdev)
2018{
358dd8ac 2019 if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
ba395927
KA		 2020 return 0;
2021 return iommu_prepare_identity_map(pdev, rmrr->base_address,
2022 rmrr->end_address + 1);
2023}
2024
49a0429e
KA		 2025#ifdef CONFIG_DMAR_FLOPPY_WA
2026static inline void iommu_prepare_isa(void)
2027{
2028 struct pci_dev *pdev;
2029 int ret;
2030
2031 pdev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
2032 if (!pdev)
2033 return;
2034
c7ab48d2 2035 printk(KERN_INFO "IOMMU: Prepare 0-16MiB unity mapping for LPC\n");
49a0429e
KA		 2036 ret = iommu_prepare_identity_map(pdev, 0, 16*1024*1024);
2037
2038 if (ret)
c7ab48d2
DW		 2039 printk(KERN_ERR "IOMMU: Failed to create 0-16MiB identity map; "
2040 "floppy might not work\n");
49a0429e
KA		 2041
2042}
2043#else
2044static inline void iommu_prepare_isa(void)
2045{
2046 return;
2047}
2048#endif /* !CONFIG_DMAR_FLPY_WA */
2049
2c2e2c38 2050static int md_domain_init(struct dmar_domain *domain, int guest_width);
c7ab48d2
DW		 2051
2052static int __init si_domain_work_fn(unsigned long start_pfn,
2053 unsigned long end_pfn, void *datax)
2054{
2055 int *ret = datax;
2056
2057 *ret = iommu_domain_identity_map(si_domain,
2058 (uint64_t)start_pfn << PAGE_SHIFT,
2059 (uint64_t)end_pfn << PAGE_SHIFT);
2060 return *ret;
2061
2062}
2063
071e1374 2064static int __init si_domain_init(int hw)
2c2e2c38
FY		 2065{
2066 struct dmar_drhd_unit *drhd;
2067 struct intel_iommu *iommu;
c7ab48d2 2068 int nid, ret = 0;
2c2e2c38
FY		 2069
2070 si_domain = alloc_domain();
2071 if (!si_domain)
2072 return -EFAULT;
2073
c7ab48d2 2074 pr_debug("Identity mapping domain is domain %d\n", si_domain->id);
2c2e2c38
FY		 2075
2076 for_each_active_iommu(iommu, drhd) {
2077 ret = iommu_attach_domain(si_domain, iommu);
2078 if (ret) {
2079 domain_exit(si_domain);
2080 return -EFAULT;
2081 }
2082 }
2083
2084 if (md_domain_init(si_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
2085 domain_exit(si_domain);
2086 return -EFAULT;
2087 }
2088
2089 si_domain->flags = DOMAIN_FLAG_STATIC_IDENTITY;
2090
19943b0e
DW		 2091 if (hw)
2092 return 0;
2093
c7ab48d2
DW		 2094 for_each_online_node(nid) {
2095 work_with_active_regions(nid, si_domain_work_fn, &ret);
2096 if (ret)
2097 return ret;
2098 }
2099
2c2e2c38
FY		 2100 return 0;
2101}
2102
2103static void domain_remove_one_dev_info(struct dmar_domain *domain,
2104 struct pci_dev *pdev);
2105static int identity_mapping(struct pci_dev *pdev)
2106{
2107 struct device_domain_info *info;
2108
2109 if (likely(!iommu_identity_mapping))
2110 return 0;
2111
2112
2113 list_for_each_entry(info, &si_domain->devices, link)
2114 if (info->dev == pdev)
2115 return 1;
2116 return 0;
2117}
2118
2119static int domain_add_dev_info(struct dmar_domain *domain,
5fe60f4e
DW		 2120 struct pci_dev *pdev,
2121 int translation)
2c2e2c38
FY		 2122{
2123 struct device_domain_info *info;
2124 unsigned long flags;
5fe60f4e 2125 int ret;
2c2e2c38
FY		 2126
2127 info = alloc_devinfo_mem();
2128 if (!info)
2129 return -ENOMEM;
2130
5fe60f4e
DW		 2131 ret = domain_context_mapping(domain, pdev, translation);
2132 if (ret) {
2133 free_devinfo_mem(info);
2134 return ret;
2135 }
2136
2c2e2c38
FY		 2137 info->segment = pci_domain_nr(pdev->bus);
2138 info->bus = pdev->bus->number;
2139 info->devfn = pdev->devfn;
2140 info->dev = pdev;
2141 info->domain = domain;
2142
2143 spin_lock_irqsave(&device_domain_lock, flags);
2144 list_add(&info->link, &domain->devices);
2145 list_add(&info->global, &device_domain_list);
2146 pdev->dev.archdata.iommu = info;
2147 spin_unlock_irqrestore(&device_domain_lock, flags);
2148
2149 return 0;
2150}
2151
6941af28
DW		 2152static int iommu_should_identity_map(struct pci_dev *pdev, int startup)
2153{
2154 if (iommu_identity_mapping == 2)
2155 return IS_GFX_DEVICE(pdev);
2156
3dfc813d
DW		 2157 /*
2158 * We want to start off with all devices in the 1:1 domain, and
2159 * take them out later if we find they can't access all of memory.
2160 *
2161 * However, we can't do this for PCI devices behind bridges,
2162 * because all PCI devices behind the same bridge will end up
2163 * with the same source-id on their transactions.
2164 *
2165 * Practically speaking, we can't change things around for these
2166 * devices at run-time, because we can't be sure there'll be no
2167 * DMA transactions in flight for any of their siblings.
2168 *
2169 * So PCI devices (unless they're on the root bus) as well as
2170 * their parent PCI-PCI or PCIe-PCI bridges must be left _out_ of
2171 * the 1:1 domain, just in _case_ one of their siblings turns out
2172 * not to be able to map all of memory.
2173 */
2174 if (!pdev->is_pcie) {
2175 if (!pci_is_root_bus(pdev->bus))
2176 return 0;
2177 if (pdev->class >> 8 == PCI_CLASS_BRIDGE_PCI)
2178 return 0;
2179 } else if (pdev->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE)
2180 return 0;
2181
2182 /*
2183 * At boot time, we don't yet know if devices will be 64-bit capable.
2184 * Assume that they will -- if they turn out not to be, then we can
2185 * take them out of the 1:1 domain later.
2186 */
6941af28
DW		 2187 if (!startup)
2188 return pdev->dma_mask > DMA_BIT_MASK(32);
2189
2190 return 1;
2191}
2192
071e1374 2193static int __init iommu_prepare_static_identity_mapping(int hw)
2c2e2c38 2194{
2c2e2c38
FY		 2195 struct pci_dev *pdev = NULL;
2196 int ret;
2197
19943b0e 2198 ret = si_domain_init(hw);
2c2e2c38
FY		 2199 if (ret)
2200 return -EFAULT;
2201
2c2e2c38 2202 for_each_pci_dev(pdev) {
6941af28 2203 if (iommu_should_identity_map(pdev, 1)) {
19943b0e
DW		 2204 printk(KERN_INFO "IOMMU: %s identity mapping for device %s\n",
2205 hw ? "hardware" : "software", pci_name(pdev));
62edf5dc 2206
5fe60f4e 2207 ret = domain_add_dev_info(si_domain, pdev,
19943b0e 2208 hw ? CONTEXT_TT_PASS_THROUGH :
62edf5dc
DW		 2209 CONTEXT_TT_MULTI_LEVEL);
2210 if (ret)
2211 return ret;
62edf5dc 2212 }
2c2e2c38
FY		 2213 }
2214
2215 return 0;
2216}
2217
2218int __init init_dmars(void)
ba395927
KA		 2219{
2220 struct dmar_drhd_unit *drhd;
2221 struct dmar_rmrr_unit *rmrr;
2222 struct pci_dev *pdev;
2223 struct intel_iommu *iommu;
9d783ba0 2224 int i, ret;
2c2e2c38 2225
ba395927
KA		 2226 /*
2227 * for each drhd
2228 * allocate root
2229 * initialize and program root entry to not present
2230 * endfor
2231 */
2232 for_each_drhd_unit(drhd) {
5e0d2a6f 2233 g_num_of_iommus++;
2234 /*
2235 * lock not needed as this is only incremented in the single
2236 * threaded kernel __init code path all other access are read
2237 * only
2238 */
2239 }
2240
d9630fe9
WH		 2241 g_iommus = kcalloc(g_num_of_iommus, sizeof(struct intel_iommu *),
2242 GFP_KERNEL);
2243 if (!g_iommus) {
2244 printk(KERN_ERR "Allocating global iommu array failed\n");
2245 ret = -ENOMEM;
2246 goto error;
2247 }
2248
80b20dd8 2249 deferred_flush = kzalloc(g_num_of_iommus *
2250 sizeof(struct deferred_flush_tables), GFP_KERNEL);
2251 if (!deferred_flush) {
5e0d2a6f 2252 ret = -ENOMEM;
2253 goto error;
2254 }
2255
5e0d2a6f 2256 for_each_drhd_unit(drhd) {
2257 if (drhd->ignored)
2258 continue;
1886e8a9
SS		 2259
2260 iommu = drhd->iommu;
d9630fe9 2261 g_iommus[iommu->seq_id] = iommu;
ba395927 2262
e61d98d8
SS		 2263 ret = iommu_init_domains(iommu);
2264 if (ret)
2265 goto error;
2266
ba395927
KA		 2267 /*
2268 * TBD:
2269 * we could share the same root & context tables
2270 * amoung all IOMMU's. Need to Split it later.
2271 */
2272 ret = iommu_alloc_root_entry(iommu);
2273 if (ret) {
2274 printk(KERN_ERR "IOMMU: allocate root entry failed\n");
2275 goto error;
2276 }
4ed0d3e6 2277 if (!ecap_pass_through(iommu->ecap))
19943b0e 2278 hw_pass_through = 0;
ba395927
KA		 2279 }
2280
1531a6a6
SS		 2281 /*
2282 * Start from the sane iommu hardware state.
2283 */
a77b67d4
YS		 2284 for_each_drhd_unit(drhd) {
2285 if (drhd->ignored)
2286 continue;
2287
2288 iommu = drhd->iommu;
1531a6a6
SS		 2289
2290 /*
2291 * If the queued invalidation is already initialized by us
2292 * (for example, while enabling interrupt-remapping) then
2293 * we got the things already rolling from a sane state.
2294 */
2295 if (iommu->qi)
2296 continue;
2297
2298 /*
2299 * Clear any previous faults.
2300 */
2301 dmar_fault(-1, iommu);
2302 /*
2303 * Disable queued invalidation if supported and already enabled
2304 * before OS handover.
2305 */
2306 dmar_disable_qi(iommu);
2307 }
2308
2309 for_each_drhd_unit(drhd) {
2310 if (drhd->ignored)
2311 continue;
2312
2313 iommu = drhd->iommu;
2314
a77b67d4
YS		 2315 if (dmar_enable_qi(iommu)) {
2316 /*
2317 * Queued Invalidate not enabled, use Register Based
2318 * Invalidate
2319 */
2320 iommu->flush.flush_context = __iommu_flush_context;
2321 iommu->flush.flush_iotlb = __iommu_flush_iotlb;
2322 printk(KERN_INFO "IOMMU 0x%Lx: using Register based "
b4e0f9eb
FT		 2323 "invalidation\n",
2324 (unsigned long long)drhd->reg_base_addr);
a77b67d4
YS		 2325 } else {
2326 iommu->flush.flush_context = qi_flush_context;
2327 iommu->flush.flush_iotlb = qi_flush_iotlb;
2328 printk(KERN_INFO "IOMMU 0x%Lx: using Queued "
b4e0f9eb
FT		 2329 "invalidation\n",
2330 (unsigned long long)drhd->reg_base_addr);
a77b67d4
YS		 2331 }
2332 }
2333
19943b0e
DW		 2334 if (iommu_pass_through)
2335 iommu_identity_mapping = 1;
2336#ifdef CONFIG_DMAR_BROKEN_GFX_WA
2337 else
2338 iommu_identity_mapping = 2;
2339#endif
ba395927 2340 /*
19943b0e
DW		 2341 * If pass through is not set or not enabled, setup context entries for
2342 * identity mappings for rmrr, gfx, and isa and may fall back to static
2343 * identity mapping if iommu_identity_mapping is set.
ba395927 2344 */
19943b0e
DW		 2345 if (iommu_identity_mapping) {
2346 ret = iommu_prepare_static_identity_mapping(hw_pass_through);
4ed0d3e6 2347 if (ret) {
19943b0e
DW		 2348 printk(KERN_CRIT "Failed to setup IOMMU pass-through\n");
2349 goto error;
ba395927
KA		 2350 }
2351 }
ba395927 2352 /*
19943b0e
DW		 2353 * For each rmrr
2354 * for each dev attached to rmrr
2355 * do
2356 * locate drhd for dev, alloc domain for dev
2357 * allocate free domain
2358 * allocate page table entries for rmrr
2359 * if context not allocated for bus
2360 * allocate and init context
2361 * set present in root table for this bus
2362 * init context with domain, translation etc
2363 * endfor
2364 * endfor
ba395927 2365 */
19943b0e
DW		 2366 printk(KERN_INFO "IOMMU: Setting RMRR:\n");
2367 for_each_rmrr_units(rmrr) {
2368 for (i = 0; i < rmrr->devices_cnt; i++) {
2369 pdev = rmrr->devices[i];
2370 /*
2371 * some BIOS lists non-exist devices in DMAR
2372 * table.
2373 */
2374 if (!pdev)
2375 continue;
2376 ret = iommu_prepare_rmrr_dev(rmrr, pdev);
2377 if (ret)
2378 printk(KERN_ERR
2379 "IOMMU: mapping reserved region failed\n");
ba395927 2380 }
4ed0d3e6 2381 }
49a0429e 2382
19943b0e
DW		 2383 iommu_prepare_isa();
2384
ba395927
KA		 2385 /*
2386 * for each drhd
2387 * enable fault log
2388 * global invalidate context cache
2389 * global invalidate iotlb
2390 * enable translation
2391 */
2392 for_each_drhd_unit(drhd) {
2393 if (drhd->ignored)
2394 continue;
2395 iommu = drhd->iommu;
ba395927
KA		 2396
2397 iommu_flush_write_buffer(iommu);
2398
3460a6d9
KA		 2399 ret = dmar_set_interrupt(iommu);
2400 if (ret)
2401 goto error;
2402
ba395927
KA		 2403 iommu_set_root_entry(iommu);
2404
4c25a2c1 2405 iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL);
1f0ef2aa 2406 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
f8bab735 2407
ba395927
KA		 2408 ret = iommu_enable_translation(iommu);
2409 if (ret)
2410 goto error;
b94996c9
DW		 2411
2412 iommu_disable_protect_mem_regions(iommu);
ba395927
KA		 2413 }
2414
2415 return 0;
2416error:
2417 for_each_drhd_unit(drhd) {
2418 if (drhd->ignored)
2419 continue;
2420 iommu = drhd->iommu;
2421 free_iommu(iommu);
2422 }
d9630fe9 2423 kfree(g_iommus);
ba395927
KA		 2424 return ret;
2425}
2426
5a5e02a6 2427/* This takes a number of _MM_ pages, not VTD pages */
875764de
DW		 2428static struct iova *intel_alloc_iova(struct device *dev,
2429 struct dmar_domain *domain,
2430 unsigned long nrpages, uint64_t dma_mask)
ba395927 2431{
ba395927 2432 struct pci_dev *pdev = to_pci_dev(dev);
ba395927 2433 struct iova *iova = NULL;
ba395927 2434
875764de
DW		 2435 /* Restrict dma_mask to the width that the iommu can handle */
2436 dma_mask = min_t(uint64_t, DOMAIN_MAX_ADDR(domain->gaw), dma_mask);
2437
2438 if (!dmar_forcedac && dma_mask > DMA_BIT_MASK(32)) {
ba395927
KA		 2439 /*
2440 * First try to allocate an io virtual address in
284901a9 2441 * DMA_BIT_MASK(32) and if that fails then try allocating
3609801e 2442 * from higher range
ba395927 2443 */
875764de
DW		 2444 iova = alloc_iova(&domain->iovad, nrpages,
2445 IOVA_PFN(DMA_BIT_MASK(32)), 1);
2446 if (iova)
2447 return iova;
2448 }
2449 iova = alloc_iova(&domain->iovad, nrpages, IOVA_PFN(dma_mask), 1);
2450 if (unlikely(!iova)) {
2451 printk(KERN_ERR "Allocating %ld-page iova for %s failed",
2452 nrpages, pci_name(pdev));
f76aec76
KA		 2453 return NULL;
2454 }
2455
2456 return iova;
2457}
2458
147202aa 2459static struct dmar_domain *__get_valid_domain_for_dev(struct pci_dev *pdev)
f76aec76
KA		 2460{
2461 struct dmar_domain *domain;
2462 int ret;
2463
2464 domain = get_domain_for_dev(pdev,
2465 DEFAULT_DOMAIN_ADDRESS_WIDTH);
2466 if (!domain) {
2467 printk(KERN_ERR
2468 "Allocating domain for %s failed", pci_name(pdev));
4fe05bbc 2469 return NULL;
ba395927
KA		 2470 }
2471
2472 /* make sure context mapping is ok */
5331fe6f 2473 if (unlikely(!domain_context_mapped(pdev))) {
4ed0d3e6
FY		 2474 ret = domain_context_mapping(domain, pdev,
2475 CONTEXT_TT_MULTI_LEVEL);
f76aec76
KA		 2476 if (ret) {
2477 printk(KERN_ERR
2478 "Domain context map for %s failed",
2479 pci_name(pdev));
4fe05bbc 2480 return NULL;
f76aec76 2481 }
ba395927
KA		 2482 }
2483
f76aec76
KA		 2484 return domain;
2485}
2486
147202aa
DW		 2487static inline struct dmar_domain *get_valid_domain_for_dev(struct pci_dev *dev)
2488{
2489 struct device_domain_info *info;
2490
2491 /* No lock here, assumes no domain exit in normal case */
2492 info = dev->dev.archdata.iommu;
2493 if (likely(info))
2494 return info->domain;
2495
2496 return __get_valid_domain_for_dev(dev);
2497}
2498
2c2e2c38
FY		 2499static int iommu_dummy(struct pci_dev *pdev)
2500{
2501 return pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO;
2502}
2503
2504/* Check if the pdev needs to go through non-identity map and unmap process.*/
73676832 2505static int iommu_no_mapping(struct device *dev)
2c2e2c38 2506{
73676832 2507 struct pci_dev *pdev;
2c2e2c38
FY		 2508 int found;
2509
73676832
DW		 2510 if (unlikely(dev->bus != &pci_bus_type))
2511 return 1;
2512
2513 pdev = to_pci_dev(dev);
1e4c64c4
DW		 2514 if (iommu_dummy(pdev))
2515 return 1;
2516
2c2e2c38 2517 if (!iommu_identity_mapping)
1e4c64c4 2518 return 0;
2c2e2c38
FY		 2519
2520 found = identity_mapping(pdev);
2521 if (found) {
6941af28 2522 if (iommu_should_identity_map(pdev, 0))
2c2e2c38
FY		 2523 return 1;
2524 else {
2525 /*
2526 * 32 bit DMA is removed from si_domain and fall back
2527 * to non-identity mapping.
2528 */
2529 domain_remove_one_dev_info(si_domain, pdev);
2530 printk(KERN_INFO "32bit %s uses non-identity mapping\n",
2531 pci_name(pdev));
2532 return 0;
2533 }
2534 } else {
2535 /*
2536 * In case of a detached 64 bit DMA device from vm, the device
2537 * is put into si_domain for identity mapping.
2538 */
6941af28 2539 if (iommu_should_identity_map(pdev, 0)) {
2c2e2c38 2540 int ret;
5fe60f4e
DW		 2541 ret = domain_add_dev_info(si_domain, pdev,
2542 hw_pass_through ?
2543 CONTEXT_TT_PASS_THROUGH :
2544 CONTEXT_TT_MULTI_LEVEL);
2c2e2c38
FY		 2545 if (!ret) {
2546 printk(KERN_INFO "64bit %s uses identity mapping\n",
2547 pci_name(pdev));
2548 return 1;
2549 }
2550 }
2551 }
2552
1e4c64c4 2553 return 0;
2c2e2c38
FY		 2554}
2555
bb9e6d65
FT		 2556static dma_addr_t __intel_map_single(struct device *hwdev, phys_addr_t paddr,
2557 size_t size, int dir, u64 dma_mask)
f76aec76
KA		 2558{
2559 struct pci_dev *pdev = to_pci_dev(hwdev);
f76aec76 2560 struct dmar_domain *domain;
5b6985ce 2561 phys_addr_t start_paddr;
f76aec76
KA		 2562 struct iova *iova;
2563 int prot = 0;
6865f0d1 2564 int ret;
8c11e798 2565 struct intel_iommu *iommu;
33041ec0 2566 unsigned long paddr_pfn = paddr >> PAGE_SHIFT;
f76aec76
KA		 2567
2568 BUG_ON(dir == DMA_NONE);
2c2e2c38 2569
73676832 2570 if (iommu_no_mapping(hwdev))
6865f0d1 2571 return paddr;
f76aec76
KA		 2572
2573 domain = get_valid_domain_for_dev(pdev);
2574 if (!domain)
2575 return 0;
2576
8c11e798 2577 iommu = domain_get_iommu(domain);
88cb6a74 2578 size = aligned_nrpages(paddr, size);
f76aec76 2579
5a5e02a6
DW		 2580 iova = intel_alloc_iova(hwdev, domain, dma_to_mm_pfn(size),
2581 pdev->dma_mask);
f76aec76
KA		 2582 if (!iova)
2583 goto error;
2584
ba395927
KA		 2585 /*
2586 * Check if DMAR supports zero-length reads on write only
2587 * mappings..
2588 */
2589 if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
8c11e798 2590 !cap_zlr(iommu->cap))
ba395927
KA		 2591 prot |= DMA_PTE_READ;
2592 if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
2593 prot |= DMA_PTE_WRITE;
2594 /*
6865f0d1 2595 * paddr - (paddr + size) might be partial page, we should map the whole
ba395927 2596 * page. Note: if two part of one page are separately mapped, we
6865f0d1 2597 * might have two guest_addr mapping to the same host paddr, but this
ba395927
KA		 2598 * is not a big problem
2599 */
0ab36de2 2600 ret = domain_pfn_mapping(domain, mm_to_dma_pfn(iova->pfn_lo),
33041ec0 2601 mm_to_dma_pfn(paddr_pfn), size, prot);
ba395927
KA		 2602 if (ret)
2603 goto error;
2604
1f0ef2aa
DW		 2605 /* it's a non-present to present mapping. Only flush if caching mode */
2606 if (cap_caching_mode(iommu->cap))
03d6a246 2607 iommu_flush_iotlb_psi(iommu, 0, mm_to_dma_pfn(iova->pfn_lo), size);
1f0ef2aa 2608 else
8c11e798 2609 iommu_flush_write_buffer(iommu);
f76aec76 2610
03d6a246
DW		 2611 start_paddr = (phys_addr_t)iova->pfn_lo << PAGE_SHIFT;
2612 start_paddr += paddr & ~PAGE_MASK;
2613 return start_paddr;
ba395927 2614
ba395927 2615error:
f76aec76
KA		 2616 if (iova)
2617 __free_iova(&domain->iovad, iova);
4cf2e75d 2618 printk(KERN_ERR"Device %s request: %zx@%llx dir %d --- failed\n",
5b6985ce 2619 pci_name(pdev), size, (unsigned long long)paddr, dir);
ba395927
KA		 2620 return 0;
2621}
2622
ffbbef5c
FT		 2623static dma_addr_t intel_map_page(struct device *dev, struct page *page,
2624 unsigned long offset, size_t size,
2625 enum dma_data_direction dir,
2626 struct dma_attrs *attrs)
bb9e6d65 2627{
ffbbef5c
FT		 2628 return __intel_map_single(dev, page_to_phys(page) + offset, size,
2629 dir, to_pci_dev(dev)->dma_mask);
bb9e6d65
FT		 2630}
2631
5e0d2a6f 2632static void flush_unmaps(void)
2633{
80b20dd8 2634 int i, j;
5e0d2a6f 2635
5e0d2a6f 2636 timer_on = 0;
2637
2638 /* just flush them all */
2639 for (i = 0; i < g_num_of_iommus; i++) {
a2bb8459
WH		 2640 struct intel_iommu *iommu = g_iommus[i];
2641 if (!iommu)
2642 continue;
c42d9f32 2643
9dd2fe89
YZ		 2644 if (!deferred_flush[i].next)
2645 continue;
2646
2647 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
93a23a72 2648 DMA_TLB_GLOBAL_FLUSH);
9dd2fe89 2649 for (j = 0; j < deferred_flush[i].next; j++) {
93a23a72
YZ		 2650 unsigned long mask;
2651 struct iova *iova = deferred_flush[i].iova[j];
2652
64de5af0 2653 mask = ilog2(mm_to_dma_pfn(iova->pfn_hi - iova->pfn_lo + 1));
93a23a72 2654 iommu_flush_dev_iotlb(deferred_flush[i].domain[j],
64de5af0 2655 (uint64_t)iova->pfn_lo << PAGE_SHIFT, mask);
93a23a72 2656 __free_iova(&deferred_flush[i].domain[j]->iovad, iova);
80b20dd8 2657 }
9dd2fe89 2658 deferred_flush[i].next = 0;
5e0d2a6f 2659 }
2660
5e0d2a6f 2661 list_size = 0;
5e0d2a6f 2662}
2663
2664static void flush_unmaps_timeout(unsigned long data)
2665{
80b20dd8 2666 unsigned long flags;
2667
2668 spin_lock_irqsave(&async_umap_flush_lock, flags);
5e0d2a6f 2669 flush_unmaps();
80b20dd8 2670 spin_unlock_irqrestore(&async_umap_flush_lock, flags);
5e0d2a6f 2671}
2672
2673static void add_unmap(struct dmar_domain *dom, struct iova *iova)
2674{
2675 unsigned long flags;
80b20dd8 2676 int next, iommu_id;
8c11e798 2677 struct intel_iommu *iommu;
5e0d2a6f 2678
2679 spin_lock_irqsave(&async_umap_flush_lock, flags);
80b20dd8 2680 if (list_size == HIGH_WATER_MARK)
2681 flush_unmaps();
2682
8c11e798
WH		 2683 iommu = domain_get_iommu(dom);
2684 iommu_id = iommu->seq_id;
c42d9f32 2685
80b20dd8 2686 next = deferred_flush[iommu_id].next;
2687 deferred_flush[iommu_id].domain[next] = dom;
2688 deferred_flush[iommu_id].iova[next] = iova;
2689 deferred_flush[iommu_id].next++;
5e0d2a6f 2690
2691 if (!timer_on) {
2692 mod_timer(&unmap_timer, jiffies + msecs_to_jiffies(10));
2693 timer_on = 1;
2694 }
2695 list_size++;
2696 spin_unlock_irqrestore(&async_umap_flush_lock, flags);
2697}
2698
ffbbef5c
FT		 2699static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr,
2700 size_t size, enum dma_data_direction dir,
2701 struct dma_attrs *attrs)
ba395927 2702{
ba395927 2703 struct pci_dev *pdev = to_pci_dev(dev);
f76aec76 2704 struct dmar_domain *domain;
d794dc9b 2705 unsigned long start_pfn, last_pfn;
ba395927 2706 struct iova *iova;
8c11e798 2707 struct intel_iommu *iommu;
ba395927 2708
73676832 2709 if (iommu_no_mapping(dev))
f76aec76 2710 return;
2c2e2c38 2711
ba395927
KA		 2712 domain = find_domain(pdev);
2713 BUG_ON(!domain);
2714
8c11e798
WH		 2715 iommu = domain_get_iommu(domain);
2716
ba395927 2717 iova = find_iova(&domain->iovad, IOVA_PFN(dev_addr));
85b98276
DW		 2718 if (WARN_ONCE(!iova, "Driver unmaps unmatched page at PFN %llx\n",
2719 (unsigned long long)dev_addr))
ba395927 2720 return;
ba395927 2721
d794dc9b
DW		 2722 start_pfn = mm_to_dma_pfn(iova->pfn_lo);
2723 last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
ba395927 2724
d794dc9b
DW		 2725 pr_debug("Device %s unmapping: pfn %lx-%lx\n",
2726 pci_name(pdev), start_pfn, last_pfn);
ba395927 2727
f76aec76 2728 /* clear the whole page */
d794dc9b
DW		 2729 dma_pte_clear_range(domain, start_pfn, last_pfn);
2730
f76aec76 2731 /* free page tables */
d794dc9b
DW		 2732 dma_pte_free_pagetable(domain, start_pfn, last_pfn);
2733
5e0d2a6f 2734 if (intel_iommu_strict) {
03d6a246 2735 iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
d794dc9b 2736 last_pfn - start_pfn + 1);
5e0d2a6f 2737 /* free iova */
2738 __free_iova(&domain->iovad, iova);
2739 } else {
2740 add_unmap(domain, iova);
2741 /*
2742 * queue up the release of the unmap to save the 1/6th of the
2743 * cpu used up by the iotlb flush operation...
2744 */
5e0d2a6f 2745 }
ba395927
KA		 2746}
2747
d7ab5c46
FT		 2748static void *intel_alloc_coherent(struct device *hwdev, size_t size,
2749 dma_addr_t *dma_handle, gfp_t flags)
ba395927
KA		 2750{
2751 void *vaddr;
2752 int order;
2753
5b6985ce 2754 size = PAGE_ALIGN(size);
ba395927
KA		 2755 order = get_order(size);
2756 flags &= ~(GFP_DMA | GFP_DMA32);
2757
2758 vaddr = (void *)__get_free_pages(flags, order);
2759 if (!vaddr)
2760 return NULL;
2761 memset(vaddr, 0, size);
2762
bb9e6d65
FT		 2763 *dma_handle = __intel_map_single(hwdev, virt_to_bus(vaddr), size,
2764 DMA_BIDIRECTIONAL,
2765 hwdev->coherent_dma_mask);
ba395927
KA		 2766 if (*dma_handle)
2767 return vaddr;
2768 free_pages((unsigned long)vaddr, order);
2769 return NULL;
2770}
2771
d7ab5c46
FT		 2772static void intel_free_coherent(struct device *hwdev, size_t size, void *vaddr,
2773 dma_addr_t dma_handle)
ba395927
KA		 2774{
2775 int order;
2776
5b6985ce 2777 size = PAGE_ALIGN(size);
ba395927
KA		 2778 order = get_order(size);
2779
0db9b7ae 2780 intel_unmap_page(hwdev, dma_handle, size, DMA_BIDIRECTIONAL, NULL);
ba395927
KA		 2781 free_pages((unsigned long)vaddr, order);
2782}
2783
d7ab5c46
FT		 2784static void intel_unmap_sg(struct device *hwdev, struct scatterlist *sglist,
2785 int nelems, enum dma_data_direction dir,
2786 struct dma_attrs *attrs)
ba395927 2787{
ba395927
KA		 2788 struct pci_dev *pdev = to_pci_dev(hwdev);
2789 struct dmar_domain *domain;
d794dc9b 2790 unsigned long start_pfn, last_pfn;
f76aec76 2791 struct iova *iova;
8c11e798 2792 struct intel_iommu *iommu;
ba395927 2793
73676832 2794 if (iommu_no_mapping(hwdev))
ba395927
KA		 2795 return;
2796
2797 domain = find_domain(pdev);
8c11e798
WH		 2798 BUG_ON(!domain);
2799
2800 iommu = domain_get_iommu(domain);
ba395927 2801
c03ab37c 2802 iova = find_iova(&domain->iovad, IOVA_PFN(sglist[0].dma_address));
85b98276
DW		 2803 if (WARN_ONCE(!iova, "Driver unmaps unmatched sglist at PFN %llx\n",
2804 (unsigned long long)sglist[0].dma_address))
f76aec76 2805 return;
f76aec76 2806
d794dc9b
DW		 2807 start_pfn = mm_to_dma_pfn(iova->pfn_lo);
2808 last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
f76aec76
KA		 2809
2810 /* clear the whole page */
d794dc9b
DW		 2811 dma_pte_clear_range(domain, start_pfn, last_pfn);
2812
f76aec76 2813 /* free page tables */
d794dc9b 2814 dma_pte_free_pagetable(domain, start_pfn, last_pfn);
f76aec76 2815
acea0018
DW		 2816 if (intel_iommu_strict) {
2817 iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
2818 last_pfn - start_pfn + 1);
2819 /* free iova */
2820 __free_iova(&domain->iovad, iova);
2821 } else {
2822 add_unmap(domain, iova);
2823 /*
2824 * queue up the release of the unmap to save the 1/6th of the
2825 * cpu used up by the iotlb flush operation...
2826 */
2827 }
ba395927
KA		 2828}
2829
ba395927 2830static int intel_nontranslate_map_sg(struct device *hddev,
c03ab37c 2831 struct scatterlist *sglist, int nelems, int dir)
ba395927
KA		 2832{
2833 int i;
c03ab37c 2834 struct scatterlist *sg;
ba395927 2835
c03ab37c 2836 for_each_sg(sglist, sg, nelems, i) {
12d4d40e 2837 BUG_ON(!sg_page(sg));
4cf2e75d 2838 sg->dma_address = page_to_phys(sg_page(sg)) + sg->offset;
c03ab37c 2839 sg->dma_length = sg->length;
ba395927
KA		 2840 }
2841 return nelems;
2842}
2843
d7ab5c46
FT		 2844static int intel_map_sg(struct device *hwdev, struct scatterlist *sglist, int nelems,
2845 enum dma_data_direction dir, struct dma_attrs *attrs)
ba395927 2846{
ba395927 2847 int i;
ba395927
KA		 2848 struct pci_dev *pdev = to_pci_dev(hwdev);
2849 struct dmar_domain *domain;
f76aec76
KA		 2850 size_t size = 0;
2851 int prot = 0;
b536d24d 2852 size_t offset_pfn = 0;
f76aec76
KA		 2853 struct iova *iova = NULL;
2854 int ret;
c03ab37c 2855 struct scatterlist *sg;
b536d24d 2856 unsigned long start_vpfn;
8c11e798 2857 struct intel_iommu *iommu;
ba395927
KA		 2858
2859 BUG_ON(dir == DMA_NONE);
73676832 2860 if (iommu_no_mapping(hwdev))
c03ab37c 2861 return intel_nontranslate_map_sg(hwdev, sglist, nelems, dir);
ba395927 2862
f76aec76
KA		 2863 domain = get_valid_domain_for_dev(pdev);
2864 if (!domain)
2865 return 0;
2866
8c11e798
WH		 2867 iommu = domain_get_iommu(domain);
2868
b536d24d 2869 for_each_sg(sglist, sg, nelems, i)
88cb6a74 2870 size += aligned_nrpages(sg->offset, sg->length);
f76aec76 2871
5a5e02a6
DW		 2872 iova = intel_alloc_iova(hwdev, domain, dma_to_mm_pfn(size),
2873 pdev->dma_mask);
f76aec76 2874 if (!iova) {
c03ab37c 2875 sglist->dma_length = 0;
f76aec76
KA		 2876 return 0;
2877 }
2878
2879 /*
2880 * Check if DMAR supports zero-length reads on write only
2881 * mappings..
2882 */
2883 if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
8c11e798 2884 !cap_zlr(iommu->cap))
f76aec76
KA		 2885 prot |= DMA_PTE_READ;
2886 if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
2887 prot |= DMA_PTE_WRITE;
2888
b536d24d 2889 start_vpfn = mm_to_dma_pfn(iova->pfn_lo);
e1605495 2890
f532959b 2891 ret = domain_sg_mapping(domain, start_vpfn, sglist, size, prot);
e1605495
DW		 2892 if (unlikely(ret)) {
2893 /* clear the page */
2894 dma_pte_clear_range(domain, start_vpfn,
2895 start_vpfn + size - 1);
2896 /* free page tables */
2897 dma_pte_free_pagetable(domain, start_vpfn,
2898 start_vpfn + size - 1);
2899 /* free iova */
2900 __free_iova(&domain->iovad, iova);
2901 return 0;
ba395927
KA		 2902 }
2903
1f0ef2aa
DW		 2904 /* it's a non-present to present mapping. Only flush if caching mode */
2905 if (cap_caching_mode(iommu->cap))
03d6a246 2906 iommu_flush_iotlb_psi(iommu, 0, start_vpfn, offset_pfn);
1f0ef2aa 2907 else
8c11e798 2908 iommu_flush_write_buffer(iommu);
1f0ef2aa 2909
ba395927
KA		 2910 return nelems;
2911}
2912
dfb805e8
FT		 2913static int intel_mapping_error(struct device *dev, dma_addr_t dma_addr)
2914{
2915 return !dma_addr;
2916}
2917
160c1d8e 2918struct dma_map_ops intel_dma_ops = {
ba395927
KA		 2919 .alloc_coherent = intel_alloc_coherent,
2920 .free_coherent = intel_free_coherent,
ba395927
KA		 2921 .map_sg = intel_map_sg,
2922 .unmap_sg = intel_unmap_sg,
ffbbef5c
FT		 2923 .map_page = intel_map_page,
2924 .unmap_page = intel_unmap_page,
dfb805e8 2925 .mapping_error = intel_mapping_error,
ba395927
KA		 2926};
2927
2928static inline int iommu_domain_cache_init(void)
2929{
2930 int ret = 0;
2931
2932 iommu_domain_cache = kmem_cache_create("iommu_domain",
2933 sizeof(struct dmar_domain),
2934 0,
2935 SLAB_HWCACHE_ALIGN,
2936
2937 NULL);
2938 if (!iommu_domain_cache) {
2939 printk(KERN_ERR "Couldn't create iommu_domain cache\n");
2940 ret = -ENOMEM;
2941 }
2942
2943 return ret;
2944}
2945
2946static inline int iommu_devinfo_cache_init(void)
2947{
2948 int ret = 0;
2949
2950 iommu_devinfo_cache = kmem_cache_create("iommu_devinfo",
2951 sizeof(struct device_domain_info),
2952 0,
2953 SLAB_HWCACHE_ALIGN,
ba395927
KA		 2954 NULL);
2955 if (!iommu_devinfo_cache) {
2956 printk(KERN_ERR "Couldn't create devinfo cache\n");
2957 ret = -ENOMEM;
2958 }
2959
2960 return ret;
2961}
2962
2963static inline int iommu_iova_cache_init(void)
2964{
2965 int ret = 0;
2966
2967 iommu_iova_cache = kmem_cache_create("iommu_iova",
2968 sizeof(struct iova),
2969 0,
2970 SLAB_HWCACHE_ALIGN,
ba395927
KA		 2971 NULL);
2972 if (!iommu_iova_cache) {
2973 printk(KERN_ERR "Couldn't create iova cache\n");
2974 ret = -ENOMEM;
2975 }
2976
2977 return ret;
2978}
2979
2980static int __init iommu_init_mempool(void)
2981{
2982 int ret;
2983 ret = iommu_iova_cache_init();
2984 if (ret)
2985 return ret;
2986
2987 ret = iommu_domain_cache_init();
2988 if (ret)
2989 goto domain_error;
2990
2991 ret = iommu_devinfo_cache_init();
2992 if (!ret)
2993 return ret;
2994
2995 kmem_cache_destroy(iommu_domain_cache);
2996domain_error:
2997 kmem_cache_destroy(iommu_iova_cache);
2998
2999 return -ENOMEM;
3000}
3001
3002static void __init iommu_exit_mempool(void)
3003{
3004 kmem_cache_destroy(iommu_devinfo_cache);
3005 kmem_cache_destroy(iommu_domain_cache);
3006 kmem_cache_destroy(iommu_iova_cache);
3007
3008}
3009
ba395927
KA		 3010static void __init init_no_remapping_devices(void)
3011{
3012 struct dmar_drhd_unit *drhd;
3013
3014 for_each_drhd_unit(drhd) {
3015 if (!drhd->include_all) {
3016 int i;
3017 for (i = 0; i < drhd->devices_cnt; i++)
3018 if (drhd->devices[i] != NULL)
3019 break;
3020 /* ignore DMAR unit if no pci devices exist */
3021 if (i == drhd->devices_cnt)
3022 drhd->ignored = 1;
3023 }
3024 }
3025
3026 if (dmar_map_gfx)
3027 return;
3028
3029 for_each_drhd_unit(drhd) {
3030 int i;
3031 if (drhd->ignored || drhd->include_all)
3032 continue;
3033
3034 for (i = 0; i < drhd->devices_cnt; i++)
3035 if (drhd->devices[i] &&
3036 !IS_GFX_DEVICE(drhd->devices[i]))
3037 break;
3038
3039 if (i < drhd->devices_cnt)
3040 continue;
3041
3042 /* bypass IOMMU if it is just for gfx devices */
3043 drhd->ignored = 1;
3044 for (i = 0; i < drhd->devices_cnt; i++) {
3045 if (!drhd->devices[i])
3046 continue;
358dd8ac 3047 drhd->devices[i]->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
ba395927
KA		 3048 }
3049 }
3050}
3051
f59c7b69
FY		 3052#ifdef CONFIG_SUSPEND
3053static int init_iommu_hw(void)
3054{
3055 struct dmar_drhd_unit *drhd;
3056 struct intel_iommu *iommu = NULL;
3057
3058 for_each_active_iommu(iommu, drhd)
3059 if (iommu->qi)
3060 dmar_reenable_qi(iommu);
3061
3062 for_each_active_iommu(iommu, drhd) {
3063 iommu_flush_write_buffer(iommu);
3064
3065 iommu_set_root_entry(iommu);
3066
3067 iommu->flush.flush_context(iommu, 0, 0, 0,
1f0ef2aa 3068 DMA_CCMD_GLOBAL_INVL);
f59c7b69 3069 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
1f0ef2aa 3070 DMA_TLB_GLOBAL_FLUSH);
f59c7b69 3071 iommu_enable_translation(iommu);
b94996c9 3072 iommu_disable_protect_mem_regions(iommu);
f59c7b69
FY		 3073 }
3074
3075 return 0;
3076}
3077
3078static void iommu_flush_all(void)
3079{
3080 struct dmar_drhd_unit *drhd;
3081 struct intel_iommu *iommu;
3082
3083 for_each_active_iommu(iommu, drhd) {
3084 iommu->flush.flush_context(iommu, 0, 0, 0,
1f0ef2aa 3085 DMA_CCMD_GLOBAL_INVL);
f59c7b69 3086 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
1f0ef2aa 3087 DMA_TLB_GLOBAL_FLUSH);
f59c7b69
FY		 3088 }
3089}
3090
3091static int iommu_suspend(struct sys_device *dev, pm_message_t state)
3092{
3093 struct dmar_drhd_unit *drhd;
3094 struct intel_iommu *iommu = NULL;
3095 unsigned long flag;
3096
3097 for_each_active_iommu(iommu, drhd) {
3098 iommu->iommu_state = kzalloc(sizeof(u32) * MAX_SR_DMAR_REGS,
3099 GFP_ATOMIC);
3100 if (!iommu->iommu_state)
3101 goto nomem;
3102 }
3103
3104 iommu_flush_all();
3105
3106 for_each_active_iommu(iommu, drhd) {
3107 iommu_disable_translation(iommu);
3108
3109 spin_lock_irqsave(&iommu->register_lock, flag);
3110
3111 iommu->iommu_state[SR_DMAR_FECTL_REG] =
3112 readl(iommu->reg + DMAR_FECTL_REG);
3113 iommu->iommu_state[SR_DMAR_FEDATA_REG] =
3114 readl(iommu->reg + DMAR_FEDATA_REG);
3115 iommu->iommu_state[SR_DMAR_FEADDR_REG] =
3116 readl(iommu->reg + DMAR_FEADDR_REG);
3117 iommu->iommu_state[SR_DMAR_FEUADDR_REG] =
3118 readl(iommu->reg + DMAR_FEUADDR_REG);
3119
3120 spin_unlock_irqrestore(&iommu->register_lock, flag);
3121 }
3122 return 0;
3123
3124nomem:
3125 for_each_active_iommu(iommu, drhd)
3126 kfree(iommu->iommu_state);
3127
3128 return -ENOMEM;
3129}
3130
3131static int iommu_resume(struct sys_device *dev)
3132{
3133 struct dmar_drhd_unit *drhd;
3134 struct intel_iommu *iommu = NULL;
3135 unsigned long flag;
3136
3137 if (init_iommu_hw()) {
3138 WARN(1, "IOMMU setup failed, DMAR can not resume!\n");
3139 return -EIO;
3140 }
3141
3142 for_each_active_iommu(iommu, drhd) {
3143
3144 spin_lock_irqsave(&iommu->register_lock, flag);
3145
3146 writel(iommu->iommu_state[SR_DMAR_FECTL_REG],
3147 iommu->reg + DMAR_FECTL_REG);
3148 writel(iommu->iommu_state[SR_DMAR_FEDATA_REG],
3149 iommu->reg + DMAR_FEDATA_REG);
3150 writel(iommu->iommu_state[SR_DMAR_FEADDR_REG],
3151 iommu->reg + DMAR_FEADDR_REG);
3152 writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG],
3153 iommu->reg + DMAR_FEUADDR_REG);
3154
3155 spin_unlock_irqrestore(&iommu->register_lock, flag);
3156 }
3157
3158 for_each_active_iommu(iommu, drhd)
3159 kfree(iommu->iommu_state);
3160
3161 return 0;
3162}
3163
3164static struct sysdev_class iommu_sysclass = {
3165 .name = "iommu",
3166 .resume = iommu_resume,
3167 .suspend = iommu_suspend,
3168};
3169
3170static struct sys_device device_iommu = {
3171 .cls = &iommu_sysclass,
3172};
3173
3174static int __init init_iommu_sysfs(void)
3175{
3176 int error;
3177
3178 error = sysdev_class_register(&iommu_sysclass);
3179 if (error)
3180 return error;
3181
3182 error = sysdev_register(&device_iommu);
3183 if (error)
3184 sysdev_class_unregister(&iommu_sysclass);
3185
3186 return error;
3187}
3188
3189#else
3190static int __init init_iommu_sysfs(void)
3191{
3192 return 0;
3193}
3194#endif /* CONFIG_PM */
3195
ba395927
KA		 3196int __init intel_iommu_init(void)
3197{
3198 int ret = 0;
a59b50e9 3199 int force_on = 0;
ba395927 3200
a59b50e9
JC		 3201 /* VT-d is required for a TXT/tboot launch, so enforce that */
3202 force_on = tboot_force_iommu();
3203
3204 if (dmar_table_init()) {
3205 if (force_on)
3206 panic("tboot: Failed to initialize DMAR table\n");
ba395927 3207 return -ENODEV;
a59b50e9 3208 }
ba395927 3209
a59b50e9
JC		 3210 if (dmar_dev_scope_init()) {
3211 if (force_on)
3212 panic("tboot: Failed to initialize DMAR device scope\n");
1886e8a9 3213 return -ENODEV;
a59b50e9 3214 }
1886e8a9 3215
2ae21010
SS		 3216 /*
3217 * Check the need for DMA-remapping initialization now.
3218 * Above initialization will also be used by Interrupt-remapping.
3219 */
19943b0e 3220 if (no_iommu || swiotlb || dmar_disabled)
2ae21010
SS		 3221 return -ENODEV;
3222
ba395927
KA		 3223 iommu_init_mempool();
3224 dmar_init_reserved_ranges();
3225
3226 init_no_remapping_devices();
3227
3228 ret = init_dmars();
3229 if (ret) {
a59b50e9
JC		 3230 if (force_on)
3231 panic("tboot: Failed to initialize DMARs\n");
ba395927
KA		 3232 printk(KERN_ERR "IOMMU: dmar init failed\n");
3233 put_iova_domain(&reserved_iova_list);
3234 iommu_exit_mempool();
3235 return ret;
3236 }
3237 printk(KERN_INFO
3238 "PCI-DMA: Intel(R) Virtualization Technology for Directed I/O\n");
3239
5e0d2a6f 3240 init_timer(&unmap_timer);
ba395927 3241 force_iommu = 1;
19943b0e 3242 dma_ops = &intel_dma_ops;
4ed0d3e6 3243
f59c7b69 3244 init_iommu_sysfs();
a8bcbb0d
JR		 3245
3246 register_iommu(&intel_iommu_ops);
3247
ba395927
KA		 3248 return 0;
3249}
e820482c 3250
3199aa6b
HW		 3251static void iommu_detach_dependent_devices(struct intel_iommu *iommu,
3252 struct pci_dev *pdev)
3253{
3254 struct pci_dev *tmp, *parent;
3255
3256 if (!iommu || !pdev)
3257 return;
3258
3259 /* dependent device detach */
3260 tmp = pci_find_upstream_pcie_bridge(pdev);
3261 /* Secondary interface's bus number and devfn 0 */
3262 if (tmp) {
3263 parent = pdev->bus->self;
3264 while (parent != tmp) {
3265 iommu_detach_dev(iommu, parent->bus->number,
276dbf99 3266 parent->devfn);
3199aa6b
HW		 3267 parent = parent->bus->self;
3268 }
3269 if (tmp->is_pcie) /* this is a PCIE-to-PCI bridge */
3270 iommu_detach_dev(iommu,
3271 tmp->subordinate->number, 0);
3272 else /* this is a legacy PCI bridge */
276dbf99
DW		 3273 iommu_detach_dev(iommu, tmp->bus->number,
3274 tmp->devfn);
3199aa6b
HW		 3275 }
3276}
3277
2c2e2c38 3278static void domain_remove_one_dev_info(struct dmar_domain *domain,
c7151a8d
WH		 3279 struct pci_dev *pdev)
3280{
3281 struct device_domain_info *info;
3282 struct intel_iommu *iommu;
3283 unsigned long flags;
3284 int found = 0;
3285 struct list_head *entry, *tmp;
3286
276dbf99
DW		 3287 iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
3288 pdev->devfn);
c7151a8d
WH		 3289 if (!iommu)
3290 return;
3291
3292 spin_lock_irqsave(&device_domain_lock, flags);
3293 list_for_each_safe(entry, tmp, &domain->devices) {
3294 info = list_entry(entry, struct device_domain_info, link);
276dbf99 3295 /* No need to compare PCI domain; it has to be the same */
c7151a8d
WH		 3296 if (info->bus == pdev->bus->number &&
3297 info->devfn == pdev->devfn) {
3298 list_del(&info->link);
3299 list_del(&info->global);
3300 if (info->dev)
3301 info->dev->dev.archdata.iommu = NULL;
3302 spin_unlock_irqrestore(&device_domain_lock, flags);
3303
93a23a72 3304 iommu_disable_dev_iotlb(info);
c7151a8d 3305 iommu_detach_dev(iommu, info->bus, info->devfn);
3199aa6b 3306 iommu_detach_dependent_devices(iommu, pdev);
c7151a8d
WH		 3307 free_devinfo_mem(info);
3308
3309 spin_lock_irqsave(&device_domain_lock, flags);
3310
3311 if (found)
3312 break;
3313 else
3314 continue;
3315 }
3316
3317 /* if there is no other devices under the same iommu
3318 * owned by this domain, clear this iommu in iommu_bmp
3319 * update iommu count and coherency
3320 */
276dbf99
DW		 3321 if (iommu == device_to_iommu(info->segment, info->bus,
3322 info->devfn))
c7151a8d
WH		 3323 found = 1;
3324 }
3325
3326 if (found == 0) {
3327 unsigned long tmp_flags;
3328 spin_lock_irqsave(&domain->iommu_lock, tmp_flags);
3329 clear_bit(iommu->seq_id, &domain->iommu_bmp);
3330 domain->iommu_count--;
58c610bd 3331 domain_update_iommu_cap(domain);
c7151a8d
WH		 3332 spin_unlock_irqrestore(&domain->iommu_lock, tmp_flags);
3333 }
3334
3335 spin_unlock_irqrestore(&device_domain_lock, flags);
3336}
3337
3338static void vm_domain_remove_all_dev_info(struct dmar_domain *domain)
3339{
3340 struct device_domain_info *info;
3341 struct intel_iommu *iommu;
3342 unsigned long flags1, flags2;
3343
3344 spin_lock_irqsave(&device_domain_lock, flags1);
3345 while (!list_empty(&domain->devices)) {
3346 info = list_entry(domain->devices.next,
3347 struct device_domain_info, link);
3348 list_del(&info->link);
3349 list_del(&info->global);
3350 if (info->dev)
3351 info->dev->dev.archdata.iommu = NULL;
3352
3353 spin_unlock_irqrestore(&device_domain_lock, flags1);
3354
93a23a72 3355 iommu_disable_dev_iotlb(info);
276dbf99 3356 iommu = device_to_iommu(info->segment, info->bus, info->devfn);
c7151a8d 3357 iommu_detach_dev(iommu, info->bus, info->devfn);
3199aa6b 3358 iommu_detach_dependent_devices(iommu, info->dev);
c7151a8d
WH		 3359
3360 /* clear this iommu in iommu_bmp, update iommu count
58c610bd 3361 * and capabilities
c7151a8d
WH		 3362 */
3363 spin_lock_irqsave(&domain->iommu_lock, flags2);
3364 if (test_and_clear_bit(iommu->seq_id,
3365 &domain->iommu_bmp)) {
3366 domain->iommu_count--;
58c610bd 3367 domain_update_iommu_cap(domain);
c7151a8d
WH		 3368 }
3369 spin_unlock_irqrestore(&domain->iommu_lock, flags2);
3370
3371 free_devinfo_mem(info);
3372 spin_lock_irqsave(&device_domain_lock, flags1);
3373 }
3374 spin_unlock_irqrestore(&device_domain_lock, flags1);
3375}
3376
5e98c4b1
WH		 3377/* domain id for virtual machine, it won't be set in context */
3378static unsigned long vm_domid;
3379
fe40f1e0
WH		 3380static int vm_domain_min_agaw(struct dmar_domain *domain)
3381{
3382 int i;
3383 int min_agaw = domain->agaw;
3384
3385 i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
3386 for (; i < g_num_of_iommus; ) {
3387 if (min_agaw > g_iommus[i]->agaw)
3388 min_agaw = g_iommus[i]->agaw;
3389
3390 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
3391 }
3392
3393 return min_agaw;
3394}
3395
5e98c4b1
WH		 3396static struct dmar_domain *iommu_alloc_vm_domain(void)
3397{
3398 struct dmar_domain *domain;
3399
3400 domain = alloc_domain_mem();
3401 if (!domain)
3402 return NULL;
3403
3404 domain->id = vm_domid++;
3405 memset(&domain->iommu_bmp, 0, sizeof(unsigned long));
3406 domain->flags = DOMAIN_FLAG_VIRTUAL_MACHINE;
3407
3408 return domain;
3409}
3410
2c2e2c38 3411static int md_domain_init(struct dmar_domain *domain, int guest_width)
5e98c4b1
WH		 3412{
3413 int adjust_width;
3414
3415 init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
5e98c4b1
WH		 3416 spin_lock_init(&domain->iommu_lock);
3417
3418 domain_reserve_special_ranges(domain);
3419
3420 /* calculate AGAW */
3421 domain->gaw = guest_width;
3422 adjust_width = guestwidth_to_adjustwidth(guest_width);
3423 domain->agaw = width_to_agaw(adjust_width);
3424
3425 INIT_LIST_HEAD(&domain->devices);
3426
3427 domain->iommu_count = 0;
3428 domain->iommu_coherency = 0;
c5b15255 3429 domain->iommu_snooping = 0;
fe40f1e0 3430 domain->max_addr = 0;
5e98c4b1
WH		 3431
3432 /* always allocate the top pgd */
3433 domain->pgd = (struct dma_pte *)alloc_pgtable_page();
3434 if (!domain->pgd)
3435 return -ENOMEM;
3436 domain_flush_cache(domain, domain->pgd, PAGE_SIZE);
3437 return 0;
3438}
3439
3440static void iommu_free_vm_domain(struct dmar_domain *domain)
3441{
3442 unsigned long flags;
3443 struct dmar_drhd_unit *drhd;
3444 struct intel_iommu *iommu;
3445 unsigned long i;
3446 unsigned long ndomains;
3447
3448 for_each_drhd_unit(drhd) {
3449 if (drhd->ignored)
3450 continue;
3451 iommu = drhd->iommu;
3452
3453 ndomains = cap_ndoms(iommu->cap);
3454 i = find_first_bit(iommu->domain_ids, ndomains);
3455 for (; i < ndomains; ) {
3456 if (iommu->domains[i] == domain) {
3457 spin_lock_irqsave(&iommu->lock, flags);
3458 clear_bit(i, iommu->domain_ids);
3459 iommu->domains[i] = NULL;
3460 spin_unlock_irqrestore(&iommu->lock, flags);
3461 break;
3462 }
3463 i = find_next_bit(iommu->domain_ids, ndomains, i+1);
3464 }
3465 }
3466}
3467
3468static void vm_domain_exit(struct dmar_domain *domain)
3469{
5e98c4b1
WH		 3470 /* Domain 0 is reserved, so dont process it */
3471 if (!domain)
3472 return;
3473
3474 vm_domain_remove_all_dev_info(domain);
3475 /* destroy iovas */
3476 put_iova_domain(&domain->iovad);
5e98c4b1
WH		 3477
3478 /* clear ptes */
595badf5 3479 dma_pte_clear_range(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
5e98c4b1
WH		 3480
3481 /* free page tables */
d794dc9b 3482 dma_pte_free_pagetable(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
5e98c4b1
WH		 3483
3484 iommu_free_vm_domain(domain);
3485 free_domain_mem(domain);
3486}
3487
5d450806 3488static int intel_iommu_domain_init(struct iommu_domain *domain)
38717946 3489{
5d450806 3490 struct dmar_domain *dmar_domain;
38717946 3491
5d450806
JR		 3492 dmar_domain = iommu_alloc_vm_domain();
3493 if (!dmar_domain) {
38717946 3494 printk(KERN_ERR
5d450806
JR		 3495 "intel_iommu_domain_init: dmar_domain == NULL\n");
3496 return -ENOMEM;
38717946 3497 }
2c2e2c38 3498 if (md_domain_init(dmar_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
38717946 3499 printk(KERN_ERR
5d450806
JR		 3500 "intel_iommu_domain_init() failed\n");
3501 vm_domain_exit(dmar_domain);
3502 return -ENOMEM;
38717946 3503 }
5d450806 3504 domain->priv = dmar_domain;
faa3d6f5 3505
5d450806 3506 return 0;
38717946 3507}
38717946 3508
5d450806 3509static void intel_iommu_domain_destroy(struct iommu_domain *domain)
38717946 3510{
5d450806
JR		 3511 struct dmar_domain *dmar_domain = domain->priv;
3512
3513 domain->priv = NULL;
3514 vm_domain_exit(dmar_domain);
38717946 3515}
38717946 3516
4c5478c9
JR		 3517static int intel_iommu_attach_device(struct iommu_domain *domain,
3518 struct device *dev)
38717946 3519{
4c5478c9
JR		 3520 struct dmar_domain *dmar_domain = domain->priv;
3521 struct pci_dev *pdev = to_pci_dev(dev);
fe40f1e0
WH		 3522 struct intel_iommu *iommu;
3523 int addr_width;
3524 u64 end;
faa3d6f5
WH		 3525
3526 /* normally pdev is not mapped */
3527 if (unlikely(domain_context_mapped(pdev))) {
3528 struct dmar_domain *old_domain;
3529
3530 old_domain = find_domain(pdev);
3531 if (old_domain) {
2c2e2c38
FY		 3532 if (dmar_domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
3533 dmar_domain->flags & DOMAIN_FLAG_STATIC_IDENTITY)
3534 domain_remove_one_dev_info(old_domain, pdev);
faa3d6f5
WH		 3535 else
3536 domain_remove_dev_info(old_domain);
3537 }
3538 }
3539
276dbf99
DW		 3540 iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
3541 pdev->devfn);
fe40f1e0
WH		 3542 if (!iommu)
3543 return -ENODEV;
3544
3545 /* check if this iommu agaw is sufficient for max mapped address */
3546 addr_width = agaw_to_width(iommu->agaw);
3547 end = DOMAIN_MAX_ADDR(addr_width);
3548 end = end & VTD_PAGE_MASK;
4c5478c9 3549 if (end < dmar_domain->max_addr) {
fe40f1e0
WH		 3550 printk(KERN_ERR "%s: iommu agaw (%d) is not "
3551 "sufficient for the mapped address (%llx)\n",
4c5478c9 3552 __func__, iommu->agaw, dmar_domain->max_addr);
fe40f1e0
WH		 3553 return -EFAULT;
3554 }
3555
5fe60f4e 3556 return domain_add_dev_info(dmar_domain, pdev, CONTEXT_TT_MULTI_LEVEL);
38717946 3557}
38717946 3558
4c5478c9
JR		 3559static void intel_iommu_detach_device(struct iommu_domain *domain,
3560 struct device *dev)
38717946 3561{
4c5478c9
JR		 3562 struct dmar_domain *dmar_domain = domain->priv;
3563 struct pci_dev *pdev = to_pci_dev(dev);
3564
2c2e2c38 3565 domain_remove_one_dev_info(dmar_domain, pdev);
faa3d6f5 3566}
c7151a8d 3567
dde57a21
JR		 3568static int intel_iommu_map_range(struct iommu_domain *domain,
3569 unsigned long iova, phys_addr_t hpa,
3570 size_t size, int iommu_prot)
faa3d6f5 3571{
dde57a21 3572 struct dmar_domain *dmar_domain = domain->priv;
fe40f1e0
WH		 3573 u64 max_addr;
3574 int addr_width;
dde57a21 3575 int prot = 0;
faa3d6f5 3576 int ret;
fe40f1e0 3577
dde57a21
JR		 3578 if (iommu_prot & IOMMU_READ)
3579 prot |= DMA_PTE_READ;
3580 if (iommu_prot & IOMMU_WRITE)
3581 prot |= DMA_PTE_WRITE;
9cf06697
SY		 3582 if ((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping)
3583 prot |= DMA_PTE_SNP;
dde57a21 3584
163cc52c 3585 max_addr = iova + size;
dde57a21 3586 if (dmar_domain->max_addr < max_addr) {
fe40f1e0
WH		 3587 int min_agaw;
3588 u64 end;
3589
3590 /* check if minimum agaw is sufficient for mapped address */
dde57a21 3591 min_agaw = vm_domain_min_agaw(dmar_domain);
fe40f1e0
WH		 3592 addr_width = agaw_to_width(min_agaw);
3593 end = DOMAIN_MAX_ADDR(addr_width);
3594 end = end & VTD_PAGE_MASK;
3595 if (end < max_addr) {
3596 printk(KERN_ERR "%s: iommu agaw (%d) is not "
3597 "sufficient for the mapped address (%llx)\n",
3598 __func__, min_agaw, max_addr);
3599 return -EFAULT;
3600 }
dde57a21 3601 dmar_domain->max_addr = max_addr;
fe40f1e0 3602 }
ad051221
DW		 3603 /* Round up size to next multiple of PAGE_SIZE, if it and
3604 the low bits of hpa would take us onto the next page */
88cb6a74 3605 size = aligned_nrpages(hpa, size);
ad051221
DW		 3606 ret = domain_pfn_mapping(dmar_domain, iova >> VTD_PAGE_SHIFT,
3607 hpa >> VTD_PAGE_SHIFT, size, prot);
faa3d6f5 3608 return ret;
38717946 3609}
38717946 3610
dde57a21
JR		 3611static void intel_iommu_unmap_range(struct iommu_domain *domain,
3612 unsigned long iova, size_t size)
38717946 3613{
dde57a21 3614 struct dmar_domain *dmar_domain = domain->priv;
faa3d6f5 3615
4b99d352
SY		 3616 if (!size)
3617 return;
3618
163cc52c
DW		 3619 dma_pte_clear_range(dmar_domain, iova >> VTD_PAGE_SHIFT,
3620 (iova + size - 1) >> VTD_PAGE_SHIFT);
fe40f1e0 3621
163cc52c
DW		 3622 if (dmar_domain->max_addr == iova + size)
3623 dmar_domain->max_addr = iova;
38717946 3624}
38717946 3625
d14d6577
JR		 3626static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain,
3627 unsigned long iova)
38717946 3628{
d14d6577 3629 struct dmar_domain *dmar_domain = domain->priv;
38717946 3630 struct dma_pte *pte;
faa3d6f5 3631 u64 phys = 0;
38717946 3632
b026fd28 3633 pte = pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT);
38717946 3634 if (pte)
faa3d6f5 3635 phys = dma_pte_addr(pte);
38717946 3636
faa3d6f5 3637 return phys;
38717946 3638}
a8bcbb0d 3639
dbb9fd86
SY		 3640static int intel_iommu_domain_has_cap(struct iommu_domain *domain,
3641 unsigned long cap)
3642{
3643 struct dmar_domain *dmar_domain = domain->priv;
3644
3645 if (cap == IOMMU_CAP_CACHE_COHERENCY)
3646 return dmar_domain->iommu_snooping;
3647
3648 return 0;
3649}
3650
a8bcbb0d
JR		 3651static struct iommu_ops intel_iommu_ops = {
3652 .domain_init = intel_iommu_domain_init,
3653 .domain_destroy = intel_iommu_domain_destroy,
3654 .attach_dev = intel_iommu_attach_device,
3655 .detach_dev = intel_iommu_detach_device,
3656 .map = intel_iommu_map_range,
3657 .unmap = intel_iommu_unmap_range,
3658 .iova_to_phys = intel_iommu_iova_to_phys,
dbb9fd86 3659 .domain_has_cap = intel_iommu_domain_has_cap,
a8bcbb0d 3660};
9af88143
DW		 3661
3662static void __devinit quirk_iommu_rwbf(struct pci_dev *dev)
3663{
3664 /*
3665 * Mobile 4 Series Chipset neglects to set RWBF capability,
3666 * but needs it:
3667 */
3668 printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n");
3669 rwbf_quirk = 1;
3670}
3671
3672DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);
Linux kernel - Deliverables
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