projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
intel-iommu: iommu init error path bug fixes
[deliverable/linux.git] / drivers / pci / intel-iommu.c
CommitLineData
ba395927
KA		 1/*
2 * Copyright (c) 2006, Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
15 * Place - Suite 330, Boston, MA 02111-1307 USA.
16 *
98bcef56 17 * Copyright (C) 2006-2008 Intel Corporation
18 * Author: Ashok Raj <ashok.raj@intel.com>
19 * Author: Shaohua Li <shaohua.li@intel.com>
20 * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
5b6985ce 21 * Author: Fenghua Yu <fenghua.yu@intel.com>
ba395927
KA		 22 */
23
24#include <linux/init.h>
25#include <linux/bitmap.h>
5e0d2a6f 26#include <linux/debugfs.h>
ba395927
KA		 27#include <linux/slab.h>
28#include <linux/irq.h>
29#include <linux/interrupt.h>
ba395927
KA		 30#include <linux/spinlock.h>
31#include <linux/pci.h>
32#include <linux/dmar.h>
33#include <linux/dma-mapping.h>
34#include <linux/mempool.h>
5e0d2a6f 35#include <linux/timer.h>
38717946 36#include <linux/iova.h>
5d450806 37#include <linux/iommu.h>
38717946 38#include <linux/intel-iommu.h>
f59c7b69 39#include <linux/sysdev.h>
ba395927 40#include <asm/cacheflush.h>
46a7fa27 41#include <asm/iommu.h>
ba395927
KA		 42#include "pci.h"
43
5b6985ce
FY		 44#define ROOT_SIZE VTD_PAGE_SIZE
45#define CONTEXT_SIZE VTD_PAGE_SIZE
46
ba395927
KA		 47#define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
48#define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
49
50#define IOAPIC_RANGE_START (0xfee00000)
51#define IOAPIC_RANGE_END (0xfeefffff)
52#define IOVA_START_ADDR (0x1000)
53
54#define DEFAULT_DOMAIN_ADDRESS_WIDTH 48
55
4ed0d3e6
FY		 56#define MAX_AGAW_WIDTH 64
57
ba395927 58#define DOMAIN_MAX_ADDR(gaw) ((((u64)1) << gaw) - 1)
595badf5 59#define DOMAIN_MAX_PFN(gaw) ((((u64)1) << (gaw-VTD_PAGE_SHIFT)) - 1)
ba395927 60
f27be03b 61#define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
284901a9 62#define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32))
6a35528a 63#define DMA_64BIT_PFN IOVA_PFN(DMA_BIT_MASK(64))
5e0d2a6f 64
fd18de50 65
dd4e8319
DW		 66/* VT-d pages must always be _smaller_ than MM pages. Otherwise things
67 are never going to work. */
68static inline unsigned long dma_to_mm_pfn(unsigned long dma_pfn)
69{
70 return dma_pfn >> (PAGE_SHIFT - VTD_PAGE_SHIFT);
71}
72
73static inline unsigned long mm_to_dma_pfn(unsigned long mm_pfn)
74{
75 return mm_pfn << (PAGE_SHIFT - VTD_PAGE_SHIFT);
76}
77static inline unsigned long page_to_dma_pfn(struct page *pg)
78{
79 return mm_to_dma_pfn(page_to_pfn(pg));
80}
81static inline unsigned long virt_to_dma_pfn(void *p)
82{
83 return page_to_dma_pfn(virt_to_page(p));
84}
85
d9630fe9
WH		 86/* global iommu list, set NULL for ignored DMAR units */
87static struct intel_iommu **g_iommus;
88
9af88143
DW		 89static int rwbf_quirk;
90
46b08e1a
MM		 91/*
92 * 0: Present
93 * 1-11: Reserved
94 * 12-63: Context Ptr (12 - (haw-1))
95 * 64-127: Reserved
96 */
97struct root_entry {
98 u64 val;
99 u64 rsvd1;
100};
101#define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry))
102static inline bool root_present(struct root_entry *root)
103{
104 return (root->val & 1);
105}
106static inline void set_root_present(struct root_entry *root)
107{
108 root->val |= 1;
109}
110static inline void set_root_value(struct root_entry *root, unsigned long value)
111{
112 root->val |= value & VTD_PAGE_MASK;
113}
114
115static inline struct context_entry *
116get_context_addr_from_root(struct root_entry *root)
117{
118 return (struct context_entry *)
119 (root_present(root)?phys_to_virt(
120 root->val & VTD_PAGE_MASK) :
121 NULL);
122}
123
7a8fc25e
MM		 124/*
125 * low 64 bits:
126 * 0: present
127 * 1: fault processing disable
128 * 2-3: translation type
129 * 12-63: address space root
130 * high 64 bits:
131 * 0-2: address width
132 * 3-6: aval
133 * 8-23: domain id
134 */
135struct context_entry {
136 u64 lo;
137 u64 hi;
138};
c07e7d21
MM		 139
140static inline bool context_present(struct context_entry *context)
141{
142 return (context->lo & 1);
143}
144static inline void context_set_present(struct context_entry *context)
145{
146 context->lo |= 1;
147}
148
149static inline void context_set_fault_enable(struct context_entry *context)
150{
151 context->lo &= (((u64)-1) << 2) | 1;
152}
153
c07e7d21
MM		 154static inline void context_set_translation_type(struct context_entry *context,
155 unsigned long value)
156{
157 context->lo &= (((u64)-1) << 4) | 3;
158 context->lo |= (value & 3) << 2;
159}
160
161static inline void context_set_address_root(struct context_entry *context,
162 unsigned long value)
163{
164 context->lo |= value & VTD_PAGE_MASK;
165}
166
167static inline void context_set_address_width(struct context_entry *context,
168 unsigned long value)
169{
170 context->hi |= value & 7;
171}
172
173static inline void context_set_domain_id(struct context_entry *context,
174 unsigned long value)
175{
176 context->hi |= (value & ((1 << 16) - 1)) << 8;
177}
178
179static inline void context_clear_entry(struct context_entry *context)
180{
181 context->lo = 0;
182 context->hi = 0;
183}
7a8fc25e 184
622ba12a
MM		 185/*
186 * 0: readable
187 * 1: writable
188 * 2-6: reserved
189 * 7: super page
9cf06697
SY		 190 * 8-10: available
191 * 11: snoop behavior
622ba12a
MM		 192 * 12-63: Host physcial address
193 */
194struct dma_pte {
195 u64 val;
196};
622ba12a 197
19c239ce
MM		 198static inline void dma_clear_pte(struct dma_pte *pte)
199{
200 pte->val = 0;
201}
202
203static inline void dma_set_pte_readable(struct dma_pte *pte)
204{
205 pte->val |= DMA_PTE_READ;
206}
207
208static inline void dma_set_pte_writable(struct dma_pte *pte)
209{
210 pte->val |= DMA_PTE_WRITE;
211}
212
9cf06697
SY		 213static inline void dma_set_pte_snp(struct dma_pte *pte)
214{
215 pte->val |= DMA_PTE_SNP;
216}
217
19c239ce
MM		 218static inline void dma_set_pte_prot(struct dma_pte *pte, unsigned long prot)
219{
220 pte->val = (pte->val & ~3) | (prot & 3);
221}
222
223static inline u64 dma_pte_addr(struct dma_pte *pte)
224{
c85994e4
DW		 225#ifdef CONFIG_64BIT
226 return pte->val & VTD_PAGE_MASK;
227#else
228 /* Must have a full atomic 64-bit read */
229 return __cmpxchg64(pte, 0ULL, 0ULL) & VTD_PAGE_MASK;
230#endif
19c239ce
MM		 231}
232
dd4e8319 233static inline void dma_set_pte_pfn(struct dma_pte *pte, unsigned long pfn)
19c239ce 234{
dd4e8319 235 pte->val |= (uint64_t)pfn << VTD_PAGE_SHIFT;
19c239ce
MM		 236}
237
238static inline bool dma_pte_present(struct dma_pte *pte)
239{
240 return (pte->val & 3) != 0;
241}
622ba12a 242
75e6bf96
DW		 243static inline int first_pte_in_page(struct dma_pte *pte)
244{
245 return !((unsigned long)pte & ~VTD_PAGE_MASK);
246}
247
2c2e2c38
FY		 248/*
249 * This domain is a statically identity mapping domain.
250 * 1. This domain creats a static 1:1 mapping to all usable memory.
251 * 2. It maps to each iommu if successful.
252 * 3. Each iommu mapps to this domain if successful.
253 */
19943b0e
DW		 254static struct dmar_domain *si_domain;
255static int hw_pass_through = 1;
2c2e2c38 256
3b5410e7 257/* devices under the same p2p bridge are owned in one domain */
cdc7b837 258#define DOMAIN_FLAG_P2P_MULTIPLE_DEVICES (1 << 0)
3b5410e7 259
1ce28feb
WH		 260/* domain represents a virtual machine, more than one devices
261 * across iommus may be owned in one domain, e.g. kvm guest.
262 */
263#define DOMAIN_FLAG_VIRTUAL_MACHINE (1 << 1)
264
2c2e2c38
FY		 265/* si_domain contains mulitple devices */
266#define DOMAIN_FLAG_STATIC_IDENTITY (1 << 2)
267
99126f7c
MM		 268struct dmar_domain {
269 int id; /* domain id */
8c11e798 270 unsigned long iommu_bmp; /* bitmap of iommus this domain uses*/
99126f7c
MM		 271
272 struct list_head devices; /* all devices' list */
273 struct iova_domain iovad; /* iova's that belong to this domain */
274
275 struct dma_pte *pgd; /* virtual address */
99126f7c
MM		 276 int gaw; /* max guest address width */
277
278 /* adjusted guest address width, 0 is level 2 30-bit */
279 int agaw;
280
3b5410e7 281 int flags; /* flags to find out type of domain */
8e604097
WH		 282
283 int iommu_coherency;/* indicate coherency of iommu access */
58c610bd 284 int iommu_snooping; /* indicate snooping control feature*/
c7151a8d
WH		 285 int iommu_count; /* reference count of iommu */
286 spinlock_t iommu_lock; /* protect iommu set in domain */
fe40f1e0 287 u64 max_addr; /* maximum mapped address */
99126f7c
MM		 288};
289
a647dacb
MM		 290/* PCI domain-device relationship */
291struct device_domain_info {
292 struct list_head link; /* link to domain siblings */
293 struct list_head global; /* link to global list */
276dbf99
DW		 294 int segment; /* PCI domain */
295 u8 bus; /* PCI bus number */
a647dacb
MM		 296 u8 devfn; /* PCI devfn number */
297 struct pci_dev *dev; /* it's NULL for PCIE-to-PCI bridge */
93a23a72 298 struct intel_iommu *iommu; /* IOMMU used by this device */
a647dacb
MM		 299 struct dmar_domain *domain; /* pointer to domain */
300};
301
5e0d2a6f 302static void flush_unmaps_timeout(unsigned long data);
303
304DEFINE_TIMER(unmap_timer, flush_unmaps_timeout, 0, 0);
305
80b20dd8 306#define HIGH_WATER_MARK 250
307struct deferred_flush_tables {
308 int next;
309 struct iova *iova[HIGH_WATER_MARK];
310 struct dmar_domain *domain[HIGH_WATER_MARK];
311};
312
313static struct deferred_flush_tables *deferred_flush;
314
5e0d2a6f 315/* bitmap for indexing intel_iommus */
5e0d2a6f 316static int g_num_of_iommus;
317
318static DEFINE_SPINLOCK(async_umap_flush_lock);
319static LIST_HEAD(unmaps_to_do);
320
321static int timer_on;
322static long list_size;
5e0d2a6f 323
ba395927
KA		 324static void domain_remove_dev_info(struct dmar_domain *domain);
325
0cd5c3c8
KM		 326#ifdef CONFIG_DMAR_DEFAULT_ON
327int dmar_disabled = 0;
328#else
329int dmar_disabled = 1;
330#endif /*CONFIG_DMAR_DEFAULT_ON*/
331
ba395927 332static int __initdata dmar_map_gfx = 1;
7d3b03ce 333static int dmar_forcedac;
5e0d2a6f 334static int intel_iommu_strict;
ba395927
KA		 335
336#define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1))
337static DEFINE_SPINLOCK(device_domain_lock);
338static LIST_HEAD(device_domain_list);
339
a8bcbb0d
JR		 340static struct iommu_ops intel_iommu_ops;
341
ba395927
KA		 342static int __init intel_iommu_setup(char *str)
343{
344 if (!str)
345 return -EINVAL;
346 while (*str) {
0cd5c3c8
KM		 347 if (!strncmp(str, "on", 2)) {
348 dmar_disabled = 0;
349 printk(KERN_INFO "Intel-IOMMU: enabled\n");
350 } else if (!strncmp(str, "off", 3)) {
ba395927 351 dmar_disabled = 1;
0cd5c3c8 352 printk(KERN_INFO "Intel-IOMMU: disabled\n");
ba395927
KA		 353 } else if (!strncmp(str, "igfx_off", 8)) {
354 dmar_map_gfx = 0;
355 printk(KERN_INFO
356 "Intel-IOMMU: disable GFX device mapping\n");
7d3b03ce 357 } else if (!strncmp(str, "forcedac", 8)) {
5e0d2a6f 358 printk(KERN_INFO
7d3b03ce
KA		 359 "Intel-IOMMU: Forcing DAC for PCI devices\n");
360 dmar_forcedac = 1;
5e0d2a6f 361 } else if (!strncmp(str, "strict", 6)) {
362 printk(KERN_INFO
363 "Intel-IOMMU: disable batched IOTLB flush\n");
364 intel_iommu_strict = 1;
ba395927
KA		 365 }
366
367 str += strcspn(str, ",");
368 while (*str == ',')
369 str++;
370 }
371 return 0;
372}
373__setup("intel_iommu=", intel_iommu_setup);
374
375static struct kmem_cache *iommu_domain_cache;
376static struct kmem_cache *iommu_devinfo_cache;
377static struct kmem_cache *iommu_iova_cache;
378
eb3fa7cb
KA		 379static inline void *iommu_kmem_cache_alloc(struct kmem_cache *cachep)
380{
381 unsigned int flags;
382 void *vaddr;
383
384 /* trying to avoid low memory issues */
385 flags = current->flags & PF_MEMALLOC;
386 current->flags |= PF_MEMALLOC;
387 vaddr = kmem_cache_alloc(cachep, GFP_ATOMIC);
388 current->flags &= (~PF_MEMALLOC | flags);
389 return vaddr;
390}
391
392
ba395927
KA		 393static inline void *alloc_pgtable_page(void)
394{
eb3fa7cb
KA		 395 unsigned int flags;
396 void *vaddr;
397
398 /* trying to avoid low memory issues */
399 flags = current->flags & PF_MEMALLOC;
400 current->flags |= PF_MEMALLOC;
401 vaddr = (void *)get_zeroed_page(GFP_ATOMIC);
402 current->flags &= (~PF_MEMALLOC | flags);
403 return vaddr;
ba395927
KA		 404}
405
406static inline void free_pgtable_page(void *vaddr)
407{
408 free_page((unsigned long)vaddr);
409}
410
411static inline void *alloc_domain_mem(void)
412{
eb3fa7cb 413 return iommu_kmem_cache_alloc(iommu_domain_cache);
ba395927
KA		 414}
415
38717946 416static void free_domain_mem(void *vaddr)
ba395927
KA		 417{
418 kmem_cache_free(iommu_domain_cache, vaddr);
419}
420
421static inline void * alloc_devinfo_mem(void)
422{
eb3fa7cb 423 return iommu_kmem_cache_alloc(iommu_devinfo_cache);
ba395927
KA		 424}
425
426static inline void free_devinfo_mem(void *vaddr)
427{
428 kmem_cache_free(iommu_devinfo_cache, vaddr);
429}
430
431struct iova *alloc_iova_mem(void)
432{
eb3fa7cb 433 return iommu_kmem_cache_alloc(iommu_iova_cache);
ba395927
KA		 434}
435
436void free_iova_mem(struct iova *iova)
437{
438 kmem_cache_free(iommu_iova_cache, iova);
439}
440
1b573683
WH		 441
442static inline int width_to_agaw(int width);
443
4ed0d3e6 444static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw)
1b573683
WH		 445{
446 unsigned long sagaw;
447 int agaw = -1;
448
449 sagaw = cap_sagaw(iommu->cap);
4ed0d3e6 450 for (agaw = width_to_agaw(max_gaw);
1b573683
WH		 451 agaw >= 0; agaw--) {
452 if (test_bit(agaw, &sagaw))
453 break;
454 }
455
456 return agaw;
457}
458
4ed0d3e6
FY		 459/*
460 * Calculate max SAGAW for each iommu.
461 */
462int iommu_calculate_max_sagaw(struct intel_iommu *iommu)
463{
464 return __iommu_calculate_agaw(iommu, MAX_AGAW_WIDTH);
465}
466
467/*
468 * calculate agaw for each iommu.
469 * "SAGAW" may be different across iommus, use a default agaw, and
470 * get a supported less agaw for iommus that don't support the default agaw.
471 */
472int iommu_calculate_agaw(struct intel_iommu *iommu)
473{
474 return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH);
475}
476
2c2e2c38 477/* This functionin only returns single iommu in a domain */
8c11e798
WH		 478static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain)
479{
480 int iommu_id;
481
2c2e2c38 482 /* si_domain and vm domain should not get here. */
1ce28feb 483 BUG_ON(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE);
2c2e2c38 484 BUG_ON(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY);
1ce28feb 485
8c11e798
WH		 486 iommu_id = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
487 if (iommu_id < 0 || iommu_id >= g_num_of_iommus)
488 return NULL;
489
490 return g_iommus[iommu_id];
491}
492
8e604097
WH		 493static void domain_update_iommu_coherency(struct dmar_domain *domain)
494{
495 int i;
496
497 domain->iommu_coherency = 1;
498
499 i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
500 for (; i < g_num_of_iommus; ) {
501 if (!ecap_coherent(g_iommus[i]->ecap)) {
502 domain->iommu_coherency = 0;
503 break;
504 }
505 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
506 }
507}
508
58c610bd
SY		 509static void domain_update_iommu_snooping(struct dmar_domain *domain)
510{
511 int i;
512
513 domain->iommu_snooping = 1;
514
515 i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
516 for (; i < g_num_of_iommus; ) {
517 if (!ecap_sc_support(g_iommus[i]->ecap)) {
518 domain->iommu_snooping = 0;
519 break;
520 }
521 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
522 }
523}
524
525/* Some capabilities may be different across iommus */
526static void domain_update_iommu_cap(struct dmar_domain *domain)
527{
528 domain_update_iommu_coherency(domain);
529 domain_update_iommu_snooping(domain);
530}
531
276dbf99 532static struct intel_iommu *device_to_iommu(int segment, u8 bus, u8 devfn)
c7151a8d
WH		 533{
534 struct dmar_drhd_unit *drhd = NULL;
535 int i;
536
537 for_each_drhd_unit(drhd) {
538 if (drhd->ignored)
539 continue;
276dbf99
DW		 540 if (segment != drhd->segment)
541 continue;
c7151a8d 542
924b6231 543 for (i = 0; i < drhd->devices_cnt; i++) {
288e4877
DH		 544 if (drhd->devices[i] &&
545 drhd->devices[i]->bus->number == bus &&
c7151a8d
WH		 546 drhd->devices[i]->devfn == devfn)
547 return drhd->iommu;
4958c5dc
DW		 548 if (drhd->devices[i] &&
549 drhd->devices[i]->subordinate &&
924b6231
DW		 550 drhd->devices[i]->subordinate->number <= bus &&
551 drhd->devices[i]->subordinate->subordinate >= bus)
552 return drhd->iommu;
553 }
c7151a8d
WH		 554
555 if (drhd->include_all)
556 return drhd->iommu;
557 }
558
559 return NULL;
560}
561
5331fe6f
WH		 562static void domain_flush_cache(struct dmar_domain *domain,
563 void *addr, int size)
564{
565 if (!domain->iommu_coherency)
566 clflush_cache_range(addr, size);
567}
568
ba395927
KA		 569/* Gets context entry for a given bus and devfn */
570static struct context_entry * device_to_context_entry(struct intel_iommu *iommu,
571 u8 bus, u8 devfn)
572{
573 struct root_entry *root;
574 struct context_entry *context;
575 unsigned long phy_addr;
576 unsigned long flags;
577
578 spin_lock_irqsave(&iommu->lock, flags);
579 root = &iommu->root_entry[bus];
580 context = get_context_addr_from_root(root);
581 if (!context) {
582 context = (struct context_entry *)alloc_pgtable_page();
583 if (!context) {
584 spin_unlock_irqrestore(&iommu->lock, flags);
585 return NULL;
586 }
5b6985ce 587 __iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE);
ba395927
KA		 588 phy_addr = virt_to_phys((void *)context);
589 set_root_value(root, phy_addr);
590 set_root_present(root);
591 __iommu_flush_cache(iommu, root, sizeof(*root));
592 }
593 spin_unlock_irqrestore(&iommu->lock, flags);
594 return &context[devfn];
595}
596
597static int device_context_mapped(struct intel_iommu *iommu, u8 bus, u8 devfn)
598{
599 struct root_entry *root;
600 struct context_entry *context;
601 int ret;
602 unsigned long flags;
603
604 spin_lock_irqsave(&iommu->lock, flags);
605 root = &iommu->root_entry[bus];
606 context = get_context_addr_from_root(root);
607 if (!context) {
608 ret = 0;
609 goto out;
610 }
c07e7d21 611 ret = context_present(&context[devfn]);
ba395927
KA		 612out:
613 spin_unlock_irqrestore(&iommu->lock, flags);
614 return ret;
615}
616
617static void clear_context_table(struct intel_iommu *iommu, u8 bus, u8 devfn)
618{
619 struct root_entry *root;
620 struct context_entry *context;
621 unsigned long flags;
622
623 spin_lock_irqsave(&iommu->lock, flags);
624 root = &iommu->root_entry[bus];
625 context = get_context_addr_from_root(root);
626 if (context) {
c07e7d21 627 context_clear_entry(&context[devfn]);
ba395927
KA		 628 __iommu_flush_cache(iommu, &context[devfn], \
629 sizeof(*context));
630 }
631 spin_unlock_irqrestore(&iommu->lock, flags);
632}
633
634static void free_context_table(struct intel_iommu *iommu)
635{
636 struct root_entry *root;
637 int i;
638 unsigned long flags;
639 struct context_entry *context;
640
641 spin_lock_irqsave(&iommu->lock, flags);
642 if (!iommu->root_entry) {
643 goto out;
644 }
645 for (i = 0; i < ROOT_ENTRY_NR; i++) {
646 root = &iommu->root_entry[i];
647 context = get_context_addr_from_root(root);
648 if (context)
649 free_pgtable_page(context);
650 }
651 free_pgtable_page(iommu->root_entry);
652 iommu->root_entry = NULL;
653out:
654 spin_unlock_irqrestore(&iommu->lock, flags);
655}
656
657/* page table handling */
658#define LEVEL_STRIDE (9)
659#define LEVEL_MASK (((u64)1 << LEVEL_STRIDE) - 1)
660
661static inline int agaw_to_level(int agaw)
662{
663 return agaw + 2;
664}
665
666static inline int agaw_to_width(int agaw)
667{
668 return 30 + agaw * LEVEL_STRIDE;
669
670}
671
672static inline int width_to_agaw(int width)
673{
674 return (width - 30) / LEVEL_STRIDE;
675}
676
677static inline unsigned int level_to_offset_bits(int level)
678{
6660c63a 679 return (level - 1) * LEVEL_STRIDE;
ba395927
KA		 680}
681
77dfa56c 682static inline int pfn_level_offset(unsigned long pfn, int level)
ba395927 683{
6660c63a 684 return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK;
ba395927
KA		 685}
686
6660c63a 687static inline unsigned long level_mask(int level)
ba395927 688{
6660c63a 689 return -1UL << level_to_offset_bits(level);
ba395927
KA		 690}
691
6660c63a 692static inline unsigned long level_size(int level)
ba395927 693{
6660c63a 694 return 1UL << level_to_offset_bits(level);
ba395927
KA		 695}
696
6660c63a 697static inline unsigned long align_to_level(unsigned long pfn, int level)
ba395927 698{
6660c63a 699 return (pfn + level_size(level) - 1) & level_mask(level);
ba395927
KA		 700}
701
b026fd28
DW		 702static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain,
703 unsigned long pfn)
ba395927 704{
b026fd28 705 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
ba395927
KA		 706 struct dma_pte *parent, *pte = NULL;
707 int level = agaw_to_level(domain->agaw);
708 int offset;
ba395927
KA		 709
710 BUG_ON(!domain->pgd);
b026fd28 711 BUG_ON(addr_width < BITS_PER_LONG && pfn >> addr_width);
ba395927
KA		 712 parent = domain->pgd;
713
ba395927
KA		 714 while (level > 0) {
715 void *tmp_page;
716
b026fd28 717 offset = pfn_level_offset(pfn, level);
ba395927
KA		 718 pte = &parent[offset];
719 if (level == 1)
720 break;
721
19c239ce 722 if (!dma_pte_present(pte)) {
c85994e4
DW		 723 uint64_t pteval;
724
ba395927
KA		 725 tmp_page = alloc_pgtable_page();
726
206a73c1 727 if (!tmp_page)
ba395927 728 return NULL;
206a73c1 729
c85994e4
DW		 730 domain_flush_cache(domain, tmp_page, VTD_PAGE_SIZE);
731 pteval = (virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE;
732 if (cmpxchg64(&pte->val, 0ULL, pteval)) {
733 /* Someone else set it while we were thinking; use theirs. */
734 free_pgtable_page(tmp_page);
735 } else {
736 dma_pte_addr(pte);
737 domain_flush_cache(domain, pte, sizeof(*pte));
738 }
ba395927 739 }
19c239ce 740 parent = phys_to_virt(dma_pte_addr(pte));
ba395927
KA		 741 level--;
742 }
743
ba395927
KA		 744 return pte;
745}
746
747/* return address's pte at specific level */
90dcfb5e
DW		 748static struct dma_pte *dma_pfn_level_pte(struct dmar_domain *domain,
749 unsigned long pfn,
750 int level)
ba395927
KA		 751{
752 struct dma_pte *parent, *pte = NULL;
753 int total = agaw_to_level(domain->agaw);
754 int offset;
755
756 parent = domain->pgd;
757 while (level <= total) {
90dcfb5e 758 offset = pfn_level_offset(pfn, total);
ba395927
KA		 759 pte = &parent[offset];
760 if (level == total)
761 return pte;
762
19c239ce 763 if (!dma_pte_present(pte))
ba395927 764 break;
19c239ce 765 parent = phys_to_virt(dma_pte_addr(pte));
ba395927
KA		 766 total--;
767 }
768 return NULL;
769}
770
ba395927 771/* clear last level pte, a tlb flush should be followed */
595badf5
DW		 772static void dma_pte_clear_range(struct dmar_domain *domain,
773 unsigned long start_pfn,
774 unsigned long last_pfn)
ba395927 775{
04b18e65 776 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
310a5ab9 777 struct dma_pte *first_pte, *pte;
66eae846 778
04b18e65 779 BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
595badf5 780 BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
ba395927 781
04b18e65 782 /* we don't need lock here; nobody else touches the iova range */
595badf5 783 while (start_pfn <= last_pfn) {
310a5ab9
DW		 784 first_pte = pte = dma_pfn_level_pte(domain, start_pfn, 1);
785 if (!pte) {
786 start_pfn = align_to_level(start_pfn + 1, 2);
787 continue;
788 }
75e6bf96 789 do {
310a5ab9
DW		 790 dma_clear_pte(pte);
791 start_pfn++;
792 pte++;
75e6bf96
DW		 793 } while (start_pfn <= last_pfn && !first_pte_in_page(pte));
794
310a5ab9
DW		 795 domain_flush_cache(domain, first_pte,
796 (void *)pte - (void *)first_pte);
ba395927
KA		 797 }
798}
799
800/* free page table pages. last level pte should already be cleared */
801static void dma_pte_free_pagetable(struct dmar_domain *domain,
d794dc9b
DW		 802 unsigned long start_pfn,
803 unsigned long last_pfn)
ba395927 804{
6660c63a 805 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
f3a0a52f 806 struct dma_pte *first_pte, *pte;
ba395927
KA		 807 int total = agaw_to_level(domain->agaw);
808 int level;
6660c63a 809 unsigned long tmp;
ba395927 810
6660c63a
DW		 811 BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
812 BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
ba395927 813
f3a0a52f 814 /* We don't need lock here; nobody else touches the iova range */
ba395927
KA		 815 level = 2;
816 while (level <= total) {
6660c63a
DW		 817 tmp = align_to_level(start_pfn, level);
818
f3a0a52f 819 /* If we can't even clear one PTE at this level, we're done */
6660c63a 820 if (tmp + level_size(level) - 1 > last_pfn)
ba395927
KA		 821 return;
822
3d7b0e41 823 while (tmp + level_size(level) - 1 <= last_pfn) {
f3a0a52f
DW		 824 first_pte = pte = dma_pfn_level_pte(domain, tmp, level);
825 if (!pte) {
826 tmp = align_to_level(tmp + 1, level + 1);
827 continue;
828 }
75e6bf96 829 do {
6a43e574
DW		 830 if (dma_pte_present(pte)) {
831 free_pgtable_page(phys_to_virt(dma_pte_addr(pte)));
832 dma_clear_pte(pte);
833 }
f3a0a52f
DW		 834 pte++;
835 tmp += level_size(level);
75e6bf96
DW		 836 } while (!first_pte_in_page(pte) &&
837 tmp + level_size(level) - 1 <= last_pfn);
838
f3a0a52f
DW		 839 domain_flush_cache(domain, first_pte,
840 (void *)pte - (void *)first_pte);
841
ba395927
KA		 842 }
843 level++;
844 }
845 /* free pgd */
d794dc9b 846 if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) {
ba395927
KA		 847 free_pgtable_page(domain->pgd);
848 domain->pgd = NULL;
849 }
850}
851
852/* iommu handling */
853static int iommu_alloc_root_entry(struct intel_iommu *iommu)
854{
855 struct root_entry *root;
856 unsigned long flags;
857
858 root = (struct root_entry *)alloc_pgtable_page();
859 if (!root)
860 return -ENOMEM;
861
5b6985ce 862 __iommu_flush_cache(iommu, root, ROOT_SIZE);
ba395927
KA		 863
864 spin_lock_irqsave(&iommu->lock, flags);
865 iommu->root_entry = root;
866 spin_unlock_irqrestore(&iommu->lock, flags);
867
868 return 0;
869}
870
ba395927
KA		 871static void iommu_set_root_entry(struct intel_iommu *iommu)
872{
873 void *addr;
c416daa9 874 u32 sts;
ba395927
KA		 875 unsigned long flag;
876
877 addr = iommu->root_entry;
878
879 spin_lock_irqsave(&iommu->register_lock, flag);
880 dmar_writeq(iommu->reg + DMAR_RTADDR_REG, virt_to_phys(addr));
881
c416daa9 882 writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG);
ba395927
KA		 883
884 /* Make sure hardware complete it */
885 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 886 readl, (sts & DMA_GSTS_RTPS), sts);
ba395927
KA		 887
888 spin_unlock_irqrestore(&iommu->register_lock, flag);
889}
890
891static void iommu_flush_write_buffer(struct intel_iommu *iommu)
892{
893 u32 val;
894 unsigned long flag;
895
9af88143 896 if (!rwbf_quirk && !cap_rwbf(iommu->cap))
ba395927 897 return;
ba395927
KA		 898
899 spin_lock_irqsave(&iommu->register_lock, flag);
462b60f6 900 writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG);
ba395927
KA		 901
902 /* Make sure hardware complete it */
903 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 904 readl, (!(val & DMA_GSTS_WBFS)), val);
ba395927
KA		 905
906 spin_unlock_irqrestore(&iommu->register_lock, flag);
907}
908
909/* return value determine if we need a write buffer flush */
4c25a2c1
DW		 910static void __iommu_flush_context(struct intel_iommu *iommu,
911 u16 did, u16 source_id, u8 function_mask,
912 u64 type)
ba395927
KA		 913{
914 u64 val = 0;
915 unsigned long flag;
916
ba395927
KA		 917 switch (type) {
918 case DMA_CCMD_GLOBAL_INVL:
919 val = DMA_CCMD_GLOBAL_INVL;
920 break;
921 case DMA_CCMD_DOMAIN_INVL:
922 val = DMA_CCMD_DOMAIN_INVL|DMA_CCMD_DID(did);
923 break;
924 case DMA_CCMD_DEVICE_INVL:
925 val = DMA_CCMD_DEVICE_INVL|DMA_CCMD_DID(did)
926 | DMA_CCMD_SID(source_id) | DMA_CCMD_FM(function_mask);
927 break;
928 default:
929 BUG();
930 }
931 val |= DMA_CCMD_ICC;
932
933 spin_lock_irqsave(&iommu->register_lock, flag);
934 dmar_writeq(iommu->reg + DMAR_CCMD_REG, val);
935
936 /* Make sure hardware complete it */
937 IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG,
938 dmar_readq, (!(val & DMA_CCMD_ICC)), val);
939
940 spin_unlock_irqrestore(&iommu->register_lock, flag);
ba395927
KA		 941}
942
ba395927 943/* return value determine if we need a write buffer flush */
1f0ef2aa
DW		 944static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did,
945 u64 addr, unsigned int size_order, u64 type)
ba395927
KA		 946{
947 int tlb_offset = ecap_iotlb_offset(iommu->ecap);
948 u64 val = 0, val_iva = 0;
949 unsigned long flag;
950
ba395927
KA		 951 switch (type) {
952 case DMA_TLB_GLOBAL_FLUSH:
953 /* global flush doesn't need set IVA_REG */
954 val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT;
955 break;
956 case DMA_TLB_DSI_FLUSH:
957 val = DMA_TLB_DSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
958 break;
959 case DMA_TLB_PSI_FLUSH:
960 val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
961 /* Note: always flush non-leaf currently */
962 val_iva = size_order | addr;
963 break;
964 default:
965 BUG();
966 }
967 /* Note: set drain read/write */
968#if 0
969 /*
970 * This is probably to be super secure.. Looks like we can
971 * ignore it without any impact.
972 */
973 if (cap_read_drain(iommu->cap))
974 val |= DMA_TLB_READ_DRAIN;
975#endif
976 if (cap_write_drain(iommu->cap))
977 val |= DMA_TLB_WRITE_DRAIN;
978
979 spin_lock_irqsave(&iommu->register_lock, flag);
980 /* Note: Only uses first TLB reg currently */
981 if (val_iva)
982 dmar_writeq(iommu->reg + tlb_offset, val_iva);
983 dmar_writeq(iommu->reg + tlb_offset + 8, val);
984
985 /* Make sure hardware complete it */
986 IOMMU_WAIT_OP(iommu, tlb_offset + 8,
987 dmar_readq, (!(val & DMA_TLB_IVT)), val);
988
989 spin_unlock_irqrestore(&iommu->register_lock, flag);
990
991 /* check IOTLB invalidation granularity */
992 if (DMA_TLB_IAIG(val) == 0)
993 printk(KERN_ERR"IOMMU: flush IOTLB failed\n");
994 if (DMA_TLB_IAIG(val) != DMA_TLB_IIRG(type))
995 pr_debug("IOMMU: tlb flush request %Lx, actual %Lx\n",
5b6985ce
FY		 996 (unsigned long long)DMA_TLB_IIRG(type),
997 (unsigned long long)DMA_TLB_IAIG(val));
ba395927
KA		 998}
999
93a23a72
YZ		 1000static struct device_domain_info *iommu_support_dev_iotlb(
1001 struct dmar_domain *domain, int segment, u8 bus, u8 devfn)
1002{
1003 int found = 0;
1004 unsigned long flags;
1005 struct device_domain_info *info;
1006 struct intel_iommu *iommu = device_to_iommu(segment, bus, devfn);
1007
1008 if (!ecap_dev_iotlb_support(iommu->ecap))
1009 return NULL;
1010
1011 if (!iommu->qi)
1012 return NULL;
1013
1014 spin_lock_irqsave(&device_domain_lock, flags);
1015 list_for_each_entry(info, &domain->devices, link)
1016 if (info->bus == bus && info->devfn == devfn) {
1017 found = 1;
1018 break;
1019 }
1020 spin_unlock_irqrestore(&device_domain_lock, flags);
1021
1022 if (!found || !info->dev)
1023 return NULL;
1024
1025 if (!pci_find_ext_capability(info->dev, PCI_EXT_CAP_ID_ATS))
1026 return NULL;
1027
1028 if (!dmar_find_matched_atsr_unit(info->dev))
1029 return NULL;
1030
1031 info->iommu = iommu;
1032
1033 return info;
1034}
1035
1036static void iommu_enable_dev_iotlb(struct device_domain_info *info)
ba395927 1037{
93a23a72
YZ		 1038 if (!info)
1039 return;
1040
1041 pci_enable_ats(info->dev, VTD_PAGE_SHIFT);
1042}
1043
1044static void iommu_disable_dev_iotlb(struct device_domain_info *info)
1045{
1046 if (!info->dev || !pci_ats_enabled(info->dev))
1047 return;
1048
1049 pci_disable_ats(info->dev);
1050}
1051
1052static void iommu_flush_dev_iotlb(struct dmar_domain *domain,
1053 u64 addr, unsigned mask)
1054{
1055 u16 sid, qdep;
1056 unsigned long flags;
1057 struct device_domain_info *info;
1058
1059 spin_lock_irqsave(&device_domain_lock, flags);
1060 list_for_each_entry(info, &domain->devices, link) {
1061 if (!info->dev || !pci_ats_enabled(info->dev))
1062 continue;
1063
1064 sid = info->bus << 8 | info->devfn;
1065 qdep = pci_ats_queue_depth(info->dev);
1066 qi_flush_dev_iotlb(info->iommu, sid, qdep, addr, mask);
1067 }
1068 spin_unlock_irqrestore(&device_domain_lock, flags);
1069}
1070
1f0ef2aa 1071static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, u16 did,
03d6a246 1072 unsigned long pfn, unsigned int pages)
ba395927 1073{
9dd2fe89 1074 unsigned int mask = ilog2(__roundup_pow_of_two(pages));
03d6a246 1075 uint64_t addr = (uint64_t)pfn << VTD_PAGE_SHIFT;
ba395927 1076
ba395927
KA		 1077 BUG_ON(pages == 0);
1078
ba395927 1079 /*
9dd2fe89
YZ		 1080 * Fallback to domain selective flush if no PSI support or the size is
1081 * too big.
ba395927
KA		 1082 * PSI requires page size to be 2 ^ x, and the base address is naturally
1083 * aligned to the size
1084 */
9dd2fe89
YZ		 1085 if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap))
1086 iommu->flush.flush_iotlb(iommu, did, 0, 0,
1f0ef2aa 1087 DMA_TLB_DSI_FLUSH);
9dd2fe89
YZ		 1088 else
1089 iommu->flush.flush_iotlb(iommu, did, addr, mask,
1090 DMA_TLB_PSI_FLUSH);
bf92df30
YZ		 1091
1092 /*
1093 * In caching mode, domain ID 0 is reserved for non-present to present
1094 * mapping flush. Device IOTLB doesn't need to be flushed in this case.
1095 */
1096 if (!cap_caching_mode(iommu->cap) || did)
93a23a72 1097 iommu_flush_dev_iotlb(iommu->domains[did], addr, mask);
ba395927
KA		 1098}
1099
f8bab735 1100static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu)
1101{
1102 u32 pmen;
1103 unsigned long flags;
1104
1105 spin_lock_irqsave(&iommu->register_lock, flags);
1106 pmen = readl(iommu->reg + DMAR_PMEN_REG);
1107 pmen &= ~DMA_PMEN_EPM;
1108 writel(pmen, iommu->reg + DMAR_PMEN_REG);
1109
1110 /* wait for the protected region status bit to clear */
1111 IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG,
1112 readl, !(pmen & DMA_PMEN_PRS), pmen);
1113
1114 spin_unlock_irqrestore(&iommu->register_lock, flags);
1115}
1116
ba395927
KA		 1117static int iommu_enable_translation(struct intel_iommu *iommu)
1118{
1119 u32 sts;
1120 unsigned long flags;
1121
1122 spin_lock_irqsave(&iommu->register_lock, flags);
c416daa9
DW		 1123 iommu->gcmd |= DMA_GCMD_TE;
1124 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
ba395927
KA		 1125
1126 /* Make sure hardware complete it */
1127 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 1128 readl, (sts & DMA_GSTS_TES), sts);
ba395927 1129
ba395927
KA		 1130 spin_unlock_irqrestore(&iommu->register_lock, flags);
1131 return 0;
1132}
1133
1134static int iommu_disable_translation(struct intel_iommu *iommu)
1135{
1136 u32 sts;
1137 unsigned long flag;
1138
1139 spin_lock_irqsave(&iommu->register_lock, flag);
1140 iommu->gcmd &= ~DMA_GCMD_TE;
1141 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1142
1143 /* Make sure hardware complete it */
1144 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 1145 readl, (!(sts & DMA_GSTS_TES)), sts);
ba395927
KA		 1146
1147 spin_unlock_irqrestore(&iommu->register_lock, flag);
1148 return 0;
1149}
1150
3460a6d9 1151
ba395927
KA		 1152static int iommu_init_domains(struct intel_iommu *iommu)
1153{
1154 unsigned long ndomains;
1155 unsigned long nlongs;
1156
1157 ndomains = cap_ndoms(iommu->cap);
1158 pr_debug("Number of Domains supportd <%ld>\n", ndomains);
1159 nlongs = BITS_TO_LONGS(ndomains);
1160
94a91b50
DD		 1161 spin_lock_init(&iommu->lock);
1162
ba395927
KA		 1163 /* TBD: there might be 64K domains,
1164 * consider other allocation for future chip
1165 */
1166 iommu->domain_ids = kcalloc(nlongs, sizeof(unsigned long), GFP_KERNEL);
1167 if (!iommu->domain_ids) {
1168 printk(KERN_ERR "Allocating domain id array failed\n");
1169 return -ENOMEM;
1170 }
1171 iommu->domains = kcalloc(ndomains, sizeof(struct dmar_domain *),
1172 GFP_KERNEL);
1173 if (!iommu->domains) {
1174 printk(KERN_ERR "Allocating domain array failed\n");
ba395927
KA		 1175 return -ENOMEM;
1176 }
1177
1178 /*
1179 * if Caching mode is set, then invalid translations are tagged
1180 * with domainid 0. Hence we need to pre-allocate it.
1181 */
1182 if (cap_caching_mode(iommu->cap))
1183 set_bit(0, iommu->domain_ids);
1184 return 0;
1185}
ba395927 1186
ba395927
KA		 1187
1188static void domain_exit(struct dmar_domain *domain);
5e98c4b1 1189static void vm_domain_exit(struct dmar_domain *domain);
e61d98d8
SS		 1190
1191void free_dmar_iommu(struct intel_iommu *iommu)
ba395927
KA		 1192{
1193 struct dmar_domain *domain;
1194 int i;
c7151a8d 1195 unsigned long flags;
ba395927 1196
94a91b50
DD		 1197 if ((iommu->domains) && (iommu->domain_ids)) {
1198 i = find_first_bit(iommu->domain_ids, cap_ndoms(iommu->cap));
1199 for (; i < cap_ndoms(iommu->cap); ) {
1200 domain = iommu->domains[i];
1201 clear_bit(i, iommu->domain_ids);
1202
1203 spin_lock_irqsave(&domain->iommu_lock, flags);
1204 if (--domain->iommu_count == 0) {
1205 if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE)
1206 vm_domain_exit(domain);
1207 else
1208 domain_exit(domain);
1209 }
1210 spin_unlock_irqrestore(&domain->iommu_lock, flags);
c7151a8d 1211
94a91b50
DD		 1212 i = find_next_bit(iommu->domain_ids,
1213 cap_ndoms(iommu->cap), i+1);
1214 }
ba395927
KA		 1215 }
1216
1217 if (iommu->gcmd & DMA_GCMD_TE)
1218 iommu_disable_translation(iommu);
1219
1220 if (iommu->irq) {
1221 set_irq_data(iommu->irq, NULL);
1222 /* This will mask the irq */
1223 free_irq(iommu->irq, iommu);
1224 destroy_irq(iommu->irq);
1225 }
1226
1227 kfree(iommu->domains);
1228 kfree(iommu->domain_ids);
1229
d9630fe9
WH		 1230 g_iommus[iommu->seq_id] = NULL;
1231
1232 /* if all iommus are freed, free g_iommus */
1233 for (i = 0; i < g_num_of_iommus; i++) {
1234 if (g_iommus[i])
1235 break;
1236 }
1237
1238 if (i == g_num_of_iommus)
1239 kfree(g_iommus);
1240
ba395927
KA		 1241 /* free context mapping */
1242 free_context_table(iommu);
ba395927
KA		 1243}
1244
2c2e2c38 1245static struct dmar_domain *alloc_domain(void)
ba395927 1246{
ba395927 1247 struct dmar_domain *domain;
ba395927
KA		 1248
1249 domain = alloc_domain_mem();
1250 if (!domain)
1251 return NULL;
1252
2c2e2c38
FY		 1253 memset(&domain->iommu_bmp, 0, sizeof(unsigned long));
1254 domain->flags = 0;
1255
1256 return domain;
1257}
1258
1259static int iommu_attach_domain(struct dmar_domain *domain,
1260 struct intel_iommu *iommu)
1261{
1262 int num;
1263 unsigned long ndomains;
1264 unsigned long flags;
1265
ba395927
KA		 1266 ndomains = cap_ndoms(iommu->cap);
1267
1268 spin_lock_irqsave(&iommu->lock, flags);
2c2e2c38 1269
ba395927
KA		 1270 num = find_first_zero_bit(iommu->domain_ids, ndomains);
1271 if (num >= ndomains) {
1272 spin_unlock_irqrestore(&iommu->lock, flags);
ba395927 1273 printk(KERN_ERR "IOMMU: no free domain ids\n");
2c2e2c38 1274 return -ENOMEM;
ba395927
KA		 1275 }
1276
ba395927 1277 domain->id = num;
2c2e2c38 1278 set_bit(num, iommu->domain_ids);
8c11e798 1279 set_bit(iommu->seq_id, &domain->iommu_bmp);
ba395927
KA		 1280 iommu->domains[num] = domain;
1281 spin_unlock_irqrestore(&iommu->lock, flags);
1282
2c2e2c38 1283 return 0;
ba395927
KA		 1284}
1285
2c2e2c38
FY		 1286static void iommu_detach_domain(struct dmar_domain *domain,
1287 struct intel_iommu *iommu)
ba395927
KA		 1288{
1289 unsigned long flags;
2c2e2c38
FY		 1290 int num, ndomains;
1291 int found = 0;
ba395927 1292
8c11e798 1293 spin_lock_irqsave(&iommu->lock, flags);
2c2e2c38
FY		 1294 ndomains = cap_ndoms(iommu->cap);
1295 num = find_first_bit(iommu->domain_ids, ndomains);
1296 for (; num < ndomains; ) {
1297 if (iommu->domains[num] == domain) {
1298 found = 1;
1299 break;
1300 }
1301 num = find_next_bit(iommu->domain_ids,
1302 cap_ndoms(iommu->cap), num+1);
1303 }
1304
1305 if (found) {
1306 clear_bit(num, iommu->domain_ids);
1307 clear_bit(iommu->seq_id, &domain->iommu_bmp);
1308 iommu->domains[num] = NULL;
1309 }
8c11e798 1310 spin_unlock_irqrestore(&iommu->lock, flags);
ba395927
KA		 1311}
1312
1313static struct iova_domain reserved_iova_list;
8a443df4 1314static struct lock_class_key reserved_rbtree_key;
ba395927
KA		 1315
1316static void dmar_init_reserved_ranges(void)
1317{
1318 struct pci_dev *pdev = NULL;
1319 struct iova *iova;
1320 int i;
ba395927 1321
f661197e 1322 init_iova_domain(&reserved_iova_list, DMA_32BIT_PFN);
ba395927 1323
8a443df4
MG		 1324 lockdep_set_class(&reserved_iova_list.iova_rbtree_lock,
1325 &reserved_rbtree_key);
1326
ba395927
KA		 1327 /* IOAPIC ranges shouldn't be accessed by DMA */
1328 iova = reserve_iova(&reserved_iova_list, IOVA_PFN(IOAPIC_RANGE_START),
1329 IOVA_PFN(IOAPIC_RANGE_END));
1330 if (!iova)
1331 printk(KERN_ERR "Reserve IOAPIC range failed\n");
1332
1333 /* Reserve all PCI MMIO to avoid peer-to-peer access */
1334 for_each_pci_dev(pdev) {
1335 struct resource *r;
1336
1337 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1338 r = &pdev->resource[i];
1339 if (!r->flags || !(r->flags & IORESOURCE_MEM))
1340 continue;
1a4a4551
DW		 1341 iova = reserve_iova(&reserved_iova_list,
1342 IOVA_PFN(r->start),
1343 IOVA_PFN(r->end));
ba395927
KA		 1344 if (!iova)
1345 printk(KERN_ERR "Reserve iova failed\n");
1346 }
1347 }
1348
1349}
1350
1351static void domain_reserve_special_ranges(struct dmar_domain *domain)
1352{
1353 copy_reserved_iova(&reserved_iova_list, &domain->iovad);
1354}
1355
1356static inline int guestwidth_to_adjustwidth(int gaw)
1357{
1358 int agaw;
1359 int r = (gaw - 12) % 9;
1360
1361 if (r == 0)
1362 agaw = gaw;
1363 else
1364 agaw = gaw + 9 - r;
1365 if (agaw > 64)
1366 agaw = 64;
1367 return agaw;
1368}
1369
1370static int domain_init(struct dmar_domain *domain, int guest_width)
1371{
1372 struct intel_iommu *iommu;
1373 int adjust_width, agaw;
1374 unsigned long sagaw;
1375
f661197e 1376 init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
c7151a8d 1377 spin_lock_init(&domain->iommu_lock);
ba395927
KA		 1378
1379 domain_reserve_special_ranges(domain);
1380
1381 /* calculate AGAW */
8c11e798 1382 iommu = domain_get_iommu(domain);
ba395927
KA		 1383 if (guest_width > cap_mgaw(iommu->cap))
1384 guest_width = cap_mgaw(iommu->cap);
1385 domain->gaw = guest_width;
1386 adjust_width = guestwidth_to_adjustwidth(guest_width);
1387 agaw = width_to_agaw(adjust_width);
1388 sagaw = cap_sagaw(iommu->cap);
1389 if (!test_bit(agaw, &sagaw)) {
1390 /* hardware doesn't support it, choose a bigger one */
1391 pr_debug("IOMMU: hardware doesn't support agaw %d\n", agaw);
1392 agaw = find_next_bit(&sagaw, 5, agaw);
1393 if (agaw >= 5)
1394 return -ENODEV;
1395 }
1396 domain->agaw = agaw;
1397 INIT_LIST_HEAD(&domain->devices);
1398
8e604097
WH		 1399 if (ecap_coherent(iommu->ecap))
1400 domain->iommu_coherency = 1;
1401 else
1402 domain->iommu_coherency = 0;
1403
58c610bd
SY		 1404 if (ecap_sc_support(iommu->ecap))
1405 domain->iommu_snooping = 1;
1406 else
1407 domain->iommu_snooping = 0;
1408
c7151a8d
WH		 1409 domain->iommu_count = 1;
1410
ba395927
KA		 1411 /* always allocate the top pgd */
1412 domain->pgd = (struct dma_pte *)alloc_pgtable_page();
1413 if (!domain->pgd)
1414 return -ENOMEM;
5b6985ce 1415 __iommu_flush_cache(iommu, domain->pgd, PAGE_SIZE);
ba395927
KA		 1416 return 0;
1417}
1418
1419static void domain_exit(struct dmar_domain *domain)
1420{
2c2e2c38
FY		 1421 struct dmar_drhd_unit *drhd;
1422 struct intel_iommu *iommu;
ba395927
KA		 1423
1424 /* Domain 0 is reserved, so dont process it */
1425 if (!domain)
1426 return;
1427
1428 domain_remove_dev_info(domain);
1429 /* destroy iovas */
1430 put_iova_domain(&domain->iovad);
ba395927
KA		 1431
1432 /* clear ptes */
595badf5 1433 dma_pte_clear_range(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
ba395927
KA		 1434
1435 /* free page tables */
d794dc9b 1436 dma_pte_free_pagetable(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
ba395927 1437
2c2e2c38
FY		 1438 for_each_active_iommu(iommu, drhd)
1439 if (test_bit(iommu->seq_id, &domain->iommu_bmp))
1440 iommu_detach_domain(domain, iommu);
1441
ba395927
KA		 1442 free_domain_mem(domain);
1443}
1444
4ed0d3e6
FY		 1445static int domain_context_mapping_one(struct dmar_domain *domain, int segment,
1446 u8 bus, u8 devfn, int translation)
ba395927
KA		 1447{
1448 struct context_entry *context;
ba395927 1449 unsigned long flags;
5331fe6f 1450 struct intel_iommu *iommu;
ea6606b0
WH		 1451 struct dma_pte *pgd;
1452 unsigned long num;
1453 unsigned long ndomains;
1454 int id;
1455 int agaw;
93a23a72 1456 struct device_domain_info *info = NULL;
ba395927
KA		 1457
1458 pr_debug("Set context mapping for %02x:%02x.%d\n",
1459 bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
4ed0d3e6 1460
ba395927 1461 BUG_ON(!domain->pgd);
4ed0d3e6
FY		 1462 BUG_ON(translation != CONTEXT_TT_PASS_THROUGH &&
1463 translation != CONTEXT_TT_MULTI_LEVEL);
5331fe6f 1464
276dbf99 1465 iommu = device_to_iommu(segment, bus, devfn);
5331fe6f
WH		 1466 if (!iommu)
1467 return -ENODEV;
1468
ba395927
KA		 1469 context = device_to_context_entry(iommu, bus, devfn);
1470 if (!context)
1471 return -ENOMEM;
1472 spin_lock_irqsave(&iommu->lock, flags);
c07e7d21 1473 if (context_present(context)) {
ba395927
KA		 1474 spin_unlock_irqrestore(&iommu->lock, flags);
1475 return 0;
1476 }
1477
ea6606b0
WH		 1478 id = domain->id;
1479 pgd = domain->pgd;
1480
2c2e2c38
FY		 1481 if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
1482 domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) {
ea6606b0
WH		 1483 int found = 0;
1484
1485 /* find an available domain id for this device in iommu */
1486 ndomains = cap_ndoms(iommu->cap);
1487 num = find_first_bit(iommu->domain_ids, ndomains);
1488 for (; num < ndomains; ) {
1489 if (iommu->domains[num] == domain) {
1490 id = num;
1491 found = 1;
1492 break;
1493 }
1494 num = find_next_bit(iommu->domain_ids,
1495 cap_ndoms(iommu->cap), num+1);
1496 }
1497
1498 if (found == 0) {
1499 num = find_first_zero_bit(iommu->domain_ids, ndomains);
1500 if (num >= ndomains) {
1501 spin_unlock_irqrestore(&iommu->lock, flags);
1502 printk(KERN_ERR "IOMMU: no free domain ids\n");
1503 return -EFAULT;
1504 }
1505
1506 set_bit(num, iommu->domain_ids);
1507 iommu->domains[num] = domain;
1508 id = num;
1509 }
1510
1511 /* Skip top levels of page tables for
1512 * iommu which has less agaw than default.
1513 */
1514 for (agaw = domain->agaw; agaw != iommu->agaw; agaw--) {
1515 pgd = phys_to_virt(dma_pte_addr(pgd));
1516 if (!dma_pte_present(pgd)) {
1517 spin_unlock_irqrestore(&iommu->lock, flags);
1518 return -ENOMEM;
1519 }
1520 }
1521 }
1522
1523 context_set_domain_id(context, id);
4ed0d3e6 1524
93a23a72
YZ		 1525 if (translation != CONTEXT_TT_PASS_THROUGH) {
1526 info = iommu_support_dev_iotlb(domain, segment, bus, devfn);
1527 translation = info ? CONTEXT_TT_DEV_IOTLB :
1528 CONTEXT_TT_MULTI_LEVEL;
1529 }
4ed0d3e6
FY		 1530 /*
1531 * In pass through mode, AW must be programmed to indicate the largest
1532 * AGAW value supported by hardware. And ASR is ignored by hardware.
1533 */
93a23a72 1534 if (unlikely(translation == CONTEXT_TT_PASS_THROUGH))
4ed0d3e6 1535 context_set_address_width(context, iommu->msagaw);
93a23a72
YZ		 1536 else {
1537 context_set_address_root(context, virt_to_phys(pgd));
1538 context_set_address_width(context, iommu->agaw);
1539 }
4ed0d3e6
FY		 1540
1541 context_set_translation_type(context, translation);
c07e7d21
MM		 1542 context_set_fault_enable(context);
1543 context_set_present(context);
5331fe6f 1544 domain_flush_cache(domain, context, sizeof(*context));
ba395927 1545
4c25a2c1
DW		 1546 /*
1547 * It's a non-present to present mapping. If hardware doesn't cache
1548 * non-present entry we only need to flush the write-buffer. If the
1549 * _does_ cache non-present entries, then it does so in the special
1550 * domain #0, which we have to flush:
1551 */
1552 if (cap_caching_mode(iommu->cap)) {
1553 iommu->flush.flush_context(iommu, 0,
1554 (((u16)bus) << 8) | devfn,
1555 DMA_CCMD_MASK_NOBIT,
1556 DMA_CCMD_DEVICE_INVL);
1f0ef2aa 1557 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_DSI_FLUSH);
4c25a2c1 1558 } else {
ba395927 1559 iommu_flush_write_buffer(iommu);
4c25a2c1 1560 }
93a23a72 1561 iommu_enable_dev_iotlb(info);
ba395927 1562 spin_unlock_irqrestore(&iommu->lock, flags);
c7151a8d
WH		 1563
1564 spin_lock_irqsave(&domain->iommu_lock, flags);
1565 if (!test_and_set_bit(iommu->seq_id, &domain->iommu_bmp)) {
1566 domain->iommu_count++;
58c610bd 1567 domain_update_iommu_cap(domain);
c7151a8d
WH		 1568 }
1569 spin_unlock_irqrestore(&domain->iommu_lock, flags);
ba395927
KA		 1570 return 0;
1571}
1572
1573static int
4ed0d3e6
FY		 1574domain_context_mapping(struct dmar_domain *domain, struct pci_dev *pdev,
1575 int translation)
ba395927
KA		 1576{
1577 int ret;
1578 struct pci_dev *tmp, *parent;
1579
276dbf99 1580 ret = domain_context_mapping_one(domain, pci_domain_nr(pdev->bus),
4ed0d3e6
FY		 1581 pdev->bus->number, pdev->devfn,
1582 translation);
ba395927
KA		 1583 if (ret)
1584 return ret;
1585
1586 /* dependent device mapping */
1587 tmp = pci_find_upstream_pcie_bridge(pdev);
1588 if (!tmp)
1589 return 0;
1590 /* Secondary interface's bus number and devfn 0 */
1591 parent = pdev->bus->self;
1592 while (parent != tmp) {
276dbf99
DW		 1593 ret = domain_context_mapping_one(domain,
1594 pci_domain_nr(parent->bus),
1595 parent->bus->number,
4ed0d3e6 1596 parent->devfn, translation);
ba395927
KA		 1597 if (ret)
1598 return ret;
1599 parent = parent->bus->self;
1600 }
1601 if (tmp->is_pcie) /* this is a PCIE-to-PCI bridge */
1602 return domain_context_mapping_one(domain,
276dbf99 1603 pci_domain_nr(tmp->subordinate),
4ed0d3e6
FY		 1604 tmp->subordinate->number, 0,
1605 translation);
ba395927
KA		 1606 else /* this is a legacy PCI bridge */
1607 return domain_context_mapping_one(domain,
276dbf99
DW		 1608 pci_domain_nr(tmp->bus),
1609 tmp->bus->number,
4ed0d3e6
FY		 1610 tmp->devfn,
1611 translation);
ba395927
KA		 1612}
1613
5331fe6f 1614static int domain_context_mapped(struct pci_dev *pdev)
ba395927
KA		 1615{
1616 int ret;
1617 struct pci_dev *tmp, *parent;
5331fe6f
WH		 1618 struct intel_iommu *iommu;
1619
276dbf99
DW		 1620 iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
1621 pdev->devfn);
5331fe6f
WH		 1622 if (!iommu)
1623 return -ENODEV;
ba395927 1624
276dbf99 1625 ret = device_context_mapped(iommu, pdev->bus->number, pdev->devfn);
ba395927
KA		 1626 if (!ret)
1627 return ret;
1628 /* dependent device mapping */
1629 tmp = pci_find_upstream_pcie_bridge(pdev);
1630 if (!tmp)
1631 return ret;
1632 /* Secondary interface's bus number and devfn 0 */
1633 parent = pdev->bus->self;
1634 while (parent != tmp) {
8c11e798 1635 ret = device_context_mapped(iommu, parent->bus->number,
276dbf99 1636 parent->devfn);
ba395927
KA		 1637 if (!ret)
1638 return ret;
1639 parent = parent->bus->self;
1640 }
1641 if (tmp->is_pcie)
276dbf99
DW		 1642 return device_context_mapped(iommu, tmp->subordinate->number,
1643 0);
ba395927 1644 else
276dbf99
DW		 1645 return device_context_mapped(iommu, tmp->bus->number,
1646 tmp->devfn);
ba395927
KA		 1647}
1648
f532959b
FY		 1649/* Returns a number of VTD pages, but aligned to MM page size */
1650static inline unsigned long aligned_nrpages(unsigned long host_addr,
1651 size_t size)
1652{
1653 host_addr &= ~PAGE_MASK;
1654 return PAGE_ALIGN(host_addr + size) >> VTD_PAGE_SHIFT;
1655}
1656
9051aa02
DW		 1657static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1658 struct scatterlist *sg, unsigned long phys_pfn,
1659 unsigned long nr_pages, int prot)
e1605495
DW		 1660{
1661 struct dma_pte *first_pte = NULL, *pte = NULL;
9051aa02 1662 phys_addr_t uninitialized_var(pteval);
e1605495 1663 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
9051aa02 1664 unsigned long sg_res;
e1605495
DW		 1665
1666 BUG_ON(addr_width < BITS_PER_LONG && (iov_pfn + nr_pages - 1) >> addr_width);
1667
1668 if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0)
1669 return -EINVAL;
1670
1671 prot &= DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP;
1672
9051aa02
DW		 1673 if (sg)
1674 sg_res = 0;
1675 else {
1676 sg_res = nr_pages + 1;
1677 pteval = ((phys_addr_t)phys_pfn << VTD_PAGE_SHIFT) | prot;
1678 }
1679
e1605495 1680 while (nr_pages--) {
c85994e4
DW		 1681 uint64_t tmp;
1682
e1605495 1683 if (!sg_res) {
f532959b 1684 sg_res = aligned_nrpages(sg->offset, sg->length);
e1605495
DW		 1685 sg->dma_address = ((dma_addr_t)iov_pfn << VTD_PAGE_SHIFT) + sg->offset;
1686 sg->dma_length = sg->length;
1687 pteval = page_to_phys(sg_page(sg)) | prot;
1688 }
1689 if (!pte) {
1690 first_pte = pte = pfn_to_dma_pte(domain, iov_pfn);
1691 if (!pte)
1692 return -ENOMEM;
1693 }
1694 /* We don't need lock here, nobody else
1695 * touches the iova range
1696 */
7766a3fb 1697 tmp = cmpxchg64_local(&pte->val, 0ULL, pteval);
c85994e4 1698 if (tmp) {
1bf20f0d 1699 static int dumps = 5;
c85994e4
DW		 1700 printk(KERN_CRIT "ERROR: DMA PTE for vPFN 0x%lx already set (to %llx not %llx)\n",
1701 iov_pfn, tmp, (unsigned long long)pteval);
1bf20f0d
DW		 1702 if (dumps) {
1703 dumps--;
1704 debug_dma_dump_mappings(NULL);
1705 }
1706 WARN_ON(1);
1707 }
e1605495 1708 pte++;
75e6bf96 1709 if (!nr_pages || first_pte_in_page(pte)) {
e1605495
DW		 1710 domain_flush_cache(domain, first_pte,
1711 (void *)pte - (void *)first_pte);
1712 pte = NULL;
1713 }
1714 iov_pfn++;
1715 pteval += VTD_PAGE_SIZE;
1716 sg_res--;
1717 if (!sg_res)
1718 sg = sg_next(sg);
1719 }
1720 return 0;
1721}
1722
9051aa02
DW		 1723static inline int domain_sg_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1724 struct scatterlist *sg, unsigned long nr_pages,
1725 int prot)
ba395927 1726{
9051aa02
DW		 1727 return __domain_mapping(domain, iov_pfn, sg, 0, nr_pages, prot);
1728}
6f6a00e4 1729
9051aa02
DW		 1730static inline int domain_pfn_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1731 unsigned long phys_pfn, unsigned long nr_pages,
1732 int prot)
1733{
1734 return __domain_mapping(domain, iov_pfn, NULL, phys_pfn, nr_pages, prot);
ba395927
KA		 1735}
1736
c7151a8d 1737static void iommu_detach_dev(struct intel_iommu *iommu, u8 bus, u8 devfn)
ba395927 1738{
c7151a8d
WH		 1739 if (!iommu)
1740 return;
8c11e798
WH		 1741
1742 clear_context_table(iommu, bus, devfn);
1743 iommu->flush.flush_context(iommu, 0, 0, 0,
4c25a2c1 1744 DMA_CCMD_GLOBAL_INVL);
1f0ef2aa 1745 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
ba395927
KA		 1746}
1747
1748static void domain_remove_dev_info(struct dmar_domain *domain)
1749{
1750 struct device_domain_info *info;
1751 unsigned long flags;
c7151a8d 1752 struct intel_iommu *iommu;
ba395927
KA		 1753
1754 spin_lock_irqsave(&device_domain_lock, flags);
1755 while (!list_empty(&domain->devices)) {
1756 info = list_entry(domain->devices.next,
1757 struct device_domain_info, link);
1758 list_del(&info->link);
1759 list_del(&info->global);
1760 if (info->dev)
358dd8ac 1761 info->dev->dev.archdata.iommu = NULL;
ba395927
KA		 1762 spin_unlock_irqrestore(&device_domain_lock, flags);
1763
93a23a72 1764 iommu_disable_dev_iotlb(info);
276dbf99 1765 iommu = device_to_iommu(info->segment, info->bus, info->devfn);
c7151a8d 1766 iommu_detach_dev(iommu, info->bus, info->devfn);
ba395927
KA		 1767 free_devinfo_mem(info);
1768
1769 spin_lock_irqsave(&device_domain_lock, flags);
1770 }
1771 spin_unlock_irqrestore(&device_domain_lock, flags);
1772}
1773
1774/*
1775 * find_domain
358dd8ac 1776 * Note: we use struct pci_dev->dev.archdata.iommu stores the info
ba395927 1777 */
38717946 1778static struct dmar_domain *
ba395927
KA		 1779find_domain(struct pci_dev *pdev)
1780{
1781 struct device_domain_info *info;
1782
1783 /* No lock here, assumes no domain exit in normal case */
358dd8ac 1784 info = pdev->dev.archdata.iommu;
ba395927
KA		 1785 if (info)
1786 return info->domain;
1787 return NULL;
1788}
1789
ba395927
KA		 1790/* domain is initialized */
1791static struct dmar_domain *get_domain_for_dev(struct pci_dev *pdev, int gaw)
1792{
1793 struct dmar_domain *domain, *found = NULL;
1794 struct intel_iommu *iommu;
1795 struct dmar_drhd_unit *drhd;
1796 struct device_domain_info *info, *tmp;
1797 struct pci_dev *dev_tmp;
1798 unsigned long flags;
1799 int bus = 0, devfn = 0;
276dbf99 1800 int segment;
2c2e2c38 1801 int ret;
ba395927
KA		 1802
1803 domain = find_domain(pdev);
1804 if (domain)
1805 return domain;
1806
276dbf99
DW		 1807 segment = pci_domain_nr(pdev->bus);
1808
ba395927
KA		 1809 dev_tmp = pci_find_upstream_pcie_bridge(pdev);
1810 if (dev_tmp) {
1811 if (dev_tmp->is_pcie) {
1812 bus = dev_tmp->subordinate->number;
1813 devfn = 0;
1814 } else {
1815 bus = dev_tmp->bus->number;
1816 devfn = dev_tmp->devfn;
1817 }
1818 spin_lock_irqsave(&device_domain_lock, flags);
1819 list_for_each_entry(info, &device_domain_list, global) {
276dbf99
DW		 1820 if (info->segment == segment &&
1821 info->bus == bus && info->devfn == devfn) {
ba395927
KA		 1822 found = info->domain;
1823 break;
1824 }
1825 }
1826 spin_unlock_irqrestore(&device_domain_lock, flags);
1827 /* pcie-pci bridge already has a domain, uses it */
1828 if (found) {
1829 domain = found;
1830 goto found_domain;
1831 }
1832 }
1833
2c2e2c38
FY		 1834 domain = alloc_domain();
1835 if (!domain)
1836 goto error;
1837
ba395927
KA		 1838 /* Allocate new domain for the device */
1839 drhd = dmar_find_matched_drhd_unit(pdev);
1840 if (!drhd) {
1841 printk(KERN_ERR "IOMMU: can't find DMAR for device %s\n",
1842 pci_name(pdev));
1843 return NULL;
1844 }
1845 iommu = drhd->iommu;
1846
2c2e2c38
FY		 1847 ret = iommu_attach_domain(domain, iommu);
1848 if (ret) {
1849 domain_exit(domain);
ba395927 1850 goto error;
2c2e2c38 1851 }
ba395927
KA		 1852
1853 if (domain_init(domain, gaw)) {
1854 domain_exit(domain);
1855 goto error;
1856 }
1857
1858 /* register pcie-to-pci device */
1859 if (dev_tmp) {
1860 info = alloc_devinfo_mem();
1861 if (!info) {
1862 domain_exit(domain);
1863 goto error;
1864 }
276dbf99 1865 info->segment = segment;
ba395927
KA		 1866 info->bus = bus;
1867 info->devfn = devfn;
1868 info->dev = NULL;
1869 info->domain = domain;
1870 /* This domain is shared by devices under p2p bridge */
3b5410e7 1871 domain->flags |= DOMAIN_FLAG_P2P_MULTIPLE_DEVICES;
ba395927
KA		 1872
1873 /* pcie-to-pci bridge already has a domain, uses it */
1874 found = NULL;
1875 spin_lock_irqsave(&device_domain_lock, flags);
1876 list_for_each_entry(tmp, &device_domain_list, global) {
276dbf99
DW		 1877 if (tmp->segment == segment &&
1878 tmp->bus == bus && tmp->devfn == devfn) {
ba395927
KA		 1879 found = tmp->domain;
1880 break;
1881 }
1882 }
1883 if (found) {
1884 free_devinfo_mem(info);
1885 domain_exit(domain);
1886 domain = found;
1887 } else {
1888 list_add(&info->link, &domain->devices);
1889 list_add(&info->global, &device_domain_list);
1890 }
1891 spin_unlock_irqrestore(&device_domain_lock, flags);
1892 }
1893
1894found_domain:
1895 info = alloc_devinfo_mem();
1896 if (!info)
1897 goto error;
276dbf99 1898 info->segment = segment;
ba395927
KA		 1899 info->bus = pdev->bus->number;
1900 info->devfn = pdev->devfn;
1901 info->dev = pdev;
1902 info->domain = domain;
1903 spin_lock_irqsave(&device_domain_lock, flags);
1904 /* somebody is fast */
1905 found = find_domain(pdev);
1906 if (found != NULL) {
1907 spin_unlock_irqrestore(&device_domain_lock, flags);
1908 if (found != domain) {
1909 domain_exit(domain);
1910 domain = found;
1911 }
1912 free_devinfo_mem(info);
1913 return domain;
1914 }
1915 list_add(&info->link, &domain->devices);
1916 list_add(&info->global, &device_domain_list);
358dd8ac 1917 pdev->dev.archdata.iommu = info;
ba395927
KA		 1918 spin_unlock_irqrestore(&device_domain_lock, flags);
1919 return domain;
1920error:
1921 /* recheck it here, maybe others set it */
1922 return find_domain(pdev);
1923}
1924
2c2e2c38
FY		 1925static int iommu_identity_mapping;
1926
b213203e
DW		 1927static int iommu_domain_identity_map(struct dmar_domain *domain,
1928 unsigned long long start,
1929 unsigned long long end)
ba395927 1930{
c5395d5c
DW		 1931 unsigned long first_vpfn = start >> VTD_PAGE_SHIFT;
1932 unsigned long last_vpfn = end >> VTD_PAGE_SHIFT;
1933
1934 if (!reserve_iova(&domain->iovad, dma_to_mm_pfn(first_vpfn),
1935 dma_to_mm_pfn(last_vpfn))) {
ba395927 1936 printk(KERN_ERR "IOMMU: reserve iova failed\n");
b213203e 1937 return -ENOMEM;
ba395927
KA		 1938 }
1939
c5395d5c
DW		 1940 pr_debug("Mapping reserved region %llx-%llx for domain %d\n",
1941 start, end, domain->id);
ba395927
KA		 1942 /*
1943 * RMRR range might have overlap with physical memory range,
1944 * clear it first
1945 */
c5395d5c 1946 dma_pte_clear_range(domain, first_vpfn, last_vpfn);
ba395927 1947
c5395d5c
DW		 1948 return domain_pfn_mapping(domain, first_vpfn, first_vpfn,
1949 last_vpfn - first_vpfn + 1,
61df7443 1950 DMA_PTE_READ|DMA_PTE_WRITE);
b213203e
DW		 1951}
1952
1953static int iommu_prepare_identity_map(struct pci_dev *pdev,
1954 unsigned long long start,
1955 unsigned long long end)
1956{
1957 struct dmar_domain *domain;
1958 int ret;
1959
c7ab48d2 1960 domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
b213203e
DW		 1961 if (!domain)
1962 return -ENOMEM;
1963
19943b0e
DW		 1964 /* For _hardware_ passthrough, don't bother. But for software
1965 passthrough, we do it anyway -- it may indicate a memory
1966 range which is reserved in E820, so which didn't get set
1967 up to start with in si_domain */
1968 if (domain == si_domain && hw_pass_through) {
1969 printk("Ignoring identity map for HW passthrough device %s [0x%Lx - 0x%Lx]\n",
1970 pci_name(pdev), start, end);
1971 return 0;
1972 }
1973
1974 printk(KERN_INFO
1975 "IOMMU: Setting identity map for device %s [0x%Lx - 0x%Lx]\n",
1976 pci_name(pdev), start, end);
1977
b213203e 1978 ret = iommu_domain_identity_map(domain, start, end);
ba395927
KA		 1979 if (ret)
1980 goto error;
1981
1982 /* context entry init */
4ed0d3e6 1983 ret = domain_context_mapping(domain, pdev, CONTEXT_TT_MULTI_LEVEL);
b213203e
DW		 1984 if (ret)
1985 goto error;
1986
1987 return 0;
1988
1989 error:
ba395927
KA		 1990 domain_exit(domain);
1991 return ret;
ba395927
KA		 1992}
1993
1994static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit *rmrr,
1995 struct pci_dev *pdev)
1996{
358dd8ac 1997 if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
ba395927
KA		 1998 return 0;
1999 return iommu_prepare_identity_map(pdev, rmrr->base_address,
2000 rmrr->end_address + 1);
2001}
2002
49a0429e
KA		 2003#ifdef CONFIG_DMAR_FLOPPY_WA
2004static inline void iommu_prepare_isa(void)
2005{
2006 struct pci_dev *pdev;
2007 int ret;
2008
2009 pdev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
2010 if (!pdev)
2011 return;
2012
c7ab48d2 2013 printk(KERN_INFO "IOMMU: Prepare 0-16MiB unity mapping for LPC\n");
49a0429e
KA		 2014 ret = iommu_prepare_identity_map(pdev, 0, 16*1024*1024);
2015
2016 if (ret)
c7ab48d2
DW		 2017 printk(KERN_ERR "IOMMU: Failed to create 0-16MiB identity map; "
2018 "floppy might not work\n");
49a0429e
KA		 2019
2020}
2021#else
2022static inline void iommu_prepare_isa(void)
2023{
2024 return;
2025}
2026#endif /* !CONFIG_DMAR_FLPY_WA */
2027
2c2e2c38 2028static int md_domain_init(struct dmar_domain *domain, int guest_width);
c7ab48d2
DW		 2029
2030static int __init si_domain_work_fn(unsigned long start_pfn,
2031 unsigned long end_pfn, void *datax)
2032{
2033 int *ret = datax;
2034
2035 *ret = iommu_domain_identity_map(si_domain,
2036 (uint64_t)start_pfn << PAGE_SHIFT,
2037 (uint64_t)end_pfn << PAGE_SHIFT);
2038 return *ret;
2039
2040}
2041
071e1374 2042static int __init si_domain_init(int hw)
2c2e2c38
FY		 2043{
2044 struct dmar_drhd_unit *drhd;
2045 struct intel_iommu *iommu;
c7ab48d2 2046 int nid, ret = 0;
2c2e2c38
FY		 2047
2048 si_domain = alloc_domain();
2049 if (!si_domain)
2050 return -EFAULT;
2051
c7ab48d2 2052 pr_debug("Identity mapping domain is domain %d\n", si_domain->id);
2c2e2c38
FY		 2053
2054 for_each_active_iommu(iommu, drhd) {
2055 ret = iommu_attach_domain(si_domain, iommu);
2056 if (ret) {
2057 domain_exit(si_domain);
2058 return -EFAULT;
2059 }
2060 }
2061
2062 if (md_domain_init(si_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
2063 domain_exit(si_domain);
2064 return -EFAULT;
2065 }
2066
2067 si_domain->flags = DOMAIN_FLAG_STATIC_IDENTITY;
2068
19943b0e
DW		 2069 if (hw)
2070 return 0;
2071
c7ab48d2
DW		 2072 for_each_online_node(nid) {
2073 work_with_active_regions(nid, si_domain_work_fn, &ret);
2074 if (ret)
2075 return ret;
2076 }
2077
2c2e2c38
FY		 2078 return 0;
2079}
2080
2081static void domain_remove_one_dev_info(struct dmar_domain *domain,
2082 struct pci_dev *pdev);
2083static int identity_mapping(struct pci_dev *pdev)
2084{
2085 struct device_domain_info *info;
2086
2087 if (likely(!iommu_identity_mapping))
2088 return 0;
2089
2090
2091 list_for_each_entry(info, &si_domain->devices, link)
2092 if (info->dev == pdev)
2093 return 1;
2094 return 0;
2095}
2096
2097static int domain_add_dev_info(struct dmar_domain *domain,
5fe60f4e
DW		 2098 struct pci_dev *pdev,
2099 int translation)
2c2e2c38
FY		 2100{
2101 struct device_domain_info *info;
2102 unsigned long flags;
5fe60f4e 2103 int ret;
2c2e2c38
FY		 2104
2105 info = alloc_devinfo_mem();
2106 if (!info)
2107 return -ENOMEM;
2108
5fe60f4e
DW		 2109 ret = domain_context_mapping(domain, pdev, translation);
2110 if (ret) {
2111 free_devinfo_mem(info);
2112 return ret;
2113 }
2114
2c2e2c38
FY		 2115 info->segment = pci_domain_nr(pdev->bus);
2116 info->bus = pdev->bus->number;
2117 info->devfn = pdev->devfn;
2118 info->dev = pdev;
2119 info->domain = domain;
2120
2121 spin_lock_irqsave(&device_domain_lock, flags);
2122 list_add(&info->link, &domain->devices);
2123 list_add(&info->global, &device_domain_list);
2124 pdev->dev.archdata.iommu = info;
2125 spin_unlock_irqrestore(&device_domain_lock, flags);
2126
2127 return 0;
2128}
2129
6941af28
DW		 2130static int iommu_should_identity_map(struct pci_dev *pdev, int startup)
2131{
2132 if (iommu_identity_mapping == 2)
2133 return IS_GFX_DEVICE(pdev);
2134
3dfc813d
DW		 2135 /*
2136 * We want to start off with all devices in the 1:1 domain, and
2137 * take them out later if we find they can't access all of memory.
2138 *
2139 * However, we can't do this for PCI devices behind bridges,
2140 * because all PCI devices behind the same bridge will end up
2141 * with the same source-id on their transactions.
2142 *
2143 * Practically speaking, we can't change things around for these
2144 * devices at run-time, because we can't be sure there'll be no
2145 * DMA transactions in flight for any of their siblings.
2146 *
2147 * So PCI devices (unless they're on the root bus) as well as
2148 * their parent PCI-PCI or PCIe-PCI bridges must be left _out_ of
2149 * the 1:1 domain, just in _case_ one of their siblings turns out
2150 * not to be able to map all of memory.
2151 */
2152 if (!pdev->is_pcie) {
2153 if (!pci_is_root_bus(pdev->bus))
2154 return 0;
2155 if (pdev->class >> 8 == PCI_CLASS_BRIDGE_PCI)
2156 return 0;
2157 } else if (pdev->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE)
2158 return 0;
2159
2160 /*
2161 * At boot time, we don't yet know if devices will be 64-bit capable.
2162 * Assume that they will -- if they turn out not to be, then we can
2163 * take them out of the 1:1 domain later.
2164 */
6941af28
DW		 2165 if (!startup)
2166 return pdev->dma_mask > DMA_BIT_MASK(32);
2167
2168 return 1;
2169}
2170
071e1374 2171static int __init iommu_prepare_static_identity_mapping(int hw)
2c2e2c38 2172{
2c2e2c38
FY		 2173 struct pci_dev *pdev = NULL;
2174 int ret;
2175
19943b0e 2176 ret = si_domain_init(hw);
2c2e2c38
FY		 2177 if (ret)
2178 return -EFAULT;
2179
2c2e2c38 2180 for_each_pci_dev(pdev) {
6941af28 2181 if (iommu_should_identity_map(pdev, 1)) {
19943b0e
DW		 2182 printk(KERN_INFO "IOMMU: %s identity mapping for device %s\n",
2183 hw ? "hardware" : "software", pci_name(pdev));
62edf5dc 2184
5fe60f4e 2185 ret = domain_add_dev_info(si_domain, pdev,
19943b0e 2186 hw ? CONTEXT_TT_PASS_THROUGH :
62edf5dc
DW		 2187 CONTEXT_TT_MULTI_LEVEL);
2188 if (ret)
2189 return ret;
62edf5dc 2190 }
2c2e2c38
FY		 2191 }
2192
2193 return 0;
2194}
2195
2196int __init init_dmars(void)
ba395927
KA		 2197{
2198 struct dmar_drhd_unit *drhd;
2199 struct dmar_rmrr_unit *rmrr;
2200 struct pci_dev *pdev;
2201 struct intel_iommu *iommu;
9d783ba0 2202 int i, ret;
2c2e2c38 2203
ba395927
KA		 2204 /*
2205 * for each drhd
2206 * allocate root
2207 * initialize and program root entry to not present
2208 * endfor
2209 */
2210 for_each_drhd_unit(drhd) {
5e0d2a6f 2211 g_num_of_iommus++;
2212 /*
2213 * lock not needed as this is only incremented in the single
2214 * threaded kernel __init code path all other access are read
2215 * only
2216 */
2217 }
2218
d9630fe9
WH		 2219 g_iommus = kcalloc(g_num_of_iommus, sizeof(struct intel_iommu *),
2220 GFP_KERNEL);
2221 if (!g_iommus) {
2222 printk(KERN_ERR "Allocating global iommu array failed\n");
2223 ret = -ENOMEM;
2224 goto error;
2225 }
2226
80b20dd8 2227 deferred_flush = kzalloc(g_num_of_iommus *
2228 sizeof(struct deferred_flush_tables), GFP_KERNEL);
2229 if (!deferred_flush) {
5e0d2a6f 2230 ret = -ENOMEM;
2231 goto error;
2232 }
2233
5e0d2a6f 2234 for_each_drhd_unit(drhd) {
2235 if (drhd->ignored)
2236 continue;
1886e8a9
SS		 2237
2238 iommu = drhd->iommu;
d9630fe9 2239 g_iommus[iommu->seq_id] = iommu;
ba395927 2240
e61d98d8
SS		 2241 ret = iommu_init_domains(iommu);
2242 if (ret)
2243 goto error;
2244
ba395927
KA		 2245 /*
2246 * TBD:
2247 * we could share the same root & context tables
2248 * amoung all IOMMU's. Need to Split it later.
2249 */
2250 ret = iommu_alloc_root_entry(iommu);
2251 if (ret) {
2252 printk(KERN_ERR "IOMMU: allocate root entry failed\n");
2253 goto error;
2254 }
4ed0d3e6 2255 if (!ecap_pass_through(iommu->ecap))
19943b0e 2256 hw_pass_through = 0;
ba395927
KA		 2257 }
2258
1531a6a6
SS		 2259 /*
2260 * Start from the sane iommu hardware state.
2261 */
a77b67d4
YS		 2262 for_each_drhd_unit(drhd) {
2263 if (drhd->ignored)
2264 continue;
2265
2266 iommu = drhd->iommu;
1531a6a6
SS		 2267
2268 /*
2269 * If the queued invalidation is already initialized by us
2270 * (for example, while enabling interrupt-remapping) then
2271 * we got the things already rolling from a sane state.
2272 */
2273 if (iommu->qi)
2274 continue;
2275
2276 /*
2277 * Clear any previous faults.
2278 */
2279 dmar_fault(-1, iommu);
2280 /*
2281 * Disable queued invalidation if supported and already enabled
2282 * before OS handover.
2283 */
2284 dmar_disable_qi(iommu);
2285 }
2286
2287 for_each_drhd_unit(drhd) {
2288 if (drhd->ignored)
2289 continue;
2290
2291 iommu = drhd->iommu;
2292
a77b67d4
YS		 2293 if (dmar_enable_qi(iommu)) {
2294 /*
2295 * Queued Invalidate not enabled, use Register Based
2296 * Invalidate
2297 */
2298 iommu->flush.flush_context = __iommu_flush_context;
2299 iommu->flush.flush_iotlb = __iommu_flush_iotlb;
2300 printk(KERN_INFO "IOMMU 0x%Lx: using Register based "
b4e0f9eb
FT		 2301 "invalidation\n",
2302 (unsigned long long)drhd->reg_base_addr);
a77b67d4
YS		 2303 } else {
2304 iommu->flush.flush_context = qi_flush_context;
2305 iommu->flush.flush_iotlb = qi_flush_iotlb;
2306 printk(KERN_INFO "IOMMU 0x%Lx: using Queued "
b4e0f9eb
FT		 2307 "invalidation\n",
2308 (unsigned long long)drhd->reg_base_addr);
a77b67d4
YS		 2309 }
2310 }
2311
19943b0e
DW		 2312 if (iommu_pass_through)
2313 iommu_identity_mapping = 1;
2314#ifdef CONFIG_DMAR_BROKEN_GFX_WA
2315 else
2316 iommu_identity_mapping = 2;
2317#endif
ba395927 2318 /*
19943b0e
DW		 2319 * If pass through is not set or not enabled, setup context entries for
2320 * identity mappings for rmrr, gfx, and isa and may fall back to static
2321 * identity mapping if iommu_identity_mapping is set.
ba395927 2322 */
19943b0e
DW		 2323 if (iommu_identity_mapping) {
2324 ret = iommu_prepare_static_identity_mapping(hw_pass_through);
4ed0d3e6 2325 if (ret) {
19943b0e
DW		 2326 printk(KERN_CRIT "Failed to setup IOMMU pass-through\n");
2327 goto error;
ba395927
KA		 2328 }
2329 }
ba395927 2330 /*
19943b0e
DW		 2331 * For each rmrr
2332 * for each dev attached to rmrr
2333 * do
2334 * locate drhd for dev, alloc domain for dev
2335 * allocate free domain
2336 * allocate page table entries for rmrr
2337 * if context not allocated for bus
2338 * allocate and init context
2339 * set present in root table for this bus
2340 * init context with domain, translation etc
2341 * endfor
2342 * endfor
ba395927 2343 */
19943b0e
DW		 2344 printk(KERN_INFO "IOMMU: Setting RMRR:\n");
2345 for_each_rmrr_units(rmrr) {
2346 for (i = 0; i < rmrr->devices_cnt; i++) {
2347 pdev = rmrr->devices[i];
2348 /*
2349 * some BIOS lists non-exist devices in DMAR
2350 * table.
2351 */
2352 if (!pdev)
2353 continue;
2354 ret = iommu_prepare_rmrr_dev(rmrr, pdev);
2355 if (ret)
2356 printk(KERN_ERR
2357 "IOMMU: mapping reserved region failed\n");
ba395927 2358 }
4ed0d3e6 2359 }
49a0429e 2360
19943b0e
DW		 2361 iommu_prepare_isa();
2362
ba395927
KA		 2363 /*
2364 * for each drhd
2365 * enable fault log
2366 * global invalidate context cache
2367 * global invalidate iotlb
2368 * enable translation
2369 */
2370 for_each_drhd_unit(drhd) {
2371 if (drhd->ignored)
2372 continue;
2373 iommu = drhd->iommu;
ba395927
KA		 2374
2375 iommu_flush_write_buffer(iommu);
2376
3460a6d9
KA		 2377 ret = dmar_set_interrupt(iommu);
2378 if (ret)
2379 goto error;
2380
ba395927
KA		 2381 iommu_set_root_entry(iommu);
2382
4c25a2c1 2383 iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL);
1f0ef2aa 2384 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
f8bab735 2385 iommu_disable_protect_mem_regions(iommu);
2386
ba395927
KA		 2387 ret = iommu_enable_translation(iommu);
2388 if (ret)
2389 goto error;
2390 }
2391
2392 return 0;
2393error:
2394 for_each_drhd_unit(drhd) {
2395 if (drhd->ignored)
2396 continue;
2397 iommu = drhd->iommu;
2398 free_iommu(iommu);
2399 }
d9630fe9 2400 kfree(g_iommus);
ba395927
KA		 2401 return ret;
2402}
2403
5a5e02a6 2404/* This takes a number of _MM_ pages, not VTD pages */
875764de
DW		 2405static struct iova *intel_alloc_iova(struct device *dev,
2406 struct dmar_domain *domain,
2407 unsigned long nrpages, uint64_t dma_mask)
ba395927 2408{
ba395927 2409 struct pci_dev *pdev = to_pci_dev(dev);
ba395927 2410 struct iova *iova = NULL;
ba395927 2411
875764de
DW		 2412 /* Restrict dma_mask to the width that the iommu can handle */
2413 dma_mask = min_t(uint64_t, DOMAIN_MAX_ADDR(domain->gaw), dma_mask);
2414
2415 if (!dmar_forcedac && dma_mask > DMA_BIT_MASK(32)) {
ba395927
KA		 2416 /*
2417 * First try to allocate an io virtual address in
284901a9 2418 * DMA_BIT_MASK(32) and if that fails then try allocating
3609801e 2419 * from higher range
ba395927 2420 */
875764de
DW		 2421 iova = alloc_iova(&domain->iovad, nrpages,
2422 IOVA_PFN(DMA_BIT_MASK(32)), 1);
2423 if (iova)
2424 return iova;
2425 }
2426 iova = alloc_iova(&domain->iovad, nrpages, IOVA_PFN(dma_mask), 1);
2427 if (unlikely(!iova)) {
2428 printk(KERN_ERR "Allocating %ld-page iova for %s failed",
2429 nrpages, pci_name(pdev));
f76aec76
KA		 2430 return NULL;
2431 }
2432
2433 return iova;
2434}
2435
147202aa 2436static struct dmar_domain *__get_valid_domain_for_dev(struct pci_dev *pdev)
f76aec76
KA		 2437{
2438 struct dmar_domain *domain;
2439 int ret;
2440
2441 domain = get_domain_for_dev(pdev,
2442 DEFAULT_DOMAIN_ADDRESS_WIDTH);
2443 if (!domain) {
2444 printk(KERN_ERR
2445 "Allocating domain for %s failed", pci_name(pdev));
4fe05bbc 2446 return NULL;
ba395927
KA		 2447 }
2448
2449 /* make sure context mapping is ok */
5331fe6f 2450 if (unlikely(!domain_context_mapped(pdev))) {
4ed0d3e6
FY		 2451 ret = domain_context_mapping(domain, pdev,
2452 CONTEXT_TT_MULTI_LEVEL);
f76aec76
KA		 2453 if (ret) {
2454 printk(KERN_ERR
2455 "Domain context map for %s failed",
2456 pci_name(pdev));
4fe05bbc 2457 return NULL;
f76aec76 2458 }
ba395927
KA		 2459 }
2460
f76aec76
KA		 2461 return domain;
2462}
2463
147202aa
DW		 2464static inline struct dmar_domain *get_valid_domain_for_dev(struct pci_dev *dev)
2465{
2466 struct device_domain_info *info;
2467
2468 /* No lock here, assumes no domain exit in normal case */
2469 info = dev->dev.archdata.iommu;
2470 if (likely(info))
2471 return info->domain;
2472
2473 return __get_valid_domain_for_dev(dev);
2474}
2475
2c2e2c38
FY		 2476static int iommu_dummy(struct pci_dev *pdev)
2477{
2478 return pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO;
2479}
2480
2481/* Check if the pdev needs to go through non-identity map and unmap process.*/
73676832 2482static int iommu_no_mapping(struct device *dev)
2c2e2c38 2483{
73676832 2484 struct pci_dev *pdev;
2c2e2c38
FY		 2485 int found;
2486
73676832
DW		 2487 if (unlikely(dev->bus != &pci_bus_type))
2488 return 1;
2489
2490 pdev = to_pci_dev(dev);
1e4c64c4
DW		 2491 if (iommu_dummy(pdev))
2492 return 1;
2493
2c2e2c38 2494 if (!iommu_identity_mapping)
1e4c64c4 2495 return 0;
2c2e2c38
FY		 2496
2497 found = identity_mapping(pdev);
2498 if (found) {
6941af28 2499 if (iommu_should_identity_map(pdev, 0))
2c2e2c38
FY		 2500 return 1;
2501 else {
2502 /*
2503 * 32 bit DMA is removed from si_domain and fall back
2504 * to non-identity mapping.
2505 */
2506 domain_remove_one_dev_info(si_domain, pdev);
2507 printk(KERN_INFO "32bit %s uses non-identity mapping\n",
2508 pci_name(pdev));
2509 return 0;
2510 }
2511 } else {
2512 /*
2513 * In case of a detached 64 bit DMA device from vm, the device
2514 * is put into si_domain for identity mapping.
2515 */
6941af28 2516 if (iommu_should_identity_map(pdev, 0)) {
2c2e2c38 2517 int ret;
5fe60f4e
DW		 2518 ret = domain_add_dev_info(si_domain, pdev,
2519 hw_pass_through ?
2520 CONTEXT_TT_PASS_THROUGH :
2521 CONTEXT_TT_MULTI_LEVEL);
2c2e2c38
FY		 2522 if (!ret) {
2523 printk(KERN_INFO "64bit %s uses identity mapping\n",
2524 pci_name(pdev));
2525 return 1;
2526 }
2527 }
2528 }
2529
1e4c64c4 2530 return 0;
2c2e2c38
FY		 2531}
2532
bb9e6d65
FT		 2533static dma_addr_t __intel_map_single(struct device *hwdev, phys_addr_t paddr,
2534 size_t size, int dir, u64 dma_mask)
f76aec76
KA		 2535{
2536 struct pci_dev *pdev = to_pci_dev(hwdev);
f76aec76 2537 struct dmar_domain *domain;
5b6985ce 2538 phys_addr_t start_paddr;
f76aec76
KA		 2539 struct iova *iova;
2540 int prot = 0;
6865f0d1 2541 int ret;
8c11e798 2542 struct intel_iommu *iommu;
33041ec0 2543 unsigned long paddr_pfn = paddr >> PAGE_SHIFT;
f76aec76
KA		 2544
2545 BUG_ON(dir == DMA_NONE);
2c2e2c38 2546
73676832 2547 if (iommu_no_mapping(hwdev))
6865f0d1 2548 return paddr;
f76aec76
KA		 2549
2550 domain = get_valid_domain_for_dev(pdev);
2551 if (!domain)
2552 return 0;
2553
8c11e798 2554 iommu = domain_get_iommu(domain);
88cb6a74 2555 size = aligned_nrpages(paddr, size);
f76aec76 2556
5a5e02a6
DW		 2557 iova = intel_alloc_iova(hwdev, domain, dma_to_mm_pfn(size),
2558 pdev->dma_mask);
f76aec76
KA		 2559 if (!iova)
2560 goto error;
2561
ba395927
KA		 2562 /*
2563 * Check if DMAR supports zero-length reads on write only
2564 * mappings..
2565 */
2566 if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
8c11e798 2567 !cap_zlr(iommu->cap))
ba395927
KA		 2568 prot |= DMA_PTE_READ;
2569 if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
2570 prot |= DMA_PTE_WRITE;
2571 /*
6865f0d1 2572 * paddr - (paddr + size) might be partial page, we should map the whole
ba395927 2573 * page. Note: if two part of one page are separately mapped, we
6865f0d1 2574 * might have two guest_addr mapping to the same host paddr, but this
ba395927
KA		 2575 * is not a big problem
2576 */
0ab36de2 2577 ret = domain_pfn_mapping(domain, mm_to_dma_pfn(iova->pfn_lo),
33041ec0 2578 mm_to_dma_pfn(paddr_pfn), size, prot);
ba395927
KA		 2579 if (ret)
2580 goto error;
2581
1f0ef2aa
DW		 2582 /* it's a non-present to present mapping. Only flush if caching mode */
2583 if (cap_caching_mode(iommu->cap))
03d6a246 2584 iommu_flush_iotlb_psi(iommu, 0, mm_to_dma_pfn(iova->pfn_lo), size);
1f0ef2aa 2585 else
8c11e798 2586 iommu_flush_write_buffer(iommu);
f76aec76 2587
03d6a246
DW		 2588 start_paddr = (phys_addr_t)iova->pfn_lo << PAGE_SHIFT;
2589 start_paddr += paddr & ~PAGE_MASK;
2590 return start_paddr;
ba395927 2591
ba395927 2592error:
f76aec76
KA		 2593 if (iova)
2594 __free_iova(&domain->iovad, iova);
4cf2e75d 2595 printk(KERN_ERR"Device %s request: %zx@%llx dir %d --- failed\n",
5b6985ce 2596 pci_name(pdev), size, (unsigned long long)paddr, dir);
ba395927
KA		 2597 return 0;
2598}
2599
ffbbef5c
FT		 2600static dma_addr_t intel_map_page(struct device *dev, struct page *page,
2601 unsigned long offset, size_t size,
2602 enum dma_data_direction dir,
2603 struct dma_attrs *attrs)
bb9e6d65 2604{
ffbbef5c
FT		 2605 return __intel_map_single(dev, page_to_phys(page) + offset, size,
2606 dir, to_pci_dev(dev)->dma_mask);
bb9e6d65
FT		 2607}
2608
5e0d2a6f 2609static void flush_unmaps(void)
2610{
80b20dd8 2611 int i, j;
5e0d2a6f 2612
5e0d2a6f 2613 timer_on = 0;
2614
2615 /* just flush them all */
2616 for (i = 0; i < g_num_of_iommus; i++) {
a2bb8459
WH		 2617 struct intel_iommu *iommu = g_iommus[i];
2618 if (!iommu)
2619 continue;
c42d9f32 2620
9dd2fe89
YZ		 2621 if (!deferred_flush[i].next)
2622 continue;
2623
2624 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
93a23a72 2625 DMA_TLB_GLOBAL_FLUSH);
9dd2fe89 2626 for (j = 0; j < deferred_flush[i].next; j++) {
93a23a72
YZ		 2627 unsigned long mask;
2628 struct iova *iova = deferred_flush[i].iova[j];
2629
2630 mask = (iova->pfn_hi - iova->pfn_lo + 1) << PAGE_SHIFT;
2631 mask = ilog2(mask >> VTD_PAGE_SHIFT);
2632 iommu_flush_dev_iotlb(deferred_flush[i].domain[j],
2633 iova->pfn_lo << PAGE_SHIFT, mask);
2634 __free_iova(&deferred_flush[i].domain[j]->iovad, iova);
80b20dd8 2635 }
9dd2fe89 2636 deferred_flush[i].next = 0;
5e0d2a6f 2637 }
2638
5e0d2a6f 2639 list_size = 0;
5e0d2a6f 2640}
2641
2642static void flush_unmaps_timeout(unsigned long data)
2643{
80b20dd8 2644 unsigned long flags;
2645
2646 spin_lock_irqsave(&async_umap_flush_lock, flags);
5e0d2a6f 2647 flush_unmaps();
80b20dd8 2648 spin_unlock_irqrestore(&async_umap_flush_lock, flags);
5e0d2a6f 2649}
2650
2651static void add_unmap(struct dmar_domain *dom, struct iova *iova)
2652{
2653 unsigned long flags;
80b20dd8 2654 int next, iommu_id;
8c11e798 2655 struct intel_iommu *iommu;
5e0d2a6f 2656
2657 spin_lock_irqsave(&async_umap_flush_lock, flags);
80b20dd8 2658 if (list_size == HIGH_WATER_MARK)
2659 flush_unmaps();
2660
8c11e798
WH		 2661 iommu = domain_get_iommu(dom);
2662 iommu_id = iommu->seq_id;
c42d9f32 2663
80b20dd8 2664 next = deferred_flush[iommu_id].next;
2665 deferred_flush[iommu_id].domain[next] = dom;
2666 deferred_flush[iommu_id].iova[next] = iova;
2667 deferred_flush[iommu_id].next++;
5e0d2a6f 2668
2669 if (!timer_on) {
2670 mod_timer(&unmap_timer, jiffies + msecs_to_jiffies(10));
2671 timer_on = 1;
2672 }
2673 list_size++;
2674 spin_unlock_irqrestore(&async_umap_flush_lock, flags);
2675}
2676
ffbbef5c
FT		 2677static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr,
2678 size_t size, enum dma_data_direction dir,
2679 struct dma_attrs *attrs)
ba395927 2680{
ba395927 2681 struct pci_dev *pdev = to_pci_dev(dev);
f76aec76 2682 struct dmar_domain *domain;
d794dc9b 2683 unsigned long start_pfn, last_pfn;
ba395927 2684 struct iova *iova;
8c11e798 2685 struct intel_iommu *iommu;
ba395927 2686
73676832 2687 if (iommu_no_mapping(dev))
f76aec76 2688 return;
2c2e2c38 2689
ba395927
KA		 2690 domain = find_domain(pdev);
2691 BUG_ON(!domain);
2692
8c11e798
WH		 2693 iommu = domain_get_iommu(domain);
2694
ba395927 2695 iova = find_iova(&domain->iovad, IOVA_PFN(dev_addr));
85b98276
DW		 2696 if (WARN_ONCE(!iova, "Driver unmaps unmatched page at PFN %llx\n",
2697 (unsigned long long)dev_addr))
ba395927 2698 return;
ba395927 2699
d794dc9b
DW		 2700 start_pfn = mm_to_dma_pfn(iova->pfn_lo);
2701 last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
ba395927 2702
d794dc9b
DW		 2703 pr_debug("Device %s unmapping: pfn %lx-%lx\n",
2704 pci_name(pdev), start_pfn, last_pfn);
ba395927 2705
f76aec76 2706 /* clear the whole page */
d794dc9b
DW		 2707 dma_pte_clear_range(domain, start_pfn, last_pfn);
2708
f76aec76 2709 /* free page tables */
d794dc9b
DW		 2710 dma_pte_free_pagetable(domain, start_pfn, last_pfn);
2711
5e0d2a6f 2712 if (intel_iommu_strict) {
03d6a246 2713 iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
d794dc9b 2714 last_pfn - start_pfn + 1);
5e0d2a6f 2715 /* free iova */
2716 __free_iova(&domain->iovad, iova);
2717 } else {
2718 add_unmap(domain, iova);
2719 /*
2720 * queue up the release of the unmap to save the 1/6th of the
2721 * cpu used up by the iotlb flush operation...
2722 */
5e0d2a6f 2723 }
ba395927
KA		 2724}
2725
d7ab5c46
FT		 2726static void *intel_alloc_coherent(struct device *hwdev, size_t size,
2727 dma_addr_t *dma_handle, gfp_t flags)
ba395927
KA		 2728{
2729 void *vaddr;
2730 int order;
2731
5b6985ce 2732 size = PAGE_ALIGN(size);
ba395927
KA		 2733 order = get_order(size);
2734 flags &= ~(GFP_DMA | GFP_DMA32);
2735
2736 vaddr = (void *)__get_free_pages(flags, order);
2737 if (!vaddr)
2738 return NULL;
2739 memset(vaddr, 0, size);
2740
bb9e6d65
FT		 2741 *dma_handle = __intel_map_single(hwdev, virt_to_bus(vaddr), size,
2742 DMA_BIDIRECTIONAL,
2743 hwdev->coherent_dma_mask);
ba395927
KA		 2744 if (*dma_handle)
2745 return vaddr;
2746 free_pages((unsigned long)vaddr, order);
2747 return NULL;
2748}
2749
d7ab5c46
FT		 2750static void intel_free_coherent(struct device *hwdev, size_t size, void *vaddr,
2751 dma_addr_t dma_handle)
ba395927
KA		 2752{
2753 int order;
2754
5b6985ce 2755 size = PAGE_ALIGN(size);
ba395927
KA		 2756 order = get_order(size);
2757
0db9b7ae 2758 intel_unmap_page(hwdev, dma_handle, size, DMA_BIDIRECTIONAL, NULL);
ba395927
KA		 2759 free_pages((unsigned long)vaddr, order);
2760}
2761
d7ab5c46
FT		 2762static void intel_unmap_sg(struct device *hwdev, struct scatterlist *sglist,
2763 int nelems, enum dma_data_direction dir,
2764 struct dma_attrs *attrs)
ba395927 2765{
ba395927
KA		 2766 struct pci_dev *pdev = to_pci_dev(hwdev);
2767 struct dmar_domain *domain;
d794dc9b 2768 unsigned long start_pfn, last_pfn;
f76aec76 2769 struct iova *iova;
8c11e798 2770 struct intel_iommu *iommu;
ba395927 2771
73676832 2772 if (iommu_no_mapping(hwdev))
ba395927
KA		 2773 return;
2774
2775 domain = find_domain(pdev);
8c11e798
WH		 2776 BUG_ON(!domain);
2777
2778 iommu = domain_get_iommu(domain);
ba395927 2779
c03ab37c 2780 iova = find_iova(&domain->iovad, IOVA_PFN(sglist[0].dma_address));
85b98276
DW		 2781 if (WARN_ONCE(!iova, "Driver unmaps unmatched sglist at PFN %llx\n",
2782 (unsigned long long)sglist[0].dma_address))
f76aec76 2783 return;
f76aec76 2784
d794dc9b
DW		 2785 start_pfn = mm_to_dma_pfn(iova->pfn_lo);
2786 last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
f76aec76
KA		 2787
2788 /* clear the whole page */
d794dc9b
DW		 2789 dma_pte_clear_range(domain, start_pfn, last_pfn);
2790
f76aec76 2791 /* free page tables */
d794dc9b 2792 dma_pte_free_pagetable(domain, start_pfn, last_pfn);
f76aec76 2793
acea0018
DW		 2794 if (intel_iommu_strict) {
2795 iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
2796 last_pfn - start_pfn + 1);
2797 /* free iova */
2798 __free_iova(&domain->iovad, iova);
2799 } else {
2800 add_unmap(domain, iova);
2801 /*
2802 * queue up the release of the unmap to save the 1/6th of the
2803 * cpu used up by the iotlb flush operation...
2804 */
2805 }
ba395927
KA		 2806}
2807
ba395927 2808static int intel_nontranslate_map_sg(struct device *hddev,
c03ab37c 2809 struct scatterlist *sglist, int nelems, int dir)
ba395927
KA		 2810{
2811 int i;
c03ab37c 2812 struct scatterlist *sg;
ba395927 2813
c03ab37c 2814 for_each_sg(sglist, sg, nelems, i) {
12d4d40e 2815 BUG_ON(!sg_page(sg));
4cf2e75d 2816 sg->dma_address = page_to_phys(sg_page(sg)) + sg->offset;
c03ab37c 2817 sg->dma_length = sg->length;
ba395927
KA		 2818 }
2819 return nelems;
2820}
2821
d7ab5c46
FT		 2822static int intel_map_sg(struct device *hwdev, struct scatterlist *sglist, int nelems,
2823 enum dma_data_direction dir, struct dma_attrs *attrs)
ba395927 2824{
ba395927 2825 int i;
ba395927
KA		 2826 struct pci_dev *pdev = to_pci_dev(hwdev);
2827 struct dmar_domain *domain;
f76aec76
KA		 2828 size_t size = 0;
2829 int prot = 0;
b536d24d 2830 size_t offset_pfn = 0;
f76aec76
KA		 2831 struct iova *iova = NULL;
2832 int ret;
c03ab37c 2833 struct scatterlist *sg;
b536d24d 2834 unsigned long start_vpfn;
8c11e798 2835 struct intel_iommu *iommu;
ba395927
KA		 2836
2837 BUG_ON(dir == DMA_NONE);
73676832 2838 if (iommu_no_mapping(hwdev))
c03ab37c 2839 return intel_nontranslate_map_sg(hwdev, sglist, nelems, dir);
ba395927 2840
f76aec76
KA		 2841 domain = get_valid_domain_for_dev(pdev);
2842 if (!domain)
2843 return 0;
2844
8c11e798
WH		 2845 iommu = domain_get_iommu(domain);
2846
b536d24d 2847 for_each_sg(sglist, sg, nelems, i)
88cb6a74 2848 size += aligned_nrpages(sg->offset, sg->length);
f76aec76 2849
5a5e02a6
DW		 2850 iova = intel_alloc_iova(hwdev, domain, dma_to_mm_pfn(size),
2851 pdev->dma_mask);
f76aec76 2852 if (!iova) {
c03ab37c 2853 sglist->dma_length = 0;
f76aec76
KA		 2854 return 0;
2855 }
2856
2857 /*
2858 * Check if DMAR supports zero-length reads on write only
2859 * mappings..
2860 */
2861 if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
8c11e798 2862 !cap_zlr(iommu->cap))
f76aec76
KA		 2863 prot |= DMA_PTE_READ;
2864 if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
2865 prot |= DMA_PTE_WRITE;
2866
b536d24d 2867 start_vpfn = mm_to_dma_pfn(iova->pfn_lo);
e1605495 2868
f532959b 2869 ret = domain_sg_mapping(domain, start_vpfn, sglist, size, prot);
e1605495
DW		 2870 if (unlikely(ret)) {
2871 /* clear the page */
2872 dma_pte_clear_range(domain, start_vpfn,
2873 start_vpfn + size - 1);
2874 /* free page tables */
2875 dma_pte_free_pagetable(domain, start_vpfn,
2876 start_vpfn + size - 1);
2877 /* free iova */
2878 __free_iova(&domain->iovad, iova);
2879 return 0;
ba395927
KA		 2880 }
2881
1f0ef2aa
DW		 2882 /* it's a non-present to present mapping. Only flush if caching mode */
2883 if (cap_caching_mode(iommu->cap))
03d6a246 2884 iommu_flush_iotlb_psi(iommu, 0, start_vpfn, offset_pfn);
1f0ef2aa 2885 else
8c11e798 2886 iommu_flush_write_buffer(iommu);
1f0ef2aa 2887
ba395927
KA		 2888 return nelems;
2889}
2890
dfb805e8
FT		 2891static int intel_mapping_error(struct device *dev, dma_addr_t dma_addr)
2892{
2893 return !dma_addr;
2894}
2895
160c1d8e 2896struct dma_map_ops intel_dma_ops = {
ba395927
KA		 2897 .alloc_coherent = intel_alloc_coherent,
2898 .free_coherent = intel_free_coherent,
ba395927
KA		 2899 .map_sg = intel_map_sg,
2900 .unmap_sg = intel_unmap_sg,
ffbbef5c
FT		 2901 .map_page = intel_map_page,
2902 .unmap_page = intel_unmap_page,
dfb805e8 2903 .mapping_error = intel_mapping_error,
ba395927
KA		 2904};
2905
2906static inline int iommu_domain_cache_init(void)
2907{
2908 int ret = 0;
2909
2910 iommu_domain_cache = kmem_cache_create("iommu_domain",
2911 sizeof(struct dmar_domain),
2912 0,
2913 SLAB_HWCACHE_ALIGN,
2914
2915 NULL);
2916 if (!iommu_domain_cache) {
2917 printk(KERN_ERR "Couldn't create iommu_domain cache\n");
2918 ret = -ENOMEM;
2919 }
2920
2921 return ret;
2922}
2923
2924static inline int iommu_devinfo_cache_init(void)
2925{
2926 int ret = 0;
2927
2928 iommu_devinfo_cache = kmem_cache_create("iommu_devinfo",
2929 sizeof(struct device_domain_info),
2930 0,
2931 SLAB_HWCACHE_ALIGN,
ba395927
KA		 2932 NULL);
2933 if (!iommu_devinfo_cache) {
2934 printk(KERN_ERR "Couldn't create devinfo cache\n");
2935 ret = -ENOMEM;
2936 }
2937
2938 return ret;
2939}
2940
2941static inline int iommu_iova_cache_init(void)
2942{
2943 int ret = 0;
2944
2945 iommu_iova_cache = kmem_cache_create("iommu_iova",
2946 sizeof(struct iova),
2947 0,
2948 SLAB_HWCACHE_ALIGN,
ba395927
KA		 2949 NULL);
2950 if (!iommu_iova_cache) {
2951 printk(KERN_ERR "Couldn't create iova cache\n");
2952 ret = -ENOMEM;
2953 }
2954
2955 return ret;
2956}
2957
2958static int __init iommu_init_mempool(void)
2959{
2960 int ret;
2961 ret = iommu_iova_cache_init();
2962 if (ret)
2963 return ret;
2964
2965 ret = iommu_domain_cache_init();
2966 if (ret)
2967 goto domain_error;
2968
2969 ret = iommu_devinfo_cache_init();
2970 if (!ret)
2971 return ret;
2972
2973 kmem_cache_destroy(iommu_domain_cache);
2974domain_error:
2975 kmem_cache_destroy(iommu_iova_cache);
2976
2977 return -ENOMEM;
2978}
2979
2980static void __init iommu_exit_mempool(void)
2981{
2982 kmem_cache_destroy(iommu_devinfo_cache);
2983 kmem_cache_destroy(iommu_domain_cache);
2984 kmem_cache_destroy(iommu_iova_cache);
2985
2986}
2987
ba395927
KA		 2988static void __init init_no_remapping_devices(void)
2989{
2990 struct dmar_drhd_unit *drhd;
2991
2992 for_each_drhd_unit(drhd) {
2993 if (!drhd->include_all) {
2994 int i;
2995 for (i = 0; i < drhd->devices_cnt; i++)
2996 if (drhd->devices[i] != NULL)
2997 break;
2998 /* ignore DMAR unit if no pci devices exist */
2999 if (i == drhd->devices_cnt)
3000 drhd->ignored = 1;
3001 }
3002 }
3003
3004 if (dmar_map_gfx)
3005 return;
3006
3007 for_each_drhd_unit(drhd) {
3008 int i;
3009 if (drhd->ignored || drhd->include_all)
3010 continue;
3011
3012 for (i = 0; i < drhd->devices_cnt; i++)
3013 if (drhd->devices[i] &&
3014 !IS_GFX_DEVICE(drhd->devices[i]))
3015 break;
3016
3017 if (i < drhd->devices_cnt)
3018 continue;
3019
3020 /* bypass IOMMU if it is just for gfx devices */
3021 drhd->ignored = 1;
3022 for (i = 0; i < drhd->devices_cnt; i++) {
3023 if (!drhd->devices[i])
3024 continue;
358dd8ac 3025 drhd->devices[i]->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
ba395927
KA		 3026 }
3027 }
3028}
3029
f59c7b69
FY		 3030#ifdef CONFIG_SUSPEND
3031static int init_iommu_hw(void)
3032{
3033 struct dmar_drhd_unit *drhd;
3034 struct intel_iommu *iommu = NULL;
3035
3036 for_each_active_iommu(iommu, drhd)
3037 if (iommu->qi)
3038 dmar_reenable_qi(iommu);
3039
3040 for_each_active_iommu(iommu, drhd) {
3041 iommu_flush_write_buffer(iommu);
3042
3043 iommu_set_root_entry(iommu);
3044
3045 iommu->flush.flush_context(iommu, 0, 0, 0,
1f0ef2aa 3046 DMA_CCMD_GLOBAL_INVL);
f59c7b69 3047 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
1f0ef2aa 3048 DMA_TLB_GLOBAL_FLUSH);
f59c7b69
FY		 3049 iommu_disable_protect_mem_regions(iommu);
3050 iommu_enable_translation(iommu);
3051 }
3052
3053 return 0;
3054}
3055
3056static void iommu_flush_all(void)
3057{
3058 struct dmar_drhd_unit *drhd;
3059 struct intel_iommu *iommu;
3060
3061 for_each_active_iommu(iommu, drhd) {
3062 iommu->flush.flush_context(iommu, 0, 0, 0,
1f0ef2aa 3063 DMA_CCMD_GLOBAL_INVL);
f59c7b69 3064 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
1f0ef2aa 3065 DMA_TLB_GLOBAL_FLUSH);
f59c7b69
FY		 3066 }
3067}
3068
3069static int iommu_suspend(struct sys_device *dev, pm_message_t state)
3070{
3071 struct dmar_drhd_unit *drhd;
3072 struct intel_iommu *iommu = NULL;
3073 unsigned long flag;
3074
3075 for_each_active_iommu(iommu, drhd) {
3076 iommu->iommu_state = kzalloc(sizeof(u32) * MAX_SR_DMAR_REGS,
3077 GFP_ATOMIC);
3078 if (!iommu->iommu_state)
3079 goto nomem;
3080 }
3081
3082 iommu_flush_all();
3083
3084 for_each_active_iommu(iommu, drhd) {
3085 iommu_disable_translation(iommu);
3086
3087 spin_lock_irqsave(&iommu->register_lock, flag);
3088
3089 iommu->iommu_state[SR_DMAR_FECTL_REG] =
3090 readl(iommu->reg + DMAR_FECTL_REG);
3091 iommu->iommu_state[SR_DMAR_FEDATA_REG] =
3092 readl(iommu->reg + DMAR_FEDATA_REG);
3093 iommu->iommu_state[SR_DMAR_FEADDR_REG] =
3094 readl(iommu->reg + DMAR_FEADDR_REG);
3095 iommu->iommu_state[SR_DMAR_FEUADDR_REG] =
3096 readl(iommu->reg + DMAR_FEUADDR_REG);
3097
3098 spin_unlock_irqrestore(&iommu->register_lock, flag);
3099 }
3100 return 0;
3101
3102nomem:
3103 for_each_active_iommu(iommu, drhd)
3104 kfree(iommu->iommu_state);
3105
3106 return -ENOMEM;
3107}
3108
3109static int iommu_resume(struct sys_device *dev)
3110{
3111 struct dmar_drhd_unit *drhd;
3112 struct intel_iommu *iommu = NULL;
3113 unsigned long flag;
3114
3115 if (init_iommu_hw()) {
3116 WARN(1, "IOMMU setup failed, DMAR can not resume!\n");
3117 return -EIO;
3118 }
3119
3120 for_each_active_iommu(iommu, drhd) {
3121
3122 spin_lock_irqsave(&iommu->register_lock, flag);
3123
3124 writel(iommu->iommu_state[SR_DMAR_FECTL_REG],
3125 iommu->reg + DMAR_FECTL_REG);
3126 writel(iommu->iommu_state[SR_DMAR_FEDATA_REG],
3127 iommu->reg + DMAR_FEDATA_REG);
3128 writel(iommu->iommu_state[SR_DMAR_FEADDR_REG],
3129 iommu->reg + DMAR_FEADDR_REG);
3130 writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG],
3131 iommu->reg + DMAR_FEUADDR_REG);
3132
3133 spin_unlock_irqrestore(&iommu->register_lock, flag);
3134 }
3135
3136 for_each_active_iommu(iommu, drhd)
3137 kfree(iommu->iommu_state);
3138
3139 return 0;
3140}
3141
3142static struct sysdev_class iommu_sysclass = {
3143 .name = "iommu",
3144 .resume = iommu_resume,
3145 .suspend = iommu_suspend,
3146};
3147
3148static struct sys_device device_iommu = {
3149 .cls = &iommu_sysclass,
3150};
3151
3152static int __init init_iommu_sysfs(void)
3153{
3154 int error;
3155
3156 error = sysdev_class_register(&iommu_sysclass);
3157 if (error)
3158 return error;
3159
3160 error = sysdev_register(&device_iommu);
3161 if (error)
3162 sysdev_class_unregister(&iommu_sysclass);
3163
3164 return error;
3165}
3166
3167#else
3168static int __init init_iommu_sysfs(void)
3169{
3170 return 0;
3171}
3172#endif /* CONFIG_PM */
3173
ba395927
KA		 3174int __init intel_iommu_init(void)
3175{
3176 int ret = 0;
3177
ba395927
KA		 3178 if (dmar_table_init())
3179 return -ENODEV;
3180
1886e8a9
SS		 3181 if (dmar_dev_scope_init())
3182 return -ENODEV;
3183
2ae21010
SS		 3184 /*
3185 * Check the need for DMA-remapping initialization now.
3186 * Above initialization will also be used by Interrupt-remapping.
3187 */
19943b0e 3188 if (no_iommu || swiotlb || dmar_disabled)
2ae21010
SS		 3189 return -ENODEV;
3190
ba395927
KA		 3191 iommu_init_mempool();
3192 dmar_init_reserved_ranges();
3193
3194 init_no_remapping_devices();
3195
3196 ret = init_dmars();
3197 if (ret) {
3198 printk(KERN_ERR "IOMMU: dmar init failed\n");
3199 put_iova_domain(&reserved_iova_list);
3200 iommu_exit_mempool();
3201 return ret;
3202 }
3203 printk(KERN_INFO
3204 "PCI-DMA: Intel(R) Virtualization Technology for Directed I/O\n");
3205
5e0d2a6f 3206 init_timer(&unmap_timer);
ba395927 3207 force_iommu = 1;
19943b0e 3208 dma_ops = &intel_dma_ops;
4ed0d3e6 3209
f59c7b69 3210 init_iommu_sysfs();
a8bcbb0d
JR		 3211
3212 register_iommu(&intel_iommu_ops);
3213
ba395927
KA		 3214 return 0;
3215}
e820482c 3216
3199aa6b
HW		 3217static void iommu_detach_dependent_devices(struct intel_iommu *iommu,
3218 struct pci_dev *pdev)
3219{
3220 struct pci_dev *tmp, *parent;
3221
3222 if (!iommu || !pdev)
3223 return;
3224
3225 /* dependent device detach */
3226 tmp = pci_find_upstream_pcie_bridge(pdev);
3227 /* Secondary interface's bus number and devfn 0 */
3228 if (tmp) {
3229 parent = pdev->bus->self;
3230 while (parent != tmp) {
3231 iommu_detach_dev(iommu, parent->bus->number,
276dbf99 3232 parent->devfn);
3199aa6b
HW		 3233 parent = parent->bus->self;
3234 }
3235 if (tmp->is_pcie) /* this is a PCIE-to-PCI bridge */
3236 iommu_detach_dev(iommu,
3237 tmp->subordinate->number, 0);
3238 else /* this is a legacy PCI bridge */
276dbf99
DW		 3239 iommu_detach_dev(iommu, tmp->bus->number,
3240 tmp->devfn);
3199aa6b
HW		 3241 }
3242}
3243
2c2e2c38 3244static void domain_remove_one_dev_info(struct dmar_domain *domain,
c7151a8d
WH		 3245 struct pci_dev *pdev)
3246{
3247 struct device_domain_info *info;
3248 struct intel_iommu *iommu;
3249 unsigned long flags;
3250 int found = 0;
3251 struct list_head *entry, *tmp;
3252
276dbf99
DW		 3253 iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
3254 pdev->devfn);
c7151a8d
WH		 3255 if (!iommu)
3256 return;
3257
3258 spin_lock_irqsave(&device_domain_lock, flags);
3259 list_for_each_safe(entry, tmp, &domain->devices) {
3260 info = list_entry(entry, struct device_domain_info, link);
276dbf99 3261 /* No need to compare PCI domain; it has to be the same */
c7151a8d
WH		 3262 if (info->bus == pdev->bus->number &&
3263 info->devfn == pdev->devfn) {
3264 list_del(&info->link);
3265 list_del(&info->global);
3266 if (info->dev)
3267 info->dev->dev.archdata.iommu = NULL;
3268 spin_unlock_irqrestore(&device_domain_lock, flags);
3269
93a23a72 3270 iommu_disable_dev_iotlb(info);
c7151a8d 3271 iommu_detach_dev(iommu, info->bus, info->devfn);
3199aa6b 3272 iommu_detach_dependent_devices(iommu, pdev);
c7151a8d
WH		 3273 free_devinfo_mem(info);
3274
3275 spin_lock_irqsave(&device_domain_lock, flags);
3276
3277 if (found)
3278 break;
3279 else
3280 continue;
3281 }
3282
3283 /* if there is no other devices under the same iommu
3284 * owned by this domain, clear this iommu in iommu_bmp
3285 * update iommu count and coherency
3286 */
276dbf99
DW		 3287 if (iommu == device_to_iommu(info->segment, info->bus,
3288 info->devfn))
c7151a8d
WH		 3289 found = 1;
3290 }
3291
3292 if (found == 0) {
3293 unsigned long tmp_flags;
3294 spin_lock_irqsave(&domain->iommu_lock, tmp_flags);
3295 clear_bit(iommu->seq_id, &domain->iommu_bmp);
3296 domain->iommu_count--;
58c610bd 3297 domain_update_iommu_cap(domain);
c7151a8d
WH		 3298 spin_unlock_irqrestore(&domain->iommu_lock, tmp_flags);
3299 }
3300
3301 spin_unlock_irqrestore(&device_domain_lock, flags);
3302}
3303
3304static void vm_domain_remove_all_dev_info(struct dmar_domain *domain)
3305{
3306 struct device_domain_info *info;
3307 struct intel_iommu *iommu;
3308 unsigned long flags1, flags2;
3309
3310 spin_lock_irqsave(&device_domain_lock, flags1);
3311 while (!list_empty(&domain->devices)) {
3312 info = list_entry(domain->devices.next,
3313 struct device_domain_info, link);
3314 list_del(&info->link);
3315 list_del(&info->global);
3316 if (info->dev)
3317 info->dev->dev.archdata.iommu = NULL;
3318
3319 spin_unlock_irqrestore(&device_domain_lock, flags1);
3320
93a23a72 3321 iommu_disable_dev_iotlb(info);
276dbf99 3322 iommu = device_to_iommu(info->segment, info->bus, info->devfn);
c7151a8d 3323 iommu_detach_dev(iommu, info->bus, info->devfn);
3199aa6b 3324 iommu_detach_dependent_devices(iommu, info->dev);
c7151a8d
WH		 3325
3326 /* clear this iommu in iommu_bmp, update iommu count
58c610bd 3327 * and capabilities
c7151a8d
WH		 3328 */
3329 spin_lock_irqsave(&domain->iommu_lock, flags2);
3330 if (test_and_clear_bit(iommu->seq_id,
3331 &domain->iommu_bmp)) {
3332 domain->iommu_count--;
58c610bd 3333 domain_update_iommu_cap(domain);
c7151a8d
WH		 3334 }
3335 spin_unlock_irqrestore(&domain->iommu_lock, flags2);
3336
3337 free_devinfo_mem(info);
3338 spin_lock_irqsave(&device_domain_lock, flags1);
3339 }
3340 spin_unlock_irqrestore(&device_domain_lock, flags1);
3341}
3342
5e98c4b1
WH		 3343/* domain id for virtual machine, it won't be set in context */
3344static unsigned long vm_domid;
3345
fe40f1e0
WH		 3346static int vm_domain_min_agaw(struct dmar_domain *domain)
3347{
3348 int i;
3349 int min_agaw = domain->agaw;
3350
3351 i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
3352 for (; i < g_num_of_iommus; ) {
3353 if (min_agaw > g_iommus[i]->agaw)
3354 min_agaw = g_iommus[i]->agaw;
3355
3356 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
3357 }
3358
3359 return min_agaw;
3360}
3361
5e98c4b1
WH		 3362static struct dmar_domain *iommu_alloc_vm_domain(void)
3363{
3364 struct dmar_domain *domain;
3365
3366 domain = alloc_domain_mem();
3367 if (!domain)
3368 return NULL;
3369
3370 domain->id = vm_domid++;
3371 memset(&domain->iommu_bmp, 0, sizeof(unsigned long));
3372 domain->flags = DOMAIN_FLAG_VIRTUAL_MACHINE;
3373
3374 return domain;
3375}
3376
2c2e2c38 3377static int md_domain_init(struct dmar_domain *domain, int guest_width)
5e98c4b1
WH		 3378{
3379 int adjust_width;
3380
3381 init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
5e98c4b1
WH		 3382 spin_lock_init(&domain->iommu_lock);
3383
3384 domain_reserve_special_ranges(domain);
3385
3386 /* calculate AGAW */
3387 domain->gaw = guest_width;
3388 adjust_width = guestwidth_to_adjustwidth(guest_width);
3389 domain->agaw = width_to_agaw(adjust_width);
3390
3391 INIT_LIST_HEAD(&domain->devices);
3392
3393 domain->iommu_count = 0;
3394 domain->iommu_coherency = 0;
c5b15255 3395 domain->iommu_snooping = 0;
fe40f1e0 3396 domain->max_addr = 0;
5e98c4b1
WH		 3397
3398 /* always allocate the top pgd */
3399 domain->pgd = (struct dma_pte *)alloc_pgtable_page();
3400 if (!domain->pgd)
3401 return -ENOMEM;
3402 domain_flush_cache(domain, domain->pgd, PAGE_SIZE);
3403 return 0;
3404}
3405
3406static void iommu_free_vm_domain(struct dmar_domain *domain)
3407{
3408 unsigned long flags;
3409 struct dmar_drhd_unit *drhd;
3410 struct intel_iommu *iommu;
3411 unsigned long i;
3412 unsigned long ndomains;
3413
3414 for_each_drhd_unit(drhd) {
3415 if (drhd->ignored)
3416 continue;
3417 iommu = drhd->iommu;
3418
3419 ndomains = cap_ndoms(iommu->cap);
3420 i = find_first_bit(iommu->domain_ids, ndomains);
3421 for (; i < ndomains; ) {
3422 if (iommu->domains[i] == domain) {
3423 spin_lock_irqsave(&iommu->lock, flags);
3424 clear_bit(i, iommu->domain_ids);
3425 iommu->domains[i] = NULL;
3426 spin_unlock_irqrestore(&iommu->lock, flags);
3427 break;
3428 }
3429 i = find_next_bit(iommu->domain_ids, ndomains, i+1);
3430 }
3431 }
3432}
3433
3434static void vm_domain_exit(struct dmar_domain *domain)
3435{
5e98c4b1
WH		 3436 /* Domain 0 is reserved, so dont process it */
3437 if (!domain)
3438 return;
3439
3440 vm_domain_remove_all_dev_info(domain);
3441 /* destroy iovas */
3442 put_iova_domain(&domain->iovad);
5e98c4b1
WH		 3443
3444 /* clear ptes */
595badf5 3445 dma_pte_clear_range(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
5e98c4b1
WH		 3446
3447 /* free page tables */
d794dc9b 3448 dma_pte_free_pagetable(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
5e98c4b1
WH		 3449
3450 iommu_free_vm_domain(domain);
3451 free_domain_mem(domain);
3452}
3453
5d450806 3454static int intel_iommu_domain_init(struct iommu_domain *domain)
38717946 3455{
5d450806 3456 struct dmar_domain *dmar_domain;
38717946 3457
5d450806
JR		 3458 dmar_domain = iommu_alloc_vm_domain();
3459 if (!dmar_domain) {
38717946 3460 printk(KERN_ERR
5d450806
JR		 3461 "intel_iommu_domain_init: dmar_domain == NULL\n");
3462 return -ENOMEM;
38717946 3463 }
2c2e2c38 3464 if (md_domain_init(dmar_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
38717946 3465 printk(KERN_ERR
5d450806
JR		 3466 "intel_iommu_domain_init() failed\n");
3467 vm_domain_exit(dmar_domain);
3468 return -ENOMEM;
38717946 3469 }
5d450806 3470 domain->priv = dmar_domain;
faa3d6f5 3471
5d450806 3472 return 0;
38717946 3473}
38717946 3474
5d450806 3475static void intel_iommu_domain_destroy(struct iommu_domain *domain)
38717946 3476{
5d450806
JR		 3477 struct dmar_domain *dmar_domain = domain->priv;
3478
3479 domain->priv = NULL;
3480 vm_domain_exit(dmar_domain);
38717946 3481}
38717946 3482
4c5478c9
JR		 3483static int intel_iommu_attach_device(struct iommu_domain *domain,
3484 struct device *dev)
38717946 3485{
4c5478c9
JR		 3486 struct dmar_domain *dmar_domain = domain->priv;
3487 struct pci_dev *pdev = to_pci_dev(dev);
fe40f1e0
WH		 3488 struct intel_iommu *iommu;
3489 int addr_width;
3490 u64 end;
faa3d6f5
WH		 3491
3492 /* normally pdev is not mapped */
3493 if (unlikely(domain_context_mapped(pdev))) {
3494 struct dmar_domain *old_domain;
3495
3496 old_domain = find_domain(pdev);
3497 if (old_domain) {
2c2e2c38
FY		 3498 if (dmar_domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
3499 dmar_domain->flags & DOMAIN_FLAG_STATIC_IDENTITY)
3500 domain_remove_one_dev_info(old_domain, pdev);
faa3d6f5
WH		 3501 else
3502 domain_remove_dev_info(old_domain);
3503 }
3504 }
3505
276dbf99
DW		 3506 iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
3507 pdev->devfn);
fe40f1e0
WH		 3508 if (!iommu)
3509 return -ENODEV;
3510
3511 /* check if this iommu agaw is sufficient for max mapped address */
3512 addr_width = agaw_to_width(iommu->agaw);
3513 end = DOMAIN_MAX_ADDR(addr_width);
3514 end = end & VTD_PAGE_MASK;
4c5478c9 3515 if (end < dmar_domain->max_addr) {
fe40f1e0
WH		 3516 printk(KERN_ERR "%s: iommu agaw (%d) is not "
3517 "sufficient for the mapped address (%llx)\n",
4c5478c9 3518 __func__, iommu->agaw, dmar_domain->max_addr);
fe40f1e0
WH		 3519 return -EFAULT;
3520 }
3521
5fe60f4e 3522 return domain_add_dev_info(dmar_domain, pdev, CONTEXT_TT_MULTI_LEVEL);
38717946 3523}
38717946 3524
4c5478c9
JR		 3525static void intel_iommu_detach_device(struct iommu_domain *domain,
3526 struct device *dev)
38717946 3527{
4c5478c9
JR		 3528 struct dmar_domain *dmar_domain = domain->priv;
3529 struct pci_dev *pdev = to_pci_dev(dev);
3530
2c2e2c38 3531 domain_remove_one_dev_info(dmar_domain, pdev);
faa3d6f5 3532}
c7151a8d 3533
dde57a21
JR		 3534static int intel_iommu_map_range(struct iommu_domain *domain,
3535 unsigned long iova, phys_addr_t hpa,
3536 size_t size, int iommu_prot)
faa3d6f5 3537{
dde57a21 3538 struct dmar_domain *dmar_domain = domain->priv;
fe40f1e0
WH		 3539 u64 max_addr;
3540 int addr_width;
dde57a21 3541 int prot = 0;
faa3d6f5 3542 int ret;
fe40f1e0 3543
dde57a21
JR		 3544 if (iommu_prot & IOMMU_READ)
3545 prot |= DMA_PTE_READ;
3546 if (iommu_prot & IOMMU_WRITE)
3547 prot |= DMA_PTE_WRITE;
9cf06697
SY		 3548 if ((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping)
3549 prot |= DMA_PTE_SNP;
dde57a21 3550
163cc52c 3551 max_addr = iova + size;
dde57a21 3552 if (dmar_domain->max_addr < max_addr) {
fe40f1e0
WH		 3553 int min_agaw;
3554 u64 end;
3555
3556 /* check if minimum agaw is sufficient for mapped address */
dde57a21 3557 min_agaw = vm_domain_min_agaw(dmar_domain);
fe40f1e0
WH		 3558 addr_width = agaw_to_width(min_agaw);
3559 end = DOMAIN_MAX_ADDR(addr_width);
3560 end = end & VTD_PAGE_MASK;
3561 if (end < max_addr) {
3562 printk(KERN_ERR "%s: iommu agaw (%d) is not "
3563 "sufficient for the mapped address (%llx)\n",
3564 __func__, min_agaw, max_addr);
3565 return -EFAULT;
3566 }
dde57a21 3567 dmar_domain->max_addr = max_addr;
fe40f1e0 3568 }
ad051221
DW		 3569 /* Round up size to next multiple of PAGE_SIZE, if it and
3570 the low bits of hpa would take us onto the next page */
88cb6a74 3571 size = aligned_nrpages(hpa, size);
ad051221
DW		 3572 ret = domain_pfn_mapping(dmar_domain, iova >> VTD_PAGE_SHIFT,
3573 hpa >> VTD_PAGE_SHIFT, size, prot);
faa3d6f5 3574 return ret;
38717946 3575}
38717946 3576
dde57a21
JR		 3577static void intel_iommu_unmap_range(struct iommu_domain *domain,
3578 unsigned long iova, size_t size)
38717946 3579{
dde57a21 3580 struct dmar_domain *dmar_domain = domain->priv;
faa3d6f5 3581
4b99d352
SY		 3582 if (!size)
3583 return;
3584
163cc52c
DW		 3585 dma_pte_clear_range(dmar_domain, iova >> VTD_PAGE_SHIFT,
3586 (iova + size - 1) >> VTD_PAGE_SHIFT);
fe40f1e0 3587
163cc52c
DW		 3588 if (dmar_domain->max_addr == iova + size)
3589 dmar_domain->max_addr = iova;
38717946 3590}
38717946 3591
d14d6577
JR		 3592static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain,
3593 unsigned long iova)
38717946 3594{
d14d6577 3595 struct dmar_domain *dmar_domain = domain->priv;
38717946 3596 struct dma_pte *pte;
faa3d6f5 3597 u64 phys = 0;
38717946 3598
b026fd28 3599 pte = pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT);
38717946 3600 if (pte)
faa3d6f5 3601 phys = dma_pte_addr(pte);
38717946 3602
faa3d6f5 3603 return phys;
38717946 3604}
a8bcbb0d 3605
dbb9fd86
SY		 3606static int intel_iommu_domain_has_cap(struct iommu_domain *domain,
3607 unsigned long cap)
3608{
3609 struct dmar_domain *dmar_domain = domain->priv;
3610
3611 if (cap == IOMMU_CAP_CACHE_COHERENCY)
3612 return dmar_domain->iommu_snooping;
3613
3614 return 0;
3615}
3616
a8bcbb0d
JR		 3617static struct iommu_ops intel_iommu_ops = {
3618 .domain_init = intel_iommu_domain_init,
3619 .domain_destroy = intel_iommu_domain_destroy,
3620 .attach_dev = intel_iommu_attach_device,
3621 .detach_dev = intel_iommu_detach_device,
3622 .map = intel_iommu_map_range,
3623 .unmap = intel_iommu_unmap_range,
3624 .iova_to_phys = intel_iommu_iova_to_phys,
dbb9fd86 3625 .domain_has_cap = intel_iommu_domain_has_cap,
a8bcbb0d 3626};
9af88143
DW		 3627
3628static void __devinit quirk_iommu_rwbf(struct pci_dev *dev)
3629{
3630 /*
3631 * Mobile 4 Series Chipset neglects to set RWBF capability,
3632 * but needs it:
3633 */
3634 printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n");
3635 rwbf_quirk = 1;
3636}
3637
3638DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);
Linux kernel - Deliverables
This page took 0.460606 seconds and 5 git commands to generate.