Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * PCI Bus Services, see include/linux/pci.h for further explanation. |
3 | * | |
4 | * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, | |
5 | * David Mosberger-Tang | |
6 | * | |
7 | * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz> | |
8 | */ | |
9 | ||
10 | #include <linux/kernel.h> | |
11 | #include <linux/delay.h> | |
12 | #include <linux/init.h> | |
7c674700 LP |
13 | #include <linux/of.h> |
14 | #include <linux/of_pci.h> | |
1da177e4 | 15 | #include <linux/pci.h> |
075c1771 | 16 | #include <linux/pm.h> |
5a0e3ad6 | 17 | #include <linux/slab.h> |
1da177e4 LT |
18 | #include <linux/module.h> |
19 | #include <linux/spinlock.h> | |
4e57b681 | 20 | #include <linux/string.h> |
229f5afd | 21 | #include <linux/log2.h> |
7d715a6c | 22 | #include <linux/pci-aspm.h> |
c300bd2f | 23 | #include <linux/pm_wakeup.h> |
8dd7f803 | 24 | #include <linux/interrupt.h> |
32a9a682 | 25 | #include <linux/device.h> |
b67ea761 | 26 | #include <linux/pm_runtime.h> |
608c3881 | 27 | #include <linux/pci_hotplug.h> |
284f5f9d | 28 | #include <asm-generic/pci-bridge.h> |
32a9a682 | 29 | #include <asm/setup.h> |
bc56b9e0 | 30 | #include "pci.h" |
1da177e4 | 31 | |
00240c38 AS |
32 | const char *pci_power_names[] = { |
33 | "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown", | |
34 | }; | |
35 | EXPORT_SYMBOL_GPL(pci_power_names); | |
36 | ||
93177a74 RW |
37 | int isa_dma_bridge_buggy; |
38 | EXPORT_SYMBOL(isa_dma_bridge_buggy); | |
39 | ||
40 | int pci_pci_problems; | |
41 | EXPORT_SYMBOL(pci_pci_problems); | |
42 | ||
1ae861e6 RW |
43 | unsigned int pci_pm_d3_delay; |
44 | ||
df17e62e MG |
45 | static void pci_pme_list_scan(struct work_struct *work); |
46 | ||
47 | static LIST_HEAD(pci_pme_list); | |
48 | static DEFINE_MUTEX(pci_pme_list_mutex); | |
49 | static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan); | |
50 | ||
51 | struct pci_pme_device { | |
52 | struct list_head list; | |
53 | struct pci_dev *dev; | |
54 | }; | |
55 | ||
56 | #define PME_TIMEOUT 1000 /* How long between PME checks */ | |
57 | ||
1ae861e6 RW |
58 | static void pci_dev_d3_sleep(struct pci_dev *dev) |
59 | { | |
60 | unsigned int delay = dev->d3_delay; | |
61 | ||
62 | if (delay < pci_pm_d3_delay) | |
63 | delay = pci_pm_d3_delay; | |
64 | ||
65 | msleep(delay); | |
66 | } | |
1da177e4 | 67 | |
32a2eea7 JG |
68 | #ifdef CONFIG_PCI_DOMAINS |
69 | int pci_domains_supported = 1; | |
70 | #endif | |
71 | ||
4516a618 AN |
72 | #define DEFAULT_CARDBUS_IO_SIZE (256) |
73 | #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024) | |
74 | /* pci=cbmemsize=nnM,cbiosize=nn can override this */ | |
75 | unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE; | |
76 | unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE; | |
77 | ||
28760489 EB |
78 | #define DEFAULT_HOTPLUG_IO_SIZE (256) |
79 | #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024) | |
80 | /* pci=hpmemsize=nnM,hpiosize=nn can override this */ | |
81 | unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE; | |
82 | unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE; | |
83 | ||
5f39e670 | 84 | enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF; |
b03e7495 | 85 | |
ac1aa47b JB |
86 | /* |
87 | * The default CLS is used if arch didn't set CLS explicitly and not | |
88 | * all pci devices agree on the same value. Arch can override either | |
89 | * the dfl or actual value as it sees fit. Don't forget this is | |
90 | * measured in 32-bit words, not bytes. | |
91 | */ | |
15856ad5 | 92 | u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2; |
ac1aa47b JB |
93 | u8 pci_cache_line_size; |
94 | ||
96c55900 MS |
95 | /* |
96 | * If we set up a device for bus mastering, we need to check the latency | |
97 | * timer as certain BIOSes forget to set it properly. | |
98 | */ | |
99 | unsigned int pcibios_max_latency = 255; | |
100 | ||
6748dcc2 RW |
101 | /* If set, the PCIe ARI capability will not be used. */ |
102 | static bool pcie_ari_disabled; | |
103 | ||
1da177e4 LT |
104 | /** |
105 | * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children | |
106 | * @bus: pointer to PCI bus structure to search | |
107 | * | |
108 | * Given a PCI bus, returns the highest PCI bus number present in the set | |
109 | * including the given PCI bus and its list of child PCI buses. | |
110 | */ | |
07656d83 | 111 | unsigned char pci_bus_max_busnr(struct pci_bus *bus) |
1da177e4 | 112 | { |
94e6a9b9 | 113 | struct pci_bus *tmp; |
1da177e4 LT |
114 | unsigned char max, n; |
115 | ||
b918c62e | 116 | max = bus->busn_res.end; |
94e6a9b9 YW |
117 | list_for_each_entry(tmp, &bus->children, node) { |
118 | n = pci_bus_max_busnr(tmp); | |
3c78bc61 | 119 | if (n > max) |
1da177e4 LT |
120 | max = n; |
121 | } | |
122 | return max; | |
123 | } | |
b82db5ce | 124 | EXPORT_SYMBOL_GPL(pci_bus_max_busnr); |
1da177e4 | 125 | |
1684f5dd AM |
126 | #ifdef CONFIG_HAS_IOMEM |
127 | void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar) | |
128 | { | |
129 | /* | |
130 | * Make sure the BAR is actually a memory resource, not an IO resource | |
131 | */ | |
132 | if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { | |
133 | WARN_ON(1); | |
134 | return NULL; | |
135 | } | |
136 | return ioremap_nocache(pci_resource_start(pdev, bar), | |
137 | pci_resource_len(pdev, bar)); | |
138 | } | |
139 | EXPORT_SYMBOL_GPL(pci_ioremap_bar); | |
140 | #endif | |
141 | ||
687d5fe3 ME |
142 | #define PCI_FIND_CAP_TTL 48 |
143 | ||
144 | static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, | |
145 | u8 pos, int cap, int *ttl) | |
24a4e377 RD |
146 | { |
147 | u8 id; | |
24a4e377 | 148 | |
687d5fe3 | 149 | while ((*ttl)--) { |
24a4e377 RD |
150 | pci_bus_read_config_byte(bus, devfn, pos, &pos); |
151 | if (pos < 0x40) | |
152 | break; | |
153 | pos &= ~3; | |
154 | pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID, | |
155 | &id); | |
156 | if (id == 0xff) | |
157 | break; | |
158 | if (id == cap) | |
159 | return pos; | |
160 | pos += PCI_CAP_LIST_NEXT; | |
161 | } | |
162 | return 0; | |
163 | } | |
164 | ||
687d5fe3 ME |
165 | static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, |
166 | u8 pos, int cap) | |
167 | { | |
168 | int ttl = PCI_FIND_CAP_TTL; | |
169 | ||
170 | return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl); | |
171 | } | |
172 | ||
24a4e377 RD |
173 | int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) |
174 | { | |
175 | return __pci_find_next_cap(dev->bus, dev->devfn, | |
176 | pos + PCI_CAP_LIST_NEXT, cap); | |
177 | } | |
178 | EXPORT_SYMBOL_GPL(pci_find_next_capability); | |
179 | ||
d3bac118 ME |
180 | static int __pci_bus_find_cap_start(struct pci_bus *bus, |
181 | unsigned int devfn, u8 hdr_type) | |
1da177e4 LT |
182 | { |
183 | u16 status; | |
1da177e4 LT |
184 | |
185 | pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status); | |
186 | if (!(status & PCI_STATUS_CAP_LIST)) | |
187 | return 0; | |
188 | ||
189 | switch (hdr_type) { | |
190 | case PCI_HEADER_TYPE_NORMAL: | |
191 | case PCI_HEADER_TYPE_BRIDGE: | |
d3bac118 | 192 | return PCI_CAPABILITY_LIST; |
1da177e4 | 193 | case PCI_HEADER_TYPE_CARDBUS: |
d3bac118 | 194 | return PCI_CB_CAPABILITY_LIST; |
1da177e4 LT |
195 | default: |
196 | return 0; | |
197 | } | |
d3bac118 ME |
198 | |
199 | return 0; | |
1da177e4 LT |
200 | } |
201 | ||
202 | /** | |
f7625980 | 203 | * pci_find_capability - query for devices' capabilities |
1da177e4 LT |
204 | * @dev: PCI device to query |
205 | * @cap: capability code | |
206 | * | |
207 | * Tell if a device supports a given PCI capability. | |
208 | * Returns the address of the requested capability structure within the | |
209 | * device's PCI configuration space or 0 in case the device does not | |
210 | * support it. Possible values for @cap: | |
211 | * | |
f7625980 BH |
212 | * %PCI_CAP_ID_PM Power Management |
213 | * %PCI_CAP_ID_AGP Accelerated Graphics Port | |
214 | * %PCI_CAP_ID_VPD Vital Product Data | |
215 | * %PCI_CAP_ID_SLOTID Slot Identification | |
1da177e4 | 216 | * %PCI_CAP_ID_MSI Message Signalled Interrupts |
f7625980 | 217 | * %PCI_CAP_ID_CHSWP CompactPCI HotSwap |
1da177e4 LT |
218 | * %PCI_CAP_ID_PCIX PCI-X |
219 | * %PCI_CAP_ID_EXP PCI Express | |
220 | */ | |
221 | int pci_find_capability(struct pci_dev *dev, int cap) | |
222 | { | |
d3bac118 ME |
223 | int pos; |
224 | ||
225 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); | |
226 | if (pos) | |
227 | pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap); | |
228 | ||
229 | return pos; | |
1da177e4 | 230 | } |
b7fe9434 | 231 | EXPORT_SYMBOL(pci_find_capability); |
1da177e4 LT |
232 | |
233 | /** | |
f7625980 | 234 | * pci_bus_find_capability - query for devices' capabilities |
1da177e4 LT |
235 | * @bus: the PCI bus to query |
236 | * @devfn: PCI device to query | |
237 | * @cap: capability code | |
238 | * | |
239 | * Like pci_find_capability() but works for pci devices that do not have a | |
f7625980 | 240 | * pci_dev structure set up yet. |
1da177e4 LT |
241 | * |
242 | * Returns the address of the requested capability structure within the | |
243 | * device's PCI configuration space or 0 in case the device does not | |
244 | * support it. | |
245 | */ | |
246 | int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) | |
247 | { | |
d3bac118 | 248 | int pos; |
1da177e4 LT |
249 | u8 hdr_type; |
250 | ||
251 | pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type); | |
252 | ||
d3bac118 ME |
253 | pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f); |
254 | if (pos) | |
255 | pos = __pci_find_next_cap(bus, devfn, pos, cap); | |
256 | ||
257 | return pos; | |
1da177e4 | 258 | } |
b7fe9434 | 259 | EXPORT_SYMBOL(pci_bus_find_capability); |
1da177e4 LT |
260 | |
261 | /** | |
44a9a36f | 262 | * pci_find_next_ext_capability - Find an extended capability |
1da177e4 | 263 | * @dev: PCI device to query |
44a9a36f | 264 | * @start: address at which to start looking (0 to start at beginning of list) |
1da177e4 LT |
265 | * @cap: capability code |
266 | * | |
44a9a36f | 267 | * Returns the address of the next matching extended capability structure |
1da177e4 | 268 | * within the device's PCI configuration space or 0 if the device does |
44a9a36f BH |
269 | * not support it. Some capabilities can occur several times, e.g., the |
270 | * vendor-specific capability, and this provides a way to find them all. | |
1da177e4 | 271 | */ |
44a9a36f | 272 | int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap) |
1da177e4 LT |
273 | { |
274 | u32 header; | |
557848c3 ZY |
275 | int ttl; |
276 | int pos = PCI_CFG_SPACE_SIZE; | |
1da177e4 | 277 | |
557848c3 ZY |
278 | /* minimum 8 bytes per capability */ |
279 | ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; | |
280 | ||
281 | if (dev->cfg_size <= PCI_CFG_SPACE_SIZE) | |
1da177e4 LT |
282 | return 0; |
283 | ||
44a9a36f BH |
284 | if (start) |
285 | pos = start; | |
286 | ||
1da177e4 LT |
287 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) |
288 | return 0; | |
289 | ||
290 | /* | |
291 | * If we have no capabilities, this is indicated by cap ID, | |
292 | * cap version and next pointer all being 0. | |
293 | */ | |
294 | if (header == 0) | |
295 | return 0; | |
296 | ||
297 | while (ttl-- > 0) { | |
44a9a36f | 298 | if (PCI_EXT_CAP_ID(header) == cap && pos != start) |
1da177e4 LT |
299 | return pos; |
300 | ||
301 | pos = PCI_EXT_CAP_NEXT(header); | |
557848c3 | 302 | if (pos < PCI_CFG_SPACE_SIZE) |
1da177e4 LT |
303 | break; |
304 | ||
305 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) | |
306 | break; | |
307 | } | |
308 | ||
309 | return 0; | |
310 | } | |
44a9a36f BH |
311 | EXPORT_SYMBOL_GPL(pci_find_next_ext_capability); |
312 | ||
313 | /** | |
314 | * pci_find_ext_capability - Find an extended capability | |
315 | * @dev: PCI device to query | |
316 | * @cap: capability code | |
317 | * | |
318 | * Returns the address of the requested extended capability structure | |
319 | * within the device's PCI configuration space or 0 if the device does | |
320 | * not support it. Possible values for @cap: | |
321 | * | |
322 | * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting | |
323 | * %PCI_EXT_CAP_ID_VC Virtual Channel | |
324 | * %PCI_EXT_CAP_ID_DSN Device Serial Number | |
325 | * %PCI_EXT_CAP_ID_PWR Power Budgeting | |
326 | */ | |
327 | int pci_find_ext_capability(struct pci_dev *dev, int cap) | |
328 | { | |
329 | return pci_find_next_ext_capability(dev, 0, cap); | |
330 | } | |
3a720d72 | 331 | EXPORT_SYMBOL_GPL(pci_find_ext_capability); |
1da177e4 | 332 | |
687d5fe3 ME |
333 | static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap) |
334 | { | |
335 | int rc, ttl = PCI_FIND_CAP_TTL; | |
336 | u8 cap, mask; | |
337 | ||
338 | if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST) | |
339 | mask = HT_3BIT_CAP_MASK; | |
340 | else | |
341 | mask = HT_5BIT_CAP_MASK; | |
342 | ||
343 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos, | |
344 | PCI_CAP_ID_HT, &ttl); | |
345 | while (pos) { | |
346 | rc = pci_read_config_byte(dev, pos + 3, &cap); | |
347 | if (rc != PCIBIOS_SUCCESSFUL) | |
348 | return 0; | |
349 | ||
350 | if ((cap & mask) == ht_cap) | |
351 | return pos; | |
352 | ||
47a4d5be BG |
353 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, |
354 | pos + PCI_CAP_LIST_NEXT, | |
687d5fe3 ME |
355 | PCI_CAP_ID_HT, &ttl); |
356 | } | |
357 | ||
358 | return 0; | |
359 | } | |
360 | /** | |
361 | * pci_find_next_ht_capability - query a device's Hypertransport capabilities | |
362 | * @dev: PCI device to query | |
363 | * @pos: Position from which to continue searching | |
364 | * @ht_cap: Hypertransport capability code | |
365 | * | |
366 | * To be used in conjunction with pci_find_ht_capability() to search for | |
367 | * all capabilities matching @ht_cap. @pos should always be a value returned | |
368 | * from pci_find_ht_capability(). | |
369 | * | |
370 | * NB. To be 100% safe against broken PCI devices, the caller should take | |
371 | * steps to avoid an infinite loop. | |
372 | */ | |
373 | int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap) | |
374 | { | |
375 | return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap); | |
376 | } | |
377 | EXPORT_SYMBOL_GPL(pci_find_next_ht_capability); | |
378 | ||
379 | /** | |
380 | * pci_find_ht_capability - query a device's Hypertransport capabilities | |
381 | * @dev: PCI device to query | |
382 | * @ht_cap: Hypertransport capability code | |
383 | * | |
384 | * Tell if a device supports a given Hypertransport capability. | |
385 | * Returns an address within the device's PCI configuration space | |
386 | * or 0 in case the device does not support the request capability. | |
387 | * The address points to the PCI capability, of type PCI_CAP_ID_HT, | |
388 | * which has a Hypertransport capability matching @ht_cap. | |
389 | */ | |
390 | int pci_find_ht_capability(struct pci_dev *dev, int ht_cap) | |
391 | { | |
392 | int pos; | |
393 | ||
394 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); | |
395 | if (pos) | |
396 | pos = __pci_find_next_ht_cap(dev, pos, ht_cap); | |
397 | ||
398 | return pos; | |
399 | } | |
400 | EXPORT_SYMBOL_GPL(pci_find_ht_capability); | |
401 | ||
1da177e4 LT |
402 | /** |
403 | * pci_find_parent_resource - return resource region of parent bus of given region | |
404 | * @dev: PCI device structure contains resources to be searched | |
405 | * @res: child resource record for which parent is sought | |
406 | * | |
407 | * For given resource region of given device, return the resource | |
f44116ae | 408 | * region of parent bus the given region is contained in. |
1da177e4 | 409 | */ |
3c78bc61 RD |
410 | struct resource *pci_find_parent_resource(const struct pci_dev *dev, |
411 | struct resource *res) | |
1da177e4 LT |
412 | { |
413 | const struct pci_bus *bus = dev->bus; | |
f44116ae | 414 | struct resource *r; |
1da177e4 | 415 | int i; |
1da177e4 | 416 | |
89a74ecc | 417 | pci_bus_for_each_resource(bus, r, i) { |
1da177e4 LT |
418 | if (!r) |
419 | continue; | |
f44116ae BH |
420 | if (res->start && resource_contains(r, res)) { |
421 | ||
422 | /* | |
423 | * If the window is prefetchable but the BAR is | |
424 | * not, the allocator made a mistake. | |
425 | */ | |
426 | if (r->flags & IORESOURCE_PREFETCH && | |
427 | !(res->flags & IORESOURCE_PREFETCH)) | |
428 | return NULL; | |
429 | ||
430 | /* | |
431 | * If we're below a transparent bridge, there may | |
432 | * be both a positively-decoded aperture and a | |
433 | * subtractively-decoded region that contain the BAR. | |
434 | * We want the positively-decoded one, so this depends | |
435 | * on pci_bus_for_each_resource() giving us those | |
436 | * first. | |
437 | */ | |
438 | return r; | |
439 | } | |
1da177e4 | 440 | } |
f44116ae | 441 | return NULL; |
1da177e4 | 442 | } |
b7fe9434 | 443 | EXPORT_SYMBOL(pci_find_parent_resource); |
1da177e4 | 444 | |
157e876f AW |
445 | /** |
446 | * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos | |
447 | * @dev: the PCI device to operate on | |
448 | * @pos: config space offset of status word | |
449 | * @mask: mask of bit(s) to care about in status word | |
450 | * | |
451 | * Return 1 when mask bit(s) in status word clear, 0 otherwise. | |
452 | */ | |
453 | int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask) | |
454 | { | |
455 | int i; | |
456 | ||
457 | /* Wait for Transaction Pending bit clean */ | |
458 | for (i = 0; i < 4; i++) { | |
459 | u16 status; | |
460 | if (i) | |
461 | msleep((1 << (i - 1)) * 100); | |
462 | ||
463 | pci_read_config_word(dev, pos, &status); | |
464 | if (!(status & mask)) | |
465 | return 1; | |
466 | } | |
467 | ||
468 | return 0; | |
469 | } | |
470 | ||
064b53db JL |
471 | /** |
472 | * pci_restore_bars - restore a devices BAR values (e.g. after wake-up) | |
473 | * @dev: PCI device to have its BARs restored | |
474 | * | |
475 | * Restore the BAR values for a given device, so as to make it | |
476 | * accessible by its driver. | |
477 | */ | |
3c78bc61 | 478 | static void pci_restore_bars(struct pci_dev *dev) |
064b53db | 479 | { |
bc5f5a82 | 480 | int i; |
064b53db | 481 | |
bc5f5a82 | 482 | for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) |
14add80b | 483 | pci_update_resource(dev, i); |
064b53db JL |
484 | } |
485 | ||
961d9120 RW |
486 | static struct pci_platform_pm_ops *pci_platform_pm; |
487 | ||
488 | int pci_set_platform_pm(struct pci_platform_pm_ops *ops) | |
489 | { | |
eb9d0fe4 | 490 | if (!ops->is_manageable || !ops->set_state || !ops->choose_state |
d2e5f0c1 | 491 | || !ops->sleep_wake) |
961d9120 RW |
492 | return -EINVAL; |
493 | pci_platform_pm = ops; | |
494 | return 0; | |
495 | } | |
496 | ||
497 | static inline bool platform_pci_power_manageable(struct pci_dev *dev) | |
498 | { | |
499 | return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false; | |
500 | } | |
501 | ||
502 | static inline int platform_pci_set_power_state(struct pci_dev *dev, | |
3c78bc61 | 503 | pci_power_t t) |
961d9120 RW |
504 | { |
505 | return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS; | |
506 | } | |
507 | ||
508 | static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev) | |
509 | { | |
510 | return pci_platform_pm ? | |
511 | pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR; | |
512 | } | |
8f7020d3 | 513 | |
eb9d0fe4 RW |
514 | static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable) |
515 | { | |
516 | return pci_platform_pm ? | |
517 | pci_platform_pm->sleep_wake(dev, enable) : -ENODEV; | |
518 | } | |
519 | ||
b67ea761 RW |
520 | static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable) |
521 | { | |
522 | return pci_platform_pm ? | |
523 | pci_platform_pm->run_wake(dev, enable) : -ENODEV; | |
524 | } | |
525 | ||
bac2a909 RW |
526 | static inline bool platform_pci_need_resume(struct pci_dev *dev) |
527 | { | |
528 | return pci_platform_pm ? pci_platform_pm->need_resume(dev) : false; | |
529 | } | |
530 | ||
1da177e4 | 531 | /** |
44e4e66e RW |
532 | * pci_raw_set_power_state - Use PCI PM registers to set the power state of |
533 | * given PCI device | |
534 | * @dev: PCI device to handle. | |
44e4e66e | 535 | * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. |
1da177e4 | 536 | * |
44e4e66e RW |
537 | * RETURN VALUE: |
538 | * -EINVAL if the requested state is invalid. | |
539 | * -EIO if device does not support PCI PM or its PM capabilities register has a | |
540 | * wrong version, or device doesn't support the requested state. | |
541 | * 0 if device already is in the requested state. | |
542 | * 0 if device's power state has been successfully changed. | |
1da177e4 | 543 | */ |
f00a20ef | 544 | static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state) |
1da177e4 | 545 | { |
337001b6 | 546 | u16 pmcsr; |
44e4e66e | 547 | bool need_restore = false; |
1da177e4 | 548 | |
4a865905 RW |
549 | /* Check if we're already there */ |
550 | if (dev->current_state == state) | |
551 | return 0; | |
552 | ||
337001b6 | 553 | if (!dev->pm_cap) |
cca03dec AL |
554 | return -EIO; |
555 | ||
44e4e66e RW |
556 | if (state < PCI_D0 || state > PCI_D3hot) |
557 | return -EINVAL; | |
558 | ||
1da177e4 | 559 | /* Validate current state: |
f7625980 | 560 | * Can enter D0 from any state, but if we can only go deeper |
1da177e4 LT |
561 | * to sleep if we're already in a low power state |
562 | */ | |
4a865905 | 563 | if (state != PCI_D0 && dev->current_state <= PCI_D3cold |
44e4e66e | 564 | && dev->current_state > state) { |
227f0647 RD |
565 | dev_err(&dev->dev, "invalid power transition (from state %d to %d)\n", |
566 | dev->current_state, state); | |
1da177e4 | 567 | return -EINVAL; |
44e4e66e | 568 | } |
1da177e4 | 569 | |
1da177e4 | 570 | /* check if this device supports the desired state */ |
337001b6 RW |
571 | if ((state == PCI_D1 && !dev->d1_support) |
572 | || (state == PCI_D2 && !dev->d2_support)) | |
3fe9d19f | 573 | return -EIO; |
1da177e4 | 574 | |
337001b6 | 575 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
064b53db | 576 | |
32a36585 | 577 | /* If we're (effectively) in D3, force entire word to 0. |
1da177e4 LT |
578 | * This doesn't affect PME_Status, disables PME_En, and |
579 | * sets PowerState to 0. | |
580 | */ | |
32a36585 | 581 | switch (dev->current_state) { |
d3535fbb JL |
582 | case PCI_D0: |
583 | case PCI_D1: | |
584 | case PCI_D2: | |
585 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | |
586 | pmcsr |= state; | |
587 | break; | |
f62795f1 RW |
588 | case PCI_D3hot: |
589 | case PCI_D3cold: | |
32a36585 JL |
590 | case PCI_UNKNOWN: /* Boot-up */ |
591 | if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot | |
f00a20ef | 592 | && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) |
44e4e66e | 593 | need_restore = true; |
32a36585 | 594 | /* Fall-through: force to D0 */ |
32a36585 | 595 | default: |
d3535fbb | 596 | pmcsr = 0; |
32a36585 | 597 | break; |
1da177e4 LT |
598 | } |
599 | ||
600 | /* enter specified state */ | |
337001b6 | 601 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); |
1da177e4 LT |
602 | |
603 | /* Mandatory power management transition delays */ | |
604 | /* see PCI PM 1.1 5.6.1 table 18 */ | |
605 | if (state == PCI_D3hot || dev->current_state == PCI_D3hot) | |
1ae861e6 | 606 | pci_dev_d3_sleep(dev); |
1da177e4 | 607 | else if (state == PCI_D2 || dev->current_state == PCI_D2) |
aa8c6c93 | 608 | udelay(PCI_PM_D2_DELAY); |
1da177e4 | 609 | |
e13cdbd7 RW |
610 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
611 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); | |
612 | if (dev->current_state != state && printk_ratelimit()) | |
227f0647 RD |
613 | dev_info(&dev->dev, "Refused to change power state, currently in D%d\n", |
614 | dev->current_state); | |
064b53db | 615 | |
448bd857 HY |
616 | /* |
617 | * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT | |
064b53db JL |
618 | * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning |
619 | * from D3hot to D0 _may_ perform an internal reset, thereby | |
620 | * going to "D0 Uninitialized" rather than "D0 Initialized". | |
621 | * For example, at least some versions of the 3c905B and the | |
622 | * 3c556B exhibit this behaviour. | |
623 | * | |
624 | * At least some laptop BIOSen (e.g. the Thinkpad T21) leave | |
625 | * devices in a D3hot state at boot. Consequently, we need to | |
626 | * restore at least the BARs so that the device will be | |
627 | * accessible to its driver. | |
628 | */ | |
629 | if (need_restore) | |
630 | pci_restore_bars(dev); | |
631 | ||
f00a20ef | 632 | if (dev->bus->self) |
7d715a6c SL |
633 | pcie_aspm_pm_state_change(dev->bus->self); |
634 | ||
1da177e4 LT |
635 | return 0; |
636 | } | |
637 | ||
44e4e66e RW |
638 | /** |
639 | * pci_update_current_state - Read PCI power state of given device from its | |
640 | * PCI PM registers and cache it | |
641 | * @dev: PCI device to handle. | |
f06fc0b6 | 642 | * @state: State to cache in case the device doesn't have the PM capability |
44e4e66e | 643 | */ |
73410429 | 644 | void pci_update_current_state(struct pci_dev *dev, pci_power_t state) |
44e4e66e | 645 | { |
337001b6 | 646 | if (dev->pm_cap) { |
44e4e66e RW |
647 | u16 pmcsr; |
648 | ||
448bd857 HY |
649 | /* |
650 | * Configuration space is not accessible for device in | |
651 | * D3cold, so just keep or set D3cold for safety | |
652 | */ | |
653 | if (dev->current_state == PCI_D3cold) | |
654 | return; | |
655 | if (state == PCI_D3cold) { | |
656 | dev->current_state = PCI_D3cold; | |
657 | return; | |
658 | } | |
337001b6 | 659 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
44e4e66e | 660 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); |
f06fc0b6 RW |
661 | } else { |
662 | dev->current_state = state; | |
44e4e66e RW |
663 | } |
664 | } | |
665 | ||
db288c9c RW |
666 | /** |
667 | * pci_power_up - Put the given device into D0 forcibly | |
668 | * @dev: PCI device to power up | |
669 | */ | |
670 | void pci_power_up(struct pci_dev *dev) | |
671 | { | |
672 | if (platform_pci_power_manageable(dev)) | |
673 | platform_pci_set_power_state(dev, PCI_D0); | |
674 | ||
675 | pci_raw_set_power_state(dev, PCI_D0); | |
676 | pci_update_current_state(dev, PCI_D0); | |
677 | } | |
678 | ||
0e5dd46b RW |
679 | /** |
680 | * pci_platform_power_transition - Use platform to change device power state | |
681 | * @dev: PCI device to handle. | |
682 | * @state: State to put the device into. | |
683 | */ | |
684 | static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state) | |
685 | { | |
686 | int error; | |
687 | ||
688 | if (platform_pci_power_manageable(dev)) { | |
689 | error = platform_pci_set_power_state(dev, state); | |
690 | if (!error) | |
691 | pci_update_current_state(dev, state); | |
769ba721 | 692 | } else |
0e5dd46b | 693 | error = -ENODEV; |
769ba721 RW |
694 | |
695 | if (error && !dev->pm_cap) /* Fall back to PCI_D0 */ | |
696 | dev->current_state = PCI_D0; | |
0e5dd46b RW |
697 | |
698 | return error; | |
699 | } | |
700 | ||
0b950f0f SH |
701 | /** |
702 | * pci_wakeup - Wake up a PCI device | |
703 | * @pci_dev: Device to handle. | |
704 | * @ign: ignored parameter | |
705 | */ | |
706 | static int pci_wakeup(struct pci_dev *pci_dev, void *ign) | |
707 | { | |
708 | pci_wakeup_event(pci_dev); | |
709 | pm_request_resume(&pci_dev->dev); | |
710 | return 0; | |
711 | } | |
712 | ||
713 | /** | |
714 | * pci_wakeup_bus - Walk given bus and wake up devices on it | |
715 | * @bus: Top bus of the subtree to walk. | |
716 | */ | |
717 | static void pci_wakeup_bus(struct pci_bus *bus) | |
718 | { | |
719 | if (bus) | |
720 | pci_walk_bus(bus, pci_wakeup, NULL); | |
721 | } | |
722 | ||
0e5dd46b RW |
723 | /** |
724 | * __pci_start_power_transition - Start power transition of a PCI device | |
725 | * @dev: PCI device to handle. | |
726 | * @state: State to put the device into. | |
727 | */ | |
728 | static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state) | |
729 | { | |
448bd857 | 730 | if (state == PCI_D0) { |
0e5dd46b | 731 | pci_platform_power_transition(dev, PCI_D0); |
448bd857 HY |
732 | /* |
733 | * Mandatory power management transition delays, see | |
734 | * PCI Express Base Specification Revision 2.0 Section | |
735 | * 6.6.1: Conventional Reset. Do not delay for | |
736 | * devices powered on/off by corresponding bridge, | |
737 | * because have already delayed for the bridge. | |
738 | */ | |
739 | if (dev->runtime_d3cold) { | |
740 | msleep(dev->d3cold_delay); | |
741 | /* | |
742 | * When powering on a bridge from D3cold, the | |
743 | * whole hierarchy may be powered on into | |
744 | * D0uninitialized state, resume them to give | |
745 | * them a chance to suspend again | |
746 | */ | |
747 | pci_wakeup_bus(dev->subordinate); | |
748 | } | |
749 | } | |
750 | } | |
751 | ||
752 | /** | |
753 | * __pci_dev_set_current_state - Set current state of a PCI device | |
754 | * @dev: Device to handle | |
755 | * @data: pointer to state to be set | |
756 | */ | |
757 | static int __pci_dev_set_current_state(struct pci_dev *dev, void *data) | |
758 | { | |
759 | pci_power_t state = *(pci_power_t *)data; | |
760 | ||
761 | dev->current_state = state; | |
762 | return 0; | |
763 | } | |
764 | ||
765 | /** | |
766 | * __pci_bus_set_current_state - Walk given bus and set current state of devices | |
767 | * @bus: Top bus of the subtree to walk. | |
768 | * @state: state to be set | |
769 | */ | |
770 | static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state) | |
771 | { | |
772 | if (bus) | |
773 | pci_walk_bus(bus, __pci_dev_set_current_state, &state); | |
0e5dd46b RW |
774 | } |
775 | ||
776 | /** | |
777 | * __pci_complete_power_transition - Complete power transition of a PCI device | |
778 | * @dev: PCI device to handle. | |
779 | * @state: State to put the device into. | |
780 | * | |
781 | * This function should not be called directly by device drivers. | |
782 | */ | |
783 | int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state) | |
784 | { | |
448bd857 HY |
785 | int ret; |
786 | ||
db288c9c | 787 | if (state <= PCI_D0) |
448bd857 HY |
788 | return -EINVAL; |
789 | ret = pci_platform_power_transition(dev, state); | |
790 | /* Power off the bridge may power off the whole hierarchy */ | |
791 | if (!ret && state == PCI_D3cold) | |
792 | __pci_bus_set_current_state(dev->subordinate, PCI_D3cold); | |
793 | return ret; | |
0e5dd46b RW |
794 | } |
795 | EXPORT_SYMBOL_GPL(__pci_complete_power_transition); | |
796 | ||
44e4e66e RW |
797 | /** |
798 | * pci_set_power_state - Set the power state of a PCI device | |
799 | * @dev: PCI device to handle. | |
800 | * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. | |
801 | * | |
877d0310 | 802 | * Transition a device to a new power state, using the platform firmware and/or |
44e4e66e RW |
803 | * the device's PCI PM registers. |
804 | * | |
805 | * RETURN VALUE: | |
806 | * -EINVAL if the requested state is invalid. | |
807 | * -EIO if device does not support PCI PM or its PM capabilities register has a | |
808 | * wrong version, or device doesn't support the requested state. | |
809 | * 0 if device already is in the requested state. | |
810 | * 0 if device's power state has been successfully changed. | |
811 | */ | |
812 | int pci_set_power_state(struct pci_dev *dev, pci_power_t state) | |
813 | { | |
337001b6 | 814 | int error; |
44e4e66e RW |
815 | |
816 | /* bound the state we're entering */ | |
448bd857 HY |
817 | if (state > PCI_D3cold) |
818 | state = PCI_D3cold; | |
44e4e66e RW |
819 | else if (state < PCI_D0) |
820 | state = PCI_D0; | |
821 | else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev)) | |
822 | /* | |
823 | * If the device or the parent bridge do not support PCI PM, | |
824 | * ignore the request if we're doing anything other than putting | |
825 | * it into D0 (which would only happen on boot). | |
826 | */ | |
827 | return 0; | |
828 | ||
db288c9c RW |
829 | /* Check if we're already there */ |
830 | if (dev->current_state == state) | |
831 | return 0; | |
832 | ||
0e5dd46b RW |
833 | __pci_start_power_transition(dev, state); |
834 | ||
979b1791 AC |
835 | /* This device is quirked not to be put into D3, so |
836 | don't put it in D3 */ | |
448bd857 | 837 | if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3)) |
979b1791 | 838 | return 0; |
44e4e66e | 839 | |
448bd857 HY |
840 | /* |
841 | * To put device in D3cold, we put device into D3hot in native | |
842 | * way, then put device into D3cold with platform ops | |
843 | */ | |
844 | error = pci_raw_set_power_state(dev, state > PCI_D3hot ? | |
845 | PCI_D3hot : state); | |
44e4e66e | 846 | |
0e5dd46b RW |
847 | if (!__pci_complete_power_transition(dev, state)) |
848 | error = 0; | |
44e4e66e RW |
849 | |
850 | return error; | |
851 | } | |
b7fe9434 | 852 | EXPORT_SYMBOL(pci_set_power_state); |
44e4e66e | 853 | |
1da177e4 LT |
854 | /** |
855 | * pci_choose_state - Choose the power state of a PCI device | |
856 | * @dev: PCI device to be suspended | |
857 | * @state: target sleep state for the whole system. This is the value | |
858 | * that is passed to suspend() function. | |
859 | * | |
860 | * Returns PCI power state suitable for given device and given system | |
861 | * message. | |
862 | */ | |
863 | ||
864 | pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) | |
865 | { | |
ab826ca4 | 866 | pci_power_t ret; |
0f64474b | 867 | |
728cdb75 | 868 | if (!dev->pm_cap) |
1da177e4 LT |
869 | return PCI_D0; |
870 | ||
961d9120 RW |
871 | ret = platform_pci_choose_state(dev); |
872 | if (ret != PCI_POWER_ERROR) | |
873 | return ret; | |
ca078bae PM |
874 | |
875 | switch (state.event) { | |
876 | case PM_EVENT_ON: | |
877 | return PCI_D0; | |
878 | case PM_EVENT_FREEZE: | |
b887d2e6 DB |
879 | case PM_EVENT_PRETHAW: |
880 | /* REVISIT both freeze and pre-thaw "should" use D0 */ | |
ca078bae | 881 | case PM_EVENT_SUSPEND: |
3a2d5b70 | 882 | case PM_EVENT_HIBERNATE: |
ca078bae | 883 | return PCI_D3hot; |
1da177e4 | 884 | default: |
80ccba11 BH |
885 | dev_info(&dev->dev, "unrecognized suspend event %d\n", |
886 | state.event); | |
1da177e4 LT |
887 | BUG(); |
888 | } | |
889 | return PCI_D0; | |
890 | } | |
1da177e4 LT |
891 | EXPORT_SYMBOL(pci_choose_state); |
892 | ||
89858517 YZ |
893 | #define PCI_EXP_SAVE_REGS 7 |
894 | ||
fd0f7f73 AW |
895 | static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev, |
896 | u16 cap, bool extended) | |
34a4876e YL |
897 | { |
898 | struct pci_cap_saved_state *tmp; | |
34a4876e | 899 | |
b67bfe0d | 900 | hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) { |
fd0f7f73 | 901 | if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap) |
34a4876e YL |
902 | return tmp; |
903 | } | |
904 | return NULL; | |
905 | } | |
906 | ||
fd0f7f73 AW |
907 | struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap) |
908 | { | |
909 | return _pci_find_saved_cap(dev, cap, false); | |
910 | } | |
911 | ||
912 | struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap) | |
913 | { | |
914 | return _pci_find_saved_cap(dev, cap, true); | |
915 | } | |
916 | ||
b56a5a23 MT |
917 | static int pci_save_pcie_state(struct pci_dev *dev) |
918 | { | |
59875ae4 | 919 | int i = 0; |
b56a5a23 MT |
920 | struct pci_cap_saved_state *save_state; |
921 | u16 *cap; | |
922 | ||
59875ae4 | 923 | if (!pci_is_pcie(dev)) |
b56a5a23 MT |
924 | return 0; |
925 | ||
9f35575d | 926 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); |
b56a5a23 | 927 | if (!save_state) { |
e496b617 | 928 | dev_err(&dev->dev, "buffer not found in %s\n", __func__); |
b56a5a23 MT |
929 | return -ENOMEM; |
930 | } | |
63f4898a | 931 | |
59875ae4 JL |
932 | cap = (u16 *)&save_state->cap.data[0]; |
933 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]); | |
934 | pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]); | |
935 | pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]); | |
936 | pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]); | |
937 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]); | |
938 | pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]); | |
939 | pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]); | |
9cb604ed | 940 | |
b56a5a23 MT |
941 | return 0; |
942 | } | |
943 | ||
944 | static void pci_restore_pcie_state(struct pci_dev *dev) | |
945 | { | |
59875ae4 | 946 | int i = 0; |
b56a5a23 MT |
947 | struct pci_cap_saved_state *save_state; |
948 | u16 *cap; | |
949 | ||
950 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); | |
59875ae4 | 951 | if (!save_state) |
9cb604ed MS |
952 | return; |
953 | ||
59875ae4 JL |
954 | cap = (u16 *)&save_state->cap.data[0]; |
955 | pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]); | |
956 | pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]); | |
957 | pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]); | |
958 | pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]); | |
959 | pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]); | |
960 | pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]); | |
961 | pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]); | |
b56a5a23 MT |
962 | } |
963 | ||
cc692a5f SH |
964 | |
965 | static int pci_save_pcix_state(struct pci_dev *dev) | |
966 | { | |
63f4898a | 967 | int pos; |
cc692a5f | 968 | struct pci_cap_saved_state *save_state; |
cc692a5f SH |
969 | |
970 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
971 | if (pos <= 0) | |
972 | return 0; | |
973 | ||
f34303de | 974 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); |
cc692a5f | 975 | if (!save_state) { |
e496b617 | 976 | dev_err(&dev->dev, "buffer not found in %s\n", __func__); |
cc692a5f SH |
977 | return -ENOMEM; |
978 | } | |
cc692a5f | 979 | |
24a4742f AW |
980 | pci_read_config_word(dev, pos + PCI_X_CMD, |
981 | (u16 *)save_state->cap.data); | |
63f4898a | 982 | |
cc692a5f SH |
983 | return 0; |
984 | } | |
985 | ||
986 | static void pci_restore_pcix_state(struct pci_dev *dev) | |
987 | { | |
988 | int i = 0, pos; | |
989 | struct pci_cap_saved_state *save_state; | |
990 | u16 *cap; | |
991 | ||
992 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); | |
993 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
994 | if (!save_state || pos <= 0) | |
995 | return; | |
24a4742f | 996 | cap = (u16 *)&save_state->cap.data[0]; |
cc692a5f SH |
997 | |
998 | pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]); | |
cc692a5f SH |
999 | } |
1000 | ||
1001 | ||
1da177e4 LT |
1002 | /** |
1003 | * pci_save_state - save the PCI configuration space of a device before suspending | |
1004 | * @dev: - PCI device that we're dealing with | |
1da177e4 | 1005 | */ |
3c78bc61 | 1006 | int pci_save_state(struct pci_dev *dev) |
1da177e4 LT |
1007 | { |
1008 | int i; | |
1009 | /* XXX: 100% dword access ok here? */ | |
1010 | for (i = 0; i < 16; i++) | |
9e0b5b2c | 1011 | pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]); |
aa8c6c93 | 1012 | dev->state_saved = true; |
79e50e72 QL |
1013 | |
1014 | i = pci_save_pcie_state(dev); | |
1015 | if (i != 0) | |
b56a5a23 | 1016 | return i; |
79e50e72 QL |
1017 | |
1018 | i = pci_save_pcix_state(dev); | |
1019 | if (i != 0) | |
cc692a5f | 1020 | return i; |
79e50e72 | 1021 | |
754834b9 | 1022 | return pci_save_vc_state(dev); |
1da177e4 | 1023 | } |
b7fe9434 | 1024 | EXPORT_SYMBOL(pci_save_state); |
1da177e4 | 1025 | |
ebfc5b80 RW |
1026 | static void pci_restore_config_dword(struct pci_dev *pdev, int offset, |
1027 | u32 saved_val, int retry) | |
1028 | { | |
1029 | u32 val; | |
1030 | ||
1031 | pci_read_config_dword(pdev, offset, &val); | |
1032 | if (val == saved_val) | |
1033 | return; | |
1034 | ||
1035 | for (;;) { | |
227f0647 RD |
1036 | dev_dbg(&pdev->dev, "restoring config space at offset %#x (was %#x, writing %#x)\n", |
1037 | offset, val, saved_val); | |
ebfc5b80 RW |
1038 | pci_write_config_dword(pdev, offset, saved_val); |
1039 | if (retry-- <= 0) | |
1040 | return; | |
1041 | ||
1042 | pci_read_config_dword(pdev, offset, &val); | |
1043 | if (val == saved_val) | |
1044 | return; | |
1045 | ||
1046 | mdelay(1); | |
1047 | } | |
1048 | } | |
1049 | ||
a6cb9ee7 RW |
1050 | static void pci_restore_config_space_range(struct pci_dev *pdev, |
1051 | int start, int end, int retry) | |
ebfc5b80 RW |
1052 | { |
1053 | int index; | |
1054 | ||
1055 | for (index = end; index >= start; index--) | |
1056 | pci_restore_config_dword(pdev, 4 * index, | |
1057 | pdev->saved_config_space[index], | |
1058 | retry); | |
1059 | } | |
1060 | ||
a6cb9ee7 RW |
1061 | static void pci_restore_config_space(struct pci_dev *pdev) |
1062 | { | |
1063 | if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) { | |
1064 | pci_restore_config_space_range(pdev, 10, 15, 0); | |
1065 | /* Restore BARs before the command register. */ | |
1066 | pci_restore_config_space_range(pdev, 4, 9, 10); | |
1067 | pci_restore_config_space_range(pdev, 0, 3, 0); | |
1068 | } else { | |
1069 | pci_restore_config_space_range(pdev, 0, 15, 0); | |
1070 | } | |
1071 | } | |
1072 | ||
f7625980 | 1073 | /** |
1da177e4 LT |
1074 | * pci_restore_state - Restore the saved state of a PCI device |
1075 | * @dev: - PCI device that we're dealing with | |
1da177e4 | 1076 | */ |
1d3c16a8 | 1077 | void pci_restore_state(struct pci_dev *dev) |
1da177e4 | 1078 | { |
c82f63e4 | 1079 | if (!dev->state_saved) |
1d3c16a8 | 1080 | return; |
4b77b0a2 | 1081 | |
b56a5a23 MT |
1082 | /* PCI Express register must be restored first */ |
1083 | pci_restore_pcie_state(dev); | |
1900ca13 | 1084 | pci_restore_ats_state(dev); |
425c1b22 | 1085 | pci_restore_vc_state(dev); |
b56a5a23 | 1086 | |
a6cb9ee7 | 1087 | pci_restore_config_space(dev); |
ebfc5b80 | 1088 | |
cc692a5f | 1089 | pci_restore_pcix_state(dev); |
41017f0c | 1090 | pci_restore_msi_state(dev); |
8c5cdb6a | 1091 | pci_restore_iov_state(dev); |
8fed4b65 | 1092 | |
4b77b0a2 | 1093 | dev->state_saved = false; |
1da177e4 | 1094 | } |
b7fe9434 | 1095 | EXPORT_SYMBOL(pci_restore_state); |
1da177e4 | 1096 | |
ffbdd3f7 AW |
1097 | struct pci_saved_state { |
1098 | u32 config_space[16]; | |
1099 | struct pci_cap_saved_data cap[0]; | |
1100 | }; | |
1101 | ||
1102 | /** | |
1103 | * pci_store_saved_state - Allocate and return an opaque struct containing | |
1104 | * the device saved state. | |
1105 | * @dev: PCI device that we're dealing with | |
1106 | * | |
f7625980 | 1107 | * Return NULL if no state or error. |
ffbdd3f7 AW |
1108 | */ |
1109 | struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev) | |
1110 | { | |
1111 | struct pci_saved_state *state; | |
1112 | struct pci_cap_saved_state *tmp; | |
1113 | struct pci_cap_saved_data *cap; | |
ffbdd3f7 AW |
1114 | size_t size; |
1115 | ||
1116 | if (!dev->state_saved) | |
1117 | return NULL; | |
1118 | ||
1119 | size = sizeof(*state) + sizeof(struct pci_cap_saved_data); | |
1120 | ||
b67bfe0d | 1121 | hlist_for_each_entry(tmp, &dev->saved_cap_space, next) |
ffbdd3f7 AW |
1122 | size += sizeof(struct pci_cap_saved_data) + tmp->cap.size; |
1123 | ||
1124 | state = kzalloc(size, GFP_KERNEL); | |
1125 | if (!state) | |
1126 | return NULL; | |
1127 | ||
1128 | memcpy(state->config_space, dev->saved_config_space, | |
1129 | sizeof(state->config_space)); | |
1130 | ||
1131 | cap = state->cap; | |
b67bfe0d | 1132 | hlist_for_each_entry(tmp, &dev->saved_cap_space, next) { |
ffbdd3f7 AW |
1133 | size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size; |
1134 | memcpy(cap, &tmp->cap, len); | |
1135 | cap = (struct pci_cap_saved_data *)((u8 *)cap + len); | |
1136 | } | |
1137 | /* Empty cap_save terminates list */ | |
1138 | ||
1139 | return state; | |
1140 | } | |
1141 | EXPORT_SYMBOL_GPL(pci_store_saved_state); | |
1142 | ||
1143 | /** | |
1144 | * pci_load_saved_state - Reload the provided save state into struct pci_dev. | |
1145 | * @dev: PCI device that we're dealing with | |
1146 | * @state: Saved state returned from pci_store_saved_state() | |
1147 | */ | |
98d9b271 KRW |
1148 | int pci_load_saved_state(struct pci_dev *dev, |
1149 | struct pci_saved_state *state) | |
ffbdd3f7 AW |
1150 | { |
1151 | struct pci_cap_saved_data *cap; | |
1152 | ||
1153 | dev->state_saved = false; | |
1154 | ||
1155 | if (!state) | |
1156 | return 0; | |
1157 | ||
1158 | memcpy(dev->saved_config_space, state->config_space, | |
1159 | sizeof(state->config_space)); | |
1160 | ||
1161 | cap = state->cap; | |
1162 | while (cap->size) { | |
1163 | struct pci_cap_saved_state *tmp; | |
1164 | ||
fd0f7f73 | 1165 | tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended); |
ffbdd3f7 AW |
1166 | if (!tmp || tmp->cap.size != cap->size) |
1167 | return -EINVAL; | |
1168 | ||
1169 | memcpy(tmp->cap.data, cap->data, tmp->cap.size); | |
1170 | cap = (struct pci_cap_saved_data *)((u8 *)cap + | |
1171 | sizeof(struct pci_cap_saved_data) + cap->size); | |
1172 | } | |
1173 | ||
1174 | dev->state_saved = true; | |
1175 | return 0; | |
1176 | } | |
98d9b271 | 1177 | EXPORT_SYMBOL_GPL(pci_load_saved_state); |
ffbdd3f7 AW |
1178 | |
1179 | /** | |
1180 | * pci_load_and_free_saved_state - Reload the save state pointed to by state, | |
1181 | * and free the memory allocated for it. | |
1182 | * @dev: PCI device that we're dealing with | |
1183 | * @state: Pointer to saved state returned from pci_store_saved_state() | |
1184 | */ | |
1185 | int pci_load_and_free_saved_state(struct pci_dev *dev, | |
1186 | struct pci_saved_state **state) | |
1187 | { | |
1188 | int ret = pci_load_saved_state(dev, *state); | |
1189 | kfree(*state); | |
1190 | *state = NULL; | |
1191 | return ret; | |
1192 | } | |
1193 | EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state); | |
1194 | ||
8a9d5609 BH |
1195 | int __weak pcibios_enable_device(struct pci_dev *dev, int bars) |
1196 | { | |
1197 | return pci_enable_resources(dev, bars); | |
1198 | } | |
1199 | ||
38cc1302 HS |
1200 | static int do_pci_enable_device(struct pci_dev *dev, int bars) |
1201 | { | |
1202 | int err; | |
1f6ae47e | 1203 | struct pci_dev *bridge; |
1e2571a7 BH |
1204 | u16 cmd; |
1205 | u8 pin; | |
38cc1302 HS |
1206 | |
1207 | err = pci_set_power_state(dev, PCI_D0); | |
1208 | if (err < 0 && err != -EIO) | |
1209 | return err; | |
1f6ae47e VS |
1210 | |
1211 | bridge = pci_upstream_bridge(dev); | |
1212 | if (bridge) | |
1213 | pcie_aspm_powersave_config_link(bridge); | |
1214 | ||
38cc1302 HS |
1215 | err = pcibios_enable_device(dev, bars); |
1216 | if (err < 0) | |
1217 | return err; | |
1218 | pci_fixup_device(pci_fixup_enable, dev); | |
1219 | ||
866d5417 BH |
1220 | if (dev->msi_enabled || dev->msix_enabled) |
1221 | return 0; | |
1222 | ||
1e2571a7 BH |
1223 | pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); |
1224 | if (pin) { | |
1225 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
1226 | if (cmd & PCI_COMMAND_INTX_DISABLE) | |
1227 | pci_write_config_word(dev, PCI_COMMAND, | |
1228 | cmd & ~PCI_COMMAND_INTX_DISABLE); | |
1229 | } | |
1230 | ||
38cc1302 HS |
1231 | return 0; |
1232 | } | |
1233 | ||
1234 | /** | |
0b62e13b | 1235 | * pci_reenable_device - Resume abandoned device |
38cc1302 HS |
1236 | * @dev: PCI device to be resumed |
1237 | * | |
1238 | * Note this function is a backend of pci_default_resume and is not supposed | |
1239 | * to be called by normal code, write proper resume handler and use it instead. | |
1240 | */ | |
0b62e13b | 1241 | int pci_reenable_device(struct pci_dev *dev) |
38cc1302 | 1242 | { |
296ccb08 | 1243 | if (pci_is_enabled(dev)) |
38cc1302 HS |
1244 | return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1); |
1245 | return 0; | |
1246 | } | |
b7fe9434 | 1247 | EXPORT_SYMBOL(pci_reenable_device); |
38cc1302 | 1248 | |
928bea96 YL |
1249 | static void pci_enable_bridge(struct pci_dev *dev) |
1250 | { | |
79272138 | 1251 | struct pci_dev *bridge; |
928bea96 YL |
1252 | int retval; |
1253 | ||
79272138 BH |
1254 | bridge = pci_upstream_bridge(dev); |
1255 | if (bridge) | |
1256 | pci_enable_bridge(bridge); | |
928bea96 | 1257 | |
cf3e1feb | 1258 | if (pci_is_enabled(dev)) { |
fbeeb822 | 1259 | if (!dev->is_busmaster) |
cf3e1feb | 1260 | pci_set_master(dev); |
928bea96 | 1261 | return; |
cf3e1feb YL |
1262 | } |
1263 | ||
928bea96 YL |
1264 | retval = pci_enable_device(dev); |
1265 | if (retval) | |
1266 | dev_err(&dev->dev, "Error enabling bridge (%d), continuing\n", | |
1267 | retval); | |
1268 | pci_set_master(dev); | |
1269 | } | |
1270 | ||
b4b4fbba | 1271 | static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags) |
1da177e4 | 1272 | { |
79272138 | 1273 | struct pci_dev *bridge; |
1da177e4 | 1274 | int err; |
b718989d | 1275 | int i, bars = 0; |
1da177e4 | 1276 | |
97c145f7 JB |
1277 | /* |
1278 | * Power state could be unknown at this point, either due to a fresh | |
1279 | * boot or a device removal call. So get the current power state | |
1280 | * so that things like MSI message writing will behave as expected | |
1281 | * (e.g. if the device really is in D0 at enable time). | |
1282 | */ | |
1283 | if (dev->pm_cap) { | |
1284 | u16 pmcsr; | |
1285 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); | |
1286 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); | |
1287 | } | |
1288 | ||
cc7ba39b | 1289 | if (atomic_inc_return(&dev->enable_cnt) > 1) |
9fb625c3 HS |
1290 | return 0; /* already enabled */ |
1291 | ||
79272138 BH |
1292 | bridge = pci_upstream_bridge(dev); |
1293 | if (bridge) | |
1294 | pci_enable_bridge(bridge); | |
928bea96 | 1295 | |
497f16f2 YL |
1296 | /* only skip sriov related */ |
1297 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) | |
1298 | if (dev->resource[i].flags & flags) | |
1299 | bars |= (1 << i); | |
1300 | for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++) | |
b718989d BH |
1301 | if (dev->resource[i].flags & flags) |
1302 | bars |= (1 << i); | |
1303 | ||
38cc1302 | 1304 | err = do_pci_enable_device(dev, bars); |
95a62965 | 1305 | if (err < 0) |
38cc1302 | 1306 | atomic_dec(&dev->enable_cnt); |
9fb625c3 | 1307 | return err; |
1da177e4 LT |
1308 | } |
1309 | ||
b718989d BH |
1310 | /** |
1311 | * pci_enable_device_io - Initialize a device for use with IO space | |
1312 | * @dev: PCI device to be initialized | |
1313 | * | |
1314 | * Initialize device before it's used by a driver. Ask low-level code | |
1315 | * to enable I/O resources. Wake up the device if it was suspended. | |
1316 | * Beware, this function can fail. | |
1317 | */ | |
1318 | int pci_enable_device_io(struct pci_dev *dev) | |
1319 | { | |
b4b4fbba | 1320 | return pci_enable_device_flags(dev, IORESOURCE_IO); |
b718989d | 1321 | } |
b7fe9434 | 1322 | EXPORT_SYMBOL(pci_enable_device_io); |
b718989d BH |
1323 | |
1324 | /** | |
1325 | * pci_enable_device_mem - Initialize a device for use with Memory space | |
1326 | * @dev: PCI device to be initialized | |
1327 | * | |
1328 | * Initialize device before it's used by a driver. Ask low-level code | |
1329 | * to enable Memory resources. Wake up the device if it was suspended. | |
1330 | * Beware, this function can fail. | |
1331 | */ | |
1332 | int pci_enable_device_mem(struct pci_dev *dev) | |
1333 | { | |
b4b4fbba | 1334 | return pci_enable_device_flags(dev, IORESOURCE_MEM); |
b718989d | 1335 | } |
b7fe9434 | 1336 | EXPORT_SYMBOL(pci_enable_device_mem); |
b718989d | 1337 | |
bae94d02 IPG |
1338 | /** |
1339 | * pci_enable_device - Initialize device before it's used by a driver. | |
1340 | * @dev: PCI device to be initialized | |
1341 | * | |
1342 | * Initialize device before it's used by a driver. Ask low-level code | |
1343 | * to enable I/O and memory. Wake up the device if it was suspended. | |
1344 | * Beware, this function can fail. | |
1345 | * | |
1346 | * Note we don't actually enable the device many times if we call | |
1347 | * this function repeatedly (we just increment the count). | |
1348 | */ | |
1349 | int pci_enable_device(struct pci_dev *dev) | |
1350 | { | |
b4b4fbba | 1351 | return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO); |
bae94d02 | 1352 | } |
b7fe9434 | 1353 | EXPORT_SYMBOL(pci_enable_device); |
bae94d02 | 1354 | |
9ac7849e TH |
1355 | /* |
1356 | * Managed PCI resources. This manages device on/off, intx/msi/msix | |
1357 | * on/off and BAR regions. pci_dev itself records msi/msix status, so | |
1358 | * there's no need to track it separately. pci_devres is initialized | |
1359 | * when a device is enabled using managed PCI device enable interface. | |
1360 | */ | |
1361 | struct pci_devres { | |
7f375f32 TH |
1362 | unsigned int enabled:1; |
1363 | unsigned int pinned:1; | |
9ac7849e TH |
1364 | unsigned int orig_intx:1; |
1365 | unsigned int restore_intx:1; | |
1366 | u32 region_mask; | |
1367 | }; | |
1368 | ||
1369 | static void pcim_release(struct device *gendev, void *res) | |
1370 | { | |
1371 | struct pci_dev *dev = container_of(gendev, struct pci_dev, dev); | |
1372 | struct pci_devres *this = res; | |
1373 | int i; | |
1374 | ||
1375 | if (dev->msi_enabled) | |
1376 | pci_disable_msi(dev); | |
1377 | if (dev->msix_enabled) | |
1378 | pci_disable_msix(dev); | |
1379 | ||
1380 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) | |
1381 | if (this->region_mask & (1 << i)) | |
1382 | pci_release_region(dev, i); | |
1383 | ||
1384 | if (this->restore_intx) | |
1385 | pci_intx(dev, this->orig_intx); | |
1386 | ||
7f375f32 | 1387 | if (this->enabled && !this->pinned) |
9ac7849e TH |
1388 | pci_disable_device(dev); |
1389 | } | |
1390 | ||
07656d83 | 1391 | static struct pci_devres *get_pci_dr(struct pci_dev *pdev) |
9ac7849e TH |
1392 | { |
1393 | struct pci_devres *dr, *new_dr; | |
1394 | ||
1395 | dr = devres_find(&pdev->dev, pcim_release, NULL, NULL); | |
1396 | if (dr) | |
1397 | return dr; | |
1398 | ||
1399 | new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL); | |
1400 | if (!new_dr) | |
1401 | return NULL; | |
1402 | return devres_get(&pdev->dev, new_dr, NULL, NULL); | |
1403 | } | |
1404 | ||
07656d83 | 1405 | static struct pci_devres *find_pci_dr(struct pci_dev *pdev) |
9ac7849e TH |
1406 | { |
1407 | if (pci_is_managed(pdev)) | |
1408 | return devres_find(&pdev->dev, pcim_release, NULL, NULL); | |
1409 | return NULL; | |
1410 | } | |
1411 | ||
1412 | /** | |
1413 | * pcim_enable_device - Managed pci_enable_device() | |
1414 | * @pdev: PCI device to be initialized | |
1415 | * | |
1416 | * Managed pci_enable_device(). | |
1417 | */ | |
1418 | int pcim_enable_device(struct pci_dev *pdev) | |
1419 | { | |
1420 | struct pci_devres *dr; | |
1421 | int rc; | |
1422 | ||
1423 | dr = get_pci_dr(pdev); | |
1424 | if (unlikely(!dr)) | |
1425 | return -ENOMEM; | |
b95d58ea TH |
1426 | if (dr->enabled) |
1427 | return 0; | |
9ac7849e TH |
1428 | |
1429 | rc = pci_enable_device(pdev); | |
1430 | if (!rc) { | |
1431 | pdev->is_managed = 1; | |
7f375f32 | 1432 | dr->enabled = 1; |
9ac7849e TH |
1433 | } |
1434 | return rc; | |
1435 | } | |
b7fe9434 | 1436 | EXPORT_SYMBOL(pcim_enable_device); |
9ac7849e TH |
1437 | |
1438 | /** | |
1439 | * pcim_pin_device - Pin managed PCI device | |
1440 | * @pdev: PCI device to pin | |
1441 | * | |
1442 | * Pin managed PCI device @pdev. Pinned device won't be disabled on | |
1443 | * driver detach. @pdev must have been enabled with | |
1444 | * pcim_enable_device(). | |
1445 | */ | |
1446 | void pcim_pin_device(struct pci_dev *pdev) | |
1447 | { | |
1448 | struct pci_devres *dr; | |
1449 | ||
1450 | dr = find_pci_dr(pdev); | |
7f375f32 | 1451 | WARN_ON(!dr || !dr->enabled); |
9ac7849e | 1452 | if (dr) |
7f375f32 | 1453 | dr->pinned = 1; |
9ac7849e | 1454 | } |
b7fe9434 | 1455 | EXPORT_SYMBOL(pcim_pin_device); |
9ac7849e | 1456 | |
eca0d467 MG |
1457 | /* |
1458 | * pcibios_add_device - provide arch specific hooks when adding device dev | |
1459 | * @dev: the PCI device being added | |
1460 | * | |
1461 | * Permits the platform to provide architecture specific functionality when | |
1462 | * devices are added. This is the default implementation. Architecture | |
1463 | * implementations can override this. | |
1464 | */ | |
3c78bc61 | 1465 | int __weak pcibios_add_device(struct pci_dev *dev) |
eca0d467 MG |
1466 | { |
1467 | return 0; | |
1468 | } | |
1469 | ||
6ae32c53 SO |
1470 | /** |
1471 | * pcibios_release_device - provide arch specific hooks when releasing device dev | |
1472 | * @dev: the PCI device being released | |
1473 | * | |
1474 | * Permits the platform to provide architecture specific functionality when | |
1475 | * devices are released. This is the default implementation. Architecture | |
1476 | * implementations can override this. | |
1477 | */ | |
1478 | void __weak pcibios_release_device(struct pci_dev *dev) {} | |
1479 | ||
1da177e4 LT |
1480 | /** |
1481 | * pcibios_disable_device - disable arch specific PCI resources for device dev | |
1482 | * @dev: the PCI device to disable | |
1483 | * | |
1484 | * Disables architecture specific PCI resources for the device. This | |
1485 | * is the default implementation. Architecture implementations can | |
1486 | * override this. | |
1487 | */ | |
d6d88c83 | 1488 | void __weak pcibios_disable_device (struct pci_dev *dev) {} |
1da177e4 | 1489 | |
a43ae58c HG |
1490 | /** |
1491 | * pcibios_penalize_isa_irq - penalize an ISA IRQ | |
1492 | * @irq: ISA IRQ to penalize | |
1493 | * @active: IRQ active or not | |
1494 | * | |
1495 | * Permits the platform to provide architecture-specific functionality when | |
1496 | * penalizing ISA IRQs. This is the default implementation. Architecture | |
1497 | * implementations can override this. | |
1498 | */ | |
1499 | void __weak pcibios_penalize_isa_irq(int irq, int active) {} | |
1500 | ||
fa58d305 RW |
1501 | static void do_pci_disable_device(struct pci_dev *dev) |
1502 | { | |
1503 | u16 pci_command; | |
1504 | ||
1505 | pci_read_config_word(dev, PCI_COMMAND, &pci_command); | |
1506 | if (pci_command & PCI_COMMAND_MASTER) { | |
1507 | pci_command &= ~PCI_COMMAND_MASTER; | |
1508 | pci_write_config_word(dev, PCI_COMMAND, pci_command); | |
1509 | } | |
1510 | ||
1511 | pcibios_disable_device(dev); | |
1512 | } | |
1513 | ||
1514 | /** | |
1515 | * pci_disable_enabled_device - Disable device without updating enable_cnt | |
1516 | * @dev: PCI device to disable | |
1517 | * | |
1518 | * NOTE: This function is a backend of PCI power management routines and is | |
1519 | * not supposed to be called drivers. | |
1520 | */ | |
1521 | void pci_disable_enabled_device(struct pci_dev *dev) | |
1522 | { | |
296ccb08 | 1523 | if (pci_is_enabled(dev)) |
fa58d305 RW |
1524 | do_pci_disable_device(dev); |
1525 | } | |
1526 | ||
1da177e4 LT |
1527 | /** |
1528 | * pci_disable_device - Disable PCI device after use | |
1529 | * @dev: PCI device to be disabled | |
1530 | * | |
1531 | * Signal to the system that the PCI device is not in use by the system | |
1532 | * anymore. This only involves disabling PCI bus-mastering, if active. | |
bae94d02 IPG |
1533 | * |
1534 | * Note we don't actually disable the device until all callers of | |
ee6583f6 | 1535 | * pci_enable_device() have called pci_disable_device(). |
1da177e4 | 1536 | */ |
3c78bc61 | 1537 | void pci_disable_device(struct pci_dev *dev) |
1da177e4 | 1538 | { |
9ac7849e | 1539 | struct pci_devres *dr; |
99dc804d | 1540 | |
9ac7849e TH |
1541 | dr = find_pci_dr(dev); |
1542 | if (dr) | |
7f375f32 | 1543 | dr->enabled = 0; |
9ac7849e | 1544 | |
fd6dceab KK |
1545 | dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0, |
1546 | "disabling already-disabled device"); | |
1547 | ||
cc7ba39b | 1548 | if (atomic_dec_return(&dev->enable_cnt) != 0) |
bae94d02 IPG |
1549 | return; |
1550 | ||
fa58d305 | 1551 | do_pci_disable_device(dev); |
1da177e4 | 1552 | |
fa58d305 | 1553 | dev->is_busmaster = 0; |
1da177e4 | 1554 | } |
b7fe9434 | 1555 | EXPORT_SYMBOL(pci_disable_device); |
1da177e4 | 1556 | |
f7bdd12d BK |
1557 | /** |
1558 | * pcibios_set_pcie_reset_state - set reset state for device dev | |
45e829ea | 1559 | * @dev: the PCIe device reset |
f7bdd12d BK |
1560 | * @state: Reset state to enter into |
1561 | * | |
1562 | * | |
45e829ea | 1563 | * Sets the PCIe reset state for the device. This is the default |
f7bdd12d BK |
1564 | * implementation. Architecture implementations can override this. |
1565 | */ | |
d6d88c83 BH |
1566 | int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev, |
1567 | enum pcie_reset_state state) | |
f7bdd12d BK |
1568 | { |
1569 | return -EINVAL; | |
1570 | } | |
1571 | ||
1572 | /** | |
1573 | * pci_set_pcie_reset_state - set reset state for device dev | |
45e829ea | 1574 | * @dev: the PCIe device reset |
f7bdd12d BK |
1575 | * @state: Reset state to enter into |
1576 | * | |
1577 | * | |
1578 | * Sets the PCI reset state for the device. | |
1579 | */ | |
1580 | int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) | |
1581 | { | |
1582 | return pcibios_set_pcie_reset_state(dev, state); | |
1583 | } | |
b7fe9434 | 1584 | EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state); |
f7bdd12d | 1585 | |
58ff4633 RW |
1586 | /** |
1587 | * pci_check_pme_status - Check if given device has generated PME. | |
1588 | * @dev: Device to check. | |
1589 | * | |
1590 | * Check the PME status of the device and if set, clear it and clear PME enable | |
1591 | * (if set). Return 'true' if PME status and PME enable were both set or | |
1592 | * 'false' otherwise. | |
1593 | */ | |
1594 | bool pci_check_pme_status(struct pci_dev *dev) | |
1595 | { | |
1596 | int pmcsr_pos; | |
1597 | u16 pmcsr; | |
1598 | bool ret = false; | |
1599 | ||
1600 | if (!dev->pm_cap) | |
1601 | return false; | |
1602 | ||
1603 | pmcsr_pos = dev->pm_cap + PCI_PM_CTRL; | |
1604 | pci_read_config_word(dev, pmcsr_pos, &pmcsr); | |
1605 | if (!(pmcsr & PCI_PM_CTRL_PME_STATUS)) | |
1606 | return false; | |
1607 | ||
1608 | /* Clear PME status. */ | |
1609 | pmcsr |= PCI_PM_CTRL_PME_STATUS; | |
1610 | if (pmcsr & PCI_PM_CTRL_PME_ENABLE) { | |
1611 | /* Disable PME to avoid interrupt flood. */ | |
1612 | pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; | |
1613 | ret = true; | |
1614 | } | |
1615 | ||
1616 | pci_write_config_word(dev, pmcsr_pos, pmcsr); | |
1617 | ||
1618 | return ret; | |
1619 | } | |
1620 | ||
b67ea761 RW |
1621 | /** |
1622 | * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set. | |
1623 | * @dev: Device to handle. | |
379021d5 | 1624 | * @pme_poll_reset: Whether or not to reset the device's pme_poll flag. |
b67ea761 RW |
1625 | * |
1626 | * Check if @dev has generated PME and queue a resume request for it in that | |
1627 | * case. | |
1628 | */ | |
379021d5 | 1629 | static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset) |
b67ea761 | 1630 | { |
379021d5 RW |
1631 | if (pme_poll_reset && dev->pme_poll) |
1632 | dev->pme_poll = false; | |
1633 | ||
c125e96f | 1634 | if (pci_check_pme_status(dev)) { |
c125e96f | 1635 | pci_wakeup_event(dev); |
0f953bf6 | 1636 | pm_request_resume(&dev->dev); |
c125e96f | 1637 | } |
b67ea761 RW |
1638 | return 0; |
1639 | } | |
1640 | ||
1641 | /** | |
1642 | * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary. | |
1643 | * @bus: Top bus of the subtree to walk. | |
1644 | */ | |
1645 | void pci_pme_wakeup_bus(struct pci_bus *bus) | |
1646 | { | |
1647 | if (bus) | |
379021d5 | 1648 | pci_walk_bus(bus, pci_pme_wakeup, (void *)true); |
b67ea761 RW |
1649 | } |
1650 | ||
448bd857 | 1651 | |
eb9d0fe4 RW |
1652 | /** |
1653 | * pci_pme_capable - check the capability of PCI device to generate PME# | |
1654 | * @dev: PCI device to handle. | |
eb9d0fe4 RW |
1655 | * @state: PCI state from which device will issue PME#. |
1656 | */ | |
e5899e1b | 1657 | bool pci_pme_capable(struct pci_dev *dev, pci_power_t state) |
eb9d0fe4 | 1658 | { |
337001b6 | 1659 | if (!dev->pm_cap) |
eb9d0fe4 RW |
1660 | return false; |
1661 | ||
337001b6 | 1662 | return !!(dev->pme_support & (1 << state)); |
eb9d0fe4 | 1663 | } |
b7fe9434 | 1664 | EXPORT_SYMBOL(pci_pme_capable); |
eb9d0fe4 | 1665 | |
df17e62e MG |
1666 | static void pci_pme_list_scan(struct work_struct *work) |
1667 | { | |
379021d5 | 1668 | struct pci_pme_device *pme_dev, *n; |
df17e62e MG |
1669 | |
1670 | mutex_lock(&pci_pme_list_mutex); | |
ce300008 BH |
1671 | list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) { |
1672 | if (pme_dev->dev->pme_poll) { | |
1673 | struct pci_dev *bridge; | |
1674 | ||
1675 | bridge = pme_dev->dev->bus->self; | |
1676 | /* | |
1677 | * If bridge is in low power state, the | |
1678 | * configuration space of subordinate devices | |
1679 | * may be not accessible | |
1680 | */ | |
1681 | if (bridge && bridge->current_state != PCI_D0) | |
1682 | continue; | |
1683 | pci_pme_wakeup(pme_dev->dev, NULL); | |
1684 | } else { | |
1685 | list_del(&pme_dev->list); | |
1686 | kfree(pme_dev); | |
379021d5 | 1687 | } |
df17e62e | 1688 | } |
ce300008 BH |
1689 | if (!list_empty(&pci_pme_list)) |
1690 | schedule_delayed_work(&pci_pme_work, | |
1691 | msecs_to_jiffies(PME_TIMEOUT)); | |
df17e62e MG |
1692 | mutex_unlock(&pci_pme_list_mutex); |
1693 | } | |
1694 | ||
eb9d0fe4 RW |
1695 | /** |
1696 | * pci_pme_active - enable or disable PCI device's PME# function | |
1697 | * @dev: PCI device to handle. | |
eb9d0fe4 RW |
1698 | * @enable: 'true' to enable PME# generation; 'false' to disable it. |
1699 | * | |
1700 | * The caller must verify that the device is capable of generating PME# before | |
1701 | * calling this function with @enable equal to 'true'. | |
1702 | */ | |
5a6c9b60 | 1703 | void pci_pme_active(struct pci_dev *dev, bool enable) |
eb9d0fe4 RW |
1704 | { |
1705 | u16 pmcsr; | |
1706 | ||
ffaddbe8 | 1707 | if (!dev->pme_support) |
eb9d0fe4 RW |
1708 | return; |
1709 | ||
337001b6 | 1710 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
eb9d0fe4 RW |
1711 | /* Clear PME_Status by writing 1 to it and enable PME# */ |
1712 | pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE; | |
1713 | if (!enable) | |
1714 | pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; | |
1715 | ||
337001b6 | 1716 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); |
eb9d0fe4 | 1717 | |
6e965e0d HY |
1718 | /* |
1719 | * PCI (as opposed to PCIe) PME requires that the device have | |
1720 | * its PME# line hooked up correctly. Not all hardware vendors | |
1721 | * do this, so the PME never gets delivered and the device | |
1722 | * remains asleep. The easiest way around this is to | |
1723 | * periodically walk the list of suspended devices and check | |
1724 | * whether any have their PME flag set. The assumption is that | |
1725 | * we'll wake up often enough anyway that this won't be a huge | |
1726 | * hit, and the power savings from the devices will still be a | |
1727 | * win. | |
1728 | * | |
1729 | * Although PCIe uses in-band PME message instead of PME# line | |
1730 | * to report PME, PME does not work for some PCIe devices in | |
1731 | * reality. For example, there are devices that set their PME | |
1732 | * status bits, but don't really bother to send a PME message; | |
1733 | * there are PCI Express Root Ports that don't bother to | |
1734 | * trigger interrupts when they receive PME messages from the | |
1735 | * devices below. So PME poll is used for PCIe devices too. | |
1736 | */ | |
df17e62e | 1737 | |
379021d5 | 1738 | if (dev->pme_poll) { |
df17e62e MG |
1739 | struct pci_pme_device *pme_dev; |
1740 | if (enable) { | |
1741 | pme_dev = kmalloc(sizeof(struct pci_pme_device), | |
1742 | GFP_KERNEL); | |
0394cb19 BH |
1743 | if (!pme_dev) { |
1744 | dev_warn(&dev->dev, "can't enable PME#\n"); | |
1745 | return; | |
1746 | } | |
df17e62e MG |
1747 | pme_dev->dev = dev; |
1748 | mutex_lock(&pci_pme_list_mutex); | |
1749 | list_add(&pme_dev->list, &pci_pme_list); | |
1750 | if (list_is_singular(&pci_pme_list)) | |
1751 | schedule_delayed_work(&pci_pme_work, | |
1752 | msecs_to_jiffies(PME_TIMEOUT)); | |
1753 | mutex_unlock(&pci_pme_list_mutex); | |
1754 | } else { | |
1755 | mutex_lock(&pci_pme_list_mutex); | |
1756 | list_for_each_entry(pme_dev, &pci_pme_list, list) { | |
1757 | if (pme_dev->dev == dev) { | |
1758 | list_del(&pme_dev->list); | |
1759 | kfree(pme_dev); | |
1760 | break; | |
1761 | } | |
1762 | } | |
1763 | mutex_unlock(&pci_pme_list_mutex); | |
1764 | } | |
1765 | } | |
1766 | ||
85b8582d | 1767 | dev_dbg(&dev->dev, "PME# %s\n", enable ? "enabled" : "disabled"); |
eb9d0fe4 | 1768 | } |
b7fe9434 | 1769 | EXPORT_SYMBOL(pci_pme_active); |
eb9d0fe4 | 1770 | |
1da177e4 | 1771 | /** |
6cbf8214 | 1772 | * __pci_enable_wake - enable PCI device as wakeup event source |
075c1771 DB |
1773 | * @dev: PCI device affected |
1774 | * @state: PCI state from which device will issue wakeup events | |
6cbf8214 | 1775 | * @runtime: True if the events are to be generated at run time |
075c1771 DB |
1776 | * @enable: True to enable event generation; false to disable |
1777 | * | |
1778 | * This enables the device as a wakeup event source, or disables it. | |
1779 | * When such events involves platform-specific hooks, those hooks are | |
1780 | * called automatically by this routine. | |
1781 | * | |
1782 | * Devices with legacy power management (no standard PCI PM capabilities) | |
eb9d0fe4 | 1783 | * always require such platform hooks. |
075c1771 | 1784 | * |
eb9d0fe4 RW |
1785 | * RETURN VALUE: |
1786 | * 0 is returned on success | |
1787 | * -EINVAL is returned if device is not supposed to wake up the system | |
1788 | * Error code depending on the platform is returned if both the platform and | |
1789 | * the native mechanism fail to enable the generation of wake-up events | |
1da177e4 | 1790 | */ |
6cbf8214 RW |
1791 | int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, |
1792 | bool runtime, bool enable) | |
1da177e4 | 1793 | { |
5bcc2fb4 | 1794 | int ret = 0; |
075c1771 | 1795 | |
6cbf8214 | 1796 | if (enable && !runtime && !device_may_wakeup(&dev->dev)) |
eb9d0fe4 | 1797 | return -EINVAL; |
1da177e4 | 1798 | |
e80bb09d RW |
1799 | /* Don't do the same thing twice in a row for one device. */ |
1800 | if (!!enable == !!dev->wakeup_prepared) | |
1801 | return 0; | |
1802 | ||
eb9d0fe4 RW |
1803 | /* |
1804 | * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don | |
1805 | * Anderson we should be doing PME# wake enable followed by ACPI wake | |
1806 | * enable. To disable wake-up we call the platform first, for symmetry. | |
075c1771 | 1807 | */ |
1da177e4 | 1808 | |
5bcc2fb4 RW |
1809 | if (enable) { |
1810 | int error; | |
1da177e4 | 1811 | |
5bcc2fb4 RW |
1812 | if (pci_pme_capable(dev, state)) |
1813 | pci_pme_active(dev, true); | |
1814 | else | |
1815 | ret = 1; | |
6cbf8214 RW |
1816 | error = runtime ? platform_pci_run_wake(dev, true) : |
1817 | platform_pci_sleep_wake(dev, true); | |
5bcc2fb4 RW |
1818 | if (ret) |
1819 | ret = error; | |
e80bb09d RW |
1820 | if (!ret) |
1821 | dev->wakeup_prepared = true; | |
5bcc2fb4 | 1822 | } else { |
6cbf8214 RW |
1823 | if (runtime) |
1824 | platform_pci_run_wake(dev, false); | |
1825 | else | |
1826 | platform_pci_sleep_wake(dev, false); | |
5bcc2fb4 | 1827 | pci_pme_active(dev, false); |
e80bb09d | 1828 | dev->wakeup_prepared = false; |
5bcc2fb4 | 1829 | } |
1da177e4 | 1830 | |
5bcc2fb4 | 1831 | return ret; |
eb9d0fe4 | 1832 | } |
6cbf8214 | 1833 | EXPORT_SYMBOL(__pci_enable_wake); |
1da177e4 | 1834 | |
0235c4fc RW |
1835 | /** |
1836 | * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold | |
1837 | * @dev: PCI device to prepare | |
1838 | * @enable: True to enable wake-up event generation; false to disable | |
1839 | * | |
1840 | * Many drivers want the device to wake up the system from D3_hot or D3_cold | |
1841 | * and this function allows them to set that up cleanly - pci_enable_wake() | |
1842 | * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI | |
1843 | * ordering constraints. | |
1844 | * | |
1845 | * This function only returns error code if the device is not capable of | |
1846 | * generating PME# from both D3_hot and D3_cold, and the platform is unable to | |
1847 | * enable wake-up power for it. | |
1848 | */ | |
1849 | int pci_wake_from_d3(struct pci_dev *dev, bool enable) | |
1850 | { | |
1851 | return pci_pme_capable(dev, PCI_D3cold) ? | |
1852 | pci_enable_wake(dev, PCI_D3cold, enable) : | |
1853 | pci_enable_wake(dev, PCI_D3hot, enable); | |
1854 | } | |
b7fe9434 | 1855 | EXPORT_SYMBOL(pci_wake_from_d3); |
0235c4fc | 1856 | |
404cc2d8 | 1857 | /** |
37139074 JB |
1858 | * pci_target_state - find an appropriate low power state for a given PCI dev |
1859 | * @dev: PCI device | |
1860 | * | |
1861 | * Use underlying platform code to find a supported low power state for @dev. | |
1862 | * If the platform can't manage @dev, return the deepest state from which it | |
1863 | * can generate wake events, based on any available PME info. | |
404cc2d8 | 1864 | */ |
0b950f0f | 1865 | static pci_power_t pci_target_state(struct pci_dev *dev) |
404cc2d8 RW |
1866 | { |
1867 | pci_power_t target_state = PCI_D3hot; | |
404cc2d8 RW |
1868 | |
1869 | if (platform_pci_power_manageable(dev)) { | |
1870 | /* | |
1871 | * Call the platform to choose the target state of the device | |
1872 | * and enable wake-up from this state if supported. | |
1873 | */ | |
1874 | pci_power_t state = platform_pci_choose_state(dev); | |
1875 | ||
1876 | switch (state) { | |
1877 | case PCI_POWER_ERROR: | |
1878 | case PCI_UNKNOWN: | |
1879 | break; | |
1880 | case PCI_D1: | |
1881 | case PCI_D2: | |
1882 | if (pci_no_d1d2(dev)) | |
1883 | break; | |
1884 | default: | |
1885 | target_state = state; | |
404cc2d8 | 1886 | } |
d2abdf62 RW |
1887 | } else if (!dev->pm_cap) { |
1888 | target_state = PCI_D0; | |
404cc2d8 RW |
1889 | } else if (device_may_wakeup(&dev->dev)) { |
1890 | /* | |
1891 | * Find the deepest state from which the device can generate | |
1892 | * wake-up events, make it the target state and enable device | |
1893 | * to generate PME#. | |
1894 | */ | |
337001b6 RW |
1895 | if (dev->pme_support) { |
1896 | while (target_state | |
1897 | && !(dev->pme_support & (1 << target_state))) | |
1898 | target_state--; | |
404cc2d8 RW |
1899 | } |
1900 | } | |
1901 | ||
e5899e1b RW |
1902 | return target_state; |
1903 | } | |
1904 | ||
1905 | /** | |
1906 | * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state | |
1907 | * @dev: Device to handle. | |
1908 | * | |
1909 | * Choose the power state appropriate for the device depending on whether | |
1910 | * it can wake up the system and/or is power manageable by the platform | |
1911 | * (PCI_D3hot is the default) and put the device into that state. | |
1912 | */ | |
1913 | int pci_prepare_to_sleep(struct pci_dev *dev) | |
1914 | { | |
1915 | pci_power_t target_state = pci_target_state(dev); | |
1916 | int error; | |
1917 | ||
1918 | if (target_state == PCI_POWER_ERROR) | |
1919 | return -EIO; | |
1920 | ||
8efb8c76 | 1921 | pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev)); |
c157dfa3 | 1922 | |
404cc2d8 RW |
1923 | error = pci_set_power_state(dev, target_state); |
1924 | ||
1925 | if (error) | |
1926 | pci_enable_wake(dev, target_state, false); | |
1927 | ||
1928 | return error; | |
1929 | } | |
b7fe9434 | 1930 | EXPORT_SYMBOL(pci_prepare_to_sleep); |
404cc2d8 RW |
1931 | |
1932 | /** | |
443bd1c4 | 1933 | * pci_back_from_sleep - turn PCI device on during system-wide transition into working state |
404cc2d8 RW |
1934 | * @dev: Device to handle. |
1935 | * | |
88393161 | 1936 | * Disable device's system wake-up capability and put it into D0. |
404cc2d8 RW |
1937 | */ |
1938 | int pci_back_from_sleep(struct pci_dev *dev) | |
1939 | { | |
1940 | pci_enable_wake(dev, PCI_D0, false); | |
1941 | return pci_set_power_state(dev, PCI_D0); | |
1942 | } | |
b7fe9434 | 1943 | EXPORT_SYMBOL(pci_back_from_sleep); |
404cc2d8 | 1944 | |
6cbf8214 RW |
1945 | /** |
1946 | * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend. | |
1947 | * @dev: PCI device being suspended. | |
1948 | * | |
1949 | * Prepare @dev to generate wake-up events at run time and put it into a low | |
1950 | * power state. | |
1951 | */ | |
1952 | int pci_finish_runtime_suspend(struct pci_dev *dev) | |
1953 | { | |
1954 | pci_power_t target_state = pci_target_state(dev); | |
1955 | int error; | |
1956 | ||
1957 | if (target_state == PCI_POWER_ERROR) | |
1958 | return -EIO; | |
1959 | ||
448bd857 HY |
1960 | dev->runtime_d3cold = target_state == PCI_D3cold; |
1961 | ||
6cbf8214 RW |
1962 | __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev)); |
1963 | ||
1964 | error = pci_set_power_state(dev, target_state); | |
1965 | ||
448bd857 | 1966 | if (error) { |
6cbf8214 | 1967 | __pci_enable_wake(dev, target_state, true, false); |
448bd857 HY |
1968 | dev->runtime_d3cold = false; |
1969 | } | |
6cbf8214 RW |
1970 | |
1971 | return error; | |
1972 | } | |
1973 | ||
b67ea761 RW |
1974 | /** |
1975 | * pci_dev_run_wake - Check if device can generate run-time wake-up events. | |
1976 | * @dev: Device to check. | |
1977 | * | |
f7625980 | 1978 | * Return true if the device itself is capable of generating wake-up events |
b67ea761 RW |
1979 | * (through the platform or using the native PCIe PME) or if the device supports |
1980 | * PME and one of its upstream bridges can generate wake-up events. | |
1981 | */ | |
1982 | bool pci_dev_run_wake(struct pci_dev *dev) | |
1983 | { | |
1984 | struct pci_bus *bus = dev->bus; | |
1985 | ||
1986 | if (device_run_wake(&dev->dev)) | |
1987 | return true; | |
1988 | ||
1989 | if (!dev->pme_support) | |
1990 | return false; | |
1991 | ||
1992 | while (bus->parent) { | |
1993 | struct pci_dev *bridge = bus->self; | |
1994 | ||
1995 | if (device_run_wake(&bridge->dev)) | |
1996 | return true; | |
1997 | ||
1998 | bus = bus->parent; | |
1999 | } | |
2000 | ||
2001 | /* We have reached the root bus. */ | |
2002 | if (bus->bridge) | |
2003 | return device_run_wake(bus->bridge); | |
2004 | ||
2005 | return false; | |
2006 | } | |
2007 | EXPORT_SYMBOL_GPL(pci_dev_run_wake); | |
2008 | ||
bac2a909 RW |
2009 | /** |
2010 | * pci_dev_keep_suspended - Check if the device can stay in the suspended state. | |
2011 | * @pci_dev: Device to check. | |
2012 | * | |
2013 | * Return 'true' if the device is runtime-suspended, it doesn't have to be | |
2014 | * reconfigured due to wakeup settings difference between system and runtime | |
2015 | * suspend and the current power state of it is suitable for the upcoming | |
2016 | * (system) transition. | |
2017 | */ | |
2018 | bool pci_dev_keep_suspended(struct pci_dev *pci_dev) | |
2019 | { | |
2020 | struct device *dev = &pci_dev->dev; | |
2021 | ||
2022 | if (!pm_runtime_suspended(dev) | |
2023 | || (device_can_wakeup(dev) && !device_may_wakeup(dev)) | |
2024 | || platform_pci_need_resume(pci_dev)) | |
2025 | return false; | |
2026 | ||
2027 | return pci_target_state(pci_dev) == pci_dev->current_state; | |
2028 | } | |
2029 | ||
b3c32c4f HY |
2030 | void pci_config_pm_runtime_get(struct pci_dev *pdev) |
2031 | { | |
2032 | struct device *dev = &pdev->dev; | |
2033 | struct device *parent = dev->parent; | |
2034 | ||
2035 | if (parent) | |
2036 | pm_runtime_get_sync(parent); | |
2037 | pm_runtime_get_noresume(dev); | |
2038 | /* | |
2039 | * pdev->current_state is set to PCI_D3cold during suspending, | |
2040 | * so wait until suspending completes | |
2041 | */ | |
2042 | pm_runtime_barrier(dev); | |
2043 | /* | |
2044 | * Only need to resume devices in D3cold, because config | |
2045 | * registers are still accessible for devices suspended but | |
2046 | * not in D3cold. | |
2047 | */ | |
2048 | if (pdev->current_state == PCI_D3cold) | |
2049 | pm_runtime_resume(dev); | |
2050 | } | |
2051 | ||
2052 | void pci_config_pm_runtime_put(struct pci_dev *pdev) | |
2053 | { | |
2054 | struct device *dev = &pdev->dev; | |
2055 | struct device *parent = dev->parent; | |
2056 | ||
2057 | pm_runtime_put(dev); | |
2058 | if (parent) | |
2059 | pm_runtime_put_sync(parent); | |
2060 | } | |
2061 | ||
eb9d0fe4 RW |
2062 | /** |
2063 | * pci_pm_init - Initialize PM functions of given PCI device | |
2064 | * @dev: PCI device to handle. | |
2065 | */ | |
2066 | void pci_pm_init(struct pci_dev *dev) | |
2067 | { | |
2068 | int pm; | |
2069 | u16 pmc; | |
1da177e4 | 2070 | |
bb910a70 | 2071 | pm_runtime_forbid(&dev->dev); |
967577b0 HY |
2072 | pm_runtime_set_active(&dev->dev); |
2073 | pm_runtime_enable(&dev->dev); | |
a1e4d72c | 2074 | device_enable_async_suspend(&dev->dev); |
e80bb09d | 2075 | dev->wakeup_prepared = false; |
bb910a70 | 2076 | |
337001b6 | 2077 | dev->pm_cap = 0; |
ffaddbe8 | 2078 | dev->pme_support = 0; |
337001b6 | 2079 | |
eb9d0fe4 RW |
2080 | /* find PCI PM capability in list */ |
2081 | pm = pci_find_capability(dev, PCI_CAP_ID_PM); | |
2082 | if (!pm) | |
50246dd4 | 2083 | return; |
eb9d0fe4 RW |
2084 | /* Check device's ability to generate PME# */ |
2085 | pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc); | |
075c1771 | 2086 | |
eb9d0fe4 RW |
2087 | if ((pmc & PCI_PM_CAP_VER_MASK) > 3) { |
2088 | dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n", | |
2089 | pmc & PCI_PM_CAP_VER_MASK); | |
50246dd4 | 2090 | return; |
eb9d0fe4 RW |
2091 | } |
2092 | ||
337001b6 | 2093 | dev->pm_cap = pm; |
1ae861e6 | 2094 | dev->d3_delay = PCI_PM_D3_WAIT; |
448bd857 | 2095 | dev->d3cold_delay = PCI_PM_D3COLD_WAIT; |
4f9c1397 | 2096 | dev->d3cold_allowed = true; |
337001b6 RW |
2097 | |
2098 | dev->d1_support = false; | |
2099 | dev->d2_support = false; | |
2100 | if (!pci_no_d1d2(dev)) { | |
c9ed77ee | 2101 | if (pmc & PCI_PM_CAP_D1) |
337001b6 | 2102 | dev->d1_support = true; |
c9ed77ee | 2103 | if (pmc & PCI_PM_CAP_D2) |
337001b6 | 2104 | dev->d2_support = true; |
c9ed77ee BH |
2105 | |
2106 | if (dev->d1_support || dev->d2_support) | |
2107 | dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n", | |
ec84f126 JB |
2108 | dev->d1_support ? " D1" : "", |
2109 | dev->d2_support ? " D2" : ""); | |
337001b6 RW |
2110 | } |
2111 | ||
2112 | pmc &= PCI_PM_CAP_PME_MASK; | |
2113 | if (pmc) { | |
10c3d71d BH |
2114 | dev_printk(KERN_DEBUG, &dev->dev, |
2115 | "PME# supported from%s%s%s%s%s\n", | |
c9ed77ee BH |
2116 | (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "", |
2117 | (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "", | |
2118 | (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "", | |
2119 | (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "", | |
2120 | (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : ""); | |
337001b6 | 2121 | dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT; |
379021d5 | 2122 | dev->pme_poll = true; |
eb9d0fe4 RW |
2123 | /* |
2124 | * Make device's PM flags reflect the wake-up capability, but | |
2125 | * let the user space enable it to wake up the system as needed. | |
2126 | */ | |
2127 | device_set_wakeup_capable(&dev->dev, true); | |
eb9d0fe4 | 2128 | /* Disable the PME# generation functionality */ |
337001b6 | 2129 | pci_pme_active(dev, false); |
eb9d0fe4 | 2130 | } |
1da177e4 LT |
2131 | } |
2132 | ||
34a4876e YL |
2133 | static void pci_add_saved_cap(struct pci_dev *pci_dev, |
2134 | struct pci_cap_saved_state *new_cap) | |
2135 | { | |
2136 | hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space); | |
2137 | } | |
2138 | ||
63f4898a | 2139 | /** |
fd0f7f73 AW |
2140 | * _pci_add_cap_save_buffer - allocate buffer for saving given |
2141 | * capability registers | |
63f4898a RW |
2142 | * @dev: the PCI device |
2143 | * @cap: the capability to allocate the buffer for | |
fd0f7f73 | 2144 | * @extended: Standard or Extended capability ID |
63f4898a RW |
2145 | * @size: requested size of the buffer |
2146 | */ | |
fd0f7f73 AW |
2147 | static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap, |
2148 | bool extended, unsigned int size) | |
63f4898a RW |
2149 | { |
2150 | int pos; | |
2151 | struct pci_cap_saved_state *save_state; | |
2152 | ||
fd0f7f73 AW |
2153 | if (extended) |
2154 | pos = pci_find_ext_capability(dev, cap); | |
2155 | else | |
2156 | pos = pci_find_capability(dev, cap); | |
2157 | ||
63f4898a RW |
2158 | if (pos <= 0) |
2159 | return 0; | |
2160 | ||
2161 | save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL); | |
2162 | if (!save_state) | |
2163 | return -ENOMEM; | |
2164 | ||
24a4742f | 2165 | save_state->cap.cap_nr = cap; |
fd0f7f73 | 2166 | save_state->cap.cap_extended = extended; |
24a4742f | 2167 | save_state->cap.size = size; |
63f4898a RW |
2168 | pci_add_saved_cap(dev, save_state); |
2169 | ||
2170 | return 0; | |
2171 | } | |
2172 | ||
fd0f7f73 AW |
2173 | int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size) |
2174 | { | |
2175 | return _pci_add_cap_save_buffer(dev, cap, false, size); | |
2176 | } | |
2177 | ||
2178 | int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size) | |
2179 | { | |
2180 | return _pci_add_cap_save_buffer(dev, cap, true, size); | |
2181 | } | |
2182 | ||
63f4898a RW |
2183 | /** |
2184 | * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities | |
2185 | * @dev: the PCI device | |
2186 | */ | |
2187 | void pci_allocate_cap_save_buffers(struct pci_dev *dev) | |
2188 | { | |
2189 | int error; | |
2190 | ||
89858517 YZ |
2191 | error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP, |
2192 | PCI_EXP_SAVE_REGS * sizeof(u16)); | |
63f4898a RW |
2193 | if (error) |
2194 | dev_err(&dev->dev, | |
2195 | "unable to preallocate PCI Express save buffer\n"); | |
2196 | ||
2197 | error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16)); | |
2198 | if (error) | |
2199 | dev_err(&dev->dev, | |
2200 | "unable to preallocate PCI-X save buffer\n"); | |
425c1b22 AW |
2201 | |
2202 | pci_allocate_vc_save_buffers(dev); | |
63f4898a RW |
2203 | } |
2204 | ||
f796841e YL |
2205 | void pci_free_cap_save_buffers(struct pci_dev *dev) |
2206 | { | |
2207 | struct pci_cap_saved_state *tmp; | |
b67bfe0d | 2208 | struct hlist_node *n; |
f796841e | 2209 | |
b67bfe0d | 2210 | hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next) |
f796841e YL |
2211 | kfree(tmp); |
2212 | } | |
2213 | ||
58c3a727 | 2214 | /** |
31ab2476 | 2215 | * pci_configure_ari - enable or disable ARI forwarding |
58c3a727 | 2216 | * @dev: the PCI device |
b0cc6020 YW |
2217 | * |
2218 | * If @dev and its upstream bridge both support ARI, enable ARI in the | |
2219 | * bridge. Otherwise, disable ARI in the bridge. | |
58c3a727 | 2220 | */ |
31ab2476 | 2221 | void pci_configure_ari(struct pci_dev *dev) |
58c3a727 | 2222 | { |
58c3a727 | 2223 | u32 cap; |
8113587c | 2224 | struct pci_dev *bridge; |
58c3a727 | 2225 | |
6748dcc2 | 2226 | if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn) |
58c3a727 YZ |
2227 | return; |
2228 | ||
8113587c | 2229 | bridge = dev->bus->self; |
cb97ae34 | 2230 | if (!bridge) |
8113587c ZY |
2231 | return; |
2232 | ||
59875ae4 | 2233 | pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap); |
58c3a727 YZ |
2234 | if (!(cap & PCI_EXP_DEVCAP2_ARI)) |
2235 | return; | |
2236 | ||
b0cc6020 YW |
2237 | if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) { |
2238 | pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2, | |
2239 | PCI_EXP_DEVCTL2_ARI); | |
2240 | bridge->ari_enabled = 1; | |
2241 | } else { | |
2242 | pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2, | |
2243 | PCI_EXP_DEVCTL2_ARI); | |
2244 | bridge->ari_enabled = 0; | |
2245 | } | |
58c3a727 YZ |
2246 | } |
2247 | ||
5d990b62 CW |
2248 | static int pci_acs_enable; |
2249 | ||
2250 | /** | |
2251 | * pci_request_acs - ask for ACS to be enabled if supported | |
2252 | */ | |
2253 | void pci_request_acs(void) | |
2254 | { | |
2255 | pci_acs_enable = 1; | |
2256 | } | |
2257 | ||
ae21ee65 | 2258 | /** |
2c744244 | 2259 | * pci_std_enable_acs - enable ACS on devices using standard ACS capabilites |
ae21ee65 AK |
2260 | * @dev: the PCI device |
2261 | */ | |
2c744244 | 2262 | static int pci_std_enable_acs(struct pci_dev *dev) |
ae21ee65 AK |
2263 | { |
2264 | int pos; | |
2265 | u16 cap; | |
2266 | u16 ctrl; | |
2267 | ||
ae21ee65 AK |
2268 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); |
2269 | if (!pos) | |
2c744244 | 2270 | return -ENODEV; |
ae21ee65 AK |
2271 | |
2272 | pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap); | |
2273 | pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl); | |
2274 | ||
2275 | /* Source Validation */ | |
2276 | ctrl |= (cap & PCI_ACS_SV); | |
2277 | ||
2278 | /* P2P Request Redirect */ | |
2279 | ctrl |= (cap & PCI_ACS_RR); | |
2280 | ||
2281 | /* P2P Completion Redirect */ | |
2282 | ctrl |= (cap & PCI_ACS_CR); | |
2283 | ||
2284 | /* Upstream Forwarding */ | |
2285 | ctrl |= (cap & PCI_ACS_UF); | |
2286 | ||
2287 | pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl); | |
2c744244 AW |
2288 | |
2289 | return 0; | |
2290 | } | |
2291 | ||
2292 | /** | |
2293 | * pci_enable_acs - enable ACS if hardware support it | |
2294 | * @dev: the PCI device | |
2295 | */ | |
2296 | void pci_enable_acs(struct pci_dev *dev) | |
2297 | { | |
2298 | if (!pci_acs_enable) | |
2299 | return; | |
2300 | ||
2301 | if (!pci_std_enable_acs(dev)) | |
2302 | return; | |
2303 | ||
2304 | pci_dev_specific_enable_acs(dev); | |
ae21ee65 AK |
2305 | } |
2306 | ||
0a67119f AW |
2307 | static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags) |
2308 | { | |
2309 | int pos; | |
83db7e0b | 2310 | u16 cap, ctrl; |
0a67119f AW |
2311 | |
2312 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS); | |
2313 | if (!pos) | |
2314 | return false; | |
2315 | ||
83db7e0b AW |
2316 | /* |
2317 | * Except for egress control, capabilities are either required | |
2318 | * or only required if controllable. Features missing from the | |
2319 | * capability field can therefore be assumed as hard-wired enabled. | |
2320 | */ | |
2321 | pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap); | |
2322 | acs_flags &= (cap | PCI_ACS_EC); | |
2323 | ||
0a67119f AW |
2324 | pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl); |
2325 | return (ctrl & acs_flags) == acs_flags; | |
2326 | } | |
2327 | ||
ad805758 AW |
2328 | /** |
2329 | * pci_acs_enabled - test ACS against required flags for a given device | |
2330 | * @pdev: device to test | |
2331 | * @acs_flags: required PCI ACS flags | |
2332 | * | |
2333 | * Return true if the device supports the provided flags. Automatically | |
2334 | * filters out flags that are not implemented on multifunction devices. | |
0a67119f AW |
2335 | * |
2336 | * Note that this interface checks the effective ACS capabilities of the | |
2337 | * device rather than the actual capabilities. For instance, most single | |
2338 | * function endpoints are not required to support ACS because they have no | |
2339 | * opportunity for peer-to-peer access. We therefore return 'true' | |
2340 | * regardless of whether the device exposes an ACS capability. This makes | |
2341 | * it much easier for callers of this function to ignore the actual type | |
2342 | * or topology of the device when testing ACS support. | |
ad805758 AW |
2343 | */ |
2344 | bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags) | |
2345 | { | |
0a67119f | 2346 | int ret; |
ad805758 AW |
2347 | |
2348 | ret = pci_dev_specific_acs_enabled(pdev, acs_flags); | |
2349 | if (ret >= 0) | |
2350 | return ret > 0; | |
2351 | ||
0a67119f AW |
2352 | /* |
2353 | * Conventional PCI and PCI-X devices never support ACS, either | |
2354 | * effectively or actually. The shared bus topology implies that | |
2355 | * any device on the bus can receive or snoop DMA. | |
2356 | */ | |
ad805758 AW |
2357 | if (!pci_is_pcie(pdev)) |
2358 | return false; | |
2359 | ||
0a67119f AW |
2360 | switch (pci_pcie_type(pdev)) { |
2361 | /* | |
2362 | * PCI/X-to-PCIe bridges are not specifically mentioned by the spec, | |
f7625980 | 2363 | * but since their primary interface is PCI/X, we conservatively |
0a67119f AW |
2364 | * handle them as we would a non-PCIe device. |
2365 | */ | |
2366 | case PCI_EXP_TYPE_PCIE_BRIDGE: | |
2367 | /* | |
2368 | * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never | |
2369 | * applicable... must never implement an ACS Extended Capability...". | |
2370 | * This seems arbitrary, but we take a conservative interpretation | |
2371 | * of this statement. | |
2372 | */ | |
2373 | case PCI_EXP_TYPE_PCI_BRIDGE: | |
2374 | case PCI_EXP_TYPE_RC_EC: | |
2375 | return false; | |
2376 | /* | |
2377 | * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should | |
2378 | * implement ACS in order to indicate their peer-to-peer capabilities, | |
2379 | * regardless of whether they are single- or multi-function devices. | |
2380 | */ | |
2381 | case PCI_EXP_TYPE_DOWNSTREAM: | |
2382 | case PCI_EXP_TYPE_ROOT_PORT: | |
2383 | return pci_acs_flags_enabled(pdev, acs_flags); | |
2384 | /* | |
2385 | * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be | |
2386 | * implemented by the remaining PCIe types to indicate peer-to-peer | |
f7625980 | 2387 | * capabilities, but only when they are part of a multifunction |
0a67119f AW |
2388 | * device. The footnote for section 6.12 indicates the specific |
2389 | * PCIe types included here. | |
2390 | */ | |
2391 | case PCI_EXP_TYPE_ENDPOINT: | |
2392 | case PCI_EXP_TYPE_UPSTREAM: | |
2393 | case PCI_EXP_TYPE_LEG_END: | |
2394 | case PCI_EXP_TYPE_RC_END: | |
2395 | if (!pdev->multifunction) | |
2396 | break; | |
2397 | ||
0a67119f | 2398 | return pci_acs_flags_enabled(pdev, acs_flags); |
ad805758 AW |
2399 | } |
2400 | ||
0a67119f | 2401 | /* |
f7625980 | 2402 | * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable |
0a67119f AW |
2403 | * to single function devices with the exception of downstream ports. |
2404 | */ | |
ad805758 AW |
2405 | return true; |
2406 | } | |
2407 | ||
2408 | /** | |
2409 | * pci_acs_path_enable - test ACS flags from start to end in a hierarchy | |
2410 | * @start: starting downstream device | |
2411 | * @end: ending upstream device or NULL to search to the root bus | |
2412 | * @acs_flags: required flags | |
2413 | * | |
2414 | * Walk up a device tree from start to end testing PCI ACS support. If | |
2415 | * any step along the way does not support the required flags, return false. | |
2416 | */ | |
2417 | bool pci_acs_path_enabled(struct pci_dev *start, | |
2418 | struct pci_dev *end, u16 acs_flags) | |
2419 | { | |
2420 | struct pci_dev *pdev, *parent = start; | |
2421 | ||
2422 | do { | |
2423 | pdev = parent; | |
2424 | ||
2425 | if (!pci_acs_enabled(pdev, acs_flags)) | |
2426 | return false; | |
2427 | ||
2428 | if (pci_is_root_bus(pdev->bus)) | |
2429 | return (end == NULL); | |
2430 | ||
2431 | parent = pdev->bus->self; | |
2432 | } while (pdev != end); | |
2433 | ||
2434 | return true; | |
2435 | } | |
2436 | ||
57c2cf71 BH |
2437 | /** |
2438 | * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge | |
2439 | * @dev: the PCI device | |
bb5c2de2 | 2440 | * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD) |
57c2cf71 BH |
2441 | * |
2442 | * Perform INTx swizzling for a device behind one level of bridge. This is | |
2443 | * required by section 9.1 of the PCI-to-PCI bridge specification for devices | |
46b952a3 MW |
2444 | * behind bridges on add-in cards. For devices with ARI enabled, the slot |
2445 | * number is always 0 (see the Implementation Note in section 2.2.8.1 of | |
2446 | * the PCI Express Base Specification, Revision 2.1) | |
57c2cf71 | 2447 | */ |
3df425f3 | 2448 | u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin) |
57c2cf71 | 2449 | { |
46b952a3 MW |
2450 | int slot; |
2451 | ||
2452 | if (pci_ari_enabled(dev->bus)) | |
2453 | slot = 0; | |
2454 | else | |
2455 | slot = PCI_SLOT(dev->devfn); | |
2456 | ||
2457 | return (((pin - 1) + slot) % 4) + 1; | |
57c2cf71 BH |
2458 | } |
2459 | ||
3c78bc61 | 2460 | int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge) |
1da177e4 LT |
2461 | { |
2462 | u8 pin; | |
2463 | ||
514d207d | 2464 | pin = dev->pin; |
1da177e4 LT |
2465 | if (!pin) |
2466 | return -1; | |
878f2e50 | 2467 | |
8784fd4d | 2468 | while (!pci_is_root_bus(dev->bus)) { |
57c2cf71 | 2469 | pin = pci_swizzle_interrupt_pin(dev, pin); |
1da177e4 LT |
2470 | dev = dev->bus->self; |
2471 | } | |
2472 | *bridge = dev; | |
2473 | return pin; | |
2474 | } | |
2475 | ||
68feac87 BH |
2476 | /** |
2477 | * pci_common_swizzle - swizzle INTx all the way to root bridge | |
2478 | * @dev: the PCI device | |
2479 | * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD) | |
2480 | * | |
2481 | * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI | |
2482 | * bridges all the way up to a PCI root bus. | |
2483 | */ | |
2484 | u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp) | |
2485 | { | |
2486 | u8 pin = *pinp; | |
2487 | ||
1eb39487 | 2488 | while (!pci_is_root_bus(dev->bus)) { |
68feac87 BH |
2489 | pin = pci_swizzle_interrupt_pin(dev, pin); |
2490 | dev = dev->bus->self; | |
2491 | } | |
2492 | *pinp = pin; | |
2493 | return PCI_SLOT(dev->devfn); | |
2494 | } | |
2495 | ||
1da177e4 LT |
2496 | /** |
2497 | * pci_release_region - Release a PCI bar | |
2498 | * @pdev: PCI device whose resources were previously reserved by pci_request_region | |
2499 | * @bar: BAR to release | |
2500 | * | |
2501 | * Releases the PCI I/O and memory resources previously reserved by a | |
2502 | * successful call to pci_request_region. Call this function only | |
2503 | * after all use of the PCI regions has ceased. | |
2504 | */ | |
2505 | void pci_release_region(struct pci_dev *pdev, int bar) | |
2506 | { | |
9ac7849e TH |
2507 | struct pci_devres *dr; |
2508 | ||
1da177e4 LT |
2509 | if (pci_resource_len(pdev, bar) == 0) |
2510 | return; | |
2511 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) | |
2512 | release_region(pci_resource_start(pdev, bar), | |
2513 | pci_resource_len(pdev, bar)); | |
2514 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) | |
2515 | release_mem_region(pci_resource_start(pdev, bar), | |
2516 | pci_resource_len(pdev, bar)); | |
9ac7849e TH |
2517 | |
2518 | dr = find_pci_dr(pdev); | |
2519 | if (dr) | |
2520 | dr->region_mask &= ~(1 << bar); | |
1da177e4 | 2521 | } |
b7fe9434 | 2522 | EXPORT_SYMBOL(pci_release_region); |
1da177e4 LT |
2523 | |
2524 | /** | |
f5ddcac4 | 2525 | * __pci_request_region - Reserved PCI I/O and memory resource |
1da177e4 LT |
2526 | * @pdev: PCI device whose resources are to be reserved |
2527 | * @bar: BAR to be reserved | |
2528 | * @res_name: Name to be associated with resource. | |
f5ddcac4 | 2529 | * @exclusive: whether the region access is exclusive or not |
1da177e4 LT |
2530 | * |
2531 | * Mark the PCI region associated with PCI device @pdev BR @bar as | |
2532 | * being reserved by owner @res_name. Do not access any | |
2533 | * address inside the PCI regions unless this call returns | |
2534 | * successfully. | |
2535 | * | |
f5ddcac4 RD |
2536 | * If @exclusive is set, then the region is marked so that userspace |
2537 | * is explicitly not allowed to map the resource via /dev/mem or | |
f7625980 | 2538 | * sysfs MMIO access. |
f5ddcac4 | 2539 | * |
1da177e4 LT |
2540 | * Returns 0 on success, or %EBUSY on error. A warning |
2541 | * message is also printed on failure. | |
2542 | */ | |
3c78bc61 RD |
2543 | static int __pci_request_region(struct pci_dev *pdev, int bar, |
2544 | const char *res_name, int exclusive) | |
1da177e4 | 2545 | { |
9ac7849e TH |
2546 | struct pci_devres *dr; |
2547 | ||
1da177e4 LT |
2548 | if (pci_resource_len(pdev, bar) == 0) |
2549 | return 0; | |
f7625980 | 2550 | |
1da177e4 LT |
2551 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) { |
2552 | if (!request_region(pci_resource_start(pdev, bar), | |
2553 | pci_resource_len(pdev, bar), res_name)) | |
2554 | goto err_out; | |
3c78bc61 | 2555 | } else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { |
e8de1481 AV |
2556 | if (!__request_mem_region(pci_resource_start(pdev, bar), |
2557 | pci_resource_len(pdev, bar), res_name, | |
2558 | exclusive)) | |
1da177e4 LT |
2559 | goto err_out; |
2560 | } | |
9ac7849e TH |
2561 | |
2562 | dr = find_pci_dr(pdev); | |
2563 | if (dr) | |
2564 | dr->region_mask |= 1 << bar; | |
2565 | ||
1da177e4 LT |
2566 | return 0; |
2567 | ||
2568 | err_out: | |
c7dabef8 | 2569 | dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar, |
096e6f67 | 2570 | &pdev->resource[bar]); |
1da177e4 LT |
2571 | return -EBUSY; |
2572 | } | |
2573 | ||
e8de1481 | 2574 | /** |
f5ddcac4 | 2575 | * pci_request_region - Reserve PCI I/O and memory resource |
e8de1481 AV |
2576 | * @pdev: PCI device whose resources are to be reserved |
2577 | * @bar: BAR to be reserved | |
f5ddcac4 | 2578 | * @res_name: Name to be associated with resource |
e8de1481 | 2579 | * |
f5ddcac4 | 2580 | * Mark the PCI region associated with PCI device @pdev BAR @bar as |
e8de1481 AV |
2581 | * being reserved by owner @res_name. Do not access any |
2582 | * address inside the PCI regions unless this call returns | |
2583 | * successfully. | |
2584 | * | |
2585 | * Returns 0 on success, or %EBUSY on error. A warning | |
2586 | * message is also printed on failure. | |
2587 | */ | |
2588 | int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) | |
2589 | { | |
2590 | return __pci_request_region(pdev, bar, res_name, 0); | |
2591 | } | |
b7fe9434 | 2592 | EXPORT_SYMBOL(pci_request_region); |
e8de1481 AV |
2593 | |
2594 | /** | |
2595 | * pci_request_region_exclusive - Reserved PCI I/O and memory resource | |
2596 | * @pdev: PCI device whose resources are to be reserved | |
2597 | * @bar: BAR to be reserved | |
2598 | * @res_name: Name to be associated with resource. | |
2599 | * | |
2600 | * Mark the PCI region associated with PCI device @pdev BR @bar as | |
2601 | * being reserved by owner @res_name. Do not access any | |
2602 | * address inside the PCI regions unless this call returns | |
2603 | * successfully. | |
2604 | * | |
2605 | * Returns 0 on success, or %EBUSY on error. A warning | |
2606 | * message is also printed on failure. | |
2607 | * | |
2608 | * The key difference that _exclusive makes it that userspace is | |
2609 | * explicitly not allowed to map the resource via /dev/mem or | |
f7625980 | 2610 | * sysfs. |
e8de1481 | 2611 | */ |
3c78bc61 RD |
2612 | int pci_request_region_exclusive(struct pci_dev *pdev, int bar, |
2613 | const char *res_name) | |
e8de1481 AV |
2614 | { |
2615 | return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE); | |
2616 | } | |
b7fe9434 RD |
2617 | EXPORT_SYMBOL(pci_request_region_exclusive); |
2618 | ||
c87deff7 HS |
2619 | /** |
2620 | * pci_release_selected_regions - Release selected PCI I/O and memory resources | |
2621 | * @pdev: PCI device whose resources were previously reserved | |
2622 | * @bars: Bitmask of BARs to be released | |
2623 | * | |
2624 | * Release selected PCI I/O and memory resources previously reserved. | |
2625 | * Call this function only after all use of the PCI regions has ceased. | |
2626 | */ | |
2627 | void pci_release_selected_regions(struct pci_dev *pdev, int bars) | |
2628 | { | |
2629 | int i; | |
2630 | ||
2631 | for (i = 0; i < 6; i++) | |
2632 | if (bars & (1 << i)) | |
2633 | pci_release_region(pdev, i); | |
2634 | } | |
b7fe9434 | 2635 | EXPORT_SYMBOL(pci_release_selected_regions); |
c87deff7 | 2636 | |
9738abed | 2637 | static int __pci_request_selected_regions(struct pci_dev *pdev, int bars, |
3c78bc61 | 2638 | const char *res_name, int excl) |
c87deff7 HS |
2639 | { |
2640 | int i; | |
2641 | ||
2642 | for (i = 0; i < 6; i++) | |
2643 | if (bars & (1 << i)) | |
e8de1481 | 2644 | if (__pci_request_region(pdev, i, res_name, excl)) |
c87deff7 HS |
2645 | goto err_out; |
2646 | return 0; | |
2647 | ||
2648 | err_out: | |
3c78bc61 | 2649 | while (--i >= 0) |
c87deff7 HS |
2650 | if (bars & (1 << i)) |
2651 | pci_release_region(pdev, i); | |
2652 | ||
2653 | return -EBUSY; | |
2654 | } | |
1da177e4 | 2655 | |
e8de1481 AV |
2656 | |
2657 | /** | |
2658 | * pci_request_selected_regions - Reserve selected PCI I/O and memory resources | |
2659 | * @pdev: PCI device whose resources are to be reserved | |
2660 | * @bars: Bitmask of BARs to be requested | |
2661 | * @res_name: Name to be associated with resource | |
2662 | */ | |
2663 | int pci_request_selected_regions(struct pci_dev *pdev, int bars, | |
2664 | const char *res_name) | |
2665 | { | |
2666 | return __pci_request_selected_regions(pdev, bars, res_name, 0); | |
2667 | } | |
b7fe9434 | 2668 | EXPORT_SYMBOL(pci_request_selected_regions); |
e8de1481 | 2669 | |
3c78bc61 RD |
2670 | int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars, |
2671 | const char *res_name) | |
e8de1481 AV |
2672 | { |
2673 | return __pci_request_selected_regions(pdev, bars, res_name, | |
2674 | IORESOURCE_EXCLUSIVE); | |
2675 | } | |
b7fe9434 | 2676 | EXPORT_SYMBOL(pci_request_selected_regions_exclusive); |
e8de1481 | 2677 | |
1da177e4 LT |
2678 | /** |
2679 | * pci_release_regions - Release reserved PCI I/O and memory resources | |
2680 | * @pdev: PCI device whose resources were previously reserved by pci_request_regions | |
2681 | * | |
2682 | * Releases all PCI I/O and memory resources previously reserved by a | |
2683 | * successful call to pci_request_regions. Call this function only | |
2684 | * after all use of the PCI regions has ceased. | |
2685 | */ | |
2686 | ||
2687 | void pci_release_regions(struct pci_dev *pdev) | |
2688 | { | |
c87deff7 | 2689 | pci_release_selected_regions(pdev, (1 << 6) - 1); |
1da177e4 | 2690 | } |
b7fe9434 | 2691 | EXPORT_SYMBOL(pci_release_regions); |
1da177e4 LT |
2692 | |
2693 | /** | |
2694 | * pci_request_regions - Reserved PCI I/O and memory resources | |
2695 | * @pdev: PCI device whose resources are to be reserved | |
2696 | * @res_name: Name to be associated with resource. | |
2697 | * | |
2698 | * Mark all PCI regions associated with PCI device @pdev as | |
2699 | * being reserved by owner @res_name. Do not access any | |
2700 | * address inside the PCI regions unless this call returns | |
2701 | * successfully. | |
2702 | * | |
2703 | * Returns 0 on success, or %EBUSY on error. A warning | |
2704 | * message is also printed on failure. | |
2705 | */ | |
3c990e92 | 2706 | int pci_request_regions(struct pci_dev *pdev, const char *res_name) |
1da177e4 | 2707 | { |
c87deff7 | 2708 | return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name); |
1da177e4 | 2709 | } |
b7fe9434 | 2710 | EXPORT_SYMBOL(pci_request_regions); |
1da177e4 | 2711 | |
e8de1481 AV |
2712 | /** |
2713 | * pci_request_regions_exclusive - Reserved PCI I/O and memory resources | |
2714 | * @pdev: PCI device whose resources are to be reserved | |
2715 | * @res_name: Name to be associated with resource. | |
2716 | * | |
2717 | * Mark all PCI regions associated with PCI device @pdev as | |
2718 | * being reserved by owner @res_name. Do not access any | |
2719 | * address inside the PCI regions unless this call returns | |
2720 | * successfully. | |
2721 | * | |
2722 | * pci_request_regions_exclusive() will mark the region so that | |
f7625980 | 2723 | * /dev/mem and the sysfs MMIO access will not be allowed. |
e8de1481 AV |
2724 | * |
2725 | * Returns 0 on success, or %EBUSY on error. A warning | |
2726 | * message is also printed on failure. | |
2727 | */ | |
2728 | int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name) | |
2729 | { | |
2730 | return pci_request_selected_regions_exclusive(pdev, | |
2731 | ((1 << 6) - 1), res_name); | |
2732 | } | |
b7fe9434 | 2733 | EXPORT_SYMBOL(pci_request_regions_exclusive); |
e8de1481 | 2734 | |
8b921acf LD |
2735 | /** |
2736 | * pci_remap_iospace - Remap the memory mapped I/O space | |
2737 | * @res: Resource describing the I/O space | |
2738 | * @phys_addr: physical address of range to be mapped | |
2739 | * | |
2740 | * Remap the memory mapped I/O space described by the @res | |
2741 | * and the CPU physical address @phys_addr into virtual address space. | |
2742 | * Only architectures that have memory mapped IO functions defined | |
2743 | * (and the PCI_IOBASE value defined) should call this function. | |
2744 | */ | |
2745 | int __weak pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr) | |
2746 | { | |
2747 | #if defined(PCI_IOBASE) && defined(CONFIG_MMU) | |
2748 | unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start; | |
2749 | ||
2750 | if (!(res->flags & IORESOURCE_IO)) | |
2751 | return -EINVAL; | |
2752 | ||
2753 | if (res->end > IO_SPACE_LIMIT) | |
2754 | return -EINVAL; | |
2755 | ||
2756 | return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr, | |
2757 | pgprot_device(PAGE_KERNEL)); | |
2758 | #else | |
2759 | /* this architecture does not have memory mapped I/O space, | |
2760 | so this function should never be called */ | |
2761 | WARN_ONCE(1, "This architecture does not support memory mapped I/O\n"); | |
2762 | return -ENODEV; | |
2763 | #endif | |
2764 | } | |
2765 | ||
6a479079 BH |
2766 | static void __pci_set_master(struct pci_dev *dev, bool enable) |
2767 | { | |
2768 | u16 old_cmd, cmd; | |
2769 | ||
2770 | pci_read_config_word(dev, PCI_COMMAND, &old_cmd); | |
2771 | if (enable) | |
2772 | cmd = old_cmd | PCI_COMMAND_MASTER; | |
2773 | else | |
2774 | cmd = old_cmd & ~PCI_COMMAND_MASTER; | |
2775 | if (cmd != old_cmd) { | |
2776 | dev_dbg(&dev->dev, "%s bus mastering\n", | |
2777 | enable ? "enabling" : "disabling"); | |
2778 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
2779 | } | |
2780 | dev->is_busmaster = enable; | |
2781 | } | |
e8de1481 | 2782 | |
2b6f2c35 MS |
2783 | /** |
2784 | * pcibios_setup - process "pci=" kernel boot arguments | |
2785 | * @str: string used to pass in "pci=" kernel boot arguments | |
2786 | * | |
2787 | * Process kernel boot arguments. This is the default implementation. | |
2788 | * Architecture specific implementations can override this as necessary. | |
2789 | */ | |
2790 | char * __weak __init pcibios_setup(char *str) | |
2791 | { | |
2792 | return str; | |
2793 | } | |
2794 | ||
96c55900 MS |
2795 | /** |
2796 | * pcibios_set_master - enable PCI bus-mastering for device dev | |
2797 | * @dev: the PCI device to enable | |
2798 | * | |
2799 | * Enables PCI bus-mastering for the device. This is the default | |
2800 | * implementation. Architecture specific implementations can override | |
2801 | * this if necessary. | |
2802 | */ | |
2803 | void __weak pcibios_set_master(struct pci_dev *dev) | |
2804 | { | |
2805 | u8 lat; | |
2806 | ||
f676678f MS |
2807 | /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */ |
2808 | if (pci_is_pcie(dev)) | |
2809 | return; | |
2810 | ||
96c55900 MS |
2811 | pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); |
2812 | if (lat < 16) | |
2813 | lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency; | |
2814 | else if (lat > pcibios_max_latency) | |
2815 | lat = pcibios_max_latency; | |
2816 | else | |
2817 | return; | |
a006482b | 2818 | |
96c55900 MS |
2819 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); |
2820 | } | |
2821 | ||
1da177e4 LT |
2822 | /** |
2823 | * pci_set_master - enables bus-mastering for device dev | |
2824 | * @dev: the PCI device to enable | |
2825 | * | |
2826 | * Enables bus-mastering on the device and calls pcibios_set_master() | |
2827 | * to do the needed arch specific settings. | |
2828 | */ | |
6a479079 | 2829 | void pci_set_master(struct pci_dev *dev) |
1da177e4 | 2830 | { |
6a479079 | 2831 | __pci_set_master(dev, true); |
1da177e4 LT |
2832 | pcibios_set_master(dev); |
2833 | } | |
b7fe9434 | 2834 | EXPORT_SYMBOL(pci_set_master); |
1da177e4 | 2835 | |
6a479079 BH |
2836 | /** |
2837 | * pci_clear_master - disables bus-mastering for device dev | |
2838 | * @dev: the PCI device to disable | |
2839 | */ | |
2840 | void pci_clear_master(struct pci_dev *dev) | |
2841 | { | |
2842 | __pci_set_master(dev, false); | |
2843 | } | |
b7fe9434 | 2844 | EXPORT_SYMBOL(pci_clear_master); |
6a479079 | 2845 | |
1da177e4 | 2846 | /** |
edb2d97e MW |
2847 | * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed |
2848 | * @dev: the PCI device for which MWI is to be enabled | |
1da177e4 | 2849 | * |
edb2d97e MW |
2850 | * Helper function for pci_set_mwi. |
2851 | * Originally copied from drivers/net/acenic.c. | |
1da177e4 LT |
2852 | * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. |
2853 | * | |
2854 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
2855 | */ | |
15ea76d4 | 2856 | int pci_set_cacheline_size(struct pci_dev *dev) |
1da177e4 LT |
2857 | { |
2858 | u8 cacheline_size; | |
2859 | ||
2860 | if (!pci_cache_line_size) | |
15ea76d4 | 2861 | return -EINVAL; |
1da177e4 LT |
2862 | |
2863 | /* Validate current setting: the PCI_CACHE_LINE_SIZE must be | |
2864 | equal to or multiple of the right value. */ | |
2865 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
2866 | if (cacheline_size >= pci_cache_line_size && | |
2867 | (cacheline_size % pci_cache_line_size) == 0) | |
2868 | return 0; | |
2869 | ||
2870 | /* Write the correct value. */ | |
2871 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size); | |
2872 | /* Read it back. */ | |
2873 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
2874 | if (cacheline_size == pci_cache_line_size) | |
2875 | return 0; | |
2876 | ||
227f0647 RD |
2877 | dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not supported\n", |
2878 | pci_cache_line_size << 2); | |
1da177e4 LT |
2879 | |
2880 | return -EINVAL; | |
2881 | } | |
15ea76d4 TH |
2882 | EXPORT_SYMBOL_GPL(pci_set_cacheline_size); |
2883 | ||
1da177e4 LT |
2884 | /** |
2885 | * pci_set_mwi - enables memory-write-invalidate PCI transaction | |
2886 | * @dev: the PCI device for which MWI is enabled | |
2887 | * | |
694625c0 | 2888 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. |
1da177e4 LT |
2889 | * |
2890 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
2891 | */ | |
3c78bc61 | 2892 | int pci_set_mwi(struct pci_dev *dev) |
1da177e4 | 2893 | { |
b7fe9434 RD |
2894 | #ifdef PCI_DISABLE_MWI |
2895 | return 0; | |
2896 | #else | |
1da177e4 LT |
2897 | int rc; |
2898 | u16 cmd; | |
2899 | ||
edb2d97e | 2900 | rc = pci_set_cacheline_size(dev); |
1da177e4 LT |
2901 | if (rc) |
2902 | return rc; | |
2903 | ||
2904 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
3c78bc61 | 2905 | if (!(cmd & PCI_COMMAND_INVALIDATE)) { |
80ccba11 | 2906 | dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n"); |
1da177e4 LT |
2907 | cmd |= PCI_COMMAND_INVALIDATE; |
2908 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
2909 | } | |
1da177e4 | 2910 | return 0; |
b7fe9434 | 2911 | #endif |
1da177e4 | 2912 | } |
b7fe9434 | 2913 | EXPORT_SYMBOL(pci_set_mwi); |
1da177e4 | 2914 | |
694625c0 RD |
2915 | /** |
2916 | * pci_try_set_mwi - enables memory-write-invalidate PCI transaction | |
2917 | * @dev: the PCI device for which MWI is enabled | |
2918 | * | |
2919 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. | |
2920 | * Callers are not required to check the return value. | |
2921 | * | |
2922 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
2923 | */ | |
2924 | int pci_try_set_mwi(struct pci_dev *dev) | |
2925 | { | |
b7fe9434 RD |
2926 | #ifdef PCI_DISABLE_MWI |
2927 | return 0; | |
2928 | #else | |
2929 | return pci_set_mwi(dev); | |
2930 | #endif | |
694625c0 | 2931 | } |
b7fe9434 | 2932 | EXPORT_SYMBOL(pci_try_set_mwi); |
694625c0 | 2933 | |
1da177e4 LT |
2934 | /** |
2935 | * pci_clear_mwi - disables Memory-Write-Invalidate for device dev | |
2936 | * @dev: the PCI device to disable | |
2937 | * | |
2938 | * Disables PCI Memory-Write-Invalidate transaction on the device | |
2939 | */ | |
3c78bc61 | 2940 | void pci_clear_mwi(struct pci_dev *dev) |
1da177e4 | 2941 | { |
b7fe9434 | 2942 | #ifndef PCI_DISABLE_MWI |
1da177e4 LT |
2943 | u16 cmd; |
2944 | ||
2945 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
2946 | if (cmd & PCI_COMMAND_INVALIDATE) { | |
2947 | cmd &= ~PCI_COMMAND_INVALIDATE; | |
2948 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
2949 | } | |
b7fe9434 | 2950 | #endif |
1da177e4 | 2951 | } |
b7fe9434 | 2952 | EXPORT_SYMBOL(pci_clear_mwi); |
1da177e4 | 2953 | |
a04ce0ff BR |
2954 | /** |
2955 | * pci_intx - enables/disables PCI INTx for device dev | |
8f7020d3 RD |
2956 | * @pdev: the PCI device to operate on |
2957 | * @enable: boolean: whether to enable or disable PCI INTx | |
a04ce0ff BR |
2958 | * |
2959 | * Enables/disables PCI INTx for device dev | |
2960 | */ | |
3c78bc61 | 2961 | void pci_intx(struct pci_dev *pdev, int enable) |
a04ce0ff BR |
2962 | { |
2963 | u16 pci_command, new; | |
2964 | ||
2965 | pci_read_config_word(pdev, PCI_COMMAND, &pci_command); | |
2966 | ||
3c78bc61 | 2967 | if (enable) |
a04ce0ff | 2968 | new = pci_command & ~PCI_COMMAND_INTX_DISABLE; |
3c78bc61 | 2969 | else |
a04ce0ff | 2970 | new = pci_command | PCI_COMMAND_INTX_DISABLE; |
a04ce0ff BR |
2971 | |
2972 | if (new != pci_command) { | |
9ac7849e TH |
2973 | struct pci_devres *dr; |
2974 | ||
2fd9d74b | 2975 | pci_write_config_word(pdev, PCI_COMMAND, new); |
9ac7849e TH |
2976 | |
2977 | dr = find_pci_dr(pdev); | |
2978 | if (dr && !dr->restore_intx) { | |
2979 | dr->restore_intx = 1; | |
2980 | dr->orig_intx = !enable; | |
2981 | } | |
a04ce0ff BR |
2982 | } |
2983 | } | |
b7fe9434 | 2984 | EXPORT_SYMBOL_GPL(pci_intx); |
a04ce0ff | 2985 | |
a2e27787 JK |
2986 | /** |
2987 | * pci_intx_mask_supported - probe for INTx masking support | |
6e9292c5 | 2988 | * @dev: the PCI device to operate on |
a2e27787 JK |
2989 | * |
2990 | * Check if the device dev support INTx masking via the config space | |
2991 | * command word. | |
2992 | */ | |
2993 | bool pci_intx_mask_supported(struct pci_dev *dev) | |
2994 | { | |
2995 | bool mask_supported = false; | |
2996 | u16 orig, new; | |
2997 | ||
fbebb9fd BH |
2998 | if (dev->broken_intx_masking) |
2999 | return false; | |
3000 | ||
a2e27787 JK |
3001 | pci_cfg_access_lock(dev); |
3002 | ||
3003 | pci_read_config_word(dev, PCI_COMMAND, &orig); | |
3004 | pci_write_config_word(dev, PCI_COMMAND, | |
3005 | orig ^ PCI_COMMAND_INTX_DISABLE); | |
3006 | pci_read_config_word(dev, PCI_COMMAND, &new); | |
3007 | ||
3008 | /* | |
3009 | * There's no way to protect against hardware bugs or detect them | |
3010 | * reliably, but as long as we know what the value should be, let's | |
3011 | * go ahead and check it. | |
3012 | */ | |
3013 | if ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) { | |
227f0647 RD |
3014 | dev_err(&dev->dev, "Command register changed from 0x%x to 0x%x: driver or hardware bug?\n", |
3015 | orig, new); | |
a2e27787 JK |
3016 | } else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) { |
3017 | mask_supported = true; | |
3018 | pci_write_config_word(dev, PCI_COMMAND, orig); | |
3019 | } | |
3020 | ||
3021 | pci_cfg_access_unlock(dev); | |
3022 | return mask_supported; | |
3023 | } | |
3024 | EXPORT_SYMBOL_GPL(pci_intx_mask_supported); | |
3025 | ||
3026 | static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask) | |
3027 | { | |
3028 | struct pci_bus *bus = dev->bus; | |
3029 | bool mask_updated = true; | |
3030 | u32 cmd_status_dword; | |
3031 | u16 origcmd, newcmd; | |
3032 | unsigned long flags; | |
3033 | bool irq_pending; | |
3034 | ||
3035 | /* | |
3036 | * We do a single dword read to retrieve both command and status. | |
3037 | * Document assumptions that make this possible. | |
3038 | */ | |
3039 | BUILD_BUG_ON(PCI_COMMAND % 4); | |
3040 | BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS); | |
3041 | ||
3042 | raw_spin_lock_irqsave(&pci_lock, flags); | |
3043 | ||
3044 | bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword); | |
3045 | ||
3046 | irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT; | |
3047 | ||
3048 | /* | |
3049 | * Check interrupt status register to see whether our device | |
3050 | * triggered the interrupt (when masking) or the next IRQ is | |
3051 | * already pending (when unmasking). | |
3052 | */ | |
3053 | if (mask != irq_pending) { | |
3054 | mask_updated = false; | |
3055 | goto done; | |
3056 | } | |
3057 | ||
3058 | origcmd = cmd_status_dword; | |
3059 | newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE; | |
3060 | if (mask) | |
3061 | newcmd |= PCI_COMMAND_INTX_DISABLE; | |
3062 | if (newcmd != origcmd) | |
3063 | bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd); | |
3064 | ||
3065 | done: | |
3066 | raw_spin_unlock_irqrestore(&pci_lock, flags); | |
3067 | ||
3068 | return mask_updated; | |
3069 | } | |
3070 | ||
3071 | /** | |
3072 | * pci_check_and_mask_intx - mask INTx on pending interrupt | |
6e9292c5 | 3073 | * @dev: the PCI device to operate on |
a2e27787 JK |
3074 | * |
3075 | * Check if the device dev has its INTx line asserted, mask it and | |
3076 | * return true in that case. False is returned if not interrupt was | |
3077 | * pending. | |
3078 | */ | |
3079 | bool pci_check_and_mask_intx(struct pci_dev *dev) | |
3080 | { | |
3081 | return pci_check_and_set_intx_mask(dev, true); | |
3082 | } | |
3083 | EXPORT_SYMBOL_GPL(pci_check_and_mask_intx); | |
3084 | ||
3085 | /** | |
ebd50b93 | 3086 | * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending |
6e9292c5 | 3087 | * @dev: the PCI device to operate on |
a2e27787 JK |
3088 | * |
3089 | * Check if the device dev has its INTx line asserted, unmask it if not | |
3090 | * and return true. False is returned and the mask remains active if | |
3091 | * there was still an interrupt pending. | |
3092 | */ | |
3093 | bool pci_check_and_unmask_intx(struct pci_dev *dev) | |
3094 | { | |
3095 | return pci_check_and_set_intx_mask(dev, false); | |
3096 | } | |
3097 | EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx); | |
3098 | ||
f5f2b131 | 3099 | /** |
da27f4b3 | 3100 | * pci_msi_off - disables any MSI or MSI-X capabilities |
8d7d86e9 | 3101 | * @dev: the PCI device to operate on |
f5f2b131 | 3102 | * |
da27f4b3 BH |
3103 | * If you want to use MSI, see pci_enable_msi() and friends. |
3104 | * This is a lower-level primitive that allows us to disable | |
3105 | * MSI operation at the device level. | |
f5f2b131 EB |
3106 | */ |
3107 | void pci_msi_off(struct pci_dev *dev) | |
3108 | { | |
3109 | int pos; | |
3110 | u16 control; | |
3111 | ||
da27f4b3 BH |
3112 | /* |
3113 | * This looks like it could go in msi.c, but we need it even when | |
3114 | * CONFIG_PCI_MSI=n. For the same reason, we can't use | |
3115 | * dev->msi_cap or dev->msix_cap here. | |
3116 | */ | |
f5f2b131 EB |
3117 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); |
3118 | if (pos) { | |
3119 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); | |
3120 | control &= ~PCI_MSI_FLAGS_ENABLE; | |
3121 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); | |
3122 | } | |
3123 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
3124 | if (pos) { | |
3125 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); | |
3126 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
3127 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
3128 | } | |
3129 | } | |
b03214d5 | 3130 | EXPORT_SYMBOL_GPL(pci_msi_off); |
f5f2b131 | 3131 | |
4d57cdfa FT |
3132 | int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size) |
3133 | { | |
3134 | return dma_set_max_seg_size(&dev->dev, size); | |
3135 | } | |
3136 | EXPORT_SYMBOL(pci_set_dma_max_seg_size); | |
4d57cdfa | 3137 | |
59fc67de FT |
3138 | int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask) |
3139 | { | |
3140 | return dma_set_seg_boundary(&dev->dev, mask); | |
3141 | } | |
3142 | EXPORT_SYMBOL(pci_set_dma_seg_boundary); | |
59fc67de | 3143 | |
3775a209 CL |
3144 | /** |
3145 | * pci_wait_for_pending_transaction - waits for pending transaction | |
3146 | * @dev: the PCI device to operate on | |
3147 | * | |
3148 | * Return 0 if transaction is pending 1 otherwise. | |
3149 | */ | |
3150 | int pci_wait_for_pending_transaction(struct pci_dev *dev) | |
8dd7f803 | 3151 | { |
157e876f AW |
3152 | if (!pci_is_pcie(dev)) |
3153 | return 1; | |
8c1c699f | 3154 | |
d0b4cc4e GS |
3155 | return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA, |
3156 | PCI_EXP_DEVSTA_TRPND); | |
3775a209 CL |
3157 | } |
3158 | EXPORT_SYMBOL(pci_wait_for_pending_transaction); | |
3159 | ||
3160 | static int pcie_flr(struct pci_dev *dev, int probe) | |
3161 | { | |
3162 | u32 cap; | |
3163 | ||
3164 | pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); | |
3165 | if (!(cap & PCI_EXP_DEVCAP_FLR)) | |
3166 | return -ENOTTY; | |
3167 | ||
3168 | if (probe) | |
3169 | return 0; | |
3170 | ||
3171 | if (!pci_wait_for_pending_transaction(dev)) | |
bb383e28 | 3172 | dev_err(&dev->dev, "timed out waiting for pending transaction; performing function level reset anyway\n"); |
8c1c699f | 3173 | |
59875ae4 | 3174 | pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); |
8c1c699f | 3175 | msleep(100); |
8dd7f803 SY |
3176 | return 0; |
3177 | } | |
d91cdc74 | 3178 | |
8c1c699f | 3179 | static int pci_af_flr(struct pci_dev *dev, int probe) |
1ca88797 | 3180 | { |
8c1c699f | 3181 | int pos; |
1ca88797 SY |
3182 | u8 cap; |
3183 | ||
8c1c699f YZ |
3184 | pos = pci_find_capability(dev, PCI_CAP_ID_AF); |
3185 | if (!pos) | |
1ca88797 | 3186 | return -ENOTTY; |
8c1c699f YZ |
3187 | |
3188 | pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap); | |
1ca88797 SY |
3189 | if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR)) |
3190 | return -ENOTTY; | |
3191 | ||
3192 | if (probe) | |
3193 | return 0; | |
3194 | ||
d066c946 AW |
3195 | /* |
3196 | * Wait for Transaction Pending bit to clear. A word-aligned test | |
3197 | * is used, so we use the conrol offset rather than status and shift | |
3198 | * the test bit to match. | |
3199 | */ | |
bb383e28 | 3200 | if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL, |
d066c946 | 3201 | PCI_AF_STATUS_TP << 8)) |
bb383e28 | 3202 | dev_err(&dev->dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n"); |
5fe5db05 | 3203 | |
8c1c699f | 3204 | pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR); |
1ca88797 | 3205 | msleep(100); |
1ca88797 SY |
3206 | return 0; |
3207 | } | |
3208 | ||
83d74e03 RW |
3209 | /** |
3210 | * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0. | |
3211 | * @dev: Device to reset. | |
3212 | * @probe: If set, only check if the device can be reset this way. | |
3213 | * | |
3214 | * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is | |
3215 | * unset, it will be reinitialized internally when going from PCI_D3hot to | |
3216 | * PCI_D0. If that's the case and the device is not in a low-power state | |
3217 | * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset. | |
3218 | * | |
3219 | * NOTE: This causes the caller to sleep for twice the device power transition | |
3220 | * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms | |
f7625980 | 3221 | * by default (i.e. unless the @dev's d3_delay field has a different value). |
83d74e03 RW |
3222 | * Moreover, only devices in D0 can be reset by this function. |
3223 | */ | |
f85876ba | 3224 | static int pci_pm_reset(struct pci_dev *dev, int probe) |
d91cdc74 | 3225 | { |
f85876ba YZ |
3226 | u16 csr; |
3227 | ||
51e53738 | 3228 | if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET) |
f85876ba | 3229 | return -ENOTTY; |
d91cdc74 | 3230 | |
f85876ba YZ |
3231 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr); |
3232 | if (csr & PCI_PM_CTRL_NO_SOFT_RESET) | |
3233 | return -ENOTTY; | |
d91cdc74 | 3234 | |
f85876ba YZ |
3235 | if (probe) |
3236 | return 0; | |
1ca88797 | 3237 | |
f85876ba YZ |
3238 | if (dev->current_state != PCI_D0) |
3239 | return -EINVAL; | |
3240 | ||
3241 | csr &= ~PCI_PM_CTRL_STATE_MASK; | |
3242 | csr |= PCI_D3hot; | |
3243 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); | |
1ae861e6 | 3244 | pci_dev_d3_sleep(dev); |
f85876ba YZ |
3245 | |
3246 | csr &= ~PCI_PM_CTRL_STATE_MASK; | |
3247 | csr |= PCI_D0; | |
3248 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); | |
1ae861e6 | 3249 | pci_dev_d3_sleep(dev); |
f85876ba YZ |
3250 | |
3251 | return 0; | |
3252 | } | |
3253 | ||
9e33002f | 3254 | void pci_reset_secondary_bus(struct pci_dev *dev) |
c12ff1df YZ |
3255 | { |
3256 | u16 ctrl; | |
64e8674f AW |
3257 | |
3258 | pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl); | |
3259 | ctrl |= PCI_BRIDGE_CTL_BUS_RESET; | |
3260 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl); | |
de0c548c AW |
3261 | /* |
3262 | * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double | |
f7625980 | 3263 | * this to 2ms to ensure that we meet the minimum requirement. |
de0c548c AW |
3264 | */ |
3265 | msleep(2); | |
64e8674f AW |
3266 | |
3267 | ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; | |
3268 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl); | |
de0c548c AW |
3269 | |
3270 | /* | |
3271 | * Trhfa for conventional PCI is 2^25 clock cycles. | |
3272 | * Assuming a minimum 33MHz clock this results in a 1s | |
3273 | * delay before we can consider subordinate devices to | |
3274 | * be re-initialized. PCIe has some ways to shorten this, | |
3275 | * but we don't make use of them yet. | |
3276 | */ | |
3277 | ssleep(1); | |
64e8674f | 3278 | } |
d92a208d | 3279 | |
9e33002f GS |
3280 | void __weak pcibios_reset_secondary_bus(struct pci_dev *dev) |
3281 | { | |
3282 | pci_reset_secondary_bus(dev); | |
3283 | } | |
3284 | ||
d92a208d GS |
3285 | /** |
3286 | * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge. | |
3287 | * @dev: Bridge device | |
3288 | * | |
3289 | * Use the bridge control register to assert reset on the secondary bus. | |
3290 | * Devices on the secondary bus are left in power-on state. | |
3291 | */ | |
3292 | void pci_reset_bridge_secondary_bus(struct pci_dev *dev) | |
3293 | { | |
3294 | pcibios_reset_secondary_bus(dev); | |
3295 | } | |
64e8674f AW |
3296 | EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus); |
3297 | ||
3298 | static int pci_parent_bus_reset(struct pci_dev *dev, int probe) | |
3299 | { | |
c12ff1df YZ |
3300 | struct pci_dev *pdev; |
3301 | ||
f331a859 AW |
3302 | if (pci_is_root_bus(dev->bus) || dev->subordinate || |
3303 | !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) | |
c12ff1df YZ |
3304 | return -ENOTTY; |
3305 | ||
3306 | list_for_each_entry(pdev, &dev->bus->devices, bus_list) | |
3307 | if (pdev != dev) | |
3308 | return -ENOTTY; | |
3309 | ||
3310 | if (probe) | |
3311 | return 0; | |
3312 | ||
64e8674f | 3313 | pci_reset_bridge_secondary_bus(dev->bus->self); |
c12ff1df YZ |
3314 | |
3315 | return 0; | |
3316 | } | |
3317 | ||
608c3881 AW |
3318 | static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe) |
3319 | { | |
3320 | int rc = -ENOTTY; | |
3321 | ||
3322 | if (!hotplug || !try_module_get(hotplug->ops->owner)) | |
3323 | return rc; | |
3324 | ||
3325 | if (hotplug->ops->reset_slot) | |
3326 | rc = hotplug->ops->reset_slot(hotplug, probe); | |
3327 | ||
3328 | module_put(hotplug->ops->owner); | |
3329 | ||
3330 | return rc; | |
3331 | } | |
3332 | ||
3333 | static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe) | |
3334 | { | |
3335 | struct pci_dev *pdev; | |
3336 | ||
f331a859 AW |
3337 | if (dev->subordinate || !dev->slot || |
3338 | dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) | |
608c3881 AW |
3339 | return -ENOTTY; |
3340 | ||
3341 | list_for_each_entry(pdev, &dev->bus->devices, bus_list) | |
3342 | if (pdev != dev && pdev->slot == dev->slot) | |
3343 | return -ENOTTY; | |
3344 | ||
3345 | return pci_reset_hotplug_slot(dev->slot->hotplug, probe); | |
3346 | } | |
3347 | ||
977f857c | 3348 | static int __pci_dev_reset(struct pci_dev *dev, int probe) |
d91cdc74 | 3349 | { |
8c1c699f YZ |
3350 | int rc; |
3351 | ||
3352 | might_sleep(); | |
3353 | ||
b9c3b266 DC |
3354 | rc = pci_dev_specific_reset(dev, probe); |
3355 | if (rc != -ENOTTY) | |
3356 | goto done; | |
3357 | ||
8c1c699f YZ |
3358 | rc = pcie_flr(dev, probe); |
3359 | if (rc != -ENOTTY) | |
3360 | goto done; | |
d91cdc74 | 3361 | |
8c1c699f | 3362 | rc = pci_af_flr(dev, probe); |
f85876ba YZ |
3363 | if (rc != -ENOTTY) |
3364 | goto done; | |
3365 | ||
3366 | rc = pci_pm_reset(dev, probe); | |
c12ff1df YZ |
3367 | if (rc != -ENOTTY) |
3368 | goto done; | |
3369 | ||
608c3881 AW |
3370 | rc = pci_dev_reset_slot_function(dev, probe); |
3371 | if (rc != -ENOTTY) | |
3372 | goto done; | |
3373 | ||
c12ff1df | 3374 | rc = pci_parent_bus_reset(dev, probe); |
8c1c699f | 3375 | done: |
977f857c KRW |
3376 | return rc; |
3377 | } | |
3378 | ||
77cb985a AW |
3379 | static void pci_dev_lock(struct pci_dev *dev) |
3380 | { | |
3381 | pci_cfg_access_lock(dev); | |
3382 | /* block PM suspend, driver probe, etc. */ | |
3383 | device_lock(&dev->dev); | |
3384 | } | |
3385 | ||
61cf16d8 AW |
3386 | /* Return 1 on successful lock, 0 on contention */ |
3387 | static int pci_dev_trylock(struct pci_dev *dev) | |
3388 | { | |
3389 | if (pci_cfg_access_trylock(dev)) { | |
3390 | if (device_trylock(&dev->dev)) | |
3391 | return 1; | |
3392 | pci_cfg_access_unlock(dev); | |
3393 | } | |
3394 | ||
3395 | return 0; | |
3396 | } | |
3397 | ||
77cb985a AW |
3398 | static void pci_dev_unlock(struct pci_dev *dev) |
3399 | { | |
3400 | device_unlock(&dev->dev); | |
3401 | pci_cfg_access_unlock(dev); | |
3402 | } | |
3403 | ||
3ebe7f9f KB |
3404 | /** |
3405 | * pci_reset_notify - notify device driver of reset | |
3406 | * @dev: device to be notified of reset | |
3407 | * @prepare: 'true' if device is about to be reset; 'false' if reset attempt | |
3408 | * completed | |
3409 | * | |
3410 | * Must be called prior to device access being disabled and after device | |
3411 | * access is restored. | |
3412 | */ | |
3413 | static void pci_reset_notify(struct pci_dev *dev, bool prepare) | |
3414 | { | |
3415 | const struct pci_error_handlers *err_handler = | |
3416 | dev->driver ? dev->driver->err_handler : NULL; | |
3417 | if (err_handler && err_handler->reset_notify) | |
3418 | err_handler->reset_notify(dev, prepare); | |
3419 | } | |
3420 | ||
77cb985a AW |
3421 | static void pci_dev_save_and_disable(struct pci_dev *dev) |
3422 | { | |
3ebe7f9f KB |
3423 | pci_reset_notify(dev, true); |
3424 | ||
a6cbaade AW |
3425 | /* |
3426 | * Wake-up device prior to save. PM registers default to D0 after | |
3427 | * reset and a simple register restore doesn't reliably return | |
3428 | * to a non-D0 state anyway. | |
3429 | */ | |
3430 | pci_set_power_state(dev, PCI_D0); | |
3431 | ||
77cb985a AW |
3432 | pci_save_state(dev); |
3433 | /* | |
3434 | * Disable the device by clearing the Command register, except for | |
3435 | * INTx-disable which is set. This not only disables MMIO and I/O port | |
3436 | * BARs, but also prevents the device from being Bus Master, preventing | |
3437 | * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3 | |
3438 | * compliant devices, INTx-disable prevents legacy interrupts. | |
3439 | */ | |
3440 | pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE); | |
3441 | } | |
3442 | ||
3443 | static void pci_dev_restore(struct pci_dev *dev) | |
3444 | { | |
3445 | pci_restore_state(dev); | |
3ebe7f9f | 3446 | pci_reset_notify(dev, false); |
77cb985a AW |
3447 | } |
3448 | ||
977f857c KRW |
3449 | static int pci_dev_reset(struct pci_dev *dev, int probe) |
3450 | { | |
3451 | int rc; | |
3452 | ||
77cb985a AW |
3453 | if (!probe) |
3454 | pci_dev_lock(dev); | |
977f857c KRW |
3455 | |
3456 | rc = __pci_dev_reset(dev, probe); | |
3457 | ||
77cb985a AW |
3458 | if (!probe) |
3459 | pci_dev_unlock(dev); | |
3460 | ||
8c1c699f | 3461 | return rc; |
d91cdc74 | 3462 | } |
3ebe7f9f | 3463 | |
d91cdc74 | 3464 | /** |
8c1c699f YZ |
3465 | * __pci_reset_function - reset a PCI device function |
3466 | * @dev: PCI device to reset | |
d91cdc74 SY |
3467 | * |
3468 | * Some devices allow an individual function to be reset without affecting | |
3469 | * other functions in the same device. The PCI device must be responsive | |
3470 | * to PCI config space in order to use this function. | |
3471 | * | |
3472 | * The device function is presumed to be unused when this function is called. | |
3473 | * Resetting the device will make the contents of PCI configuration space | |
3474 | * random, so any caller of this must be prepared to reinitialise the | |
3475 | * device including MSI, bus mastering, BARs, decoding IO and memory spaces, | |
3476 | * etc. | |
3477 | * | |
8c1c699f | 3478 | * Returns 0 if the device function was successfully reset or negative if the |
d91cdc74 SY |
3479 | * device doesn't support resetting a single function. |
3480 | */ | |
8c1c699f | 3481 | int __pci_reset_function(struct pci_dev *dev) |
d91cdc74 | 3482 | { |
8c1c699f | 3483 | return pci_dev_reset(dev, 0); |
d91cdc74 | 3484 | } |
8c1c699f | 3485 | EXPORT_SYMBOL_GPL(__pci_reset_function); |
8dd7f803 | 3486 | |
6fbf9e7a KRW |
3487 | /** |
3488 | * __pci_reset_function_locked - reset a PCI device function while holding | |
3489 | * the @dev mutex lock. | |
3490 | * @dev: PCI device to reset | |
3491 | * | |
3492 | * Some devices allow an individual function to be reset without affecting | |
3493 | * other functions in the same device. The PCI device must be responsive | |
3494 | * to PCI config space in order to use this function. | |
3495 | * | |
3496 | * The device function is presumed to be unused and the caller is holding | |
3497 | * the device mutex lock when this function is called. | |
3498 | * Resetting the device will make the contents of PCI configuration space | |
3499 | * random, so any caller of this must be prepared to reinitialise the | |
3500 | * device including MSI, bus mastering, BARs, decoding IO and memory spaces, | |
3501 | * etc. | |
3502 | * | |
3503 | * Returns 0 if the device function was successfully reset or negative if the | |
3504 | * device doesn't support resetting a single function. | |
3505 | */ | |
3506 | int __pci_reset_function_locked(struct pci_dev *dev) | |
3507 | { | |
977f857c | 3508 | return __pci_dev_reset(dev, 0); |
6fbf9e7a KRW |
3509 | } |
3510 | EXPORT_SYMBOL_GPL(__pci_reset_function_locked); | |
3511 | ||
711d5779 MT |
3512 | /** |
3513 | * pci_probe_reset_function - check whether the device can be safely reset | |
3514 | * @dev: PCI device to reset | |
3515 | * | |
3516 | * Some devices allow an individual function to be reset without affecting | |
3517 | * other functions in the same device. The PCI device must be responsive | |
3518 | * to PCI config space in order to use this function. | |
3519 | * | |
3520 | * Returns 0 if the device function can be reset or negative if the | |
3521 | * device doesn't support resetting a single function. | |
3522 | */ | |
3523 | int pci_probe_reset_function(struct pci_dev *dev) | |
3524 | { | |
3525 | return pci_dev_reset(dev, 1); | |
3526 | } | |
3527 | ||
8dd7f803 | 3528 | /** |
8c1c699f YZ |
3529 | * pci_reset_function - quiesce and reset a PCI device function |
3530 | * @dev: PCI device to reset | |
8dd7f803 SY |
3531 | * |
3532 | * Some devices allow an individual function to be reset without affecting | |
3533 | * other functions in the same device. The PCI device must be responsive | |
3534 | * to PCI config space in order to use this function. | |
3535 | * | |
3536 | * This function does not just reset the PCI portion of a device, but | |
3537 | * clears all the state associated with the device. This function differs | |
8c1c699f | 3538 | * from __pci_reset_function in that it saves and restores device state |
8dd7f803 SY |
3539 | * over the reset. |
3540 | * | |
8c1c699f | 3541 | * Returns 0 if the device function was successfully reset or negative if the |
8dd7f803 SY |
3542 | * device doesn't support resetting a single function. |
3543 | */ | |
3544 | int pci_reset_function(struct pci_dev *dev) | |
3545 | { | |
8c1c699f | 3546 | int rc; |
8dd7f803 | 3547 | |
8c1c699f YZ |
3548 | rc = pci_dev_reset(dev, 1); |
3549 | if (rc) | |
3550 | return rc; | |
8dd7f803 | 3551 | |
77cb985a | 3552 | pci_dev_save_and_disable(dev); |
8dd7f803 | 3553 | |
8c1c699f | 3554 | rc = pci_dev_reset(dev, 0); |
8dd7f803 | 3555 | |
77cb985a | 3556 | pci_dev_restore(dev); |
8dd7f803 | 3557 | |
8c1c699f | 3558 | return rc; |
8dd7f803 SY |
3559 | } |
3560 | EXPORT_SYMBOL_GPL(pci_reset_function); | |
3561 | ||
61cf16d8 AW |
3562 | /** |
3563 | * pci_try_reset_function - quiesce and reset a PCI device function | |
3564 | * @dev: PCI device to reset | |
3565 | * | |
3566 | * Same as above, except return -EAGAIN if unable to lock device. | |
3567 | */ | |
3568 | int pci_try_reset_function(struct pci_dev *dev) | |
3569 | { | |
3570 | int rc; | |
3571 | ||
3572 | rc = pci_dev_reset(dev, 1); | |
3573 | if (rc) | |
3574 | return rc; | |
3575 | ||
3576 | pci_dev_save_and_disable(dev); | |
3577 | ||
3578 | if (pci_dev_trylock(dev)) { | |
3579 | rc = __pci_dev_reset(dev, 0); | |
3580 | pci_dev_unlock(dev); | |
3581 | } else | |
3582 | rc = -EAGAIN; | |
3583 | ||
3584 | pci_dev_restore(dev); | |
3585 | ||
3586 | return rc; | |
3587 | } | |
3588 | EXPORT_SYMBOL_GPL(pci_try_reset_function); | |
3589 | ||
f331a859 AW |
3590 | /* Do any devices on or below this bus prevent a bus reset? */ |
3591 | static bool pci_bus_resetable(struct pci_bus *bus) | |
3592 | { | |
3593 | struct pci_dev *dev; | |
3594 | ||
3595 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
3596 | if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET || | |
3597 | (dev->subordinate && !pci_bus_resetable(dev->subordinate))) | |
3598 | return false; | |
3599 | } | |
3600 | ||
3601 | return true; | |
3602 | } | |
3603 | ||
090a3c53 AW |
3604 | /* Lock devices from the top of the tree down */ |
3605 | static void pci_bus_lock(struct pci_bus *bus) | |
3606 | { | |
3607 | struct pci_dev *dev; | |
3608 | ||
3609 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
3610 | pci_dev_lock(dev); | |
3611 | if (dev->subordinate) | |
3612 | pci_bus_lock(dev->subordinate); | |
3613 | } | |
3614 | } | |
3615 | ||
3616 | /* Unlock devices from the bottom of the tree up */ | |
3617 | static void pci_bus_unlock(struct pci_bus *bus) | |
3618 | { | |
3619 | struct pci_dev *dev; | |
3620 | ||
3621 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
3622 | if (dev->subordinate) | |
3623 | pci_bus_unlock(dev->subordinate); | |
3624 | pci_dev_unlock(dev); | |
3625 | } | |
3626 | } | |
3627 | ||
61cf16d8 AW |
3628 | /* Return 1 on successful lock, 0 on contention */ |
3629 | static int pci_bus_trylock(struct pci_bus *bus) | |
3630 | { | |
3631 | struct pci_dev *dev; | |
3632 | ||
3633 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
3634 | if (!pci_dev_trylock(dev)) | |
3635 | goto unlock; | |
3636 | if (dev->subordinate) { | |
3637 | if (!pci_bus_trylock(dev->subordinate)) { | |
3638 | pci_dev_unlock(dev); | |
3639 | goto unlock; | |
3640 | } | |
3641 | } | |
3642 | } | |
3643 | return 1; | |
3644 | ||
3645 | unlock: | |
3646 | list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) { | |
3647 | if (dev->subordinate) | |
3648 | pci_bus_unlock(dev->subordinate); | |
3649 | pci_dev_unlock(dev); | |
3650 | } | |
3651 | return 0; | |
3652 | } | |
3653 | ||
f331a859 AW |
3654 | /* Do any devices on or below this slot prevent a bus reset? */ |
3655 | static bool pci_slot_resetable(struct pci_slot *slot) | |
3656 | { | |
3657 | struct pci_dev *dev; | |
3658 | ||
3659 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
3660 | if (!dev->slot || dev->slot != slot) | |
3661 | continue; | |
3662 | if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET || | |
3663 | (dev->subordinate && !pci_bus_resetable(dev->subordinate))) | |
3664 | return false; | |
3665 | } | |
3666 | ||
3667 | return true; | |
3668 | } | |
3669 | ||
090a3c53 AW |
3670 | /* Lock devices from the top of the tree down */ |
3671 | static void pci_slot_lock(struct pci_slot *slot) | |
3672 | { | |
3673 | struct pci_dev *dev; | |
3674 | ||
3675 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
3676 | if (!dev->slot || dev->slot != slot) | |
3677 | continue; | |
3678 | pci_dev_lock(dev); | |
3679 | if (dev->subordinate) | |
3680 | pci_bus_lock(dev->subordinate); | |
3681 | } | |
3682 | } | |
3683 | ||
3684 | /* Unlock devices from the bottom of the tree up */ | |
3685 | static void pci_slot_unlock(struct pci_slot *slot) | |
3686 | { | |
3687 | struct pci_dev *dev; | |
3688 | ||
3689 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
3690 | if (!dev->slot || dev->slot != slot) | |
3691 | continue; | |
3692 | if (dev->subordinate) | |
3693 | pci_bus_unlock(dev->subordinate); | |
3694 | pci_dev_unlock(dev); | |
3695 | } | |
3696 | } | |
3697 | ||
61cf16d8 AW |
3698 | /* Return 1 on successful lock, 0 on contention */ |
3699 | static int pci_slot_trylock(struct pci_slot *slot) | |
3700 | { | |
3701 | struct pci_dev *dev; | |
3702 | ||
3703 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
3704 | if (!dev->slot || dev->slot != slot) | |
3705 | continue; | |
3706 | if (!pci_dev_trylock(dev)) | |
3707 | goto unlock; | |
3708 | if (dev->subordinate) { | |
3709 | if (!pci_bus_trylock(dev->subordinate)) { | |
3710 | pci_dev_unlock(dev); | |
3711 | goto unlock; | |
3712 | } | |
3713 | } | |
3714 | } | |
3715 | return 1; | |
3716 | ||
3717 | unlock: | |
3718 | list_for_each_entry_continue_reverse(dev, | |
3719 | &slot->bus->devices, bus_list) { | |
3720 | if (!dev->slot || dev->slot != slot) | |
3721 | continue; | |
3722 | if (dev->subordinate) | |
3723 | pci_bus_unlock(dev->subordinate); | |
3724 | pci_dev_unlock(dev); | |
3725 | } | |
3726 | return 0; | |
3727 | } | |
3728 | ||
090a3c53 AW |
3729 | /* Save and disable devices from the top of the tree down */ |
3730 | static void pci_bus_save_and_disable(struct pci_bus *bus) | |
3731 | { | |
3732 | struct pci_dev *dev; | |
3733 | ||
3734 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
3735 | pci_dev_save_and_disable(dev); | |
3736 | if (dev->subordinate) | |
3737 | pci_bus_save_and_disable(dev->subordinate); | |
3738 | } | |
3739 | } | |
3740 | ||
3741 | /* | |
3742 | * Restore devices from top of the tree down - parent bridges need to be | |
3743 | * restored before we can get to subordinate devices. | |
3744 | */ | |
3745 | static void pci_bus_restore(struct pci_bus *bus) | |
3746 | { | |
3747 | struct pci_dev *dev; | |
3748 | ||
3749 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
3750 | pci_dev_restore(dev); | |
3751 | if (dev->subordinate) | |
3752 | pci_bus_restore(dev->subordinate); | |
3753 | } | |
3754 | } | |
3755 | ||
3756 | /* Save and disable devices from the top of the tree down */ | |
3757 | static void pci_slot_save_and_disable(struct pci_slot *slot) | |
3758 | { | |
3759 | struct pci_dev *dev; | |
3760 | ||
3761 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
3762 | if (!dev->slot || dev->slot != slot) | |
3763 | continue; | |
3764 | pci_dev_save_and_disable(dev); | |
3765 | if (dev->subordinate) | |
3766 | pci_bus_save_and_disable(dev->subordinate); | |
3767 | } | |
3768 | } | |
3769 | ||
3770 | /* | |
3771 | * Restore devices from top of the tree down - parent bridges need to be | |
3772 | * restored before we can get to subordinate devices. | |
3773 | */ | |
3774 | static void pci_slot_restore(struct pci_slot *slot) | |
3775 | { | |
3776 | struct pci_dev *dev; | |
3777 | ||
3778 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
3779 | if (!dev->slot || dev->slot != slot) | |
3780 | continue; | |
3781 | pci_dev_restore(dev); | |
3782 | if (dev->subordinate) | |
3783 | pci_bus_restore(dev->subordinate); | |
3784 | } | |
3785 | } | |
3786 | ||
3787 | static int pci_slot_reset(struct pci_slot *slot, int probe) | |
3788 | { | |
3789 | int rc; | |
3790 | ||
f331a859 | 3791 | if (!slot || !pci_slot_resetable(slot)) |
090a3c53 AW |
3792 | return -ENOTTY; |
3793 | ||
3794 | if (!probe) | |
3795 | pci_slot_lock(slot); | |
3796 | ||
3797 | might_sleep(); | |
3798 | ||
3799 | rc = pci_reset_hotplug_slot(slot->hotplug, probe); | |
3800 | ||
3801 | if (!probe) | |
3802 | pci_slot_unlock(slot); | |
3803 | ||
3804 | return rc; | |
3805 | } | |
3806 | ||
9a3d2b9b AW |
3807 | /** |
3808 | * pci_probe_reset_slot - probe whether a PCI slot can be reset | |
3809 | * @slot: PCI slot to probe | |
3810 | * | |
3811 | * Return 0 if slot can be reset, negative if a slot reset is not supported. | |
3812 | */ | |
3813 | int pci_probe_reset_slot(struct pci_slot *slot) | |
3814 | { | |
3815 | return pci_slot_reset(slot, 1); | |
3816 | } | |
3817 | EXPORT_SYMBOL_GPL(pci_probe_reset_slot); | |
3818 | ||
090a3c53 AW |
3819 | /** |
3820 | * pci_reset_slot - reset a PCI slot | |
3821 | * @slot: PCI slot to reset | |
3822 | * | |
3823 | * A PCI bus may host multiple slots, each slot may support a reset mechanism | |
3824 | * independent of other slots. For instance, some slots may support slot power | |
3825 | * control. In the case of a 1:1 bus to slot architecture, this function may | |
3826 | * wrap the bus reset to avoid spurious slot related events such as hotplug. | |
3827 | * Generally a slot reset should be attempted before a bus reset. All of the | |
3828 | * function of the slot and any subordinate buses behind the slot are reset | |
3829 | * through this function. PCI config space of all devices in the slot and | |
3830 | * behind the slot is saved before and restored after reset. | |
3831 | * | |
3832 | * Return 0 on success, non-zero on error. | |
3833 | */ | |
3834 | int pci_reset_slot(struct pci_slot *slot) | |
3835 | { | |
3836 | int rc; | |
3837 | ||
3838 | rc = pci_slot_reset(slot, 1); | |
3839 | if (rc) | |
3840 | return rc; | |
3841 | ||
3842 | pci_slot_save_and_disable(slot); | |
3843 | ||
3844 | rc = pci_slot_reset(slot, 0); | |
3845 | ||
3846 | pci_slot_restore(slot); | |
3847 | ||
3848 | return rc; | |
3849 | } | |
3850 | EXPORT_SYMBOL_GPL(pci_reset_slot); | |
3851 | ||
61cf16d8 AW |
3852 | /** |
3853 | * pci_try_reset_slot - Try to reset a PCI slot | |
3854 | * @slot: PCI slot to reset | |
3855 | * | |
3856 | * Same as above except return -EAGAIN if the slot cannot be locked | |
3857 | */ | |
3858 | int pci_try_reset_slot(struct pci_slot *slot) | |
3859 | { | |
3860 | int rc; | |
3861 | ||
3862 | rc = pci_slot_reset(slot, 1); | |
3863 | if (rc) | |
3864 | return rc; | |
3865 | ||
3866 | pci_slot_save_and_disable(slot); | |
3867 | ||
3868 | if (pci_slot_trylock(slot)) { | |
3869 | might_sleep(); | |
3870 | rc = pci_reset_hotplug_slot(slot->hotplug, 0); | |
3871 | pci_slot_unlock(slot); | |
3872 | } else | |
3873 | rc = -EAGAIN; | |
3874 | ||
3875 | pci_slot_restore(slot); | |
3876 | ||
3877 | return rc; | |
3878 | } | |
3879 | EXPORT_SYMBOL_GPL(pci_try_reset_slot); | |
3880 | ||
090a3c53 AW |
3881 | static int pci_bus_reset(struct pci_bus *bus, int probe) |
3882 | { | |
f331a859 | 3883 | if (!bus->self || !pci_bus_resetable(bus)) |
090a3c53 AW |
3884 | return -ENOTTY; |
3885 | ||
3886 | if (probe) | |
3887 | return 0; | |
3888 | ||
3889 | pci_bus_lock(bus); | |
3890 | ||
3891 | might_sleep(); | |
3892 | ||
3893 | pci_reset_bridge_secondary_bus(bus->self); | |
3894 | ||
3895 | pci_bus_unlock(bus); | |
3896 | ||
3897 | return 0; | |
3898 | } | |
3899 | ||
9a3d2b9b AW |
3900 | /** |
3901 | * pci_probe_reset_bus - probe whether a PCI bus can be reset | |
3902 | * @bus: PCI bus to probe | |
3903 | * | |
3904 | * Return 0 if bus can be reset, negative if a bus reset is not supported. | |
3905 | */ | |
3906 | int pci_probe_reset_bus(struct pci_bus *bus) | |
3907 | { | |
3908 | return pci_bus_reset(bus, 1); | |
3909 | } | |
3910 | EXPORT_SYMBOL_GPL(pci_probe_reset_bus); | |
3911 | ||
090a3c53 AW |
3912 | /** |
3913 | * pci_reset_bus - reset a PCI bus | |
3914 | * @bus: top level PCI bus to reset | |
3915 | * | |
3916 | * Do a bus reset on the given bus and any subordinate buses, saving | |
3917 | * and restoring state of all devices. | |
3918 | * | |
3919 | * Return 0 on success, non-zero on error. | |
3920 | */ | |
3921 | int pci_reset_bus(struct pci_bus *bus) | |
3922 | { | |
3923 | int rc; | |
3924 | ||
3925 | rc = pci_bus_reset(bus, 1); | |
3926 | if (rc) | |
3927 | return rc; | |
3928 | ||
3929 | pci_bus_save_and_disable(bus); | |
3930 | ||
3931 | rc = pci_bus_reset(bus, 0); | |
3932 | ||
3933 | pci_bus_restore(bus); | |
3934 | ||
3935 | return rc; | |
3936 | } | |
3937 | EXPORT_SYMBOL_GPL(pci_reset_bus); | |
3938 | ||
61cf16d8 AW |
3939 | /** |
3940 | * pci_try_reset_bus - Try to reset a PCI bus | |
3941 | * @bus: top level PCI bus to reset | |
3942 | * | |
3943 | * Same as above except return -EAGAIN if the bus cannot be locked | |
3944 | */ | |
3945 | int pci_try_reset_bus(struct pci_bus *bus) | |
3946 | { | |
3947 | int rc; | |
3948 | ||
3949 | rc = pci_bus_reset(bus, 1); | |
3950 | if (rc) | |
3951 | return rc; | |
3952 | ||
3953 | pci_bus_save_and_disable(bus); | |
3954 | ||
3955 | if (pci_bus_trylock(bus)) { | |
3956 | might_sleep(); | |
3957 | pci_reset_bridge_secondary_bus(bus->self); | |
3958 | pci_bus_unlock(bus); | |
3959 | } else | |
3960 | rc = -EAGAIN; | |
3961 | ||
3962 | pci_bus_restore(bus); | |
3963 | ||
3964 | return rc; | |
3965 | } | |
3966 | EXPORT_SYMBOL_GPL(pci_try_reset_bus); | |
3967 | ||
d556ad4b PO |
3968 | /** |
3969 | * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count | |
3970 | * @dev: PCI device to query | |
3971 | * | |
3972 | * Returns mmrbc: maximum designed memory read count in bytes | |
3973 | * or appropriate error value. | |
3974 | */ | |
3975 | int pcix_get_max_mmrbc(struct pci_dev *dev) | |
3976 | { | |
7c9e2b1c | 3977 | int cap; |
d556ad4b PO |
3978 | u32 stat; |
3979 | ||
3980 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
3981 | if (!cap) | |
3982 | return -EINVAL; | |
3983 | ||
7c9e2b1c | 3984 | if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat)) |
d556ad4b PO |
3985 | return -EINVAL; |
3986 | ||
25daeb55 | 3987 | return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21); |
d556ad4b PO |
3988 | } |
3989 | EXPORT_SYMBOL(pcix_get_max_mmrbc); | |
3990 | ||
3991 | /** | |
3992 | * pcix_get_mmrbc - get PCI-X maximum memory read byte count | |
3993 | * @dev: PCI device to query | |
3994 | * | |
3995 | * Returns mmrbc: maximum memory read count in bytes | |
3996 | * or appropriate error value. | |
3997 | */ | |
3998 | int pcix_get_mmrbc(struct pci_dev *dev) | |
3999 | { | |
7c9e2b1c | 4000 | int cap; |
bdc2bda7 | 4001 | u16 cmd; |
d556ad4b PO |
4002 | |
4003 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
4004 | if (!cap) | |
4005 | return -EINVAL; | |
4006 | ||
7c9e2b1c DN |
4007 | if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd)) |
4008 | return -EINVAL; | |
d556ad4b | 4009 | |
7c9e2b1c | 4010 | return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2); |
d556ad4b PO |
4011 | } |
4012 | EXPORT_SYMBOL(pcix_get_mmrbc); | |
4013 | ||
4014 | /** | |
4015 | * pcix_set_mmrbc - set PCI-X maximum memory read byte count | |
4016 | * @dev: PCI device to query | |
4017 | * @mmrbc: maximum memory read count in bytes | |
4018 | * valid values are 512, 1024, 2048, 4096 | |
4019 | * | |
4020 | * If possible sets maximum memory read byte count, some bridges have erratas | |
4021 | * that prevent this. | |
4022 | */ | |
4023 | int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc) | |
4024 | { | |
7c9e2b1c | 4025 | int cap; |
bdc2bda7 DN |
4026 | u32 stat, v, o; |
4027 | u16 cmd; | |
d556ad4b | 4028 | |
229f5afd | 4029 | if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc)) |
7c9e2b1c | 4030 | return -EINVAL; |
d556ad4b PO |
4031 | |
4032 | v = ffs(mmrbc) - 10; | |
4033 | ||
4034 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
4035 | if (!cap) | |
7c9e2b1c | 4036 | return -EINVAL; |
d556ad4b | 4037 | |
7c9e2b1c DN |
4038 | if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat)) |
4039 | return -EINVAL; | |
d556ad4b PO |
4040 | |
4041 | if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21) | |
4042 | return -E2BIG; | |
4043 | ||
7c9e2b1c DN |
4044 | if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd)) |
4045 | return -EINVAL; | |
d556ad4b PO |
4046 | |
4047 | o = (cmd & PCI_X_CMD_MAX_READ) >> 2; | |
4048 | if (o != v) { | |
809a3bf9 | 4049 | if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC)) |
d556ad4b PO |
4050 | return -EIO; |
4051 | ||
4052 | cmd &= ~PCI_X_CMD_MAX_READ; | |
4053 | cmd |= v << 2; | |
7c9e2b1c DN |
4054 | if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd)) |
4055 | return -EIO; | |
d556ad4b | 4056 | } |
7c9e2b1c | 4057 | return 0; |
d556ad4b PO |
4058 | } |
4059 | EXPORT_SYMBOL(pcix_set_mmrbc); | |
4060 | ||
4061 | /** | |
4062 | * pcie_get_readrq - get PCI Express read request size | |
4063 | * @dev: PCI device to query | |
4064 | * | |
4065 | * Returns maximum memory read request in bytes | |
4066 | * or appropriate error value. | |
4067 | */ | |
4068 | int pcie_get_readrq(struct pci_dev *dev) | |
4069 | { | |
d556ad4b PO |
4070 | u16 ctl; |
4071 | ||
59875ae4 | 4072 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); |
d556ad4b | 4073 | |
59875ae4 | 4074 | return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12); |
d556ad4b PO |
4075 | } |
4076 | EXPORT_SYMBOL(pcie_get_readrq); | |
4077 | ||
4078 | /** | |
4079 | * pcie_set_readrq - set PCI Express maximum memory read request | |
4080 | * @dev: PCI device to query | |
42e61f4a | 4081 | * @rq: maximum memory read count in bytes |
d556ad4b PO |
4082 | * valid values are 128, 256, 512, 1024, 2048, 4096 |
4083 | * | |
c9b378c7 | 4084 | * If possible sets maximum memory read request in bytes |
d556ad4b PO |
4085 | */ |
4086 | int pcie_set_readrq(struct pci_dev *dev, int rq) | |
4087 | { | |
59875ae4 | 4088 | u16 v; |
d556ad4b | 4089 | |
229f5afd | 4090 | if (rq < 128 || rq > 4096 || !is_power_of_2(rq)) |
59875ae4 | 4091 | return -EINVAL; |
d556ad4b | 4092 | |
a1c473aa BH |
4093 | /* |
4094 | * If using the "performance" PCIe config, we clamp the | |
4095 | * read rq size to the max packet size to prevent the | |
4096 | * host bridge generating requests larger than we can | |
4097 | * cope with | |
4098 | */ | |
4099 | if (pcie_bus_config == PCIE_BUS_PERFORMANCE) { | |
4100 | int mps = pcie_get_mps(dev); | |
4101 | ||
a1c473aa BH |
4102 | if (mps < rq) |
4103 | rq = mps; | |
4104 | } | |
4105 | ||
4106 | v = (ffs(rq) - 8) << 12; | |
d556ad4b | 4107 | |
59875ae4 JL |
4108 | return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, |
4109 | PCI_EXP_DEVCTL_READRQ, v); | |
d556ad4b PO |
4110 | } |
4111 | EXPORT_SYMBOL(pcie_set_readrq); | |
4112 | ||
b03e7495 JM |
4113 | /** |
4114 | * pcie_get_mps - get PCI Express maximum payload size | |
4115 | * @dev: PCI device to query | |
4116 | * | |
4117 | * Returns maximum payload size in bytes | |
b03e7495 JM |
4118 | */ |
4119 | int pcie_get_mps(struct pci_dev *dev) | |
4120 | { | |
b03e7495 JM |
4121 | u16 ctl; |
4122 | ||
59875ae4 | 4123 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); |
b03e7495 | 4124 | |
59875ae4 | 4125 | return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); |
b03e7495 | 4126 | } |
f1c66c46 | 4127 | EXPORT_SYMBOL(pcie_get_mps); |
b03e7495 JM |
4128 | |
4129 | /** | |
4130 | * pcie_set_mps - set PCI Express maximum payload size | |
4131 | * @dev: PCI device to query | |
47c08f31 | 4132 | * @mps: maximum payload size in bytes |
b03e7495 JM |
4133 | * valid values are 128, 256, 512, 1024, 2048, 4096 |
4134 | * | |
4135 | * If possible sets maximum payload size | |
4136 | */ | |
4137 | int pcie_set_mps(struct pci_dev *dev, int mps) | |
4138 | { | |
59875ae4 | 4139 | u16 v; |
b03e7495 JM |
4140 | |
4141 | if (mps < 128 || mps > 4096 || !is_power_of_2(mps)) | |
59875ae4 | 4142 | return -EINVAL; |
b03e7495 JM |
4143 | |
4144 | v = ffs(mps) - 8; | |
f7625980 | 4145 | if (v > dev->pcie_mpss) |
59875ae4 | 4146 | return -EINVAL; |
b03e7495 JM |
4147 | v <<= 5; |
4148 | ||
59875ae4 JL |
4149 | return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, |
4150 | PCI_EXP_DEVCTL_PAYLOAD, v); | |
b03e7495 | 4151 | } |
f1c66c46 | 4152 | EXPORT_SYMBOL(pcie_set_mps); |
b03e7495 | 4153 | |
81377c8d JK |
4154 | /** |
4155 | * pcie_get_minimum_link - determine minimum link settings of a PCI device | |
4156 | * @dev: PCI device to query | |
4157 | * @speed: storage for minimum speed | |
4158 | * @width: storage for minimum width | |
4159 | * | |
4160 | * This function will walk up the PCI device chain and determine the minimum | |
4161 | * link width and speed of the device. | |
4162 | */ | |
4163 | int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed, | |
4164 | enum pcie_link_width *width) | |
4165 | { | |
4166 | int ret; | |
4167 | ||
4168 | *speed = PCI_SPEED_UNKNOWN; | |
4169 | *width = PCIE_LNK_WIDTH_UNKNOWN; | |
4170 | ||
4171 | while (dev) { | |
4172 | u16 lnksta; | |
4173 | enum pci_bus_speed next_speed; | |
4174 | enum pcie_link_width next_width; | |
4175 | ||
4176 | ret = pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); | |
4177 | if (ret) | |
4178 | return ret; | |
4179 | ||
4180 | next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS]; | |
4181 | next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >> | |
4182 | PCI_EXP_LNKSTA_NLW_SHIFT; | |
4183 | ||
4184 | if (next_speed < *speed) | |
4185 | *speed = next_speed; | |
4186 | ||
4187 | if (next_width < *width) | |
4188 | *width = next_width; | |
4189 | ||
4190 | dev = dev->bus->self; | |
4191 | } | |
4192 | ||
4193 | return 0; | |
4194 | } | |
4195 | EXPORT_SYMBOL(pcie_get_minimum_link); | |
4196 | ||
c87deff7 HS |
4197 | /** |
4198 | * pci_select_bars - Make BAR mask from the type of resource | |
f95d882d | 4199 | * @dev: the PCI device for which BAR mask is made |
c87deff7 HS |
4200 | * @flags: resource type mask to be selected |
4201 | * | |
4202 | * This helper routine makes bar mask from the type of resource. | |
4203 | */ | |
4204 | int pci_select_bars(struct pci_dev *dev, unsigned long flags) | |
4205 | { | |
4206 | int i, bars = 0; | |
4207 | for (i = 0; i < PCI_NUM_RESOURCES; i++) | |
4208 | if (pci_resource_flags(dev, i) & flags) | |
4209 | bars |= (1 << i); | |
4210 | return bars; | |
4211 | } | |
b7fe9434 | 4212 | EXPORT_SYMBOL(pci_select_bars); |
c87deff7 | 4213 | |
613e7ed6 YZ |
4214 | /** |
4215 | * pci_resource_bar - get position of the BAR associated with a resource | |
4216 | * @dev: the PCI device | |
4217 | * @resno: the resource number | |
4218 | * @type: the BAR type to be filled in | |
4219 | * | |
4220 | * Returns BAR position in config space, or 0 if the BAR is invalid. | |
4221 | */ | |
4222 | int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type) | |
4223 | { | |
d1b054da YZ |
4224 | int reg; |
4225 | ||
613e7ed6 YZ |
4226 | if (resno < PCI_ROM_RESOURCE) { |
4227 | *type = pci_bar_unknown; | |
4228 | return PCI_BASE_ADDRESS_0 + 4 * resno; | |
4229 | } else if (resno == PCI_ROM_RESOURCE) { | |
4230 | *type = pci_bar_mem32; | |
4231 | return dev->rom_base_reg; | |
d1b054da YZ |
4232 | } else if (resno < PCI_BRIDGE_RESOURCES) { |
4233 | /* device specific resource */ | |
26ff46c6 MS |
4234 | *type = pci_bar_unknown; |
4235 | reg = pci_iov_resource_bar(dev, resno); | |
d1b054da YZ |
4236 | if (reg) |
4237 | return reg; | |
613e7ed6 YZ |
4238 | } |
4239 | ||
865df576 | 4240 | dev_err(&dev->dev, "BAR %d: invalid resource\n", resno); |
613e7ed6 YZ |
4241 | return 0; |
4242 | } | |
4243 | ||
95a8b6ef MT |
4244 | /* Some architectures require additional programming to enable VGA */ |
4245 | static arch_set_vga_state_t arch_set_vga_state; | |
4246 | ||
4247 | void __init pci_register_set_vga_state(arch_set_vga_state_t func) | |
4248 | { | |
4249 | arch_set_vga_state = func; /* NULL disables */ | |
4250 | } | |
4251 | ||
4252 | static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode, | |
3c78bc61 | 4253 | unsigned int command_bits, u32 flags) |
95a8b6ef MT |
4254 | { |
4255 | if (arch_set_vga_state) | |
4256 | return arch_set_vga_state(dev, decode, command_bits, | |
7ad35cf2 | 4257 | flags); |
95a8b6ef MT |
4258 | return 0; |
4259 | } | |
4260 | ||
deb2d2ec BH |
4261 | /** |
4262 | * pci_set_vga_state - set VGA decode state on device and parents if requested | |
19eea630 RD |
4263 | * @dev: the PCI device |
4264 | * @decode: true = enable decoding, false = disable decoding | |
4265 | * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY | |
3f37d622 | 4266 | * @flags: traverse ancestors and change bridges |
3448a19d | 4267 | * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE |
deb2d2ec BH |
4268 | */ |
4269 | int pci_set_vga_state(struct pci_dev *dev, bool decode, | |
3448a19d | 4270 | unsigned int command_bits, u32 flags) |
deb2d2ec BH |
4271 | { |
4272 | struct pci_bus *bus; | |
4273 | struct pci_dev *bridge; | |
4274 | u16 cmd; | |
95a8b6ef | 4275 | int rc; |
deb2d2ec | 4276 | |
67ebd814 | 4277 | WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY))); |
deb2d2ec | 4278 | |
95a8b6ef | 4279 | /* ARCH specific VGA enables */ |
3448a19d | 4280 | rc = pci_set_vga_state_arch(dev, decode, command_bits, flags); |
95a8b6ef MT |
4281 | if (rc) |
4282 | return rc; | |
4283 | ||
3448a19d DA |
4284 | if (flags & PCI_VGA_STATE_CHANGE_DECODES) { |
4285 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
4286 | if (decode == true) | |
4287 | cmd |= command_bits; | |
4288 | else | |
4289 | cmd &= ~command_bits; | |
4290 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
4291 | } | |
deb2d2ec | 4292 | |
3448a19d | 4293 | if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE)) |
deb2d2ec BH |
4294 | return 0; |
4295 | ||
4296 | bus = dev->bus; | |
4297 | while (bus) { | |
4298 | bridge = bus->self; | |
4299 | if (bridge) { | |
4300 | pci_read_config_word(bridge, PCI_BRIDGE_CONTROL, | |
4301 | &cmd); | |
4302 | if (decode == true) | |
4303 | cmd |= PCI_BRIDGE_CTL_VGA; | |
4304 | else | |
4305 | cmd &= ~PCI_BRIDGE_CTL_VGA; | |
4306 | pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, | |
4307 | cmd); | |
4308 | } | |
4309 | bus = bus->parent; | |
4310 | } | |
4311 | return 0; | |
4312 | } | |
4313 | ||
8496e85c RW |
4314 | bool pci_device_is_present(struct pci_dev *pdev) |
4315 | { | |
4316 | u32 v; | |
4317 | ||
4318 | return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0); | |
4319 | } | |
4320 | EXPORT_SYMBOL_GPL(pci_device_is_present); | |
4321 | ||
32a9a682 YS |
4322 | #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE |
4323 | static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0}; | |
e9d1e492 | 4324 | static DEFINE_SPINLOCK(resource_alignment_lock); |
32a9a682 YS |
4325 | |
4326 | /** | |
4327 | * pci_specified_resource_alignment - get resource alignment specified by user. | |
4328 | * @dev: the PCI device to get | |
4329 | * | |
4330 | * RETURNS: Resource alignment if it is specified. | |
4331 | * Zero if it is not specified. | |
4332 | */ | |
9738abed | 4333 | static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev) |
32a9a682 YS |
4334 | { |
4335 | int seg, bus, slot, func, align_order, count; | |
4336 | resource_size_t align = 0; | |
4337 | char *p; | |
4338 | ||
4339 | spin_lock(&resource_alignment_lock); | |
4340 | p = resource_alignment_param; | |
4341 | while (*p) { | |
4342 | count = 0; | |
4343 | if (sscanf(p, "%d%n", &align_order, &count) == 1 && | |
4344 | p[count] == '@') { | |
4345 | p += count + 1; | |
4346 | } else { | |
4347 | align_order = -1; | |
4348 | } | |
4349 | if (sscanf(p, "%x:%x:%x.%x%n", | |
4350 | &seg, &bus, &slot, &func, &count) != 4) { | |
4351 | seg = 0; | |
4352 | if (sscanf(p, "%x:%x.%x%n", | |
4353 | &bus, &slot, &func, &count) != 3) { | |
4354 | /* Invalid format */ | |
4355 | printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n", | |
4356 | p); | |
4357 | break; | |
4358 | } | |
4359 | } | |
4360 | p += count; | |
4361 | if (seg == pci_domain_nr(dev->bus) && | |
4362 | bus == dev->bus->number && | |
4363 | slot == PCI_SLOT(dev->devfn) && | |
4364 | func == PCI_FUNC(dev->devfn)) { | |
3c78bc61 | 4365 | if (align_order == -1) |
32a9a682 | 4366 | align = PAGE_SIZE; |
3c78bc61 | 4367 | else |
32a9a682 | 4368 | align = 1 << align_order; |
32a9a682 YS |
4369 | /* Found */ |
4370 | break; | |
4371 | } | |
4372 | if (*p != ';' && *p != ',') { | |
4373 | /* End of param or invalid format */ | |
4374 | break; | |
4375 | } | |
4376 | p++; | |
4377 | } | |
4378 | spin_unlock(&resource_alignment_lock); | |
4379 | return align; | |
4380 | } | |
4381 | ||
2069ecfb YL |
4382 | /* |
4383 | * This function disables memory decoding and releases memory resources | |
4384 | * of the device specified by kernel's boot parameter 'pci=resource_alignment='. | |
4385 | * It also rounds up size to specified alignment. | |
4386 | * Later on, the kernel will assign page-aligned memory resource back | |
4387 | * to the device. | |
4388 | */ | |
4389 | void pci_reassigndev_resource_alignment(struct pci_dev *dev) | |
4390 | { | |
4391 | int i; | |
4392 | struct resource *r; | |
4393 | resource_size_t align, size; | |
4394 | u16 command; | |
4395 | ||
10c463a7 YL |
4396 | /* check if specified PCI is target device to reassign */ |
4397 | align = pci_specified_resource_alignment(dev); | |
4398 | if (!align) | |
2069ecfb YL |
4399 | return; |
4400 | ||
4401 | if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL && | |
4402 | (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) { | |
4403 | dev_warn(&dev->dev, | |
4404 | "Can't reassign resources to host bridge.\n"); | |
4405 | return; | |
4406 | } | |
4407 | ||
4408 | dev_info(&dev->dev, | |
4409 | "Disabling memory decoding and releasing memory resources.\n"); | |
4410 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
4411 | command &= ~PCI_COMMAND_MEMORY; | |
4412 | pci_write_config_word(dev, PCI_COMMAND, command); | |
4413 | ||
2069ecfb YL |
4414 | for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) { |
4415 | r = &dev->resource[i]; | |
4416 | if (!(r->flags & IORESOURCE_MEM)) | |
4417 | continue; | |
4418 | size = resource_size(r); | |
4419 | if (size < align) { | |
4420 | size = align; | |
4421 | dev_info(&dev->dev, | |
4422 | "Rounding up size of resource #%d to %#llx.\n", | |
4423 | i, (unsigned long long)size); | |
4424 | } | |
bd064f0a | 4425 | r->flags |= IORESOURCE_UNSET; |
2069ecfb YL |
4426 | r->end = size - 1; |
4427 | r->start = 0; | |
4428 | } | |
4429 | /* Need to disable bridge's resource window, | |
4430 | * to enable the kernel to reassign new resource | |
4431 | * window later on. | |
4432 | */ | |
4433 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE && | |
4434 | (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { | |
4435 | for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) { | |
4436 | r = &dev->resource[i]; | |
4437 | if (!(r->flags & IORESOURCE_MEM)) | |
4438 | continue; | |
bd064f0a | 4439 | r->flags |= IORESOURCE_UNSET; |
2069ecfb YL |
4440 | r->end = resource_size(r) - 1; |
4441 | r->start = 0; | |
4442 | } | |
4443 | pci_disable_bridge_window(dev); | |
4444 | } | |
4445 | } | |
4446 | ||
9738abed | 4447 | static ssize_t pci_set_resource_alignment_param(const char *buf, size_t count) |
32a9a682 YS |
4448 | { |
4449 | if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1) | |
4450 | count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1; | |
4451 | spin_lock(&resource_alignment_lock); | |
4452 | strncpy(resource_alignment_param, buf, count); | |
4453 | resource_alignment_param[count] = '\0'; | |
4454 | spin_unlock(&resource_alignment_lock); | |
4455 | return count; | |
4456 | } | |
4457 | ||
9738abed | 4458 | static ssize_t pci_get_resource_alignment_param(char *buf, size_t size) |
32a9a682 YS |
4459 | { |
4460 | size_t count; | |
4461 | spin_lock(&resource_alignment_lock); | |
4462 | count = snprintf(buf, size, "%s", resource_alignment_param); | |
4463 | spin_unlock(&resource_alignment_lock); | |
4464 | return count; | |
4465 | } | |
4466 | ||
4467 | static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf) | |
4468 | { | |
4469 | return pci_get_resource_alignment_param(buf, PAGE_SIZE); | |
4470 | } | |
4471 | ||
4472 | static ssize_t pci_resource_alignment_store(struct bus_type *bus, | |
4473 | const char *buf, size_t count) | |
4474 | { | |
4475 | return pci_set_resource_alignment_param(buf, count); | |
4476 | } | |
4477 | ||
4478 | BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show, | |
4479 | pci_resource_alignment_store); | |
4480 | ||
4481 | static int __init pci_resource_alignment_sysfs_init(void) | |
4482 | { | |
4483 | return bus_create_file(&pci_bus_type, | |
4484 | &bus_attr_resource_alignment); | |
4485 | } | |
32a9a682 YS |
4486 | late_initcall(pci_resource_alignment_sysfs_init); |
4487 | ||
15856ad5 | 4488 | static void pci_no_domains(void) |
32a2eea7 JG |
4489 | { |
4490 | #ifdef CONFIG_PCI_DOMAINS | |
4491 | pci_domains_supported = 0; | |
4492 | #endif | |
4493 | } | |
4494 | ||
41e5c0f8 LD |
4495 | #ifdef CONFIG_PCI_DOMAINS |
4496 | static atomic_t __domain_nr = ATOMIC_INIT(-1); | |
4497 | ||
4498 | int pci_get_new_domain_nr(void) | |
4499 | { | |
4500 | return atomic_inc_return(&__domain_nr); | |
4501 | } | |
7c674700 LP |
4502 | |
4503 | #ifdef CONFIG_PCI_DOMAINS_GENERIC | |
4504 | void pci_bus_assign_domain_nr(struct pci_bus *bus, struct device *parent) | |
4505 | { | |
4506 | static int use_dt_domains = -1; | |
4507 | int domain = of_get_pci_domain_nr(parent->of_node); | |
4508 | ||
4509 | /* | |
4510 | * Check DT domain and use_dt_domains values. | |
4511 | * | |
4512 | * If DT domain property is valid (domain >= 0) and | |
4513 | * use_dt_domains != 0, the DT assignment is valid since this means | |
4514 | * we have not previously allocated a domain number by using | |
4515 | * pci_get_new_domain_nr(); we should also update use_dt_domains to | |
4516 | * 1, to indicate that we have just assigned a domain number from | |
4517 | * DT. | |
4518 | * | |
4519 | * If DT domain property value is not valid (ie domain < 0), and we | |
4520 | * have not previously assigned a domain number from DT | |
4521 | * (use_dt_domains != 1) we should assign a domain number by | |
4522 | * using the: | |
4523 | * | |
4524 | * pci_get_new_domain_nr() | |
4525 | * | |
4526 | * API and update the use_dt_domains value to keep track of method we | |
4527 | * are using to assign domain numbers (use_dt_domains = 0). | |
4528 | * | |
4529 | * All other combinations imply we have a platform that is trying | |
4530 | * to mix domain numbers obtained from DT and pci_get_new_domain_nr(), | |
4531 | * which is a recipe for domain mishandling and it is prevented by | |
4532 | * invalidating the domain value (domain = -1) and printing a | |
4533 | * corresponding error. | |
4534 | */ | |
4535 | if (domain >= 0 && use_dt_domains) { | |
4536 | use_dt_domains = 1; | |
4537 | } else if (domain < 0 && use_dt_domains != 1) { | |
4538 | use_dt_domains = 0; | |
4539 | domain = pci_get_new_domain_nr(); | |
4540 | } else { | |
4541 | dev_err(parent, "Node %s has inconsistent \"linux,pci-domain\" property in DT\n", | |
4542 | parent->of_node->full_name); | |
4543 | domain = -1; | |
4544 | } | |
4545 | ||
4546 | bus->domain_nr = domain; | |
4547 | } | |
4548 | #endif | |
41e5c0f8 LD |
4549 | #endif |
4550 | ||
0ef5f8f6 | 4551 | /** |
642c92da | 4552 | * pci_ext_cfg_avail - can we access extended PCI config space? |
0ef5f8f6 AP |
4553 | * |
4554 | * Returns 1 if we can access PCI extended config space (offsets | |
4555 | * greater than 0xff). This is the default implementation. Architecture | |
4556 | * implementations can override this. | |
4557 | */ | |
642c92da | 4558 | int __weak pci_ext_cfg_avail(void) |
0ef5f8f6 AP |
4559 | { |
4560 | return 1; | |
4561 | } | |
4562 | ||
2d1c8618 BH |
4563 | void __weak pci_fixup_cardbus(struct pci_bus *bus) |
4564 | { | |
4565 | } | |
4566 | EXPORT_SYMBOL(pci_fixup_cardbus); | |
4567 | ||
ad04d31e | 4568 | static int __init pci_setup(char *str) |
1da177e4 LT |
4569 | { |
4570 | while (str) { | |
4571 | char *k = strchr(str, ','); | |
4572 | if (k) | |
4573 | *k++ = 0; | |
4574 | if (*str && (str = pcibios_setup(str)) && *str) { | |
309e57df MW |
4575 | if (!strcmp(str, "nomsi")) { |
4576 | pci_no_msi(); | |
7f785763 RD |
4577 | } else if (!strcmp(str, "noaer")) { |
4578 | pci_no_aer(); | |
b55438fd YL |
4579 | } else if (!strncmp(str, "realloc=", 8)) { |
4580 | pci_realloc_get_opt(str + 8); | |
f483d392 | 4581 | } else if (!strncmp(str, "realloc", 7)) { |
b55438fd | 4582 | pci_realloc_get_opt("on"); |
32a2eea7 JG |
4583 | } else if (!strcmp(str, "nodomains")) { |
4584 | pci_no_domains(); | |
6748dcc2 RW |
4585 | } else if (!strncmp(str, "noari", 5)) { |
4586 | pcie_ari_disabled = true; | |
4516a618 AN |
4587 | } else if (!strncmp(str, "cbiosize=", 9)) { |
4588 | pci_cardbus_io_size = memparse(str + 9, &str); | |
4589 | } else if (!strncmp(str, "cbmemsize=", 10)) { | |
4590 | pci_cardbus_mem_size = memparse(str + 10, &str); | |
32a9a682 YS |
4591 | } else if (!strncmp(str, "resource_alignment=", 19)) { |
4592 | pci_set_resource_alignment_param(str + 19, | |
4593 | strlen(str + 19)); | |
43c16408 AP |
4594 | } else if (!strncmp(str, "ecrc=", 5)) { |
4595 | pcie_ecrc_get_policy(str + 5); | |
28760489 EB |
4596 | } else if (!strncmp(str, "hpiosize=", 9)) { |
4597 | pci_hotplug_io_size = memparse(str + 9, &str); | |
4598 | } else if (!strncmp(str, "hpmemsize=", 10)) { | |
4599 | pci_hotplug_mem_size = memparse(str + 10, &str); | |
5f39e670 JM |
4600 | } else if (!strncmp(str, "pcie_bus_tune_off", 17)) { |
4601 | pcie_bus_config = PCIE_BUS_TUNE_OFF; | |
b03e7495 JM |
4602 | } else if (!strncmp(str, "pcie_bus_safe", 13)) { |
4603 | pcie_bus_config = PCIE_BUS_SAFE; | |
4604 | } else if (!strncmp(str, "pcie_bus_perf", 13)) { | |
4605 | pcie_bus_config = PCIE_BUS_PERFORMANCE; | |
5f39e670 JM |
4606 | } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) { |
4607 | pcie_bus_config = PCIE_BUS_PEER2PEER; | |
284f5f9d BH |
4608 | } else if (!strncmp(str, "pcie_scan_all", 13)) { |
4609 | pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS); | |
309e57df MW |
4610 | } else { |
4611 | printk(KERN_ERR "PCI: Unknown option `%s'\n", | |
4612 | str); | |
4613 | } | |
1da177e4 LT |
4614 | } |
4615 | str = k; | |
4616 | } | |
0637a70a | 4617 | return 0; |
1da177e4 | 4618 | } |
0637a70a | 4619 | early_param("pci", pci_setup); |