Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * PCI Bus Services, see include/linux/pci.h for further explanation. |
3 | * | |
4 | * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, | |
5 | * David Mosberger-Tang | |
6 | * | |
7 | * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz> | |
8 | */ | |
9 | ||
10 | #include <linux/kernel.h> | |
11 | #include <linux/delay.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/pci.h> | |
075c1771 | 14 | #include <linux/pm.h> |
5a0e3ad6 | 15 | #include <linux/slab.h> |
1da177e4 LT |
16 | #include <linux/module.h> |
17 | #include <linux/spinlock.h> | |
4e57b681 | 18 | #include <linux/string.h> |
229f5afd | 19 | #include <linux/log2.h> |
7d715a6c | 20 | #include <linux/pci-aspm.h> |
c300bd2f | 21 | #include <linux/pm_wakeup.h> |
8dd7f803 | 22 | #include <linux/interrupt.h> |
32a9a682 | 23 | #include <linux/device.h> |
b67ea761 | 24 | #include <linux/pm_runtime.h> |
284f5f9d | 25 | #include <asm-generic/pci-bridge.h> |
32a9a682 | 26 | #include <asm/setup.h> |
bc56b9e0 | 27 | #include "pci.h" |
1da177e4 | 28 | |
00240c38 AS |
29 | const char *pci_power_names[] = { |
30 | "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown", | |
31 | }; | |
32 | EXPORT_SYMBOL_GPL(pci_power_names); | |
33 | ||
93177a74 RW |
34 | int isa_dma_bridge_buggy; |
35 | EXPORT_SYMBOL(isa_dma_bridge_buggy); | |
36 | ||
37 | int pci_pci_problems; | |
38 | EXPORT_SYMBOL(pci_pci_problems); | |
39 | ||
1ae861e6 RW |
40 | unsigned int pci_pm_d3_delay; |
41 | ||
df17e62e MG |
42 | static void pci_pme_list_scan(struct work_struct *work); |
43 | ||
44 | static LIST_HEAD(pci_pme_list); | |
45 | static DEFINE_MUTEX(pci_pme_list_mutex); | |
46 | static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan); | |
47 | ||
48 | struct pci_pme_device { | |
49 | struct list_head list; | |
50 | struct pci_dev *dev; | |
51 | }; | |
52 | ||
53 | #define PME_TIMEOUT 1000 /* How long between PME checks */ | |
54 | ||
1ae861e6 RW |
55 | static void pci_dev_d3_sleep(struct pci_dev *dev) |
56 | { | |
57 | unsigned int delay = dev->d3_delay; | |
58 | ||
59 | if (delay < pci_pm_d3_delay) | |
60 | delay = pci_pm_d3_delay; | |
61 | ||
62 | msleep(delay); | |
63 | } | |
1da177e4 | 64 | |
32a2eea7 JG |
65 | #ifdef CONFIG_PCI_DOMAINS |
66 | int pci_domains_supported = 1; | |
67 | #endif | |
68 | ||
4516a618 AN |
69 | #define DEFAULT_CARDBUS_IO_SIZE (256) |
70 | #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024) | |
71 | /* pci=cbmemsize=nnM,cbiosize=nn can override this */ | |
72 | unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE; | |
73 | unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE; | |
74 | ||
28760489 EB |
75 | #define DEFAULT_HOTPLUG_IO_SIZE (256) |
76 | #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024) | |
77 | /* pci=hpmemsize=nnM,hpiosize=nn can override this */ | |
78 | unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE; | |
79 | unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE; | |
80 | ||
5f39e670 | 81 | enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF; |
b03e7495 | 82 | |
ac1aa47b JB |
83 | /* |
84 | * The default CLS is used if arch didn't set CLS explicitly and not | |
85 | * all pci devices agree on the same value. Arch can override either | |
86 | * the dfl or actual value as it sees fit. Don't forget this is | |
87 | * measured in 32-bit words, not bytes. | |
88 | */ | |
98e724c7 | 89 | u8 pci_dfl_cache_line_size __devinitdata = L1_CACHE_BYTES >> 2; |
ac1aa47b JB |
90 | u8 pci_cache_line_size; |
91 | ||
96c55900 MS |
92 | /* |
93 | * If we set up a device for bus mastering, we need to check the latency | |
94 | * timer as certain BIOSes forget to set it properly. | |
95 | */ | |
96 | unsigned int pcibios_max_latency = 255; | |
97 | ||
6748dcc2 RW |
98 | /* If set, the PCIe ARI capability will not be used. */ |
99 | static bool pcie_ari_disabled; | |
100 | ||
1da177e4 LT |
101 | /** |
102 | * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children | |
103 | * @bus: pointer to PCI bus structure to search | |
104 | * | |
105 | * Given a PCI bus, returns the highest PCI bus number present in the set | |
106 | * including the given PCI bus and its list of child PCI buses. | |
107 | */ | |
96bde06a | 108 | unsigned char pci_bus_max_busnr(struct pci_bus* bus) |
1da177e4 LT |
109 | { |
110 | struct list_head *tmp; | |
111 | unsigned char max, n; | |
112 | ||
b918c62e | 113 | max = bus->busn_res.end; |
1da177e4 LT |
114 | list_for_each(tmp, &bus->children) { |
115 | n = pci_bus_max_busnr(pci_bus_b(tmp)); | |
116 | if(n > max) | |
117 | max = n; | |
118 | } | |
119 | return max; | |
120 | } | |
b82db5ce | 121 | EXPORT_SYMBOL_GPL(pci_bus_max_busnr); |
1da177e4 | 122 | |
1684f5dd AM |
123 | #ifdef CONFIG_HAS_IOMEM |
124 | void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar) | |
125 | { | |
126 | /* | |
127 | * Make sure the BAR is actually a memory resource, not an IO resource | |
128 | */ | |
129 | if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { | |
130 | WARN_ON(1); | |
131 | return NULL; | |
132 | } | |
133 | return ioremap_nocache(pci_resource_start(pdev, bar), | |
134 | pci_resource_len(pdev, bar)); | |
135 | } | |
136 | EXPORT_SYMBOL_GPL(pci_ioremap_bar); | |
137 | #endif | |
138 | ||
687d5fe3 ME |
139 | #define PCI_FIND_CAP_TTL 48 |
140 | ||
141 | static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, | |
142 | u8 pos, int cap, int *ttl) | |
24a4e377 RD |
143 | { |
144 | u8 id; | |
24a4e377 | 145 | |
687d5fe3 | 146 | while ((*ttl)--) { |
24a4e377 RD |
147 | pci_bus_read_config_byte(bus, devfn, pos, &pos); |
148 | if (pos < 0x40) | |
149 | break; | |
150 | pos &= ~3; | |
151 | pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID, | |
152 | &id); | |
153 | if (id == 0xff) | |
154 | break; | |
155 | if (id == cap) | |
156 | return pos; | |
157 | pos += PCI_CAP_LIST_NEXT; | |
158 | } | |
159 | return 0; | |
160 | } | |
161 | ||
687d5fe3 ME |
162 | static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, |
163 | u8 pos, int cap) | |
164 | { | |
165 | int ttl = PCI_FIND_CAP_TTL; | |
166 | ||
167 | return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl); | |
168 | } | |
169 | ||
24a4e377 RD |
170 | int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) |
171 | { | |
172 | return __pci_find_next_cap(dev->bus, dev->devfn, | |
173 | pos + PCI_CAP_LIST_NEXT, cap); | |
174 | } | |
175 | EXPORT_SYMBOL_GPL(pci_find_next_capability); | |
176 | ||
d3bac118 ME |
177 | static int __pci_bus_find_cap_start(struct pci_bus *bus, |
178 | unsigned int devfn, u8 hdr_type) | |
1da177e4 LT |
179 | { |
180 | u16 status; | |
1da177e4 LT |
181 | |
182 | pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status); | |
183 | if (!(status & PCI_STATUS_CAP_LIST)) | |
184 | return 0; | |
185 | ||
186 | switch (hdr_type) { | |
187 | case PCI_HEADER_TYPE_NORMAL: | |
188 | case PCI_HEADER_TYPE_BRIDGE: | |
d3bac118 | 189 | return PCI_CAPABILITY_LIST; |
1da177e4 | 190 | case PCI_HEADER_TYPE_CARDBUS: |
d3bac118 | 191 | return PCI_CB_CAPABILITY_LIST; |
1da177e4 LT |
192 | default: |
193 | return 0; | |
194 | } | |
d3bac118 ME |
195 | |
196 | return 0; | |
1da177e4 LT |
197 | } |
198 | ||
199 | /** | |
200 | * pci_find_capability - query for devices' capabilities | |
201 | * @dev: PCI device to query | |
202 | * @cap: capability code | |
203 | * | |
204 | * Tell if a device supports a given PCI capability. | |
205 | * Returns the address of the requested capability structure within the | |
206 | * device's PCI configuration space or 0 in case the device does not | |
207 | * support it. Possible values for @cap: | |
208 | * | |
209 | * %PCI_CAP_ID_PM Power Management | |
210 | * %PCI_CAP_ID_AGP Accelerated Graphics Port | |
211 | * %PCI_CAP_ID_VPD Vital Product Data | |
212 | * %PCI_CAP_ID_SLOTID Slot Identification | |
213 | * %PCI_CAP_ID_MSI Message Signalled Interrupts | |
214 | * %PCI_CAP_ID_CHSWP CompactPCI HotSwap | |
215 | * %PCI_CAP_ID_PCIX PCI-X | |
216 | * %PCI_CAP_ID_EXP PCI Express | |
217 | */ | |
218 | int pci_find_capability(struct pci_dev *dev, int cap) | |
219 | { | |
d3bac118 ME |
220 | int pos; |
221 | ||
222 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); | |
223 | if (pos) | |
224 | pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap); | |
225 | ||
226 | return pos; | |
1da177e4 LT |
227 | } |
228 | ||
229 | /** | |
230 | * pci_bus_find_capability - query for devices' capabilities | |
231 | * @bus: the PCI bus to query | |
232 | * @devfn: PCI device to query | |
233 | * @cap: capability code | |
234 | * | |
235 | * Like pci_find_capability() but works for pci devices that do not have a | |
236 | * pci_dev structure set up yet. | |
237 | * | |
238 | * Returns the address of the requested capability structure within the | |
239 | * device's PCI configuration space or 0 in case the device does not | |
240 | * support it. | |
241 | */ | |
242 | int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) | |
243 | { | |
d3bac118 | 244 | int pos; |
1da177e4 LT |
245 | u8 hdr_type; |
246 | ||
247 | pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type); | |
248 | ||
d3bac118 ME |
249 | pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f); |
250 | if (pos) | |
251 | pos = __pci_find_next_cap(bus, devfn, pos, cap); | |
252 | ||
253 | return pos; | |
1da177e4 LT |
254 | } |
255 | ||
256 | /** | |
44a9a36f | 257 | * pci_find_next_ext_capability - Find an extended capability |
1da177e4 | 258 | * @dev: PCI device to query |
44a9a36f | 259 | * @start: address at which to start looking (0 to start at beginning of list) |
1da177e4 LT |
260 | * @cap: capability code |
261 | * | |
44a9a36f | 262 | * Returns the address of the next matching extended capability structure |
1da177e4 | 263 | * within the device's PCI configuration space or 0 if the device does |
44a9a36f BH |
264 | * not support it. Some capabilities can occur several times, e.g., the |
265 | * vendor-specific capability, and this provides a way to find them all. | |
1da177e4 | 266 | */ |
44a9a36f | 267 | int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap) |
1da177e4 LT |
268 | { |
269 | u32 header; | |
557848c3 ZY |
270 | int ttl; |
271 | int pos = PCI_CFG_SPACE_SIZE; | |
1da177e4 | 272 | |
557848c3 ZY |
273 | /* minimum 8 bytes per capability */ |
274 | ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; | |
275 | ||
276 | if (dev->cfg_size <= PCI_CFG_SPACE_SIZE) | |
1da177e4 LT |
277 | return 0; |
278 | ||
44a9a36f BH |
279 | if (start) |
280 | pos = start; | |
281 | ||
1da177e4 LT |
282 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) |
283 | return 0; | |
284 | ||
285 | /* | |
286 | * If we have no capabilities, this is indicated by cap ID, | |
287 | * cap version and next pointer all being 0. | |
288 | */ | |
289 | if (header == 0) | |
290 | return 0; | |
291 | ||
292 | while (ttl-- > 0) { | |
44a9a36f | 293 | if (PCI_EXT_CAP_ID(header) == cap && pos != start) |
1da177e4 LT |
294 | return pos; |
295 | ||
296 | pos = PCI_EXT_CAP_NEXT(header); | |
557848c3 | 297 | if (pos < PCI_CFG_SPACE_SIZE) |
1da177e4 LT |
298 | break; |
299 | ||
300 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) | |
301 | break; | |
302 | } | |
303 | ||
304 | return 0; | |
305 | } | |
44a9a36f BH |
306 | EXPORT_SYMBOL_GPL(pci_find_next_ext_capability); |
307 | ||
308 | /** | |
309 | * pci_find_ext_capability - Find an extended capability | |
310 | * @dev: PCI device to query | |
311 | * @cap: capability code | |
312 | * | |
313 | * Returns the address of the requested extended capability structure | |
314 | * within the device's PCI configuration space or 0 if the device does | |
315 | * not support it. Possible values for @cap: | |
316 | * | |
317 | * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting | |
318 | * %PCI_EXT_CAP_ID_VC Virtual Channel | |
319 | * %PCI_EXT_CAP_ID_DSN Device Serial Number | |
320 | * %PCI_EXT_CAP_ID_PWR Power Budgeting | |
321 | */ | |
322 | int pci_find_ext_capability(struct pci_dev *dev, int cap) | |
323 | { | |
324 | return pci_find_next_ext_capability(dev, 0, cap); | |
325 | } | |
3a720d72 | 326 | EXPORT_SYMBOL_GPL(pci_find_ext_capability); |
1da177e4 | 327 | |
687d5fe3 ME |
328 | static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap) |
329 | { | |
330 | int rc, ttl = PCI_FIND_CAP_TTL; | |
331 | u8 cap, mask; | |
332 | ||
333 | if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST) | |
334 | mask = HT_3BIT_CAP_MASK; | |
335 | else | |
336 | mask = HT_5BIT_CAP_MASK; | |
337 | ||
338 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos, | |
339 | PCI_CAP_ID_HT, &ttl); | |
340 | while (pos) { | |
341 | rc = pci_read_config_byte(dev, pos + 3, &cap); | |
342 | if (rc != PCIBIOS_SUCCESSFUL) | |
343 | return 0; | |
344 | ||
345 | if ((cap & mask) == ht_cap) | |
346 | return pos; | |
347 | ||
47a4d5be BG |
348 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, |
349 | pos + PCI_CAP_LIST_NEXT, | |
687d5fe3 ME |
350 | PCI_CAP_ID_HT, &ttl); |
351 | } | |
352 | ||
353 | return 0; | |
354 | } | |
355 | /** | |
356 | * pci_find_next_ht_capability - query a device's Hypertransport capabilities | |
357 | * @dev: PCI device to query | |
358 | * @pos: Position from which to continue searching | |
359 | * @ht_cap: Hypertransport capability code | |
360 | * | |
361 | * To be used in conjunction with pci_find_ht_capability() to search for | |
362 | * all capabilities matching @ht_cap. @pos should always be a value returned | |
363 | * from pci_find_ht_capability(). | |
364 | * | |
365 | * NB. To be 100% safe against broken PCI devices, the caller should take | |
366 | * steps to avoid an infinite loop. | |
367 | */ | |
368 | int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap) | |
369 | { | |
370 | return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap); | |
371 | } | |
372 | EXPORT_SYMBOL_GPL(pci_find_next_ht_capability); | |
373 | ||
374 | /** | |
375 | * pci_find_ht_capability - query a device's Hypertransport capabilities | |
376 | * @dev: PCI device to query | |
377 | * @ht_cap: Hypertransport capability code | |
378 | * | |
379 | * Tell if a device supports a given Hypertransport capability. | |
380 | * Returns an address within the device's PCI configuration space | |
381 | * or 0 in case the device does not support the request capability. | |
382 | * The address points to the PCI capability, of type PCI_CAP_ID_HT, | |
383 | * which has a Hypertransport capability matching @ht_cap. | |
384 | */ | |
385 | int pci_find_ht_capability(struct pci_dev *dev, int ht_cap) | |
386 | { | |
387 | int pos; | |
388 | ||
389 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); | |
390 | if (pos) | |
391 | pos = __pci_find_next_ht_cap(dev, pos, ht_cap); | |
392 | ||
393 | return pos; | |
394 | } | |
395 | EXPORT_SYMBOL_GPL(pci_find_ht_capability); | |
396 | ||
1da177e4 LT |
397 | /** |
398 | * pci_find_parent_resource - return resource region of parent bus of given region | |
399 | * @dev: PCI device structure contains resources to be searched | |
400 | * @res: child resource record for which parent is sought | |
401 | * | |
402 | * For given resource region of given device, return the resource | |
403 | * region of parent bus the given region is contained in or where | |
404 | * it should be allocated from. | |
405 | */ | |
406 | struct resource * | |
407 | pci_find_parent_resource(const struct pci_dev *dev, struct resource *res) | |
408 | { | |
409 | const struct pci_bus *bus = dev->bus; | |
410 | int i; | |
89a74ecc | 411 | struct resource *best = NULL, *r; |
1da177e4 | 412 | |
89a74ecc | 413 | pci_bus_for_each_resource(bus, r, i) { |
1da177e4 LT |
414 | if (!r) |
415 | continue; | |
416 | if (res->start && !(res->start >= r->start && res->end <= r->end)) | |
417 | continue; /* Not contained */ | |
418 | if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM)) | |
419 | continue; /* Wrong type */ | |
420 | if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH)) | |
421 | return r; /* Exact match */ | |
8c8def26 LT |
422 | /* We can't insert a non-prefetch resource inside a prefetchable parent .. */ |
423 | if (r->flags & IORESOURCE_PREFETCH) | |
424 | continue; | |
425 | /* .. but we can put a prefetchable resource inside a non-prefetchable one */ | |
426 | if (!best) | |
427 | best = r; | |
1da177e4 LT |
428 | } |
429 | return best; | |
430 | } | |
431 | ||
064b53db JL |
432 | /** |
433 | * pci_restore_bars - restore a devices BAR values (e.g. after wake-up) | |
434 | * @dev: PCI device to have its BARs restored | |
435 | * | |
436 | * Restore the BAR values for a given device, so as to make it | |
437 | * accessible by its driver. | |
438 | */ | |
ad668599 | 439 | static void |
064b53db JL |
440 | pci_restore_bars(struct pci_dev *dev) |
441 | { | |
bc5f5a82 | 442 | int i; |
064b53db | 443 | |
bc5f5a82 | 444 | for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) |
14add80b | 445 | pci_update_resource(dev, i); |
064b53db JL |
446 | } |
447 | ||
961d9120 RW |
448 | static struct pci_platform_pm_ops *pci_platform_pm; |
449 | ||
450 | int pci_set_platform_pm(struct pci_platform_pm_ops *ops) | |
451 | { | |
eb9d0fe4 RW |
452 | if (!ops->is_manageable || !ops->set_state || !ops->choose_state |
453 | || !ops->sleep_wake || !ops->can_wakeup) | |
961d9120 RW |
454 | return -EINVAL; |
455 | pci_platform_pm = ops; | |
456 | return 0; | |
457 | } | |
458 | ||
459 | static inline bool platform_pci_power_manageable(struct pci_dev *dev) | |
460 | { | |
461 | return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false; | |
462 | } | |
463 | ||
464 | static inline int platform_pci_set_power_state(struct pci_dev *dev, | |
465 | pci_power_t t) | |
466 | { | |
467 | return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS; | |
468 | } | |
469 | ||
470 | static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev) | |
471 | { | |
472 | return pci_platform_pm ? | |
473 | pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR; | |
474 | } | |
8f7020d3 | 475 | |
eb9d0fe4 RW |
476 | static inline bool platform_pci_can_wakeup(struct pci_dev *dev) |
477 | { | |
478 | return pci_platform_pm ? pci_platform_pm->can_wakeup(dev) : false; | |
479 | } | |
480 | ||
481 | static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable) | |
482 | { | |
483 | return pci_platform_pm ? | |
484 | pci_platform_pm->sleep_wake(dev, enable) : -ENODEV; | |
485 | } | |
486 | ||
b67ea761 RW |
487 | static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable) |
488 | { | |
489 | return pci_platform_pm ? | |
490 | pci_platform_pm->run_wake(dev, enable) : -ENODEV; | |
491 | } | |
492 | ||
1da177e4 | 493 | /** |
44e4e66e RW |
494 | * pci_raw_set_power_state - Use PCI PM registers to set the power state of |
495 | * given PCI device | |
496 | * @dev: PCI device to handle. | |
44e4e66e | 497 | * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. |
1da177e4 | 498 | * |
44e4e66e RW |
499 | * RETURN VALUE: |
500 | * -EINVAL if the requested state is invalid. | |
501 | * -EIO if device does not support PCI PM or its PM capabilities register has a | |
502 | * wrong version, or device doesn't support the requested state. | |
503 | * 0 if device already is in the requested state. | |
504 | * 0 if device's power state has been successfully changed. | |
1da177e4 | 505 | */ |
f00a20ef | 506 | static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state) |
1da177e4 | 507 | { |
337001b6 | 508 | u16 pmcsr; |
44e4e66e | 509 | bool need_restore = false; |
1da177e4 | 510 | |
4a865905 RW |
511 | /* Check if we're already there */ |
512 | if (dev->current_state == state) | |
513 | return 0; | |
514 | ||
337001b6 | 515 | if (!dev->pm_cap) |
cca03dec AL |
516 | return -EIO; |
517 | ||
44e4e66e RW |
518 | if (state < PCI_D0 || state > PCI_D3hot) |
519 | return -EINVAL; | |
520 | ||
1da177e4 LT |
521 | /* Validate current state: |
522 | * Can enter D0 from any state, but if we can only go deeper | |
523 | * to sleep if we're already in a low power state | |
524 | */ | |
4a865905 | 525 | if (state != PCI_D0 && dev->current_state <= PCI_D3cold |
44e4e66e | 526 | && dev->current_state > state) { |
80ccba11 BH |
527 | dev_err(&dev->dev, "invalid power transition " |
528 | "(from state %d to %d)\n", dev->current_state, state); | |
1da177e4 | 529 | return -EINVAL; |
44e4e66e | 530 | } |
1da177e4 | 531 | |
1da177e4 | 532 | /* check if this device supports the desired state */ |
337001b6 RW |
533 | if ((state == PCI_D1 && !dev->d1_support) |
534 | || (state == PCI_D2 && !dev->d2_support)) | |
3fe9d19f | 535 | return -EIO; |
1da177e4 | 536 | |
337001b6 | 537 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
064b53db | 538 | |
32a36585 | 539 | /* If we're (effectively) in D3, force entire word to 0. |
1da177e4 LT |
540 | * This doesn't affect PME_Status, disables PME_En, and |
541 | * sets PowerState to 0. | |
542 | */ | |
32a36585 | 543 | switch (dev->current_state) { |
d3535fbb JL |
544 | case PCI_D0: |
545 | case PCI_D1: | |
546 | case PCI_D2: | |
547 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | |
548 | pmcsr |= state; | |
549 | break; | |
f62795f1 RW |
550 | case PCI_D3hot: |
551 | case PCI_D3cold: | |
32a36585 JL |
552 | case PCI_UNKNOWN: /* Boot-up */ |
553 | if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot | |
f00a20ef | 554 | && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) |
44e4e66e | 555 | need_restore = true; |
32a36585 | 556 | /* Fall-through: force to D0 */ |
32a36585 | 557 | default: |
d3535fbb | 558 | pmcsr = 0; |
32a36585 | 559 | break; |
1da177e4 LT |
560 | } |
561 | ||
562 | /* enter specified state */ | |
337001b6 | 563 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); |
1da177e4 LT |
564 | |
565 | /* Mandatory power management transition delays */ | |
566 | /* see PCI PM 1.1 5.6.1 table 18 */ | |
567 | if (state == PCI_D3hot || dev->current_state == PCI_D3hot) | |
1ae861e6 | 568 | pci_dev_d3_sleep(dev); |
1da177e4 | 569 | else if (state == PCI_D2 || dev->current_state == PCI_D2) |
aa8c6c93 | 570 | udelay(PCI_PM_D2_DELAY); |
1da177e4 | 571 | |
e13cdbd7 RW |
572 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
573 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); | |
574 | if (dev->current_state != state && printk_ratelimit()) | |
575 | dev_info(&dev->dev, "Refused to change power state, " | |
576 | "currently in D%d\n", dev->current_state); | |
064b53db | 577 | |
448bd857 HY |
578 | /* |
579 | * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT | |
064b53db JL |
580 | * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning |
581 | * from D3hot to D0 _may_ perform an internal reset, thereby | |
582 | * going to "D0 Uninitialized" rather than "D0 Initialized". | |
583 | * For example, at least some versions of the 3c905B and the | |
584 | * 3c556B exhibit this behaviour. | |
585 | * | |
586 | * At least some laptop BIOSen (e.g. the Thinkpad T21) leave | |
587 | * devices in a D3hot state at boot. Consequently, we need to | |
588 | * restore at least the BARs so that the device will be | |
589 | * accessible to its driver. | |
590 | */ | |
591 | if (need_restore) | |
592 | pci_restore_bars(dev); | |
593 | ||
f00a20ef | 594 | if (dev->bus->self) |
7d715a6c SL |
595 | pcie_aspm_pm_state_change(dev->bus->self); |
596 | ||
1da177e4 LT |
597 | return 0; |
598 | } | |
599 | ||
44e4e66e RW |
600 | /** |
601 | * pci_update_current_state - Read PCI power state of given device from its | |
602 | * PCI PM registers and cache it | |
603 | * @dev: PCI device to handle. | |
f06fc0b6 | 604 | * @state: State to cache in case the device doesn't have the PM capability |
44e4e66e | 605 | */ |
73410429 | 606 | void pci_update_current_state(struct pci_dev *dev, pci_power_t state) |
44e4e66e | 607 | { |
337001b6 | 608 | if (dev->pm_cap) { |
44e4e66e RW |
609 | u16 pmcsr; |
610 | ||
448bd857 HY |
611 | /* |
612 | * Configuration space is not accessible for device in | |
613 | * D3cold, so just keep or set D3cold for safety | |
614 | */ | |
615 | if (dev->current_state == PCI_D3cold) | |
616 | return; | |
617 | if (state == PCI_D3cold) { | |
618 | dev->current_state = PCI_D3cold; | |
619 | return; | |
620 | } | |
337001b6 | 621 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
44e4e66e | 622 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); |
f06fc0b6 RW |
623 | } else { |
624 | dev->current_state = state; | |
44e4e66e RW |
625 | } |
626 | } | |
627 | ||
db288c9c RW |
628 | /** |
629 | * pci_power_up - Put the given device into D0 forcibly | |
630 | * @dev: PCI device to power up | |
631 | */ | |
632 | void pci_power_up(struct pci_dev *dev) | |
633 | { | |
634 | if (platform_pci_power_manageable(dev)) | |
635 | platform_pci_set_power_state(dev, PCI_D0); | |
636 | ||
637 | pci_raw_set_power_state(dev, PCI_D0); | |
638 | pci_update_current_state(dev, PCI_D0); | |
639 | } | |
640 | ||
0e5dd46b RW |
641 | /** |
642 | * pci_platform_power_transition - Use platform to change device power state | |
643 | * @dev: PCI device to handle. | |
644 | * @state: State to put the device into. | |
645 | */ | |
646 | static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state) | |
647 | { | |
648 | int error; | |
649 | ||
650 | if (platform_pci_power_manageable(dev)) { | |
651 | error = platform_pci_set_power_state(dev, state); | |
652 | if (!error) | |
653 | pci_update_current_state(dev, state); | |
b51306c6 AH |
654 | /* Fall back to PCI_D0 if native PM is not supported */ |
655 | if (!dev->pm_cap) | |
656 | dev->current_state = PCI_D0; | |
0e5dd46b RW |
657 | } else { |
658 | error = -ENODEV; | |
659 | /* Fall back to PCI_D0 if native PM is not supported */ | |
b3bad72e RW |
660 | if (!dev->pm_cap) |
661 | dev->current_state = PCI_D0; | |
0e5dd46b RW |
662 | } |
663 | ||
664 | return error; | |
665 | } | |
666 | ||
667 | /** | |
668 | * __pci_start_power_transition - Start power transition of a PCI device | |
669 | * @dev: PCI device to handle. | |
670 | * @state: State to put the device into. | |
671 | */ | |
672 | static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state) | |
673 | { | |
448bd857 | 674 | if (state == PCI_D0) { |
0e5dd46b | 675 | pci_platform_power_transition(dev, PCI_D0); |
448bd857 HY |
676 | /* |
677 | * Mandatory power management transition delays, see | |
678 | * PCI Express Base Specification Revision 2.0 Section | |
679 | * 6.6.1: Conventional Reset. Do not delay for | |
680 | * devices powered on/off by corresponding bridge, | |
681 | * because have already delayed for the bridge. | |
682 | */ | |
683 | if (dev->runtime_d3cold) { | |
684 | msleep(dev->d3cold_delay); | |
685 | /* | |
686 | * When powering on a bridge from D3cold, the | |
687 | * whole hierarchy may be powered on into | |
688 | * D0uninitialized state, resume them to give | |
689 | * them a chance to suspend again | |
690 | */ | |
691 | pci_wakeup_bus(dev->subordinate); | |
692 | } | |
693 | } | |
694 | } | |
695 | ||
696 | /** | |
697 | * __pci_dev_set_current_state - Set current state of a PCI device | |
698 | * @dev: Device to handle | |
699 | * @data: pointer to state to be set | |
700 | */ | |
701 | static int __pci_dev_set_current_state(struct pci_dev *dev, void *data) | |
702 | { | |
703 | pci_power_t state = *(pci_power_t *)data; | |
704 | ||
705 | dev->current_state = state; | |
706 | return 0; | |
707 | } | |
708 | ||
709 | /** | |
710 | * __pci_bus_set_current_state - Walk given bus and set current state of devices | |
711 | * @bus: Top bus of the subtree to walk. | |
712 | * @state: state to be set | |
713 | */ | |
714 | static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state) | |
715 | { | |
716 | if (bus) | |
717 | pci_walk_bus(bus, __pci_dev_set_current_state, &state); | |
0e5dd46b RW |
718 | } |
719 | ||
720 | /** | |
721 | * __pci_complete_power_transition - Complete power transition of a PCI device | |
722 | * @dev: PCI device to handle. | |
723 | * @state: State to put the device into. | |
724 | * | |
725 | * This function should not be called directly by device drivers. | |
726 | */ | |
727 | int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state) | |
728 | { | |
448bd857 HY |
729 | int ret; |
730 | ||
db288c9c | 731 | if (state <= PCI_D0) |
448bd857 HY |
732 | return -EINVAL; |
733 | ret = pci_platform_power_transition(dev, state); | |
734 | /* Power off the bridge may power off the whole hierarchy */ | |
735 | if (!ret && state == PCI_D3cold) | |
736 | __pci_bus_set_current_state(dev->subordinate, PCI_D3cold); | |
737 | return ret; | |
0e5dd46b RW |
738 | } |
739 | EXPORT_SYMBOL_GPL(__pci_complete_power_transition); | |
740 | ||
44e4e66e RW |
741 | /** |
742 | * pci_set_power_state - Set the power state of a PCI device | |
743 | * @dev: PCI device to handle. | |
744 | * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. | |
745 | * | |
877d0310 | 746 | * Transition a device to a new power state, using the platform firmware and/or |
44e4e66e RW |
747 | * the device's PCI PM registers. |
748 | * | |
749 | * RETURN VALUE: | |
750 | * -EINVAL if the requested state is invalid. | |
751 | * -EIO if device does not support PCI PM or its PM capabilities register has a | |
752 | * wrong version, or device doesn't support the requested state. | |
753 | * 0 if device already is in the requested state. | |
754 | * 0 if device's power state has been successfully changed. | |
755 | */ | |
756 | int pci_set_power_state(struct pci_dev *dev, pci_power_t state) | |
757 | { | |
337001b6 | 758 | int error; |
44e4e66e RW |
759 | |
760 | /* bound the state we're entering */ | |
448bd857 HY |
761 | if (state > PCI_D3cold) |
762 | state = PCI_D3cold; | |
44e4e66e RW |
763 | else if (state < PCI_D0) |
764 | state = PCI_D0; | |
765 | else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev)) | |
766 | /* | |
767 | * If the device or the parent bridge do not support PCI PM, | |
768 | * ignore the request if we're doing anything other than putting | |
769 | * it into D0 (which would only happen on boot). | |
770 | */ | |
771 | return 0; | |
772 | ||
db288c9c RW |
773 | /* Check if we're already there */ |
774 | if (dev->current_state == state) | |
775 | return 0; | |
776 | ||
0e5dd46b RW |
777 | __pci_start_power_transition(dev, state); |
778 | ||
979b1791 AC |
779 | /* This device is quirked not to be put into D3, so |
780 | don't put it in D3 */ | |
448bd857 | 781 | if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3)) |
979b1791 | 782 | return 0; |
44e4e66e | 783 | |
448bd857 HY |
784 | /* |
785 | * To put device in D3cold, we put device into D3hot in native | |
786 | * way, then put device into D3cold with platform ops | |
787 | */ | |
788 | error = pci_raw_set_power_state(dev, state > PCI_D3hot ? | |
789 | PCI_D3hot : state); | |
44e4e66e | 790 | |
0e5dd46b RW |
791 | if (!__pci_complete_power_transition(dev, state)) |
792 | error = 0; | |
1a680b7c NC |
793 | /* |
794 | * When aspm_policy is "powersave" this call ensures | |
795 | * that ASPM is configured. | |
796 | */ | |
797 | if (!error && dev->bus->self) | |
798 | pcie_aspm_powersave_config_link(dev->bus->self); | |
44e4e66e RW |
799 | |
800 | return error; | |
801 | } | |
802 | ||
1da177e4 LT |
803 | /** |
804 | * pci_choose_state - Choose the power state of a PCI device | |
805 | * @dev: PCI device to be suspended | |
806 | * @state: target sleep state for the whole system. This is the value | |
807 | * that is passed to suspend() function. | |
808 | * | |
809 | * Returns PCI power state suitable for given device and given system | |
810 | * message. | |
811 | */ | |
812 | ||
813 | pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) | |
814 | { | |
ab826ca4 | 815 | pci_power_t ret; |
0f64474b | 816 | |
1da177e4 LT |
817 | if (!pci_find_capability(dev, PCI_CAP_ID_PM)) |
818 | return PCI_D0; | |
819 | ||
961d9120 RW |
820 | ret = platform_pci_choose_state(dev); |
821 | if (ret != PCI_POWER_ERROR) | |
822 | return ret; | |
ca078bae PM |
823 | |
824 | switch (state.event) { | |
825 | case PM_EVENT_ON: | |
826 | return PCI_D0; | |
827 | case PM_EVENT_FREEZE: | |
b887d2e6 DB |
828 | case PM_EVENT_PRETHAW: |
829 | /* REVISIT both freeze and pre-thaw "should" use D0 */ | |
ca078bae | 830 | case PM_EVENT_SUSPEND: |
3a2d5b70 | 831 | case PM_EVENT_HIBERNATE: |
ca078bae | 832 | return PCI_D3hot; |
1da177e4 | 833 | default: |
80ccba11 BH |
834 | dev_info(&dev->dev, "unrecognized suspend event %d\n", |
835 | state.event); | |
1da177e4 LT |
836 | BUG(); |
837 | } | |
838 | return PCI_D0; | |
839 | } | |
840 | ||
841 | EXPORT_SYMBOL(pci_choose_state); | |
842 | ||
89858517 YZ |
843 | #define PCI_EXP_SAVE_REGS 7 |
844 | ||
1b6b8ce2 | 845 | |
34a4876e YL |
846 | static struct pci_cap_saved_state *pci_find_saved_cap( |
847 | struct pci_dev *pci_dev, char cap) | |
848 | { | |
849 | struct pci_cap_saved_state *tmp; | |
850 | struct hlist_node *pos; | |
851 | ||
852 | hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) { | |
853 | if (tmp->cap.cap_nr == cap) | |
854 | return tmp; | |
855 | } | |
856 | return NULL; | |
857 | } | |
858 | ||
b56a5a23 MT |
859 | static int pci_save_pcie_state(struct pci_dev *dev) |
860 | { | |
59875ae4 | 861 | int i = 0; |
b56a5a23 MT |
862 | struct pci_cap_saved_state *save_state; |
863 | u16 *cap; | |
864 | ||
59875ae4 | 865 | if (!pci_is_pcie(dev)) |
b56a5a23 MT |
866 | return 0; |
867 | ||
9f35575d | 868 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); |
b56a5a23 | 869 | if (!save_state) { |
e496b617 | 870 | dev_err(&dev->dev, "buffer not found in %s\n", __func__); |
b56a5a23 MT |
871 | return -ENOMEM; |
872 | } | |
63f4898a | 873 | |
59875ae4 JL |
874 | cap = (u16 *)&save_state->cap.data[0]; |
875 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]); | |
876 | pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]); | |
877 | pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]); | |
878 | pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]); | |
879 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]); | |
880 | pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]); | |
881 | pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]); | |
9cb604ed | 882 | |
b56a5a23 MT |
883 | return 0; |
884 | } | |
885 | ||
886 | static void pci_restore_pcie_state(struct pci_dev *dev) | |
887 | { | |
59875ae4 | 888 | int i = 0; |
b56a5a23 MT |
889 | struct pci_cap_saved_state *save_state; |
890 | u16 *cap; | |
891 | ||
892 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); | |
59875ae4 | 893 | if (!save_state) |
9cb604ed MS |
894 | return; |
895 | ||
59875ae4 JL |
896 | cap = (u16 *)&save_state->cap.data[0]; |
897 | pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]); | |
898 | pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]); | |
899 | pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]); | |
900 | pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]); | |
901 | pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]); | |
902 | pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]); | |
903 | pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]); | |
b56a5a23 MT |
904 | } |
905 | ||
cc692a5f SH |
906 | |
907 | static int pci_save_pcix_state(struct pci_dev *dev) | |
908 | { | |
63f4898a | 909 | int pos; |
cc692a5f | 910 | struct pci_cap_saved_state *save_state; |
cc692a5f SH |
911 | |
912 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
913 | if (pos <= 0) | |
914 | return 0; | |
915 | ||
f34303de | 916 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); |
cc692a5f | 917 | if (!save_state) { |
e496b617 | 918 | dev_err(&dev->dev, "buffer not found in %s\n", __func__); |
cc692a5f SH |
919 | return -ENOMEM; |
920 | } | |
cc692a5f | 921 | |
24a4742f AW |
922 | pci_read_config_word(dev, pos + PCI_X_CMD, |
923 | (u16 *)save_state->cap.data); | |
63f4898a | 924 | |
cc692a5f SH |
925 | return 0; |
926 | } | |
927 | ||
928 | static void pci_restore_pcix_state(struct pci_dev *dev) | |
929 | { | |
930 | int i = 0, pos; | |
931 | struct pci_cap_saved_state *save_state; | |
932 | u16 *cap; | |
933 | ||
934 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); | |
935 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
936 | if (!save_state || pos <= 0) | |
937 | return; | |
24a4742f | 938 | cap = (u16 *)&save_state->cap.data[0]; |
cc692a5f SH |
939 | |
940 | pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]); | |
cc692a5f SH |
941 | } |
942 | ||
943 | ||
1da177e4 LT |
944 | /** |
945 | * pci_save_state - save the PCI configuration space of a device before suspending | |
946 | * @dev: - PCI device that we're dealing with | |
1da177e4 LT |
947 | */ |
948 | int | |
949 | pci_save_state(struct pci_dev *dev) | |
950 | { | |
951 | int i; | |
952 | /* XXX: 100% dword access ok here? */ | |
953 | for (i = 0; i < 16; i++) | |
9e0b5b2c | 954 | pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]); |
aa8c6c93 | 955 | dev->state_saved = true; |
b56a5a23 MT |
956 | if ((i = pci_save_pcie_state(dev)) != 0) |
957 | return i; | |
cc692a5f SH |
958 | if ((i = pci_save_pcix_state(dev)) != 0) |
959 | return i; | |
1da177e4 LT |
960 | return 0; |
961 | } | |
962 | ||
ebfc5b80 RW |
963 | static void pci_restore_config_dword(struct pci_dev *pdev, int offset, |
964 | u32 saved_val, int retry) | |
965 | { | |
966 | u32 val; | |
967 | ||
968 | pci_read_config_dword(pdev, offset, &val); | |
969 | if (val == saved_val) | |
970 | return; | |
971 | ||
972 | for (;;) { | |
973 | dev_dbg(&pdev->dev, "restoring config space at offset " | |
974 | "%#x (was %#x, writing %#x)\n", offset, val, saved_val); | |
975 | pci_write_config_dword(pdev, offset, saved_val); | |
976 | if (retry-- <= 0) | |
977 | return; | |
978 | ||
979 | pci_read_config_dword(pdev, offset, &val); | |
980 | if (val == saved_val) | |
981 | return; | |
982 | ||
983 | mdelay(1); | |
984 | } | |
985 | } | |
986 | ||
a6cb9ee7 RW |
987 | static void pci_restore_config_space_range(struct pci_dev *pdev, |
988 | int start, int end, int retry) | |
ebfc5b80 RW |
989 | { |
990 | int index; | |
991 | ||
992 | for (index = end; index >= start; index--) | |
993 | pci_restore_config_dword(pdev, 4 * index, | |
994 | pdev->saved_config_space[index], | |
995 | retry); | |
996 | } | |
997 | ||
a6cb9ee7 RW |
998 | static void pci_restore_config_space(struct pci_dev *pdev) |
999 | { | |
1000 | if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) { | |
1001 | pci_restore_config_space_range(pdev, 10, 15, 0); | |
1002 | /* Restore BARs before the command register. */ | |
1003 | pci_restore_config_space_range(pdev, 4, 9, 10); | |
1004 | pci_restore_config_space_range(pdev, 0, 3, 0); | |
1005 | } else { | |
1006 | pci_restore_config_space_range(pdev, 0, 15, 0); | |
1007 | } | |
1008 | } | |
1009 | ||
1da177e4 LT |
1010 | /** |
1011 | * pci_restore_state - Restore the saved state of a PCI device | |
1012 | * @dev: - PCI device that we're dealing with | |
1da177e4 | 1013 | */ |
1d3c16a8 | 1014 | void pci_restore_state(struct pci_dev *dev) |
1da177e4 | 1015 | { |
c82f63e4 | 1016 | if (!dev->state_saved) |
1d3c16a8 | 1017 | return; |
4b77b0a2 | 1018 | |
b56a5a23 MT |
1019 | /* PCI Express register must be restored first */ |
1020 | pci_restore_pcie_state(dev); | |
1900ca13 | 1021 | pci_restore_ats_state(dev); |
b56a5a23 | 1022 | |
a6cb9ee7 | 1023 | pci_restore_config_space(dev); |
ebfc5b80 | 1024 | |
cc692a5f | 1025 | pci_restore_pcix_state(dev); |
41017f0c | 1026 | pci_restore_msi_state(dev); |
8c5cdb6a | 1027 | pci_restore_iov_state(dev); |
8fed4b65 | 1028 | |
4b77b0a2 | 1029 | dev->state_saved = false; |
1da177e4 LT |
1030 | } |
1031 | ||
ffbdd3f7 AW |
1032 | struct pci_saved_state { |
1033 | u32 config_space[16]; | |
1034 | struct pci_cap_saved_data cap[0]; | |
1035 | }; | |
1036 | ||
1037 | /** | |
1038 | * pci_store_saved_state - Allocate and return an opaque struct containing | |
1039 | * the device saved state. | |
1040 | * @dev: PCI device that we're dealing with | |
1041 | * | |
1042 | * Rerturn NULL if no state or error. | |
1043 | */ | |
1044 | struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev) | |
1045 | { | |
1046 | struct pci_saved_state *state; | |
1047 | struct pci_cap_saved_state *tmp; | |
1048 | struct pci_cap_saved_data *cap; | |
1049 | struct hlist_node *pos; | |
1050 | size_t size; | |
1051 | ||
1052 | if (!dev->state_saved) | |
1053 | return NULL; | |
1054 | ||
1055 | size = sizeof(*state) + sizeof(struct pci_cap_saved_data); | |
1056 | ||
1057 | hlist_for_each_entry(tmp, pos, &dev->saved_cap_space, next) | |
1058 | size += sizeof(struct pci_cap_saved_data) + tmp->cap.size; | |
1059 | ||
1060 | state = kzalloc(size, GFP_KERNEL); | |
1061 | if (!state) | |
1062 | return NULL; | |
1063 | ||
1064 | memcpy(state->config_space, dev->saved_config_space, | |
1065 | sizeof(state->config_space)); | |
1066 | ||
1067 | cap = state->cap; | |
1068 | hlist_for_each_entry(tmp, pos, &dev->saved_cap_space, next) { | |
1069 | size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size; | |
1070 | memcpy(cap, &tmp->cap, len); | |
1071 | cap = (struct pci_cap_saved_data *)((u8 *)cap + len); | |
1072 | } | |
1073 | /* Empty cap_save terminates list */ | |
1074 | ||
1075 | return state; | |
1076 | } | |
1077 | EXPORT_SYMBOL_GPL(pci_store_saved_state); | |
1078 | ||
1079 | /** | |
1080 | * pci_load_saved_state - Reload the provided save state into struct pci_dev. | |
1081 | * @dev: PCI device that we're dealing with | |
1082 | * @state: Saved state returned from pci_store_saved_state() | |
1083 | */ | |
1084 | int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state) | |
1085 | { | |
1086 | struct pci_cap_saved_data *cap; | |
1087 | ||
1088 | dev->state_saved = false; | |
1089 | ||
1090 | if (!state) | |
1091 | return 0; | |
1092 | ||
1093 | memcpy(dev->saved_config_space, state->config_space, | |
1094 | sizeof(state->config_space)); | |
1095 | ||
1096 | cap = state->cap; | |
1097 | while (cap->size) { | |
1098 | struct pci_cap_saved_state *tmp; | |
1099 | ||
1100 | tmp = pci_find_saved_cap(dev, cap->cap_nr); | |
1101 | if (!tmp || tmp->cap.size != cap->size) | |
1102 | return -EINVAL; | |
1103 | ||
1104 | memcpy(tmp->cap.data, cap->data, tmp->cap.size); | |
1105 | cap = (struct pci_cap_saved_data *)((u8 *)cap + | |
1106 | sizeof(struct pci_cap_saved_data) + cap->size); | |
1107 | } | |
1108 | ||
1109 | dev->state_saved = true; | |
1110 | return 0; | |
1111 | } | |
1112 | EXPORT_SYMBOL_GPL(pci_load_saved_state); | |
1113 | ||
1114 | /** | |
1115 | * pci_load_and_free_saved_state - Reload the save state pointed to by state, | |
1116 | * and free the memory allocated for it. | |
1117 | * @dev: PCI device that we're dealing with | |
1118 | * @state: Pointer to saved state returned from pci_store_saved_state() | |
1119 | */ | |
1120 | int pci_load_and_free_saved_state(struct pci_dev *dev, | |
1121 | struct pci_saved_state **state) | |
1122 | { | |
1123 | int ret = pci_load_saved_state(dev, *state); | |
1124 | kfree(*state); | |
1125 | *state = NULL; | |
1126 | return ret; | |
1127 | } | |
1128 | EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state); | |
1129 | ||
38cc1302 HS |
1130 | static int do_pci_enable_device(struct pci_dev *dev, int bars) |
1131 | { | |
1132 | int err; | |
1133 | ||
1134 | err = pci_set_power_state(dev, PCI_D0); | |
1135 | if (err < 0 && err != -EIO) | |
1136 | return err; | |
1137 | err = pcibios_enable_device(dev, bars); | |
1138 | if (err < 0) | |
1139 | return err; | |
1140 | pci_fixup_device(pci_fixup_enable, dev); | |
1141 | ||
1142 | return 0; | |
1143 | } | |
1144 | ||
1145 | /** | |
0b62e13b | 1146 | * pci_reenable_device - Resume abandoned device |
38cc1302 HS |
1147 | * @dev: PCI device to be resumed |
1148 | * | |
1149 | * Note this function is a backend of pci_default_resume and is not supposed | |
1150 | * to be called by normal code, write proper resume handler and use it instead. | |
1151 | */ | |
0b62e13b | 1152 | int pci_reenable_device(struct pci_dev *dev) |
38cc1302 | 1153 | { |
296ccb08 | 1154 | if (pci_is_enabled(dev)) |
38cc1302 HS |
1155 | return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1); |
1156 | return 0; | |
1157 | } | |
1158 | ||
b718989d BH |
1159 | static int __pci_enable_device_flags(struct pci_dev *dev, |
1160 | resource_size_t flags) | |
1da177e4 LT |
1161 | { |
1162 | int err; | |
b718989d | 1163 | int i, bars = 0; |
1da177e4 | 1164 | |
97c145f7 JB |
1165 | /* |
1166 | * Power state could be unknown at this point, either due to a fresh | |
1167 | * boot or a device removal call. So get the current power state | |
1168 | * so that things like MSI message writing will behave as expected | |
1169 | * (e.g. if the device really is in D0 at enable time). | |
1170 | */ | |
1171 | if (dev->pm_cap) { | |
1172 | u16 pmcsr; | |
1173 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); | |
1174 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); | |
1175 | } | |
1176 | ||
9fb625c3 HS |
1177 | if (atomic_add_return(1, &dev->enable_cnt) > 1) |
1178 | return 0; /* already enabled */ | |
1179 | ||
497f16f2 YL |
1180 | /* only skip sriov related */ |
1181 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) | |
1182 | if (dev->resource[i].flags & flags) | |
1183 | bars |= (1 << i); | |
1184 | for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++) | |
b718989d BH |
1185 | if (dev->resource[i].flags & flags) |
1186 | bars |= (1 << i); | |
1187 | ||
38cc1302 | 1188 | err = do_pci_enable_device(dev, bars); |
95a62965 | 1189 | if (err < 0) |
38cc1302 | 1190 | atomic_dec(&dev->enable_cnt); |
9fb625c3 | 1191 | return err; |
1da177e4 LT |
1192 | } |
1193 | ||
b718989d BH |
1194 | /** |
1195 | * pci_enable_device_io - Initialize a device for use with IO space | |
1196 | * @dev: PCI device to be initialized | |
1197 | * | |
1198 | * Initialize device before it's used by a driver. Ask low-level code | |
1199 | * to enable I/O resources. Wake up the device if it was suspended. | |
1200 | * Beware, this function can fail. | |
1201 | */ | |
1202 | int pci_enable_device_io(struct pci_dev *dev) | |
1203 | { | |
1204 | return __pci_enable_device_flags(dev, IORESOURCE_IO); | |
1205 | } | |
1206 | ||
1207 | /** | |
1208 | * pci_enable_device_mem - Initialize a device for use with Memory space | |
1209 | * @dev: PCI device to be initialized | |
1210 | * | |
1211 | * Initialize device before it's used by a driver. Ask low-level code | |
1212 | * to enable Memory resources. Wake up the device if it was suspended. | |
1213 | * Beware, this function can fail. | |
1214 | */ | |
1215 | int pci_enable_device_mem(struct pci_dev *dev) | |
1216 | { | |
1217 | return __pci_enable_device_flags(dev, IORESOURCE_MEM); | |
1218 | } | |
1219 | ||
bae94d02 IPG |
1220 | /** |
1221 | * pci_enable_device - Initialize device before it's used by a driver. | |
1222 | * @dev: PCI device to be initialized | |
1223 | * | |
1224 | * Initialize device before it's used by a driver. Ask low-level code | |
1225 | * to enable I/O and memory. Wake up the device if it was suspended. | |
1226 | * Beware, this function can fail. | |
1227 | * | |
1228 | * Note we don't actually enable the device many times if we call | |
1229 | * this function repeatedly (we just increment the count). | |
1230 | */ | |
1231 | int pci_enable_device(struct pci_dev *dev) | |
1232 | { | |
b718989d | 1233 | return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO); |
bae94d02 IPG |
1234 | } |
1235 | ||
9ac7849e TH |
1236 | /* |
1237 | * Managed PCI resources. This manages device on/off, intx/msi/msix | |
1238 | * on/off and BAR regions. pci_dev itself records msi/msix status, so | |
1239 | * there's no need to track it separately. pci_devres is initialized | |
1240 | * when a device is enabled using managed PCI device enable interface. | |
1241 | */ | |
1242 | struct pci_devres { | |
7f375f32 TH |
1243 | unsigned int enabled:1; |
1244 | unsigned int pinned:1; | |
9ac7849e TH |
1245 | unsigned int orig_intx:1; |
1246 | unsigned int restore_intx:1; | |
1247 | u32 region_mask; | |
1248 | }; | |
1249 | ||
1250 | static void pcim_release(struct device *gendev, void *res) | |
1251 | { | |
1252 | struct pci_dev *dev = container_of(gendev, struct pci_dev, dev); | |
1253 | struct pci_devres *this = res; | |
1254 | int i; | |
1255 | ||
1256 | if (dev->msi_enabled) | |
1257 | pci_disable_msi(dev); | |
1258 | if (dev->msix_enabled) | |
1259 | pci_disable_msix(dev); | |
1260 | ||
1261 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) | |
1262 | if (this->region_mask & (1 << i)) | |
1263 | pci_release_region(dev, i); | |
1264 | ||
1265 | if (this->restore_intx) | |
1266 | pci_intx(dev, this->orig_intx); | |
1267 | ||
7f375f32 | 1268 | if (this->enabled && !this->pinned) |
9ac7849e TH |
1269 | pci_disable_device(dev); |
1270 | } | |
1271 | ||
1272 | static struct pci_devres * get_pci_dr(struct pci_dev *pdev) | |
1273 | { | |
1274 | struct pci_devres *dr, *new_dr; | |
1275 | ||
1276 | dr = devres_find(&pdev->dev, pcim_release, NULL, NULL); | |
1277 | if (dr) | |
1278 | return dr; | |
1279 | ||
1280 | new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL); | |
1281 | if (!new_dr) | |
1282 | return NULL; | |
1283 | return devres_get(&pdev->dev, new_dr, NULL, NULL); | |
1284 | } | |
1285 | ||
1286 | static struct pci_devres * find_pci_dr(struct pci_dev *pdev) | |
1287 | { | |
1288 | if (pci_is_managed(pdev)) | |
1289 | return devres_find(&pdev->dev, pcim_release, NULL, NULL); | |
1290 | return NULL; | |
1291 | } | |
1292 | ||
1293 | /** | |
1294 | * pcim_enable_device - Managed pci_enable_device() | |
1295 | * @pdev: PCI device to be initialized | |
1296 | * | |
1297 | * Managed pci_enable_device(). | |
1298 | */ | |
1299 | int pcim_enable_device(struct pci_dev *pdev) | |
1300 | { | |
1301 | struct pci_devres *dr; | |
1302 | int rc; | |
1303 | ||
1304 | dr = get_pci_dr(pdev); | |
1305 | if (unlikely(!dr)) | |
1306 | return -ENOMEM; | |
b95d58ea TH |
1307 | if (dr->enabled) |
1308 | return 0; | |
9ac7849e TH |
1309 | |
1310 | rc = pci_enable_device(pdev); | |
1311 | if (!rc) { | |
1312 | pdev->is_managed = 1; | |
7f375f32 | 1313 | dr->enabled = 1; |
9ac7849e TH |
1314 | } |
1315 | return rc; | |
1316 | } | |
1317 | ||
1318 | /** | |
1319 | * pcim_pin_device - Pin managed PCI device | |
1320 | * @pdev: PCI device to pin | |
1321 | * | |
1322 | * Pin managed PCI device @pdev. Pinned device won't be disabled on | |
1323 | * driver detach. @pdev must have been enabled with | |
1324 | * pcim_enable_device(). | |
1325 | */ | |
1326 | void pcim_pin_device(struct pci_dev *pdev) | |
1327 | { | |
1328 | struct pci_devres *dr; | |
1329 | ||
1330 | dr = find_pci_dr(pdev); | |
7f375f32 | 1331 | WARN_ON(!dr || !dr->enabled); |
9ac7849e | 1332 | if (dr) |
7f375f32 | 1333 | dr->pinned = 1; |
9ac7849e TH |
1334 | } |
1335 | ||
1da177e4 LT |
1336 | /** |
1337 | * pcibios_disable_device - disable arch specific PCI resources for device dev | |
1338 | * @dev: the PCI device to disable | |
1339 | * | |
1340 | * Disables architecture specific PCI resources for the device. This | |
1341 | * is the default implementation. Architecture implementations can | |
1342 | * override this. | |
1343 | */ | |
d6d88c83 | 1344 | void __weak pcibios_disable_device (struct pci_dev *dev) {} |
1da177e4 | 1345 | |
fa58d305 RW |
1346 | static void do_pci_disable_device(struct pci_dev *dev) |
1347 | { | |
1348 | u16 pci_command; | |
1349 | ||
1350 | pci_read_config_word(dev, PCI_COMMAND, &pci_command); | |
1351 | if (pci_command & PCI_COMMAND_MASTER) { | |
1352 | pci_command &= ~PCI_COMMAND_MASTER; | |
1353 | pci_write_config_word(dev, PCI_COMMAND, pci_command); | |
1354 | } | |
1355 | ||
1356 | pcibios_disable_device(dev); | |
1357 | } | |
1358 | ||
1359 | /** | |
1360 | * pci_disable_enabled_device - Disable device without updating enable_cnt | |
1361 | * @dev: PCI device to disable | |
1362 | * | |
1363 | * NOTE: This function is a backend of PCI power management routines and is | |
1364 | * not supposed to be called drivers. | |
1365 | */ | |
1366 | void pci_disable_enabled_device(struct pci_dev *dev) | |
1367 | { | |
296ccb08 | 1368 | if (pci_is_enabled(dev)) |
fa58d305 RW |
1369 | do_pci_disable_device(dev); |
1370 | } | |
1371 | ||
1da177e4 LT |
1372 | /** |
1373 | * pci_disable_device - Disable PCI device after use | |
1374 | * @dev: PCI device to be disabled | |
1375 | * | |
1376 | * Signal to the system that the PCI device is not in use by the system | |
1377 | * anymore. This only involves disabling PCI bus-mastering, if active. | |
bae94d02 IPG |
1378 | * |
1379 | * Note we don't actually disable the device until all callers of | |
ee6583f6 | 1380 | * pci_enable_device() have called pci_disable_device(). |
1da177e4 LT |
1381 | */ |
1382 | void | |
1383 | pci_disable_device(struct pci_dev *dev) | |
1384 | { | |
9ac7849e | 1385 | struct pci_devres *dr; |
99dc804d | 1386 | |
9ac7849e TH |
1387 | dr = find_pci_dr(dev); |
1388 | if (dr) | |
7f375f32 | 1389 | dr->enabled = 0; |
9ac7849e | 1390 | |
bae94d02 IPG |
1391 | if (atomic_sub_return(1, &dev->enable_cnt) != 0) |
1392 | return; | |
1393 | ||
fa58d305 | 1394 | do_pci_disable_device(dev); |
1da177e4 | 1395 | |
fa58d305 | 1396 | dev->is_busmaster = 0; |
1da177e4 LT |
1397 | } |
1398 | ||
f7bdd12d BK |
1399 | /** |
1400 | * pcibios_set_pcie_reset_state - set reset state for device dev | |
45e829ea | 1401 | * @dev: the PCIe device reset |
f7bdd12d BK |
1402 | * @state: Reset state to enter into |
1403 | * | |
1404 | * | |
45e829ea | 1405 | * Sets the PCIe reset state for the device. This is the default |
f7bdd12d BK |
1406 | * implementation. Architecture implementations can override this. |
1407 | */ | |
d6d88c83 BH |
1408 | int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev, |
1409 | enum pcie_reset_state state) | |
f7bdd12d BK |
1410 | { |
1411 | return -EINVAL; | |
1412 | } | |
1413 | ||
1414 | /** | |
1415 | * pci_set_pcie_reset_state - set reset state for device dev | |
45e829ea | 1416 | * @dev: the PCIe device reset |
f7bdd12d BK |
1417 | * @state: Reset state to enter into |
1418 | * | |
1419 | * | |
1420 | * Sets the PCI reset state for the device. | |
1421 | */ | |
1422 | int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) | |
1423 | { | |
1424 | return pcibios_set_pcie_reset_state(dev, state); | |
1425 | } | |
1426 | ||
58ff4633 RW |
1427 | /** |
1428 | * pci_check_pme_status - Check if given device has generated PME. | |
1429 | * @dev: Device to check. | |
1430 | * | |
1431 | * Check the PME status of the device and if set, clear it and clear PME enable | |
1432 | * (if set). Return 'true' if PME status and PME enable were both set or | |
1433 | * 'false' otherwise. | |
1434 | */ | |
1435 | bool pci_check_pme_status(struct pci_dev *dev) | |
1436 | { | |
1437 | int pmcsr_pos; | |
1438 | u16 pmcsr; | |
1439 | bool ret = false; | |
1440 | ||
1441 | if (!dev->pm_cap) | |
1442 | return false; | |
1443 | ||
1444 | pmcsr_pos = dev->pm_cap + PCI_PM_CTRL; | |
1445 | pci_read_config_word(dev, pmcsr_pos, &pmcsr); | |
1446 | if (!(pmcsr & PCI_PM_CTRL_PME_STATUS)) | |
1447 | return false; | |
1448 | ||
1449 | /* Clear PME status. */ | |
1450 | pmcsr |= PCI_PM_CTRL_PME_STATUS; | |
1451 | if (pmcsr & PCI_PM_CTRL_PME_ENABLE) { | |
1452 | /* Disable PME to avoid interrupt flood. */ | |
1453 | pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; | |
1454 | ret = true; | |
1455 | } | |
1456 | ||
1457 | pci_write_config_word(dev, pmcsr_pos, pmcsr); | |
1458 | ||
1459 | return ret; | |
1460 | } | |
1461 | ||
b67ea761 RW |
1462 | /** |
1463 | * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set. | |
1464 | * @dev: Device to handle. | |
379021d5 | 1465 | * @pme_poll_reset: Whether or not to reset the device's pme_poll flag. |
b67ea761 RW |
1466 | * |
1467 | * Check if @dev has generated PME and queue a resume request for it in that | |
1468 | * case. | |
1469 | */ | |
379021d5 | 1470 | static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset) |
b67ea761 | 1471 | { |
379021d5 RW |
1472 | if (pme_poll_reset && dev->pme_poll) |
1473 | dev->pme_poll = false; | |
1474 | ||
c125e96f | 1475 | if (pci_check_pme_status(dev)) { |
c125e96f | 1476 | pci_wakeup_event(dev); |
0f953bf6 | 1477 | pm_request_resume(&dev->dev); |
c125e96f | 1478 | } |
b67ea761 RW |
1479 | return 0; |
1480 | } | |
1481 | ||
1482 | /** | |
1483 | * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary. | |
1484 | * @bus: Top bus of the subtree to walk. | |
1485 | */ | |
1486 | void pci_pme_wakeup_bus(struct pci_bus *bus) | |
1487 | { | |
1488 | if (bus) | |
379021d5 | 1489 | pci_walk_bus(bus, pci_pme_wakeup, (void *)true); |
b67ea761 RW |
1490 | } |
1491 | ||
448bd857 HY |
1492 | /** |
1493 | * pci_wakeup - Wake up a PCI device | |
ceaf5b5f | 1494 | * @pci_dev: Device to handle. |
448bd857 HY |
1495 | * @ign: ignored parameter |
1496 | */ | |
1497 | static int pci_wakeup(struct pci_dev *pci_dev, void *ign) | |
1498 | { | |
1499 | pci_wakeup_event(pci_dev); | |
1500 | pm_request_resume(&pci_dev->dev); | |
1501 | return 0; | |
1502 | } | |
1503 | ||
1504 | /** | |
1505 | * pci_wakeup_bus - Walk given bus and wake up devices on it | |
1506 | * @bus: Top bus of the subtree to walk. | |
1507 | */ | |
1508 | void pci_wakeup_bus(struct pci_bus *bus) | |
1509 | { | |
1510 | if (bus) | |
1511 | pci_walk_bus(bus, pci_wakeup, NULL); | |
1512 | } | |
1513 | ||
eb9d0fe4 RW |
1514 | /** |
1515 | * pci_pme_capable - check the capability of PCI device to generate PME# | |
1516 | * @dev: PCI device to handle. | |
eb9d0fe4 RW |
1517 | * @state: PCI state from which device will issue PME#. |
1518 | */ | |
e5899e1b | 1519 | bool pci_pme_capable(struct pci_dev *dev, pci_power_t state) |
eb9d0fe4 | 1520 | { |
337001b6 | 1521 | if (!dev->pm_cap) |
eb9d0fe4 RW |
1522 | return false; |
1523 | ||
337001b6 | 1524 | return !!(dev->pme_support & (1 << state)); |
eb9d0fe4 RW |
1525 | } |
1526 | ||
df17e62e MG |
1527 | static void pci_pme_list_scan(struct work_struct *work) |
1528 | { | |
379021d5 | 1529 | struct pci_pme_device *pme_dev, *n; |
df17e62e MG |
1530 | |
1531 | mutex_lock(&pci_pme_list_mutex); | |
1532 | if (!list_empty(&pci_pme_list)) { | |
379021d5 RW |
1533 | list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) { |
1534 | if (pme_dev->dev->pme_poll) { | |
71a83bd7 ZY |
1535 | struct pci_dev *bridge; |
1536 | ||
1537 | bridge = pme_dev->dev->bus->self; | |
1538 | /* | |
1539 | * If bridge is in low power state, the | |
1540 | * configuration space of subordinate devices | |
1541 | * may be not accessible | |
1542 | */ | |
1543 | if (bridge && bridge->current_state != PCI_D0) | |
1544 | continue; | |
379021d5 RW |
1545 | pci_pme_wakeup(pme_dev->dev, NULL); |
1546 | } else { | |
1547 | list_del(&pme_dev->list); | |
1548 | kfree(pme_dev); | |
1549 | } | |
1550 | } | |
1551 | if (!list_empty(&pci_pme_list)) | |
1552 | schedule_delayed_work(&pci_pme_work, | |
1553 | msecs_to_jiffies(PME_TIMEOUT)); | |
df17e62e MG |
1554 | } |
1555 | mutex_unlock(&pci_pme_list_mutex); | |
1556 | } | |
1557 | ||
eb9d0fe4 RW |
1558 | /** |
1559 | * pci_pme_active - enable or disable PCI device's PME# function | |
1560 | * @dev: PCI device to handle. | |
eb9d0fe4 RW |
1561 | * @enable: 'true' to enable PME# generation; 'false' to disable it. |
1562 | * | |
1563 | * The caller must verify that the device is capable of generating PME# before | |
1564 | * calling this function with @enable equal to 'true'. | |
1565 | */ | |
5a6c9b60 | 1566 | void pci_pme_active(struct pci_dev *dev, bool enable) |
eb9d0fe4 RW |
1567 | { |
1568 | u16 pmcsr; | |
1569 | ||
337001b6 | 1570 | if (!dev->pm_cap) |
eb9d0fe4 RW |
1571 | return; |
1572 | ||
337001b6 | 1573 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
eb9d0fe4 RW |
1574 | /* Clear PME_Status by writing 1 to it and enable PME# */ |
1575 | pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE; | |
1576 | if (!enable) | |
1577 | pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; | |
1578 | ||
337001b6 | 1579 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); |
eb9d0fe4 | 1580 | |
df17e62e MG |
1581 | /* PCI (as opposed to PCIe) PME requires that the device have |
1582 | its PME# line hooked up correctly. Not all hardware vendors | |
1583 | do this, so the PME never gets delivered and the device | |
1584 | remains asleep. The easiest way around this is to | |
1585 | periodically walk the list of suspended devices and check | |
1586 | whether any have their PME flag set. The assumption is that | |
1587 | we'll wake up often enough anyway that this won't be a huge | |
1588 | hit, and the power savings from the devices will still be a | |
1589 | win. */ | |
1590 | ||
379021d5 | 1591 | if (dev->pme_poll) { |
df17e62e MG |
1592 | struct pci_pme_device *pme_dev; |
1593 | if (enable) { | |
1594 | pme_dev = kmalloc(sizeof(struct pci_pme_device), | |
1595 | GFP_KERNEL); | |
1596 | if (!pme_dev) | |
1597 | goto out; | |
1598 | pme_dev->dev = dev; | |
1599 | mutex_lock(&pci_pme_list_mutex); | |
1600 | list_add(&pme_dev->list, &pci_pme_list); | |
1601 | if (list_is_singular(&pci_pme_list)) | |
1602 | schedule_delayed_work(&pci_pme_work, | |
1603 | msecs_to_jiffies(PME_TIMEOUT)); | |
1604 | mutex_unlock(&pci_pme_list_mutex); | |
1605 | } else { | |
1606 | mutex_lock(&pci_pme_list_mutex); | |
1607 | list_for_each_entry(pme_dev, &pci_pme_list, list) { | |
1608 | if (pme_dev->dev == dev) { | |
1609 | list_del(&pme_dev->list); | |
1610 | kfree(pme_dev); | |
1611 | break; | |
1612 | } | |
1613 | } | |
1614 | mutex_unlock(&pci_pme_list_mutex); | |
1615 | } | |
1616 | } | |
1617 | ||
1618 | out: | |
85b8582d | 1619 | dev_dbg(&dev->dev, "PME# %s\n", enable ? "enabled" : "disabled"); |
eb9d0fe4 RW |
1620 | } |
1621 | ||
1da177e4 | 1622 | /** |
6cbf8214 | 1623 | * __pci_enable_wake - enable PCI device as wakeup event source |
075c1771 DB |
1624 | * @dev: PCI device affected |
1625 | * @state: PCI state from which device will issue wakeup events | |
6cbf8214 | 1626 | * @runtime: True if the events are to be generated at run time |
075c1771 DB |
1627 | * @enable: True to enable event generation; false to disable |
1628 | * | |
1629 | * This enables the device as a wakeup event source, or disables it. | |
1630 | * When such events involves platform-specific hooks, those hooks are | |
1631 | * called automatically by this routine. | |
1632 | * | |
1633 | * Devices with legacy power management (no standard PCI PM capabilities) | |
eb9d0fe4 | 1634 | * always require such platform hooks. |
075c1771 | 1635 | * |
eb9d0fe4 RW |
1636 | * RETURN VALUE: |
1637 | * 0 is returned on success | |
1638 | * -EINVAL is returned if device is not supposed to wake up the system | |
1639 | * Error code depending on the platform is returned if both the platform and | |
1640 | * the native mechanism fail to enable the generation of wake-up events | |
1da177e4 | 1641 | */ |
6cbf8214 RW |
1642 | int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, |
1643 | bool runtime, bool enable) | |
1da177e4 | 1644 | { |
5bcc2fb4 | 1645 | int ret = 0; |
075c1771 | 1646 | |
6cbf8214 | 1647 | if (enable && !runtime && !device_may_wakeup(&dev->dev)) |
eb9d0fe4 | 1648 | return -EINVAL; |
1da177e4 | 1649 | |
e80bb09d RW |
1650 | /* Don't do the same thing twice in a row for one device. */ |
1651 | if (!!enable == !!dev->wakeup_prepared) | |
1652 | return 0; | |
1653 | ||
eb9d0fe4 RW |
1654 | /* |
1655 | * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don | |
1656 | * Anderson we should be doing PME# wake enable followed by ACPI wake | |
1657 | * enable. To disable wake-up we call the platform first, for symmetry. | |
075c1771 | 1658 | */ |
1da177e4 | 1659 | |
5bcc2fb4 RW |
1660 | if (enable) { |
1661 | int error; | |
1da177e4 | 1662 | |
5bcc2fb4 RW |
1663 | if (pci_pme_capable(dev, state)) |
1664 | pci_pme_active(dev, true); | |
1665 | else | |
1666 | ret = 1; | |
6cbf8214 RW |
1667 | error = runtime ? platform_pci_run_wake(dev, true) : |
1668 | platform_pci_sleep_wake(dev, true); | |
5bcc2fb4 RW |
1669 | if (ret) |
1670 | ret = error; | |
e80bb09d RW |
1671 | if (!ret) |
1672 | dev->wakeup_prepared = true; | |
5bcc2fb4 | 1673 | } else { |
6cbf8214 RW |
1674 | if (runtime) |
1675 | platform_pci_run_wake(dev, false); | |
1676 | else | |
1677 | platform_pci_sleep_wake(dev, false); | |
5bcc2fb4 | 1678 | pci_pme_active(dev, false); |
e80bb09d | 1679 | dev->wakeup_prepared = false; |
5bcc2fb4 | 1680 | } |
1da177e4 | 1681 | |
5bcc2fb4 | 1682 | return ret; |
eb9d0fe4 | 1683 | } |
6cbf8214 | 1684 | EXPORT_SYMBOL(__pci_enable_wake); |
1da177e4 | 1685 | |
0235c4fc RW |
1686 | /** |
1687 | * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold | |
1688 | * @dev: PCI device to prepare | |
1689 | * @enable: True to enable wake-up event generation; false to disable | |
1690 | * | |
1691 | * Many drivers want the device to wake up the system from D3_hot or D3_cold | |
1692 | * and this function allows them to set that up cleanly - pci_enable_wake() | |
1693 | * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI | |
1694 | * ordering constraints. | |
1695 | * | |
1696 | * This function only returns error code if the device is not capable of | |
1697 | * generating PME# from both D3_hot and D3_cold, and the platform is unable to | |
1698 | * enable wake-up power for it. | |
1699 | */ | |
1700 | int pci_wake_from_d3(struct pci_dev *dev, bool enable) | |
1701 | { | |
1702 | return pci_pme_capable(dev, PCI_D3cold) ? | |
1703 | pci_enable_wake(dev, PCI_D3cold, enable) : | |
1704 | pci_enable_wake(dev, PCI_D3hot, enable); | |
1705 | } | |
1706 | ||
404cc2d8 | 1707 | /** |
37139074 JB |
1708 | * pci_target_state - find an appropriate low power state for a given PCI dev |
1709 | * @dev: PCI device | |
1710 | * | |
1711 | * Use underlying platform code to find a supported low power state for @dev. | |
1712 | * If the platform can't manage @dev, return the deepest state from which it | |
1713 | * can generate wake events, based on any available PME info. | |
404cc2d8 | 1714 | */ |
e5899e1b | 1715 | pci_power_t pci_target_state(struct pci_dev *dev) |
404cc2d8 RW |
1716 | { |
1717 | pci_power_t target_state = PCI_D3hot; | |
404cc2d8 RW |
1718 | |
1719 | if (platform_pci_power_manageable(dev)) { | |
1720 | /* | |
1721 | * Call the platform to choose the target state of the device | |
1722 | * and enable wake-up from this state if supported. | |
1723 | */ | |
1724 | pci_power_t state = platform_pci_choose_state(dev); | |
1725 | ||
1726 | switch (state) { | |
1727 | case PCI_POWER_ERROR: | |
1728 | case PCI_UNKNOWN: | |
1729 | break; | |
1730 | case PCI_D1: | |
1731 | case PCI_D2: | |
1732 | if (pci_no_d1d2(dev)) | |
1733 | break; | |
1734 | default: | |
1735 | target_state = state; | |
404cc2d8 | 1736 | } |
d2abdf62 RW |
1737 | } else if (!dev->pm_cap) { |
1738 | target_state = PCI_D0; | |
404cc2d8 RW |
1739 | } else if (device_may_wakeup(&dev->dev)) { |
1740 | /* | |
1741 | * Find the deepest state from which the device can generate | |
1742 | * wake-up events, make it the target state and enable device | |
1743 | * to generate PME#. | |
1744 | */ | |
337001b6 RW |
1745 | if (dev->pme_support) { |
1746 | while (target_state | |
1747 | && !(dev->pme_support & (1 << target_state))) | |
1748 | target_state--; | |
404cc2d8 RW |
1749 | } |
1750 | } | |
1751 | ||
e5899e1b RW |
1752 | return target_state; |
1753 | } | |
1754 | ||
1755 | /** | |
1756 | * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state | |
1757 | * @dev: Device to handle. | |
1758 | * | |
1759 | * Choose the power state appropriate for the device depending on whether | |
1760 | * it can wake up the system and/or is power manageable by the platform | |
1761 | * (PCI_D3hot is the default) and put the device into that state. | |
1762 | */ | |
1763 | int pci_prepare_to_sleep(struct pci_dev *dev) | |
1764 | { | |
1765 | pci_power_t target_state = pci_target_state(dev); | |
1766 | int error; | |
1767 | ||
1768 | if (target_state == PCI_POWER_ERROR) | |
1769 | return -EIO; | |
1770 | ||
448bd857 HY |
1771 | /* D3cold during system suspend/hibernate is not supported */ |
1772 | if (target_state > PCI_D3hot) | |
1773 | target_state = PCI_D3hot; | |
1774 | ||
8efb8c76 | 1775 | pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev)); |
c157dfa3 | 1776 | |
404cc2d8 RW |
1777 | error = pci_set_power_state(dev, target_state); |
1778 | ||
1779 | if (error) | |
1780 | pci_enable_wake(dev, target_state, false); | |
1781 | ||
1782 | return error; | |
1783 | } | |
1784 | ||
1785 | /** | |
443bd1c4 | 1786 | * pci_back_from_sleep - turn PCI device on during system-wide transition into working state |
404cc2d8 RW |
1787 | * @dev: Device to handle. |
1788 | * | |
88393161 | 1789 | * Disable device's system wake-up capability and put it into D0. |
404cc2d8 RW |
1790 | */ |
1791 | int pci_back_from_sleep(struct pci_dev *dev) | |
1792 | { | |
1793 | pci_enable_wake(dev, PCI_D0, false); | |
1794 | return pci_set_power_state(dev, PCI_D0); | |
1795 | } | |
1796 | ||
6cbf8214 RW |
1797 | /** |
1798 | * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend. | |
1799 | * @dev: PCI device being suspended. | |
1800 | * | |
1801 | * Prepare @dev to generate wake-up events at run time and put it into a low | |
1802 | * power state. | |
1803 | */ | |
1804 | int pci_finish_runtime_suspend(struct pci_dev *dev) | |
1805 | { | |
1806 | pci_power_t target_state = pci_target_state(dev); | |
1807 | int error; | |
1808 | ||
1809 | if (target_state == PCI_POWER_ERROR) | |
1810 | return -EIO; | |
1811 | ||
448bd857 HY |
1812 | dev->runtime_d3cold = target_state == PCI_D3cold; |
1813 | ||
6cbf8214 RW |
1814 | __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev)); |
1815 | ||
1816 | error = pci_set_power_state(dev, target_state); | |
1817 | ||
448bd857 | 1818 | if (error) { |
6cbf8214 | 1819 | __pci_enable_wake(dev, target_state, true, false); |
448bd857 HY |
1820 | dev->runtime_d3cold = false; |
1821 | } | |
6cbf8214 RW |
1822 | |
1823 | return error; | |
1824 | } | |
1825 | ||
b67ea761 RW |
1826 | /** |
1827 | * pci_dev_run_wake - Check if device can generate run-time wake-up events. | |
1828 | * @dev: Device to check. | |
1829 | * | |
1830 | * Return true if the device itself is cabable of generating wake-up events | |
1831 | * (through the platform or using the native PCIe PME) or if the device supports | |
1832 | * PME and one of its upstream bridges can generate wake-up events. | |
1833 | */ | |
1834 | bool pci_dev_run_wake(struct pci_dev *dev) | |
1835 | { | |
1836 | struct pci_bus *bus = dev->bus; | |
1837 | ||
1838 | if (device_run_wake(&dev->dev)) | |
1839 | return true; | |
1840 | ||
1841 | if (!dev->pme_support) | |
1842 | return false; | |
1843 | ||
1844 | while (bus->parent) { | |
1845 | struct pci_dev *bridge = bus->self; | |
1846 | ||
1847 | if (device_run_wake(&bridge->dev)) | |
1848 | return true; | |
1849 | ||
1850 | bus = bus->parent; | |
1851 | } | |
1852 | ||
1853 | /* We have reached the root bus. */ | |
1854 | if (bus->bridge) | |
1855 | return device_run_wake(bus->bridge); | |
1856 | ||
1857 | return false; | |
1858 | } | |
1859 | EXPORT_SYMBOL_GPL(pci_dev_run_wake); | |
1860 | ||
b3c32c4f HY |
1861 | void pci_config_pm_runtime_get(struct pci_dev *pdev) |
1862 | { | |
1863 | struct device *dev = &pdev->dev; | |
1864 | struct device *parent = dev->parent; | |
1865 | ||
1866 | if (parent) | |
1867 | pm_runtime_get_sync(parent); | |
1868 | pm_runtime_get_noresume(dev); | |
1869 | /* | |
1870 | * pdev->current_state is set to PCI_D3cold during suspending, | |
1871 | * so wait until suspending completes | |
1872 | */ | |
1873 | pm_runtime_barrier(dev); | |
1874 | /* | |
1875 | * Only need to resume devices in D3cold, because config | |
1876 | * registers are still accessible for devices suspended but | |
1877 | * not in D3cold. | |
1878 | */ | |
1879 | if (pdev->current_state == PCI_D3cold) | |
1880 | pm_runtime_resume(dev); | |
1881 | } | |
1882 | ||
1883 | void pci_config_pm_runtime_put(struct pci_dev *pdev) | |
1884 | { | |
1885 | struct device *dev = &pdev->dev; | |
1886 | struct device *parent = dev->parent; | |
1887 | ||
1888 | pm_runtime_put(dev); | |
1889 | if (parent) | |
1890 | pm_runtime_put_sync(parent); | |
1891 | } | |
1892 | ||
eb9d0fe4 RW |
1893 | /** |
1894 | * pci_pm_init - Initialize PM functions of given PCI device | |
1895 | * @dev: PCI device to handle. | |
1896 | */ | |
1897 | void pci_pm_init(struct pci_dev *dev) | |
1898 | { | |
1899 | int pm; | |
1900 | u16 pmc; | |
1da177e4 | 1901 | |
bb910a70 | 1902 | pm_runtime_forbid(&dev->dev); |
a1e4d72c | 1903 | device_enable_async_suspend(&dev->dev); |
e80bb09d | 1904 | dev->wakeup_prepared = false; |
bb910a70 | 1905 | |
337001b6 RW |
1906 | dev->pm_cap = 0; |
1907 | ||
eb9d0fe4 RW |
1908 | /* find PCI PM capability in list */ |
1909 | pm = pci_find_capability(dev, PCI_CAP_ID_PM); | |
1910 | if (!pm) | |
50246dd4 | 1911 | return; |
eb9d0fe4 RW |
1912 | /* Check device's ability to generate PME# */ |
1913 | pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc); | |
075c1771 | 1914 | |
eb9d0fe4 RW |
1915 | if ((pmc & PCI_PM_CAP_VER_MASK) > 3) { |
1916 | dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n", | |
1917 | pmc & PCI_PM_CAP_VER_MASK); | |
50246dd4 | 1918 | return; |
eb9d0fe4 RW |
1919 | } |
1920 | ||
337001b6 | 1921 | dev->pm_cap = pm; |
1ae861e6 | 1922 | dev->d3_delay = PCI_PM_D3_WAIT; |
448bd857 | 1923 | dev->d3cold_delay = PCI_PM_D3COLD_WAIT; |
4f9c1397 | 1924 | dev->d3cold_allowed = true; |
337001b6 RW |
1925 | |
1926 | dev->d1_support = false; | |
1927 | dev->d2_support = false; | |
1928 | if (!pci_no_d1d2(dev)) { | |
c9ed77ee | 1929 | if (pmc & PCI_PM_CAP_D1) |
337001b6 | 1930 | dev->d1_support = true; |
c9ed77ee | 1931 | if (pmc & PCI_PM_CAP_D2) |
337001b6 | 1932 | dev->d2_support = true; |
c9ed77ee BH |
1933 | |
1934 | if (dev->d1_support || dev->d2_support) | |
1935 | dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n", | |
ec84f126 JB |
1936 | dev->d1_support ? " D1" : "", |
1937 | dev->d2_support ? " D2" : ""); | |
337001b6 RW |
1938 | } |
1939 | ||
1940 | pmc &= PCI_PM_CAP_PME_MASK; | |
1941 | if (pmc) { | |
10c3d71d BH |
1942 | dev_printk(KERN_DEBUG, &dev->dev, |
1943 | "PME# supported from%s%s%s%s%s\n", | |
c9ed77ee BH |
1944 | (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "", |
1945 | (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "", | |
1946 | (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "", | |
1947 | (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "", | |
1948 | (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : ""); | |
337001b6 | 1949 | dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT; |
379021d5 | 1950 | dev->pme_poll = true; |
eb9d0fe4 RW |
1951 | /* |
1952 | * Make device's PM flags reflect the wake-up capability, but | |
1953 | * let the user space enable it to wake up the system as needed. | |
1954 | */ | |
1955 | device_set_wakeup_capable(&dev->dev, true); | |
eb9d0fe4 | 1956 | /* Disable the PME# generation functionality */ |
337001b6 RW |
1957 | pci_pme_active(dev, false); |
1958 | } else { | |
1959 | dev->pme_support = 0; | |
eb9d0fe4 | 1960 | } |
1da177e4 LT |
1961 | } |
1962 | ||
eb9c39d0 JB |
1963 | /** |
1964 | * platform_pci_wakeup_init - init platform wakeup if present | |
1965 | * @dev: PCI device | |
1966 | * | |
1967 | * Some devices don't have PCI PM caps but can still generate wakeup | |
1968 | * events through platform methods (like ACPI events). If @dev supports | |
1969 | * platform wakeup events, set the device flag to indicate as much. This | |
1970 | * may be redundant if the device also supports PCI PM caps, but double | |
1971 | * initialization should be safe in that case. | |
1972 | */ | |
1973 | void platform_pci_wakeup_init(struct pci_dev *dev) | |
1974 | { | |
1975 | if (!platform_pci_can_wakeup(dev)) | |
1976 | return; | |
1977 | ||
1978 | device_set_wakeup_capable(&dev->dev, true); | |
eb9c39d0 JB |
1979 | platform_pci_sleep_wake(dev, false); |
1980 | } | |
1981 | ||
34a4876e YL |
1982 | static void pci_add_saved_cap(struct pci_dev *pci_dev, |
1983 | struct pci_cap_saved_state *new_cap) | |
1984 | { | |
1985 | hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space); | |
1986 | } | |
1987 | ||
63f4898a RW |
1988 | /** |
1989 | * pci_add_save_buffer - allocate buffer for saving given capability registers | |
1990 | * @dev: the PCI device | |
1991 | * @cap: the capability to allocate the buffer for | |
1992 | * @size: requested size of the buffer | |
1993 | */ | |
1994 | static int pci_add_cap_save_buffer( | |
1995 | struct pci_dev *dev, char cap, unsigned int size) | |
1996 | { | |
1997 | int pos; | |
1998 | struct pci_cap_saved_state *save_state; | |
1999 | ||
2000 | pos = pci_find_capability(dev, cap); | |
2001 | if (pos <= 0) | |
2002 | return 0; | |
2003 | ||
2004 | save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL); | |
2005 | if (!save_state) | |
2006 | return -ENOMEM; | |
2007 | ||
24a4742f AW |
2008 | save_state->cap.cap_nr = cap; |
2009 | save_state->cap.size = size; | |
63f4898a RW |
2010 | pci_add_saved_cap(dev, save_state); |
2011 | ||
2012 | return 0; | |
2013 | } | |
2014 | ||
2015 | /** | |
2016 | * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities | |
2017 | * @dev: the PCI device | |
2018 | */ | |
2019 | void pci_allocate_cap_save_buffers(struct pci_dev *dev) | |
2020 | { | |
2021 | int error; | |
2022 | ||
89858517 YZ |
2023 | error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP, |
2024 | PCI_EXP_SAVE_REGS * sizeof(u16)); | |
63f4898a RW |
2025 | if (error) |
2026 | dev_err(&dev->dev, | |
2027 | "unable to preallocate PCI Express save buffer\n"); | |
2028 | ||
2029 | error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16)); | |
2030 | if (error) | |
2031 | dev_err(&dev->dev, | |
2032 | "unable to preallocate PCI-X save buffer\n"); | |
2033 | } | |
2034 | ||
f796841e YL |
2035 | void pci_free_cap_save_buffers(struct pci_dev *dev) |
2036 | { | |
2037 | struct pci_cap_saved_state *tmp; | |
2038 | struct hlist_node *pos, *n; | |
2039 | ||
2040 | hlist_for_each_entry_safe(tmp, pos, n, &dev->saved_cap_space, next) | |
2041 | kfree(tmp); | |
2042 | } | |
2043 | ||
58c3a727 YZ |
2044 | /** |
2045 | * pci_enable_ari - enable ARI forwarding if hardware support it | |
2046 | * @dev: the PCI device | |
2047 | */ | |
2048 | void pci_enable_ari(struct pci_dev *dev) | |
2049 | { | |
58c3a727 | 2050 | u32 cap; |
8113587c | 2051 | struct pci_dev *bridge; |
58c3a727 | 2052 | |
6748dcc2 | 2053 | if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn) |
58c3a727 YZ |
2054 | return; |
2055 | ||
59875ae4 | 2056 | if (!pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) |
58c3a727 YZ |
2057 | return; |
2058 | ||
8113587c | 2059 | bridge = dev->bus->self; |
cb97ae34 | 2060 | if (!bridge) |
8113587c ZY |
2061 | return; |
2062 | ||
59875ae4 | 2063 | pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap); |
58c3a727 YZ |
2064 | if (!(cap & PCI_EXP_DEVCAP2_ARI)) |
2065 | return; | |
2066 | ||
59875ae4 | 2067 | pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_ARI); |
8113587c | 2068 | bridge->ari_enabled = 1; |
58c3a727 YZ |
2069 | } |
2070 | ||
b48d4425 | 2071 | /** |
c463b8cb | 2072 | * pci_enable_ido - enable ID-based Ordering on a device |
b48d4425 JB |
2073 | * @dev: the PCI device |
2074 | * @type: which types of IDO to enable | |
2075 | * | |
2076 | * Enable ID-based ordering on @dev. @type can contain the bits | |
2077 | * %PCI_EXP_IDO_REQUEST and/or %PCI_EXP_IDO_COMPLETION to indicate | |
2078 | * which types of transactions are allowed to be re-ordered. | |
2079 | */ | |
2080 | void pci_enable_ido(struct pci_dev *dev, unsigned long type) | |
2081 | { | |
59875ae4 | 2082 | u16 ctrl = 0; |
b48d4425 | 2083 | |
b48d4425 JB |
2084 | if (type & PCI_EXP_IDO_REQUEST) |
2085 | ctrl |= PCI_EXP_IDO_REQ_EN; | |
2086 | if (type & PCI_EXP_IDO_COMPLETION) | |
2087 | ctrl |= PCI_EXP_IDO_CMP_EN; | |
59875ae4 JL |
2088 | if (ctrl) |
2089 | pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, ctrl); | |
b48d4425 JB |
2090 | } |
2091 | EXPORT_SYMBOL(pci_enable_ido); | |
2092 | ||
2093 | /** | |
2094 | * pci_disable_ido - disable ID-based ordering on a device | |
2095 | * @dev: the PCI device | |
2096 | * @type: which types of IDO to disable | |
2097 | */ | |
2098 | void pci_disable_ido(struct pci_dev *dev, unsigned long type) | |
2099 | { | |
59875ae4 | 2100 | u16 ctrl = 0; |
b48d4425 | 2101 | |
b48d4425 | 2102 | if (type & PCI_EXP_IDO_REQUEST) |
59875ae4 | 2103 | ctrl |= PCI_EXP_IDO_REQ_EN; |
b48d4425 | 2104 | if (type & PCI_EXP_IDO_COMPLETION) |
59875ae4 JL |
2105 | ctrl |= PCI_EXP_IDO_CMP_EN; |
2106 | if (ctrl) | |
2107 | pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, ctrl); | |
b48d4425 JB |
2108 | } |
2109 | EXPORT_SYMBOL(pci_disable_ido); | |
2110 | ||
48a92a81 JB |
2111 | /** |
2112 | * pci_enable_obff - enable optimized buffer flush/fill | |
2113 | * @dev: PCI device | |
2114 | * @type: type of signaling to use | |
2115 | * | |
2116 | * Try to enable @type OBFF signaling on @dev. It will try using WAKE# | |
2117 | * signaling if possible, falling back to message signaling only if | |
2118 | * WAKE# isn't supported. @type should indicate whether the PCIe link | |
2119 | * be brought out of L0s or L1 to send the message. It should be either | |
2120 | * %PCI_EXP_OBFF_SIGNAL_ALWAYS or %PCI_OBFF_SIGNAL_L0. | |
2121 | * | |
2122 | * If your device can benefit from receiving all messages, even at the | |
2123 | * power cost of bringing the link back up from a low power state, use | |
2124 | * %PCI_EXP_OBFF_SIGNAL_ALWAYS. Otherwise, use %PCI_OBFF_SIGNAL_L0 (the | |
2125 | * preferred type). | |
2126 | * | |
2127 | * RETURNS: | |
2128 | * Zero on success, appropriate error number on failure. | |
2129 | */ | |
2130 | int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type) | |
2131 | { | |
48a92a81 JB |
2132 | u32 cap; |
2133 | u16 ctrl; | |
2134 | int ret; | |
2135 | ||
59875ae4 | 2136 | pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); |
48a92a81 JB |
2137 | if (!(cap & PCI_EXP_OBFF_MASK)) |
2138 | return -ENOTSUPP; /* no OBFF support at all */ | |
2139 | ||
2140 | /* Make sure the topology supports OBFF as well */ | |
8291550f | 2141 | if (dev->bus->self) { |
48a92a81 JB |
2142 | ret = pci_enable_obff(dev->bus->self, type); |
2143 | if (ret) | |
2144 | return ret; | |
2145 | } | |
2146 | ||
59875ae4 | 2147 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &ctrl); |
48a92a81 JB |
2148 | if (cap & PCI_EXP_OBFF_WAKE) |
2149 | ctrl |= PCI_EXP_OBFF_WAKE_EN; | |
2150 | else { | |
2151 | switch (type) { | |
2152 | case PCI_EXP_OBFF_SIGNAL_L0: | |
2153 | if (!(ctrl & PCI_EXP_OBFF_WAKE_EN)) | |
2154 | ctrl |= PCI_EXP_OBFF_MSGA_EN; | |
2155 | break; | |
2156 | case PCI_EXP_OBFF_SIGNAL_ALWAYS: | |
2157 | ctrl &= ~PCI_EXP_OBFF_WAKE_EN; | |
2158 | ctrl |= PCI_EXP_OBFF_MSGB_EN; | |
2159 | break; | |
2160 | default: | |
2161 | WARN(1, "bad OBFF signal type\n"); | |
2162 | return -ENOTSUPP; | |
2163 | } | |
2164 | } | |
59875ae4 | 2165 | pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, ctrl); |
48a92a81 JB |
2166 | |
2167 | return 0; | |
2168 | } | |
2169 | EXPORT_SYMBOL(pci_enable_obff); | |
2170 | ||
2171 | /** | |
2172 | * pci_disable_obff - disable optimized buffer flush/fill | |
2173 | * @dev: PCI device | |
2174 | * | |
2175 | * Disable OBFF on @dev. | |
2176 | */ | |
2177 | void pci_disable_obff(struct pci_dev *dev) | |
2178 | { | |
59875ae4 | 2179 | pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, PCI_EXP_OBFF_WAKE_EN); |
48a92a81 JB |
2180 | } |
2181 | EXPORT_SYMBOL(pci_disable_obff); | |
2182 | ||
51c2e0a7 JB |
2183 | /** |
2184 | * pci_ltr_supported - check whether a device supports LTR | |
2185 | * @dev: PCI device | |
2186 | * | |
2187 | * RETURNS: | |
2188 | * True if @dev supports latency tolerance reporting, false otherwise. | |
2189 | */ | |
c32823f8 | 2190 | static bool pci_ltr_supported(struct pci_dev *dev) |
51c2e0a7 | 2191 | { |
51c2e0a7 JB |
2192 | u32 cap; |
2193 | ||
59875ae4 | 2194 | pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); |
51c2e0a7 JB |
2195 | |
2196 | return cap & PCI_EXP_DEVCAP2_LTR; | |
2197 | } | |
51c2e0a7 JB |
2198 | |
2199 | /** | |
2200 | * pci_enable_ltr - enable latency tolerance reporting | |
2201 | * @dev: PCI device | |
2202 | * | |
2203 | * Enable LTR on @dev if possible, which means enabling it first on | |
2204 | * upstream ports. | |
2205 | * | |
2206 | * RETURNS: | |
2207 | * Zero on success, errno on failure. | |
2208 | */ | |
2209 | int pci_enable_ltr(struct pci_dev *dev) | |
2210 | { | |
51c2e0a7 JB |
2211 | int ret; |
2212 | ||
51c2e0a7 JB |
2213 | /* Only primary function can enable/disable LTR */ |
2214 | if (PCI_FUNC(dev->devfn) != 0) | |
2215 | return -EINVAL; | |
2216 | ||
59875ae4 JL |
2217 | if (!pci_ltr_supported(dev)) |
2218 | return -ENOTSUPP; | |
2219 | ||
51c2e0a7 | 2220 | /* Enable upstream ports first */ |
8291550f | 2221 | if (dev->bus->self) { |
51c2e0a7 JB |
2222 | ret = pci_enable_ltr(dev->bus->self); |
2223 | if (ret) | |
2224 | return ret; | |
2225 | } | |
2226 | ||
59875ae4 | 2227 | return pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, PCI_EXP_LTR_EN); |
51c2e0a7 JB |
2228 | } |
2229 | EXPORT_SYMBOL(pci_enable_ltr); | |
2230 | ||
2231 | /** | |
2232 | * pci_disable_ltr - disable latency tolerance reporting | |
2233 | * @dev: PCI device | |
2234 | */ | |
2235 | void pci_disable_ltr(struct pci_dev *dev) | |
2236 | { | |
51c2e0a7 JB |
2237 | /* Only primary function can enable/disable LTR */ |
2238 | if (PCI_FUNC(dev->devfn) != 0) | |
2239 | return; | |
2240 | ||
59875ae4 JL |
2241 | if (!pci_ltr_supported(dev)) |
2242 | return; | |
2243 | ||
2244 | pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, PCI_EXP_LTR_EN); | |
51c2e0a7 JB |
2245 | } |
2246 | EXPORT_SYMBOL(pci_disable_ltr); | |
2247 | ||
2248 | static int __pci_ltr_scale(int *val) | |
2249 | { | |
2250 | int scale = 0; | |
2251 | ||
2252 | while (*val > 1023) { | |
2253 | *val = (*val + 31) / 32; | |
2254 | scale++; | |
2255 | } | |
2256 | return scale; | |
2257 | } | |
2258 | ||
2259 | /** | |
2260 | * pci_set_ltr - set LTR latency values | |
2261 | * @dev: PCI device | |
2262 | * @snoop_lat_ns: snoop latency in nanoseconds | |
2263 | * @nosnoop_lat_ns: nosnoop latency in nanoseconds | |
2264 | * | |
2265 | * Figure out the scale and set the LTR values accordingly. | |
2266 | */ | |
2267 | int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns) | |
2268 | { | |
2269 | int pos, ret, snoop_scale, nosnoop_scale; | |
2270 | u16 val; | |
2271 | ||
2272 | if (!pci_ltr_supported(dev)) | |
2273 | return -ENOTSUPP; | |
2274 | ||
2275 | snoop_scale = __pci_ltr_scale(&snoop_lat_ns); | |
2276 | nosnoop_scale = __pci_ltr_scale(&nosnoop_lat_ns); | |
2277 | ||
2278 | if (snoop_lat_ns > PCI_LTR_VALUE_MASK || | |
2279 | nosnoop_lat_ns > PCI_LTR_VALUE_MASK) | |
2280 | return -EINVAL; | |
2281 | ||
2282 | if ((snoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)) || | |
2283 | (nosnoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT))) | |
2284 | return -EINVAL; | |
2285 | ||
2286 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR); | |
2287 | if (!pos) | |
2288 | return -ENOTSUPP; | |
2289 | ||
2290 | val = (snoop_scale << PCI_LTR_SCALE_SHIFT) | snoop_lat_ns; | |
2291 | ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_SNOOP_LAT, val); | |
2292 | if (ret != 4) | |
2293 | return -EIO; | |
2294 | ||
2295 | val = (nosnoop_scale << PCI_LTR_SCALE_SHIFT) | nosnoop_lat_ns; | |
2296 | ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_NOSNOOP_LAT, val); | |
2297 | if (ret != 4) | |
2298 | return -EIO; | |
2299 | ||
2300 | return 0; | |
2301 | } | |
2302 | EXPORT_SYMBOL(pci_set_ltr); | |
2303 | ||
5d990b62 CW |
2304 | static int pci_acs_enable; |
2305 | ||
2306 | /** | |
2307 | * pci_request_acs - ask for ACS to be enabled if supported | |
2308 | */ | |
2309 | void pci_request_acs(void) | |
2310 | { | |
2311 | pci_acs_enable = 1; | |
2312 | } | |
2313 | ||
ae21ee65 AK |
2314 | /** |
2315 | * pci_enable_acs - enable ACS if hardware support it | |
2316 | * @dev: the PCI device | |
2317 | */ | |
2318 | void pci_enable_acs(struct pci_dev *dev) | |
2319 | { | |
2320 | int pos; | |
2321 | u16 cap; | |
2322 | u16 ctrl; | |
2323 | ||
5d990b62 CW |
2324 | if (!pci_acs_enable) |
2325 | return; | |
2326 | ||
ae21ee65 AK |
2327 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); |
2328 | if (!pos) | |
2329 | return; | |
2330 | ||
2331 | pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap); | |
2332 | pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl); | |
2333 | ||
2334 | /* Source Validation */ | |
2335 | ctrl |= (cap & PCI_ACS_SV); | |
2336 | ||
2337 | /* P2P Request Redirect */ | |
2338 | ctrl |= (cap & PCI_ACS_RR); | |
2339 | ||
2340 | /* P2P Completion Redirect */ | |
2341 | ctrl |= (cap & PCI_ACS_CR); | |
2342 | ||
2343 | /* Upstream Forwarding */ | |
2344 | ctrl |= (cap & PCI_ACS_UF); | |
2345 | ||
2346 | pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl); | |
2347 | } | |
2348 | ||
ad805758 AW |
2349 | /** |
2350 | * pci_acs_enabled - test ACS against required flags for a given device | |
2351 | * @pdev: device to test | |
2352 | * @acs_flags: required PCI ACS flags | |
2353 | * | |
2354 | * Return true if the device supports the provided flags. Automatically | |
2355 | * filters out flags that are not implemented on multifunction devices. | |
2356 | */ | |
2357 | bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags) | |
2358 | { | |
2359 | int pos, ret; | |
2360 | u16 ctrl; | |
2361 | ||
2362 | ret = pci_dev_specific_acs_enabled(pdev, acs_flags); | |
2363 | if (ret >= 0) | |
2364 | return ret > 0; | |
2365 | ||
2366 | if (!pci_is_pcie(pdev)) | |
2367 | return false; | |
2368 | ||
2369 | /* Filter out flags not applicable to multifunction */ | |
2370 | if (pdev->multifunction) | |
2371 | acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | | |
2372 | PCI_ACS_EC | PCI_ACS_DT); | |
2373 | ||
62f87c0e YW |
2374 | if (pci_pcie_type(pdev) == PCI_EXP_TYPE_DOWNSTREAM || |
2375 | pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT || | |
ad805758 AW |
2376 | pdev->multifunction) { |
2377 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS); | |
2378 | if (!pos) | |
2379 | return false; | |
2380 | ||
2381 | pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl); | |
2382 | if ((ctrl & acs_flags) != acs_flags) | |
2383 | return false; | |
2384 | } | |
2385 | ||
2386 | return true; | |
2387 | } | |
2388 | ||
2389 | /** | |
2390 | * pci_acs_path_enable - test ACS flags from start to end in a hierarchy | |
2391 | * @start: starting downstream device | |
2392 | * @end: ending upstream device or NULL to search to the root bus | |
2393 | * @acs_flags: required flags | |
2394 | * | |
2395 | * Walk up a device tree from start to end testing PCI ACS support. If | |
2396 | * any step along the way does not support the required flags, return false. | |
2397 | */ | |
2398 | bool pci_acs_path_enabled(struct pci_dev *start, | |
2399 | struct pci_dev *end, u16 acs_flags) | |
2400 | { | |
2401 | struct pci_dev *pdev, *parent = start; | |
2402 | ||
2403 | do { | |
2404 | pdev = parent; | |
2405 | ||
2406 | if (!pci_acs_enabled(pdev, acs_flags)) | |
2407 | return false; | |
2408 | ||
2409 | if (pci_is_root_bus(pdev->bus)) | |
2410 | return (end == NULL); | |
2411 | ||
2412 | parent = pdev->bus->self; | |
2413 | } while (pdev != end); | |
2414 | ||
2415 | return true; | |
2416 | } | |
2417 | ||
57c2cf71 BH |
2418 | /** |
2419 | * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge | |
2420 | * @dev: the PCI device | |
2421 | * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD) | |
2422 | * | |
2423 | * Perform INTx swizzling for a device behind one level of bridge. This is | |
2424 | * required by section 9.1 of the PCI-to-PCI bridge specification for devices | |
46b952a3 MW |
2425 | * behind bridges on add-in cards. For devices with ARI enabled, the slot |
2426 | * number is always 0 (see the Implementation Note in section 2.2.8.1 of | |
2427 | * the PCI Express Base Specification, Revision 2.1) | |
57c2cf71 | 2428 | */ |
3df425f3 | 2429 | u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin) |
57c2cf71 | 2430 | { |
46b952a3 MW |
2431 | int slot; |
2432 | ||
2433 | if (pci_ari_enabled(dev->bus)) | |
2434 | slot = 0; | |
2435 | else | |
2436 | slot = PCI_SLOT(dev->devfn); | |
2437 | ||
2438 | return (((pin - 1) + slot) % 4) + 1; | |
57c2cf71 BH |
2439 | } |
2440 | ||
1da177e4 LT |
2441 | int |
2442 | pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge) | |
2443 | { | |
2444 | u8 pin; | |
2445 | ||
514d207d | 2446 | pin = dev->pin; |
1da177e4 LT |
2447 | if (!pin) |
2448 | return -1; | |
878f2e50 | 2449 | |
8784fd4d | 2450 | while (!pci_is_root_bus(dev->bus)) { |
57c2cf71 | 2451 | pin = pci_swizzle_interrupt_pin(dev, pin); |
1da177e4 LT |
2452 | dev = dev->bus->self; |
2453 | } | |
2454 | *bridge = dev; | |
2455 | return pin; | |
2456 | } | |
2457 | ||
68feac87 BH |
2458 | /** |
2459 | * pci_common_swizzle - swizzle INTx all the way to root bridge | |
2460 | * @dev: the PCI device | |
2461 | * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD) | |
2462 | * | |
2463 | * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI | |
2464 | * bridges all the way up to a PCI root bus. | |
2465 | */ | |
2466 | u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp) | |
2467 | { | |
2468 | u8 pin = *pinp; | |
2469 | ||
1eb39487 | 2470 | while (!pci_is_root_bus(dev->bus)) { |
68feac87 BH |
2471 | pin = pci_swizzle_interrupt_pin(dev, pin); |
2472 | dev = dev->bus->self; | |
2473 | } | |
2474 | *pinp = pin; | |
2475 | return PCI_SLOT(dev->devfn); | |
2476 | } | |
2477 | ||
1da177e4 LT |
2478 | /** |
2479 | * pci_release_region - Release a PCI bar | |
2480 | * @pdev: PCI device whose resources were previously reserved by pci_request_region | |
2481 | * @bar: BAR to release | |
2482 | * | |
2483 | * Releases the PCI I/O and memory resources previously reserved by a | |
2484 | * successful call to pci_request_region. Call this function only | |
2485 | * after all use of the PCI regions has ceased. | |
2486 | */ | |
2487 | void pci_release_region(struct pci_dev *pdev, int bar) | |
2488 | { | |
9ac7849e TH |
2489 | struct pci_devres *dr; |
2490 | ||
1da177e4 LT |
2491 | if (pci_resource_len(pdev, bar) == 0) |
2492 | return; | |
2493 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) | |
2494 | release_region(pci_resource_start(pdev, bar), | |
2495 | pci_resource_len(pdev, bar)); | |
2496 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) | |
2497 | release_mem_region(pci_resource_start(pdev, bar), | |
2498 | pci_resource_len(pdev, bar)); | |
9ac7849e TH |
2499 | |
2500 | dr = find_pci_dr(pdev); | |
2501 | if (dr) | |
2502 | dr->region_mask &= ~(1 << bar); | |
1da177e4 LT |
2503 | } |
2504 | ||
2505 | /** | |
f5ddcac4 | 2506 | * __pci_request_region - Reserved PCI I/O and memory resource |
1da177e4 LT |
2507 | * @pdev: PCI device whose resources are to be reserved |
2508 | * @bar: BAR to be reserved | |
2509 | * @res_name: Name to be associated with resource. | |
f5ddcac4 | 2510 | * @exclusive: whether the region access is exclusive or not |
1da177e4 LT |
2511 | * |
2512 | * Mark the PCI region associated with PCI device @pdev BR @bar as | |
2513 | * being reserved by owner @res_name. Do not access any | |
2514 | * address inside the PCI regions unless this call returns | |
2515 | * successfully. | |
2516 | * | |
f5ddcac4 RD |
2517 | * If @exclusive is set, then the region is marked so that userspace |
2518 | * is explicitly not allowed to map the resource via /dev/mem or | |
2519 | * sysfs MMIO access. | |
2520 | * | |
1da177e4 LT |
2521 | * Returns 0 on success, or %EBUSY on error. A warning |
2522 | * message is also printed on failure. | |
2523 | */ | |
e8de1481 AV |
2524 | static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name, |
2525 | int exclusive) | |
1da177e4 | 2526 | { |
9ac7849e TH |
2527 | struct pci_devres *dr; |
2528 | ||
1da177e4 LT |
2529 | if (pci_resource_len(pdev, bar) == 0) |
2530 | return 0; | |
2531 | ||
2532 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) { | |
2533 | if (!request_region(pci_resource_start(pdev, bar), | |
2534 | pci_resource_len(pdev, bar), res_name)) | |
2535 | goto err_out; | |
2536 | } | |
2537 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { | |
e8de1481 AV |
2538 | if (!__request_mem_region(pci_resource_start(pdev, bar), |
2539 | pci_resource_len(pdev, bar), res_name, | |
2540 | exclusive)) | |
1da177e4 LT |
2541 | goto err_out; |
2542 | } | |
9ac7849e TH |
2543 | |
2544 | dr = find_pci_dr(pdev); | |
2545 | if (dr) | |
2546 | dr->region_mask |= 1 << bar; | |
2547 | ||
1da177e4 LT |
2548 | return 0; |
2549 | ||
2550 | err_out: | |
c7dabef8 | 2551 | dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar, |
096e6f67 | 2552 | &pdev->resource[bar]); |
1da177e4 LT |
2553 | return -EBUSY; |
2554 | } | |
2555 | ||
e8de1481 | 2556 | /** |
f5ddcac4 | 2557 | * pci_request_region - Reserve PCI I/O and memory resource |
e8de1481 AV |
2558 | * @pdev: PCI device whose resources are to be reserved |
2559 | * @bar: BAR to be reserved | |
f5ddcac4 | 2560 | * @res_name: Name to be associated with resource |
e8de1481 | 2561 | * |
f5ddcac4 | 2562 | * Mark the PCI region associated with PCI device @pdev BAR @bar as |
e8de1481 AV |
2563 | * being reserved by owner @res_name. Do not access any |
2564 | * address inside the PCI regions unless this call returns | |
2565 | * successfully. | |
2566 | * | |
2567 | * Returns 0 on success, or %EBUSY on error. A warning | |
2568 | * message is also printed on failure. | |
2569 | */ | |
2570 | int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) | |
2571 | { | |
2572 | return __pci_request_region(pdev, bar, res_name, 0); | |
2573 | } | |
2574 | ||
2575 | /** | |
2576 | * pci_request_region_exclusive - Reserved PCI I/O and memory resource | |
2577 | * @pdev: PCI device whose resources are to be reserved | |
2578 | * @bar: BAR to be reserved | |
2579 | * @res_name: Name to be associated with resource. | |
2580 | * | |
2581 | * Mark the PCI region associated with PCI device @pdev BR @bar as | |
2582 | * being reserved by owner @res_name. Do not access any | |
2583 | * address inside the PCI regions unless this call returns | |
2584 | * successfully. | |
2585 | * | |
2586 | * Returns 0 on success, or %EBUSY on error. A warning | |
2587 | * message is also printed on failure. | |
2588 | * | |
2589 | * The key difference that _exclusive makes it that userspace is | |
2590 | * explicitly not allowed to map the resource via /dev/mem or | |
2591 | * sysfs. | |
2592 | */ | |
2593 | int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name) | |
2594 | { | |
2595 | return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE); | |
2596 | } | |
c87deff7 HS |
2597 | /** |
2598 | * pci_release_selected_regions - Release selected PCI I/O and memory resources | |
2599 | * @pdev: PCI device whose resources were previously reserved | |
2600 | * @bars: Bitmask of BARs to be released | |
2601 | * | |
2602 | * Release selected PCI I/O and memory resources previously reserved. | |
2603 | * Call this function only after all use of the PCI regions has ceased. | |
2604 | */ | |
2605 | void pci_release_selected_regions(struct pci_dev *pdev, int bars) | |
2606 | { | |
2607 | int i; | |
2608 | ||
2609 | for (i = 0; i < 6; i++) | |
2610 | if (bars & (1 << i)) | |
2611 | pci_release_region(pdev, i); | |
2612 | } | |
2613 | ||
e8de1481 AV |
2614 | int __pci_request_selected_regions(struct pci_dev *pdev, int bars, |
2615 | const char *res_name, int excl) | |
c87deff7 HS |
2616 | { |
2617 | int i; | |
2618 | ||
2619 | for (i = 0; i < 6; i++) | |
2620 | if (bars & (1 << i)) | |
e8de1481 | 2621 | if (__pci_request_region(pdev, i, res_name, excl)) |
c87deff7 HS |
2622 | goto err_out; |
2623 | return 0; | |
2624 | ||
2625 | err_out: | |
2626 | while(--i >= 0) | |
2627 | if (bars & (1 << i)) | |
2628 | pci_release_region(pdev, i); | |
2629 | ||
2630 | return -EBUSY; | |
2631 | } | |
1da177e4 | 2632 | |
e8de1481 AV |
2633 | |
2634 | /** | |
2635 | * pci_request_selected_regions - Reserve selected PCI I/O and memory resources | |
2636 | * @pdev: PCI device whose resources are to be reserved | |
2637 | * @bars: Bitmask of BARs to be requested | |
2638 | * @res_name: Name to be associated with resource | |
2639 | */ | |
2640 | int pci_request_selected_regions(struct pci_dev *pdev, int bars, | |
2641 | const char *res_name) | |
2642 | { | |
2643 | return __pci_request_selected_regions(pdev, bars, res_name, 0); | |
2644 | } | |
2645 | ||
2646 | int pci_request_selected_regions_exclusive(struct pci_dev *pdev, | |
2647 | int bars, const char *res_name) | |
2648 | { | |
2649 | return __pci_request_selected_regions(pdev, bars, res_name, | |
2650 | IORESOURCE_EXCLUSIVE); | |
2651 | } | |
2652 | ||
1da177e4 LT |
2653 | /** |
2654 | * pci_release_regions - Release reserved PCI I/O and memory resources | |
2655 | * @pdev: PCI device whose resources were previously reserved by pci_request_regions | |
2656 | * | |
2657 | * Releases all PCI I/O and memory resources previously reserved by a | |
2658 | * successful call to pci_request_regions. Call this function only | |
2659 | * after all use of the PCI regions has ceased. | |
2660 | */ | |
2661 | ||
2662 | void pci_release_regions(struct pci_dev *pdev) | |
2663 | { | |
c87deff7 | 2664 | pci_release_selected_regions(pdev, (1 << 6) - 1); |
1da177e4 LT |
2665 | } |
2666 | ||
2667 | /** | |
2668 | * pci_request_regions - Reserved PCI I/O and memory resources | |
2669 | * @pdev: PCI device whose resources are to be reserved | |
2670 | * @res_name: Name to be associated with resource. | |
2671 | * | |
2672 | * Mark all PCI regions associated with PCI device @pdev as | |
2673 | * being reserved by owner @res_name. Do not access any | |
2674 | * address inside the PCI regions unless this call returns | |
2675 | * successfully. | |
2676 | * | |
2677 | * Returns 0 on success, or %EBUSY on error. A warning | |
2678 | * message is also printed on failure. | |
2679 | */ | |
3c990e92 | 2680 | int pci_request_regions(struct pci_dev *pdev, const char *res_name) |
1da177e4 | 2681 | { |
c87deff7 | 2682 | return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name); |
1da177e4 LT |
2683 | } |
2684 | ||
e8de1481 AV |
2685 | /** |
2686 | * pci_request_regions_exclusive - Reserved PCI I/O and memory resources | |
2687 | * @pdev: PCI device whose resources are to be reserved | |
2688 | * @res_name: Name to be associated with resource. | |
2689 | * | |
2690 | * Mark all PCI regions associated with PCI device @pdev as | |
2691 | * being reserved by owner @res_name. Do not access any | |
2692 | * address inside the PCI regions unless this call returns | |
2693 | * successfully. | |
2694 | * | |
2695 | * pci_request_regions_exclusive() will mark the region so that | |
2696 | * /dev/mem and the sysfs MMIO access will not be allowed. | |
2697 | * | |
2698 | * Returns 0 on success, or %EBUSY on error. A warning | |
2699 | * message is also printed on failure. | |
2700 | */ | |
2701 | int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name) | |
2702 | { | |
2703 | return pci_request_selected_regions_exclusive(pdev, | |
2704 | ((1 << 6) - 1), res_name); | |
2705 | } | |
2706 | ||
6a479079 BH |
2707 | static void __pci_set_master(struct pci_dev *dev, bool enable) |
2708 | { | |
2709 | u16 old_cmd, cmd; | |
2710 | ||
2711 | pci_read_config_word(dev, PCI_COMMAND, &old_cmd); | |
2712 | if (enable) | |
2713 | cmd = old_cmd | PCI_COMMAND_MASTER; | |
2714 | else | |
2715 | cmd = old_cmd & ~PCI_COMMAND_MASTER; | |
2716 | if (cmd != old_cmd) { | |
2717 | dev_dbg(&dev->dev, "%s bus mastering\n", | |
2718 | enable ? "enabling" : "disabling"); | |
2719 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
2720 | } | |
2721 | dev->is_busmaster = enable; | |
2722 | } | |
e8de1481 | 2723 | |
2b6f2c35 MS |
2724 | /** |
2725 | * pcibios_setup - process "pci=" kernel boot arguments | |
2726 | * @str: string used to pass in "pci=" kernel boot arguments | |
2727 | * | |
2728 | * Process kernel boot arguments. This is the default implementation. | |
2729 | * Architecture specific implementations can override this as necessary. | |
2730 | */ | |
2731 | char * __weak __init pcibios_setup(char *str) | |
2732 | { | |
2733 | return str; | |
2734 | } | |
2735 | ||
96c55900 MS |
2736 | /** |
2737 | * pcibios_set_master - enable PCI bus-mastering for device dev | |
2738 | * @dev: the PCI device to enable | |
2739 | * | |
2740 | * Enables PCI bus-mastering for the device. This is the default | |
2741 | * implementation. Architecture specific implementations can override | |
2742 | * this if necessary. | |
2743 | */ | |
2744 | void __weak pcibios_set_master(struct pci_dev *dev) | |
2745 | { | |
2746 | u8 lat; | |
2747 | ||
f676678f MS |
2748 | /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */ |
2749 | if (pci_is_pcie(dev)) | |
2750 | return; | |
2751 | ||
96c55900 MS |
2752 | pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); |
2753 | if (lat < 16) | |
2754 | lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency; | |
2755 | else if (lat > pcibios_max_latency) | |
2756 | lat = pcibios_max_latency; | |
2757 | else | |
2758 | return; | |
2759 | dev_printk(KERN_DEBUG, &dev->dev, "setting latency timer to %d\n", lat); | |
2760 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); | |
2761 | } | |
2762 | ||
1da177e4 LT |
2763 | /** |
2764 | * pci_set_master - enables bus-mastering for device dev | |
2765 | * @dev: the PCI device to enable | |
2766 | * | |
2767 | * Enables bus-mastering on the device and calls pcibios_set_master() | |
2768 | * to do the needed arch specific settings. | |
2769 | */ | |
6a479079 | 2770 | void pci_set_master(struct pci_dev *dev) |
1da177e4 | 2771 | { |
6a479079 | 2772 | __pci_set_master(dev, true); |
1da177e4 LT |
2773 | pcibios_set_master(dev); |
2774 | } | |
2775 | ||
6a479079 BH |
2776 | /** |
2777 | * pci_clear_master - disables bus-mastering for device dev | |
2778 | * @dev: the PCI device to disable | |
2779 | */ | |
2780 | void pci_clear_master(struct pci_dev *dev) | |
2781 | { | |
2782 | __pci_set_master(dev, false); | |
2783 | } | |
2784 | ||
1da177e4 | 2785 | /** |
edb2d97e MW |
2786 | * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed |
2787 | * @dev: the PCI device for which MWI is to be enabled | |
1da177e4 | 2788 | * |
edb2d97e MW |
2789 | * Helper function for pci_set_mwi. |
2790 | * Originally copied from drivers/net/acenic.c. | |
1da177e4 LT |
2791 | * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. |
2792 | * | |
2793 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
2794 | */ | |
15ea76d4 | 2795 | int pci_set_cacheline_size(struct pci_dev *dev) |
1da177e4 LT |
2796 | { |
2797 | u8 cacheline_size; | |
2798 | ||
2799 | if (!pci_cache_line_size) | |
15ea76d4 | 2800 | return -EINVAL; |
1da177e4 LT |
2801 | |
2802 | /* Validate current setting: the PCI_CACHE_LINE_SIZE must be | |
2803 | equal to or multiple of the right value. */ | |
2804 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
2805 | if (cacheline_size >= pci_cache_line_size && | |
2806 | (cacheline_size % pci_cache_line_size) == 0) | |
2807 | return 0; | |
2808 | ||
2809 | /* Write the correct value. */ | |
2810 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size); | |
2811 | /* Read it back. */ | |
2812 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
2813 | if (cacheline_size == pci_cache_line_size) | |
2814 | return 0; | |
2815 | ||
80ccba11 BH |
2816 | dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not " |
2817 | "supported\n", pci_cache_line_size << 2); | |
1da177e4 LT |
2818 | |
2819 | return -EINVAL; | |
2820 | } | |
15ea76d4 TH |
2821 | EXPORT_SYMBOL_GPL(pci_set_cacheline_size); |
2822 | ||
2823 | #ifdef PCI_DISABLE_MWI | |
2824 | int pci_set_mwi(struct pci_dev *dev) | |
2825 | { | |
2826 | return 0; | |
2827 | } | |
2828 | ||
2829 | int pci_try_set_mwi(struct pci_dev *dev) | |
2830 | { | |
2831 | return 0; | |
2832 | } | |
2833 | ||
2834 | void pci_clear_mwi(struct pci_dev *dev) | |
2835 | { | |
2836 | } | |
2837 | ||
2838 | #else | |
1da177e4 LT |
2839 | |
2840 | /** | |
2841 | * pci_set_mwi - enables memory-write-invalidate PCI transaction | |
2842 | * @dev: the PCI device for which MWI is enabled | |
2843 | * | |
694625c0 | 2844 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. |
1da177e4 LT |
2845 | * |
2846 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
2847 | */ | |
2848 | int | |
2849 | pci_set_mwi(struct pci_dev *dev) | |
2850 | { | |
2851 | int rc; | |
2852 | u16 cmd; | |
2853 | ||
edb2d97e | 2854 | rc = pci_set_cacheline_size(dev); |
1da177e4 LT |
2855 | if (rc) |
2856 | return rc; | |
2857 | ||
2858 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
2859 | if (! (cmd & PCI_COMMAND_INVALIDATE)) { | |
80ccba11 | 2860 | dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n"); |
1da177e4 LT |
2861 | cmd |= PCI_COMMAND_INVALIDATE; |
2862 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
2863 | } | |
2864 | ||
2865 | return 0; | |
2866 | } | |
2867 | ||
694625c0 RD |
2868 | /** |
2869 | * pci_try_set_mwi - enables memory-write-invalidate PCI transaction | |
2870 | * @dev: the PCI device for which MWI is enabled | |
2871 | * | |
2872 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. | |
2873 | * Callers are not required to check the return value. | |
2874 | * | |
2875 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
2876 | */ | |
2877 | int pci_try_set_mwi(struct pci_dev *dev) | |
2878 | { | |
2879 | int rc = pci_set_mwi(dev); | |
2880 | return rc; | |
2881 | } | |
2882 | ||
1da177e4 LT |
2883 | /** |
2884 | * pci_clear_mwi - disables Memory-Write-Invalidate for device dev | |
2885 | * @dev: the PCI device to disable | |
2886 | * | |
2887 | * Disables PCI Memory-Write-Invalidate transaction on the device | |
2888 | */ | |
2889 | void | |
2890 | pci_clear_mwi(struct pci_dev *dev) | |
2891 | { | |
2892 | u16 cmd; | |
2893 | ||
2894 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
2895 | if (cmd & PCI_COMMAND_INVALIDATE) { | |
2896 | cmd &= ~PCI_COMMAND_INVALIDATE; | |
2897 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
2898 | } | |
2899 | } | |
edb2d97e | 2900 | #endif /* ! PCI_DISABLE_MWI */ |
1da177e4 | 2901 | |
a04ce0ff BR |
2902 | /** |
2903 | * pci_intx - enables/disables PCI INTx for device dev | |
8f7020d3 RD |
2904 | * @pdev: the PCI device to operate on |
2905 | * @enable: boolean: whether to enable or disable PCI INTx | |
a04ce0ff BR |
2906 | * |
2907 | * Enables/disables PCI INTx for device dev | |
2908 | */ | |
2909 | void | |
2910 | pci_intx(struct pci_dev *pdev, int enable) | |
2911 | { | |
2912 | u16 pci_command, new; | |
2913 | ||
2914 | pci_read_config_word(pdev, PCI_COMMAND, &pci_command); | |
2915 | ||
2916 | if (enable) { | |
2917 | new = pci_command & ~PCI_COMMAND_INTX_DISABLE; | |
2918 | } else { | |
2919 | new = pci_command | PCI_COMMAND_INTX_DISABLE; | |
2920 | } | |
2921 | ||
2922 | if (new != pci_command) { | |
9ac7849e TH |
2923 | struct pci_devres *dr; |
2924 | ||
2fd9d74b | 2925 | pci_write_config_word(pdev, PCI_COMMAND, new); |
9ac7849e TH |
2926 | |
2927 | dr = find_pci_dr(pdev); | |
2928 | if (dr && !dr->restore_intx) { | |
2929 | dr->restore_intx = 1; | |
2930 | dr->orig_intx = !enable; | |
2931 | } | |
a04ce0ff BR |
2932 | } |
2933 | } | |
2934 | ||
a2e27787 JK |
2935 | /** |
2936 | * pci_intx_mask_supported - probe for INTx masking support | |
6e9292c5 | 2937 | * @dev: the PCI device to operate on |
a2e27787 JK |
2938 | * |
2939 | * Check if the device dev support INTx masking via the config space | |
2940 | * command word. | |
2941 | */ | |
2942 | bool pci_intx_mask_supported(struct pci_dev *dev) | |
2943 | { | |
2944 | bool mask_supported = false; | |
2945 | u16 orig, new; | |
2946 | ||
fbebb9fd BH |
2947 | if (dev->broken_intx_masking) |
2948 | return false; | |
2949 | ||
a2e27787 JK |
2950 | pci_cfg_access_lock(dev); |
2951 | ||
2952 | pci_read_config_word(dev, PCI_COMMAND, &orig); | |
2953 | pci_write_config_word(dev, PCI_COMMAND, | |
2954 | orig ^ PCI_COMMAND_INTX_DISABLE); | |
2955 | pci_read_config_word(dev, PCI_COMMAND, &new); | |
2956 | ||
2957 | /* | |
2958 | * There's no way to protect against hardware bugs or detect them | |
2959 | * reliably, but as long as we know what the value should be, let's | |
2960 | * go ahead and check it. | |
2961 | */ | |
2962 | if ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) { | |
2963 | dev_err(&dev->dev, "Command register changed from " | |
2964 | "0x%x to 0x%x: driver or hardware bug?\n", orig, new); | |
2965 | } else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) { | |
2966 | mask_supported = true; | |
2967 | pci_write_config_word(dev, PCI_COMMAND, orig); | |
2968 | } | |
2969 | ||
2970 | pci_cfg_access_unlock(dev); | |
2971 | return mask_supported; | |
2972 | } | |
2973 | EXPORT_SYMBOL_GPL(pci_intx_mask_supported); | |
2974 | ||
2975 | static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask) | |
2976 | { | |
2977 | struct pci_bus *bus = dev->bus; | |
2978 | bool mask_updated = true; | |
2979 | u32 cmd_status_dword; | |
2980 | u16 origcmd, newcmd; | |
2981 | unsigned long flags; | |
2982 | bool irq_pending; | |
2983 | ||
2984 | /* | |
2985 | * We do a single dword read to retrieve both command and status. | |
2986 | * Document assumptions that make this possible. | |
2987 | */ | |
2988 | BUILD_BUG_ON(PCI_COMMAND % 4); | |
2989 | BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS); | |
2990 | ||
2991 | raw_spin_lock_irqsave(&pci_lock, flags); | |
2992 | ||
2993 | bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword); | |
2994 | ||
2995 | irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT; | |
2996 | ||
2997 | /* | |
2998 | * Check interrupt status register to see whether our device | |
2999 | * triggered the interrupt (when masking) or the next IRQ is | |
3000 | * already pending (when unmasking). | |
3001 | */ | |
3002 | if (mask != irq_pending) { | |
3003 | mask_updated = false; | |
3004 | goto done; | |
3005 | } | |
3006 | ||
3007 | origcmd = cmd_status_dword; | |
3008 | newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE; | |
3009 | if (mask) | |
3010 | newcmd |= PCI_COMMAND_INTX_DISABLE; | |
3011 | if (newcmd != origcmd) | |
3012 | bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd); | |
3013 | ||
3014 | done: | |
3015 | raw_spin_unlock_irqrestore(&pci_lock, flags); | |
3016 | ||
3017 | return mask_updated; | |
3018 | } | |
3019 | ||
3020 | /** | |
3021 | * pci_check_and_mask_intx - mask INTx on pending interrupt | |
6e9292c5 | 3022 | * @dev: the PCI device to operate on |
a2e27787 JK |
3023 | * |
3024 | * Check if the device dev has its INTx line asserted, mask it and | |
3025 | * return true in that case. False is returned if not interrupt was | |
3026 | * pending. | |
3027 | */ | |
3028 | bool pci_check_and_mask_intx(struct pci_dev *dev) | |
3029 | { | |
3030 | return pci_check_and_set_intx_mask(dev, true); | |
3031 | } | |
3032 | EXPORT_SYMBOL_GPL(pci_check_and_mask_intx); | |
3033 | ||
3034 | /** | |
3035 | * pci_check_and_mask_intx - unmask INTx of no interrupt is pending | |
6e9292c5 | 3036 | * @dev: the PCI device to operate on |
a2e27787 JK |
3037 | * |
3038 | * Check if the device dev has its INTx line asserted, unmask it if not | |
3039 | * and return true. False is returned and the mask remains active if | |
3040 | * there was still an interrupt pending. | |
3041 | */ | |
3042 | bool pci_check_and_unmask_intx(struct pci_dev *dev) | |
3043 | { | |
3044 | return pci_check_and_set_intx_mask(dev, false); | |
3045 | } | |
3046 | EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx); | |
3047 | ||
f5f2b131 EB |
3048 | /** |
3049 | * pci_msi_off - disables any msi or msix capabilities | |
8d7d86e9 | 3050 | * @dev: the PCI device to operate on |
f5f2b131 EB |
3051 | * |
3052 | * If you want to use msi see pci_enable_msi and friends. | |
3053 | * This is a lower level primitive that allows us to disable | |
3054 | * msi operation at the device level. | |
3055 | */ | |
3056 | void pci_msi_off(struct pci_dev *dev) | |
3057 | { | |
3058 | int pos; | |
3059 | u16 control; | |
3060 | ||
3061 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
3062 | if (pos) { | |
3063 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); | |
3064 | control &= ~PCI_MSI_FLAGS_ENABLE; | |
3065 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); | |
3066 | } | |
3067 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
3068 | if (pos) { | |
3069 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); | |
3070 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
3071 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
3072 | } | |
3073 | } | |
b03214d5 | 3074 | EXPORT_SYMBOL_GPL(pci_msi_off); |
f5f2b131 | 3075 | |
4d57cdfa FT |
3076 | int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size) |
3077 | { | |
3078 | return dma_set_max_seg_size(&dev->dev, size); | |
3079 | } | |
3080 | EXPORT_SYMBOL(pci_set_dma_max_seg_size); | |
4d57cdfa | 3081 | |
59fc67de FT |
3082 | int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask) |
3083 | { | |
3084 | return dma_set_seg_boundary(&dev->dev, mask); | |
3085 | } | |
3086 | EXPORT_SYMBOL(pci_set_dma_seg_boundary); | |
59fc67de | 3087 | |
8c1c699f | 3088 | static int pcie_flr(struct pci_dev *dev, int probe) |
8dd7f803 | 3089 | { |
8c1c699f | 3090 | int i; |
8dd7f803 | 3091 | u32 cap; |
59875ae4 | 3092 | u16 status; |
8c1c699f | 3093 | |
59875ae4 | 3094 | pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); |
8dd7f803 SY |
3095 | if (!(cap & PCI_EXP_DEVCAP_FLR)) |
3096 | return -ENOTTY; | |
3097 | ||
d91cdc74 SY |
3098 | if (probe) |
3099 | return 0; | |
3100 | ||
8dd7f803 | 3101 | /* Wait for Transaction Pending bit clean */ |
8c1c699f YZ |
3102 | for (i = 0; i < 4; i++) { |
3103 | if (i) | |
3104 | msleep((1 << (i - 1)) * 100); | |
5fe5db05 | 3105 | |
59875ae4 | 3106 | pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status); |
8c1c699f YZ |
3107 | if (!(status & PCI_EXP_DEVSTA_TRPND)) |
3108 | goto clear; | |
3109 | } | |
3110 | ||
3111 | dev_err(&dev->dev, "transaction is not cleared; " | |
3112 | "proceeding with reset anyway\n"); | |
3113 | ||
3114 | clear: | |
59875ae4 | 3115 | pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); |
04b55c47 | 3116 | |
8c1c699f | 3117 | msleep(100); |
8dd7f803 | 3118 | |
8dd7f803 SY |
3119 | return 0; |
3120 | } | |
d91cdc74 | 3121 | |
8c1c699f | 3122 | static int pci_af_flr(struct pci_dev *dev, int probe) |
1ca88797 | 3123 | { |
8c1c699f YZ |
3124 | int i; |
3125 | int pos; | |
1ca88797 | 3126 | u8 cap; |
8c1c699f | 3127 | u8 status; |
1ca88797 | 3128 | |
8c1c699f YZ |
3129 | pos = pci_find_capability(dev, PCI_CAP_ID_AF); |
3130 | if (!pos) | |
1ca88797 | 3131 | return -ENOTTY; |
8c1c699f YZ |
3132 | |
3133 | pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap); | |
1ca88797 SY |
3134 | if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR)) |
3135 | return -ENOTTY; | |
3136 | ||
3137 | if (probe) | |
3138 | return 0; | |
3139 | ||
1ca88797 | 3140 | /* Wait for Transaction Pending bit clean */ |
8c1c699f YZ |
3141 | for (i = 0; i < 4; i++) { |
3142 | if (i) | |
3143 | msleep((1 << (i - 1)) * 100); | |
3144 | ||
3145 | pci_read_config_byte(dev, pos + PCI_AF_STATUS, &status); | |
3146 | if (!(status & PCI_AF_STATUS_TP)) | |
3147 | goto clear; | |
3148 | } | |
5fe5db05 | 3149 | |
8c1c699f YZ |
3150 | dev_err(&dev->dev, "transaction is not cleared; " |
3151 | "proceeding with reset anyway\n"); | |
5fe5db05 | 3152 | |
8c1c699f YZ |
3153 | clear: |
3154 | pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR); | |
1ca88797 | 3155 | msleep(100); |
8c1c699f | 3156 | |
1ca88797 SY |
3157 | return 0; |
3158 | } | |
3159 | ||
83d74e03 RW |
3160 | /** |
3161 | * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0. | |
3162 | * @dev: Device to reset. | |
3163 | * @probe: If set, only check if the device can be reset this way. | |
3164 | * | |
3165 | * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is | |
3166 | * unset, it will be reinitialized internally when going from PCI_D3hot to | |
3167 | * PCI_D0. If that's the case and the device is not in a low-power state | |
3168 | * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset. | |
3169 | * | |
3170 | * NOTE: This causes the caller to sleep for twice the device power transition | |
3171 | * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms | |
3172 | * by devault (i.e. unless the @dev's d3_delay field has a different value). | |
3173 | * Moreover, only devices in D0 can be reset by this function. | |
3174 | */ | |
f85876ba | 3175 | static int pci_pm_reset(struct pci_dev *dev, int probe) |
d91cdc74 | 3176 | { |
f85876ba YZ |
3177 | u16 csr; |
3178 | ||
3179 | if (!dev->pm_cap) | |
3180 | return -ENOTTY; | |
d91cdc74 | 3181 | |
f85876ba YZ |
3182 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr); |
3183 | if (csr & PCI_PM_CTRL_NO_SOFT_RESET) | |
3184 | return -ENOTTY; | |
d91cdc74 | 3185 | |
f85876ba YZ |
3186 | if (probe) |
3187 | return 0; | |
1ca88797 | 3188 | |
f85876ba YZ |
3189 | if (dev->current_state != PCI_D0) |
3190 | return -EINVAL; | |
3191 | ||
3192 | csr &= ~PCI_PM_CTRL_STATE_MASK; | |
3193 | csr |= PCI_D3hot; | |
3194 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); | |
1ae861e6 | 3195 | pci_dev_d3_sleep(dev); |
f85876ba YZ |
3196 | |
3197 | csr &= ~PCI_PM_CTRL_STATE_MASK; | |
3198 | csr |= PCI_D0; | |
3199 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); | |
1ae861e6 | 3200 | pci_dev_d3_sleep(dev); |
f85876ba YZ |
3201 | |
3202 | return 0; | |
3203 | } | |
3204 | ||
c12ff1df YZ |
3205 | static int pci_parent_bus_reset(struct pci_dev *dev, int probe) |
3206 | { | |
3207 | u16 ctrl; | |
3208 | struct pci_dev *pdev; | |
3209 | ||
654b75e0 | 3210 | if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self) |
c12ff1df YZ |
3211 | return -ENOTTY; |
3212 | ||
3213 | list_for_each_entry(pdev, &dev->bus->devices, bus_list) | |
3214 | if (pdev != dev) | |
3215 | return -ENOTTY; | |
3216 | ||
3217 | if (probe) | |
3218 | return 0; | |
3219 | ||
3220 | pci_read_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, &ctrl); | |
3221 | ctrl |= PCI_BRIDGE_CTL_BUS_RESET; | |
3222 | pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl); | |
3223 | msleep(100); | |
3224 | ||
3225 | ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; | |
3226 | pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl); | |
3227 | msleep(100); | |
3228 | ||
3229 | return 0; | |
3230 | } | |
3231 | ||
977f857c | 3232 | static int __pci_dev_reset(struct pci_dev *dev, int probe) |
d91cdc74 | 3233 | { |
8c1c699f YZ |
3234 | int rc; |
3235 | ||
3236 | might_sleep(); | |
3237 | ||
b9c3b266 DC |
3238 | rc = pci_dev_specific_reset(dev, probe); |
3239 | if (rc != -ENOTTY) | |
3240 | goto done; | |
3241 | ||
8c1c699f YZ |
3242 | rc = pcie_flr(dev, probe); |
3243 | if (rc != -ENOTTY) | |
3244 | goto done; | |
d91cdc74 | 3245 | |
8c1c699f | 3246 | rc = pci_af_flr(dev, probe); |
f85876ba YZ |
3247 | if (rc != -ENOTTY) |
3248 | goto done; | |
3249 | ||
3250 | rc = pci_pm_reset(dev, probe); | |
c12ff1df YZ |
3251 | if (rc != -ENOTTY) |
3252 | goto done; | |
3253 | ||
3254 | rc = pci_parent_bus_reset(dev, probe); | |
8c1c699f | 3255 | done: |
977f857c KRW |
3256 | return rc; |
3257 | } | |
3258 | ||
3259 | static int pci_dev_reset(struct pci_dev *dev, int probe) | |
3260 | { | |
3261 | int rc; | |
3262 | ||
3263 | if (!probe) { | |
3264 | pci_cfg_access_lock(dev); | |
3265 | /* block PM suspend, driver probe, etc. */ | |
3266 | device_lock(&dev->dev); | |
3267 | } | |
3268 | ||
3269 | rc = __pci_dev_reset(dev, probe); | |
3270 | ||
8c1c699f | 3271 | if (!probe) { |
8e9394ce | 3272 | device_unlock(&dev->dev); |
fb51ccbf | 3273 | pci_cfg_access_unlock(dev); |
8c1c699f | 3274 | } |
8c1c699f | 3275 | return rc; |
d91cdc74 | 3276 | } |
d91cdc74 | 3277 | /** |
8c1c699f YZ |
3278 | * __pci_reset_function - reset a PCI device function |
3279 | * @dev: PCI device to reset | |
d91cdc74 SY |
3280 | * |
3281 | * Some devices allow an individual function to be reset without affecting | |
3282 | * other functions in the same device. The PCI device must be responsive | |
3283 | * to PCI config space in order to use this function. | |
3284 | * | |
3285 | * The device function is presumed to be unused when this function is called. | |
3286 | * Resetting the device will make the contents of PCI configuration space | |
3287 | * random, so any caller of this must be prepared to reinitialise the | |
3288 | * device including MSI, bus mastering, BARs, decoding IO and memory spaces, | |
3289 | * etc. | |
3290 | * | |
8c1c699f | 3291 | * Returns 0 if the device function was successfully reset or negative if the |
d91cdc74 SY |
3292 | * device doesn't support resetting a single function. |
3293 | */ | |
8c1c699f | 3294 | int __pci_reset_function(struct pci_dev *dev) |
d91cdc74 | 3295 | { |
8c1c699f | 3296 | return pci_dev_reset(dev, 0); |
d91cdc74 | 3297 | } |
8c1c699f | 3298 | EXPORT_SYMBOL_GPL(__pci_reset_function); |
8dd7f803 | 3299 | |
6fbf9e7a KRW |
3300 | /** |
3301 | * __pci_reset_function_locked - reset a PCI device function while holding | |
3302 | * the @dev mutex lock. | |
3303 | * @dev: PCI device to reset | |
3304 | * | |
3305 | * Some devices allow an individual function to be reset without affecting | |
3306 | * other functions in the same device. The PCI device must be responsive | |
3307 | * to PCI config space in order to use this function. | |
3308 | * | |
3309 | * The device function is presumed to be unused and the caller is holding | |
3310 | * the device mutex lock when this function is called. | |
3311 | * Resetting the device will make the contents of PCI configuration space | |
3312 | * random, so any caller of this must be prepared to reinitialise the | |
3313 | * device including MSI, bus mastering, BARs, decoding IO and memory spaces, | |
3314 | * etc. | |
3315 | * | |
3316 | * Returns 0 if the device function was successfully reset or negative if the | |
3317 | * device doesn't support resetting a single function. | |
3318 | */ | |
3319 | int __pci_reset_function_locked(struct pci_dev *dev) | |
3320 | { | |
977f857c | 3321 | return __pci_dev_reset(dev, 0); |
6fbf9e7a KRW |
3322 | } |
3323 | EXPORT_SYMBOL_GPL(__pci_reset_function_locked); | |
3324 | ||
711d5779 MT |
3325 | /** |
3326 | * pci_probe_reset_function - check whether the device can be safely reset | |
3327 | * @dev: PCI device to reset | |
3328 | * | |
3329 | * Some devices allow an individual function to be reset without affecting | |
3330 | * other functions in the same device. The PCI device must be responsive | |
3331 | * to PCI config space in order to use this function. | |
3332 | * | |
3333 | * Returns 0 if the device function can be reset or negative if the | |
3334 | * device doesn't support resetting a single function. | |
3335 | */ | |
3336 | int pci_probe_reset_function(struct pci_dev *dev) | |
3337 | { | |
3338 | return pci_dev_reset(dev, 1); | |
3339 | } | |
3340 | ||
8dd7f803 | 3341 | /** |
8c1c699f YZ |
3342 | * pci_reset_function - quiesce and reset a PCI device function |
3343 | * @dev: PCI device to reset | |
8dd7f803 SY |
3344 | * |
3345 | * Some devices allow an individual function to be reset without affecting | |
3346 | * other functions in the same device. The PCI device must be responsive | |
3347 | * to PCI config space in order to use this function. | |
3348 | * | |
3349 | * This function does not just reset the PCI portion of a device, but | |
3350 | * clears all the state associated with the device. This function differs | |
8c1c699f | 3351 | * from __pci_reset_function in that it saves and restores device state |
8dd7f803 SY |
3352 | * over the reset. |
3353 | * | |
8c1c699f | 3354 | * Returns 0 if the device function was successfully reset or negative if the |
8dd7f803 SY |
3355 | * device doesn't support resetting a single function. |
3356 | */ | |
3357 | int pci_reset_function(struct pci_dev *dev) | |
3358 | { | |
8c1c699f | 3359 | int rc; |
8dd7f803 | 3360 | |
8c1c699f YZ |
3361 | rc = pci_dev_reset(dev, 1); |
3362 | if (rc) | |
3363 | return rc; | |
8dd7f803 | 3364 | |
8dd7f803 SY |
3365 | pci_save_state(dev); |
3366 | ||
8c1c699f YZ |
3367 | /* |
3368 | * both INTx and MSI are disabled after the Interrupt Disable bit | |
3369 | * is set and the Bus Master bit is cleared. | |
3370 | */ | |
8dd7f803 SY |
3371 | pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE); |
3372 | ||
8c1c699f | 3373 | rc = pci_dev_reset(dev, 0); |
8dd7f803 SY |
3374 | |
3375 | pci_restore_state(dev); | |
8dd7f803 | 3376 | |
8c1c699f | 3377 | return rc; |
8dd7f803 SY |
3378 | } |
3379 | EXPORT_SYMBOL_GPL(pci_reset_function); | |
3380 | ||
d556ad4b PO |
3381 | /** |
3382 | * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count | |
3383 | * @dev: PCI device to query | |
3384 | * | |
3385 | * Returns mmrbc: maximum designed memory read count in bytes | |
3386 | * or appropriate error value. | |
3387 | */ | |
3388 | int pcix_get_max_mmrbc(struct pci_dev *dev) | |
3389 | { | |
7c9e2b1c | 3390 | int cap; |
d556ad4b PO |
3391 | u32 stat; |
3392 | ||
3393 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
3394 | if (!cap) | |
3395 | return -EINVAL; | |
3396 | ||
7c9e2b1c | 3397 | if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat)) |
d556ad4b PO |
3398 | return -EINVAL; |
3399 | ||
25daeb55 | 3400 | return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21); |
d556ad4b PO |
3401 | } |
3402 | EXPORT_SYMBOL(pcix_get_max_mmrbc); | |
3403 | ||
3404 | /** | |
3405 | * pcix_get_mmrbc - get PCI-X maximum memory read byte count | |
3406 | * @dev: PCI device to query | |
3407 | * | |
3408 | * Returns mmrbc: maximum memory read count in bytes | |
3409 | * or appropriate error value. | |
3410 | */ | |
3411 | int pcix_get_mmrbc(struct pci_dev *dev) | |
3412 | { | |
7c9e2b1c | 3413 | int cap; |
bdc2bda7 | 3414 | u16 cmd; |
d556ad4b PO |
3415 | |
3416 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
3417 | if (!cap) | |
3418 | return -EINVAL; | |
3419 | ||
7c9e2b1c DN |
3420 | if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd)) |
3421 | return -EINVAL; | |
d556ad4b | 3422 | |
7c9e2b1c | 3423 | return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2); |
d556ad4b PO |
3424 | } |
3425 | EXPORT_SYMBOL(pcix_get_mmrbc); | |
3426 | ||
3427 | /** | |
3428 | * pcix_set_mmrbc - set PCI-X maximum memory read byte count | |
3429 | * @dev: PCI device to query | |
3430 | * @mmrbc: maximum memory read count in bytes | |
3431 | * valid values are 512, 1024, 2048, 4096 | |
3432 | * | |
3433 | * If possible sets maximum memory read byte count, some bridges have erratas | |
3434 | * that prevent this. | |
3435 | */ | |
3436 | int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc) | |
3437 | { | |
7c9e2b1c | 3438 | int cap; |
bdc2bda7 DN |
3439 | u32 stat, v, o; |
3440 | u16 cmd; | |
d556ad4b | 3441 | |
229f5afd | 3442 | if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc)) |
7c9e2b1c | 3443 | return -EINVAL; |
d556ad4b PO |
3444 | |
3445 | v = ffs(mmrbc) - 10; | |
3446 | ||
3447 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
3448 | if (!cap) | |
7c9e2b1c | 3449 | return -EINVAL; |
d556ad4b | 3450 | |
7c9e2b1c DN |
3451 | if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat)) |
3452 | return -EINVAL; | |
d556ad4b PO |
3453 | |
3454 | if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21) | |
3455 | return -E2BIG; | |
3456 | ||
7c9e2b1c DN |
3457 | if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd)) |
3458 | return -EINVAL; | |
d556ad4b PO |
3459 | |
3460 | o = (cmd & PCI_X_CMD_MAX_READ) >> 2; | |
3461 | if (o != v) { | |
809a3bf9 | 3462 | if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC)) |
d556ad4b PO |
3463 | return -EIO; |
3464 | ||
3465 | cmd &= ~PCI_X_CMD_MAX_READ; | |
3466 | cmd |= v << 2; | |
7c9e2b1c DN |
3467 | if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd)) |
3468 | return -EIO; | |
d556ad4b | 3469 | } |
7c9e2b1c | 3470 | return 0; |
d556ad4b PO |
3471 | } |
3472 | EXPORT_SYMBOL(pcix_set_mmrbc); | |
3473 | ||
3474 | /** | |
3475 | * pcie_get_readrq - get PCI Express read request size | |
3476 | * @dev: PCI device to query | |
3477 | * | |
3478 | * Returns maximum memory read request in bytes | |
3479 | * or appropriate error value. | |
3480 | */ | |
3481 | int pcie_get_readrq(struct pci_dev *dev) | |
3482 | { | |
d556ad4b PO |
3483 | u16 ctl; |
3484 | ||
59875ae4 | 3485 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); |
d556ad4b | 3486 | |
59875ae4 | 3487 | return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12); |
d556ad4b PO |
3488 | } |
3489 | EXPORT_SYMBOL(pcie_get_readrq); | |
3490 | ||
3491 | /** | |
3492 | * pcie_set_readrq - set PCI Express maximum memory read request | |
3493 | * @dev: PCI device to query | |
42e61f4a | 3494 | * @rq: maximum memory read count in bytes |
d556ad4b PO |
3495 | * valid values are 128, 256, 512, 1024, 2048, 4096 |
3496 | * | |
c9b378c7 | 3497 | * If possible sets maximum memory read request in bytes |
d556ad4b PO |
3498 | */ |
3499 | int pcie_set_readrq(struct pci_dev *dev, int rq) | |
3500 | { | |
59875ae4 | 3501 | u16 v; |
d556ad4b | 3502 | |
229f5afd | 3503 | if (rq < 128 || rq > 4096 || !is_power_of_2(rq)) |
59875ae4 | 3504 | return -EINVAL; |
d556ad4b | 3505 | |
a1c473aa BH |
3506 | /* |
3507 | * If using the "performance" PCIe config, we clamp the | |
3508 | * read rq size to the max packet size to prevent the | |
3509 | * host bridge generating requests larger than we can | |
3510 | * cope with | |
3511 | */ | |
3512 | if (pcie_bus_config == PCIE_BUS_PERFORMANCE) { | |
3513 | int mps = pcie_get_mps(dev); | |
3514 | ||
3515 | if (mps < 0) | |
3516 | return mps; | |
3517 | if (mps < rq) | |
3518 | rq = mps; | |
3519 | } | |
3520 | ||
3521 | v = (ffs(rq) - 8) << 12; | |
d556ad4b | 3522 | |
59875ae4 JL |
3523 | return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, |
3524 | PCI_EXP_DEVCTL_READRQ, v); | |
d556ad4b PO |
3525 | } |
3526 | EXPORT_SYMBOL(pcie_set_readrq); | |
3527 | ||
b03e7495 JM |
3528 | /** |
3529 | * pcie_get_mps - get PCI Express maximum payload size | |
3530 | * @dev: PCI device to query | |
3531 | * | |
3532 | * Returns maximum payload size in bytes | |
3533 | * or appropriate error value. | |
3534 | */ | |
3535 | int pcie_get_mps(struct pci_dev *dev) | |
3536 | { | |
b03e7495 JM |
3537 | u16 ctl; |
3538 | ||
59875ae4 | 3539 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); |
b03e7495 | 3540 | |
59875ae4 | 3541 | return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); |
b03e7495 JM |
3542 | } |
3543 | ||
3544 | /** | |
3545 | * pcie_set_mps - set PCI Express maximum payload size | |
3546 | * @dev: PCI device to query | |
47c08f31 | 3547 | * @mps: maximum payload size in bytes |
b03e7495 JM |
3548 | * valid values are 128, 256, 512, 1024, 2048, 4096 |
3549 | * | |
3550 | * If possible sets maximum payload size | |
3551 | */ | |
3552 | int pcie_set_mps(struct pci_dev *dev, int mps) | |
3553 | { | |
59875ae4 | 3554 | u16 v; |
b03e7495 JM |
3555 | |
3556 | if (mps < 128 || mps > 4096 || !is_power_of_2(mps)) | |
59875ae4 | 3557 | return -EINVAL; |
b03e7495 JM |
3558 | |
3559 | v = ffs(mps) - 8; | |
3560 | if (v > dev->pcie_mpss) | |
59875ae4 | 3561 | return -EINVAL; |
b03e7495 JM |
3562 | v <<= 5; |
3563 | ||
59875ae4 JL |
3564 | return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, |
3565 | PCI_EXP_DEVCTL_PAYLOAD, v); | |
b03e7495 JM |
3566 | } |
3567 | ||
c87deff7 HS |
3568 | /** |
3569 | * pci_select_bars - Make BAR mask from the type of resource | |
f95d882d | 3570 | * @dev: the PCI device for which BAR mask is made |
c87deff7 HS |
3571 | * @flags: resource type mask to be selected |
3572 | * | |
3573 | * This helper routine makes bar mask from the type of resource. | |
3574 | */ | |
3575 | int pci_select_bars(struct pci_dev *dev, unsigned long flags) | |
3576 | { | |
3577 | int i, bars = 0; | |
3578 | for (i = 0; i < PCI_NUM_RESOURCES; i++) | |
3579 | if (pci_resource_flags(dev, i) & flags) | |
3580 | bars |= (1 << i); | |
3581 | return bars; | |
3582 | } | |
3583 | ||
613e7ed6 YZ |
3584 | /** |
3585 | * pci_resource_bar - get position of the BAR associated with a resource | |
3586 | * @dev: the PCI device | |
3587 | * @resno: the resource number | |
3588 | * @type: the BAR type to be filled in | |
3589 | * | |
3590 | * Returns BAR position in config space, or 0 if the BAR is invalid. | |
3591 | */ | |
3592 | int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type) | |
3593 | { | |
d1b054da YZ |
3594 | int reg; |
3595 | ||
613e7ed6 YZ |
3596 | if (resno < PCI_ROM_RESOURCE) { |
3597 | *type = pci_bar_unknown; | |
3598 | return PCI_BASE_ADDRESS_0 + 4 * resno; | |
3599 | } else if (resno == PCI_ROM_RESOURCE) { | |
3600 | *type = pci_bar_mem32; | |
3601 | return dev->rom_base_reg; | |
d1b054da YZ |
3602 | } else if (resno < PCI_BRIDGE_RESOURCES) { |
3603 | /* device specific resource */ | |
3604 | reg = pci_iov_resource_bar(dev, resno, type); | |
3605 | if (reg) | |
3606 | return reg; | |
613e7ed6 YZ |
3607 | } |
3608 | ||
865df576 | 3609 | dev_err(&dev->dev, "BAR %d: invalid resource\n", resno); |
613e7ed6 YZ |
3610 | return 0; |
3611 | } | |
3612 | ||
95a8b6ef MT |
3613 | /* Some architectures require additional programming to enable VGA */ |
3614 | static arch_set_vga_state_t arch_set_vga_state; | |
3615 | ||
3616 | void __init pci_register_set_vga_state(arch_set_vga_state_t func) | |
3617 | { | |
3618 | arch_set_vga_state = func; /* NULL disables */ | |
3619 | } | |
3620 | ||
3621 | static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode, | |
7ad35cf2 | 3622 | unsigned int command_bits, u32 flags) |
95a8b6ef MT |
3623 | { |
3624 | if (arch_set_vga_state) | |
3625 | return arch_set_vga_state(dev, decode, command_bits, | |
7ad35cf2 | 3626 | flags); |
95a8b6ef MT |
3627 | return 0; |
3628 | } | |
3629 | ||
deb2d2ec BH |
3630 | /** |
3631 | * pci_set_vga_state - set VGA decode state on device and parents if requested | |
19eea630 RD |
3632 | * @dev: the PCI device |
3633 | * @decode: true = enable decoding, false = disable decoding | |
3634 | * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY | |
3f37d622 | 3635 | * @flags: traverse ancestors and change bridges |
3448a19d | 3636 | * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE |
deb2d2ec BH |
3637 | */ |
3638 | int pci_set_vga_state(struct pci_dev *dev, bool decode, | |
3448a19d | 3639 | unsigned int command_bits, u32 flags) |
deb2d2ec BH |
3640 | { |
3641 | struct pci_bus *bus; | |
3642 | struct pci_dev *bridge; | |
3643 | u16 cmd; | |
95a8b6ef | 3644 | int rc; |
deb2d2ec | 3645 | |
3448a19d | 3646 | WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) & (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY))); |
deb2d2ec | 3647 | |
95a8b6ef | 3648 | /* ARCH specific VGA enables */ |
3448a19d | 3649 | rc = pci_set_vga_state_arch(dev, decode, command_bits, flags); |
95a8b6ef MT |
3650 | if (rc) |
3651 | return rc; | |
3652 | ||
3448a19d DA |
3653 | if (flags & PCI_VGA_STATE_CHANGE_DECODES) { |
3654 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
3655 | if (decode == true) | |
3656 | cmd |= command_bits; | |
3657 | else | |
3658 | cmd &= ~command_bits; | |
3659 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
3660 | } | |
deb2d2ec | 3661 | |
3448a19d | 3662 | if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE)) |
deb2d2ec BH |
3663 | return 0; |
3664 | ||
3665 | bus = dev->bus; | |
3666 | while (bus) { | |
3667 | bridge = bus->self; | |
3668 | if (bridge) { | |
3669 | pci_read_config_word(bridge, PCI_BRIDGE_CONTROL, | |
3670 | &cmd); | |
3671 | if (decode == true) | |
3672 | cmd |= PCI_BRIDGE_CTL_VGA; | |
3673 | else | |
3674 | cmd &= ~PCI_BRIDGE_CTL_VGA; | |
3675 | pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, | |
3676 | cmd); | |
3677 | } | |
3678 | bus = bus->parent; | |
3679 | } | |
3680 | return 0; | |
3681 | } | |
3682 | ||
32a9a682 YS |
3683 | #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE |
3684 | static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0}; | |
e9d1e492 | 3685 | static DEFINE_SPINLOCK(resource_alignment_lock); |
32a9a682 YS |
3686 | |
3687 | /** | |
3688 | * pci_specified_resource_alignment - get resource alignment specified by user. | |
3689 | * @dev: the PCI device to get | |
3690 | * | |
3691 | * RETURNS: Resource alignment if it is specified. | |
3692 | * Zero if it is not specified. | |
3693 | */ | |
3694 | resource_size_t pci_specified_resource_alignment(struct pci_dev *dev) | |
3695 | { | |
3696 | int seg, bus, slot, func, align_order, count; | |
3697 | resource_size_t align = 0; | |
3698 | char *p; | |
3699 | ||
3700 | spin_lock(&resource_alignment_lock); | |
3701 | p = resource_alignment_param; | |
3702 | while (*p) { | |
3703 | count = 0; | |
3704 | if (sscanf(p, "%d%n", &align_order, &count) == 1 && | |
3705 | p[count] == '@') { | |
3706 | p += count + 1; | |
3707 | } else { | |
3708 | align_order = -1; | |
3709 | } | |
3710 | if (sscanf(p, "%x:%x:%x.%x%n", | |
3711 | &seg, &bus, &slot, &func, &count) != 4) { | |
3712 | seg = 0; | |
3713 | if (sscanf(p, "%x:%x.%x%n", | |
3714 | &bus, &slot, &func, &count) != 3) { | |
3715 | /* Invalid format */ | |
3716 | printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n", | |
3717 | p); | |
3718 | break; | |
3719 | } | |
3720 | } | |
3721 | p += count; | |
3722 | if (seg == pci_domain_nr(dev->bus) && | |
3723 | bus == dev->bus->number && | |
3724 | slot == PCI_SLOT(dev->devfn) && | |
3725 | func == PCI_FUNC(dev->devfn)) { | |
3726 | if (align_order == -1) { | |
3727 | align = PAGE_SIZE; | |
3728 | } else { | |
3729 | align = 1 << align_order; | |
3730 | } | |
3731 | /* Found */ | |
3732 | break; | |
3733 | } | |
3734 | if (*p != ';' && *p != ',') { | |
3735 | /* End of param or invalid format */ | |
3736 | break; | |
3737 | } | |
3738 | p++; | |
3739 | } | |
3740 | spin_unlock(&resource_alignment_lock); | |
3741 | return align; | |
3742 | } | |
3743 | ||
3744 | /** | |
3745 | * pci_is_reassigndev - check if specified PCI is target device to reassign | |
3746 | * @dev: the PCI device to check | |
3747 | * | |
3748 | * RETURNS: non-zero for PCI device is a target device to reassign, | |
3749 | * or zero is not. | |
3750 | */ | |
3751 | int pci_is_reassigndev(struct pci_dev *dev) | |
3752 | { | |
3753 | return (pci_specified_resource_alignment(dev) != 0); | |
3754 | } | |
3755 | ||
2069ecfb YL |
3756 | /* |
3757 | * This function disables memory decoding and releases memory resources | |
3758 | * of the device specified by kernel's boot parameter 'pci=resource_alignment='. | |
3759 | * It also rounds up size to specified alignment. | |
3760 | * Later on, the kernel will assign page-aligned memory resource back | |
3761 | * to the device. | |
3762 | */ | |
3763 | void pci_reassigndev_resource_alignment(struct pci_dev *dev) | |
3764 | { | |
3765 | int i; | |
3766 | struct resource *r; | |
3767 | resource_size_t align, size; | |
3768 | u16 command; | |
3769 | ||
3770 | if (!pci_is_reassigndev(dev)) | |
3771 | return; | |
3772 | ||
3773 | if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL && | |
3774 | (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) { | |
3775 | dev_warn(&dev->dev, | |
3776 | "Can't reassign resources to host bridge.\n"); | |
3777 | return; | |
3778 | } | |
3779 | ||
3780 | dev_info(&dev->dev, | |
3781 | "Disabling memory decoding and releasing memory resources.\n"); | |
3782 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
3783 | command &= ~PCI_COMMAND_MEMORY; | |
3784 | pci_write_config_word(dev, PCI_COMMAND, command); | |
3785 | ||
3786 | align = pci_specified_resource_alignment(dev); | |
3787 | for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) { | |
3788 | r = &dev->resource[i]; | |
3789 | if (!(r->flags & IORESOURCE_MEM)) | |
3790 | continue; | |
3791 | size = resource_size(r); | |
3792 | if (size < align) { | |
3793 | size = align; | |
3794 | dev_info(&dev->dev, | |
3795 | "Rounding up size of resource #%d to %#llx.\n", | |
3796 | i, (unsigned long long)size); | |
3797 | } | |
3798 | r->end = size - 1; | |
3799 | r->start = 0; | |
3800 | } | |
3801 | /* Need to disable bridge's resource window, | |
3802 | * to enable the kernel to reassign new resource | |
3803 | * window later on. | |
3804 | */ | |
3805 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE && | |
3806 | (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { | |
3807 | for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) { | |
3808 | r = &dev->resource[i]; | |
3809 | if (!(r->flags & IORESOURCE_MEM)) | |
3810 | continue; | |
3811 | r->end = resource_size(r) - 1; | |
3812 | r->start = 0; | |
3813 | } | |
3814 | pci_disable_bridge_window(dev); | |
3815 | } | |
3816 | } | |
3817 | ||
32a9a682 YS |
3818 | ssize_t pci_set_resource_alignment_param(const char *buf, size_t count) |
3819 | { | |
3820 | if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1) | |
3821 | count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1; | |
3822 | spin_lock(&resource_alignment_lock); | |
3823 | strncpy(resource_alignment_param, buf, count); | |
3824 | resource_alignment_param[count] = '\0'; | |
3825 | spin_unlock(&resource_alignment_lock); | |
3826 | return count; | |
3827 | } | |
3828 | ||
3829 | ssize_t pci_get_resource_alignment_param(char *buf, size_t size) | |
3830 | { | |
3831 | size_t count; | |
3832 | spin_lock(&resource_alignment_lock); | |
3833 | count = snprintf(buf, size, "%s", resource_alignment_param); | |
3834 | spin_unlock(&resource_alignment_lock); | |
3835 | return count; | |
3836 | } | |
3837 | ||
3838 | static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf) | |
3839 | { | |
3840 | return pci_get_resource_alignment_param(buf, PAGE_SIZE); | |
3841 | } | |
3842 | ||
3843 | static ssize_t pci_resource_alignment_store(struct bus_type *bus, | |
3844 | const char *buf, size_t count) | |
3845 | { | |
3846 | return pci_set_resource_alignment_param(buf, count); | |
3847 | } | |
3848 | ||
3849 | BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show, | |
3850 | pci_resource_alignment_store); | |
3851 | ||
3852 | static int __init pci_resource_alignment_sysfs_init(void) | |
3853 | { | |
3854 | return bus_create_file(&pci_bus_type, | |
3855 | &bus_attr_resource_alignment); | |
3856 | } | |
3857 | ||
3858 | late_initcall(pci_resource_alignment_sysfs_init); | |
3859 | ||
32a2eea7 JG |
3860 | static void __devinit pci_no_domains(void) |
3861 | { | |
3862 | #ifdef CONFIG_PCI_DOMAINS | |
3863 | pci_domains_supported = 0; | |
3864 | #endif | |
3865 | } | |
3866 | ||
0ef5f8f6 AP |
3867 | /** |
3868 | * pci_ext_cfg_enabled - can we access extended PCI config space? | |
3869 | * @dev: The PCI device of the root bridge. | |
3870 | * | |
3871 | * Returns 1 if we can access PCI extended config space (offsets | |
3872 | * greater than 0xff). This is the default implementation. Architecture | |
3873 | * implementations can override this. | |
3874 | */ | |
d6d88c83 | 3875 | int __weak pci_ext_cfg_avail(struct pci_dev *dev) |
0ef5f8f6 AP |
3876 | { |
3877 | return 1; | |
3878 | } | |
3879 | ||
2d1c8618 BH |
3880 | void __weak pci_fixup_cardbus(struct pci_bus *bus) |
3881 | { | |
3882 | } | |
3883 | EXPORT_SYMBOL(pci_fixup_cardbus); | |
3884 | ||
ad04d31e | 3885 | static int __init pci_setup(char *str) |
1da177e4 LT |
3886 | { |
3887 | while (str) { | |
3888 | char *k = strchr(str, ','); | |
3889 | if (k) | |
3890 | *k++ = 0; | |
3891 | if (*str && (str = pcibios_setup(str)) && *str) { | |
309e57df MW |
3892 | if (!strcmp(str, "nomsi")) { |
3893 | pci_no_msi(); | |
7f785763 RD |
3894 | } else if (!strcmp(str, "noaer")) { |
3895 | pci_no_aer(); | |
b55438fd YL |
3896 | } else if (!strncmp(str, "realloc=", 8)) { |
3897 | pci_realloc_get_opt(str + 8); | |
f483d392 | 3898 | } else if (!strncmp(str, "realloc", 7)) { |
b55438fd | 3899 | pci_realloc_get_opt("on"); |
32a2eea7 JG |
3900 | } else if (!strcmp(str, "nodomains")) { |
3901 | pci_no_domains(); | |
6748dcc2 RW |
3902 | } else if (!strncmp(str, "noari", 5)) { |
3903 | pcie_ari_disabled = true; | |
4516a618 AN |
3904 | } else if (!strncmp(str, "cbiosize=", 9)) { |
3905 | pci_cardbus_io_size = memparse(str + 9, &str); | |
3906 | } else if (!strncmp(str, "cbmemsize=", 10)) { | |
3907 | pci_cardbus_mem_size = memparse(str + 10, &str); | |
32a9a682 YS |
3908 | } else if (!strncmp(str, "resource_alignment=", 19)) { |
3909 | pci_set_resource_alignment_param(str + 19, | |
3910 | strlen(str + 19)); | |
43c16408 AP |
3911 | } else if (!strncmp(str, "ecrc=", 5)) { |
3912 | pcie_ecrc_get_policy(str + 5); | |
28760489 EB |
3913 | } else if (!strncmp(str, "hpiosize=", 9)) { |
3914 | pci_hotplug_io_size = memparse(str + 9, &str); | |
3915 | } else if (!strncmp(str, "hpmemsize=", 10)) { | |
3916 | pci_hotplug_mem_size = memparse(str + 10, &str); | |
5f39e670 JM |
3917 | } else if (!strncmp(str, "pcie_bus_tune_off", 17)) { |
3918 | pcie_bus_config = PCIE_BUS_TUNE_OFF; | |
b03e7495 JM |
3919 | } else if (!strncmp(str, "pcie_bus_safe", 13)) { |
3920 | pcie_bus_config = PCIE_BUS_SAFE; | |
3921 | } else if (!strncmp(str, "pcie_bus_perf", 13)) { | |
3922 | pcie_bus_config = PCIE_BUS_PERFORMANCE; | |
5f39e670 JM |
3923 | } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) { |
3924 | pcie_bus_config = PCIE_BUS_PEER2PEER; | |
284f5f9d BH |
3925 | } else if (!strncmp(str, "pcie_scan_all", 13)) { |
3926 | pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS); | |
309e57df MW |
3927 | } else { |
3928 | printk(KERN_ERR "PCI: Unknown option `%s'\n", | |
3929 | str); | |
3930 | } | |
1da177e4 LT |
3931 | } |
3932 | str = k; | |
3933 | } | |
0637a70a | 3934 | return 0; |
1da177e4 | 3935 | } |
0637a70a | 3936 | early_param("pci", pci_setup); |
1da177e4 | 3937 | |
0b62e13b | 3938 | EXPORT_SYMBOL(pci_reenable_device); |
b718989d BH |
3939 | EXPORT_SYMBOL(pci_enable_device_io); |
3940 | EXPORT_SYMBOL(pci_enable_device_mem); | |
1da177e4 | 3941 | EXPORT_SYMBOL(pci_enable_device); |
9ac7849e TH |
3942 | EXPORT_SYMBOL(pcim_enable_device); |
3943 | EXPORT_SYMBOL(pcim_pin_device); | |
1da177e4 | 3944 | EXPORT_SYMBOL(pci_disable_device); |
1da177e4 LT |
3945 | EXPORT_SYMBOL(pci_find_capability); |
3946 | EXPORT_SYMBOL(pci_bus_find_capability); | |
3947 | EXPORT_SYMBOL(pci_release_regions); | |
3948 | EXPORT_SYMBOL(pci_request_regions); | |
e8de1481 | 3949 | EXPORT_SYMBOL(pci_request_regions_exclusive); |
1da177e4 LT |
3950 | EXPORT_SYMBOL(pci_release_region); |
3951 | EXPORT_SYMBOL(pci_request_region); | |
e8de1481 | 3952 | EXPORT_SYMBOL(pci_request_region_exclusive); |
c87deff7 HS |
3953 | EXPORT_SYMBOL(pci_release_selected_regions); |
3954 | EXPORT_SYMBOL(pci_request_selected_regions); | |
e8de1481 | 3955 | EXPORT_SYMBOL(pci_request_selected_regions_exclusive); |
1da177e4 | 3956 | EXPORT_SYMBOL(pci_set_master); |
6a479079 | 3957 | EXPORT_SYMBOL(pci_clear_master); |
1da177e4 | 3958 | EXPORT_SYMBOL(pci_set_mwi); |
694625c0 | 3959 | EXPORT_SYMBOL(pci_try_set_mwi); |
1da177e4 | 3960 | EXPORT_SYMBOL(pci_clear_mwi); |
a04ce0ff | 3961 | EXPORT_SYMBOL_GPL(pci_intx); |
1da177e4 LT |
3962 | EXPORT_SYMBOL(pci_assign_resource); |
3963 | EXPORT_SYMBOL(pci_find_parent_resource); | |
c87deff7 | 3964 | EXPORT_SYMBOL(pci_select_bars); |
1da177e4 LT |
3965 | |
3966 | EXPORT_SYMBOL(pci_set_power_state); | |
3967 | EXPORT_SYMBOL(pci_save_state); | |
3968 | EXPORT_SYMBOL(pci_restore_state); | |
e5899e1b | 3969 | EXPORT_SYMBOL(pci_pme_capable); |
5a6c9b60 | 3970 | EXPORT_SYMBOL(pci_pme_active); |
0235c4fc | 3971 | EXPORT_SYMBOL(pci_wake_from_d3); |
e5899e1b | 3972 | EXPORT_SYMBOL(pci_target_state); |
404cc2d8 RW |
3973 | EXPORT_SYMBOL(pci_prepare_to_sleep); |
3974 | EXPORT_SYMBOL(pci_back_from_sleep); | |
f7bdd12d | 3975 | EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state); |