Commit | Line | Data |
---|---|---|
7d715a6c SL |
1 | /* |
2 | * File: drivers/pci/pcie/aspm.c | |
45e829ea | 3 | * Enabling PCIe link L0s/L1 state and Clock Power Management |
7d715a6c SL |
4 | * |
5 | * Copyright (C) 2007 Intel | |
6 | * Copyright (C) Zhang Yanmin (yanmin.zhang@intel.com) | |
7 | * Copyright (C) Shaohua Li (shaohua.li@intel.com) | |
8 | */ | |
9 | ||
10 | #include <linux/kernel.h> | |
11 | #include <linux/module.h> | |
12 | #include <linux/moduleparam.h> | |
13 | #include <linux/pci.h> | |
14 | #include <linux/pci_regs.h> | |
15 | #include <linux/errno.h> | |
16 | #include <linux/pm.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/slab.h> | |
2a42d9db | 19 | #include <linux/jiffies.h> |
987a4c78 | 20 | #include <linux/delay.h> |
7d715a6c SL |
21 | #include <linux/pci-aspm.h> |
22 | #include "../pci.h" | |
23 | ||
24 | #ifdef MODULE_PARAM_PREFIX | |
25 | #undef MODULE_PARAM_PREFIX | |
26 | #endif | |
27 | #define MODULE_PARAM_PREFIX "pcie_aspm." | |
28 | ||
ac18018a KK |
29 | /* Note: those are not register definitions */ |
30 | #define ASPM_STATE_L0S_UP (1) /* Upstream direction L0s state */ | |
31 | #define ASPM_STATE_L0S_DW (2) /* Downstream direction L0s state */ | |
32 | #define ASPM_STATE_L1 (4) /* L1 state */ | |
33 | #define ASPM_STATE_L0S (ASPM_STATE_L0S_UP | ASPM_STATE_L0S_DW) | |
34 | #define ASPM_STATE_ALL (ASPM_STATE_L0S | ASPM_STATE_L1) | |
35 | ||
b6c2e54d KK |
36 | struct aspm_latency { |
37 | u32 l0s; /* L0s latency (nsec) */ | |
38 | u32 l1; /* L1 latency (nsec) */ | |
7d715a6c SL |
39 | }; |
40 | ||
41 | struct pcie_link_state { | |
5cde89d8 | 42 | struct pci_dev *pdev; /* Upstream component of the Link */ |
5c92ffb1 | 43 | struct pcie_link_state *root; /* pointer to the root port link */ |
5cde89d8 KK |
44 | struct pcie_link_state *parent; /* pointer to the parent Link state */ |
45 | struct list_head sibling; /* node in link_list */ | |
46 | struct list_head children; /* list of child link states */ | |
47 | struct list_head link; /* node in parent's children list */ | |
7d715a6c SL |
48 | |
49 | /* ASPM state */ | |
ac18018a KK |
50 | u32 aspm_support:3; /* Supported ASPM state */ |
51 | u32 aspm_enabled:3; /* Enabled ASPM state */ | |
52 | u32 aspm_capable:3; /* Capable ASPM state with latency */ | |
53 | u32 aspm_default:3; /* Default ASPM state by BIOS */ | |
54 | u32 aspm_disable:3; /* Disabled ASPM state */ | |
80bfdbe3 | 55 | |
4d246e45 KK |
56 | /* Clock PM state */ |
57 | u32 clkpm_capable:1; /* Clock PM capable? */ | |
58 | u32 clkpm_enabled:1; /* Current Clock PM state */ | |
59 | u32 clkpm_default:1; /* Default Clock PM state by BIOS */ | |
60 | ||
ac18018a KK |
61 | /* Exit latencies */ |
62 | struct aspm_latency latency_up; /* Upstream direction exit latency */ | |
63 | struct aspm_latency latency_dw; /* Downstream direction exit latency */ | |
7d715a6c | 64 | /* |
b6c2e54d KK |
65 | * Endpoint acceptable latencies. A pcie downstream port only |
66 | * has one slot under it, so at most there are 8 functions. | |
7d715a6c | 67 | */ |
b6c2e54d | 68 | struct aspm_latency acceptable[8]; |
7d715a6c SL |
69 | }; |
70 | ||
3c076351 | 71 | static int aspm_disabled, aspm_force; |
8b8bae90 | 72 | static bool aspm_support_enabled = true; |
7d715a6c SL |
73 | static DEFINE_MUTEX(aspm_lock); |
74 | static LIST_HEAD(link_list); | |
75 | ||
76 | #define POLICY_DEFAULT 0 /* BIOS default setting */ | |
77 | #define POLICY_PERFORMANCE 1 /* high performance */ | |
78 | #define POLICY_POWERSAVE 2 /* high power saving */ | |
ad71c962 MG |
79 | |
80 | #ifdef CONFIG_PCIEASPM_PERFORMANCE | |
81 | static int aspm_policy = POLICY_PERFORMANCE; | |
82 | #elif defined CONFIG_PCIEASPM_POWERSAVE | |
83 | static int aspm_policy = POLICY_POWERSAVE; | |
84 | #else | |
7d715a6c | 85 | static int aspm_policy; |
ad71c962 MG |
86 | #endif |
87 | ||
7d715a6c SL |
88 | static const char *policy_str[] = { |
89 | [POLICY_DEFAULT] = "default", | |
90 | [POLICY_PERFORMANCE] = "performance", | |
91 | [POLICY_POWERSAVE] = "powersave" | |
92 | }; | |
93 | ||
987a4c78 AP |
94 | #define LINK_RETRAIN_TIMEOUT HZ |
95 | ||
5aa63583 | 96 | static int policy_to_aspm_state(struct pcie_link_state *link) |
7d715a6c | 97 | { |
7d715a6c SL |
98 | switch (aspm_policy) { |
99 | case POLICY_PERFORMANCE: | |
100 | /* Disable ASPM and Clock PM */ | |
101 | return 0; | |
102 | case POLICY_POWERSAVE: | |
103 | /* Enable ASPM L0s/L1 */ | |
ac18018a | 104 | return ASPM_STATE_ALL; |
7d715a6c | 105 | case POLICY_DEFAULT: |
5aa63583 | 106 | return link->aspm_default; |
7d715a6c SL |
107 | } |
108 | return 0; | |
109 | } | |
110 | ||
5aa63583 | 111 | static int policy_to_clkpm_state(struct pcie_link_state *link) |
7d715a6c | 112 | { |
7d715a6c SL |
113 | switch (aspm_policy) { |
114 | case POLICY_PERFORMANCE: | |
115 | /* Disable ASPM and Clock PM */ | |
116 | return 0; | |
117 | case POLICY_POWERSAVE: | |
118 | /* Disable Clock PM */ | |
119 | return 1; | |
120 | case POLICY_DEFAULT: | |
5aa63583 | 121 | return link->clkpm_default; |
7d715a6c SL |
122 | } |
123 | return 0; | |
124 | } | |
125 | ||
430842e2 | 126 | static void pcie_set_clkpm_nocheck(struct pcie_link_state *link, int enable) |
7d715a6c | 127 | { |
5aa63583 KK |
128 | struct pci_dev *child; |
129 | struct pci_bus *linkbus = link->pdev->subordinate; | |
7d715a6c | 130 | |
5aa63583 | 131 | list_for_each_entry(child, &linkbus->devices, bus_list) { |
7d715a6c | 132 | if (enable) |
f12eb72a JL |
133 | pcie_capability_set_word(child, PCI_EXP_LNKCTL, |
134 | PCI_EXP_LNKCTL_CLKREQ_EN); | |
7d715a6c | 135 | else |
f12eb72a JL |
136 | pcie_capability_clear_word(child, PCI_EXP_LNKCTL, |
137 | PCI_EXP_LNKCTL_CLKREQ_EN); | |
7d715a6c | 138 | } |
5aa63583 | 139 | link->clkpm_enabled = !!enable; |
7d715a6c SL |
140 | } |
141 | ||
430842e2 KK |
142 | static void pcie_set_clkpm(struct pcie_link_state *link, int enable) |
143 | { | |
144 | /* Don't enable Clock PM if the link is not Clock PM capable */ | |
145 | if (!link->clkpm_capable && enable) | |
2f671e2d | 146 | enable = 0; |
430842e2 KK |
147 | /* Need nothing if the specified equals to current state */ |
148 | if (link->clkpm_enabled == enable) | |
149 | return; | |
150 | pcie_set_clkpm_nocheck(link, enable); | |
151 | } | |
152 | ||
8d349ace | 153 | static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist) |
7d715a6c | 154 | { |
f12eb72a | 155 | int capable = 1, enabled = 1; |
7d715a6c SL |
156 | u32 reg32; |
157 | u16 reg16; | |
5aa63583 KK |
158 | struct pci_dev *child; |
159 | struct pci_bus *linkbus = link->pdev->subordinate; | |
7d715a6c SL |
160 | |
161 | /* All functions should have the same cap and state, take the worst */ | |
5aa63583 | 162 | list_for_each_entry(child, &linkbus->devices, bus_list) { |
f12eb72a | 163 | pcie_capability_read_dword(child, PCI_EXP_LNKCAP, ®32); |
7d715a6c SL |
164 | if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) { |
165 | capable = 0; | |
166 | enabled = 0; | |
167 | break; | |
168 | } | |
f12eb72a | 169 | pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16); |
7d715a6c SL |
170 | if (!(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN)) |
171 | enabled = 0; | |
172 | } | |
5aa63583 KK |
173 | link->clkpm_enabled = enabled; |
174 | link->clkpm_default = enabled; | |
8d349ace | 175 | link->clkpm_capable = (blacklist) ? 0 : capable; |
46bbdfa4 SL |
176 | } |
177 | ||
7d715a6c SL |
178 | /* |
179 | * pcie_aspm_configure_common_clock: check if the 2 ends of a link | |
180 | * could use common clock. If they are, configure them to use the | |
181 | * common clock. That will reduce the ASPM state exit latency. | |
182 | */ | |
5aa63583 | 183 | static void pcie_aspm_configure_common_clock(struct pcie_link_state *link) |
7d715a6c | 184 | { |
f12eb72a | 185 | int same_clock = 1; |
5aa63583 | 186 | u16 reg16, parent_reg, child_reg[8]; |
2a42d9db | 187 | unsigned long start_jiffies; |
5aa63583 KK |
188 | struct pci_dev *child, *parent = link->pdev; |
189 | struct pci_bus *linkbus = parent->subordinate; | |
7d715a6c | 190 | /* |
5aa63583 | 191 | * All functions of a slot should have the same Slot Clock |
7d715a6c | 192 | * Configuration, so just check one function |
5aa63583 KK |
193 | */ |
194 | child = list_entry(linkbus->devices.next, struct pci_dev, bus_list); | |
8b06477d | 195 | BUG_ON(!pci_is_pcie(child)); |
7d715a6c SL |
196 | |
197 | /* Check downstream component if bit Slot Clock Configuration is 1 */ | |
f12eb72a | 198 | pcie_capability_read_word(child, PCI_EXP_LNKSTA, ®16); |
7d715a6c SL |
199 | if (!(reg16 & PCI_EXP_LNKSTA_SLC)) |
200 | same_clock = 0; | |
201 | ||
202 | /* Check upstream component if bit Slot Clock Configuration is 1 */ | |
f12eb72a | 203 | pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16); |
7d715a6c SL |
204 | if (!(reg16 & PCI_EXP_LNKSTA_SLC)) |
205 | same_clock = 0; | |
206 | ||
207 | /* Configure downstream component, all functions */ | |
5aa63583 | 208 | list_for_each_entry(child, &linkbus->devices, bus_list) { |
f12eb72a | 209 | pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16); |
5aa63583 | 210 | child_reg[PCI_FUNC(child->devfn)] = reg16; |
7d715a6c SL |
211 | if (same_clock) |
212 | reg16 |= PCI_EXP_LNKCTL_CCC; | |
213 | else | |
214 | reg16 &= ~PCI_EXP_LNKCTL_CCC; | |
f12eb72a | 215 | pcie_capability_write_word(child, PCI_EXP_LNKCTL, reg16); |
7d715a6c SL |
216 | } |
217 | ||
218 | /* Configure upstream component */ | |
f12eb72a | 219 | pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16); |
2a42d9db | 220 | parent_reg = reg16; |
7d715a6c SL |
221 | if (same_clock) |
222 | reg16 |= PCI_EXP_LNKCTL_CCC; | |
223 | else | |
224 | reg16 &= ~PCI_EXP_LNKCTL_CCC; | |
f12eb72a | 225 | pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16); |
7d715a6c | 226 | |
5aa63583 | 227 | /* Retrain link */ |
7d715a6c | 228 | reg16 |= PCI_EXP_LNKCTL_RL; |
f12eb72a | 229 | pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16); |
7d715a6c | 230 | |
5aa63583 | 231 | /* Wait for link training end. Break out after waiting for timeout */ |
2a42d9db | 232 | start_jiffies = jiffies; |
987a4c78 | 233 | for (;;) { |
f12eb72a | 234 | pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16); |
7d715a6c SL |
235 | if (!(reg16 & PCI_EXP_LNKSTA_LT)) |
236 | break; | |
987a4c78 AP |
237 | if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT)) |
238 | break; | |
239 | msleep(1); | |
7d715a6c | 240 | } |
5aa63583 KK |
241 | if (!(reg16 & PCI_EXP_LNKSTA_LT)) |
242 | return; | |
243 | ||
244 | /* Training failed. Restore common clock configurations */ | |
438be3c6 | 245 | dev_err(&parent->dev, "ASPM: Could not configure common clock\n"); |
f12eb72a JL |
246 | list_for_each_entry(child, &linkbus->devices, bus_list) |
247 | pcie_capability_write_word(child, PCI_EXP_LNKCTL, | |
248 | child_reg[PCI_FUNC(child->devfn)]); | |
249 | pcie_capability_write_word(parent, PCI_EXP_LNKCTL, parent_reg); | |
7d715a6c SL |
250 | } |
251 | ||
5e0eaa7d KK |
252 | /* Convert L0s latency encoding to ns */ |
253 | static u32 calc_l0s_latency(u32 encoding) | |
7d715a6c | 254 | { |
5e0eaa7d KK |
255 | if (encoding == 0x7) |
256 | return (5 * 1000); /* > 4us */ | |
257 | return (64 << encoding); | |
258 | } | |
7d715a6c | 259 | |
5e0eaa7d KK |
260 | /* Convert L0s acceptable latency encoding to ns */ |
261 | static u32 calc_l0s_acceptable(u32 encoding) | |
262 | { | |
263 | if (encoding == 0x7) | |
264 | return -1U; | |
265 | return (64 << encoding); | |
7d715a6c SL |
266 | } |
267 | ||
5e0eaa7d KK |
268 | /* Convert L1 latency encoding to ns */ |
269 | static u32 calc_l1_latency(u32 encoding) | |
7d715a6c | 270 | { |
5e0eaa7d KK |
271 | if (encoding == 0x7) |
272 | return (65 * 1000); /* > 64us */ | |
273 | return (1000 << encoding); | |
274 | } | |
7d715a6c | 275 | |
5e0eaa7d KK |
276 | /* Convert L1 acceptable latency encoding to ns */ |
277 | static u32 calc_l1_acceptable(u32 encoding) | |
278 | { | |
279 | if (encoding == 0x7) | |
280 | return -1U; | |
281 | return (1000 << encoding); | |
7d715a6c SL |
282 | } |
283 | ||
ac18018a KK |
284 | struct aspm_register_info { |
285 | u32 support:2; | |
286 | u32 enabled:2; | |
287 | u32 latency_encoding_l0s; | |
288 | u32 latency_encoding_l1; | |
289 | }; | |
290 | ||
291 | static void pcie_get_aspm_reg(struct pci_dev *pdev, | |
292 | struct aspm_register_info *info) | |
7d715a6c | 293 | { |
7d715a6c | 294 | u16 reg16; |
ac18018a | 295 | u32 reg32; |
7d715a6c | 296 | |
f12eb72a | 297 | pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, ®32); |
ac18018a | 298 | info->support = (reg32 & PCI_EXP_LNKCAP_ASPMS) >> 10; |
ac18018a KK |
299 | info->latency_encoding_l0s = (reg32 & PCI_EXP_LNKCAP_L0SEL) >> 12; |
300 | info->latency_encoding_l1 = (reg32 & PCI_EXP_LNKCAP_L1EL) >> 15; | |
f12eb72a | 301 | pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, ®16); |
ac18018a | 302 | info->enabled = reg16 & PCI_EXP_LNKCTL_ASPMC; |
7d715a6c SL |
303 | } |
304 | ||
07d92760 KK |
305 | static void pcie_aspm_check_latency(struct pci_dev *endpoint) |
306 | { | |
ac18018a | 307 | u32 latency, l1_switch_latency = 0; |
07d92760 KK |
308 | struct aspm_latency *acceptable; |
309 | struct pcie_link_state *link; | |
310 | ||
311 | /* Device not in D0 doesn't need latency check */ | |
312 | if ((endpoint->current_state != PCI_D0) && | |
313 | (endpoint->current_state != PCI_UNKNOWN)) | |
314 | return; | |
315 | ||
316 | link = endpoint->bus->self->link_state; | |
317 | acceptable = &link->acceptable[PCI_FUNC(endpoint->devfn)]; | |
318 | ||
319 | while (link) { | |
ac18018a KK |
320 | /* Check upstream direction L0s latency */ |
321 | if ((link->aspm_capable & ASPM_STATE_L0S_UP) && | |
322 | (link->latency_up.l0s > acceptable->l0s)) | |
323 | link->aspm_capable &= ~ASPM_STATE_L0S_UP; | |
324 | ||
325 | /* Check downstream direction L0s latency */ | |
326 | if ((link->aspm_capable & ASPM_STATE_L0S_DW) && | |
327 | (link->latency_dw.l0s > acceptable->l0s)) | |
328 | link->aspm_capable &= ~ASPM_STATE_L0S_DW; | |
07d92760 KK |
329 | /* |
330 | * Check L1 latency. | |
331 | * Every switch on the path to root complex need 1 | |
332 | * more microsecond for L1. Spec doesn't mention L0s. | |
333 | */ | |
ac18018a KK |
334 | latency = max_t(u32, link->latency_up.l1, link->latency_dw.l1); |
335 | if ((link->aspm_capable & ASPM_STATE_L1) && | |
336 | (latency + l1_switch_latency > acceptable->l1)) | |
337 | link->aspm_capable &= ~ASPM_STATE_L1; | |
07d92760 KK |
338 | l1_switch_latency += 1000; |
339 | ||
340 | link = link->parent; | |
341 | } | |
342 | } | |
343 | ||
8d349ace | 344 | static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) |
7d715a6c | 345 | { |
5aa63583 KK |
346 | struct pci_dev *child, *parent = link->pdev; |
347 | struct pci_bus *linkbus = parent->subordinate; | |
ac18018a | 348 | struct aspm_register_info upreg, dwreg; |
7d715a6c | 349 | |
8d349ace | 350 | if (blacklist) { |
f1c0ca29 | 351 | /* Set enabled/disable so that we will disable ASPM later */ |
ac18018a KK |
352 | link->aspm_enabled = ASPM_STATE_ALL; |
353 | link->aspm_disable = ASPM_STATE_ALL; | |
8d349ace KK |
354 | return; |
355 | } | |
356 | ||
357 | /* Configure common clock before checking latencies */ | |
358 | pcie_aspm_configure_common_clock(link); | |
359 | ||
ac18018a KK |
360 | /* Get upstream/downstream components' register state */ |
361 | pcie_get_aspm_reg(parent, &upreg); | |
5aa63583 | 362 | child = list_entry(linkbus->devices.next, struct pci_dev, bus_list); |
ac18018a KK |
363 | pcie_get_aspm_reg(child, &dwreg); |
364 | ||
365 | /* | |
366 | * Setup L0s state | |
367 | * | |
368 | * Note that we must not enable L0s in either direction on a | |
369 | * given link unless components on both sides of the link each | |
370 | * support L0s. | |
371 | */ | |
372 | if (dwreg.support & upreg.support & PCIE_LINK_STATE_L0S) | |
373 | link->aspm_support |= ASPM_STATE_L0S; | |
374 | if (dwreg.enabled & PCIE_LINK_STATE_L0S) | |
375 | link->aspm_enabled |= ASPM_STATE_L0S_UP; | |
376 | if (upreg.enabled & PCIE_LINK_STATE_L0S) | |
377 | link->aspm_enabled |= ASPM_STATE_L0S_DW; | |
378 | link->latency_up.l0s = calc_l0s_latency(upreg.latency_encoding_l0s); | |
379 | link->latency_dw.l0s = calc_l0s_latency(dwreg.latency_encoding_l0s); | |
380 | ||
381 | /* Setup L1 state */ | |
382 | if (upreg.support & dwreg.support & PCIE_LINK_STATE_L1) | |
383 | link->aspm_support |= ASPM_STATE_L1; | |
384 | if (upreg.enabled & dwreg.enabled & PCIE_LINK_STATE_L1) | |
385 | link->aspm_enabled |= ASPM_STATE_L1; | |
386 | link->latency_up.l1 = calc_l1_latency(upreg.latency_encoding_l1); | |
387 | link->latency_dw.l1 = calc_l1_latency(dwreg.latency_encoding_l1); | |
5aa63583 | 388 | |
b127bd55 KK |
389 | /* Save default state */ |
390 | link->aspm_default = link->aspm_enabled; | |
07d92760 KK |
391 | |
392 | /* Setup initial capable state. Will be updated later */ | |
393 | link->aspm_capable = link->aspm_support; | |
f1c0ca29 KK |
394 | /* |
395 | * If the downstream component has pci bridge function, don't | |
396 | * do ASPM for now. | |
397 | */ | |
398 | list_for_each_entry(child, &linkbus->devices, bus_list) { | |
62f87c0e | 399 | if (pci_pcie_type(child) == PCI_EXP_TYPE_PCI_BRIDGE) { |
ac18018a | 400 | link->aspm_disable = ASPM_STATE_ALL; |
f1c0ca29 KK |
401 | break; |
402 | } | |
403 | } | |
b127bd55 | 404 | |
b7206cbf | 405 | /* Get and check endpoint acceptable latencies */ |
5aa63583 | 406 | list_for_each_entry(child, &linkbus->devices, bus_list) { |
5e0eaa7d | 407 | u32 reg32, encoding; |
b6c2e54d | 408 | struct aspm_latency *acceptable = |
5aa63583 | 409 | &link->acceptable[PCI_FUNC(child->devfn)]; |
7d715a6c | 410 | |
62f87c0e YW |
411 | if (pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT && |
412 | pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END) | |
7d715a6c SL |
413 | continue; |
414 | ||
f12eb72a | 415 | pcie_capability_read_dword(child, PCI_EXP_DEVCAP, ®32); |
07d92760 | 416 | /* Calculate endpoint L0s acceptable latency */ |
5e0eaa7d KK |
417 | encoding = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6; |
418 | acceptable->l0s = calc_l0s_acceptable(encoding); | |
07d92760 KK |
419 | /* Calculate endpoint L1 acceptable latency */ |
420 | encoding = (reg32 & PCI_EXP_DEVCAP_L1) >> 9; | |
421 | acceptable->l1 = calc_l1_acceptable(encoding); | |
422 | ||
423 | pcie_aspm_check_latency(child); | |
7d715a6c SL |
424 | } |
425 | } | |
426 | ||
ac18018a | 427 | static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val) |
7d715a6c | 428 | { |
75083206 BH |
429 | pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL, |
430 | PCI_EXP_LNKCTL_ASPMC, val); | |
7d715a6c SL |
431 | } |
432 | ||
b7206cbf | 433 | static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state) |
7d715a6c | 434 | { |
ac18018a | 435 | u32 upstream = 0, dwstream = 0; |
5aa63583 KK |
436 | struct pci_dev *child, *parent = link->pdev; |
437 | struct pci_bus *linkbus = parent->subordinate; | |
7d715a6c | 438 | |
f1c0ca29 | 439 | /* Nothing to do if the link is already in the requested state */ |
b7206cbf | 440 | state &= (link->aspm_capable & ~link->aspm_disable); |
f1c0ca29 KK |
441 | if (link->aspm_enabled == state) |
442 | return; | |
ac18018a KK |
443 | /* Convert ASPM state to upstream/downstream ASPM register state */ |
444 | if (state & ASPM_STATE_L0S_UP) | |
75083206 | 445 | dwstream |= PCI_EXP_LNKCTL_ASPM_L0S; |
ac18018a | 446 | if (state & ASPM_STATE_L0S_DW) |
75083206 | 447 | upstream |= PCI_EXP_LNKCTL_ASPM_L0S; |
ac18018a | 448 | if (state & ASPM_STATE_L1) { |
75083206 BH |
449 | upstream |= PCI_EXP_LNKCTL_ASPM_L1; |
450 | dwstream |= PCI_EXP_LNKCTL_ASPM_L1; | |
ac18018a | 451 | } |
7d715a6c | 452 | /* |
5aa63583 KK |
453 | * Spec 2.0 suggests all functions should be configured the |
454 | * same setting for ASPM. Enabling ASPM L1 should be done in | |
455 | * upstream component first and then downstream, and vice | |
456 | * versa for disabling ASPM L1. Spec doesn't mention L0S. | |
7d715a6c | 457 | */ |
ac18018a KK |
458 | if (state & ASPM_STATE_L1) |
459 | pcie_config_aspm_dev(parent, upstream); | |
5aa63583 | 460 | list_for_each_entry(child, &linkbus->devices, bus_list) |
ac18018a KK |
461 | pcie_config_aspm_dev(child, dwstream); |
462 | if (!(state & ASPM_STATE_L1)) | |
463 | pcie_config_aspm_dev(parent, upstream); | |
7d715a6c | 464 | |
5aa63583 | 465 | link->aspm_enabled = state; |
7d715a6c SL |
466 | } |
467 | ||
b7206cbf | 468 | static void pcie_config_aspm_path(struct pcie_link_state *link) |
7d715a6c | 469 | { |
b7206cbf KK |
470 | while (link) { |
471 | pcie_config_aspm_link(link, policy_to_aspm_state(link)); | |
472 | link = link->parent; | |
46bbdfa4 | 473 | } |
7d715a6c SL |
474 | } |
475 | ||
5aa63583 | 476 | static void free_link_state(struct pcie_link_state *link) |
7d715a6c | 477 | { |
5aa63583 KK |
478 | link->pdev->link_state = NULL; |
479 | kfree(link); | |
7d715a6c SL |
480 | } |
481 | ||
ddc9753f SL |
482 | static int pcie_aspm_sanity_check(struct pci_dev *pdev) |
483 | { | |
3647584d | 484 | struct pci_dev *child; |
149e1637 | 485 | u32 reg32; |
2f671e2d | 486 | |
ddc9753f | 487 | /* |
45e829ea | 488 | * Some functions in a slot might not all be PCIe functions, |
3647584d | 489 | * very strange. Disable ASPM for the whole slot |
ddc9753f | 490 | */ |
3647584d | 491 | list_for_each_entry(child, &pdev->subordinate->devices, bus_list) { |
f12eb72a | 492 | if (!pci_is_pcie(child)) |
ddc9753f | 493 | return -EINVAL; |
c9651e70 MG |
494 | |
495 | /* | |
496 | * If ASPM is disabled then we're not going to change | |
497 | * the BIOS state. It's safe to continue even if it's a | |
498 | * pre-1.1 device | |
499 | */ | |
500 | ||
501 | if (aspm_disabled) | |
502 | continue; | |
503 | ||
149e1637 SL |
504 | /* |
505 | * Disable ASPM for pre-1.1 PCIe device, we follow MS to use | |
506 | * RBER bit to determine if a function is 1.1 version device | |
507 | */ | |
f12eb72a | 508 | pcie_capability_read_dword(child, PCI_EXP_DEVCAP, ®32); |
e1f4f59d | 509 | if (!(reg32 & PCI_EXP_DEVCAP_RBER) && !aspm_force) { |
438be3c6 | 510 | dev_info(&child->dev, "disabling ASPM on pre-1.1 PCIe device. You can enable it with 'pcie_aspm=force'\n"); |
149e1637 SL |
511 | return -EINVAL; |
512 | } | |
ddc9753f SL |
513 | } |
514 | return 0; | |
515 | } | |
516 | ||
b7206cbf | 517 | static struct pcie_link_state *alloc_pcie_link_state(struct pci_dev *pdev) |
8d349ace KK |
518 | { |
519 | struct pcie_link_state *link; | |
8d349ace KK |
520 | |
521 | link = kzalloc(sizeof(*link), GFP_KERNEL); | |
522 | if (!link) | |
523 | return NULL; | |
524 | INIT_LIST_HEAD(&link->sibling); | |
525 | INIT_LIST_HEAD(&link->children); | |
526 | INIT_LIST_HEAD(&link->link); | |
527 | link->pdev = pdev; | |
62f87c0e | 528 | if (pci_pcie_type(pdev) == PCI_EXP_TYPE_DOWNSTREAM) { |
8d349ace KK |
529 | struct pcie_link_state *parent; |
530 | parent = pdev->bus->parent->self->link_state; | |
531 | if (!parent) { | |
532 | kfree(link); | |
533 | return NULL; | |
534 | } | |
535 | link->parent = parent; | |
536 | list_add(&link->link, &parent->children); | |
537 | } | |
5c92ffb1 KK |
538 | /* Setup a pointer to the root port link */ |
539 | if (!link->parent) | |
540 | link->root = link; | |
541 | else | |
542 | link->root = link->parent->root; | |
543 | ||
8d349ace | 544 | list_add(&link->sibling, &link_list); |
8d349ace | 545 | pdev->link_state = link; |
8d349ace KK |
546 | return link; |
547 | } | |
548 | ||
7d715a6c SL |
549 | /* |
550 | * pcie_aspm_init_link_state: Initiate PCI express link state. | |
551 | * It is called after the pcie and its children devices are scaned. | |
552 | * @pdev: the root port or switch downstream port | |
553 | */ | |
554 | void pcie_aspm_init_link_state(struct pci_dev *pdev) | |
555 | { | |
8d349ace | 556 | struct pcie_link_state *link; |
b7206cbf | 557 | int blacklist = !!pcie_aspm_sanity_check(pdev); |
7d715a6c | 558 | |
a26d5ecb JL |
559 | if (!aspm_support_enabled) |
560 | return; | |
561 | ||
2f671e2d | 562 | if (!pci_is_pcie(pdev) || pdev->link_state) |
7d715a6c | 563 | return; |
62f87c0e YW |
564 | if (pci_pcie_type(pdev) != PCI_EXP_TYPE_ROOT_PORT && |
565 | pci_pcie_type(pdev) != PCI_EXP_TYPE_DOWNSTREAM) | |
7d715a6c | 566 | return; |
8d349ace | 567 | |
8e822df7 | 568 | /* VIA has a strange chipset, root port is under a bridge */ |
62f87c0e | 569 | if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT && |
8d349ace | 570 | pdev->bus->self) |
8e822df7 | 571 | return; |
8d349ace | 572 | |
7d715a6c SL |
573 | down_read(&pci_bus_sem); |
574 | if (list_empty(&pdev->subordinate->devices)) | |
575 | goto out; | |
576 | ||
577 | mutex_lock(&aspm_lock); | |
b7206cbf | 578 | link = alloc_pcie_link_state(pdev); |
8d349ace KK |
579 | if (!link) |
580 | goto unlock; | |
581 | /* | |
b7206cbf KK |
582 | * Setup initial ASPM state. Note that we need to configure |
583 | * upstream links also because capable state of them can be | |
584 | * update through pcie_aspm_cap_init(). | |
8d349ace | 585 | */ |
b7206cbf | 586 | pcie_aspm_cap_init(link, blacklist); |
7d715a6c | 587 | |
8d349ace | 588 | /* Setup initial Clock PM state */ |
b7206cbf | 589 | pcie_clkpm_cap_init(link, blacklist); |
41cd766b MG |
590 | |
591 | /* | |
592 | * At this stage drivers haven't had an opportunity to change the | |
593 | * link policy setting. Enabling ASPM on broken hardware can cripple | |
594 | * it even before the driver has had a chance to disable ASPM, so | |
595 | * default to a safe level right now. If we're enabling ASPM beyond | |
596 | * the BIOS's expectation, we'll do so once pci_enable_device() is | |
597 | * called. | |
598 | */ | |
3c076351 | 599 | if (aspm_policy != POLICY_POWERSAVE) { |
41cd766b MG |
600 | pcie_config_aspm_path(link); |
601 | pcie_set_clkpm(link, policy_to_clkpm_state(link)); | |
602 | } | |
603 | ||
8d349ace | 604 | unlock: |
7d715a6c SL |
605 | mutex_unlock(&aspm_lock); |
606 | out: | |
607 | up_read(&pci_bus_sem); | |
608 | } | |
609 | ||
07d92760 KK |
610 | /* Recheck latencies and update aspm_capable for links under the root */ |
611 | static void pcie_update_aspm_capable(struct pcie_link_state *root) | |
612 | { | |
613 | struct pcie_link_state *link; | |
614 | BUG_ON(root->parent); | |
615 | list_for_each_entry(link, &link_list, sibling) { | |
616 | if (link->root != root) | |
617 | continue; | |
618 | link->aspm_capable = link->aspm_support; | |
619 | } | |
620 | list_for_each_entry(link, &link_list, sibling) { | |
621 | struct pci_dev *child; | |
622 | struct pci_bus *linkbus = link->pdev->subordinate; | |
623 | if (link->root != root) | |
624 | continue; | |
625 | list_for_each_entry(child, &linkbus->devices, bus_list) { | |
62f87c0e YW |
626 | if ((pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT) && |
627 | (pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END)) | |
07d92760 KK |
628 | continue; |
629 | pcie_aspm_check_latency(child); | |
630 | } | |
631 | } | |
632 | } | |
633 | ||
7d715a6c SL |
634 | /* @pdev: the endpoint device */ |
635 | void pcie_aspm_exit_link_state(struct pci_dev *pdev) | |
636 | { | |
637 | struct pci_dev *parent = pdev->bus->self; | |
b7206cbf | 638 | struct pcie_link_state *link, *root, *parent_link; |
7d715a6c | 639 | |
84fb913c | 640 | if (!parent || !parent->link_state) |
7d715a6c | 641 | return; |
fc87e919 | 642 | |
7d715a6c SL |
643 | down_read(&pci_bus_sem); |
644 | mutex_lock(&aspm_lock); | |
7d715a6c SL |
645 | /* |
646 | * All PCIe functions are in one slot, remove one function will remove | |
3419c75e | 647 | * the whole slot, so just wait until we are the last function left. |
7d715a6c | 648 | */ |
3419c75e | 649 | if (!list_is_last(&pdev->bus_list, &parent->subordinate->devices)) |
7d715a6c SL |
650 | goto out; |
651 | ||
fc87e919 | 652 | link = parent->link_state; |
07d92760 | 653 | root = link->root; |
b7206cbf | 654 | parent_link = link->parent; |
fc87e919 | 655 | |
7d715a6c | 656 | /* All functions are removed, so just disable ASPM for the link */ |
b7206cbf | 657 | pcie_config_aspm_link(link, 0); |
fc87e919 KK |
658 | list_del(&link->sibling); |
659 | list_del(&link->link); | |
7d715a6c | 660 | /* Clock PM is for endpoint device */ |
fc87e919 | 661 | free_link_state(link); |
07d92760 KK |
662 | |
663 | /* Recheck latencies and configure upstream links */ | |
b26a34aa KK |
664 | if (parent_link) { |
665 | pcie_update_aspm_capable(root); | |
666 | pcie_config_aspm_path(parent_link); | |
667 | } | |
7d715a6c SL |
668 | out: |
669 | mutex_unlock(&aspm_lock); | |
670 | up_read(&pci_bus_sem); | |
671 | } | |
672 | ||
673 | /* @pdev: the root port or switch downstream port */ | |
674 | void pcie_aspm_pm_state_change(struct pci_dev *pdev) | |
675 | { | |
07d92760 | 676 | struct pcie_link_state *link = pdev->link_state; |
7d715a6c | 677 | |
8b06477d | 678 | if (aspm_disabled || !pci_is_pcie(pdev) || !link) |
7d715a6c | 679 | return; |
62f87c0e YW |
680 | if ((pci_pcie_type(pdev) != PCI_EXP_TYPE_ROOT_PORT) && |
681 | (pci_pcie_type(pdev) != PCI_EXP_TYPE_DOWNSTREAM)) | |
7d715a6c SL |
682 | return; |
683 | /* | |
07d92760 KK |
684 | * Devices changed PM state, we should recheck if latency |
685 | * meets all functions' requirement | |
7d715a6c | 686 | */ |
07d92760 KK |
687 | down_read(&pci_bus_sem); |
688 | mutex_lock(&aspm_lock); | |
689 | pcie_update_aspm_capable(link->root); | |
b7206cbf | 690 | pcie_config_aspm_path(link); |
07d92760 KK |
691 | mutex_unlock(&aspm_lock); |
692 | up_read(&pci_bus_sem); | |
7d715a6c SL |
693 | } |
694 | ||
1a680b7c NC |
695 | void pcie_aspm_powersave_config_link(struct pci_dev *pdev) |
696 | { | |
697 | struct pcie_link_state *link = pdev->link_state; | |
698 | ||
699 | if (aspm_disabled || !pci_is_pcie(pdev) || !link) | |
700 | return; | |
701 | ||
702 | if (aspm_policy != POLICY_POWERSAVE) | |
703 | return; | |
704 | ||
62f87c0e YW |
705 | if ((pci_pcie_type(pdev) != PCI_EXP_TYPE_ROOT_PORT) && |
706 | (pci_pcie_type(pdev) != PCI_EXP_TYPE_DOWNSTREAM)) | |
1a680b7c NC |
707 | return; |
708 | ||
709 | down_read(&pci_bus_sem); | |
710 | mutex_lock(&aspm_lock); | |
711 | pcie_config_aspm_path(link); | |
712 | pcie_set_clkpm(link, policy_to_clkpm_state(link)); | |
713 | mutex_unlock(&aspm_lock); | |
714 | up_read(&pci_bus_sem); | |
715 | } | |
716 | ||
3c076351 MG |
717 | static void __pci_disable_link_state(struct pci_dev *pdev, int state, bool sem, |
718 | bool force) | |
7d715a6c SL |
719 | { |
720 | struct pci_dev *parent = pdev->bus->self; | |
f1c0ca29 | 721 | struct pcie_link_state *link; |
7d715a6c | 722 | |
3c076351 | 723 | if (!pci_is_pcie(pdev)) |
7d715a6c | 724 | return; |
3c076351 | 725 | |
62f87c0e YW |
726 | if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT || |
727 | pci_pcie_type(pdev) == PCI_EXP_TYPE_DOWNSTREAM) | |
7d715a6c SL |
728 | parent = pdev; |
729 | if (!parent || !parent->link_state) | |
730 | return; | |
731 | ||
2add0ec1 BH |
732 | /* |
733 | * A driver requested that ASPM be disabled on this device, but | |
734 | * if we don't have permission to manage ASPM (e.g., on ACPI | |
735 | * systems we have to observe the FADT ACPI_FADT_NO_ASPM bit and | |
736 | * the _OSC method), we can't honor that request. Windows has | |
737 | * a similar mechanism using "PciASPMOptOut", which is also | |
738 | * ignored in this situation. | |
739 | */ | |
740 | if (aspm_disabled && !force) { | |
741 | dev_warn(&pdev->dev, "can't disable ASPM; OS doesn't have ASPM control\n"); | |
742 | return; | |
743 | } | |
744 | ||
9f728f53 YL |
745 | if (sem) |
746 | down_read(&pci_bus_sem); | |
7d715a6c | 747 | mutex_lock(&aspm_lock); |
f1c0ca29 | 748 | link = parent->link_state; |
ac18018a KK |
749 | if (state & PCIE_LINK_STATE_L0S) |
750 | link->aspm_disable |= ASPM_STATE_L0S; | |
751 | if (state & PCIE_LINK_STATE_L1) | |
752 | link->aspm_disable |= ASPM_STATE_L1; | |
b7206cbf KK |
753 | pcie_config_aspm_link(link, policy_to_aspm_state(link)); |
754 | ||
430842e2 | 755 | if (state & PCIE_LINK_STATE_CLKPM) { |
f1c0ca29 KK |
756 | link->clkpm_capable = 0; |
757 | pcie_set_clkpm(link, 0); | |
430842e2 | 758 | } |
7d715a6c | 759 | mutex_unlock(&aspm_lock); |
9f728f53 YL |
760 | if (sem) |
761 | up_read(&pci_bus_sem); | |
762 | } | |
763 | ||
764 | void pci_disable_link_state_locked(struct pci_dev *pdev, int state) | |
765 | { | |
3c076351 | 766 | __pci_disable_link_state(pdev, state, false, false); |
9f728f53 YL |
767 | } |
768 | EXPORT_SYMBOL(pci_disable_link_state_locked); | |
769 | ||
2dfca877 YW |
770 | /** |
771 | * pci_disable_link_state - Disable device's link state, so the link will | |
772 | * never enter specific states. Note that if the BIOS didn't grant ASPM | |
773 | * control to the OS, this does nothing because we can't touch the LNKCTL | |
774 | * register. | |
775 | * | |
776 | * @pdev: PCI device | |
777 | * @state: ASPM link state to disable | |
778 | */ | |
9f728f53 YL |
779 | void pci_disable_link_state(struct pci_dev *pdev, int state) |
780 | { | |
3c076351 | 781 | __pci_disable_link_state(pdev, state, true, false); |
7d715a6c SL |
782 | } |
783 | EXPORT_SYMBOL(pci_disable_link_state); | |
784 | ||
3c076351 MG |
785 | void pcie_clear_aspm(struct pci_bus *bus) |
786 | { | |
787 | struct pci_dev *child; | |
788 | ||
9e167214 CIK |
789 | if (aspm_force) |
790 | return; | |
791 | ||
3c076351 MG |
792 | /* |
793 | * Clear any ASPM setup that the firmware has carried out on this bus | |
794 | */ | |
795 | list_for_each_entry(child, &bus->devices, bus_list) { | |
796 | __pci_disable_link_state(child, PCIE_LINK_STATE_L0S | | |
797 | PCIE_LINK_STATE_L1 | | |
798 | PCIE_LINK_STATE_CLKPM, | |
799 | false, true); | |
800 | } | |
801 | } | |
802 | ||
7d715a6c SL |
803 | static int pcie_aspm_set_policy(const char *val, struct kernel_param *kp) |
804 | { | |
805 | int i; | |
b7206cbf | 806 | struct pcie_link_state *link; |
7d715a6c | 807 | |
bbfa306a NC |
808 | if (aspm_disabled) |
809 | return -EPERM; | |
7d715a6c SL |
810 | for (i = 0; i < ARRAY_SIZE(policy_str); i++) |
811 | if (!strncmp(val, policy_str[i], strlen(policy_str[i]))) | |
812 | break; | |
813 | if (i >= ARRAY_SIZE(policy_str)) | |
814 | return -EINVAL; | |
815 | if (i == aspm_policy) | |
816 | return 0; | |
817 | ||
818 | down_read(&pci_bus_sem); | |
819 | mutex_lock(&aspm_lock); | |
820 | aspm_policy = i; | |
b7206cbf KK |
821 | list_for_each_entry(link, &link_list, sibling) { |
822 | pcie_config_aspm_link(link, policy_to_aspm_state(link)); | |
823 | pcie_set_clkpm(link, policy_to_clkpm_state(link)); | |
7d715a6c SL |
824 | } |
825 | mutex_unlock(&aspm_lock); | |
826 | up_read(&pci_bus_sem); | |
827 | return 0; | |
828 | } | |
829 | ||
830 | static int pcie_aspm_get_policy(char *buffer, struct kernel_param *kp) | |
831 | { | |
832 | int i, cnt = 0; | |
833 | for (i = 0; i < ARRAY_SIZE(policy_str); i++) | |
834 | if (i == aspm_policy) | |
835 | cnt += sprintf(buffer + cnt, "[%s] ", policy_str[i]); | |
836 | else | |
837 | cnt += sprintf(buffer + cnt, "%s ", policy_str[i]); | |
838 | return cnt; | |
839 | } | |
840 | ||
841 | module_param_call(policy, pcie_aspm_set_policy, pcie_aspm_get_policy, | |
842 | NULL, 0644); | |
843 | ||
844 | #ifdef CONFIG_PCIEASPM_DEBUG | |
845 | static ssize_t link_state_show(struct device *dev, | |
846 | struct device_attribute *attr, | |
847 | char *buf) | |
848 | { | |
849 | struct pci_dev *pci_device = to_pci_dev(dev); | |
850 | struct pcie_link_state *link_state = pci_device->link_state; | |
851 | ||
80bfdbe3 | 852 | return sprintf(buf, "%d\n", link_state->aspm_enabled); |
7d715a6c SL |
853 | } |
854 | ||
855 | static ssize_t link_state_store(struct device *dev, | |
856 | struct device_attribute *attr, | |
857 | const char *buf, | |
858 | size_t n) | |
859 | { | |
5aa63583 | 860 | struct pci_dev *pdev = to_pci_dev(dev); |
b7206cbf | 861 | struct pcie_link_state *link, *root = pdev->link_state->root; |
ac18018a | 862 | u32 val = buf[0] - '0', state = 0; |
7d715a6c | 863 | |
bbfa306a NC |
864 | if (aspm_disabled) |
865 | return -EPERM; | |
ac18018a | 866 | if (n < 1 || val > 3) |
7d715a6c | 867 | return -EINVAL; |
7d715a6c | 868 | |
ac18018a KK |
869 | /* Convert requested state to ASPM state */ |
870 | if (val & PCIE_LINK_STATE_L0S) | |
871 | state |= ASPM_STATE_L0S; | |
872 | if (val & PCIE_LINK_STATE_L1) | |
873 | state |= ASPM_STATE_L1; | |
874 | ||
b7206cbf KK |
875 | down_read(&pci_bus_sem); |
876 | mutex_lock(&aspm_lock); | |
877 | list_for_each_entry(link, &link_list, sibling) { | |
878 | if (link->root != root) | |
879 | continue; | |
880 | pcie_config_aspm_link(link, state); | |
881 | } | |
882 | mutex_unlock(&aspm_lock); | |
883 | up_read(&pci_bus_sem); | |
884 | return n; | |
7d715a6c SL |
885 | } |
886 | ||
887 | static ssize_t clk_ctl_show(struct device *dev, | |
888 | struct device_attribute *attr, | |
889 | char *buf) | |
890 | { | |
891 | struct pci_dev *pci_device = to_pci_dev(dev); | |
892 | struct pcie_link_state *link_state = pci_device->link_state; | |
893 | ||
4d246e45 | 894 | return sprintf(buf, "%d\n", link_state->clkpm_enabled); |
7d715a6c SL |
895 | } |
896 | ||
897 | static ssize_t clk_ctl_store(struct device *dev, | |
898 | struct device_attribute *attr, | |
899 | const char *buf, | |
900 | size_t n) | |
901 | { | |
430842e2 | 902 | struct pci_dev *pdev = to_pci_dev(dev); |
7d715a6c SL |
903 | int state; |
904 | ||
905 | if (n < 1) | |
906 | return -EINVAL; | |
907 | state = buf[0]-'0'; | |
908 | ||
909 | down_read(&pci_bus_sem); | |
910 | mutex_lock(&aspm_lock); | |
430842e2 | 911 | pcie_set_clkpm_nocheck(pdev->link_state, !!state); |
7d715a6c SL |
912 | mutex_unlock(&aspm_lock); |
913 | up_read(&pci_bus_sem); | |
914 | ||
915 | return n; | |
916 | } | |
917 | ||
918 | static DEVICE_ATTR(link_state, 0644, link_state_show, link_state_store); | |
919 | static DEVICE_ATTR(clk_ctl, 0644, clk_ctl_show, clk_ctl_store); | |
920 | ||
921 | static char power_group[] = "power"; | |
922 | void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev) | |
923 | { | |
924 | struct pcie_link_state *link_state = pdev->link_state; | |
925 | ||
8b06477d | 926 | if (!pci_is_pcie(pdev) || |
62f87c0e YW |
927 | (pci_pcie_type(pdev) != PCI_EXP_TYPE_ROOT_PORT && |
928 | pci_pcie_type(pdev) != PCI_EXP_TYPE_DOWNSTREAM) || !link_state) | |
7d715a6c SL |
929 | return; |
930 | ||
80bfdbe3 | 931 | if (link_state->aspm_support) |
7d715a6c SL |
932 | sysfs_add_file_to_group(&pdev->dev.kobj, |
933 | &dev_attr_link_state.attr, power_group); | |
4d246e45 | 934 | if (link_state->clkpm_capable) |
7d715a6c SL |
935 | sysfs_add_file_to_group(&pdev->dev.kobj, |
936 | &dev_attr_clk_ctl.attr, power_group); | |
937 | } | |
938 | ||
939 | void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev) | |
940 | { | |
941 | struct pcie_link_state *link_state = pdev->link_state; | |
942 | ||
8b06477d | 943 | if (!pci_is_pcie(pdev) || |
62f87c0e YW |
944 | (pci_pcie_type(pdev) != PCI_EXP_TYPE_ROOT_PORT && |
945 | pci_pcie_type(pdev) != PCI_EXP_TYPE_DOWNSTREAM) || !link_state) | |
7d715a6c SL |
946 | return; |
947 | ||
80bfdbe3 | 948 | if (link_state->aspm_support) |
7d715a6c SL |
949 | sysfs_remove_file_from_group(&pdev->dev.kobj, |
950 | &dev_attr_link_state.attr, power_group); | |
4d246e45 | 951 | if (link_state->clkpm_capable) |
7d715a6c SL |
952 | sysfs_remove_file_from_group(&pdev->dev.kobj, |
953 | &dev_attr_clk_ctl.attr, power_group); | |
954 | } | |
955 | #endif | |
956 | ||
957 | static int __init pcie_aspm_disable(char *str) | |
958 | { | |
d6d38574 | 959 | if (!strcmp(str, "off")) { |
3c076351 | 960 | aspm_policy = POLICY_DEFAULT; |
d6d38574 | 961 | aspm_disabled = 1; |
8b8bae90 | 962 | aspm_support_enabled = false; |
d6d38574 SL |
963 | printk(KERN_INFO "PCIe ASPM is disabled\n"); |
964 | } else if (!strcmp(str, "force")) { | |
965 | aspm_force = 1; | |
8072ba1b | 966 | printk(KERN_INFO "PCIe ASPM is forcibly enabled\n"); |
d6d38574 | 967 | } |
7d715a6c SL |
968 | return 1; |
969 | } | |
970 | ||
d6d38574 | 971 | __setup("pcie_aspm=", pcie_aspm_disable); |
7d715a6c | 972 | |
5fde244d SL |
973 | void pcie_no_aspm(void) |
974 | { | |
3c076351 MG |
975 | /* |
976 | * Disabling ASPM is intended to prevent the kernel from modifying | |
977 | * existing hardware state, not to clear existing state. To that end: | |
978 | * (a) set policy to POLICY_DEFAULT in order to avoid changing state | |
979 | * (b) prevent userspace from changing policy | |
980 | */ | |
981 | if (!aspm_force) { | |
982 | aspm_policy = POLICY_DEFAULT; | |
d6d38574 | 983 | aspm_disabled = 1; |
3c076351 | 984 | } |
5fde244d SL |
985 | } |
986 | ||
3e1b1600 AP |
987 | /** |
988 | * pcie_aspm_enabled - is PCIe ASPM enabled? | |
989 | * | |
990 | * Returns true if ASPM has not been disabled by the command-line option | |
991 | * pcie_aspm=off. | |
992 | **/ | |
993 | int pcie_aspm_enabled(void) | |
7d715a6c | 994 | { |
3e1b1600 | 995 | return !aspm_disabled; |
7d715a6c | 996 | } |
3e1b1600 | 997 | EXPORT_SYMBOL(pcie_aspm_enabled); |
7d715a6c | 998 | |
8b8bae90 RW |
999 | bool pcie_aspm_support_enabled(void) |
1000 | { | |
1001 | return aspm_support_enabled; | |
1002 | } | |
1003 | EXPORT_SYMBOL(pcie_aspm_support_enabled); |