Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * File: portdrv_core.c | |
3 | * Purpose: PCI Express Port Bus Driver's Core Functions | |
4 | * | |
5 | * Copyright (C) 2004 Intel | |
6 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) | |
7 | */ | |
8 | ||
9 | #include <linux/module.h> | |
10 | #include <linux/pci.h> | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/errno.h> | |
13 | #include <linux/pm.h> | |
4e57b681 TS |
14 | #include <linux/string.h> |
15 | #include <linux/slab.h> | |
1da177e4 | 16 | #include <linux/pcieport_if.h> |
28eb5f27 RW |
17 | #include <linux/aer.h> |
18 | #include <linux/pci-aspm.h> | |
1da177e4 | 19 | |
1bf83e55 | 20 | #include "../pci.h" |
1da177e4 LT |
21 | #include "portdrv.h" |
22 | ||
facf6d16 RW |
23 | /** |
24 | * release_pcie_device - free PCI Express port service device structure | |
25 | * @dev: Port service device to release | |
26 | * | |
27 | * Invoked automatically when device is being removed in response to | |
28 | * device_unregister(dev). Release all resources being claimed. | |
1da177e4 LT |
29 | */ |
30 | static void release_pcie_device(struct device *dev) | |
31 | { | |
40da4186 | 32 | kfree(to_pcie_device(dev)); |
1da177e4 LT |
33 | } |
34 | ||
b43d4513 RW |
35 | /** |
36 | * pcie_port_msix_add_entry - add entry to given array of MSI-X entries | |
37 | * @entries: Array of MSI-X entries | |
38 | * @new_entry: Index of the entry to add to the array | |
39 | * @nr_entries: Number of entries aleady in the array | |
40 | * | |
41 | * Return value: Position of the added entry in the array | |
42 | */ | |
43 | static int pcie_port_msix_add_entry( | |
44 | struct msix_entry *entries, int new_entry, int nr_entries) | |
45 | { | |
46 | int j; | |
47 | ||
48 | for (j = 0; j < nr_entries; j++) | |
49 | if (entries[j].entry == new_entry) | |
50 | return j; | |
51 | ||
52 | entries[j].entry = new_entry; | |
53 | return j; | |
54 | } | |
55 | ||
56 | /** | |
57 | * pcie_port_enable_msix - try to set up MSI-X as interrupt mode for given port | |
58 | * @dev: PCI Express port to handle | |
59 | * @vectors: Array of interrupt vectors to populate | |
60 | * @mask: Bitmask of port capabilities returned by get_port_device_capability() | |
61 | * | |
62 | * Return value: 0 on success, error code on failure | |
63 | */ | |
64 | static int pcie_port_enable_msix(struct pci_dev *dev, int *vectors, int mask) | |
65 | { | |
66 | struct msix_entry *msix_entries; | |
67 | int idx[PCIE_PORT_DEVICE_MAXSERVICES]; | |
68 | int nr_entries, status, pos, i, nvec; | |
69 | u16 reg16; | |
70 | u32 reg32; | |
71 | ||
72 | nr_entries = pci_msix_table_size(dev); | |
73 | if (!nr_entries) | |
74 | return -EINVAL; | |
75 | if (nr_entries > PCIE_PORT_MAX_MSIX_ENTRIES) | |
76 | nr_entries = PCIE_PORT_MAX_MSIX_ENTRIES; | |
77 | ||
78 | msix_entries = kzalloc(sizeof(*msix_entries) * nr_entries, GFP_KERNEL); | |
79 | if (!msix_entries) | |
80 | return -ENOMEM; | |
81 | ||
82 | /* | |
83 | * Allocate as many entries as the port wants, so that we can check | |
84 | * which of them will be useful. Moreover, if nr_entries is correctly | |
85 | * equal to the number of entries this port actually uses, we'll happily | |
86 | * go through without any tricks. | |
87 | */ | |
88 | for (i = 0; i < nr_entries; i++) | |
89 | msix_entries[i].entry = i; | |
90 | ||
91 | status = pci_enable_msix(dev, msix_entries, nr_entries); | |
92 | if (status) | |
93 | goto Exit; | |
94 | ||
95 | for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++) | |
96 | idx[i] = -1; | |
97 | status = -EIO; | |
98 | nvec = 0; | |
99 | ||
100 | if (mask & (PCIE_PORT_SERVICE_PME | PCIE_PORT_SERVICE_HP)) { | |
101 | int entry; | |
102 | ||
103 | /* | |
104 | * The code below follows the PCI Express Base Specification 2.0 | |
105 | * stating in Section 6.1.6 that "PME and Hot-Plug Event | |
106 | * interrupts (when both are implemented) always share the same | |
107 | * MSI or MSI-X vector, as indicated by the Interrupt Message | |
108 | * Number field in the PCI Express Capabilities register", where | |
109 | * according to Section 7.8.2 of the specification "For MSI-X, | |
110 | * the value in this field indicates which MSI-X Table entry is | |
111 | * used to generate the interrupt message." | |
112 | */ | |
dba90dfe | 113 | pos = pci_pcie_cap(dev); |
f9f45604 KK |
114 | pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); |
115 | entry = (reg16 & PCI_EXP_FLAGS_IRQ) >> 9; | |
b43d4513 RW |
116 | if (entry >= nr_entries) |
117 | goto Error; | |
118 | ||
119 | i = pcie_port_msix_add_entry(msix_entries, entry, nvec); | |
120 | if (i == nvec) | |
121 | nvec++; | |
122 | ||
123 | idx[PCIE_PORT_SERVICE_PME_SHIFT] = i; | |
124 | idx[PCIE_PORT_SERVICE_HP_SHIFT] = i; | |
125 | } | |
126 | ||
127 | if (mask & PCIE_PORT_SERVICE_AER) { | |
128 | int entry; | |
129 | ||
130 | /* | |
131 | * The code below follows Section 7.10.10 of the PCI Express | |
132 | * Base Specification 2.0 stating that bits 31-27 of the Root | |
133 | * Error Status Register contain a value indicating which of the | |
134 | * MSI/MSI-X vectors assigned to the port is going to be used | |
135 | * for AER, where "For MSI-X, the value in this register | |
136 | * indicates which MSI-X Table entry is used to generate the | |
137 | * interrupt message." | |
138 | */ | |
139 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); | |
140 | pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, ®32); | |
141 | entry = reg32 >> 27; | |
142 | if (entry >= nr_entries) | |
143 | goto Error; | |
144 | ||
145 | i = pcie_port_msix_add_entry(msix_entries, entry, nvec); | |
146 | if (i == nvec) | |
147 | nvec++; | |
148 | ||
149 | idx[PCIE_PORT_SERVICE_AER_SHIFT] = i; | |
150 | } | |
151 | ||
152 | /* | |
153 | * If nvec is equal to the allocated number of entries, we can just use | |
154 | * what we have. Otherwise, the port has some extra entries not for the | |
155 | * services we know and we need to work around that. | |
156 | */ | |
157 | if (nvec == nr_entries) { | |
158 | status = 0; | |
159 | } else { | |
160 | /* Drop the temporary MSI-X setup */ | |
161 | pci_disable_msix(dev); | |
162 | ||
163 | /* Now allocate the MSI-X vectors for real */ | |
164 | status = pci_enable_msix(dev, msix_entries, nvec); | |
165 | if (status) | |
166 | goto Exit; | |
167 | } | |
168 | ||
169 | for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++) | |
170 | vectors[i] = idx[i] >= 0 ? msix_entries[idx[i]].vector : -1; | |
171 | ||
172 | Exit: | |
173 | kfree(msix_entries); | |
174 | return status; | |
175 | ||
176 | Error: | |
177 | pci_disable_msix(dev); | |
178 | goto Exit; | |
179 | } | |
180 | ||
facf6d16 | 181 | /** |
dc535178 | 182 | * init_service_irqs - initialize irqs for PCI Express port services |
facf6d16 | 183 | * @dev: PCI Express port to handle |
dc535178 | 184 | * @irqs: Array of irqs to populate |
facf6d16 RW |
185 | * @mask: Bitmask of port capabilities returned by get_port_device_capability() |
186 | * | |
187 | * Return value: Interrupt mode associated with the port | |
188 | */ | |
dc535178 | 189 | static int init_service_irqs(struct pci_dev *dev, int *irqs, int mask) |
1da177e4 | 190 | { |
c39fae14 RW |
191 | int i, irq = -1; |
192 | ||
193 | /* We have to use INTx if MSI cannot be used for PCIe PME. */ | |
194 | if ((mask & PCIE_PORT_SERVICE_PME) && pcie_pme_no_msi()) { | |
195 | if (dev->pin) | |
196 | irq = dev->irq; | |
197 | goto no_msi; | |
198 | } | |
90e9cd50 | 199 | |
b43d4513 | 200 | /* Try to use MSI-X if supported */ |
dc535178 KK |
201 | if (!pcie_port_enable_msix(dev, irqs, mask)) |
202 | return 0; | |
c39fae14 | 203 | |
b43d4513 | 204 | /* We're not going to use MSI-X, so try MSI and fall back to INTx */ |
dc535178 KK |
205 | if (!pci_enable_msi(dev) || dev->pin) |
206 | irq = dev->irq; | |
b43d4513 | 207 | |
c39fae14 | 208 | no_msi: |
b43d4513 | 209 | for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++) |
dc535178 KK |
210 | irqs[i] = irq; |
211 | irqs[PCIE_PORT_SERVICE_VC_SHIFT] = -1; | |
1da177e4 | 212 | |
dc535178 KK |
213 | if (irq < 0) |
214 | return -ENODEV; | |
215 | return 0; | |
1da177e4 LT |
216 | } |
217 | ||
fbb5de70 KK |
218 | static void cleanup_service_irqs(struct pci_dev *dev) |
219 | { | |
220 | if (dev->msix_enabled) | |
221 | pci_disable_msix(dev); | |
222 | else if (dev->msi_enabled) | |
223 | pci_disable_msi(dev); | |
224 | } | |
225 | ||
facf6d16 RW |
226 | /** |
227 | * get_port_device_capability - discover capabilities of a PCI Express port | |
228 | * @dev: PCI Express port to examine | |
229 | * | |
230 | * The capabilities are read from the port's PCI Express configuration registers | |
231 | * as described in PCI Express Base Specification 1.0a sections 7.8.2, 7.8.9 and | |
232 | * 7.9 - 7.11. | |
233 | * | |
234 | * Return value: Bitmask of discovered port capabilities | |
235 | */ | |
1da177e4 LT |
236 | static int get_port_device_capability(struct pci_dev *dev) |
237 | { | |
238 | int services = 0, pos; | |
239 | u16 reg16; | |
240 | u32 reg32; | |
28eb5f27 RW |
241 | int cap_mask; |
242 | int err; | |
243 | ||
244 | err = pcie_port_platform_notify(dev, &cap_mask); | |
245 | if (pcie_ports_auto) { | |
246 | if (err) { | |
247 | pcie_no_aspm(); | |
248 | return 0; | |
249 | } | |
250 | } else { | |
251 | cap_mask = PCIE_PORT_SERVICE_PME | PCIE_PORT_SERVICE_HP | |
252 | | PCIE_PORT_SERVICE_VC; | |
253 | if (pci_aer_available()) | |
254 | cap_mask |= PCIE_PORT_SERVICE_AER; | |
255 | } | |
1da177e4 | 256 | |
dba90dfe | 257 | pos = pci_pcie_cap(dev); |
f9f45604 | 258 | pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); |
1da177e4 | 259 | /* Hot-Plug Capable */ |
28eb5f27 | 260 | if ((cap_mask & PCIE_PORT_SERVICE_HP) && (reg16 & PCI_EXP_FLAGS_SLOT)) { |
f9f45604 | 261 | pci_read_config_dword(dev, pos + PCI_EXP_SLTCAP, ®32); |
2bd50dd8 | 262 | if (reg32 & PCI_EXP_SLTCAP_HPC) { |
1da177e4 | 263 | services |= PCIE_PORT_SERVICE_HP; |
2bd50dd8 RW |
264 | /* |
265 | * Disable hot-plug interrupts in case they have been | |
266 | * enabled by the BIOS and the hot-plug service driver | |
267 | * is not loaded. | |
268 | */ | |
269 | pos += PCI_EXP_SLTCTL; | |
270 | pci_read_config_word(dev, pos, ®16); | |
271 | reg16 &= ~(PCI_EXP_SLTCTL_CCIE | PCI_EXP_SLTCTL_HPIE); | |
272 | pci_write_config_word(dev, pos, reg16); | |
273 | } | |
1bf83e55 RW |
274 | } |
275 | /* AER capable */ | |
28eb5f27 | 276 | if ((cap_mask & PCIE_PORT_SERVICE_AER) |
2bd50dd8 | 277 | && pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR)) { |
0927678f | 278 | services |= PCIE_PORT_SERVICE_AER; |
2bd50dd8 RW |
279 | /* |
280 | * Disable AER on this port in case it's been enabled by the | |
281 | * BIOS (the AER service driver will enable it when necessary). | |
282 | */ | |
283 | pci_disable_pcie_error_reporting(dev); | |
284 | } | |
1bf83e55 | 285 | /* VC support */ |
0927678f JB |
286 | if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_VC)) |
287 | services |= PCIE_PORT_SERVICE_VC; | |
9e5d0b16 | 288 | /* Root ports are capable of generating PME too */ |
28eb5f27 | 289 | if ((cap_mask & PCIE_PORT_SERVICE_PME) |
2bd50dd8 | 290 | && dev->pcie_type == PCI_EXP_TYPE_ROOT_PORT) { |
9e5d0b16 | 291 | services |= PCIE_PORT_SERVICE_PME; |
2bd50dd8 RW |
292 | /* |
293 | * Disable PME interrupt on this port in case it's been enabled | |
294 | * by the BIOS (the PME service driver will enable it when | |
295 | * necessary). | |
296 | */ | |
297 | pcie_pme_interrupt_enable(dev, false); | |
298 | } | |
1da177e4 LT |
299 | |
300 | return services; | |
301 | } | |
302 | ||
facf6d16 | 303 | /** |
52a0f24b KK |
304 | * pcie_device_init - allocate and initialize PCI Express port service device |
305 | * @pdev: PCI Express port to associate the service device with | |
306 | * @service: Type of service to associate with the service device | |
facf6d16 | 307 | * @irq: Interrupt vector to associate with the service device |
facf6d16 | 308 | */ |
52a0f24b | 309 | static int pcie_device_init(struct pci_dev *pdev, int service, int irq) |
1da177e4 | 310 | { |
52a0f24b KK |
311 | int retval; |
312 | struct pcie_device *pcie; | |
1da177e4 LT |
313 | struct device *device; |
314 | ||
52a0f24b KK |
315 | pcie = kzalloc(sizeof(*pcie), GFP_KERNEL); |
316 | if (!pcie) | |
317 | return -ENOMEM; | |
318 | pcie->port = pdev; | |
319 | pcie->irq = irq; | |
320 | pcie->service = service; | |
1da177e4 LT |
321 | |
322 | /* Initialize generic device interface */ | |
52a0f24b | 323 | device = &pcie->device; |
1da177e4 | 324 | device->bus = &pcie_port_bus_type; |
1da177e4 | 325 | device->release = release_pcie_device; /* callback to free pcie dev */ |
1a927133 | 326 | dev_set_name(device, "%s:pcie%02x", |
52a0f24b KK |
327 | pci_name(pdev), |
328 | get_descriptor_id(pdev->pcie_type, service)); | |
329 | device->parent = &pdev->dev; | |
a1e4d72c | 330 | device_enable_async_suspend(device); |
52a0f24b KK |
331 | |
332 | retval = device_register(device); | |
333 | if (retval) | |
334 | kfree(pcie); | |
335 | else | |
336 | get_device(device); | |
337 | return retval; | |
1da177e4 LT |
338 | } |
339 | ||
facf6d16 RW |
340 | /** |
341 | * pcie_port_device_register - register PCI Express port | |
342 | * @dev: PCI Express port to register | |
343 | * | |
344 | * Allocate the port extension structure and register services associated with | |
345 | * the port. | |
346 | */ | |
1da177e4 LT |
347 | int pcie_port_device_register(struct pci_dev *dev) |
348 | { | |
40717c39 | 349 | int status, capabilities, i, nr_service; |
dc535178 | 350 | int irqs[PCIE_PORT_DEVICE_MAXSERVICES]; |
1da177e4 | 351 | |
40717c39 | 352 | /* Get and check PCI Express port services */ |
d013598d KK |
353 | capabilities = get_port_device_capability(dev); |
354 | if (!capabilities) | |
355 | return -ENODEV; | |
356 | ||
1ce5e830 KK |
357 | /* Enable PCI Express port device */ |
358 | status = pci_enable_device(dev); | |
359 | if (status) | |
694f88ef | 360 | return status; |
1ce5e830 | 361 | pci_set_master(dev); |
dc535178 KK |
362 | /* |
363 | * Initialize service irqs. Don't use service devices that | |
364 | * require interrupts if there is no way to generate them. | |
365 | */ | |
366 | status = init_service_irqs(dev, irqs, capabilities); | |
367 | if (status) { | |
368 | capabilities &= PCIE_PORT_SERVICE_VC; | |
369 | if (!capabilities) | |
1ce5e830 | 370 | goto error_disable; |
f118c0c3 | 371 | } |
1da177e4 LT |
372 | |
373 | /* Allocate child services if any */ | |
40717c39 KK |
374 | status = -ENODEV; |
375 | nr_service = 0; | |
376 | for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++) { | |
90e9cd50 | 377 | int service = 1 << i; |
90e9cd50 RW |
378 | if (!(capabilities & service)) |
379 | continue; | |
40717c39 KK |
380 | if (!pcie_device_init(dev, service, irqs[i])) |
381 | nr_service++; | |
f118c0c3 | 382 | } |
40717c39 | 383 | if (!nr_service) |
fbb5de70 | 384 | goto error_cleanup_irqs; |
40717c39 | 385 | |
1da177e4 | 386 | return 0; |
f118c0c3 | 387 | |
fbb5de70 KK |
388 | error_cleanup_irqs: |
389 | cleanup_service_irqs(dev); | |
1ce5e830 KK |
390 | error_disable: |
391 | pci_disable_device(dev); | |
f118c0c3 | 392 | return status; |
1da177e4 LT |
393 | } |
394 | ||
395 | #ifdef CONFIG_PM | |
d0e2b4a0 | 396 | static int suspend_iter(struct device *dev, void *data) |
1da177e4 | 397 | { |
1da177e4 | 398 | struct pcie_port_service_driver *service_driver; |
d0e2b4a0 | 399 | |
40da4186 HS |
400 | if ((dev->bus == &pcie_port_bus_type) && dev->driver) { |
401 | service_driver = to_service_driver(dev->driver); | |
402 | if (service_driver->suspend) | |
403 | service_driver->suspend(to_pcie_device(dev)); | |
404 | } | |
d0e2b4a0 | 405 | return 0; |
406 | } | |
1da177e4 | 407 | |
facf6d16 RW |
408 | /** |
409 | * pcie_port_device_suspend - suspend port services associated with a PCIe port | |
410 | * @dev: PCI Express port to handle | |
facf6d16 | 411 | */ |
3a3c244c | 412 | int pcie_port_device_suspend(struct device *dev) |
d0e2b4a0 | 413 | { |
3a3c244c | 414 | return device_for_each_child(dev, NULL, suspend_iter); |
1da177e4 LT |
415 | } |
416 | ||
d0e2b4a0 | 417 | static int resume_iter(struct device *dev, void *data) |
418 | { | |
1da177e4 LT |
419 | struct pcie_port_service_driver *service_driver; |
420 | ||
d0e2b4a0 | 421 | if ((dev->bus == &pcie_port_bus_type) && |
422 | (dev->driver)) { | |
423 | service_driver = to_service_driver(dev->driver); | |
424 | if (service_driver->resume) | |
425 | service_driver->resume(to_pcie_device(dev)); | |
1da177e4 | 426 | } |
d0e2b4a0 | 427 | return 0; |
428 | } | |
1da177e4 | 429 | |
facf6d16 RW |
430 | /** |
431 | * pcie_port_device_suspend - resume port services associated with a PCIe port | |
432 | * @dev: PCI Express port to handle | |
433 | */ | |
3a3c244c | 434 | int pcie_port_device_resume(struct device *dev) |
d0e2b4a0 | 435 | { |
3a3c244c | 436 | return device_for_each_child(dev, NULL, resume_iter); |
1da177e4 | 437 | } |
3a3c244c | 438 | #endif /* PM */ |
1da177e4 | 439 | |
d0e2b4a0 | 440 | static int remove_iter(struct device *dev, void *data) |
1da177e4 | 441 | { |
d0e2b4a0 | 442 | if (dev->bus == &pcie_port_bus_type) { |
ae40582e EB |
443 | put_device(dev); |
444 | device_unregister(dev); | |
1da177e4 | 445 | } |
d0e2b4a0 | 446 | return 0; |
447 | } | |
448 | ||
facf6d16 RW |
449 | /** |
450 | * pcie_port_device_remove - unregister PCI Express port service devices | |
451 | * @dev: PCI Express port the service devices to unregister are associated with | |
452 | * | |
453 | * Remove PCI Express port service devices associated with given port and | |
454 | * disable MSI-X or MSI for the port. | |
455 | */ | |
d0e2b4a0 | 456 | void pcie_port_device_remove(struct pci_dev *dev) |
457 | { | |
ae40582e | 458 | device_for_each_child(&dev->dev, NULL, remove_iter); |
fbb5de70 | 459 | cleanup_service_irqs(dev); |
dc535178 | 460 | pci_disable_device(dev); |
1da177e4 LT |
461 | } |
462 | ||
d9347371 RW |
463 | /** |
464 | * pcie_port_probe_service - probe driver for given PCI Express port service | |
465 | * @dev: PCI Express port service device to probe against | |
466 | * | |
467 | * If PCI Express port service driver is registered with | |
468 | * pcie_port_service_register(), this function will be called by the driver core | |
469 | * whenever match is found between the driver and a port service device. | |
470 | */ | |
fa6c9937 | 471 | static int pcie_port_probe_service(struct device *dev) |
1da177e4 | 472 | { |
fa6c9937 RW |
473 | struct pcie_device *pciedev; |
474 | struct pcie_port_service_driver *driver; | |
475 | int status; | |
476 | ||
477 | if (!dev || !dev->driver) | |
478 | return -ENODEV; | |
479 | ||
480 | driver = to_service_driver(dev->driver); | |
481 | if (!driver || !driver->probe) | |
482 | return -ENODEV; | |
483 | ||
484 | pciedev = to_pcie_device(dev); | |
0516c8bc | 485 | status = driver->probe(pciedev); |
fa6c9937 RW |
486 | if (!status) { |
487 | dev_printk(KERN_DEBUG, dev, "service driver %s loaded\n", | |
488 | driver->name); | |
489 | get_device(dev); | |
490 | } | |
491 | return status; | |
1da177e4 LT |
492 | } |
493 | ||
d9347371 RW |
494 | /** |
495 | * pcie_port_remove_service - detach driver from given PCI Express port service | |
496 | * @dev: PCI Express port service device to handle | |
497 | * | |
498 | * If PCI Express port service driver is registered with | |
499 | * pcie_port_service_register(), this function will be called by the driver core | |
500 | * when device_unregister() is called for the port service device associated | |
501 | * with the driver. | |
502 | */ | |
fa6c9937 | 503 | static int pcie_port_remove_service(struct device *dev) |
1da177e4 | 504 | { |
fa6c9937 RW |
505 | struct pcie_device *pciedev; |
506 | struct pcie_port_service_driver *driver; | |
507 | ||
508 | if (!dev || !dev->driver) | |
509 | return 0; | |
510 | ||
511 | pciedev = to_pcie_device(dev); | |
512 | driver = to_service_driver(dev->driver); | |
513 | if (driver && driver->remove) { | |
514 | dev_printk(KERN_DEBUG, dev, "unloading service driver %s\n", | |
515 | driver->name); | |
516 | driver->remove(pciedev); | |
517 | put_device(dev); | |
518 | } | |
519 | return 0; | |
1da177e4 LT |
520 | } |
521 | ||
d9347371 RW |
522 | /** |
523 | * pcie_port_shutdown_service - shut down given PCI Express port service | |
524 | * @dev: PCI Express port service device to handle | |
525 | * | |
526 | * If PCI Express port service driver is registered with | |
527 | * pcie_port_service_register(), this function will be called by the driver core | |
528 | * when device_shutdown() is called for the port service device associated | |
529 | * with the driver. | |
530 | */ | |
fa6c9937 RW |
531 | static void pcie_port_shutdown_service(struct device *dev) {} |
532 | ||
d9347371 RW |
533 | /** |
534 | * pcie_port_service_register - register PCI Express port service driver | |
535 | * @new: PCI Express port service driver to register | |
536 | */ | |
1da177e4 LT |
537 | int pcie_port_service_register(struct pcie_port_service_driver *new) |
538 | { | |
79dd9182 RW |
539 | if (pcie_ports_disabled) |
540 | return -ENODEV; | |
541 | ||
1da177e4 LT |
542 | new->driver.name = (char *)new->name; |
543 | new->driver.bus = &pcie_port_bus_type; | |
544 | new->driver.probe = pcie_port_probe_service; | |
545 | new->driver.remove = pcie_port_remove_service; | |
546 | new->driver.shutdown = pcie_port_shutdown_service; | |
1da177e4 LT |
547 | |
548 | return driver_register(&new->driver); | |
d0e2b4a0 | 549 | } |
40da4186 | 550 | EXPORT_SYMBOL(pcie_port_service_register); |
1da177e4 | 551 | |
d9347371 RW |
552 | /** |
553 | * pcie_port_service_unregister - unregister PCI Express port service driver | |
554 | * @drv: PCI Express port service driver to unregister | |
555 | */ | |
fa6c9937 | 556 | void pcie_port_service_unregister(struct pcie_port_service_driver *drv) |
1da177e4 | 557 | { |
fa6c9937 | 558 | driver_unregister(&drv->driver); |
1da177e4 | 559 | } |
1da177e4 | 560 | EXPORT_SYMBOL(pcie_port_service_unregister); |