Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * probe.c - PCI detection and setup code | |
3 | */ | |
4 | ||
5 | #include <linux/kernel.h> | |
6 | #include <linux/delay.h> | |
7 | #include <linux/init.h> | |
8 | #include <linux/pci.h> | |
9 | #include <linux/slab.h> | |
10 | #include <linux/module.h> | |
11 | #include <linux/cpumask.h> | |
7d715a6c | 12 | #include <linux/pci-aspm.h> |
284f5f9d | 13 | #include <asm-generic/pci-bridge.h> |
bc56b9e0 | 14 | #include "pci.h" |
1da177e4 LT |
15 | |
16 | #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ | |
17 | #define CARDBUS_RESERVE_BUSNR 3 | |
1da177e4 LT |
18 | |
19 | /* Ugh. Need to stop exporting this to modules. */ | |
20 | LIST_HEAD(pci_root_buses); | |
21 | EXPORT_SYMBOL(pci_root_buses); | |
22 | ||
5cc62c20 YL |
23 | static LIST_HEAD(pci_domain_busn_res_list); |
24 | ||
25 | struct pci_domain_busn_res { | |
26 | struct list_head list; | |
27 | struct resource res; | |
28 | int domain_nr; | |
29 | }; | |
30 | ||
31 | static struct resource *get_pci_domain_busn_res(int domain_nr) | |
32 | { | |
33 | struct pci_domain_busn_res *r; | |
34 | ||
35 | list_for_each_entry(r, &pci_domain_busn_res_list, list) | |
36 | if (r->domain_nr == domain_nr) | |
37 | return &r->res; | |
38 | ||
39 | r = kzalloc(sizeof(*r), GFP_KERNEL); | |
40 | if (!r) | |
41 | return NULL; | |
42 | ||
43 | r->domain_nr = domain_nr; | |
44 | r->res.start = 0; | |
45 | r->res.end = 0xff; | |
46 | r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED; | |
47 | ||
48 | list_add_tail(&r->list, &pci_domain_busn_res_list); | |
49 | ||
50 | return &r->res; | |
51 | } | |
52 | ||
70308923 GKH |
53 | static int find_anything(struct device *dev, void *data) |
54 | { | |
55 | return 1; | |
56 | } | |
1da177e4 | 57 | |
ed4aaadb ZY |
58 | /* |
59 | * Some device drivers need know if pci is initiated. | |
60 | * Basically, we think pci is not initiated when there | |
70308923 | 61 | * is no device to be found on the pci_bus_type. |
ed4aaadb ZY |
62 | */ |
63 | int no_pci_devices(void) | |
64 | { | |
70308923 GKH |
65 | struct device *dev; |
66 | int no_devices; | |
ed4aaadb | 67 | |
70308923 GKH |
68 | dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything); |
69 | no_devices = (dev == NULL); | |
70 | put_device(dev); | |
71 | return no_devices; | |
72 | } | |
ed4aaadb ZY |
73 | EXPORT_SYMBOL(no_pci_devices); |
74 | ||
1da177e4 LT |
75 | /* |
76 | * PCI Bus Class | |
77 | */ | |
fd7d1ced | 78 | static void release_pcibus_dev(struct device *dev) |
1da177e4 | 79 | { |
fd7d1ced | 80 | struct pci_bus *pci_bus = to_pci_bus(dev); |
1da177e4 LT |
81 | |
82 | if (pci_bus->bridge) | |
83 | put_device(pci_bus->bridge); | |
2fe2abf8 | 84 | pci_bus_remove_resources(pci_bus); |
98d9f30c | 85 | pci_release_bus_of_node(pci_bus); |
1da177e4 LT |
86 | kfree(pci_bus); |
87 | } | |
88 | ||
89 | static struct class pcibus_class = { | |
90 | .name = "pci_bus", | |
fd7d1ced | 91 | .dev_release = &release_pcibus_dev, |
b9d320fc | 92 | .dev_attrs = pcibus_dev_attrs, |
1da177e4 LT |
93 | }; |
94 | ||
95 | static int __init pcibus_class_init(void) | |
96 | { | |
97 | return class_register(&pcibus_class); | |
98 | } | |
99 | postcore_initcall(pcibus_class_init); | |
100 | ||
6ac665c6 | 101 | static u64 pci_size(u64 base, u64 maxbase, u64 mask) |
1da177e4 | 102 | { |
6ac665c6 | 103 | u64 size = mask & maxbase; /* Find the significant bits */ |
1da177e4 LT |
104 | if (!size) |
105 | return 0; | |
106 | ||
107 | /* Get the lowest of them to find the decode size, and | |
108 | from that the extent. */ | |
109 | size = (size & ~(size-1)) - 1; | |
110 | ||
111 | /* base == maxbase can be valid only if the BAR has | |
112 | already been programmed with all 1s. */ | |
113 | if (base == maxbase && ((base | size) & mask) != mask) | |
114 | return 0; | |
115 | ||
116 | return size; | |
117 | } | |
118 | ||
28c6821a | 119 | static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar) |
6ac665c6 | 120 | { |
8d6a6a47 | 121 | u32 mem_type; |
28c6821a | 122 | unsigned long flags; |
8d6a6a47 | 123 | |
6ac665c6 | 124 | if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) { |
28c6821a BH |
125 | flags = bar & ~PCI_BASE_ADDRESS_IO_MASK; |
126 | flags |= IORESOURCE_IO; | |
127 | return flags; | |
6ac665c6 | 128 | } |
07eddf3d | 129 | |
28c6821a BH |
130 | flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK; |
131 | flags |= IORESOURCE_MEM; | |
132 | if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH) | |
133 | flags |= IORESOURCE_PREFETCH; | |
07eddf3d | 134 | |
8d6a6a47 BH |
135 | mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK; |
136 | switch (mem_type) { | |
137 | case PCI_BASE_ADDRESS_MEM_TYPE_32: | |
138 | break; | |
139 | case PCI_BASE_ADDRESS_MEM_TYPE_1M: | |
140 | dev_info(&dev->dev, "1M mem BAR treated as 32-bit BAR\n"); | |
141 | break; | |
142 | case PCI_BASE_ADDRESS_MEM_TYPE_64: | |
28c6821a BH |
143 | flags |= IORESOURCE_MEM_64; |
144 | break; | |
8d6a6a47 BH |
145 | default: |
146 | dev_warn(&dev->dev, | |
147 | "mem unknown type %x treated as 32-bit BAR\n", | |
148 | mem_type); | |
149 | break; | |
150 | } | |
28c6821a | 151 | return flags; |
07eddf3d YL |
152 | } |
153 | ||
0b400c7e YZ |
154 | /** |
155 | * pci_read_base - read a PCI BAR | |
156 | * @dev: the PCI device | |
157 | * @type: type of the BAR | |
158 | * @res: resource buffer to be filled in | |
159 | * @pos: BAR position in the config space | |
160 | * | |
161 | * Returns 1 if the BAR is 64-bit, or 0 if 32-bit. | |
6ac665c6 | 162 | */ |
0b400c7e | 163 | int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, |
6ac665c6 | 164 | struct resource *res, unsigned int pos) |
07eddf3d | 165 | { |
6ac665c6 | 166 | u32 l, sz, mask; |
253d2e54 | 167 | u16 orig_cmd; |
5bfa14ed | 168 | struct pci_bus_region region; |
6ac665c6 | 169 | |
1ed67439 | 170 | mask = type ? PCI_ROM_ADDRESS_MASK : ~0; |
6ac665c6 | 171 | |
253d2e54 JP |
172 | if (!dev->mmio_always_on) { |
173 | pci_read_config_word(dev, PCI_COMMAND, &orig_cmd); | |
174 | pci_write_config_word(dev, PCI_COMMAND, | |
175 | orig_cmd & ~(PCI_COMMAND_MEMORY | PCI_COMMAND_IO)); | |
176 | } | |
177 | ||
6ac665c6 MW |
178 | res->name = pci_name(dev); |
179 | ||
180 | pci_read_config_dword(dev, pos, &l); | |
1ed67439 | 181 | pci_write_config_dword(dev, pos, l | mask); |
6ac665c6 MW |
182 | pci_read_config_dword(dev, pos, &sz); |
183 | pci_write_config_dword(dev, pos, l); | |
184 | ||
253d2e54 JP |
185 | if (!dev->mmio_always_on) |
186 | pci_write_config_word(dev, PCI_COMMAND, orig_cmd); | |
187 | ||
6ac665c6 MW |
188 | /* |
189 | * All bits set in sz means the device isn't working properly. | |
45aa23b4 BH |
190 | * If the BAR isn't implemented, all bits must be 0. If it's a |
191 | * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit | |
192 | * 1 must be clear. | |
6ac665c6 | 193 | */ |
45aa23b4 | 194 | if (!sz || sz == 0xffffffff) |
6ac665c6 MW |
195 | goto fail; |
196 | ||
197 | /* | |
198 | * I don't know how l can have all bits set. Copied from old code. | |
199 | * Maybe it fixes a bug on some ancient platform. | |
200 | */ | |
201 | if (l == 0xffffffff) | |
202 | l = 0; | |
203 | ||
204 | if (type == pci_bar_unknown) { | |
28c6821a BH |
205 | res->flags = decode_bar(dev, l); |
206 | res->flags |= IORESOURCE_SIZEALIGN; | |
207 | if (res->flags & IORESOURCE_IO) { | |
6ac665c6 | 208 | l &= PCI_BASE_ADDRESS_IO_MASK; |
5aceca9d | 209 | mask = PCI_BASE_ADDRESS_IO_MASK & (u32) IO_SPACE_LIMIT; |
6ac665c6 MW |
210 | } else { |
211 | l &= PCI_BASE_ADDRESS_MEM_MASK; | |
212 | mask = (u32)PCI_BASE_ADDRESS_MEM_MASK; | |
213 | } | |
214 | } else { | |
215 | res->flags |= (l & IORESOURCE_ROM_ENABLE); | |
216 | l &= PCI_ROM_ADDRESS_MASK; | |
217 | mask = (u32)PCI_ROM_ADDRESS_MASK; | |
218 | } | |
219 | ||
28c6821a | 220 | if (res->flags & IORESOURCE_MEM_64) { |
6ac665c6 MW |
221 | u64 l64 = l; |
222 | u64 sz64 = sz; | |
223 | u64 mask64 = mask | (u64)~0 << 32; | |
224 | ||
225 | pci_read_config_dword(dev, pos + 4, &l); | |
226 | pci_write_config_dword(dev, pos + 4, ~0); | |
227 | pci_read_config_dword(dev, pos + 4, &sz); | |
228 | pci_write_config_dword(dev, pos + 4, l); | |
229 | ||
230 | l64 |= ((u64)l << 32); | |
231 | sz64 |= ((u64)sz << 32); | |
232 | ||
233 | sz64 = pci_size(l64, sz64, mask64); | |
234 | ||
235 | if (!sz64) | |
236 | goto fail; | |
237 | ||
cc5499c3 | 238 | if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) { |
865df576 BH |
239 | dev_err(&dev->dev, "reg %x: can't handle 64-bit BAR\n", |
240 | pos); | |
6ac665c6 | 241 | goto fail; |
c7dabef8 BH |
242 | } |
243 | ||
c7dabef8 | 244 | if ((sizeof(resource_size_t) < 8) && l) { |
6ac665c6 MW |
245 | /* Address above 32-bit boundary; disable the BAR */ |
246 | pci_write_config_dword(dev, pos, 0); | |
247 | pci_write_config_dword(dev, pos + 4, 0); | |
5bfa14ed BH |
248 | region.start = 0; |
249 | region.end = sz64; | |
fb127cb9 | 250 | pcibios_bus_to_resource(dev, res, ®ion); |
6ac665c6 | 251 | } else { |
5bfa14ed BH |
252 | region.start = l64; |
253 | region.end = l64 + sz64; | |
fb127cb9 | 254 | pcibios_bus_to_resource(dev, res, ®ion); |
c7dabef8 | 255 | dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n", |
a369c791 | 256 | pos, res); |
6ac665c6 MW |
257 | } |
258 | } else { | |
45aa23b4 | 259 | sz = pci_size(l, sz, mask); |
6ac665c6 | 260 | |
45aa23b4 | 261 | if (!sz) |
6ac665c6 MW |
262 | goto fail; |
263 | ||
5bfa14ed BH |
264 | region.start = l; |
265 | region.end = l + sz; | |
fb127cb9 | 266 | pcibios_bus_to_resource(dev, res, ®ion); |
f393d9b1 | 267 | |
c7dabef8 | 268 | dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n", pos, res); |
6ac665c6 MW |
269 | } |
270 | ||
271 | out: | |
28c6821a | 272 | return (res->flags & IORESOURCE_MEM_64) ? 1 : 0; |
6ac665c6 MW |
273 | fail: |
274 | res->flags = 0; | |
275 | goto out; | |
07eddf3d YL |
276 | } |
277 | ||
1da177e4 LT |
278 | static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) |
279 | { | |
6ac665c6 | 280 | unsigned int pos, reg; |
07eddf3d | 281 | |
6ac665c6 MW |
282 | for (pos = 0; pos < howmany; pos++) { |
283 | struct resource *res = &dev->resource[pos]; | |
1da177e4 | 284 | reg = PCI_BASE_ADDRESS_0 + (pos << 2); |
6ac665c6 | 285 | pos += __pci_read_base(dev, pci_bar_unknown, res, reg); |
1da177e4 | 286 | } |
6ac665c6 | 287 | |
1da177e4 | 288 | if (rom) { |
6ac665c6 | 289 | struct resource *res = &dev->resource[PCI_ROM_RESOURCE]; |
1da177e4 | 290 | dev->rom_base_reg = rom; |
6ac665c6 MW |
291 | res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | |
292 | IORESOURCE_READONLY | IORESOURCE_CACHEABLE | | |
293 | IORESOURCE_SIZEALIGN; | |
294 | __pci_read_base(dev, pci_bar_mem32, res, rom); | |
1da177e4 LT |
295 | } |
296 | } | |
297 | ||
fa27b2d1 | 298 | static void __devinit pci_read_bridge_io(struct pci_bus *child) |
1da177e4 LT |
299 | { |
300 | struct pci_dev *dev = child->self; | |
301 | u8 io_base_lo, io_limit_lo; | |
1da177e4 | 302 | unsigned long base, limit; |
5bfa14ed BH |
303 | struct pci_bus_region region; |
304 | struct resource *res, res2; | |
1da177e4 | 305 | |
1da177e4 LT |
306 | res = child->resource[0]; |
307 | pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); | |
308 | pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); | |
309 | base = (io_base_lo & PCI_IO_RANGE_MASK) << 8; | |
310 | limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8; | |
311 | ||
312 | if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) { | |
313 | u16 io_base_hi, io_limit_hi; | |
314 | pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi); | |
315 | pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi); | |
316 | base |= (io_base_hi << 16); | |
317 | limit |= (io_limit_hi << 16); | |
318 | } | |
319 | ||
cd81e1ea | 320 | if (base && base <= limit) { |
1da177e4 | 321 | res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; |
cf48fb6a | 322 | res2.flags = res->flags; |
5bfa14ed BH |
323 | region.start = base; |
324 | region.end = limit + 0xfff; | |
fb127cb9 | 325 | pcibios_bus_to_resource(dev, &res2, ®ion); |
9d265124 | 326 | if (!res->start) |
5bfa14ed | 327 | res->start = res2.start; |
9d265124 | 328 | if (!res->end) |
5bfa14ed | 329 | res->end = res2.end; |
c7dabef8 | 330 | dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res); |
1da177e4 | 331 | } |
fa27b2d1 BH |
332 | } |
333 | ||
334 | static void __devinit pci_read_bridge_mmio(struct pci_bus *child) | |
335 | { | |
336 | struct pci_dev *dev = child->self; | |
337 | u16 mem_base_lo, mem_limit_lo; | |
338 | unsigned long base, limit; | |
5bfa14ed | 339 | struct pci_bus_region region; |
fa27b2d1 | 340 | struct resource *res; |
1da177e4 LT |
341 | |
342 | res = child->resource[1]; | |
343 | pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo); | |
344 | pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo); | |
345 | base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16; | |
346 | limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16; | |
cd81e1ea | 347 | if (base && base <= limit) { |
1da177e4 | 348 | res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM; |
5bfa14ed BH |
349 | region.start = base; |
350 | region.end = limit + 0xfffff; | |
fb127cb9 | 351 | pcibios_bus_to_resource(dev, res, ®ion); |
c7dabef8 | 352 | dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res); |
1da177e4 | 353 | } |
fa27b2d1 BH |
354 | } |
355 | ||
356 | static void __devinit pci_read_bridge_mmio_pref(struct pci_bus *child) | |
357 | { | |
358 | struct pci_dev *dev = child->self; | |
359 | u16 mem_base_lo, mem_limit_lo; | |
360 | unsigned long base, limit; | |
5bfa14ed | 361 | struct pci_bus_region region; |
fa27b2d1 | 362 | struct resource *res; |
1da177e4 LT |
363 | |
364 | res = child->resource[2]; | |
365 | pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); | |
366 | pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); | |
367 | base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16; | |
368 | limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16; | |
369 | ||
370 | if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { | |
371 | u32 mem_base_hi, mem_limit_hi; | |
372 | pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi); | |
373 | pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi); | |
374 | ||
375 | /* | |
376 | * Some bridges set the base > limit by default, and some | |
377 | * (broken) BIOSes do not initialize them. If we find | |
378 | * this, just assume they are not being used. | |
379 | */ | |
380 | if (mem_base_hi <= mem_limit_hi) { | |
381 | #if BITS_PER_LONG == 64 | |
382 | base |= ((long) mem_base_hi) << 32; | |
383 | limit |= ((long) mem_limit_hi) << 32; | |
384 | #else | |
385 | if (mem_base_hi || mem_limit_hi) { | |
80ccba11 BH |
386 | dev_err(&dev->dev, "can't handle 64-bit " |
387 | "address space for bridge\n"); | |
1da177e4 LT |
388 | return; |
389 | } | |
390 | #endif | |
391 | } | |
392 | } | |
cd81e1ea | 393 | if (base && base <= limit) { |
1f82de10 YL |
394 | res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) | |
395 | IORESOURCE_MEM | IORESOURCE_PREFETCH; | |
396 | if (res->flags & PCI_PREF_RANGE_TYPE_64) | |
397 | res->flags |= IORESOURCE_MEM_64; | |
5bfa14ed BH |
398 | region.start = base; |
399 | region.end = limit + 0xfffff; | |
fb127cb9 | 400 | pcibios_bus_to_resource(dev, res, ®ion); |
c7dabef8 | 401 | dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res); |
1da177e4 LT |
402 | } |
403 | } | |
404 | ||
fa27b2d1 BH |
405 | void __devinit pci_read_bridge_bases(struct pci_bus *child) |
406 | { | |
407 | struct pci_dev *dev = child->self; | |
2fe2abf8 | 408 | struct resource *res; |
fa27b2d1 BH |
409 | int i; |
410 | ||
411 | if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */ | |
412 | return; | |
413 | ||
b918c62e YL |
414 | dev_info(&dev->dev, "PCI bridge to %pR%s\n", |
415 | &child->busn_res, | |
fa27b2d1 BH |
416 | dev->transparent ? " (subtractive decode)" : ""); |
417 | ||
2fe2abf8 BH |
418 | pci_bus_remove_resources(child); |
419 | for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) | |
420 | child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i]; | |
421 | ||
fa27b2d1 BH |
422 | pci_read_bridge_io(child); |
423 | pci_read_bridge_mmio(child); | |
424 | pci_read_bridge_mmio_pref(child); | |
2adf7516 BH |
425 | |
426 | if (dev->transparent) { | |
2fe2abf8 BH |
427 | pci_bus_for_each_resource(child->parent, res, i) { |
428 | if (res) { | |
429 | pci_bus_add_resource(child, res, | |
430 | PCI_SUBTRACTIVE_DECODE); | |
2adf7516 BH |
431 | dev_printk(KERN_DEBUG, &dev->dev, |
432 | " bridge window %pR (subtractive decode)\n", | |
2fe2abf8 BH |
433 | res); |
434 | } | |
2adf7516 BH |
435 | } |
436 | } | |
fa27b2d1 BH |
437 | } |
438 | ||
96bde06a | 439 | static struct pci_bus * pci_alloc_bus(void) |
1da177e4 LT |
440 | { |
441 | struct pci_bus *b; | |
442 | ||
f5afe806 | 443 | b = kzalloc(sizeof(*b), GFP_KERNEL); |
1da177e4 | 444 | if (b) { |
1da177e4 LT |
445 | INIT_LIST_HEAD(&b->node); |
446 | INIT_LIST_HEAD(&b->children); | |
447 | INIT_LIST_HEAD(&b->devices); | |
f46753c5 | 448 | INIT_LIST_HEAD(&b->slots); |
2fe2abf8 | 449 | INIT_LIST_HEAD(&b->resources); |
3749c51a MW |
450 | b->max_bus_speed = PCI_SPEED_UNKNOWN; |
451 | b->cur_bus_speed = PCI_SPEED_UNKNOWN; | |
1da177e4 LT |
452 | } |
453 | return b; | |
454 | } | |
455 | ||
7b543663 YL |
456 | static struct pci_host_bridge *pci_alloc_host_bridge(struct pci_bus *b) |
457 | { | |
458 | struct pci_host_bridge *bridge; | |
459 | ||
460 | bridge = kzalloc(sizeof(*bridge), GFP_KERNEL); | |
461 | if (bridge) { | |
462 | INIT_LIST_HEAD(&bridge->windows); | |
463 | bridge->bus = b; | |
464 | } | |
465 | ||
466 | return bridge; | |
467 | } | |
468 | ||
9be60ca0 MW |
469 | static unsigned char pcix_bus_speed[] = { |
470 | PCI_SPEED_UNKNOWN, /* 0 */ | |
471 | PCI_SPEED_66MHz_PCIX, /* 1 */ | |
472 | PCI_SPEED_100MHz_PCIX, /* 2 */ | |
473 | PCI_SPEED_133MHz_PCIX, /* 3 */ | |
474 | PCI_SPEED_UNKNOWN, /* 4 */ | |
475 | PCI_SPEED_66MHz_PCIX_ECC, /* 5 */ | |
476 | PCI_SPEED_100MHz_PCIX_ECC, /* 6 */ | |
477 | PCI_SPEED_133MHz_PCIX_ECC, /* 7 */ | |
478 | PCI_SPEED_UNKNOWN, /* 8 */ | |
479 | PCI_SPEED_66MHz_PCIX_266, /* 9 */ | |
480 | PCI_SPEED_100MHz_PCIX_266, /* A */ | |
481 | PCI_SPEED_133MHz_PCIX_266, /* B */ | |
482 | PCI_SPEED_UNKNOWN, /* C */ | |
483 | PCI_SPEED_66MHz_PCIX_533, /* D */ | |
484 | PCI_SPEED_100MHz_PCIX_533, /* E */ | |
485 | PCI_SPEED_133MHz_PCIX_533 /* F */ | |
486 | }; | |
487 | ||
3749c51a MW |
488 | static unsigned char pcie_link_speed[] = { |
489 | PCI_SPEED_UNKNOWN, /* 0 */ | |
490 | PCIE_SPEED_2_5GT, /* 1 */ | |
491 | PCIE_SPEED_5_0GT, /* 2 */ | |
9dfd97fe | 492 | PCIE_SPEED_8_0GT, /* 3 */ |
3749c51a MW |
493 | PCI_SPEED_UNKNOWN, /* 4 */ |
494 | PCI_SPEED_UNKNOWN, /* 5 */ | |
495 | PCI_SPEED_UNKNOWN, /* 6 */ | |
496 | PCI_SPEED_UNKNOWN, /* 7 */ | |
497 | PCI_SPEED_UNKNOWN, /* 8 */ | |
498 | PCI_SPEED_UNKNOWN, /* 9 */ | |
499 | PCI_SPEED_UNKNOWN, /* A */ | |
500 | PCI_SPEED_UNKNOWN, /* B */ | |
501 | PCI_SPEED_UNKNOWN, /* C */ | |
502 | PCI_SPEED_UNKNOWN, /* D */ | |
503 | PCI_SPEED_UNKNOWN, /* E */ | |
504 | PCI_SPEED_UNKNOWN /* F */ | |
505 | }; | |
506 | ||
507 | void pcie_update_link_speed(struct pci_bus *bus, u16 linksta) | |
508 | { | |
509 | bus->cur_bus_speed = pcie_link_speed[linksta & 0xf]; | |
510 | } | |
511 | EXPORT_SYMBOL_GPL(pcie_update_link_speed); | |
512 | ||
45b4cdd5 MW |
513 | static unsigned char agp_speeds[] = { |
514 | AGP_UNKNOWN, | |
515 | AGP_1X, | |
516 | AGP_2X, | |
517 | AGP_4X, | |
518 | AGP_8X | |
519 | }; | |
520 | ||
521 | static enum pci_bus_speed agp_speed(int agp3, int agpstat) | |
522 | { | |
523 | int index = 0; | |
524 | ||
525 | if (agpstat & 4) | |
526 | index = 3; | |
527 | else if (agpstat & 2) | |
528 | index = 2; | |
529 | else if (agpstat & 1) | |
530 | index = 1; | |
531 | else | |
532 | goto out; | |
533 | ||
534 | if (agp3) { | |
535 | index += 2; | |
536 | if (index == 5) | |
537 | index = 0; | |
538 | } | |
539 | ||
540 | out: | |
541 | return agp_speeds[index]; | |
542 | } | |
543 | ||
544 | ||
9be60ca0 MW |
545 | static void pci_set_bus_speed(struct pci_bus *bus) |
546 | { | |
547 | struct pci_dev *bridge = bus->self; | |
548 | int pos; | |
549 | ||
45b4cdd5 MW |
550 | pos = pci_find_capability(bridge, PCI_CAP_ID_AGP); |
551 | if (!pos) | |
552 | pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3); | |
553 | if (pos) { | |
554 | u32 agpstat, agpcmd; | |
555 | ||
556 | pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat); | |
557 | bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7); | |
558 | ||
559 | pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd); | |
560 | bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7); | |
561 | } | |
562 | ||
9be60ca0 MW |
563 | pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX); |
564 | if (pos) { | |
565 | u16 status; | |
566 | enum pci_bus_speed max; | |
567 | pci_read_config_word(bridge, pos + 2, &status); | |
568 | ||
569 | if (status & 0x8000) { | |
570 | max = PCI_SPEED_133MHz_PCIX_533; | |
571 | } else if (status & 0x4000) { | |
572 | max = PCI_SPEED_133MHz_PCIX_266; | |
573 | } else if (status & 0x0002) { | |
574 | if (((status >> 12) & 0x3) == 2) { | |
575 | max = PCI_SPEED_133MHz_PCIX_ECC; | |
576 | } else { | |
577 | max = PCI_SPEED_133MHz_PCIX; | |
578 | } | |
579 | } else { | |
580 | max = PCI_SPEED_66MHz_PCIX; | |
581 | } | |
582 | ||
583 | bus->max_bus_speed = max; | |
584 | bus->cur_bus_speed = pcix_bus_speed[(status >> 6) & 0xf]; | |
585 | ||
586 | return; | |
587 | } | |
588 | ||
589 | pos = pci_find_capability(bridge, PCI_CAP_ID_EXP); | |
590 | if (pos) { | |
591 | u32 linkcap; | |
592 | u16 linksta; | |
593 | ||
594 | pci_read_config_dword(bridge, pos + PCI_EXP_LNKCAP, &linkcap); | |
595 | bus->max_bus_speed = pcie_link_speed[linkcap & 0xf]; | |
596 | ||
597 | pci_read_config_word(bridge, pos + PCI_EXP_LNKSTA, &linksta); | |
598 | pcie_update_link_speed(bus, linksta); | |
599 | } | |
600 | } | |
601 | ||
602 | ||
cbd4e055 AB |
603 | static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent, |
604 | struct pci_dev *bridge, int busnr) | |
1da177e4 LT |
605 | { |
606 | struct pci_bus *child; | |
607 | int i; | |
608 | ||
609 | /* | |
610 | * Allocate a new bus, and inherit stuff from the parent.. | |
611 | */ | |
612 | child = pci_alloc_bus(); | |
613 | if (!child) | |
614 | return NULL; | |
615 | ||
1da177e4 LT |
616 | child->parent = parent; |
617 | child->ops = parent->ops; | |
618 | child->sysdata = parent->sysdata; | |
6e325a62 | 619 | child->bus_flags = parent->bus_flags; |
1da177e4 | 620 | |
fd7d1ced GKH |
621 | /* initialize some portions of the bus device, but don't register it |
622 | * now as the parent is not properly set up yet. This device will get | |
623 | * registered later in pci_bus_add_devices() | |
624 | */ | |
625 | child->dev.class = &pcibus_class; | |
1a927133 | 626 | dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr); |
1da177e4 LT |
627 | |
628 | /* | |
629 | * Set up the primary, secondary and subordinate | |
630 | * bus numbers. | |
631 | */ | |
b918c62e YL |
632 | child->number = child->busn_res.start = busnr; |
633 | child->primary = parent->busn_res.start; | |
634 | child->busn_res.end = 0xff; | |
1da177e4 | 635 | |
3789fa8a YZ |
636 | if (!bridge) |
637 | return child; | |
638 | ||
639 | child->self = bridge; | |
640 | child->bridge = get_device(&bridge->dev); | |
98d9f30c | 641 | pci_set_bus_of_node(child); |
9be60ca0 MW |
642 | pci_set_bus_speed(child); |
643 | ||
1da177e4 | 644 | /* Set up default resource pointers and names.. */ |
fde09c6d | 645 | for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { |
1da177e4 LT |
646 | child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i]; |
647 | child->resource[i]->name = child->name; | |
648 | } | |
649 | bridge->subordinate = child; | |
650 | ||
651 | return child; | |
652 | } | |
653 | ||
451124a7 | 654 | struct pci_bus *__ref pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr) |
1da177e4 LT |
655 | { |
656 | struct pci_bus *child; | |
657 | ||
658 | child = pci_alloc_child_bus(parent, dev, busnr); | |
e4ea9bb7 | 659 | if (child) { |
d71374da | 660 | down_write(&pci_bus_sem); |
1da177e4 | 661 | list_add_tail(&child->node, &parent->children); |
d71374da | 662 | up_write(&pci_bus_sem); |
e4ea9bb7 | 663 | } |
1da177e4 LT |
664 | return child; |
665 | } | |
666 | ||
96bde06a | 667 | static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max) |
26f674ae GKH |
668 | { |
669 | struct pci_bus *parent = child->parent; | |
12f44f46 IK |
670 | |
671 | /* Attempts to fix that up are really dangerous unless | |
672 | we're going to re-assign all bus numbers. */ | |
673 | if (!pcibios_assign_all_busses()) | |
674 | return; | |
675 | ||
b918c62e YL |
676 | while (parent->parent && parent->busn_res.end < max) { |
677 | parent->busn_res.end = max; | |
26f674ae GKH |
678 | pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max); |
679 | parent = parent->parent; | |
680 | } | |
681 | } | |
682 | ||
1da177e4 LT |
683 | /* |
684 | * If it's a bridge, configure it and scan the bus behind it. | |
685 | * For CardBus bridges, we don't scan behind as the devices will | |
686 | * be handled by the bridge driver itself. | |
687 | * | |
688 | * We need to process bridges in two passes -- first we scan those | |
689 | * already configured by the BIOS and after we are done with all of | |
690 | * them, we proceed to assigning numbers to the remaining buses in | |
691 | * order to avoid overlaps between old and new bus numbers. | |
692 | */ | |
0ab2b57f | 693 | int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass) |
1da177e4 LT |
694 | { |
695 | struct pci_bus *child; | |
696 | int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS); | |
49887941 | 697 | u32 buses, i, j = 0; |
1da177e4 | 698 | u16 bctl; |
99ddd552 | 699 | u8 primary, secondary, subordinate; |
a1c19894 | 700 | int broken = 0; |
1da177e4 LT |
701 | |
702 | pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses); | |
99ddd552 BH |
703 | primary = buses & 0xFF; |
704 | secondary = (buses >> 8) & 0xFF; | |
705 | subordinate = (buses >> 16) & 0xFF; | |
1da177e4 | 706 | |
99ddd552 BH |
707 | dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n", |
708 | secondary, subordinate, pass); | |
1da177e4 | 709 | |
71f6bd4a YL |
710 | if (!primary && (primary != bus->number) && secondary && subordinate) { |
711 | dev_warn(&dev->dev, "Primary bus is hard wired to 0\n"); | |
712 | primary = bus->number; | |
713 | } | |
714 | ||
a1c19894 BH |
715 | /* Check if setup is sensible at all */ |
716 | if (!pass && | |
99ddd552 | 717 | (primary != bus->number || secondary <= bus->number)) { |
a1c19894 BH |
718 | dev_dbg(&dev->dev, "bus configuration invalid, reconfiguring\n"); |
719 | broken = 1; | |
720 | } | |
721 | ||
1da177e4 LT |
722 | /* Disable MasterAbortMode during probing to avoid reporting |
723 | of bus errors (in some architectures) */ | |
724 | pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl); | |
725 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, | |
726 | bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT); | |
727 | ||
99ddd552 BH |
728 | if ((secondary || subordinate) && !pcibios_assign_all_busses() && |
729 | !is_cardbus && !broken) { | |
730 | unsigned int cmax; | |
1da177e4 LT |
731 | /* |
732 | * Bus already configured by firmware, process it in the first | |
733 | * pass and just note the configuration. | |
734 | */ | |
735 | if (pass) | |
bbe8f9a3 | 736 | goto out; |
1da177e4 LT |
737 | |
738 | /* | |
739 | * If we already got to this bus through a different bridge, | |
74710ded AC |
740 | * don't re-add it. This can happen with the i450NX chipset. |
741 | * | |
742 | * However, we continue to descend down the hierarchy and | |
743 | * scan remaining child buses. | |
1da177e4 | 744 | */ |
99ddd552 | 745 | child = pci_find_bus(pci_domain_nr(bus), secondary); |
74710ded | 746 | if (!child) { |
99ddd552 | 747 | child = pci_add_new_bus(bus, dev, secondary); |
74710ded AC |
748 | if (!child) |
749 | goto out; | |
99ddd552 | 750 | child->primary = primary; |
b918c62e | 751 | child->busn_res.end = subordinate; |
74710ded | 752 | child->bridge_ctl = bctl; |
1da177e4 LT |
753 | } |
754 | ||
1da177e4 LT |
755 | cmax = pci_scan_child_bus(child); |
756 | if (cmax > max) | |
757 | max = cmax; | |
b918c62e YL |
758 | if (child->busn_res.end > max) |
759 | max = child->busn_res.end; | |
1da177e4 LT |
760 | } else { |
761 | /* | |
762 | * We need to assign a number to this bus which we always | |
763 | * do in the second pass. | |
764 | */ | |
12f44f46 | 765 | if (!pass) { |
a1c19894 | 766 | if (pcibios_assign_all_busses() || broken) |
12f44f46 IK |
767 | /* Temporarily disable forwarding of the |
768 | configuration cycles on all bridges in | |
769 | this bus segment to avoid possible | |
770 | conflicts in the second pass between two | |
771 | bridges programmed with overlapping | |
772 | bus ranges. */ | |
773 | pci_write_config_dword(dev, PCI_PRIMARY_BUS, | |
774 | buses & ~0xffffff); | |
bbe8f9a3 | 775 | goto out; |
12f44f46 | 776 | } |
1da177e4 LT |
777 | |
778 | /* Clear errors */ | |
779 | pci_write_config_word(dev, PCI_STATUS, 0xffff); | |
780 | ||
cc57450f | 781 | /* Prevent assigning a bus number that already exists. |
b1a98b69 TC |
782 | * This can happen when a bridge is hot-plugged, so in |
783 | * this case we only re-scan this bus. */ | |
784 | child = pci_find_bus(pci_domain_nr(bus), max+1); | |
785 | if (!child) { | |
786 | child = pci_add_new_bus(bus, dev, ++max); | |
787 | if (!child) | |
788 | goto out; | |
789 | } | |
1da177e4 LT |
790 | buses = (buses & 0xff000000) |
791 | | ((unsigned int)(child->primary) << 0) | |
b918c62e YL |
792 | | ((unsigned int)(child->busn_res.start) << 8) |
793 | | ((unsigned int)(child->busn_res.end) << 16); | |
1da177e4 LT |
794 | |
795 | /* | |
796 | * yenta.c forces a secondary latency timer of 176. | |
797 | * Copy that behaviour here. | |
798 | */ | |
799 | if (is_cardbus) { | |
800 | buses &= ~0xff000000; | |
801 | buses |= CARDBUS_LATENCY_TIMER << 24; | |
802 | } | |
7c867c88 | 803 | |
1da177e4 LT |
804 | /* |
805 | * We need to blast all three values with a single write. | |
806 | */ | |
807 | pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses); | |
808 | ||
809 | if (!is_cardbus) { | |
11949255 | 810 | child->bridge_ctl = bctl; |
26f674ae GKH |
811 | /* |
812 | * Adjust subordinate busnr in parent buses. | |
813 | * We do this before scanning for children because | |
814 | * some devices may not be detected if the bios | |
815 | * was lazy. | |
816 | */ | |
817 | pci_fixup_parent_subordinate_busnr(child, max); | |
1da177e4 LT |
818 | /* Now we can scan all subordinate buses... */ |
819 | max = pci_scan_child_bus(child); | |
e3ac86d8 KA |
820 | /* |
821 | * now fix it up again since we have found | |
822 | * the real value of max. | |
823 | */ | |
824 | pci_fixup_parent_subordinate_busnr(child, max); | |
1da177e4 LT |
825 | } else { |
826 | /* | |
827 | * For CardBus bridges, we leave 4 bus numbers | |
828 | * as cards with a PCI-to-PCI bridge can be | |
829 | * inserted later. | |
830 | */ | |
49887941 DB |
831 | for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) { |
832 | struct pci_bus *parent = bus; | |
cc57450f RS |
833 | if (pci_find_bus(pci_domain_nr(bus), |
834 | max+i+1)) | |
835 | break; | |
49887941 DB |
836 | while (parent->parent) { |
837 | if ((!pcibios_assign_all_busses()) && | |
b918c62e YL |
838 | (parent->busn_res.end > max) && |
839 | (parent->busn_res.end <= max+i)) { | |
49887941 DB |
840 | j = 1; |
841 | } | |
842 | parent = parent->parent; | |
843 | } | |
844 | if (j) { | |
845 | /* | |
846 | * Often, there are two cardbus bridges | |
847 | * -- try to leave one valid bus number | |
848 | * for each one. | |
849 | */ | |
850 | i /= 2; | |
851 | break; | |
852 | } | |
853 | } | |
cc57450f | 854 | max += i; |
26f674ae | 855 | pci_fixup_parent_subordinate_busnr(child, max); |
1da177e4 LT |
856 | } |
857 | /* | |
858 | * Set the subordinate bus number to its real value. | |
859 | */ | |
b918c62e | 860 | child->busn_res.end = max; |
1da177e4 LT |
861 | pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max); |
862 | } | |
863 | ||
cb3576fa GH |
864 | sprintf(child->name, |
865 | (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"), | |
866 | pci_domain_nr(bus), child->number); | |
1da177e4 | 867 | |
d55bef51 | 868 | /* Has only triggered on CardBus, fixup is in yenta_socket */ |
49887941 | 869 | while (bus->parent) { |
b918c62e YL |
870 | if ((child->busn_res.end > bus->busn_res.end) || |
871 | (child->number > bus->busn_res.end) || | |
49887941 | 872 | (child->number < bus->number) || |
b918c62e YL |
873 | (child->busn_res.end < bus->number)) { |
874 | dev_info(&child->dev, "%pR %s " | |
875 | "hidden behind%s bridge %s %pR\n", | |
876 | &child->busn_res, | |
877 | (bus->number > child->busn_res.end && | |
878 | bus->busn_res.end < child->number) ? | |
a6f29a98 JP |
879 | "wholly" : "partially", |
880 | bus->self->transparent ? " transparent" : "", | |
865df576 | 881 | dev_name(&bus->dev), |
b918c62e | 882 | &bus->busn_res); |
49887941 DB |
883 | } |
884 | bus = bus->parent; | |
885 | } | |
886 | ||
bbe8f9a3 RB |
887 | out: |
888 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl); | |
889 | ||
1da177e4 LT |
890 | return max; |
891 | } | |
892 | ||
893 | /* | |
894 | * Read interrupt line and base address registers. | |
895 | * The architecture-dependent code can tweak these, of course. | |
896 | */ | |
897 | static void pci_read_irq(struct pci_dev *dev) | |
898 | { | |
899 | unsigned char irq; | |
900 | ||
901 | pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq); | |
ffeff788 | 902 | dev->pin = irq; |
1da177e4 LT |
903 | if (irq) |
904 | pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); | |
905 | dev->irq = irq; | |
906 | } | |
907 | ||
bb209c82 | 908 | void set_pcie_port_type(struct pci_dev *pdev) |
480b93b7 YZ |
909 | { |
910 | int pos; | |
911 | u16 reg16; | |
912 | ||
913 | pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); | |
914 | if (!pos) | |
915 | return; | |
916 | pdev->is_pcie = 1; | |
0efea000 | 917 | pdev->pcie_cap = pos; |
480b93b7 YZ |
918 | pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); |
919 | pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4; | |
b03e7495 JM |
920 | pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16); |
921 | pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD; | |
480b93b7 YZ |
922 | } |
923 | ||
bb209c82 | 924 | void set_pcie_hotplug_bridge(struct pci_dev *pdev) |
28760489 EB |
925 | { |
926 | int pos; | |
927 | u16 reg16; | |
928 | u32 reg32; | |
929 | ||
06a1cbaf | 930 | pos = pci_pcie_cap(pdev); |
28760489 EB |
931 | if (!pos) |
932 | return; | |
933 | pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); | |
934 | if (!(reg16 & PCI_EXP_FLAGS_SLOT)) | |
935 | return; | |
936 | pci_read_config_dword(pdev, pos + PCI_EXP_SLTCAP, ®32); | |
937 | if (reg32 & PCI_EXP_SLTCAP_HPC) | |
938 | pdev->is_hotplug_bridge = 1; | |
939 | } | |
940 | ||
01abc2aa | 941 | #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED) |
76e6a1d6 | 942 | |
1da177e4 LT |
943 | /** |
944 | * pci_setup_device - fill in class and map information of a device | |
945 | * @dev: the device structure to fill | |
946 | * | |
947 | * Initialize the device structure with information about the device's | |
948 | * vendor,class,memory and IO-space addresses,IRQ lines etc. | |
949 | * Called at initialisation of the PCI subsystem and by CardBus services. | |
480b93b7 YZ |
950 | * Returns 0 on success and negative if unknown type of device (not normal, |
951 | * bridge or CardBus). | |
1da177e4 | 952 | */ |
480b93b7 | 953 | int pci_setup_device(struct pci_dev *dev) |
1da177e4 LT |
954 | { |
955 | u32 class; | |
480b93b7 YZ |
956 | u8 hdr_type; |
957 | struct pci_slot *slot; | |
bc577d2b | 958 | int pos = 0; |
5bfa14ed BH |
959 | struct pci_bus_region region; |
960 | struct resource *res; | |
480b93b7 YZ |
961 | |
962 | if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type)) | |
963 | return -EIO; | |
964 | ||
965 | dev->sysdata = dev->bus->sysdata; | |
966 | dev->dev.parent = dev->bus->bridge; | |
967 | dev->dev.bus = &pci_bus_type; | |
968 | dev->hdr_type = hdr_type & 0x7f; | |
969 | dev->multifunction = !!(hdr_type & 0x80); | |
480b93b7 YZ |
970 | dev->error_state = pci_channel_io_normal; |
971 | set_pcie_port_type(dev); | |
972 | ||
973 | list_for_each_entry(slot, &dev->bus->slots, list) | |
974 | if (PCI_SLOT(dev->devfn) == slot->number) | |
975 | dev->slot = slot; | |
976 | ||
977 | /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer) | |
978 | set this higher, assuming the system even supports it. */ | |
979 | dev->dma_mask = 0xffffffff; | |
1da177e4 | 980 | |
eebfcfb5 GKH |
981 | dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus), |
982 | dev->bus->number, PCI_SLOT(dev->devfn), | |
983 | PCI_FUNC(dev->devfn)); | |
1da177e4 LT |
984 | |
985 | pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); | |
b8a3a521 | 986 | dev->revision = class & 0xff; |
2dd8ba92 | 987 | dev->class = class >> 8; /* upper 3 bytes */ |
1da177e4 | 988 | |
2dd8ba92 YL |
989 | dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %02x class %#08x\n", |
990 | dev->vendor, dev->device, dev->hdr_type, dev->class); | |
1da177e4 | 991 | |
853346e4 YZ |
992 | /* need to have dev->class ready */ |
993 | dev->cfg_size = pci_cfg_space_size(dev); | |
994 | ||
1da177e4 | 995 | /* "Unknown power state" */ |
3fe9d19f | 996 | dev->current_state = PCI_UNKNOWN; |
1da177e4 LT |
997 | |
998 | /* Early fixups, before probing the BARs */ | |
999 | pci_fixup_device(pci_fixup_early, dev); | |
f79b1b14 YZ |
1000 | /* device class may be changed after fixup */ |
1001 | class = dev->class >> 8; | |
1da177e4 LT |
1002 | |
1003 | switch (dev->hdr_type) { /* header type */ | |
1004 | case PCI_HEADER_TYPE_NORMAL: /* standard header */ | |
1005 | if (class == PCI_CLASS_BRIDGE_PCI) | |
1006 | goto bad; | |
1007 | pci_read_irq(dev); | |
1008 | pci_read_bases(dev, 6, PCI_ROM_ADDRESS); | |
1009 | pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); | |
1010 | pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device); | |
368c73d4 AC |
1011 | |
1012 | /* | |
1013 | * Do the ugly legacy mode stuff here rather than broken chip | |
1014 | * quirk code. Legacy mode ATA controllers have fixed | |
1015 | * addresses. These are not always echoed in BAR0-3, and | |
1016 | * BAR0-3 in a few cases contain junk! | |
1017 | */ | |
1018 | if (class == PCI_CLASS_STORAGE_IDE) { | |
1019 | u8 progif; | |
1020 | pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); | |
1021 | if ((progif & 1) == 0) { | |
5bfa14ed BH |
1022 | region.start = 0x1F0; |
1023 | region.end = 0x1F7; | |
1024 | res = &dev->resource[0]; | |
1025 | res->flags = LEGACY_IO_RESOURCE; | |
fb127cb9 | 1026 | pcibios_bus_to_resource(dev, res, ®ion); |
5bfa14ed BH |
1027 | region.start = 0x3F6; |
1028 | region.end = 0x3F6; | |
1029 | res = &dev->resource[1]; | |
1030 | res->flags = LEGACY_IO_RESOURCE; | |
fb127cb9 | 1031 | pcibios_bus_to_resource(dev, res, ®ion); |
368c73d4 AC |
1032 | } |
1033 | if ((progif & 4) == 0) { | |
5bfa14ed BH |
1034 | region.start = 0x170; |
1035 | region.end = 0x177; | |
1036 | res = &dev->resource[2]; | |
1037 | res->flags = LEGACY_IO_RESOURCE; | |
fb127cb9 | 1038 | pcibios_bus_to_resource(dev, res, ®ion); |
5bfa14ed BH |
1039 | region.start = 0x376; |
1040 | region.end = 0x376; | |
1041 | res = &dev->resource[3]; | |
1042 | res->flags = LEGACY_IO_RESOURCE; | |
fb127cb9 | 1043 | pcibios_bus_to_resource(dev, res, ®ion); |
368c73d4 AC |
1044 | } |
1045 | } | |
1da177e4 LT |
1046 | break; |
1047 | ||
1048 | case PCI_HEADER_TYPE_BRIDGE: /* bridge header */ | |
1049 | if (class != PCI_CLASS_BRIDGE_PCI) | |
1050 | goto bad; | |
1051 | /* The PCI-to-PCI bridge spec requires that subtractive | |
1052 | decoding (i.e. transparent) bridge must have programming | |
1053 | interface code of 0x01. */ | |
3efd273b | 1054 | pci_read_irq(dev); |
1da177e4 LT |
1055 | dev->transparent = ((dev->class & 0xff) == 1); |
1056 | pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); | |
28760489 | 1057 | set_pcie_hotplug_bridge(dev); |
bc577d2b GB |
1058 | pos = pci_find_capability(dev, PCI_CAP_ID_SSVID); |
1059 | if (pos) { | |
1060 | pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor); | |
1061 | pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device); | |
1062 | } | |
1da177e4 LT |
1063 | break; |
1064 | ||
1065 | case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */ | |
1066 | if (class != PCI_CLASS_BRIDGE_CARDBUS) | |
1067 | goto bad; | |
1068 | pci_read_irq(dev); | |
1069 | pci_read_bases(dev, 1, 0); | |
1070 | pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); | |
1071 | pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device); | |
1072 | break; | |
1073 | ||
1074 | default: /* unknown header */ | |
80ccba11 BH |
1075 | dev_err(&dev->dev, "unknown header type %02x, " |
1076 | "ignoring device\n", dev->hdr_type); | |
480b93b7 | 1077 | return -EIO; |
1da177e4 LT |
1078 | |
1079 | bad: | |
2dd8ba92 YL |
1080 | dev_err(&dev->dev, "ignoring class %#08x (doesn't match header " |
1081 | "type %02x)\n", dev->class, dev->hdr_type); | |
1da177e4 LT |
1082 | dev->class = PCI_CLASS_NOT_DEFINED; |
1083 | } | |
1084 | ||
1085 | /* We found a fine healthy device, go go go... */ | |
1086 | return 0; | |
1087 | } | |
1088 | ||
201de56e ZY |
1089 | static void pci_release_capabilities(struct pci_dev *dev) |
1090 | { | |
1091 | pci_vpd_release(dev); | |
d1b054da | 1092 | pci_iov_release(dev); |
f796841e | 1093 | pci_free_cap_save_buffers(dev); |
201de56e ZY |
1094 | } |
1095 | ||
1da177e4 LT |
1096 | /** |
1097 | * pci_release_dev - free a pci device structure when all users of it are finished. | |
1098 | * @dev: device that's been disconnected | |
1099 | * | |
1100 | * Will be called only by the device core when all users of this pci device are | |
1101 | * done. | |
1102 | */ | |
1103 | static void pci_release_dev(struct device *dev) | |
1104 | { | |
1105 | struct pci_dev *pci_dev; | |
1106 | ||
1107 | pci_dev = to_pci_dev(dev); | |
201de56e | 1108 | pci_release_capabilities(pci_dev); |
98d9f30c | 1109 | pci_release_of_node(pci_dev); |
1da177e4 LT |
1110 | kfree(pci_dev); |
1111 | } | |
1112 | ||
1113 | /** | |
1114 | * pci_cfg_space_size - get the configuration space size of the PCI device. | |
8f7020d3 | 1115 | * @dev: PCI device |
1da177e4 LT |
1116 | * |
1117 | * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices | |
1118 | * have 4096 bytes. Even if the device is capable, that doesn't mean we can | |
1119 | * access it. Maybe we don't have a way to generate extended config space | |
1120 | * accesses, or the device is behind a reverse Express bridge. So we try | |
1121 | * reading the dword at 0x100 which must either be 0 or a valid extended | |
1122 | * capability header. | |
1123 | */ | |
70b9f7dc | 1124 | int pci_cfg_space_size_ext(struct pci_dev *dev) |
1da177e4 | 1125 | { |
1da177e4 | 1126 | u32 status; |
557848c3 | 1127 | int pos = PCI_CFG_SPACE_SIZE; |
1da177e4 | 1128 | |
557848c3 | 1129 | if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL) |
70b9f7dc YL |
1130 | goto fail; |
1131 | if (status == 0xffffffff) | |
1132 | goto fail; | |
1133 | ||
1134 | return PCI_CFG_SPACE_EXP_SIZE; | |
1135 | ||
1136 | fail: | |
1137 | return PCI_CFG_SPACE_SIZE; | |
1138 | } | |
1139 | ||
1140 | int pci_cfg_space_size(struct pci_dev *dev) | |
1141 | { | |
1142 | int pos; | |
1143 | u32 status; | |
dfadd9ed YL |
1144 | u16 class; |
1145 | ||
1146 | class = dev->class >> 8; | |
1147 | if (class == PCI_CLASS_BRIDGE_HOST) | |
1148 | return pci_cfg_space_size_ext(dev); | |
57741a77 | 1149 | |
06a1cbaf | 1150 | pos = pci_pcie_cap(dev); |
1da177e4 LT |
1151 | if (!pos) { |
1152 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
1153 | if (!pos) | |
1154 | goto fail; | |
1155 | ||
1156 | pci_read_config_dword(dev, pos + PCI_X_STATUS, &status); | |
1157 | if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))) | |
1158 | goto fail; | |
1159 | } | |
1160 | ||
70b9f7dc | 1161 | return pci_cfg_space_size_ext(dev); |
1da177e4 LT |
1162 | |
1163 | fail: | |
1164 | return PCI_CFG_SPACE_SIZE; | |
1165 | } | |
1166 | ||
1167 | static void pci_release_bus_bridge_dev(struct device *dev) | |
1168 | { | |
7b543663 YL |
1169 | struct pci_host_bridge *bridge = to_pci_host_bridge(dev); |
1170 | ||
4fa2649a YL |
1171 | if (bridge->release_fn) |
1172 | bridge->release_fn(bridge); | |
7b543663 YL |
1173 | |
1174 | pci_free_resource_list(&bridge->windows); | |
1175 | ||
1176 | kfree(bridge); | |
1da177e4 LT |
1177 | } |
1178 | ||
65891215 ME |
1179 | struct pci_dev *alloc_pci_dev(void) |
1180 | { | |
1181 | struct pci_dev *dev; | |
1182 | ||
1183 | dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL); | |
1184 | if (!dev) | |
1185 | return NULL; | |
1186 | ||
65891215 ME |
1187 | INIT_LIST_HEAD(&dev->bus_list); |
1188 | ||
1189 | return dev; | |
1190 | } | |
1191 | EXPORT_SYMBOL(alloc_pci_dev); | |
1192 | ||
efdc87da YL |
1193 | bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l, |
1194 | int crs_timeout) | |
1da177e4 | 1195 | { |
1da177e4 LT |
1196 | int delay = 1; |
1197 | ||
efdc87da YL |
1198 | if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l)) |
1199 | return false; | |
1da177e4 LT |
1200 | |
1201 | /* some broken boards return 0 or ~0 if a slot is empty: */ | |
efdc87da YL |
1202 | if (*l == 0xffffffff || *l == 0x00000000 || |
1203 | *l == 0x0000ffff || *l == 0xffff0000) | |
1204 | return false; | |
1da177e4 LT |
1205 | |
1206 | /* Configuration request Retry Status */ | |
efdc87da YL |
1207 | while (*l == 0xffff0001) { |
1208 | if (!crs_timeout) | |
1209 | return false; | |
1210 | ||
1da177e4 LT |
1211 | msleep(delay); |
1212 | delay *= 2; | |
efdc87da YL |
1213 | if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l)) |
1214 | return false; | |
1da177e4 | 1215 | /* Card hasn't responded in 60 seconds? Must be stuck. */ |
efdc87da | 1216 | if (delay > crs_timeout) { |
80ccba11 | 1217 | printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not " |
1da177e4 LT |
1218 | "responding\n", pci_domain_nr(bus), |
1219 | bus->number, PCI_SLOT(devfn), | |
1220 | PCI_FUNC(devfn)); | |
efdc87da | 1221 | return false; |
1da177e4 LT |
1222 | } |
1223 | } | |
1224 | ||
efdc87da YL |
1225 | return true; |
1226 | } | |
1227 | EXPORT_SYMBOL(pci_bus_read_dev_vendor_id); | |
1228 | ||
1229 | /* | |
1230 | * Read the config data for a PCI device, sanity-check it | |
1231 | * and fill in the dev structure... | |
1232 | */ | |
1233 | static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn) | |
1234 | { | |
1235 | struct pci_dev *dev; | |
1236 | u32 l; | |
1237 | ||
1238 | if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000)) | |
1239 | return NULL; | |
1240 | ||
bab41e9b | 1241 | dev = alloc_pci_dev(); |
1da177e4 LT |
1242 | if (!dev) |
1243 | return NULL; | |
1244 | ||
1da177e4 | 1245 | dev->bus = bus; |
1da177e4 | 1246 | dev->devfn = devfn; |
1da177e4 LT |
1247 | dev->vendor = l & 0xffff; |
1248 | dev->device = (l >> 16) & 0xffff; | |
cef354db | 1249 | |
98d9f30c BH |
1250 | pci_set_of_node(dev); |
1251 | ||
480b93b7 | 1252 | if (pci_setup_device(dev)) { |
1da177e4 LT |
1253 | kfree(dev); |
1254 | return NULL; | |
1255 | } | |
1da177e4 LT |
1256 | |
1257 | return dev; | |
1258 | } | |
1259 | ||
201de56e ZY |
1260 | static void pci_init_capabilities(struct pci_dev *dev) |
1261 | { | |
1262 | /* MSI/MSI-X list */ | |
1263 | pci_msi_init_pci_dev(dev); | |
1264 | ||
63f4898a RW |
1265 | /* Buffers for saving PCIe and PCI-X capabilities */ |
1266 | pci_allocate_cap_save_buffers(dev); | |
1267 | ||
201de56e ZY |
1268 | /* Power Management */ |
1269 | pci_pm_init(dev); | |
eb9c39d0 | 1270 | platform_pci_wakeup_init(dev); |
201de56e ZY |
1271 | |
1272 | /* Vital Product Data */ | |
1273 | pci_vpd_pci22_init(dev); | |
58c3a727 YZ |
1274 | |
1275 | /* Alternative Routing-ID Forwarding */ | |
1276 | pci_enable_ari(dev); | |
d1b054da YZ |
1277 | |
1278 | /* Single Root I/O Virtualization */ | |
1279 | pci_iov_init(dev); | |
ae21ee65 AK |
1280 | |
1281 | /* Enable ACS P2P upstream forwarding */ | |
5d990b62 | 1282 | pci_enable_acs(dev); |
201de56e ZY |
1283 | } |
1284 | ||
96bde06a | 1285 | void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) |
1da177e4 | 1286 | { |
cdb9b9f7 PM |
1287 | device_initialize(&dev->dev); |
1288 | dev->dev.release = pci_release_dev; | |
1289 | pci_dev_get(dev); | |
1da177e4 | 1290 | |
cdb9b9f7 | 1291 | dev->dev.dma_mask = &dev->dma_mask; |
4d57cdfa | 1292 | dev->dev.dma_parms = &dev->dma_parms; |
cdb9b9f7 | 1293 | dev->dev.coherent_dma_mask = 0xffffffffull; |
1da177e4 | 1294 | |
4d57cdfa | 1295 | pci_set_dma_max_seg_size(dev, 65536); |
59fc67de | 1296 | pci_set_dma_seg_boundary(dev, 0xffffffff); |
4d57cdfa | 1297 | |
1da177e4 LT |
1298 | /* Fix up broken headers */ |
1299 | pci_fixup_device(pci_fixup_header, dev); | |
1300 | ||
2069ecfb YL |
1301 | /* moved out from quirk header fixup code */ |
1302 | pci_reassigndev_resource_alignment(dev); | |
1303 | ||
4b77b0a2 RW |
1304 | /* Clear the state_saved flag. */ |
1305 | dev->state_saved = false; | |
1306 | ||
201de56e ZY |
1307 | /* Initialize various capabilities */ |
1308 | pci_init_capabilities(dev); | |
eb9d0fe4 | 1309 | |
1da177e4 LT |
1310 | /* |
1311 | * Add the device to our list of discovered devices | |
1312 | * and the bus list for fixup functions, etc. | |
1313 | */ | |
d71374da | 1314 | down_write(&pci_bus_sem); |
1da177e4 | 1315 | list_add_tail(&dev->bus_list, &bus->devices); |
d71374da | 1316 | up_write(&pci_bus_sem); |
cdb9b9f7 PM |
1317 | } |
1318 | ||
451124a7 | 1319 | struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn) |
cdb9b9f7 PM |
1320 | { |
1321 | struct pci_dev *dev; | |
1322 | ||
90bdb311 TP |
1323 | dev = pci_get_slot(bus, devfn); |
1324 | if (dev) { | |
1325 | pci_dev_put(dev); | |
1326 | return dev; | |
1327 | } | |
1328 | ||
cdb9b9f7 PM |
1329 | dev = pci_scan_device(bus, devfn); |
1330 | if (!dev) | |
1331 | return NULL; | |
1332 | ||
1333 | pci_device_add(dev, bus); | |
1da177e4 LT |
1334 | |
1335 | return dev; | |
1336 | } | |
b73e9687 | 1337 | EXPORT_SYMBOL(pci_scan_single_device); |
1da177e4 | 1338 | |
f07852d6 MW |
1339 | static unsigned next_ari_fn(struct pci_dev *dev, unsigned fn) |
1340 | { | |
1341 | u16 cap; | |
4fb88c1a MW |
1342 | unsigned pos, next_fn; |
1343 | ||
1344 | if (!dev) | |
1345 | return 0; | |
1346 | ||
1347 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI); | |
f07852d6 MW |
1348 | if (!pos) |
1349 | return 0; | |
1350 | pci_read_config_word(dev, pos + 4, &cap); | |
4fb88c1a MW |
1351 | next_fn = cap >> 8; |
1352 | if (next_fn <= fn) | |
1353 | return 0; | |
1354 | return next_fn; | |
f07852d6 MW |
1355 | } |
1356 | ||
1357 | static unsigned next_trad_fn(struct pci_dev *dev, unsigned fn) | |
1358 | { | |
1359 | return (fn + 1) % 8; | |
1360 | } | |
1361 | ||
1362 | static unsigned no_next_fn(struct pci_dev *dev, unsigned fn) | |
1363 | { | |
1364 | return 0; | |
1365 | } | |
1366 | ||
1367 | static int only_one_child(struct pci_bus *bus) | |
1368 | { | |
1369 | struct pci_dev *parent = bus->self; | |
284f5f9d | 1370 | |
f07852d6 MW |
1371 | if (!parent || !pci_is_pcie(parent)) |
1372 | return 0; | |
284f5f9d BH |
1373 | if (parent->pcie_type == PCI_EXP_TYPE_ROOT_PORT) |
1374 | return 1; | |
1375 | if (parent->pcie_type == PCI_EXP_TYPE_DOWNSTREAM && | |
1376 | !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS)) | |
f07852d6 MW |
1377 | return 1; |
1378 | return 0; | |
1379 | } | |
1380 | ||
1da177e4 LT |
1381 | /** |
1382 | * pci_scan_slot - scan a PCI slot on a bus for devices. | |
1383 | * @bus: PCI bus to scan | |
1384 | * @devfn: slot number to scan (must have zero function.) | |
1385 | * | |
1386 | * Scan a PCI slot on the specified PCI bus for devices, adding | |
1387 | * discovered devices to the @bus->devices list. New devices | |
8a1bc901 | 1388 | * will not have is_added set. |
1b69dfc6 TP |
1389 | * |
1390 | * Returns the number of new devices found. | |
1da177e4 | 1391 | */ |
96bde06a | 1392 | int pci_scan_slot(struct pci_bus *bus, int devfn) |
1da177e4 | 1393 | { |
f07852d6 | 1394 | unsigned fn, nr = 0; |
1b69dfc6 | 1395 | struct pci_dev *dev; |
f07852d6 MW |
1396 | unsigned (*next_fn)(struct pci_dev *, unsigned) = no_next_fn; |
1397 | ||
1398 | if (only_one_child(bus) && (devfn > 0)) | |
1399 | return 0; /* Already scanned the entire slot */ | |
1da177e4 | 1400 | |
1b69dfc6 | 1401 | dev = pci_scan_single_device(bus, devfn); |
4fb88c1a MW |
1402 | if (!dev) |
1403 | return 0; | |
1404 | if (!dev->is_added) | |
1b69dfc6 TP |
1405 | nr++; |
1406 | ||
f07852d6 MW |
1407 | if (pci_ari_enabled(bus)) |
1408 | next_fn = next_ari_fn; | |
4fb88c1a | 1409 | else if (dev->multifunction) |
f07852d6 MW |
1410 | next_fn = next_trad_fn; |
1411 | ||
1412 | for (fn = next_fn(dev, 0); fn > 0; fn = next_fn(dev, fn)) { | |
1413 | dev = pci_scan_single_device(bus, devfn + fn); | |
1414 | if (dev) { | |
1415 | if (!dev->is_added) | |
1416 | nr++; | |
1417 | dev->multifunction = 1; | |
1da177e4 LT |
1418 | } |
1419 | } | |
7d715a6c | 1420 | |
149e1637 SL |
1421 | /* only one slot has pcie device */ |
1422 | if (bus->self && nr) | |
7d715a6c SL |
1423 | pcie_aspm_init_link_state(bus->self); |
1424 | ||
1da177e4 LT |
1425 | return nr; |
1426 | } | |
1427 | ||
b03e7495 JM |
1428 | static int pcie_find_smpss(struct pci_dev *dev, void *data) |
1429 | { | |
1430 | u8 *smpss = data; | |
1431 | ||
1432 | if (!pci_is_pcie(dev)) | |
1433 | return 0; | |
1434 | ||
1435 | /* For PCIE hotplug enabled slots not connected directly to a | |
1436 | * PCI-E root port, there can be problems when hotplugging | |
1437 | * devices. This is due to the possibility of hotplugging a | |
1438 | * device into the fabric with a smaller MPS that the devices | |
1439 | * currently running have configured. Modifying the MPS on the | |
1440 | * running devices could cause a fatal bus error due to an | |
1441 | * incoming frame being larger than the newly configured MPS. | |
1442 | * To work around this, the MPS for the entire fabric must be | |
1443 | * set to the minimum size. Any devices hotplugged into this | |
1444 | * fabric will have the minimum MPS set. If the PCI hotplug | |
1445 | * slot is directly connected to the root port and there are not | |
1446 | * other devices on the fabric (which seems to be the most | |
1447 | * common case), then this is not an issue and MPS discovery | |
1448 | * will occur as normal. | |
1449 | */ | |
1450 | if (dev->is_hotplug_bridge && (!list_is_singular(&dev->bus->devices) || | |
1a4b1a41 BH |
1451 | (dev->bus->self && |
1452 | dev->bus->self->pcie_type != PCI_EXP_TYPE_ROOT_PORT))) | |
b03e7495 JM |
1453 | *smpss = 0; |
1454 | ||
1455 | if (*smpss > dev->pcie_mpss) | |
1456 | *smpss = dev->pcie_mpss; | |
1457 | ||
1458 | return 0; | |
1459 | } | |
1460 | ||
1461 | static void pcie_write_mps(struct pci_dev *dev, int mps) | |
1462 | { | |
62f392ea | 1463 | int rc; |
b03e7495 JM |
1464 | |
1465 | if (pcie_bus_config == PCIE_BUS_PERFORMANCE) { | |
62f392ea | 1466 | mps = 128 << dev->pcie_mpss; |
b03e7495 | 1467 | |
62f392ea JM |
1468 | if (dev->pcie_type != PCI_EXP_TYPE_ROOT_PORT && dev->bus->self) |
1469 | /* For "Performance", the assumption is made that | |
b03e7495 JM |
1470 | * downstream communication will never be larger than |
1471 | * the MRRS. So, the MPS only needs to be configured | |
1472 | * for the upstream communication. This being the case, | |
1473 | * walk from the top down and set the MPS of the child | |
1474 | * to that of the parent bus. | |
62f392ea JM |
1475 | * |
1476 | * Configure the device MPS with the smaller of the | |
1477 | * device MPSS or the bridge MPS (which is assumed to be | |
1478 | * properly configured at this point to the largest | |
1479 | * allowable MPS based on its parent bus). | |
b03e7495 | 1480 | */ |
62f392ea | 1481 | mps = min(mps, pcie_get_mps(dev->bus->self)); |
b03e7495 JM |
1482 | } |
1483 | ||
1484 | rc = pcie_set_mps(dev, mps); | |
1485 | if (rc) | |
1486 | dev_err(&dev->dev, "Failed attempting to set the MPS\n"); | |
1487 | } | |
1488 | ||
62f392ea | 1489 | static void pcie_write_mrrs(struct pci_dev *dev) |
b03e7495 | 1490 | { |
62f392ea | 1491 | int rc, mrrs; |
b03e7495 | 1492 | |
ed2888e9 JM |
1493 | /* In the "safe" case, do not configure the MRRS. There appear to be |
1494 | * issues with setting MRRS to 0 on a number of devices. | |
1495 | */ | |
ed2888e9 JM |
1496 | if (pcie_bus_config != PCIE_BUS_PERFORMANCE) |
1497 | return; | |
1498 | ||
ed2888e9 JM |
1499 | /* For Max performance, the MRRS must be set to the largest supported |
1500 | * value. However, it cannot be configured larger than the MPS the | |
62f392ea JM |
1501 | * device or the bus can support. This should already be properly |
1502 | * configured by a prior call to pcie_write_mps. | |
ed2888e9 | 1503 | */ |
62f392ea | 1504 | mrrs = pcie_get_mps(dev); |
b03e7495 JM |
1505 | |
1506 | /* MRRS is a R/W register. Invalid values can be written, but a | |
ed2888e9 | 1507 | * subsequent read will verify if the value is acceptable or not. |
b03e7495 JM |
1508 | * If the MRRS value provided is not acceptable (e.g., too large), |
1509 | * shrink the value until it is acceptable to the HW. | |
1510 | */ | |
1511 | while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) { | |
1512 | rc = pcie_set_readrq(dev, mrrs); | |
62f392ea JM |
1513 | if (!rc) |
1514 | break; | |
b03e7495 | 1515 | |
62f392ea | 1516 | dev_warn(&dev->dev, "Failed attempting to set the MRRS\n"); |
b03e7495 JM |
1517 | mrrs /= 2; |
1518 | } | |
62f392ea JM |
1519 | |
1520 | if (mrrs < 128) | |
1521 | dev_err(&dev->dev, "MRRS was unable to be configured with a " | |
1522 | "safe value. If problems are experienced, try running " | |
1523 | "with pci=pcie_bus_safe.\n"); | |
b03e7495 JM |
1524 | } |
1525 | ||
1526 | static int pcie_bus_configure_set(struct pci_dev *dev, void *data) | |
1527 | { | |
a513a99a | 1528 | int mps, orig_mps; |
b03e7495 JM |
1529 | |
1530 | if (!pci_is_pcie(dev)) | |
1531 | return 0; | |
1532 | ||
a513a99a JM |
1533 | mps = 128 << *(u8 *)data; |
1534 | orig_mps = pcie_get_mps(dev); | |
b03e7495 JM |
1535 | |
1536 | pcie_write_mps(dev, mps); | |
62f392ea | 1537 | pcie_write_mrrs(dev); |
b03e7495 | 1538 | |
a513a99a JM |
1539 | dev_info(&dev->dev, "PCI-E Max Payload Size set to %4d/%4d (was %4d), " |
1540 | "Max Read Rq %4d\n", pcie_get_mps(dev), 128 << dev->pcie_mpss, | |
1541 | orig_mps, pcie_get_readrq(dev)); | |
b03e7495 JM |
1542 | |
1543 | return 0; | |
1544 | } | |
1545 | ||
a513a99a | 1546 | /* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down, |
b03e7495 JM |
1547 | * parents then children fashion. If this changes, then this code will not |
1548 | * work as designed. | |
1549 | */ | |
1550 | void pcie_bus_configure_settings(struct pci_bus *bus, u8 mpss) | |
1551 | { | |
5f39e670 | 1552 | u8 smpss; |
b03e7495 | 1553 | |
b03e7495 JM |
1554 | if (!pci_is_pcie(bus->self)) |
1555 | return; | |
1556 | ||
5f39e670 JM |
1557 | if (pcie_bus_config == PCIE_BUS_TUNE_OFF) |
1558 | return; | |
1559 | ||
1560 | /* FIXME - Peer to peer DMA is possible, though the endpoint would need | |
1561 | * to be aware to the MPS of the destination. To work around this, | |
1562 | * simply force the MPS of the entire system to the smallest possible. | |
1563 | */ | |
1564 | if (pcie_bus_config == PCIE_BUS_PEER2PEER) | |
1565 | smpss = 0; | |
1566 | ||
b03e7495 | 1567 | if (pcie_bus_config == PCIE_BUS_SAFE) { |
5f39e670 JM |
1568 | smpss = mpss; |
1569 | ||
b03e7495 JM |
1570 | pcie_find_smpss(bus->self, &smpss); |
1571 | pci_walk_bus(bus, pcie_find_smpss, &smpss); | |
1572 | } | |
1573 | ||
1574 | pcie_bus_configure_set(bus->self, &smpss); | |
1575 | pci_walk_bus(bus, pcie_bus_configure_set, &smpss); | |
1576 | } | |
debc3b77 | 1577 | EXPORT_SYMBOL_GPL(pcie_bus_configure_settings); |
b03e7495 | 1578 | |
0ab2b57f | 1579 | unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus) |
1da177e4 | 1580 | { |
b918c62e | 1581 | unsigned int devfn, pass, max = bus->busn_res.start; |
1da177e4 LT |
1582 | struct pci_dev *dev; |
1583 | ||
0207c356 | 1584 | dev_dbg(&bus->dev, "scanning bus\n"); |
1da177e4 LT |
1585 | |
1586 | /* Go find them, Rover! */ | |
1587 | for (devfn = 0; devfn < 0x100; devfn += 8) | |
1588 | pci_scan_slot(bus, devfn); | |
1589 | ||
a28724b0 YZ |
1590 | /* Reserve buses for SR-IOV capability. */ |
1591 | max += pci_iov_bus_range(bus); | |
1592 | ||
1da177e4 LT |
1593 | /* |
1594 | * After performing arch-dependent fixup of the bus, look behind | |
1595 | * all PCI-to-PCI bridges on this bus. | |
1596 | */ | |
74710ded | 1597 | if (!bus->is_added) { |
0207c356 | 1598 | dev_dbg(&bus->dev, "fixups for bus\n"); |
74710ded AC |
1599 | pcibios_fixup_bus(bus); |
1600 | if (pci_is_root_bus(bus)) | |
1601 | bus->is_added = 1; | |
1602 | } | |
1603 | ||
1da177e4 LT |
1604 | for (pass=0; pass < 2; pass++) |
1605 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1606 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || | |
1607 | dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) | |
1608 | max = pci_scan_bridge(bus, dev, max, pass); | |
1609 | } | |
1610 | ||
1611 | /* | |
1612 | * We've scanned the bus and so we know all about what's on | |
1613 | * the other side of any bridges that may be on this bus plus | |
1614 | * any devices. | |
1615 | * | |
1616 | * Return how far we've got finding sub-buses. | |
1617 | */ | |
0207c356 | 1618 | dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max); |
1da177e4 LT |
1619 | return max; |
1620 | } | |
1621 | ||
166c6370 BH |
1622 | struct pci_bus *pci_create_root_bus(struct device *parent, int bus, |
1623 | struct pci_ops *ops, void *sysdata, struct list_head *resources) | |
1da177e4 | 1624 | { |
0efd5aab | 1625 | int error; |
5a21d70d | 1626 | struct pci_host_bridge *bridge; |
0207c356 | 1627 | struct pci_bus *b, *b2; |
0efd5aab | 1628 | struct pci_host_bridge_window *window, *n; |
a9d9f527 | 1629 | struct resource *res; |
0efd5aab BH |
1630 | resource_size_t offset; |
1631 | char bus_addr[64]; | |
1632 | char *fmt; | |
1da177e4 | 1633 | |
5a21d70d | 1634 | |
1da177e4 LT |
1635 | b = pci_alloc_bus(); |
1636 | if (!b) | |
7b543663 | 1637 | return NULL; |
1da177e4 LT |
1638 | |
1639 | b->sysdata = sysdata; | |
1640 | b->ops = ops; | |
0207c356 BH |
1641 | b2 = pci_find_bus(pci_domain_nr(b), bus); |
1642 | if (b2) { | |
1da177e4 | 1643 | /* If we already got to this bus through a different bridge, ignore it */ |
0207c356 | 1644 | dev_dbg(&b2->dev, "bus already known\n"); |
1da177e4 LT |
1645 | goto err_out; |
1646 | } | |
d71374da | 1647 | |
7b543663 YL |
1648 | bridge = pci_alloc_host_bridge(b); |
1649 | if (!bridge) | |
1650 | goto err_out; | |
1651 | ||
1652 | bridge->dev.parent = parent; | |
1653 | bridge->dev.release = pci_release_bus_bridge_dev; | |
1654 | dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(b), bus); | |
1655 | error = device_register(&bridge->dev); | |
1da177e4 | 1656 | if (error) |
7b543663 YL |
1657 | goto bridge_dev_reg_err; |
1658 | b->bridge = get_device(&bridge->dev); | |
a1e4d72c | 1659 | device_enable_async_suspend(b->bridge); |
98d9f30c | 1660 | pci_set_bus_of_node(b); |
1da177e4 | 1661 | |
0d358f22 YL |
1662 | if (!parent) |
1663 | set_dev_node(b->bridge, pcibus_to_node(b)); | |
1664 | ||
fd7d1ced GKH |
1665 | b->dev.class = &pcibus_class; |
1666 | b->dev.parent = b->bridge; | |
1a927133 | 1667 | dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus); |
fd7d1ced | 1668 | error = device_register(&b->dev); |
1da177e4 LT |
1669 | if (error) |
1670 | goto class_dev_reg_err; | |
1da177e4 LT |
1671 | |
1672 | /* Create legacy_io and legacy_mem files for this bus */ | |
1673 | pci_create_legacy_files(b); | |
1674 | ||
b918c62e | 1675 | b->number = b->busn_res.start = bus; |
166c6370 | 1676 | |
a9d9f527 BH |
1677 | if (parent) |
1678 | dev_info(parent, "PCI host bridge to bus %s\n", dev_name(&b->dev)); | |
1679 | else | |
1680 | printk(KERN_INFO "PCI host bridge to bus %s\n", dev_name(&b->dev)); | |
1681 | ||
0efd5aab BH |
1682 | /* Add initial resources to the bus */ |
1683 | list_for_each_entry_safe(window, n, resources, list) { | |
1684 | list_move_tail(&window->list, &bridge->windows); | |
1685 | res = window->res; | |
1686 | offset = window->offset; | |
f848ffb1 YL |
1687 | if (res->flags & IORESOURCE_BUS) |
1688 | pci_bus_insert_busn_res(b, bus, res->end); | |
1689 | else | |
1690 | pci_bus_add_resource(b, res, 0); | |
0efd5aab BH |
1691 | if (offset) { |
1692 | if (resource_type(res) == IORESOURCE_IO) | |
1693 | fmt = " (bus address [%#06llx-%#06llx])"; | |
1694 | else | |
1695 | fmt = " (bus address [%#010llx-%#010llx])"; | |
1696 | snprintf(bus_addr, sizeof(bus_addr), fmt, | |
1697 | (unsigned long long) (res->start - offset), | |
1698 | (unsigned long long) (res->end - offset)); | |
1699 | } else | |
1700 | bus_addr[0] = '\0'; | |
1701 | dev_info(&b->dev, "root bus resource %pR%s\n", res, bus_addr); | |
a9d9f527 BH |
1702 | } |
1703 | ||
a5390aa6 BH |
1704 | down_write(&pci_bus_sem); |
1705 | list_add_tail(&b->node, &pci_root_buses); | |
1706 | up_write(&pci_bus_sem); | |
1707 | ||
1da177e4 LT |
1708 | return b; |
1709 | ||
1da177e4 | 1710 | class_dev_reg_err: |
7b543663 YL |
1711 | put_device(&bridge->dev); |
1712 | device_unregister(&bridge->dev); | |
1713 | bridge_dev_reg_err: | |
1714 | kfree(bridge); | |
1da177e4 | 1715 | err_out: |
1da177e4 LT |
1716 | kfree(b); |
1717 | return NULL; | |
1718 | } | |
cdb9b9f7 | 1719 | |
98a35831 YL |
1720 | int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max) |
1721 | { | |
1722 | struct resource *res = &b->busn_res; | |
1723 | struct resource *parent_res, *conflict; | |
1724 | ||
1725 | res->start = bus; | |
1726 | res->end = bus_max; | |
1727 | res->flags = IORESOURCE_BUS; | |
1728 | ||
1729 | if (!pci_is_root_bus(b)) | |
1730 | parent_res = &b->parent->busn_res; | |
1731 | else { | |
1732 | parent_res = get_pci_domain_busn_res(pci_domain_nr(b)); | |
1733 | res->flags |= IORESOURCE_PCI_FIXED; | |
1734 | } | |
1735 | ||
1736 | conflict = insert_resource_conflict(parent_res, res); | |
1737 | ||
1738 | if (conflict) | |
1739 | dev_printk(KERN_DEBUG, &b->dev, | |
1740 | "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n", | |
1741 | res, pci_is_root_bus(b) ? "domain " : "", | |
1742 | parent_res, conflict->name, conflict); | |
1743 | else | |
1744 | dev_printk(KERN_DEBUG, &b->dev, | |
1745 | "busn_res: %pR is inserted under %s%pR\n", | |
1746 | res, pci_is_root_bus(b) ? "domain " : "", | |
1747 | parent_res); | |
1748 | ||
1749 | return conflict == NULL; | |
1750 | } | |
1751 | ||
1752 | int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max) | |
1753 | { | |
1754 | struct resource *res = &b->busn_res; | |
1755 | struct resource old_res = *res; | |
1756 | resource_size_t size; | |
1757 | int ret; | |
1758 | ||
1759 | if (res->start > bus_max) | |
1760 | return -EINVAL; | |
1761 | ||
1762 | size = bus_max - res->start + 1; | |
1763 | ret = adjust_resource(res, res->start, size); | |
1764 | dev_printk(KERN_DEBUG, &b->dev, | |
1765 | "busn_res: %pR end %s updated to %02x\n", | |
1766 | &old_res, ret ? "can not be" : "is", bus_max); | |
1767 | ||
1768 | if (!ret && !res->parent) | |
1769 | pci_bus_insert_busn_res(b, res->start, res->end); | |
1770 | ||
1771 | return ret; | |
1772 | } | |
1773 | ||
1774 | void pci_bus_release_busn_res(struct pci_bus *b) | |
1775 | { | |
1776 | struct resource *res = &b->busn_res; | |
1777 | int ret; | |
1778 | ||
1779 | if (!res->flags || !res->parent) | |
1780 | return; | |
1781 | ||
1782 | ret = release_resource(res); | |
1783 | dev_printk(KERN_DEBUG, &b->dev, | |
1784 | "busn_res: %pR %s released\n", | |
1785 | res, ret ? "can not be" : "is"); | |
1786 | } | |
1787 | ||
a2ebb827 BH |
1788 | struct pci_bus * __devinit pci_scan_root_bus(struct device *parent, int bus, |
1789 | struct pci_ops *ops, void *sysdata, struct list_head *resources) | |
1790 | { | |
4d99f524 YL |
1791 | struct pci_host_bridge_window *window; |
1792 | bool found = false; | |
a2ebb827 | 1793 | struct pci_bus *b; |
4d99f524 YL |
1794 | int max; |
1795 | ||
1796 | list_for_each_entry(window, resources, list) | |
1797 | if (window->res->flags & IORESOURCE_BUS) { | |
1798 | found = true; | |
1799 | break; | |
1800 | } | |
a2ebb827 BH |
1801 | |
1802 | b = pci_create_root_bus(parent, bus, ops, sysdata, resources); | |
1803 | if (!b) | |
1804 | return NULL; | |
1805 | ||
4d99f524 YL |
1806 | if (!found) { |
1807 | dev_info(&b->dev, | |
1808 | "No busn resource found for root bus, will use [bus %02x-ff]\n", | |
1809 | bus); | |
1810 | pci_bus_insert_busn_res(b, bus, 255); | |
1811 | } | |
1812 | ||
1813 | max = pci_scan_child_bus(b); | |
1814 | ||
1815 | if (!found) | |
1816 | pci_bus_update_busn_res_end(b, max); | |
1817 | ||
a2ebb827 BH |
1818 | pci_bus_add_devices(b); |
1819 | return b; | |
1820 | } | |
1821 | EXPORT_SYMBOL(pci_scan_root_bus); | |
1822 | ||
7e00fe2e | 1823 | /* Deprecated; use pci_scan_root_bus() instead */ |
0ab2b57f | 1824 | struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent, |
cdb9b9f7 PM |
1825 | int bus, struct pci_ops *ops, void *sysdata) |
1826 | { | |
1e39ae9f | 1827 | LIST_HEAD(resources); |
cdb9b9f7 PM |
1828 | struct pci_bus *b; |
1829 | ||
1e39ae9f BH |
1830 | pci_add_resource(&resources, &ioport_resource); |
1831 | pci_add_resource(&resources, &iomem_resource); | |
1832 | b = pci_create_root_bus(parent, bus, ops, sysdata, &resources); | |
cdb9b9f7 | 1833 | if (b) |
b918c62e | 1834 | b->busn_res.end = pci_scan_child_bus(b); |
1e39ae9f BH |
1835 | else |
1836 | pci_free_resource_list(&resources); | |
cdb9b9f7 PM |
1837 | return b; |
1838 | } | |
1da177e4 LT |
1839 | EXPORT_SYMBOL(pci_scan_bus_parented); |
1840 | ||
de4b2f76 BH |
1841 | struct pci_bus * __devinit pci_scan_bus(int bus, struct pci_ops *ops, |
1842 | void *sysdata) | |
1843 | { | |
1844 | LIST_HEAD(resources); | |
1845 | struct pci_bus *b; | |
1846 | ||
1847 | pci_add_resource(&resources, &ioport_resource); | |
1848 | pci_add_resource(&resources, &iomem_resource); | |
1849 | b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources); | |
1850 | if (b) { | |
b918c62e | 1851 | b->busn_res.end = pci_scan_child_bus(b); |
de4b2f76 BH |
1852 | pci_bus_add_devices(b); |
1853 | } else { | |
1854 | pci_free_resource_list(&resources); | |
1855 | } | |
1856 | return b; | |
1857 | } | |
1858 | EXPORT_SYMBOL(pci_scan_bus); | |
1859 | ||
1da177e4 | 1860 | #ifdef CONFIG_HOTPLUG |
2f320521 YL |
1861 | /** |
1862 | * pci_rescan_bus_bridge_resize - scan a PCI bus for devices. | |
1863 | * @bridge: PCI bridge for the bus to scan | |
1864 | * | |
1865 | * Scan a PCI bus and child buses for new devices, add them, | |
1866 | * and enable them, resizing bridge mmio/io resource if necessary | |
1867 | * and possible. The caller must ensure the child devices are already | |
1868 | * removed for resizing to occur. | |
1869 | * | |
1870 | * Returns the max number of subordinate bus discovered. | |
1871 | */ | |
1872 | unsigned int __ref pci_rescan_bus_bridge_resize(struct pci_dev *bridge) | |
1873 | { | |
1874 | unsigned int max; | |
1875 | struct pci_bus *bus = bridge->subordinate; | |
1876 | ||
1877 | max = pci_scan_child_bus(bus); | |
1878 | ||
1879 | pci_assign_unassigned_bridge_resources(bridge); | |
1880 | ||
1881 | pci_bus_add_devices(bus); | |
1882 | ||
1883 | return max; | |
1884 | } | |
1885 | ||
1da177e4 | 1886 | EXPORT_SYMBOL(pci_add_new_bus); |
1da177e4 LT |
1887 | EXPORT_SYMBOL(pci_scan_slot); |
1888 | EXPORT_SYMBOL(pci_scan_bridge); | |
1da177e4 LT |
1889 | EXPORT_SYMBOL_GPL(pci_scan_child_bus); |
1890 | #endif | |
6b4b78fe | 1891 | |
99178b03 | 1892 | static int __init pci_sort_bf_cmp(const struct device *d_a, const struct device *d_b) |
6b4b78fe | 1893 | { |
99178b03 GKH |
1894 | const struct pci_dev *a = to_pci_dev(d_a); |
1895 | const struct pci_dev *b = to_pci_dev(d_b); | |
1896 | ||
6b4b78fe MD |
1897 | if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1; |
1898 | else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1; | |
1899 | ||
1900 | if (a->bus->number < b->bus->number) return -1; | |
1901 | else if (a->bus->number > b->bus->number) return 1; | |
1902 | ||
1903 | if (a->devfn < b->devfn) return -1; | |
1904 | else if (a->devfn > b->devfn) return 1; | |
1905 | ||
1906 | return 0; | |
1907 | } | |
1908 | ||
5ff580c1 | 1909 | void __init pci_sort_breadthfirst(void) |
6b4b78fe | 1910 | { |
99178b03 | 1911 | bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp); |
6b4b78fe | 1912 | } |