Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * probe.c - PCI detection and setup code | |
3 | */ | |
4 | ||
5 | #include <linux/kernel.h> | |
6 | #include <linux/delay.h> | |
7 | #include <linux/init.h> | |
8 | #include <linux/pci.h> | |
9 | #include <linux/slab.h> | |
10 | #include <linux/module.h> | |
11 | #include <linux/cpumask.h> | |
7d715a6c | 12 | #include <linux/pci-aspm.h> |
bc56b9e0 | 13 | #include "pci.h" |
1da177e4 LT |
14 | |
15 | #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ | |
16 | #define CARDBUS_RESERVE_BUSNR 3 | |
17 | #define PCI_CFG_SPACE_SIZE 256 | |
18 | #define PCI_CFG_SPACE_EXP_SIZE 4096 | |
19 | ||
20 | /* Ugh. Need to stop exporting this to modules. */ | |
21 | LIST_HEAD(pci_root_buses); | |
22 | EXPORT_SYMBOL(pci_root_buses); | |
23 | ||
70308923 GKH |
24 | |
25 | static int find_anything(struct device *dev, void *data) | |
26 | { | |
27 | return 1; | |
28 | } | |
1da177e4 | 29 | |
ed4aaadb ZY |
30 | /* |
31 | * Some device drivers need know if pci is initiated. | |
32 | * Basically, we think pci is not initiated when there | |
70308923 | 33 | * is no device to be found on the pci_bus_type. |
ed4aaadb ZY |
34 | */ |
35 | int no_pci_devices(void) | |
36 | { | |
70308923 GKH |
37 | struct device *dev; |
38 | int no_devices; | |
ed4aaadb | 39 | |
70308923 GKH |
40 | dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything); |
41 | no_devices = (dev == NULL); | |
42 | put_device(dev); | |
43 | return no_devices; | |
44 | } | |
ed4aaadb ZY |
45 | EXPORT_SYMBOL(no_pci_devices); |
46 | ||
1da177e4 LT |
47 | #ifdef HAVE_PCI_LEGACY |
48 | /** | |
49 | * pci_create_legacy_files - create legacy I/O port and memory files | |
50 | * @b: bus to create files under | |
51 | * | |
52 | * Some platforms allow access to legacy I/O port and ISA memory space on | |
53 | * a per-bus basis. This routine creates the files and ties them into | |
54 | * their associated read, write and mmap files from pci-sysfs.c | |
a844158a SH |
55 | * |
56 | * On error unwind, but don't propogate the error to the caller | |
57 | * as it is ok to set up the PCI bus without these files. | |
1da177e4 LT |
58 | */ |
59 | static void pci_create_legacy_files(struct pci_bus *b) | |
60 | { | |
a844158a SH |
61 | int error; |
62 | ||
f5afe806 | 63 | b->legacy_io = kzalloc(sizeof(struct bin_attribute) * 2, |
1da177e4 | 64 | GFP_ATOMIC); |
a844158a SH |
65 | if (!b->legacy_io) |
66 | goto kzalloc_err; | |
67 | ||
68 | b->legacy_io->attr.name = "legacy_io"; | |
69 | b->legacy_io->size = 0xffff; | |
70 | b->legacy_io->attr.mode = S_IRUSR | S_IWUSR; | |
71 | b->legacy_io->read = pci_read_legacy_io; | |
72 | b->legacy_io->write = pci_write_legacy_io; | |
73 | error = device_create_bin_file(&b->dev, b->legacy_io); | |
74 | if (error) | |
75 | goto legacy_io_err; | |
76 | ||
77 | /* Allocated above after the legacy_io struct */ | |
78 | b->legacy_mem = b->legacy_io + 1; | |
79 | b->legacy_mem->attr.name = "legacy_mem"; | |
80 | b->legacy_mem->size = 1024*1024; | |
81 | b->legacy_mem->attr.mode = S_IRUSR | S_IWUSR; | |
82 | b->legacy_mem->mmap = pci_mmap_legacy_mem; | |
83 | error = device_create_bin_file(&b->dev, b->legacy_mem); | |
84 | if (error) | |
85 | goto legacy_mem_err; | |
86 | ||
87 | return; | |
88 | ||
89 | legacy_mem_err: | |
90 | device_remove_bin_file(&b->dev, b->legacy_io); | |
91 | legacy_io_err: | |
92 | kfree(b->legacy_io); | |
93 | b->legacy_io = NULL; | |
94 | kzalloc_err: | |
95 | printk(KERN_WARNING "pci: warning: could not create legacy I/O port " | |
96 | "and ISA memory resources to sysfs\n"); | |
97 | return; | |
1da177e4 LT |
98 | } |
99 | ||
100 | void pci_remove_legacy_files(struct pci_bus *b) | |
101 | { | |
102 | if (b->legacy_io) { | |
fd7d1ced GKH |
103 | device_remove_bin_file(&b->dev, b->legacy_io); |
104 | device_remove_bin_file(&b->dev, b->legacy_mem); | |
1da177e4 LT |
105 | kfree(b->legacy_io); /* both are allocated here */ |
106 | } | |
107 | } | |
108 | #else /* !HAVE_PCI_LEGACY */ | |
109 | static inline void pci_create_legacy_files(struct pci_bus *bus) { return; } | |
110 | void pci_remove_legacy_files(struct pci_bus *bus) { return; } | |
111 | #endif /* HAVE_PCI_LEGACY */ | |
112 | ||
113 | /* | |
114 | * PCI Bus Class Devices | |
115 | */ | |
fd7d1ced | 116 | static ssize_t pci_bus_show_cpuaffinity(struct device *dev, |
39106dcf | 117 | int type, |
fd7d1ced | 118 | struct device_attribute *attr, |
4327edf6 | 119 | char *buf) |
1da177e4 | 120 | { |
1da177e4 | 121 | int ret; |
4327edf6 | 122 | cpumask_t cpumask; |
1da177e4 | 123 | |
fd7d1ced | 124 | cpumask = pcibus_to_cpumask(to_pci_bus(dev)); |
39106dcf MT |
125 | ret = type? |
126 | cpulist_scnprintf(buf, PAGE_SIZE-2, cpumask): | |
127 | cpumask_scnprintf(buf, PAGE_SIZE-2, cpumask); | |
128 | buf[ret++] = '\n'; | |
129 | buf[ret] = '\0'; | |
1da177e4 LT |
130 | return ret; |
131 | } | |
39106dcf MT |
132 | |
133 | static ssize_t inline pci_bus_show_cpumaskaffinity(struct device *dev, | |
134 | struct device_attribute *attr, | |
135 | char *buf) | |
136 | { | |
137 | return pci_bus_show_cpuaffinity(dev, 0, attr, buf); | |
138 | } | |
139 | ||
140 | static ssize_t inline pci_bus_show_cpulistaffinity(struct device *dev, | |
141 | struct device_attribute *attr, | |
142 | char *buf) | |
143 | { | |
144 | return pci_bus_show_cpuaffinity(dev, 1, attr, buf); | |
145 | } | |
146 | ||
147 | DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpumaskaffinity, NULL); | |
148 | DEVICE_ATTR(cpulistaffinity, S_IRUGO, pci_bus_show_cpulistaffinity, NULL); | |
1da177e4 LT |
149 | |
150 | /* | |
151 | * PCI Bus Class | |
152 | */ | |
fd7d1ced | 153 | static void release_pcibus_dev(struct device *dev) |
1da177e4 | 154 | { |
fd7d1ced | 155 | struct pci_bus *pci_bus = to_pci_bus(dev); |
1da177e4 LT |
156 | |
157 | if (pci_bus->bridge) | |
158 | put_device(pci_bus->bridge); | |
159 | kfree(pci_bus); | |
160 | } | |
161 | ||
162 | static struct class pcibus_class = { | |
163 | .name = "pci_bus", | |
fd7d1ced | 164 | .dev_release = &release_pcibus_dev, |
1da177e4 LT |
165 | }; |
166 | ||
167 | static int __init pcibus_class_init(void) | |
168 | { | |
169 | return class_register(&pcibus_class); | |
170 | } | |
171 | postcore_initcall(pcibus_class_init); | |
172 | ||
173 | /* | |
174 | * Translate the low bits of the PCI base | |
175 | * to the resource type | |
176 | */ | |
177 | static inline unsigned int pci_calc_resource_flags(unsigned int flags) | |
178 | { | |
179 | if (flags & PCI_BASE_ADDRESS_SPACE_IO) | |
180 | return IORESOURCE_IO; | |
181 | ||
182 | if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH) | |
183 | return IORESOURCE_MEM | IORESOURCE_PREFETCH; | |
184 | ||
185 | return IORESOURCE_MEM; | |
186 | } | |
187 | ||
6ac665c6 | 188 | static u64 pci_size(u64 base, u64 maxbase, u64 mask) |
1da177e4 | 189 | { |
6ac665c6 | 190 | u64 size = mask & maxbase; /* Find the significant bits */ |
1da177e4 LT |
191 | if (!size) |
192 | return 0; | |
193 | ||
194 | /* Get the lowest of them to find the decode size, and | |
195 | from that the extent. */ | |
196 | size = (size & ~(size-1)) - 1; | |
197 | ||
198 | /* base == maxbase can be valid only if the BAR has | |
199 | already been programmed with all 1s. */ | |
200 | if (base == maxbase && ((base | size) & mask) != mask) | |
201 | return 0; | |
202 | ||
203 | return size; | |
204 | } | |
205 | ||
6ac665c6 MW |
206 | enum pci_bar_type { |
207 | pci_bar_unknown, /* Standard PCI BAR probe */ | |
208 | pci_bar_io, /* An io port BAR */ | |
209 | pci_bar_mem32, /* A 32-bit memory BAR */ | |
210 | pci_bar_mem64, /* A 64-bit memory BAR */ | |
211 | }; | |
07eddf3d | 212 | |
6ac665c6 MW |
213 | static inline enum pci_bar_type decode_bar(struct resource *res, u32 bar) |
214 | { | |
215 | if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) { | |
216 | res->flags = bar & ~PCI_BASE_ADDRESS_IO_MASK; | |
217 | return pci_bar_io; | |
218 | } | |
07eddf3d | 219 | |
6ac665c6 | 220 | res->flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK; |
07eddf3d | 221 | |
6ac665c6 MW |
222 | if (res->flags == PCI_BASE_ADDRESS_MEM_TYPE_64) |
223 | return pci_bar_mem64; | |
224 | return pci_bar_mem32; | |
07eddf3d YL |
225 | } |
226 | ||
6ac665c6 MW |
227 | /* |
228 | * If the type is not unknown, we assume that the lowest bit is 'enable'. | |
229 | * Returns 1 if the BAR was 64-bit and 0 if it was 32-bit. | |
230 | */ | |
231 | static int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, | |
232 | struct resource *res, unsigned int pos) | |
07eddf3d | 233 | { |
6ac665c6 MW |
234 | u32 l, sz, mask; |
235 | ||
236 | mask = type ? ~PCI_ROM_ADDRESS_ENABLE : ~0; | |
237 | ||
238 | res->name = pci_name(dev); | |
239 | ||
240 | pci_read_config_dword(dev, pos, &l); | |
241 | pci_write_config_dword(dev, pos, mask); | |
242 | pci_read_config_dword(dev, pos, &sz); | |
243 | pci_write_config_dword(dev, pos, l); | |
244 | ||
245 | /* | |
246 | * All bits set in sz means the device isn't working properly. | |
247 | * If the BAR isn't implemented, all bits must be 0. If it's a | |
248 | * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit | |
249 | * 1 must be clear. | |
250 | */ | |
251 | if (!sz || sz == 0xffffffff) | |
252 | goto fail; | |
253 | ||
254 | /* | |
255 | * I don't know how l can have all bits set. Copied from old code. | |
256 | * Maybe it fixes a bug on some ancient platform. | |
257 | */ | |
258 | if (l == 0xffffffff) | |
259 | l = 0; | |
260 | ||
261 | if (type == pci_bar_unknown) { | |
262 | type = decode_bar(res, l); | |
263 | res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN; | |
264 | if (type == pci_bar_io) { | |
265 | l &= PCI_BASE_ADDRESS_IO_MASK; | |
266 | mask = PCI_BASE_ADDRESS_IO_MASK & 0xffff; | |
267 | } else { | |
268 | l &= PCI_BASE_ADDRESS_MEM_MASK; | |
269 | mask = (u32)PCI_BASE_ADDRESS_MEM_MASK; | |
270 | } | |
271 | } else { | |
272 | res->flags |= (l & IORESOURCE_ROM_ENABLE); | |
273 | l &= PCI_ROM_ADDRESS_MASK; | |
274 | mask = (u32)PCI_ROM_ADDRESS_MASK; | |
275 | } | |
276 | ||
277 | if (type == pci_bar_mem64) { | |
278 | u64 l64 = l; | |
279 | u64 sz64 = sz; | |
280 | u64 mask64 = mask | (u64)~0 << 32; | |
281 | ||
282 | pci_read_config_dword(dev, pos + 4, &l); | |
283 | pci_write_config_dword(dev, pos + 4, ~0); | |
284 | pci_read_config_dword(dev, pos + 4, &sz); | |
285 | pci_write_config_dword(dev, pos + 4, l); | |
286 | ||
287 | l64 |= ((u64)l << 32); | |
288 | sz64 |= ((u64)sz << 32); | |
289 | ||
290 | sz64 = pci_size(l64, sz64, mask64); | |
291 | ||
292 | if (!sz64) | |
293 | goto fail; | |
294 | ||
cc5499c3 | 295 | if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) { |
6ac665c6 MW |
296 | dev_err(&dev->dev, "can't handle 64-bit BAR\n"); |
297 | goto fail; | |
cc5499c3 | 298 | } else if ((sizeof(resource_size_t) < 8) && l) { |
6ac665c6 MW |
299 | /* Address above 32-bit boundary; disable the BAR */ |
300 | pci_write_config_dword(dev, pos, 0); | |
301 | pci_write_config_dword(dev, pos + 4, 0); | |
302 | res->start = 0; | |
303 | res->end = sz64; | |
304 | } else { | |
305 | res->start = l64; | |
306 | res->end = l64 + sz64; | |
096e6f67 BH |
307 | printk(KERN_DEBUG "PCI: %s reg %x 64bit mmio: %pR\n", |
308 | pci_name(dev), pos, res); | |
6ac665c6 MW |
309 | } |
310 | } else { | |
311 | sz = pci_size(l, sz, mask); | |
312 | ||
313 | if (!sz) | |
314 | goto fail; | |
315 | ||
316 | res->start = l; | |
317 | res->end = l + sz; | |
096e6f67 BH |
318 | printk(KERN_DEBUG "PCI: %s reg %x %s: %pR\n", |
319 | pci_name(dev), pos, | |
320 | (res->flags & IORESOURCE_IO) ? "io port":"32bit mmio", | |
321 | res); | |
6ac665c6 MW |
322 | } |
323 | ||
324 | out: | |
325 | return (type == pci_bar_mem64) ? 1 : 0; | |
326 | fail: | |
327 | res->flags = 0; | |
328 | goto out; | |
07eddf3d YL |
329 | } |
330 | ||
1da177e4 LT |
331 | static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) |
332 | { | |
6ac665c6 | 333 | unsigned int pos, reg; |
07eddf3d | 334 | |
6ac665c6 MW |
335 | for (pos = 0; pos < howmany; pos++) { |
336 | struct resource *res = &dev->resource[pos]; | |
1da177e4 | 337 | reg = PCI_BASE_ADDRESS_0 + (pos << 2); |
6ac665c6 | 338 | pos += __pci_read_base(dev, pci_bar_unknown, res, reg); |
1da177e4 | 339 | } |
6ac665c6 | 340 | |
1da177e4 | 341 | if (rom) { |
6ac665c6 | 342 | struct resource *res = &dev->resource[PCI_ROM_RESOURCE]; |
1da177e4 | 343 | dev->rom_base_reg = rom; |
6ac665c6 MW |
344 | res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | |
345 | IORESOURCE_READONLY | IORESOURCE_CACHEABLE | | |
346 | IORESOURCE_SIZEALIGN; | |
347 | __pci_read_base(dev, pci_bar_mem32, res, rom); | |
1da177e4 LT |
348 | } |
349 | } | |
350 | ||
0ab2b57f | 351 | void __devinit pci_read_bridge_bases(struct pci_bus *child) |
1da177e4 LT |
352 | { |
353 | struct pci_dev *dev = child->self; | |
354 | u8 io_base_lo, io_limit_lo; | |
355 | u16 mem_base_lo, mem_limit_lo; | |
356 | unsigned long base, limit; | |
357 | struct resource *res; | |
358 | int i; | |
359 | ||
360 | if (!dev) /* It's a host bus, nothing to read */ | |
361 | return; | |
362 | ||
363 | if (dev->transparent) { | |
80ccba11 | 364 | dev_info(&dev->dev, "transparent bridge\n"); |
90b54929 IK |
365 | for(i = 3; i < PCI_BUS_NUM_RESOURCES; i++) |
366 | child->resource[i] = child->parent->resource[i - 3]; | |
1da177e4 LT |
367 | } |
368 | ||
369 | for(i=0; i<3; i++) | |
370 | child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i]; | |
371 | ||
372 | res = child->resource[0]; | |
373 | pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); | |
374 | pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); | |
375 | base = (io_base_lo & PCI_IO_RANGE_MASK) << 8; | |
376 | limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8; | |
377 | ||
378 | if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) { | |
379 | u16 io_base_hi, io_limit_hi; | |
380 | pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi); | |
381 | pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi); | |
382 | base |= (io_base_hi << 16); | |
383 | limit |= (io_limit_hi << 16); | |
384 | } | |
385 | ||
386 | if (base <= limit) { | |
387 | res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; | |
9d265124 DY |
388 | if (!res->start) |
389 | res->start = base; | |
390 | if (!res->end) | |
391 | res->end = limit + 0xfff; | |
096e6f67 BH |
392 | printk(KERN_DEBUG "PCI: bridge %s io port: %pR\n", |
393 | pci_name(dev), res); | |
1da177e4 LT |
394 | } |
395 | ||
396 | res = child->resource[1]; | |
397 | pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo); | |
398 | pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo); | |
399 | base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16; | |
400 | limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16; | |
401 | if (base <= limit) { | |
402 | res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM; | |
403 | res->start = base; | |
404 | res->end = limit + 0xfffff; | |
096e6f67 BH |
405 | printk(KERN_DEBUG "PCI: bridge %s 32bit mmio: %pR\n", |
406 | pci_name(dev), res); | |
1da177e4 LT |
407 | } |
408 | ||
409 | res = child->resource[2]; | |
410 | pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); | |
411 | pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); | |
412 | base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16; | |
413 | limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16; | |
414 | ||
415 | if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { | |
416 | u32 mem_base_hi, mem_limit_hi; | |
417 | pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi); | |
418 | pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi); | |
419 | ||
420 | /* | |
421 | * Some bridges set the base > limit by default, and some | |
422 | * (broken) BIOSes do not initialize them. If we find | |
423 | * this, just assume they are not being used. | |
424 | */ | |
425 | if (mem_base_hi <= mem_limit_hi) { | |
426 | #if BITS_PER_LONG == 64 | |
427 | base |= ((long) mem_base_hi) << 32; | |
428 | limit |= ((long) mem_limit_hi) << 32; | |
429 | #else | |
430 | if (mem_base_hi || mem_limit_hi) { | |
80ccba11 BH |
431 | dev_err(&dev->dev, "can't handle 64-bit " |
432 | "address space for bridge\n"); | |
1da177e4 LT |
433 | return; |
434 | } | |
435 | #endif | |
436 | } | |
437 | } | |
438 | if (base <= limit) { | |
439 | res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM | IORESOURCE_PREFETCH; | |
440 | res->start = base; | |
441 | res->end = limit + 0xfffff; | |
096e6f67 BH |
442 | printk(KERN_DEBUG "PCI: bridge %s %sbit mmio pref: %pR\n", |
443 | pci_name(dev), | |
444 | (res->flags & PCI_PREF_RANGE_TYPE_64) ? "64":"32", res); | |
1da177e4 LT |
445 | } |
446 | } | |
447 | ||
96bde06a | 448 | static struct pci_bus * pci_alloc_bus(void) |
1da177e4 LT |
449 | { |
450 | struct pci_bus *b; | |
451 | ||
f5afe806 | 452 | b = kzalloc(sizeof(*b), GFP_KERNEL); |
1da177e4 | 453 | if (b) { |
1da177e4 LT |
454 | INIT_LIST_HEAD(&b->node); |
455 | INIT_LIST_HEAD(&b->children); | |
456 | INIT_LIST_HEAD(&b->devices); | |
f46753c5 | 457 | INIT_LIST_HEAD(&b->slots); |
1da177e4 LT |
458 | } |
459 | return b; | |
460 | } | |
461 | ||
cbd4e055 AB |
462 | static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent, |
463 | struct pci_dev *bridge, int busnr) | |
1da177e4 LT |
464 | { |
465 | struct pci_bus *child; | |
466 | int i; | |
467 | ||
468 | /* | |
469 | * Allocate a new bus, and inherit stuff from the parent.. | |
470 | */ | |
471 | child = pci_alloc_bus(); | |
472 | if (!child) | |
473 | return NULL; | |
474 | ||
475 | child->self = bridge; | |
476 | child->parent = parent; | |
477 | child->ops = parent->ops; | |
478 | child->sysdata = parent->sysdata; | |
6e325a62 | 479 | child->bus_flags = parent->bus_flags; |
1da177e4 LT |
480 | child->bridge = get_device(&bridge->dev); |
481 | ||
fd7d1ced GKH |
482 | /* initialize some portions of the bus device, but don't register it |
483 | * now as the parent is not properly set up yet. This device will get | |
484 | * registered later in pci_bus_add_devices() | |
485 | */ | |
486 | child->dev.class = &pcibus_class; | |
487 | sprintf(child->dev.bus_id, "%04x:%02x", pci_domain_nr(child), busnr); | |
1da177e4 LT |
488 | |
489 | /* | |
490 | * Set up the primary, secondary and subordinate | |
491 | * bus numbers. | |
492 | */ | |
493 | child->number = child->secondary = busnr; | |
494 | child->primary = parent->secondary; | |
495 | child->subordinate = 0xff; | |
496 | ||
497 | /* Set up default resource pointers and names.. */ | |
498 | for (i = 0; i < 4; i++) { | |
499 | child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i]; | |
500 | child->resource[i]->name = child->name; | |
501 | } | |
502 | bridge->subordinate = child; | |
503 | ||
504 | return child; | |
505 | } | |
506 | ||
451124a7 | 507 | struct pci_bus *__ref pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr) |
1da177e4 LT |
508 | { |
509 | struct pci_bus *child; | |
510 | ||
511 | child = pci_alloc_child_bus(parent, dev, busnr); | |
e4ea9bb7 | 512 | if (child) { |
d71374da | 513 | down_write(&pci_bus_sem); |
1da177e4 | 514 | list_add_tail(&child->node, &parent->children); |
d71374da | 515 | up_write(&pci_bus_sem); |
e4ea9bb7 | 516 | } |
1da177e4 LT |
517 | return child; |
518 | } | |
519 | ||
96bde06a | 520 | static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max) |
26f674ae GKH |
521 | { |
522 | struct pci_bus *parent = child->parent; | |
12f44f46 IK |
523 | |
524 | /* Attempts to fix that up are really dangerous unless | |
525 | we're going to re-assign all bus numbers. */ | |
526 | if (!pcibios_assign_all_busses()) | |
527 | return; | |
528 | ||
26f674ae GKH |
529 | while (parent->parent && parent->subordinate < max) { |
530 | parent->subordinate = max; | |
531 | pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max); | |
532 | parent = parent->parent; | |
533 | } | |
534 | } | |
535 | ||
1da177e4 LT |
536 | /* |
537 | * If it's a bridge, configure it and scan the bus behind it. | |
538 | * For CardBus bridges, we don't scan behind as the devices will | |
539 | * be handled by the bridge driver itself. | |
540 | * | |
541 | * We need to process bridges in two passes -- first we scan those | |
542 | * already configured by the BIOS and after we are done with all of | |
543 | * them, we proceed to assigning numbers to the remaining buses in | |
544 | * order to avoid overlaps between old and new bus numbers. | |
545 | */ | |
0ab2b57f | 546 | int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass) |
1da177e4 LT |
547 | { |
548 | struct pci_bus *child; | |
549 | int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS); | |
49887941 | 550 | u32 buses, i, j = 0; |
1da177e4 LT |
551 | u16 bctl; |
552 | ||
553 | pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses); | |
554 | ||
80ccba11 BH |
555 | dev_dbg(&dev->dev, "scanning behind bridge, config %06x, pass %d\n", |
556 | buses & 0xffffff, pass); | |
1da177e4 LT |
557 | |
558 | /* Disable MasterAbortMode during probing to avoid reporting | |
559 | of bus errors (in some architectures) */ | |
560 | pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl); | |
561 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, | |
562 | bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT); | |
563 | ||
1da177e4 LT |
564 | if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus) { |
565 | unsigned int cmax, busnr; | |
566 | /* | |
567 | * Bus already configured by firmware, process it in the first | |
568 | * pass and just note the configuration. | |
569 | */ | |
570 | if (pass) | |
bbe8f9a3 | 571 | goto out; |
1da177e4 LT |
572 | busnr = (buses >> 8) & 0xFF; |
573 | ||
574 | /* | |
575 | * If we already got to this bus through a different bridge, | |
576 | * ignore it. This can happen with the i450NX chipset. | |
577 | */ | |
578 | if (pci_find_bus(pci_domain_nr(bus), busnr)) { | |
80ccba11 BH |
579 | dev_info(&dev->dev, "bus %04x:%02x already known\n", |
580 | pci_domain_nr(bus), busnr); | |
bbe8f9a3 | 581 | goto out; |
1da177e4 LT |
582 | } |
583 | ||
6ef6f0e3 | 584 | child = pci_add_new_bus(bus, dev, busnr); |
1da177e4 | 585 | if (!child) |
bbe8f9a3 | 586 | goto out; |
1da177e4 LT |
587 | child->primary = buses & 0xFF; |
588 | child->subordinate = (buses >> 16) & 0xFF; | |
11949255 | 589 | child->bridge_ctl = bctl; |
1da177e4 LT |
590 | |
591 | cmax = pci_scan_child_bus(child); | |
592 | if (cmax > max) | |
593 | max = cmax; | |
594 | if (child->subordinate > max) | |
595 | max = child->subordinate; | |
596 | } else { | |
597 | /* | |
598 | * We need to assign a number to this bus which we always | |
599 | * do in the second pass. | |
600 | */ | |
12f44f46 IK |
601 | if (!pass) { |
602 | if (pcibios_assign_all_busses()) | |
603 | /* Temporarily disable forwarding of the | |
604 | configuration cycles on all bridges in | |
605 | this bus segment to avoid possible | |
606 | conflicts in the second pass between two | |
607 | bridges programmed with overlapping | |
608 | bus ranges. */ | |
609 | pci_write_config_dword(dev, PCI_PRIMARY_BUS, | |
610 | buses & ~0xffffff); | |
bbe8f9a3 | 611 | goto out; |
12f44f46 | 612 | } |
1da177e4 LT |
613 | |
614 | /* Clear errors */ | |
615 | pci_write_config_word(dev, PCI_STATUS, 0xffff); | |
616 | ||
cc57450f RS |
617 | /* Prevent assigning a bus number that already exists. |
618 | * This can happen when a bridge is hot-plugged */ | |
619 | if (pci_find_bus(pci_domain_nr(bus), max+1)) | |
bbe8f9a3 | 620 | goto out; |
6ef6f0e3 | 621 | child = pci_add_new_bus(bus, dev, ++max); |
1da177e4 LT |
622 | buses = (buses & 0xff000000) |
623 | | ((unsigned int)(child->primary) << 0) | |
624 | | ((unsigned int)(child->secondary) << 8) | |
625 | | ((unsigned int)(child->subordinate) << 16); | |
626 | ||
627 | /* | |
628 | * yenta.c forces a secondary latency timer of 176. | |
629 | * Copy that behaviour here. | |
630 | */ | |
631 | if (is_cardbus) { | |
632 | buses &= ~0xff000000; | |
633 | buses |= CARDBUS_LATENCY_TIMER << 24; | |
634 | } | |
635 | ||
636 | /* | |
637 | * We need to blast all three values with a single write. | |
638 | */ | |
639 | pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses); | |
640 | ||
641 | if (!is_cardbus) { | |
11949255 | 642 | child->bridge_ctl = bctl; |
26f674ae GKH |
643 | /* |
644 | * Adjust subordinate busnr in parent buses. | |
645 | * We do this before scanning for children because | |
646 | * some devices may not be detected if the bios | |
647 | * was lazy. | |
648 | */ | |
649 | pci_fixup_parent_subordinate_busnr(child, max); | |
1da177e4 LT |
650 | /* Now we can scan all subordinate buses... */ |
651 | max = pci_scan_child_bus(child); | |
e3ac86d8 KA |
652 | /* |
653 | * now fix it up again since we have found | |
654 | * the real value of max. | |
655 | */ | |
656 | pci_fixup_parent_subordinate_busnr(child, max); | |
1da177e4 LT |
657 | } else { |
658 | /* | |
659 | * For CardBus bridges, we leave 4 bus numbers | |
660 | * as cards with a PCI-to-PCI bridge can be | |
661 | * inserted later. | |
662 | */ | |
49887941 DB |
663 | for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) { |
664 | struct pci_bus *parent = bus; | |
cc57450f RS |
665 | if (pci_find_bus(pci_domain_nr(bus), |
666 | max+i+1)) | |
667 | break; | |
49887941 DB |
668 | while (parent->parent) { |
669 | if ((!pcibios_assign_all_busses()) && | |
670 | (parent->subordinate > max) && | |
671 | (parent->subordinate <= max+i)) { | |
672 | j = 1; | |
673 | } | |
674 | parent = parent->parent; | |
675 | } | |
676 | if (j) { | |
677 | /* | |
678 | * Often, there are two cardbus bridges | |
679 | * -- try to leave one valid bus number | |
680 | * for each one. | |
681 | */ | |
682 | i /= 2; | |
683 | break; | |
684 | } | |
685 | } | |
cc57450f | 686 | max += i; |
26f674ae | 687 | pci_fixup_parent_subordinate_busnr(child, max); |
1da177e4 LT |
688 | } |
689 | /* | |
690 | * Set the subordinate bus number to its real value. | |
691 | */ | |
692 | child->subordinate = max; | |
693 | pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max); | |
694 | } | |
695 | ||
cb3576fa GH |
696 | sprintf(child->name, |
697 | (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"), | |
698 | pci_domain_nr(bus), child->number); | |
1da177e4 | 699 | |
d55bef51 | 700 | /* Has only triggered on CardBus, fixup is in yenta_socket */ |
49887941 DB |
701 | while (bus->parent) { |
702 | if ((child->subordinate > bus->subordinate) || | |
703 | (child->number > bus->subordinate) || | |
704 | (child->number < bus->number) || | |
705 | (child->subordinate < bus->number)) { | |
a6f29a98 | 706 | pr_debug("PCI: Bus #%02x (-#%02x) is %s " |
d55bef51 BK |
707 | "hidden behind%s bridge #%02x (-#%02x)\n", |
708 | child->number, child->subordinate, | |
709 | (bus->number > child->subordinate && | |
710 | bus->subordinate < child->number) ? | |
a6f29a98 JP |
711 | "wholly" : "partially", |
712 | bus->self->transparent ? " transparent" : "", | |
d55bef51 | 713 | bus->number, bus->subordinate); |
49887941 DB |
714 | } |
715 | bus = bus->parent; | |
716 | } | |
717 | ||
bbe8f9a3 RB |
718 | out: |
719 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl); | |
720 | ||
1da177e4 LT |
721 | return max; |
722 | } | |
723 | ||
724 | /* | |
725 | * Read interrupt line and base address registers. | |
726 | * The architecture-dependent code can tweak these, of course. | |
727 | */ | |
728 | static void pci_read_irq(struct pci_dev *dev) | |
729 | { | |
730 | unsigned char irq; | |
731 | ||
732 | pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq); | |
ffeff788 | 733 | dev->pin = irq; |
1da177e4 LT |
734 | if (irq) |
735 | pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); | |
736 | dev->irq = irq; | |
737 | } | |
738 | ||
01abc2aa | 739 | #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED) |
76e6a1d6 | 740 | |
1da177e4 LT |
741 | /** |
742 | * pci_setup_device - fill in class and map information of a device | |
743 | * @dev: the device structure to fill | |
744 | * | |
745 | * Initialize the device structure with information about the device's | |
746 | * vendor,class,memory and IO-space addresses,IRQ lines etc. | |
747 | * Called at initialisation of the PCI subsystem and by CardBus services. | |
748 | * Returns 0 on success and -1 if unknown type of device (not normal, bridge | |
749 | * or CardBus). | |
750 | */ | |
751 | static int pci_setup_device(struct pci_dev * dev) | |
752 | { | |
753 | u32 class; | |
754 | ||
eebfcfb5 GKH |
755 | dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus), |
756 | dev->bus->number, PCI_SLOT(dev->devfn), | |
757 | PCI_FUNC(dev->devfn)); | |
1da177e4 LT |
758 | |
759 | pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); | |
b8a3a521 | 760 | dev->revision = class & 0xff; |
1da177e4 LT |
761 | class >>= 8; /* upper 3 bytes */ |
762 | dev->class = class; | |
763 | class >>= 8; | |
764 | ||
80ccba11 | 765 | dev_dbg(&dev->dev, "found [%04x/%04x] class %06x header type %02x\n", |
1da177e4 LT |
766 | dev->vendor, dev->device, class, dev->hdr_type); |
767 | ||
768 | /* "Unknown power state" */ | |
3fe9d19f | 769 | dev->current_state = PCI_UNKNOWN; |
1da177e4 LT |
770 | |
771 | /* Early fixups, before probing the BARs */ | |
772 | pci_fixup_device(pci_fixup_early, dev); | |
773 | class = dev->class >> 8; | |
774 | ||
775 | switch (dev->hdr_type) { /* header type */ | |
776 | case PCI_HEADER_TYPE_NORMAL: /* standard header */ | |
777 | if (class == PCI_CLASS_BRIDGE_PCI) | |
778 | goto bad; | |
779 | pci_read_irq(dev); | |
780 | pci_read_bases(dev, 6, PCI_ROM_ADDRESS); | |
781 | pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); | |
782 | pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device); | |
368c73d4 AC |
783 | |
784 | /* | |
785 | * Do the ugly legacy mode stuff here rather than broken chip | |
786 | * quirk code. Legacy mode ATA controllers have fixed | |
787 | * addresses. These are not always echoed in BAR0-3, and | |
788 | * BAR0-3 in a few cases contain junk! | |
789 | */ | |
790 | if (class == PCI_CLASS_STORAGE_IDE) { | |
791 | u8 progif; | |
792 | pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); | |
793 | if ((progif & 1) == 0) { | |
af1bff4f LT |
794 | dev->resource[0].start = 0x1F0; |
795 | dev->resource[0].end = 0x1F7; | |
796 | dev->resource[0].flags = LEGACY_IO_RESOURCE; | |
797 | dev->resource[1].start = 0x3F6; | |
798 | dev->resource[1].end = 0x3F6; | |
799 | dev->resource[1].flags = LEGACY_IO_RESOURCE; | |
368c73d4 AC |
800 | } |
801 | if ((progif & 4) == 0) { | |
af1bff4f LT |
802 | dev->resource[2].start = 0x170; |
803 | dev->resource[2].end = 0x177; | |
804 | dev->resource[2].flags = LEGACY_IO_RESOURCE; | |
805 | dev->resource[3].start = 0x376; | |
806 | dev->resource[3].end = 0x376; | |
807 | dev->resource[3].flags = LEGACY_IO_RESOURCE; | |
368c73d4 AC |
808 | } |
809 | } | |
1da177e4 LT |
810 | break; |
811 | ||
812 | case PCI_HEADER_TYPE_BRIDGE: /* bridge header */ | |
813 | if (class != PCI_CLASS_BRIDGE_PCI) | |
814 | goto bad; | |
815 | /* The PCI-to-PCI bridge spec requires that subtractive | |
816 | decoding (i.e. transparent) bridge must have programming | |
817 | interface code of 0x01. */ | |
3efd273b | 818 | pci_read_irq(dev); |
1da177e4 LT |
819 | dev->transparent = ((dev->class & 0xff) == 1); |
820 | pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); | |
821 | break; | |
822 | ||
823 | case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */ | |
824 | if (class != PCI_CLASS_BRIDGE_CARDBUS) | |
825 | goto bad; | |
826 | pci_read_irq(dev); | |
827 | pci_read_bases(dev, 1, 0); | |
828 | pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); | |
829 | pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device); | |
830 | break; | |
831 | ||
832 | default: /* unknown header */ | |
80ccba11 BH |
833 | dev_err(&dev->dev, "unknown header type %02x, " |
834 | "ignoring device\n", dev->hdr_type); | |
1da177e4 LT |
835 | return -1; |
836 | ||
837 | bad: | |
80ccba11 BH |
838 | dev_err(&dev->dev, "ignoring class %02x (doesn't match header " |
839 | "type %02x)\n", class, dev->hdr_type); | |
1da177e4 LT |
840 | dev->class = PCI_CLASS_NOT_DEFINED; |
841 | } | |
842 | ||
843 | /* We found a fine healthy device, go go go... */ | |
844 | return 0; | |
845 | } | |
846 | ||
847 | /** | |
848 | * pci_release_dev - free a pci device structure when all users of it are finished. | |
849 | * @dev: device that's been disconnected | |
850 | * | |
851 | * Will be called only by the device core when all users of this pci device are | |
852 | * done. | |
853 | */ | |
854 | static void pci_release_dev(struct device *dev) | |
855 | { | |
856 | struct pci_dev *pci_dev; | |
857 | ||
858 | pci_dev = to_pci_dev(dev); | |
94e61088 | 859 | pci_vpd_release(pci_dev); |
1da177e4 LT |
860 | kfree(pci_dev); |
861 | } | |
862 | ||
994a65e2 KA |
863 | static void set_pcie_port_type(struct pci_dev *pdev) |
864 | { | |
865 | int pos; | |
866 | u16 reg16; | |
867 | ||
868 | pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); | |
869 | if (!pos) | |
870 | return; | |
871 | pdev->is_pcie = 1; | |
872 | pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); | |
873 | pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4; | |
874 | } | |
875 | ||
1da177e4 LT |
876 | /** |
877 | * pci_cfg_space_size - get the configuration space size of the PCI device. | |
8f7020d3 | 878 | * @dev: PCI device |
1da177e4 LT |
879 | * |
880 | * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices | |
881 | * have 4096 bytes. Even if the device is capable, that doesn't mean we can | |
882 | * access it. Maybe we don't have a way to generate extended config space | |
883 | * accesses, or the device is behind a reverse Express bridge. So we try | |
884 | * reading the dword at 0x100 which must either be 0 or a valid extended | |
885 | * capability header. | |
886 | */ | |
70b9f7dc | 887 | int pci_cfg_space_size_ext(struct pci_dev *dev) |
1da177e4 | 888 | { |
1da177e4 LT |
889 | u32 status; |
890 | ||
70b9f7dc YL |
891 | if (pci_read_config_dword(dev, 256, &status) != PCIBIOS_SUCCESSFUL) |
892 | goto fail; | |
893 | if (status == 0xffffffff) | |
894 | goto fail; | |
895 | ||
896 | return PCI_CFG_SPACE_EXP_SIZE; | |
897 | ||
898 | fail: | |
899 | return PCI_CFG_SPACE_SIZE; | |
900 | } | |
901 | ||
902 | int pci_cfg_space_size(struct pci_dev *dev) | |
903 | { | |
904 | int pos; | |
905 | u32 status; | |
57741a77 | 906 | |
1da177e4 LT |
907 | pos = pci_find_capability(dev, PCI_CAP_ID_EXP); |
908 | if (!pos) { | |
909 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
910 | if (!pos) | |
911 | goto fail; | |
912 | ||
913 | pci_read_config_dword(dev, pos + PCI_X_STATUS, &status); | |
914 | if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))) | |
915 | goto fail; | |
916 | } | |
917 | ||
70b9f7dc | 918 | return pci_cfg_space_size_ext(dev); |
1da177e4 LT |
919 | |
920 | fail: | |
921 | return PCI_CFG_SPACE_SIZE; | |
922 | } | |
923 | ||
924 | static void pci_release_bus_bridge_dev(struct device *dev) | |
925 | { | |
926 | kfree(dev); | |
927 | } | |
928 | ||
65891215 ME |
929 | struct pci_dev *alloc_pci_dev(void) |
930 | { | |
931 | struct pci_dev *dev; | |
932 | ||
933 | dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL); | |
934 | if (!dev) | |
935 | return NULL; | |
936 | ||
65891215 ME |
937 | INIT_LIST_HEAD(&dev->bus_list); |
938 | ||
4aa9bc95 ME |
939 | pci_msi_init_pci_dev(dev); |
940 | ||
65891215 ME |
941 | return dev; |
942 | } | |
943 | EXPORT_SYMBOL(alloc_pci_dev); | |
944 | ||
1da177e4 LT |
945 | /* |
946 | * Read the config data for a PCI device, sanity-check it | |
947 | * and fill in the dev structure... | |
948 | */ | |
7f7b5de2 | 949 | static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn) |
1da177e4 LT |
950 | { |
951 | struct pci_dev *dev; | |
952 | u32 l; | |
953 | u8 hdr_type; | |
954 | int delay = 1; | |
955 | ||
956 | if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l)) | |
957 | return NULL; | |
958 | ||
959 | /* some broken boards return 0 or ~0 if a slot is empty: */ | |
960 | if (l == 0xffffffff || l == 0x00000000 || | |
961 | l == 0x0000ffff || l == 0xffff0000) | |
962 | return NULL; | |
963 | ||
964 | /* Configuration request Retry Status */ | |
965 | while (l == 0xffff0001) { | |
966 | msleep(delay); | |
967 | delay *= 2; | |
968 | if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l)) | |
969 | return NULL; | |
970 | /* Card hasn't responded in 60 seconds? Must be stuck. */ | |
971 | if (delay > 60 * 1000) { | |
80ccba11 | 972 | printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not " |
1da177e4 LT |
973 | "responding\n", pci_domain_nr(bus), |
974 | bus->number, PCI_SLOT(devfn), | |
975 | PCI_FUNC(devfn)); | |
976 | return NULL; | |
977 | } | |
978 | } | |
979 | ||
980 | if (pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type)) | |
981 | return NULL; | |
982 | ||
bab41e9b | 983 | dev = alloc_pci_dev(); |
1da177e4 LT |
984 | if (!dev) |
985 | return NULL; | |
986 | ||
1da177e4 LT |
987 | dev->bus = bus; |
988 | dev->sysdata = bus->sysdata; | |
989 | dev->dev.parent = bus->bridge; | |
990 | dev->dev.bus = &pci_bus_type; | |
991 | dev->devfn = devfn; | |
992 | dev->hdr_type = hdr_type & 0x7f; | |
993 | dev->multifunction = !!(hdr_type & 0x80); | |
994 | dev->vendor = l & 0xffff; | |
995 | dev->device = (l >> 16) & 0xffff; | |
996 | dev->cfg_size = pci_cfg_space_size(dev); | |
82081797 | 997 | dev->error_state = pci_channel_io_normal; |
994a65e2 | 998 | set_pcie_port_type(dev); |
1da177e4 LT |
999 | |
1000 | /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer) | |
1001 | set this higher, assuming the system even supports it. */ | |
1002 | dev->dma_mask = 0xffffffff; | |
1003 | if (pci_setup_device(dev) < 0) { | |
1004 | kfree(dev); | |
1005 | return NULL; | |
1006 | } | |
1da177e4 | 1007 | |
94e61088 BH |
1008 | pci_vpd_pci22_init(dev); |
1009 | ||
1da177e4 LT |
1010 | return dev; |
1011 | } | |
1012 | ||
96bde06a | 1013 | void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) |
1da177e4 | 1014 | { |
cdb9b9f7 PM |
1015 | device_initialize(&dev->dev); |
1016 | dev->dev.release = pci_release_dev; | |
1017 | pci_dev_get(dev); | |
1da177e4 | 1018 | |
cdb9b9f7 | 1019 | dev->dev.dma_mask = &dev->dma_mask; |
4d57cdfa | 1020 | dev->dev.dma_parms = &dev->dma_parms; |
cdb9b9f7 | 1021 | dev->dev.coherent_dma_mask = 0xffffffffull; |
1da177e4 | 1022 | |
4d57cdfa | 1023 | pci_set_dma_max_seg_size(dev, 65536); |
59fc67de | 1024 | pci_set_dma_seg_boundary(dev, 0xffffffff); |
4d57cdfa | 1025 | |
1da177e4 LT |
1026 | /* Fix up broken headers */ |
1027 | pci_fixup_device(pci_fixup_header, dev); | |
1028 | ||
eb9d0fe4 RW |
1029 | /* Initialize power management of the device */ |
1030 | pci_pm_init(dev); | |
1031 | ||
1da177e4 LT |
1032 | /* |
1033 | * Add the device to our list of discovered devices | |
1034 | * and the bus list for fixup functions, etc. | |
1035 | */ | |
d71374da | 1036 | down_write(&pci_bus_sem); |
1da177e4 | 1037 | list_add_tail(&dev->bus_list, &bus->devices); |
d71374da | 1038 | up_write(&pci_bus_sem); |
cdb9b9f7 PM |
1039 | } |
1040 | ||
451124a7 | 1041 | struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn) |
cdb9b9f7 PM |
1042 | { |
1043 | struct pci_dev *dev; | |
1044 | ||
1045 | dev = pci_scan_device(bus, devfn); | |
1046 | if (!dev) | |
1047 | return NULL; | |
1048 | ||
1049 | pci_device_add(dev, bus); | |
1da177e4 LT |
1050 | |
1051 | return dev; | |
1052 | } | |
b73e9687 | 1053 | EXPORT_SYMBOL(pci_scan_single_device); |
1da177e4 LT |
1054 | |
1055 | /** | |
1056 | * pci_scan_slot - scan a PCI slot on a bus for devices. | |
1057 | * @bus: PCI bus to scan | |
1058 | * @devfn: slot number to scan (must have zero function.) | |
1059 | * | |
1060 | * Scan a PCI slot on the specified PCI bus for devices, adding | |
1061 | * discovered devices to the @bus->devices list. New devices | |
8a1bc901 | 1062 | * will not have is_added set. |
1da177e4 | 1063 | */ |
96bde06a | 1064 | int pci_scan_slot(struct pci_bus *bus, int devfn) |
1da177e4 LT |
1065 | { |
1066 | int func, nr = 0; | |
1067 | int scan_all_fns; | |
1068 | ||
1069 | scan_all_fns = pcibios_scan_all_fns(bus, devfn); | |
1070 | ||
1071 | for (func = 0; func < 8; func++, devfn++) { | |
1072 | struct pci_dev *dev; | |
1073 | ||
1074 | dev = pci_scan_single_device(bus, devfn); | |
1075 | if (dev) { | |
1076 | nr++; | |
1077 | ||
1078 | /* | |
1079 | * If this is a single function device, | |
1080 | * don't scan past the first function. | |
1081 | */ | |
1082 | if (!dev->multifunction) { | |
1083 | if (func > 0) { | |
1084 | dev->multifunction = 1; | |
1085 | } else { | |
1086 | break; | |
1087 | } | |
1088 | } | |
1089 | } else { | |
1090 | if (func == 0 && !scan_all_fns) | |
1091 | break; | |
1092 | } | |
1093 | } | |
7d715a6c | 1094 | |
149e1637 SL |
1095 | /* only one slot has pcie device */ |
1096 | if (bus->self && nr) | |
7d715a6c SL |
1097 | pcie_aspm_init_link_state(bus->self); |
1098 | ||
1da177e4 LT |
1099 | return nr; |
1100 | } | |
1101 | ||
0ab2b57f | 1102 | unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus) |
1da177e4 LT |
1103 | { |
1104 | unsigned int devfn, pass, max = bus->secondary; | |
1105 | struct pci_dev *dev; | |
1106 | ||
1107 | pr_debug("PCI: Scanning bus %04x:%02x\n", pci_domain_nr(bus), bus->number); | |
1108 | ||
1109 | /* Go find them, Rover! */ | |
1110 | for (devfn = 0; devfn < 0x100; devfn += 8) | |
1111 | pci_scan_slot(bus, devfn); | |
1112 | ||
1113 | /* | |
1114 | * After performing arch-dependent fixup of the bus, look behind | |
1115 | * all PCI-to-PCI bridges on this bus. | |
1116 | */ | |
1117 | pr_debug("PCI: Fixups for bus %04x:%02x\n", pci_domain_nr(bus), bus->number); | |
1118 | pcibios_fixup_bus(bus); | |
1119 | for (pass=0; pass < 2; pass++) | |
1120 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1121 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || | |
1122 | dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) | |
1123 | max = pci_scan_bridge(bus, dev, max, pass); | |
1124 | } | |
1125 | ||
1126 | /* | |
1127 | * We've scanned the bus and so we know all about what's on | |
1128 | * the other side of any bridges that may be on this bus plus | |
1129 | * any devices. | |
1130 | * | |
1131 | * Return how far we've got finding sub-buses. | |
1132 | */ | |
1133 | pr_debug("PCI: Bus scan for %04x:%02x returning with max=%02x\n", | |
1134 | pci_domain_nr(bus), bus->number, max); | |
1135 | return max; | |
1136 | } | |
1137 | ||
30a18d6c YL |
1138 | void __attribute__((weak)) set_pci_bus_resources_arch_default(struct pci_bus *b) |
1139 | { | |
1140 | } | |
1141 | ||
96bde06a | 1142 | struct pci_bus * pci_create_bus(struct device *parent, |
cdb9b9f7 | 1143 | int bus, struct pci_ops *ops, void *sysdata) |
1da177e4 LT |
1144 | { |
1145 | int error; | |
1146 | struct pci_bus *b; | |
1147 | struct device *dev; | |
1148 | ||
1149 | b = pci_alloc_bus(); | |
1150 | if (!b) | |
1151 | return NULL; | |
1152 | ||
1153 | dev = kmalloc(sizeof(*dev), GFP_KERNEL); | |
1154 | if (!dev){ | |
1155 | kfree(b); | |
1156 | return NULL; | |
1157 | } | |
1158 | ||
1159 | b->sysdata = sysdata; | |
1160 | b->ops = ops; | |
1161 | ||
1162 | if (pci_find_bus(pci_domain_nr(b), bus)) { | |
1163 | /* If we already got to this bus through a different bridge, ignore it */ | |
1164 | pr_debug("PCI: Bus %04x:%02x already known\n", pci_domain_nr(b), bus); | |
1165 | goto err_out; | |
1166 | } | |
d71374da ZY |
1167 | |
1168 | down_write(&pci_bus_sem); | |
1da177e4 | 1169 | list_add_tail(&b->node, &pci_root_buses); |
d71374da | 1170 | up_write(&pci_bus_sem); |
1da177e4 LT |
1171 | |
1172 | memset(dev, 0, sizeof(*dev)); | |
1173 | dev->parent = parent; | |
1174 | dev->release = pci_release_bus_bridge_dev; | |
1175 | sprintf(dev->bus_id, "pci%04x:%02x", pci_domain_nr(b), bus); | |
1176 | error = device_register(dev); | |
1177 | if (error) | |
1178 | goto dev_reg_err; | |
1179 | b->bridge = get_device(dev); | |
1180 | ||
0d358f22 YL |
1181 | if (!parent) |
1182 | set_dev_node(b->bridge, pcibus_to_node(b)); | |
1183 | ||
fd7d1ced GKH |
1184 | b->dev.class = &pcibus_class; |
1185 | b->dev.parent = b->bridge; | |
1186 | sprintf(b->dev.bus_id, "%04x:%02x", pci_domain_nr(b), bus); | |
1187 | error = device_register(&b->dev); | |
1da177e4 LT |
1188 | if (error) |
1189 | goto class_dev_reg_err; | |
fd7d1ced | 1190 | error = device_create_file(&b->dev, &dev_attr_cpuaffinity); |
1da177e4 | 1191 | if (error) |
fd7d1ced | 1192 | goto dev_create_file_err; |
1da177e4 LT |
1193 | |
1194 | /* Create legacy_io and legacy_mem files for this bus */ | |
1195 | pci_create_legacy_files(b); | |
1196 | ||
1da177e4 LT |
1197 | b->number = b->secondary = bus; |
1198 | b->resource[0] = &ioport_resource; | |
1199 | b->resource[1] = &iomem_resource; | |
1200 | ||
30a18d6c YL |
1201 | set_pci_bus_resources_arch_default(b); |
1202 | ||
1da177e4 LT |
1203 | return b; |
1204 | ||
fd7d1ced GKH |
1205 | dev_create_file_err: |
1206 | device_unregister(&b->dev); | |
1da177e4 LT |
1207 | class_dev_reg_err: |
1208 | device_unregister(dev); | |
1209 | dev_reg_err: | |
d71374da | 1210 | down_write(&pci_bus_sem); |
1da177e4 | 1211 | list_del(&b->node); |
d71374da | 1212 | up_write(&pci_bus_sem); |
1da177e4 LT |
1213 | err_out: |
1214 | kfree(dev); | |
1215 | kfree(b); | |
1216 | return NULL; | |
1217 | } | |
cdb9b9f7 | 1218 | |
0ab2b57f | 1219 | struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent, |
cdb9b9f7 PM |
1220 | int bus, struct pci_ops *ops, void *sysdata) |
1221 | { | |
1222 | struct pci_bus *b; | |
1223 | ||
1224 | b = pci_create_bus(parent, bus, ops, sysdata); | |
1225 | if (b) | |
1226 | b->subordinate = pci_scan_child_bus(b); | |
1227 | return b; | |
1228 | } | |
1da177e4 LT |
1229 | EXPORT_SYMBOL(pci_scan_bus_parented); |
1230 | ||
1231 | #ifdef CONFIG_HOTPLUG | |
1232 | EXPORT_SYMBOL(pci_add_new_bus); | |
1da177e4 LT |
1233 | EXPORT_SYMBOL(pci_scan_slot); |
1234 | EXPORT_SYMBOL(pci_scan_bridge); | |
1da177e4 LT |
1235 | EXPORT_SYMBOL_GPL(pci_scan_child_bus); |
1236 | #endif | |
6b4b78fe | 1237 | |
99178b03 | 1238 | static int __init pci_sort_bf_cmp(const struct device *d_a, const struct device *d_b) |
6b4b78fe | 1239 | { |
99178b03 GKH |
1240 | const struct pci_dev *a = to_pci_dev(d_a); |
1241 | const struct pci_dev *b = to_pci_dev(d_b); | |
1242 | ||
6b4b78fe MD |
1243 | if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1; |
1244 | else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1; | |
1245 | ||
1246 | if (a->bus->number < b->bus->number) return -1; | |
1247 | else if (a->bus->number > b->bus->number) return 1; | |
1248 | ||
1249 | if (a->devfn < b->devfn) return -1; | |
1250 | else if (a->devfn > b->devfn) return 1; | |
1251 | ||
1252 | return 0; | |
1253 | } | |
1254 | ||
5ff580c1 | 1255 | void __init pci_sort_breadthfirst(void) |
6b4b78fe | 1256 | { |
99178b03 | 1257 | bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp); |
6b4b78fe | 1258 | } |