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[PATCH] PCI Hotplug ibmphp_pci.c: Fix masking out needed information too early
[deliverable/linux.git] / drivers / pci / quirks.c
CommitLineData
1da177e4
LT		 1/*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
10 * The bridge optimization stuff has been removed. If you really
11 * have a silly BIOS which is unable to set your host bridge right,
12 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
13 */
14
15#include <linux/config.h>
16#include <linux/types.h>
17#include <linux/kernel.h>
18#include <linux/pci.h>
19#include <linux/init.h>
20#include <linux/delay.h>
bc56b9e0 21#include "pci.h"
1da177e4
LT		 22
23/* Deal with broken BIOS'es that neglect to enable passive release,
24 which can cause problems in combination with the 82441FX/PPro MTRRs */
25static void __devinit quirk_passive_release(struct pci_dev *dev)
26{
27 struct pci_dev *d = NULL;
28 unsigned char dlc;
29
30 /* We have to make sure a particular bit is set in the PIIX3
31 ISA bridge, so we have to go out and find it. */
32 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
33 pci_read_config_byte(d, 0x82, &dlc);
34 if (!(dlc & 1<<1)) {
35 printk(KERN_ERR "PCI: PIIX3: Enabling Passive Release on %s\n", pci_name(d));
36 dlc |= 1<<1;
37 pci_write_config_byte(d, 0x82, dlc);
38 }
39 }
40}
41DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release );
42
43/* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
44 but VIA don't answer queries. If you happen to have good contacts at VIA
45 ask them for me please -- Alan
46
47 This appears to be BIOS not version dependent. So presumably there is a
48 chipset level fix */
49int isa_dma_bridge_buggy; /* Exported */
50
51static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
52{
53 if (!isa_dma_bridge_buggy) {
54 isa_dma_bridge_buggy=1;
55 printk(KERN_INFO "Activating ISA DMA hang workarounds.\n");
56 }
57}
58 /*
59 * Its not totally clear which chipsets are the problematic ones
60 * We know 82C586 and 82C596 variants are affected.
61 */
62DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs );
63DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs );
64DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs );
65DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs );
66DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs );
67DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs );
68DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs );
69
70int pci_pci_problems;
71
72/*
73 * Chipsets where PCI->PCI transfers vanish or hang
74 */
75static void __devinit quirk_nopcipci(struct pci_dev *dev)
76{
77 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
78 printk(KERN_INFO "Disabling direct PCI/PCI transfers.\n");
79 pci_pci_problems |= PCIPCI_FAIL;
80 }
81}
82DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci );
83DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci );
84
85/*
86 * Triton requires workarounds to be used by the drivers
87 */
88static void __devinit quirk_triton(struct pci_dev *dev)
89{
90 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
91 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
92 pci_pci_problems |= PCIPCI_TRITON;
93 }
94}
95DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton );
96DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton );
97DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton );
98DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton );
99
100/*
101 * VIA Apollo KT133 needs PCI latency patch
102 * Made according to a windows driver based patch by George E. Breese
103 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
104 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
105 * the info on which Mr Breese based his work.
106 *
107 * Updated based on further information from the site and also on
108 * information provided by VIA
109 */
110static void __devinit quirk_vialatency(struct pci_dev *dev)
111{
112 struct pci_dev *p;
113 u8 rev;
114 u8 busarb;
115 /* Ok we have a potential problem chipset here. Now see if we have
116 a buggy southbridge */
117
118 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
119 if (p!=NULL) {
120 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
121 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
122 /* Check for buggy part revisions */
123 if (rev < 0x40 || rev > 0x42)
124 goto exit;
125 } else {
126 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
127 if (p==NULL) /* No problem parts */
128 goto exit;
129 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
130 /* Check for buggy part revisions */
131 if (rev < 0x10 || rev > 0x12)
132 goto exit;
133 }
134
135 /*
136 * Ok we have the problem. Now set the PCI master grant to
137 * occur every master grant. The apparent bug is that under high
138 * PCI load (quite common in Linux of course) you can get data
139 * loss when the CPU is held off the bus for 3 bus master requests
140 * This happens to include the IDE controllers....
141 *
142 * VIA only apply this fix when an SB Live! is present but under
143 * both Linux and Windows this isnt enough, and we have seen
144 * corruption without SB Live! but with things like 3 UDMA IDE
145 * controllers. So we ignore that bit of the VIA recommendation..
146 */
147
148 pci_read_config_byte(dev, 0x76, &busarb);
149 /* Set bit 4 and bi 5 of byte 76 to 0x01
150 "Master priority rotation on every PCI master grant */
151 busarb &= ~(1<<5);
152 busarb |= (1<<4);
153 pci_write_config_byte(dev, 0x76, busarb);
154 printk(KERN_INFO "Applying VIA southbridge workaround.\n");
155exit:
156 pci_dev_put(p);
157}
158DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency );
159DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency );
160DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency );
161
162/*
163 * VIA Apollo VP3 needs ETBF on BT848/878
164 */
165static void __devinit quirk_viaetbf(struct pci_dev *dev)
166{
167 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
168 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
169 pci_pci_problems |= PCIPCI_VIAETBF;
170 }
171}
172DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf );
173
174static void __devinit quirk_vsfx(struct pci_dev *dev)
175{
176 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
177 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
178 pci_pci_problems |= PCIPCI_VSFX;
179 }
180}
181DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx );
182
183/*
184 * Ali Magik requires workarounds to be used by the drivers
185 * that DMA to AGP space. Latency must be set to 0xA and triton
186 * workaround applied too
187 * [Info kindly provided by ALi]
188 */
189static void __init quirk_alimagik(struct pci_dev *dev)
190{
191 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
192 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
193 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
194 }
195}
196DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik );
197DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik );
198
199/*
200 * Natoma has some interesting boundary conditions with Zoran stuff
201 * at least
202 */
203static void __devinit quirk_natoma(struct pci_dev *dev)
204{
205 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
206 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
207 pci_pci_problems |= PCIPCI_NATOMA;
208 }
209}
210DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma );
211DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma );
212DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma );
213DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma );
214DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma );
215DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma );
216
217/*
218 * This chip can cause PCI parity errors if config register 0xA0 is read
219 * while DMAs are occurring.
220 */
221static void __devinit quirk_citrine(struct pci_dev *dev)
222{
223 dev->cfg_size = 0xA0;
224}
225DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine );
226
227/*
228 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
229 * If it's needed, re-allocate the region.
230 */
231static void __devinit quirk_s3_64M(struct pci_dev *dev)
232{
233 struct resource *r = &dev->resource[0];
234
235 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
236 r->start = 0;
237 r->end = 0x3ffffff;
238 }
239}
240DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M );
241DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M );
242
243static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region, unsigned size, int nr)
244{
245 region &= ~(size-1);
246 if (region) {
247 struct resource *res = dev->resource + nr;
248
249 res->name = pci_name(dev);
250 res->start = region;
251 res->end = region + size - 1;
252 res->flags = IORESOURCE_IO;
253 pci_claim_resource(dev, nr);
254 }
255}
256
257/*
258 * ATI Northbridge setups MCE the processor if you even
259 * read somewhere between 0x3b0->0x3bb or read 0x3d3
260 */
261static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
262{
263 printk(KERN_INFO "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb.\n");
264 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
265 request_region(0x3b0, 0x0C, "RadeonIGP");
266 request_region(0x3d3, 0x01, "RadeonIGP");
267}
268DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce );
269
270/*
271 * Let's make the southbridge information explicit instead
272 * of having to worry about people probing the ACPI areas,
273 * for example.. (Yes, it happens, and if you read the wrong
274 * ACPI register it will put the machine to sleep with no
275 * way of waking it up again. Bummer).
276 *
277 * ALI M7101: Two IO regions pointed to by words at
278 * 0xE0 (64 bytes of ACPI registers)
279 * 0xE2 (32 bytes of SMB registers)
280 */
281static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
282{
283 u16 region;
284
285 pci_read_config_word(dev, 0xE0, &region);
286 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES);
287 pci_read_config_word(dev, 0xE2, &region);
288 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1);
289}
290DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi );
291
292/*
293 * PIIX4 ACPI: Two IO regions pointed to by longwords at
294 * 0x40 (64 bytes of ACPI registers)
295 * 0x90 (32 bytes of SMB registers)
296 */
297static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
298{
299 u32 region;
300
301 pci_read_config_dword(dev, 0x40, &region);
302 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES);
303 pci_read_config_dword(dev, 0x90, &region);
304 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1);
305}
306DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi );
307
308/*
309 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
310 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
311 * 0x58 (64 bytes of GPIO I/O space)
312 */
313static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
314{
315 u32 region;
316
317 pci_read_config_dword(dev, 0x40, &region);
318 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES);
319
320 pci_read_config_dword(dev, 0x58, &region);
321 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1);
322}
323DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi );
324DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi );
325DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi );
326DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi );
327DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi );
328DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi );
329DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi );
330DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi );
331DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi );
332
333/*
334 * VIA ACPI: One IO region pointed to by longword at
335 * 0x48 or 0x20 (256 bytes of ACPI registers)
336 */
337static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
338{
339 u8 rev;
340 u32 region;
341
342 pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
343 if (rev & 0x10) {
344 pci_read_config_dword(dev, 0x48, &region);
345 region &= PCI_BASE_ADDRESS_IO_MASK;
346 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES);
347 }
348}
349DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi );
350
351/*
352 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
353 * 0x48 (256 bytes of ACPI registers)
354 * 0x70 (128 bytes of hardware monitoring register)
355 * 0x90 (16 bytes of SMB registers)
356 */
357static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
358{
359 u16 hm;
360 u32 smb;
361
362 quirk_vt82c586_acpi(dev);
363
364 pci_read_config_word(dev, 0x70, &hm);
365 hm &= PCI_BASE_ADDRESS_IO_MASK;
366 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1);
367
368 pci_read_config_dword(dev, 0x90, &smb);
369 smb &= PCI_BASE_ADDRESS_IO_MASK;
370 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2);
371}
372DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi );
373
374
375#ifdef CONFIG_X86_IO_APIC
376
377#include <asm/io_apic.h>
378
379/*
380 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
381 * devices to the external APIC.
382 *
383 * TODO: When we have device-specific interrupt routers,
384 * this code will go away from quirks.
385 */
386static void __devinit quirk_via_ioapic(struct pci_dev *dev)
387{
388 u8 tmp;
389
390 if (nr_ioapics < 1)
391 tmp = 0; /* nothing routed to external APIC */
392 else
393 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
394
395 printk(KERN_INFO "PCI: %sbling Via external APIC routing\n",
396 tmp == 0 ? "Disa" : "Ena");
397
398 /* Offset 0x58: External APIC IRQ output control */
399 pci_write_config_byte (dev, 0x58, tmp);
400}
401DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic );
402
403/*
404 * The AMD io apic can hang the box when an apic irq is masked.
405 * We check all revs >= B0 (yet not in the pre production!) as the bug
406 * is currently marked NoFix
407 *
408 * We have multiple reports of hangs with this chipset that went away with
409 * noapic specified. For the moment we assume its the errata. We may be wrong
410 * of course. However the advice is demonstrably good even if so..
411 */
412static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
413{
414 u8 rev;
415
416 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
417 if (rev >= 0x02) {
418 printk(KERN_WARNING "I/O APIC: AMD Errata #22 may be present. In the event of instability try\n");
419 printk(KERN_WARNING " : booting with the \"noapic\" option.\n");
420 }
421}
422DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic );
423
424static void __init quirk_ioapic_rmw(struct pci_dev *dev)
425{
426 if (dev->devfn == 0 && dev->bus->number == 0)
427 sis_apic_bug = 1;
428}
429DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw );
430
431int pci_msi_quirk;
432
433#define AMD8131_revA0 0x01
434#define AMD8131_revB0 0x11
435#define AMD8131_MISC 0x40
436#define AMD8131_NIOAMODE_BIT 0
437static void __init quirk_amd_8131_ioapic(struct pci_dev *dev)
438{
439 unsigned char revid, tmp;
440
441 pci_msi_quirk = 1;
442 printk(KERN_WARNING "PCI: MSI quirk detected. pci_msi_quirk set.\n");
443
444 if (nr_ioapics == 0)
445 return;
446
447 pci_read_config_byte(dev, PCI_REVISION_ID, &revid);
448 if (revid == AMD8131_revA0 || revid == AMD8131_revB0) {
449 printk(KERN_INFO "Fixing up AMD8131 IOAPIC mode\n");
450 pci_read_config_byte( dev, AMD8131_MISC, &tmp);
451 tmp &= ~(1 << AMD8131_NIOAMODE_BIT);
452 pci_write_config_byte( dev, AMD8131_MISC, tmp);
453 }
454}
455DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_APIC, quirk_amd_8131_ioapic );
456
457#endif /* CONFIG_X86_IO_APIC */
458
459
460/*
461 * Via 686A/B: The PCI_INTERRUPT_LINE register for the on-chip
462 * devices, USB0/1, AC97, MC97, and ACPI, has an unusual feature:
463 * when written, it makes an internal connection to the PIC.
464 * For these devices, this register is defined to be 4 bits wide.
465 * Normally this is fine. However for IO-APIC motherboards, or
466 * non-x86 architectures (yes Via exists on PPC among other places),
467 * we must mask the PCI_INTERRUPT_LINE value versus 0xf to get
468 * interrupts delivered properly.
469 *
470 * TODO: When we have device-specific interrupt routers,
471 * quirk_via_irqpic will go away from quirks.
472 */
473
474/*
475 * FIXME: it is questionable that quirk_via_acpi
476 * is needed. It shows up as an ISA bridge, and does not
477 * support the PCI_INTERRUPT_LINE register at all. Therefore
478 * it seems like setting the pci_dev's 'irq' to the
479 * value of the ACPI SCI interrupt is only done for convenience.
480 * -jgarzik
481 */
482static void __devinit quirk_via_acpi(struct pci_dev *d)
483{
484 /*
485 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
486 */
487 u8 irq;
488 pci_read_config_byte(d, 0x42, &irq);
489 irq &= 0xf;
490 if (irq && (irq != 2))
491 d->irq = irq;
492}
493DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi );
494DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi );
495
496/*
497 * PIIX3 USB: We have to disable USB interrupts that are
498 * hardwired to PIRQD# and may be shared with an
499 * external device.
500 *
501 * Legacy Support Register (LEGSUP):
502 * bit13: USB PIRQ Enable (USBPIRQDEN),
503 * bit4: Trap/SMI On IRQ Enable (USBSMIEN).
504 *
505 * We mask out all r/wc bits, too.
506 */
507static void __devinit quirk_piix3_usb(struct pci_dev *dev)
508{
509 u16 legsup;
510
511 pci_read_config_word(dev, 0xc0, &legsup);
512 legsup &= 0x50ef;
513 pci_write_config_word(dev, 0xc0, legsup);
514}
515DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_2, quirk_piix3_usb );
516DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_2, quirk_piix3_usb );
517
518/*
519 * VIA VT82C598 has its device ID settable and many BIOSes
520 * set it to the ID of VT82C597 for backward compatibility.
521 * We need to switch it off to be able to recognize the real
522 * type of the chip.
523 */
524static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
525{
526 pci_write_config_byte(dev, 0xfc, 0);
527 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
528}
529DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id );
530
531/*
532 * CardBus controllers have a legacy base address that enables them
533 * to respond as i82365 pcmcia controllers. We don't want them to
534 * do this even if the Linux CardBus driver is not loaded, because
535 * the Linux i82365 driver does not (and should not) handle CardBus.
536 */
537static void __devinit quirk_cardbus_legacy(struct pci_dev *dev)
538{
539 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class)
540 return;
541 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
542}
543DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
544
545/*
546 * Following the PCI ordering rules is optional on the AMD762. I'm not
547 * sure what the designers were smoking but let's not inhale...
548 *
549 * To be fair to AMD, it follows the spec by default, its BIOS people
550 * who turn it off!
551 */
552static void __devinit quirk_amd_ordering(struct pci_dev *dev)
553{
554 u32 pcic;
555 pci_read_config_dword(dev, 0x4C, &pcic);
556 if ((pcic&6)!=6) {
557 pcic |= 6;
558 printk(KERN_WARNING "BIOS failed to enable PCI standards compliance, fixing this error.\n");
559 pci_write_config_dword(dev, 0x4C, pcic);
560 pci_read_config_dword(dev, 0x84, &pcic);
561 pcic |= (1<<23); /* Required in this mode */
562 pci_write_config_dword(dev, 0x84, pcic);
563 }
564}
565DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering );
566
567/*
568 * DreamWorks provided workaround for Dunord I-3000 problem
569 *
570 * This card decodes and responds to addresses not apparently
571 * assigned to it. We force a larger allocation to ensure that
572 * nothing gets put too close to it.
573 */
574static void __devinit quirk_dunord ( struct pci_dev * dev )
575{
576 struct resource *r = &dev->resource [1];
577 r->start = 0;
578 r->end = 0xffffff;
579}
580DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord );
581
582/*
583 * i82380FB mobile docking controller: its PCI-to-PCI bridge
584 * is subtractive decoding (transparent), and does indicate this
585 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
586 * instead of 0x01.
587 */
588static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
589{
590 dev->transparent = 1;
591}
592DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge );
593DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge );
594
595/*
596 * Common misconfiguration of the MediaGX/Geode PCI master that will
597 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
598 * datasheets found at http://www.national.com/ds/GX for info on what
599 * these bits do. <christer@weinigel.se>
600 */
601static void __init quirk_mediagx_master(struct pci_dev *dev)
602{
603 u8 reg;
604 pci_read_config_byte(dev, 0x41, &reg);
605 if (reg & 2) {
606 reg &= ~2;
607 printk(KERN_INFO "PCI: Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
608 pci_write_config_byte(dev, 0x41, reg);
609 }
610}
611DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master );
612
613/*
614 * As per PCI spec, ignore base address registers 0-3 of the IDE controllers
615 * running in Compatible mode (bits 0 and 2 in the ProgIf for primary and
616 * secondary channels respectively). If the device reports Compatible mode
617 * but does use BAR0-3 for address decoding, we assume that firmware has
618 * programmed these BARs with standard values (0x1f0,0x3f4 and 0x170,0x374).
619 * Exceptions (if they exist) must be handled in chip/architecture specific
620 * fixups.
621 *
622 * Note: for non x86 people. You may need an arch specific quirk to handle
623 * moving IDE devices to native mode as well. Some plug in card devices power
624 * up in compatible mode and assume the BIOS will adjust them.
625 *
626 * Q: should we load the 0x1f0,0x3f4 into the registers or zap them as
627 * we do now ? We don't want is pci_enable_device to come along
628 * and assign new resources. Both approaches work for that.
629 */
630static void __devinit quirk_ide_bases(struct pci_dev *dev)
631{
632 struct resource *res;
633 int first_bar = 2, last_bar = 0;
634
635 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
636 return;
637
638 res = &dev->resource[0];
639
640 /* primary channel: ProgIf bit 0, BAR0, BAR1 */
641 if (!(dev->class & 1) && (res[0].flags || res[1].flags)) {
642 res[0].start = res[0].end = res[0].flags = 0;
643 res[1].start = res[1].end = res[1].flags = 0;
644 first_bar = 0;
645 last_bar = 1;
646 }
647
648 /* secondary channel: ProgIf bit 2, BAR2, BAR3 */
649 if (!(dev->class & 4) && (res[2].flags || res[3].flags)) {
650 res[2].start = res[2].end = res[2].flags = 0;
651 res[3].start = res[3].end = res[3].flags = 0;
652 last_bar = 3;
653 }
654
655 if (!last_bar)
656 return;
657
658 printk(KERN_INFO "PCI: Ignoring BAR%d-%d of IDE controller %s\n",
659 first_bar, last_bar, pci_name(dev));
660}
661DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_ide_bases);
662
663/*
664 * Ensure C0 rev restreaming is off. This is normally done by
665 * the BIOS but in the odd case it is not the results are corruption
666 * hence the presence of a Linux check
667 */
668static void __init quirk_disable_pxb(struct pci_dev *pdev)
669{
670 u16 config;
671 u8 rev;
672
673 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
674 if (rev != 0x04) /* Only C0 requires this */
675 return;
676 pci_read_config_word(pdev, 0x40, &config);
677 if (config & (1<<6)) {
678 config &= ~(1<<6);
679 pci_write_config_word(pdev, 0x40, config);
680 printk(KERN_INFO "PCI: C0 revision 450NX. Disabling PCI restreaming.\n");
681 }
682}
683DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb );
684
685/*
686 * VIA northbridges care about PCI_INTERRUPT_LINE
687 */
688int via_interrupt_line_quirk;
689
690static void __devinit quirk_via_bridge(struct pci_dev *pdev)
691{
692 if(pdev->devfn == 0) {
693 printk(KERN_INFO "PCI: Via IRQ fixup\n");
694 via_interrupt_line_quirk = 1;
695 }
696}
697DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_bridge );
698
699/*
700 * Serverworks CSB5 IDE does not fully support native mode
701 */
702static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev)
703{
704 u8 prog;
705 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
706 if (prog & 5) {
707 prog &= ~5;
708 pdev->class &= ~5;
709 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
710 /* need to re-assign BARs for compat mode */
711 quirk_ide_bases(pdev);
712 }
713}
714DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide );
715
716/*
717 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
718 */
719static void __init quirk_ide_samemode(struct pci_dev *pdev)
720{
721 u8 prog;
722
723 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
724
725 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
726 printk(KERN_INFO "PCI: IDE mode mismatch; forcing legacy mode\n");
727 prog &= ~5;
728 pdev->class &= ~5;
729 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
730 /* need to re-assign BARs for compat mode */
731 quirk_ide_bases(pdev);
732 }
733}
734DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
735
736/* This was originally an Alpha specific thing, but it really fits here.
737 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
738 */
739static void __init quirk_eisa_bridge(struct pci_dev *dev)
740{
741 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
742}
743DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge );
744
745/*
746 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
747 * is not activated. The myth is that Asus said that they do not want the
748 * users to be irritated by just another PCI Device in the Win98 device
749 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
750 * package 2.7.0 for details)
751 *
752 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
753 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
754 * becomes necessary to do this tweak in two steps -- I've chosen the Host
755 * bridge as trigger.
756 */
757static int __initdata asus_hides_smbus = 0;
758
759static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
760{
761 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
762 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
763 switch(dev->subsystem_device) {
764 case 0x8070: /* P4B */
765 case 0x8088: /* P4B533 */
766 case 0x1626: /* L3C notebook */
767 asus_hides_smbus = 1;
768 }
769 if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
770 switch(dev->subsystem_device) {
771 case 0x80b1: /* P4GE-V */
772 case 0x80b2: /* P4PE */
773 case 0x8093: /* P4B533-V */
774 asus_hides_smbus = 1;
775 }
776 if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
777 switch(dev->subsystem_device) {
778 case 0x8030: /* P4T533 */
779 asus_hides_smbus = 1;
780 }
781 if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
782 switch (dev->subsystem_device) {
783 case 0x8070: /* P4G8X Deluxe */
784 asus_hides_smbus = 1;
785 }
786 if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
787 switch (dev->subsystem_device) {
788 case 0x1751: /* M2N notebook */
789 case 0x1821: /* M5N notebook */
790 asus_hides_smbus = 1;
791 }
792 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
793 switch (dev->subsystem_device) {
794 case 0x184b: /* W1N notebook */
795 case 0x186a: /* M6Ne notebook */
796 asus_hides_smbus = 1;
797 }
798 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
799 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
800 switch(dev->subsystem_device) {
801 case 0x088C: /* HP Compaq nc8000 */
802 case 0x0890: /* HP Compaq nc6000 */
803 asus_hides_smbus = 1;
804 }
805 if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
806 switch (dev->subsystem_device) {
807 case 0x12bc: /* HP D330L */
808 asus_hides_smbus = 1;
809 }
810 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_TOSHIBA)) {
811 if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
812 switch(dev->subsystem_device) {
813 case 0x0001: /* Toshiba Satellite A40 */
814 asus_hides_smbus = 1;
815 }
816 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
817 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
818 switch(dev->subsystem_device) {
819 case 0xC00C: /* Samsung P35 notebook */
820 asus_hides_smbus = 1;
821 }
822 }
823}
824DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge );
825DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge );
826DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge );
827DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge );
828DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge );
829DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge );
830DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge );
831
832static void __init asus_hides_smbus_lpc(struct pci_dev *dev)
833{
834 u16 val;
835
836 if (likely(!asus_hides_smbus))
837 return;
838
839 pci_read_config_word(dev, 0xF2, &val);
840 if (val & 0x8) {
841 pci_write_config_word(dev, 0xF2, val & (~0x8));
842 pci_read_config_word(dev, 0xF2, &val);
843 if (val & 0x8)
844 printk(KERN_INFO "PCI: i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
845 else
846 printk(KERN_INFO "PCI: Enabled i801 SMBus device\n");
847 }
848}
849DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc );
850DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc );
851DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc );
852DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc );
853DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc );
854
855/*
856 * SiS 96x south bridge: BIOS typically hides SMBus device...
857 */
858static void __init quirk_sis_96x_smbus(struct pci_dev *dev)
859{
860 u8 val = 0;
861 printk(KERN_INFO "Enabling SiS 96x SMBus.\n");
862 pci_read_config_byte(dev, 0x77, &val);
863 pci_write_config_byte(dev, 0x77, val & ~0x10);
864 pci_read_config_byte(dev, 0x77, &val);
865}
866
867
868#define UHCI_USBLEGSUP 0xc0 /* legacy support */
869#define UHCI_USBCMD 0 /* command register */
870#define UHCI_USBSTS 2 /* status register */
871#define UHCI_USBINTR 4 /* interrupt register */
872#define UHCI_USBLEGSUP_DEFAULT 0x2000 /* only PIRQ enable set */
873#define UHCI_USBCMD_RUN (1 << 0) /* RUN/STOP bit */
874#define UHCI_USBCMD_GRESET (1 << 2) /* Global reset */
875#define UHCI_USBCMD_CONFIGURE (1 << 6) /* config semaphore */
876#define UHCI_USBSTS_HALTED (1 << 5) /* HCHalted bit */
877
878#define OHCI_CONTROL 0x04
879#define OHCI_CMDSTATUS 0x08
880#define OHCI_INTRSTATUS 0x0c
881#define OHCI_INTRENABLE 0x10
882#define OHCI_INTRDISABLE 0x14
883#define OHCI_OCR (1 << 3) /* ownership change request */
884#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */
885#define OHCI_INTR_OC (1 << 30) /* ownership change */
886
887#define EHCI_HCC_PARAMS 0x08 /* extended capabilities */
888#define EHCI_USBCMD 0 /* command register */
889#define EHCI_USBCMD_RUN (1 << 0) /* RUN/STOP bit */
890#define EHCI_USBSTS 4 /* status register */
891#define EHCI_USBSTS_HALTED (1 << 12) /* HCHalted bit */
892#define EHCI_USBINTR 8 /* interrupt register */
893#define EHCI_USBLEGSUP 0 /* legacy support register */
894#define EHCI_USBLEGSUP_BIOS (1 << 16) /* BIOS semaphore */
895#define EHCI_USBLEGSUP_OS (1 << 24) /* OS semaphore */
896#define EHCI_USBLEGCTLSTS 4 /* legacy control/status */
897#define EHCI_USBLEGCTLSTS_SOOE (1 << 13) /* SMI on ownership change */
898
899int usb_early_handoff __devinitdata = 0;
900static int __init usb_handoff_early(char *str)
901{
902 usb_early_handoff = 1;
903 return 0;
904}
905__setup("usb-handoff", usb_handoff_early);
906
907static void __devinit quirk_usb_handoff_uhci(struct pci_dev *pdev)
908{
909 unsigned long base = 0;
910 int wait_time, delta;
911 u16 val, sts;
912 int i;
913
914 for (i = 0; i < PCI_ROM_RESOURCE; i++)
915 if ((pci_resource_flags(pdev, i) & IORESOURCE_IO)) {
916 base = pci_resource_start(pdev, i);
917 break;
918 }
919
920 if (!base)
921 return;
922
923 /*
924 * stop controller
925 */
926 sts = inw(base + UHCI_USBSTS);
927 val = inw(base + UHCI_USBCMD);
928 val &= ~(u16)(UHCI_USBCMD_RUN | UHCI_USBCMD_CONFIGURE);
929 outw(val, base + UHCI_USBCMD);
930
931 /*
932 * wait while it stops if it was running
933 */
934 if ((sts & UHCI_USBSTS_HALTED) == 0)
935 {
936 wait_time = 1000;
937 delta = 100;
938
939 do {
940 outw(0x1f, base + UHCI_USBSTS);
941 udelay(delta);
942 wait_time -= delta;
943 val = inw(base + UHCI_USBSTS);
944 if (val & UHCI_USBSTS_HALTED)
945 break;
946 } while (wait_time > 0);
947 }
948
949 /*
950 * disable interrupts & legacy support
951 */
952 outw(0, base + UHCI_USBINTR);
953 outw(0x1f, base + UHCI_USBSTS);
954 pci_read_config_word(pdev, UHCI_USBLEGSUP, &val);
955 if (val & 0xbf)
956 pci_write_config_word(pdev, UHCI_USBLEGSUP, UHCI_USBLEGSUP_DEFAULT);
957
958}
959
960static void __devinit quirk_usb_handoff_ohci(struct pci_dev *pdev)
961{
962 void __iomem *base;
963 int wait_time;
964
965 base = ioremap_nocache(pci_resource_start(pdev, 0),
966 pci_resource_len(pdev, 0));
967 if (base == NULL) return;
968
969 if (readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) {
970 wait_time = 500; /* 0.5 seconds */
971 writel(OHCI_INTR_OC, base + OHCI_INTRENABLE);
972 writel(OHCI_OCR, base + OHCI_CMDSTATUS);
973 while (wait_time > 0 &&
974 readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) {
975 wait_time -= 10;
976 msleep(10);
977 }
978 }
979
980 /*
981 * disable interrupts
982 */
983 writel(~(u32)0, base + OHCI_INTRDISABLE);
984 writel(~(u32)0, base + OHCI_INTRSTATUS);
985
986 iounmap(base);
987}
988
989static void __devinit quirk_usb_disable_ehci(struct pci_dev *pdev)
990{
991 int wait_time, delta;
992 void __iomem *base, *op_reg_base;
993 u32 hcc_params, val, temp;
994 u8 cap_length;
995
996 base = ioremap_nocache(pci_resource_start(pdev, 0),
997 pci_resource_len(pdev, 0));
998 if (base == NULL) return;
999
1000 cap_length = readb(base);
1001 op_reg_base = base + cap_length;
1002 hcc_params = readl(base + EHCI_HCC_PARAMS);
1003 hcc_params = (hcc_params >> 8) & 0xff;
1004 if (hcc_params) {
1005 pci_read_config_dword(pdev,
1006 hcc_params + EHCI_USBLEGSUP,
1007 &val);
1008 if (((val & 0xff) == 1) && (val & EHCI_USBLEGSUP_BIOS)) {
1009 /*
1010 * Ok, BIOS is in smm mode, try to hand off...
1011 */
1012 pci_read_config_dword(pdev,
1013 hcc_params + EHCI_USBLEGCTLSTS,
1014 &temp);
1015 pci_write_config_dword(pdev,
1016 hcc_params + EHCI_USBLEGCTLSTS,
1017 temp | EHCI_USBLEGCTLSTS_SOOE);
1018 val |= EHCI_USBLEGSUP_OS;
1019 pci_write_config_dword(pdev,
1020 hcc_params + EHCI_USBLEGSUP,
1021 val);
1022
1023 wait_time = 500;
1024 do {
1025 msleep(10);
1026 wait_time -= 10;
1027 pci_read_config_dword(pdev,
1028 hcc_params + EHCI_USBLEGSUP,
1029 &val);
1030 } while (wait_time && (val & EHCI_USBLEGSUP_BIOS));
1031 if (!wait_time) {
1032 /*
1033 * well, possibly buggy BIOS...
1034 */
1035 printk(KERN_WARNING "EHCI early BIOS handoff "
1036 "failed (BIOS bug ?)\n");
1037 pci_write_config_dword(pdev,
1038 hcc_params + EHCI_USBLEGSUP,
1039 EHCI_USBLEGSUP_OS);
1040 pci_write_config_dword(pdev,
1041 hcc_params + EHCI_USBLEGCTLSTS,
1042 0);
1043 }
1044 }
1045 }
1046
1047 /*
1048 * halt EHCI & disable its interrupts in any case
1049 */
1050 val = readl(op_reg_base + EHCI_USBSTS);
1051 if ((val & EHCI_USBSTS_HALTED) == 0) {
1052 val = readl(op_reg_base + EHCI_USBCMD);
1053 val &= ~EHCI_USBCMD_RUN;
1054 writel(val, op_reg_base + EHCI_USBCMD);
1055
1056 wait_time = 2000;
1057 delta = 100;
1058 do {
1059 writel(0x3f, op_reg_base + EHCI_USBSTS);
1060 udelay(delta);
1061 wait_time -= delta;
1062 val = readl(op_reg_base + EHCI_USBSTS);
1063 if ((val == ~(u32)0) || (val & EHCI_USBSTS_HALTED)) {
1064 break;
1065 }
1066 } while (wait_time > 0);
1067 }
1068 writel(0, op_reg_base + EHCI_USBINTR);
1069 writel(0x3f, op_reg_base + EHCI_USBSTS);
1070
1071 iounmap(base);
1072
1073 return;
1074}
1075
1076
1077
1078static void __devinit quirk_usb_early_handoff(struct pci_dev *pdev)
1079{
1080 if (!usb_early_handoff)
1081 return;
1082
1083 if (pdev->class == ((PCI_CLASS_SERIAL_USB << 8) | 0x00)) { /* UHCI */
1084 quirk_usb_handoff_uhci(pdev);
1085 } else if (pdev->class == ((PCI_CLASS_SERIAL_USB << 8) | 0x10)) { /* OHCI */
1086 quirk_usb_handoff_ohci(pdev);
1087 } else if (pdev->class == ((PCI_CLASS_SERIAL_USB << 8) | 0x20)) { /* EHCI */
1088 quirk_usb_disable_ehci(pdev);
1089 }
1090
1091 return;
1092}
1093DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_usb_early_handoff);
1094
1095/*
1096 * ... This is further complicated by the fact that some SiS96x south
1097 * bridges pretend to be 85C503/5513 instead. In that case see if we
1098 * spotted a compatible north bridge to make sure.
1099 * (pci_find_device doesn't work yet)
1100 *
1101 * We can also enable the sis96x bit in the discovery register..
1102 */
1103static int __devinitdata sis_96x_compatible = 0;
1104
1105#define SIS_DETECT_REGISTER 0x40
1106
1107static void __init quirk_sis_503(struct pci_dev *dev)
1108{
1109 u8 reg;
1110 u16 devid;
1111
1112 pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1113 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1114 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1115 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1116 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1117 return;
1118 }
1119
1120 /* Make people aware that we changed the config.. */
1121 printk(KERN_WARNING "Uncovering SIS%x that hid as a SIS503 (compatible=%d)\n", devid, sis_96x_compatible);
1122
1123 /*
1124 * Ok, it now shows up as a 96x.. The 96x quirks are after
1125 * the 503 quirk in the quirk table, so they'll automatically
1126 * run and enable things like the SMBus device
1127 */
1128 dev->device = devid;
1129}
1130
1131static void __init quirk_sis_96x_compatible(struct pci_dev *dev)
1132{
1133 sis_96x_compatible = 1;
1134}
1135DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_645, quirk_sis_96x_compatible );
1136DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_646, quirk_sis_96x_compatible );
1137DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_648, quirk_sis_96x_compatible );
1138DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_650, quirk_sis_96x_compatible );
1139DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_651, quirk_sis_96x_compatible );
1140DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_735, quirk_sis_96x_compatible );
1141
1142DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503 );
1143
1144DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus );
1145DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus );
1146DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus );
1147DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus );
1148
1149#ifdef CONFIG_X86_IO_APIC
1150static void __init quirk_alder_ioapic(struct pci_dev *pdev)
1151{
1152 int i;
1153
1154 if ((pdev->class >> 8) != 0xff00)
1155 return;
1156
1157 /* the first BAR is the location of the IO APIC...we must
1158 * not touch this (and it's already covered by the fixmap), so
1159 * forcibly insert it into the resource tree */
1160 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1161 insert_resource(&iomem_resource, &pdev->resource[0]);
1162
1163 /* The next five BARs all seem to be rubbish, so just clean
1164 * them out */
1165 for (i=1; i < 6; i++) {
1166 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1167 }
1168
1169}
1170DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic );
1171#endif
1172
1173#ifdef CONFIG_SCSI_SATA
1174static void __devinit quirk_intel_ide_combined(struct pci_dev *pdev)
1175{
1176 u8 prog, comb, tmp;
1177 int ich = 0;
1178
1179 /*
1180 * Narrow down to Intel SATA PCI devices.
1181 */
1182 switch (pdev->device) {
1183 /* PCI ids taken from drivers/scsi/ata_piix.c */
1184 case 0x24d1:
1185 case 0x24df:
1186 case 0x25a3:
1187 case 0x25b0:
1188 ich = 5;
1189 break;
1190 case 0x2651:
1191 case 0x2652:
1192 case 0x2653:
c368ca4e 1193 case 0x2680: /* ESB2 */
1da177e4
LT		 1194 ich = 6;
1195 break;
1196 case 0x27c0:
1197 case 0x27c4:
1198 ich = 7;
1199 break;
1200 default:
1201 /* we do not handle this PCI device */
1202 return;
1203 }
1204
1205 /*
1206 * Read combined mode register.
1207 */
1208 pci_read_config_byte(pdev, 0x90, &tmp); /* combined mode reg */
1209
1210 if (ich == 5) {
1211 tmp &= 0x6; /* interesting bits 2:1, PATA primary/secondary */
1212 if (tmp == 0x4) /* bits 10x */
1213 comb = (1 << 0); /* SATA port 0, PATA port 1 */
1214 else if (tmp == 0x6) /* bits 11x */
1215 comb = (1 << 2); /* PATA port 0, SATA port 1 */
1216 else
1217 return; /* not in combined mode */
1218 } else {
1219 WARN_ON((ich != 6) && (ich != 7));
1220 tmp &= 0x3; /* interesting bits 1:0 */
1221 if (tmp & (1 << 0))
1222 comb = (1 << 2); /* PATA port 0, SATA port 1 */
1223 else if (tmp & (1 << 1))
1224 comb = (1 << 0); /* SATA port 0, PATA port 1 */
1225 else
1226 return; /* not in combined mode */
1227 }
1228
1229 /*
1230 * Read programming interface register.
1231 * (Tells us if it's legacy or native mode)
1232 */
1233 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1234
1235 /* if SATA port is in native mode, we're ok. */
1236 if (prog & comb)
1237 return;
1238
1239 /* SATA port is in legacy mode. Reserve port so that
1240 * IDE driver does not attempt to use it. If request_region
1241 * fails, it will be obvious at boot time, so we don't bother
1242 * checking return values.
1243 */
1244 if (comb == (1 << 0))
1245 request_region(0x1f0, 8, "libata"); /* port 0 */
1246 else
1247 request_region(0x170, 8, "libata"); /* port 1 */
1248}
1249DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_intel_ide_combined );
1250#endif /* CONFIG_SCSI_SATA */
1251
1252
1253int pcie_mch_quirk;
1254
1255static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
1256{
1257 pcie_mch_quirk = 1;
1258}
1259DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch );
1260DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch );
1261DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch );
1262
1263static void __devinit quirk_netmos(struct pci_dev *dev)
1264{
1265 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1266 unsigned int num_serial = dev->subsystem_device & 0xf;
1267
1268 /*
1269 * These Netmos parts are multiport serial devices with optional
1270 * parallel ports. Even when parallel ports are present, they
1271 * are identified as class SERIAL, which means the serial driver
1272 * will claim them. To prevent this, mark them as class OTHER.
1273 * These combo devices should be claimed by parport_serial.
1274 *
1275 * The subdevice ID is of the form 0x00PS, where <P> is the number
1276 * of parallel ports and <S> is the number of serial ports.
1277 */
1278 switch (dev->device) {
1279 case PCI_DEVICE_ID_NETMOS_9735:
1280 case PCI_DEVICE_ID_NETMOS_9745:
1281 case PCI_DEVICE_ID_NETMOS_9835:
1282 case PCI_DEVICE_ID_NETMOS_9845:
1283 case PCI_DEVICE_ID_NETMOS_9855:
1284 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL &&
1285 num_parallel) {
1286 printk(KERN_INFO "PCI: Netmos %04x (%u parallel, "
1287 "%u serial); changing class SERIAL to OTHER "
1288 "(use parport_serial)\n",
1289 dev->device, num_parallel, num_serial);
1290 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1291 (dev->class & 0xff);
1292 }
1293 }
1294}
1295DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos);
1296
1297static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, struct pci_fixup *end)
1298{
1299 while (f < end) {
1300 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
1301 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
1302 pr_debug("PCI: Calling quirk %p for %s\n", f->hook, pci_name(dev));
1303 f->hook(dev);
1304 }
1305 f++;
1306 }
1307}
1308
1309extern struct pci_fixup __start_pci_fixups_early[];
1310extern struct pci_fixup __end_pci_fixups_early[];
1311extern struct pci_fixup __start_pci_fixups_header[];
1312extern struct pci_fixup __end_pci_fixups_header[];
1313extern struct pci_fixup __start_pci_fixups_final[];
1314extern struct pci_fixup __end_pci_fixups_final[];
1315extern struct pci_fixup __start_pci_fixups_enable[];
1316extern struct pci_fixup __end_pci_fixups_enable[];
1317
1318
1319void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
1320{
1321 struct pci_fixup *start, *end;
1322
1323 switch(pass) {
1324 case pci_fixup_early:
1325 start = __start_pci_fixups_early;
1326 end = __end_pci_fixups_early;
1327 break;
1328
1329 case pci_fixup_header:
1330 start = __start_pci_fixups_header;
1331 end = __end_pci_fixups_header;
1332 break;
1333
1334 case pci_fixup_final:
1335 start = __start_pci_fixups_final;
1336 end = __end_pci_fixups_final;
1337 break;
1338
1339 case pci_fixup_enable:
1340 start = __start_pci_fixups_enable;
1341 end = __end_pci_fixups_enable;
1342 break;
1343
1344 default:
1345 /* stupid compiler warning, you would think with an enum... */
1346 return;
1347 }
1348 pci_do_fixups(dev, start, end);
1349}
1350
1351EXPORT_SYMBOL(pcie_mch_quirk);
1352#ifdef CONFIG_HOTPLUG
1353EXPORT_SYMBOL(pci_fixup_device);
1354#endif
Linux kernel - Deliverables
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