Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * drivers/pci/setup-bus.c | |
3 | * | |
4 | * Extruded from code written by | |
5 | * Dave Rusling (david.rusling@reo.mts.dec.com) | |
6 | * David Mosberger (davidm@cs.arizona.edu) | |
7 | * David Miller (davem@redhat.com) | |
8 | * | |
9 | * Support routines for initializing a PCI subsystem. | |
10 | */ | |
11 | ||
12 | /* | |
13 | * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru> | |
14 | * PCI-PCI bridges cleanup, sorted resource allocation. | |
15 | * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru> | |
16 | * Converted to allocation in 3 passes, which gives | |
17 | * tighter packing. Prefetchable range support. | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/pci.h> | |
24 | #include <linux/errno.h> | |
25 | #include <linux/ioport.h> | |
26 | #include <linux/cache.h> | |
27 | #include <linux/slab.h> | |
6faf17f6 | 28 | #include "pci.h" |
1da177e4 | 29 | |
568ddef8 YL |
30 | struct resource_list_x { |
31 | struct resource_list_x *next; | |
32 | struct resource *res; | |
33 | struct pci_dev *dev; | |
34 | resource_size_t start; | |
35 | resource_size_t end; | |
c8adf9a3 | 36 | resource_size_t add_size; |
2bbc6942 | 37 | resource_size_t min_align; |
568ddef8 YL |
38 | unsigned long flags; |
39 | }; | |
40 | ||
094732a5 RP |
41 | #define free_list(type, head) do { \ |
42 | struct type *list, *tmp; \ | |
43 | for (list = (head)->next; list;) { \ | |
44 | tmp = list; \ | |
45 | list = list->next; \ | |
46 | kfree(tmp); \ | |
47 | } \ | |
48 | (head)->next = NULL; \ | |
49 | } while (0) | |
50 | ||
f483d392 RP |
51 | int pci_realloc_enable = 0; |
52 | #define pci_realloc_enabled() pci_realloc_enable | |
53 | void pci_realloc(void) | |
54 | { | |
55 | pci_realloc_enable = 1; | |
56 | } | |
57 | ||
c8adf9a3 RP |
58 | /** |
59 | * add_to_list() - add a new resource tracker to the list | |
60 | * @head: Head of the list | |
61 | * @dev: device corresponding to which the resource | |
62 | * belongs | |
63 | * @res: The resource to be tracked | |
64 | * @add_size: additional size to be optionally added | |
65 | * to the resource | |
66 | */ | |
67 | static void add_to_list(struct resource_list_x *head, | |
68 | struct pci_dev *dev, struct resource *res, | |
2bbc6942 | 69 | resource_size_t add_size, resource_size_t min_align) |
568ddef8 YL |
70 | { |
71 | struct resource_list_x *list = head; | |
72 | struct resource_list_x *ln = list->next; | |
73 | struct resource_list_x *tmp; | |
74 | ||
75 | tmp = kmalloc(sizeof(*tmp), GFP_KERNEL); | |
76 | if (!tmp) { | |
c8adf9a3 | 77 | pr_warning("add_to_list: kmalloc() failed!\n"); |
568ddef8 YL |
78 | return; |
79 | } | |
80 | ||
81 | tmp->next = ln; | |
82 | tmp->res = res; | |
83 | tmp->dev = dev; | |
84 | tmp->start = res->start; | |
85 | tmp->end = res->end; | |
86 | tmp->flags = res->flags; | |
c8adf9a3 | 87 | tmp->add_size = add_size; |
2bbc6942 | 88 | tmp->min_align = min_align; |
568ddef8 YL |
89 | list->next = tmp; |
90 | } | |
91 | ||
c8adf9a3 RP |
92 | static void add_to_failed_list(struct resource_list_x *head, |
93 | struct pci_dev *dev, struct resource *res) | |
94 | { | |
2bbc6942 RP |
95 | add_to_list(head, dev, res, |
96 | 0 /* dont care */, | |
97 | 0 /* dont care */); | |
c8adf9a3 RP |
98 | } |
99 | ||
6841ec68 YL |
100 | static void __dev_sort_resources(struct pci_dev *dev, |
101 | struct resource_list *head) | |
1da177e4 | 102 | { |
6841ec68 | 103 | u16 class = dev->class >> 8; |
1da177e4 | 104 | |
6841ec68 YL |
105 | /* Don't touch classless devices or host bridges or ioapics. */ |
106 | if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST) | |
107 | return; | |
1da177e4 | 108 | |
6841ec68 YL |
109 | /* Don't touch ioapic devices already enabled by firmware */ |
110 | if (class == PCI_CLASS_SYSTEM_PIC) { | |
111 | u16 command; | |
112 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
113 | if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | |
114 | return; | |
115 | } | |
1da177e4 | 116 | |
6841ec68 YL |
117 | pdev_sort_resources(dev, head); |
118 | } | |
23186279 | 119 | |
fc075e1d RP |
120 | static inline void reset_resource(struct resource *res) |
121 | { | |
122 | res->start = 0; | |
123 | res->end = 0; | |
124 | res->flags = 0; | |
125 | } | |
126 | ||
c8adf9a3 RP |
127 | /** |
128 | * adjust_resources_sorted() - satisfy any additional resource requests | |
129 | * | |
130 | * @add_head : head of the list tracking requests requiring additional | |
131 | * resources | |
132 | * @head : head of the list tracking requests with allocated | |
133 | * resources | |
134 | * | |
135 | * Walk through each element of the add_head and try to procure | |
136 | * additional resources for the element, provided the element | |
137 | * is in the head list. | |
138 | */ | |
139 | static void adjust_resources_sorted(struct resource_list_x *add_head, | |
140 | struct resource_list *head) | |
6841ec68 YL |
141 | { |
142 | struct resource *res; | |
c8adf9a3 RP |
143 | struct resource_list_x *list, *tmp, *prev; |
144 | struct resource_list *hlist; | |
145 | resource_size_t add_size; | |
6841ec68 | 146 | int idx; |
1da177e4 | 147 | |
c8adf9a3 RP |
148 | prev = add_head; |
149 | for (list = add_head->next; list;) { | |
1da177e4 | 150 | res = list->res; |
c8adf9a3 RP |
151 | /* skip resource that has been reset */ |
152 | if (!res->flags) | |
153 | goto out; | |
154 | ||
155 | /* skip this resource if not found in head list */ | |
156 | for (hlist = head->next; hlist && hlist->res != res; | |
157 | hlist = hlist->next); | |
158 | if (!hlist) { /* just skip */ | |
159 | prev = list; | |
160 | list = list->next; | |
161 | continue; | |
162 | } | |
163 | ||
1da177e4 | 164 | idx = res - &list->dev->resource[0]; |
c8adf9a3 | 165 | add_size=list->add_size; |
2bbc6942 RP |
166 | if (!resource_size(res)) { |
167 | res->end = res->start + add_size - 1; | |
168 | if(pci_assign_resource(list->dev, idx)) | |
c8adf9a3 | 169 | reset_resource(res); |
2bbc6942 RP |
170 | } else { |
171 | resource_size_t align = list->min_align; | |
172 | res->flags |= list->flags & (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN); | |
173 | if (pci_reassign_resource(list->dev, idx, add_size, align)) | |
174 | dev_printk(KERN_DEBUG, &list->dev->dev, "failed to add optional resources res=%pR\n", | |
175 | res); | |
c8adf9a3 RP |
176 | } |
177 | out: | |
178 | tmp = list; | |
179 | prev->next = list = list->next; | |
180 | kfree(tmp); | |
181 | } | |
182 | } | |
183 | ||
184 | /** | |
185 | * assign_requested_resources_sorted() - satisfy resource requests | |
186 | * | |
187 | * @head : head of the list tracking requests for resources | |
188 | * @failed_list : head of the list tracking requests that could | |
189 | * not be allocated | |
190 | * | |
191 | * Satisfy resource requests of each element in the list. Add | |
192 | * requests that could not satisfied to the failed_list. | |
193 | */ | |
194 | static void assign_requested_resources_sorted(struct resource_list *head, | |
195 | struct resource_list_x *fail_head) | |
196 | { | |
197 | struct resource *res; | |
198 | struct resource_list *list; | |
199 | int idx; | |
9a928660 | 200 | |
c8adf9a3 RP |
201 | for (list = head->next; list; list = list->next) { |
202 | res = list->res; | |
203 | idx = res - &list->dev->resource[0]; | |
204 | if (resource_size(res) && pci_assign_resource(list->dev, idx)) { | |
9a928660 YL |
205 | if (fail_head && !pci_is_root_bus(list->dev->bus)) { |
206 | /* | |
207 | * if the failed res is for ROM BAR, and it will | |
208 | * be enabled later, don't add it to the list | |
209 | */ | |
210 | if (!((idx == PCI_ROM_RESOURCE) && | |
211 | (!(res->flags & IORESOURCE_ROM_ENABLE)))) | |
212 | add_to_failed_list(fail_head, list->dev, res); | |
213 | } | |
fc075e1d | 214 | reset_resource(res); |
542df5de | 215 | } |
1da177e4 LT |
216 | } |
217 | } | |
218 | ||
c8adf9a3 RP |
219 | static void __assign_resources_sorted(struct resource_list *head, |
220 | struct resource_list_x *add_head, | |
221 | struct resource_list_x *fail_head) | |
222 | { | |
223 | /* Satisfy the must-have resource requests */ | |
224 | assign_requested_resources_sorted(head, fail_head); | |
225 | ||
226 | /* Try to satisfy any additional nice-to-have resource | |
227 | requests */ | |
228 | if (add_head) | |
229 | adjust_resources_sorted(add_head, head); | |
230 | free_list(resource_list, head); | |
231 | } | |
232 | ||
6841ec68 YL |
233 | static void pdev_assign_resources_sorted(struct pci_dev *dev, |
234 | struct resource_list_x *fail_head) | |
235 | { | |
236 | struct resource_list head; | |
237 | ||
238 | head.next = NULL; | |
239 | __dev_sort_resources(dev, &head); | |
c8adf9a3 | 240 | __assign_resources_sorted(&head, NULL, fail_head); |
6841ec68 YL |
241 | |
242 | } | |
243 | ||
244 | static void pbus_assign_resources_sorted(const struct pci_bus *bus, | |
c8adf9a3 | 245 | struct resource_list_x *add_head, |
6841ec68 YL |
246 | struct resource_list_x *fail_head) |
247 | { | |
248 | struct pci_dev *dev; | |
249 | struct resource_list head; | |
250 | ||
251 | head.next = NULL; | |
252 | list_for_each_entry(dev, &bus->devices, bus_list) | |
253 | __dev_sort_resources(dev, &head); | |
254 | ||
c8adf9a3 | 255 | __assign_resources_sorted(&head, add_head, fail_head); |
6841ec68 YL |
256 | } |
257 | ||
b3743fa4 | 258 | void pci_setup_cardbus(struct pci_bus *bus) |
1da177e4 LT |
259 | { |
260 | struct pci_dev *bridge = bus->self; | |
c7dabef8 | 261 | struct resource *res; |
1da177e4 LT |
262 | struct pci_bus_region region; |
263 | ||
865df576 BH |
264 | dev_info(&bridge->dev, "CardBus bridge to [bus %02x-%02x]\n", |
265 | bus->secondary, bus->subordinate); | |
1da177e4 | 266 | |
c7dabef8 BH |
267 | res = bus->resource[0]; |
268 | pcibios_resource_to_bus(bridge, ®ion, res); | |
269 | if (res->flags & IORESOURCE_IO) { | |
1da177e4 LT |
270 | /* |
271 | * The IO resource is allocated a range twice as large as it | |
272 | * would normally need. This allows us to set both IO regs. | |
273 | */ | |
c7dabef8 | 274 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
1da177e4 LT |
275 | pci_write_config_dword(bridge, PCI_CB_IO_BASE_0, |
276 | region.start); | |
277 | pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0, | |
278 | region.end); | |
279 | } | |
280 | ||
c7dabef8 BH |
281 | res = bus->resource[1]; |
282 | pcibios_resource_to_bus(bridge, ®ion, res); | |
283 | if (res->flags & IORESOURCE_IO) { | |
284 | dev_info(&bridge->dev, " bridge window %pR\n", res); | |
1da177e4 LT |
285 | pci_write_config_dword(bridge, PCI_CB_IO_BASE_1, |
286 | region.start); | |
287 | pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1, | |
288 | region.end); | |
289 | } | |
290 | ||
c7dabef8 BH |
291 | res = bus->resource[2]; |
292 | pcibios_resource_to_bus(bridge, ®ion, res); | |
293 | if (res->flags & IORESOURCE_MEM) { | |
294 | dev_info(&bridge->dev, " bridge window %pR\n", res); | |
1da177e4 LT |
295 | pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0, |
296 | region.start); | |
297 | pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0, | |
298 | region.end); | |
299 | } | |
300 | ||
c7dabef8 BH |
301 | res = bus->resource[3]; |
302 | pcibios_resource_to_bus(bridge, ®ion, res); | |
303 | if (res->flags & IORESOURCE_MEM) { | |
304 | dev_info(&bridge->dev, " bridge window %pR\n", res); | |
1da177e4 LT |
305 | pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1, |
306 | region.start); | |
307 | pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1, | |
308 | region.end); | |
309 | } | |
310 | } | |
b3743fa4 | 311 | EXPORT_SYMBOL(pci_setup_cardbus); |
1da177e4 LT |
312 | |
313 | /* Initialize bridges with base/limit values we have collected. | |
314 | PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998) | |
315 | requires that if there is no I/O ports or memory behind the | |
316 | bridge, corresponding range must be turned off by writing base | |
317 | value greater than limit to the bridge's base/limit registers. | |
318 | ||
319 | Note: care must be taken when updating I/O base/limit registers | |
320 | of bridges which support 32-bit I/O. This update requires two | |
321 | config space writes, so it's quite possible that an I/O window of | |
322 | the bridge will have some undesirable address (e.g. 0) after the | |
323 | first write. Ditto 64-bit prefetchable MMIO. */ | |
7cc5997d | 324 | static void pci_setup_bridge_io(struct pci_bus *bus) |
1da177e4 LT |
325 | { |
326 | struct pci_dev *bridge = bus->self; | |
c7dabef8 | 327 | struct resource *res; |
1da177e4 | 328 | struct pci_bus_region region; |
7cc5997d | 329 | u32 l, io_upper16; |
1da177e4 LT |
330 | |
331 | /* Set up the top and bottom of the PCI I/O segment for this bus. */ | |
c7dabef8 BH |
332 | res = bus->resource[0]; |
333 | pcibios_resource_to_bus(bridge, ®ion, res); | |
334 | if (res->flags & IORESOURCE_IO) { | |
1da177e4 LT |
335 | pci_read_config_dword(bridge, PCI_IO_BASE, &l); |
336 | l &= 0xffff0000; | |
337 | l |= (region.start >> 8) & 0x00f0; | |
338 | l |= region.end & 0xf000; | |
339 | /* Set up upper 16 bits of I/O base/limit. */ | |
340 | io_upper16 = (region.end & 0xffff0000) | (region.start >> 16); | |
c7dabef8 | 341 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
7cc5997d | 342 | } else { |
1da177e4 LT |
343 | /* Clear upper 16 bits of I/O base/limit. */ |
344 | io_upper16 = 0; | |
345 | l = 0x00f0; | |
1da177e4 LT |
346 | } |
347 | /* Temporarily disable the I/O range before updating PCI_IO_BASE. */ | |
348 | pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff); | |
349 | /* Update lower 16 bits of I/O base/limit. */ | |
350 | pci_write_config_dword(bridge, PCI_IO_BASE, l); | |
351 | /* Update upper 16 bits of I/O base/limit. */ | |
352 | pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16); | |
7cc5997d YL |
353 | } |
354 | ||
355 | static void pci_setup_bridge_mmio(struct pci_bus *bus) | |
356 | { | |
357 | struct pci_dev *bridge = bus->self; | |
358 | struct resource *res; | |
359 | struct pci_bus_region region; | |
360 | u32 l; | |
1da177e4 | 361 | |
7cc5997d | 362 | /* Set up the top and bottom of the PCI Memory segment for this bus. */ |
c7dabef8 BH |
363 | res = bus->resource[1]; |
364 | pcibios_resource_to_bus(bridge, ®ion, res); | |
365 | if (res->flags & IORESOURCE_MEM) { | |
1da177e4 LT |
366 | l = (region.start >> 16) & 0xfff0; |
367 | l |= region.end & 0xfff00000; | |
c7dabef8 | 368 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
7cc5997d | 369 | } else { |
1da177e4 | 370 | l = 0x0000fff0; |
1da177e4 LT |
371 | } |
372 | pci_write_config_dword(bridge, PCI_MEMORY_BASE, l); | |
7cc5997d YL |
373 | } |
374 | ||
375 | static void pci_setup_bridge_mmio_pref(struct pci_bus *bus) | |
376 | { | |
377 | struct pci_dev *bridge = bus->self; | |
378 | struct resource *res; | |
379 | struct pci_bus_region region; | |
380 | u32 l, bu, lu; | |
1da177e4 LT |
381 | |
382 | /* Clear out the upper 32 bits of PREF limit. | |
383 | If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily | |
384 | disables PREF range, which is ok. */ | |
385 | pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0); | |
386 | ||
387 | /* Set up PREF base/limit. */ | |
c40a22e0 | 388 | bu = lu = 0; |
c7dabef8 BH |
389 | res = bus->resource[2]; |
390 | pcibios_resource_to_bus(bridge, ®ion, res); | |
391 | if (res->flags & IORESOURCE_PREFETCH) { | |
1da177e4 LT |
392 | l = (region.start >> 16) & 0xfff0; |
393 | l |= region.end & 0xfff00000; | |
c7dabef8 | 394 | if (res->flags & IORESOURCE_MEM_64) { |
1f82de10 YL |
395 | bu = upper_32_bits(region.start); |
396 | lu = upper_32_bits(region.end); | |
1f82de10 | 397 | } |
c7dabef8 | 398 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
7cc5997d | 399 | } else { |
1da177e4 | 400 | l = 0x0000fff0; |
1da177e4 LT |
401 | } |
402 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l); | |
403 | ||
59353ea3 AW |
404 | /* Set the upper 32 bits of PREF base & limit. */ |
405 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu); | |
406 | pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu); | |
7cc5997d YL |
407 | } |
408 | ||
409 | static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type) | |
410 | { | |
411 | struct pci_dev *bridge = bus->self; | |
412 | ||
7cc5997d YL |
413 | dev_info(&bridge->dev, "PCI bridge to [bus %02x-%02x]\n", |
414 | bus->secondary, bus->subordinate); | |
415 | ||
416 | if (type & IORESOURCE_IO) | |
417 | pci_setup_bridge_io(bus); | |
418 | ||
419 | if (type & IORESOURCE_MEM) | |
420 | pci_setup_bridge_mmio(bus); | |
421 | ||
422 | if (type & IORESOURCE_PREFETCH) | |
423 | pci_setup_bridge_mmio_pref(bus); | |
1da177e4 LT |
424 | |
425 | pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl); | |
426 | } | |
427 | ||
7cc5997d YL |
428 | static void pci_setup_bridge(struct pci_bus *bus) |
429 | { | |
430 | unsigned long type = IORESOURCE_IO | IORESOURCE_MEM | | |
431 | IORESOURCE_PREFETCH; | |
432 | ||
433 | __pci_setup_bridge(bus, type); | |
434 | } | |
435 | ||
1da177e4 LT |
436 | /* Check whether the bridge supports optional I/O and |
437 | prefetchable memory ranges. If not, the respective | |
438 | base/limit registers must be read-only and read as 0. */ | |
96bde06a | 439 | static void pci_bridge_check_ranges(struct pci_bus *bus) |
1da177e4 LT |
440 | { |
441 | u16 io; | |
442 | u32 pmem; | |
443 | struct pci_dev *bridge = bus->self; | |
444 | struct resource *b_res; | |
445 | ||
446 | b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; | |
447 | b_res[1].flags |= IORESOURCE_MEM; | |
448 | ||
449 | pci_read_config_word(bridge, PCI_IO_BASE, &io); | |
450 | if (!io) { | |
451 | pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0); | |
452 | pci_read_config_word(bridge, PCI_IO_BASE, &io); | |
453 | pci_write_config_word(bridge, PCI_IO_BASE, 0x0); | |
454 | } | |
455 | if (io) | |
456 | b_res[0].flags |= IORESOURCE_IO; | |
457 | /* DECchip 21050 pass 2 errata: the bridge may miss an address | |
458 | disconnect boundary by one PCI data phase. | |
459 | Workaround: do not use prefetching on this device. */ | |
460 | if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001) | |
461 | return; | |
462 | pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); | |
463 | if (!pmem) { | |
464 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, | |
465 | 0xfff0fff0); | |
466 | pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); | |
467 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0); | |
468 | } | |
1f82de10 | 469 | if (pmem) { |
1da177e4 | 470 | b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; |
99586105 YL |
471 | if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == |
472 | PCI_PREF_RANGE_TYPE_64) { | |
1f82de10 | 473 | b_res[2].flags |= IORESOURCE_MEM_64; |
99586105 YL |
474 | b_res[2].flags |= PCI_PREF_RANGE_TYPE_64; |
475 | } | |
1f82de10 YL |
476 | } |
477 | ||
478 | /* double check if bridge does support 64 bit pref */ | |
479 | if (b_res[2].flags & IORESOURCE_MEM_64) { | |
480 | u32 mem_base_hi, tmp; | |
481 | pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, | |
482 | &mem_base_hi); | |
483 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, | |
484 | 0xffffffff); | |
485 | pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp); | |
486 | if (!tmp) | |
487 | b_res[2].flags &= ~IORESOURCE_MEM_64; | |
488 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, | |
489 | mem_base_hi); | |
490 | } | |
1da177e4 LT |
491 | } |
492 | ||
493 | /* Helper function for sizing routines: find first available | |
494 | bus resource of a given type. Note: we intentionally skip | |
495 | the bus resources which have already been assigned (that is, | |
496 | have non-NULL parent resource). */ | |
96bde06a | 497 | static struct resource *find_free_bus_resource(struct pci_bus *bus, unsigned long type) |
1da177e4 LT |
498 | { |
499 | int i; | |
500 | struct resource *r; | |
501 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | | |
502 | IORESOURCE_PREFETCH; | |
503 | ||
89a74ecc | 504 | pci_bus_for_each_resource(bus, r, i) { |
299de034 IK |
505 | if (r == &ioport_resource || r == &iomem_resource) |
506 | continue; | |
55a10984 JB |
507 | if (r && (r->flags & type_mask) == type && !r->parent) |
508 | return r; | |
1da177e4 LT |
509 | } |
510 | return NULL; | |
511 | } | |
512 | ||
13583b16 RP |
513 | static resource_size_t calculate_iosize(resource_size_t size, |
514 | resource_size_t min_size, | |
515 | resource_size_t size1, | |
516 | resource_size_t old_size, | |
517 | resource_size_t align) | |
518 | { | |
519 | if (size < min_size) | |
520 | size = min_size; | |
521 | if (old_size == 1 ) | |
522 | old_size = 0; | |
523 | /* To be fixed in 2.5: we should have sort of HAVE_ISA | |
524 | flag in the struct pci_bus. */ | |
525 | #if defined(CONFIG_ISA) || defined(CONFIG_EISA) | |
526 | size = (size & 0xff) + ((size & ~0xffUL) << 2); | |
527 | #endif | |
528 | size = ALIGN(size + size1, align); | |
529 | if (size < old_size) | |
530 | size = old_size; | |
531 | return size; | |
532 | } | |
533 | ||
534 | static resource_size_t calculate_memsize(resource_size_t size, | |
535 | resource_size_t min_size, | |
536 | resource_size_t size1, | |
537 | resource_size_t old_size, | |
538 | resource_size_t align) | |
539 | { | |
540 | if (size < min_size) | |
541 | size = min_size; | |
542 | if (old_size == 1 ) | |
543 | old_size = 0; | |
544 | if (size < old_size) | |
545 | size = old_size; | |
546 | size = ALIGN(size + size1, align); | |
547 | return size; | |
548 | } | |
549 | ||
be768912 YL |
550 | static resource_size_t get_res_add_size(struct resource_list_x *add_head, |
551 | struct resource *res) | |
552 | { | |
553 | struct resource_list_x *list; | |
554 | ||
555 | /* check if it is in add_head list */ | |
556 | for (list = add_head->next; list && list->res != res; | |
557 | list = list->next); | |
558 | if (list) | |
559 | return list->add_size; | |
560 | ||
561 | return 0; | |
562 | } | |
563 | ||
c8adf9a3 RP |
564 | /** |
565 | * pbus_size_io() - size the io window of a given bus | |
566 | * | |
567 | * @bus : the bus | |
568 | * @min_size : the minimum io window that must to be allocated | |
569 | * @add_size : additional optional io window | |
570 | * @add_head : track the additional io window on this list | |
571 | * | |
572 | * Sizing the IO windows of the PCI-PCI bridge is trivial, | |
573 | * since these windows have 4K granularity and the IO ranges | |
574 | * of non-bridge PCI devices are limited to 256 bytes. | |
575 | * We must be careful with the ISA aliasing though. | |
576 | */ | |
577 | static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size, | |
578 | resource_size_t add_size, struct resource_list_x *add_head) | |
1da177e4 LT |
579 | { |
580 | struct pci_dev *dev; | |
581 | struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO); | |
c8adf9a3 | 582 | unsigned long size = 0, size0 = 0, size1 = 0; |
be768912 | 583 | resource_size_t children_add_size = 0; |
1da177e4 LT |
584 | |
585 | if (!b_res) | |
586 | return; | |
587 | ||
588 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
589 | int i; | |
590 | ||
591 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
592 | struct resource *r = &dev->resource[i]; | |
593 | unsigned long r_size; | |
594 | ||
595 | if (r->parent || !(r->flags & IORESOURCE_IO)) | |
596 | continue; | |
022edd86 | 597 | r_size = resource_size(r); |
1da177e4 LT |
598 | |
599 | if (r_size < 0x400) | |
600 | /* Might be re-aligned for ISA */ | |
601 | size += r_size; | |
602 | else | |
603 | size1 += r_size; | |
be768912 YL |
604 | |
605 | if (add_head) | |
606 | children_add_size += get_res_add_size(add_head, r); | |
1da177e4 LT |
607 | } |
608 | } | |
c8adf9a3 RP |
609 | size0 = calculate_iosize(size, min_size, size1, |
610 | resource_size(b_res), 4096); | |
be768912 YL |
611 | if (children_add_size > add_size) |
612 | add_size = children_add_size; | |
93d2175d | 613 | size1 = (!add_head || (add_head && !add_size)) ? size0 : |
c8adf9a3 | 614 | calculate_iosize(size, min_size+add_size, size1, |
13583b16 | 615 | resource_size(b_res), 4096); |
c8adf9a3 | 616 | if (!size0 && !size1) { |
865df576 BH |
617 | if (b_res->start || b_res->end) |
618 | dev_info(&bus->self->dev, "disabling bridge window " | |
619 | "%pR to [bus %02x-%02x] (unused)\n", b_res, | |
620 | bus->secondary, bus->subordinate); | |
1da177e4 LT |
621 | b_res->flags = 0; |
622 | return; | |
623 | } | |
624 | /* Alignment of the IO window is always 4K */ | |
625 | b_res->start = 4096; | |
c8adf9a3 | 626 | b_res->end = b_res->start + size0 - 1; |
88452565 | 627 | b_res->flags |= IORESOURCE_STARTALIGN; |
c8adf9a3 | 628 | if (size1 > size0 && add_head) |
2bbc6942 | 629 | add_to_list(add_head, bus->self, b_res, size1-size0, 4096); |
1da177e4 LT |
630 | } |
631 | ||
c8adf9a3 RP |
632 | /** |
633 | * pbus_size_mem() - size the memory window of a given bus | |
634 | * | |
635 | * @bus : the bus | |
636 | * @min_size : the minimum memory window that must to be allocated | |
637 | * @add_size : additional optional memory window | |
638 | * @add_head : track the additional memory window on this list | |
639 | * | |
640 | * Calculate the size of the bus and minimal alignment which | |
641 | * guarantees that all child resources fit in this size. | |
642 | */ | |
28760489 | 643 | static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, |
c8adf9a3 RP |
644 | unsigned long type, resource_size_t min_size, |
645 | resource_size_t add_size, | |
646 | struct resource_list_x *add_head) | |
1da177e4 LT |
647 | { |
648 | struct pci_dev *dev; | |
c8adf9a3 | 649 | resource_size_t min_align, align, size, size0, size1; |
c40a22e0 | 650 | resource_size_t aligns[12]; /* Alignments from 1Mb to 2Gb */ |
1da177e4 LT |
651 | int order, max_order; |
652 | struct resource *b_res = find_free_bus_resource(bus, type); | |
1f82de10 | 653 | unsigned int mem64_mask = 0; |
be768912 | 654 | resource_size_t children_add_size = 0; |
1da177e4 LT |
655 | |
656 | if (!b_res) | |
657 | return 0; | |
658 | ||
659 | memset(aligns, 0, sizeof(aligns)); | |
660 | max_order = 0; | |
661 | size = 0; | |
662 | ||
1f82de10 YL |
663 | mem64_mask = b_res->flags & IORESOURCE_MEM_64; |
664 | b_res->flags &= ~IORESOURCE_MEM_64; | |
665 | ||
1da177e4 LT |
666 | list_for_each_entry(dev, &bus->devices, bus_list) { |
667 | int i; | |
1f82de10 | 668 | |
1da177e4 LT |
669 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { |
670 | struct resource *r = &dev->resource[i]; | |
c40a22e0 | 671 | resource_size_t r_size; |
1da177e4 LT |
672 | |
673 | if (r->parent || (r->flags & mask) != type) | |
674 | continue; | |
022edd86 | 675 | r_size = resource_size(r); |
2aceefcb YL |
676 | #ifdef CONFIG_PCI_IOV |
677 | /* put SRIOV requested res to the optional list */ | |
678 | if (add_head && i >= PCI_IOV_RESOURCES && | |
679 | i <= PCI_IOV_RESOURCE_END) { | |
680 | r->end = r->start - 1; | |
681 | add_to_list(add_head, dev, r, r_size, 1); | |
682 | children_add_size += r_size; | |
683 | continue; | |
684 | } | |
685 | #endif | |
1da177e4 | 686 | /* For bridges size != alignment */ |
6faf17f6 | 687 | align = pci_resource_alignment(dev, r); |
1da177e4 LT |
688 | order = __ffs(align) - 20; |
689 | if (order > 11) { | |
865df576 BH |
690 | dev_warn(&dev->dev, "disabling BAR %d: %pR " |
691 | "(bad alignment %#llx)\n", i, r, | |
692 | (unsigned long long) align); | |
1da177e4 LT |
693 | r->flags = 0; |
694 | continue; | |
695 | } | |
696 | size += r_size; | |
697 | if (order < 0) | |
698 | order = 0; | |
699 | /* Exclude ranges with size > align from | |
700 | calculation of the alignment. */ | |
701 | if (r_size == align) | |
702 | aligns[order] += align; | |
703 | if (order > max_order) | |
704 | max_order = order; | |
1f82de10 | 705 | mem64_mask &= r->flags & IORESOURCE_MEM_64; |
be768912 YL |
706 | |
707 | if (add_head) | |
708 | children_add_size += get_res_add_size(add_head, r); | |
1da177e4 LT |
709 | } |
710 | } | |
1da177e4 LT |
711 | align = 0; |
712 | min_align = 0; | |
713 | for (order = 0; order <= max_order; order++) { | |
8308c54d JF |
714 | resource_size_t align1 = 1; |
715 | ||
716 | align1 <<= (order + 20); | |
717 | ||
1da177e4 LT |
718 | if (!align) |
719 | min_align = align1; | |
6f6f8c2f | 720 | else if (ALIGN(align + min_align, min_align) < align1) |
1da177e4 LT |
721 | min_align = align1 >> 1; |
722 | align += aligns[order]; | |
723 | } | |
b42282e5 | 724 | size0 = calculate_memsize(size, min_size, 0, resource_size(b_res), min_align); |
be768912 YL |
725 | if (children_add_size > add_size) |
726 | add_size = children_add_size; | |
93d2175d | 727 | size1 = (!add_head || (add_head && !add_size)) ? size0 : |
c8adf9a3 | 728 | calculate_memsize(size, min_size+add_size, 0, |
b42282e5 | 729 | resource_size(b_res), min_align); |
c8adf9a3 | 730 | if (!size0 && !size1) { |
865df576 BH |
731 | if (b_res->start || b_res->end) |
732 | dev_info(&bus->self->dev, "disabling bridge window " | |
733 | "%pR to [bus %02x-%02x] (unused)\n", b_res, | |
734 | bus->secondary, bus->subordinate); | |
1da177e4 LT |
735 | b_res->flags = 0; |
736 | return 1; | |
737 | } | |
738 | b_res->start = min_align; | |
c8adf9a3 RP |
739 | b_res->end = size0 + min_align - 1; |
740 | b_res->flags |= IORESOURCE_STARTALIGN | mem64_mask; | |
741 | if (size1 > size0 && add_head) | |
2bbc6942 | 742 | add_to_list(add_head, bus->self, b_res, size1-size0, min_align); |
1da177e4 LT |
743 | return 1; |
744 | } | |
745 | ||
5468ae61 | 746 | static void pci_bus_size_cardbus(struct pci_bus *bus) |
1da177e4 LT |
747 | { |
748 | struct pci_dev *bridge = bus->self; | |
749 | struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; | |
750 | u16 ctrl; | |
751 | ||
752 | /* | |
753 | * Reserve some resources for CardBus. We reserve | |
754 | * a fixed amount of bus space for CardBus bridges. | |
755 | */ | |
934b7024 LT |
756 | b_res[0].start = 0; |
757 | b_res[0].end = pci_cardbus_io_size - 1; | |
758 | b_res[0].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN; | |
1da177e4 | 759 | |
934b7024 LT |
760 | b_res[1].start = 0; |
761 | b_res[1].end = pci_cardbus_io_size - 1; | |
762 | b_res[1].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN; | |
1da177e4 LT |
763 | |
764 | /* | |
765 | * Check whether prefetchable memory is supported | |
766 | * by this bridge. | |
767 | */ | |
768 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); | |
769 | if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) { | |
770 | ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0; | |
771 | pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); | |
772 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); | |
773 | } | |
774 | ||
775 | /* | |
776 | * If we have prefetchable memory support, allocate | |
777 | * two regions. Otherwise, allocate one region of | |
778 | * twice the size. | |
779 | */ | |
780 | if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) { | |
934b7024 LT |
781 | b_res[2].start = 0; |
782 | b_res[2].end = pci_cardbus_mem_size - 1; | |
783 | b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_SIZEALIGN; | |
1da177e4 | 784 | |
934b7024 LT |
785 | b_res[3].start = 0; |
786 | b_res[3].end = pci_cardbus_mem_size - 1; | |
787 | b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN; | |
1da177e4 | 788 | } else { |
934b7024 LT |
789 | b_res[3].start = 0; |
790 | b_res[3].end = pci_cardbus_mem_size * 2 - 1; | |
791 | b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN; | |
1da177e4 LT |
792 | } |
793 | } | |
794 | ||
c8adf9a3 RP |
795 | void __ref __pci_bus_size_bridges(struct pci_bus *bus, |
796 | struct resource_list_x *add_head) | |
1da177e4 LT |
797 | { |
798 | struct pci_dev *dev; | |
799 | unsigned long mask, prefmask; | |
c8adf9a3 | 800 | resource_size_t additional_mem_size = 0, additional_io_size = 0; |
1da177e4 LT |
801 | |
802 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
803 | struct pci_bus *b = dev->subordinate; | |
804 | if (!b) | |
805 | continue; | |
806 | ||
807 | switch (dev->class >> 8) { | |
808 | case PCI_CLASS_BRIDGE_CARDBUS: | |
809 | pci_bus_size_cardbus(b); | |
810 | break; | |
811 | ||
812 | case PCI_CLASS_BRIDGE_PCI: | |
813 | default: | |
c8adf9a3 | 814 | __pci_bus_size_bridges(b, add_head); |
1da177e4 LT |
815 | break; |
816 | } | |
817 | } | |
818 | ||
819 | /* The root bus? */ | |
820 | if (!bus->self) | |
821 | return; | |
822 | ||
823 | switch (bus->self->class >> 8) { | |
824 | case PCI_CLASS_BRIDGE_CARDBUS: | |
825 | /* don't size cardbuses yet. */ | |
826 | break; | |
827 | ||
828 | case PCI_CLASS_BRIDGE_PCI: | |
829 | pci_bridge_check_ranges(bus); | |
28760489 | 830 | if (bus->self->is_hotplug_bridge) { |
c8adf9a3 RP |
831 | additional_io_size = pci_hotplug_io_size; |
832 | additional_mem_size = pci_hotplug_mem_size; | |
28760489 | 833 | } |
c8adf9a3 RP |
834 | /* |
835 | * Follow thru | |
836 | */ | |
1da177e4 | 837 | default: |
c8adf9a3 | 838 | pbus_size_io(bus, 0, additional_io_size, add_head); |
1da177e4 LT |
839 | /* If the bridge supports prefetchable range, size it |
840 | separately. If it doesn't, or its prefetchable window | |
841 | has already been allocated by arch code, try | |
842 | non-prefetchable range for both types of PCI memory | |
843 | resources. */ | |
844 | mask = IORESOURCE_MEM; | |
845 | prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH; | |
c8adf9a3 | 846 | if (pbus_size_mem(bus, prefmask, prefmask, 0, additional_mem_size, add_head)) |
1da177e4 | 847 | mask = prefmask; /* Success, size non-prefetch only. */ |
28760489 | 848 | else |
c8adf9a3 RP |
849 | additional_mem_size += additional_mem_size; |
850 | pbus_size_mem(bus, mask, IORESOURCE_MEM, 0, additional_mem_size, add_head); | |
1da177e4 LT |
851 | break; |
852 | } | |
853 | } | |
c8adf9a3 RP |
854 | |
855 | void __ref pci_bus_size_bridges(struct pci_bus *bus) | |
856 | { | |
857 | __pci_bus_size_bridges(bus, NULL); | |
858 | } | |
1da177e4 LT |
859 | EXPORT_SYMBOL(pci_bus_size_bridges); |
860 | ||
568ddef8 | 861 | static void __ref __pci_bus_assign_resources(const struct pci_bus *bus, |
c8adf9a3 | 862 | struct resource_list_x *add_head, |
568ddef8 | 863 | struct resource_list_x *fail_head) |
1da177e4 LT |
864 | { |
865 | struct pci_bus *b; | |
866 | struct pci_dev *dev; | |
867 | ||
c8adf9a3 | 868 | pbus_assign_resources_sorted(bus, add_head, fail_head); |
1da177e4 | 869 | |
1da177e4 LT |
870 | list_for_each_entry(dev, &bus->devices, bus_list) { |
871 | b = dev->subordinate; | |
872 | if (!b) | |
873 | continue; | |
874 | ||
c8adf9a3 | 875 | __pci_bus_assign_resources(b, add_head, fail_head); |
1da177e4 LT |
876 | |
877 | switch (dev->class >> 8) { | |
878 | case PCI_CLASS_BRIDGE_PCI: | |
6841ec68 YL |
879 | if (!pci_is_enabled(dev)) |
880 | pci_setup_bridge(b); | |
1da177e4 LT |
881 | break; |
882 | ||
883 | case PCI_CLASS_BRIDGE_CARDBUS: | |
884 | pci_setup_cardbus(b); | |
885 | break; | |
886 | ||
887 | default: | |
80ccba11 BH |
888 | dev_info(&dev->dev, "not setting up bridge for bus " |
889 | "%04x:%02x\n", pci_domain_nr(b), b->number); | |
1da177e4 LT |
890 | break; |
891 | } | |
892 | } | |
893 | } | |
568ddef8 YL |
894 | |
895 | void __ref pci_bus_assign_resources(const struct pci_bus *bus) | |
896 | { | |
c8adf9a3 | 897 | __pci_bus_assign_resources(bus, NULL, NULL); |
568ddef8 | 898 | } |
1da177e4 LT |
899 | EXPORT_SYMBOL(pci_bus_assign_resources); |
900 | ||
6841ec68 YL |
901 | static void __ref __pci_bridge_assign_resources(const struct pci_dev *bridge, |
902 | struct resource_list_x *fail_head) | |
903 | { | |
904 | struct pci_bus *b; | |
905 | ||
906 | pdev_assign_resources_sorted((struct pci_dev *)bridge, fail_head); | |
907 | ||
908 | b = bridge->subordinate; | |
909 | if (!b) | |
910 | return; | |
911 | ||
c8adf9a3 | 912 | __pci_bus_assign_resources(b, NULL, fail_head); |
6841ec68 YL |
913 | |
914 | switch (bridge->class >> 8) { | |
915 | case PCI_CLASS_BRIDGE_PCI: | |
916 | pci_setup_bridge(b); | |
917 | break; | |
918 | ||
919 | case PCI_CLASS_BRIDGE_CARDBUS: | |
920 | pci_setup_cardbus(b); | |
921 | break; | |
922 | ||
923 | default: | |
924 | dev_info(&bridge->dev, "not setting up bridge for bus " | |
925 | "%04x:%02x\n", pci_domain_nr(b), b->number); | |
926 | break; | |
927 | } | |
928 | } | |
5009b460 YL |
929 | static void pci_bridge_release_resources(struct pci_bus *bus, |
930 | unsigned long type) | |
931 | { | |
932 | int idx; | |
933 | bool changed = false; | |
934 | struct pci_dev *dev; | |
935 | struct resource *r; | |
936 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | | |
937 | IORESOURCE_PREFETCH; | |
938 | ||
939 | dev = bus->self; | |
940 | for (idx = PCI_BRIDGE_RESOURCES; idx <= PCI_BRIDGE_RESOURCE_END; | |
941 | idx++) { | |
942 | r = &dev->resource[idx]; | |
943 | if ((r->flags & type_mask) != type) | |
944 | continue; | |
945 | if (!r->parent) | |
946 | continue; | |
947 | /* | |
948 | * if there are children under that, we should release them | |
949 | * all | |
950 | */ | |
951 | release_child_resources(r); | |
952 | if (!release_resource(r)) { | |
953 | dev_printk(KERN_DEBUG, &dev->dev, | |
954 | "resource %d %pR released\n", idx, r); | |
955 | /* keep the old size */ | |
956 | r->end = resource_size(r) - 1; | |
957 | r->start = 0; | |
958 | r->flags = 0; | |
959 | changed = true; | |
960 | } | |
961 | } | |
962 | ||
963 | if (changed) { | |
964 | /* avoiding touch the one without PREF */ | |
965 | if (type & IORESOURCE_PREFETCH) | |
966 | type = IORESOURCE_PREFETCH; | |
967 | __pci_setup_bridge(bus, type); | |
968 | } | |
969 | } | |
970 | ||
971 | enum release_type { | |
972 | leaf_only, | |
973 | whole_subtree, | |
974 | }; | |
975 | /* | |
976 | * try to release pci bridge resources that is from leaf bridge, | |
977 | * so we can allocate big new one later | |
978 | */ | |
979 | static void __ref pci_bus_release_bridge_resources(struct pci_bus *bus, | |
980 | unsigned long type, | |
981 | enum release_type rel_type) | |
982 | { | |
983 | struct pci_dev *dev; | |
984 | bool is_leaf_bridge = true; | |
985 | ||
986 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
987 | struct pci_bus *b = dev->subordinate; | |
988 | if (!b) | |
989 | continue; | |
990 | ||
991 | is_leaf_bridge = false; | |
992 | ||
993 | if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) | |
994 | continue; | |
995 | ||
996 | if (rel_type == whole_subtree) | |
997 | pci_bus_release_bridge_resources(b, type, | |
998 | whole_subtree); | |
999 | } | |
1000 | ||
1001 | if (pci_is_root_bus(bus)) | |
1002 | return; | |
1003 | ||
1004 | if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI) | |
1005 | return; | |
1006 | ||
1007 | if ((rel_type == whole_subtree) || is_leaf_bridge) | |
1008 | pci_bridge_release_resources(bus, type); | |
1009 | } | |
1010 | ||
76fbc263 YL |
1011 | static void pci_bus_dump_res(struct pci_bus *bus) |
1012 | { | |
89a74ecc BH |
1013 | struct resource *res; |
1014 | int i; | |
7c9342b8 | 1015 | |
89a74ecc | 1016 | pci_bus_for_each_resource(bus, res, i) { |
7c9342b8 | 1017 | if (!res || !res->end || !res->flags) |
76fbc263 YL |
1018 | continue; |
1019 | ||
c7dabef8 | 1020 | dev_printk(KERN_DEBUG, &bus->dev, "resource %d %pR\n", i, res); |
76fbc263 YL |
1021 | } |
1022 | } | |
1023 | ||
1024 | static void pci_bus_dump_resources(struct pci_bus *bus) | |
1025 | { | |
1026 | struct pci_bus *b; | |
1027 | struct pci_dev *dev; | |
1028 | ||
1029 | ||
1030 | pci_bus_dump_res(bus); | |
1031 | ||
1032 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1033 | b = dev->subordinate; | |
1034 | if (!b) | |
1035 | continue; | |
1036 | ||
1037 | pci_bus_dump_resources(b); | |
1038 | } | |
1039 | } | |
1040 | ||
da7822e5 YL |
1041 | static int __init pci_bus_get_depth(struct pci_bus *bus) |
1042 | { | |
1043 | int depth = 0; | |
1044 | struct pci_dev *dev; | |
1045 | ||
1046 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1047 | int ret; | |
1048 | struct pci_bus *b = dev->subordinate; | |
1049 | if (!b) | |
1050 | continue; | |
1051 | ||
1052 | ret = pci_bus_get_depth(b); | |
1053 | if (ret + 1 > depth) | |
1054 | depth = ret + 1; | |
1055 | } | |
1056 | ||
1057 | return depth; | |
1058 | } | |
1059 | static int __init pci_get_max_depth(void) | |
1060 | { | |
1061 | int depth = 0; | |
1062 | struct pci_bus *bus; | |
1063 | ||
1064 | list_for_each_entry(bus, &pci_root_buses, node) { | |
1065 | int ret; | |
1066 | ||
1067 | ret = pci_bus_get_depth(bus); | |
1068 | if (ret > depth) | |
1069 | depth = ret; | |
1070 | } | |
1071 | ||
1072 | return depth; | |
1073 | } | |
1074 | ||
f483d392 | 1075 | |
da7822e5 YL |
1076 | /* |
1077 | * first try will not touch pci bridge res | |
1078 | * second and later try will clear small leaf bridge res | |
1079 | * will stop till to the max deepth if can not find good one | |
1080 | */ | |
1da177e4 LT |
1081 | void __init |
1082 | pci_assign_unassigned_resources(void) | |
1083 | { | |
1084 | struct pci_bus *bus; | |
c8adf9a3 RP |
1085 | struct resource_list_x add_list; /* list of resources that |
1086 | want additional resources */ | |
da7822e5 YL |
1087 | int tried_times = 0; |
1088 | enum release_type rel_type = leaf_only; | |
1089 | struct resource_list_x head, *list; | |
1090 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | | |
1091 | IORESOURCE_PREFETCH; | |
1092 | unsigned long failed_type; | |
1093 | int max_depth = pci_get_max_depth(); | |
1094 | int pci_try_num; | |
1095 | ||
1096 | ||
1097 | head.next = NULL; | |
c8adf9a3 | 1098 | add_list.next = NULL; |
da7822e5 YL |
1099 | |
1100 | pci_try_num = max_depth + 1; | |
1101 | printk(KERN_DEBUG "PCI: max bus depth: %d pci_try_num: %d\n", | |
1102 | max_depth, pci_try_num); | |
1103 | ||
1104 | again: | |
1da177e4 LT |
1105 | /* Depth first, calculate sizes and alignments of all |
1106 | subordinate buses. */ | |
da7822e5 | 1107 | list_for_each_entry(bus, &pci_root_buses, node) |
c8adf9a3 | 1108 | __pci_bus_size_bridges(bus, &add_list); |
c8adf9a3 | 1109 | |
1da177e4 | 1110 | /* Depth last, allocate resources and update the hardware. */ |
da7822e5 YL |
1111 | list_for_each_entry(bus, &pci_root_buses, node) |
1112 | __pci_bus_assign_resources(bus, &add_list, &head); | |
c8adf9a3 | 1113 | BUG_ON(add_list.next); |
da7822e5 YL |
1114 | tried_times++; |
1115 | ||
1116 | /* any device complain? */ | |
1117 | if (!head.next) | |
1118 | goto enable_and_dump; | |
f483d392 RP |
1119 | |
1120 | /* don't realloc if asked to do so */ | |
1121 | if (!pci_realloc_enabled()) { | |
1122 | free_list(resource_list_x, &head); | |
1123 | goto enable_and_dump; | |
1124 | } | |
1125 | ||
da7822e5 YL |
1126 | failed_type = 0; |
1127 | for (list = head.next; list;) { | |
1128 | failed_type |= list->flags; | |
1129 | list = list->next; | |
1130 | } | |
1131 | /* | |
1132 | * io port are tight, don't try extra | |
1133 | * or if reach the limit, don't want to try more | |
1134 | */ | |
1135 | failed_type &= type_mask; | |
1136 | if ((failed_type == IORESOURCE_IO) || (tried_times >= pci_try_num)) { | |
1137 | free_list(resource_list_x, &head); | |
1138 | goto enable_and_dump; | |
1139 | } | |
1140 | ||
1141 | printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n", | |
1142 | tried_times + 1); | |
1143 | ||
1144 | /* third times and later will not check if it is leaf */ | |
1145 | if ((tried_times + 1) > 2) | |
1146 | rel_type = whole_subtree; | |
1147 | ||
1148 | /* | |
1149 | * Try to release leaf bridge's resources that doesn't fit resource of | |
1150 | * child device under that bridge | |
1151 | */ | |
1152 | for (list = head.next; list;) { | |
1153 | bus = list->dev->bus; | |
1154 | pci_bus_release_bridge_resources(bus, list->flags & type_mask, | |
1155 | rel_type); | |
1156 | list = list->next; | |
1157 | } | |
1158 | /* restore size and flags */ | |
1159 | for (list = head.next; list;) { | |
1160 | struct resource *res = list->res; | |
1161 | ||
1162 | res->start = list->start; | |
1163 | res->end = list->end; | |
1164 | res->flags = list->flags; | |
1165 | if (list->dev->subordinate) | |
1166 | res->flags = 0; | |
1167 | ||
1168 | list = list->next; | |
1169 | } | |
1170 | free_list(resource_list_x, &head); | |
1171 | ||
1172 | goto again; | |
1173 | ||
1174 | enable_and_dump: | |
1175 | /* Depth last, update the hardware. */ | |
1176 | list_for_each_entry(bus, &pci_root_buses, node) | |
1177 | pci_enable_bridges(bus); | |
76fbc263 YL |
1178 | |
1179 | /* dump the resource on buses */ | |
da7822e5 | 1180 | list_for_each_entry(bus, &pci_root_buses, node) |
76fbc263 | 1181 | pci_bus_dump_resources(bus); |
1da177e4 | 1182 | } |
6841ec68 YL |
1183 | |
1184 | void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge) | |
1185 | { | |
1186 | struct pci_bus *parent = bridge->subordinate; | |
32180e40 YL |
1187 | int tried_times = 0; |
1188 | struct resource_list_x head, *list; | |
6841ec68 | 1189 | int retval; |
32180e40 YL |
1190 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | |
1191 | IORESOURCE_PREFETCH; | |
1192 | ||
1193 | head.next = NULL; | |
6841ec68 | 1194 | |
32180e40 | 1195 | again: |
6841ec68 | 1196 | pci_bus_size_bridges(parent); |
32180e40 | 1197 | __pci_bridge_assign_resources(bridge, &head); |
32180e40 YL |
1198 | |
1199 | tried_times++; | |
1200 | ||
1201 | if (!head.next) | |
3f579c34 | 1202 | goto enable_all; |
32180e40 YL |
1203 | |
1204 | if (tried_times >= 2) { | |
1205 | /* still fail, don't need to try more */ | |
094732a5 | 1206 | free_list(resource_list_x, &head); |
3f579c34 | 1207 | goto enable_all; |
32180e40 YL |
1208 | } |
1209 | ||
1210 | printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n", | |
1211 | tried_times + 1); | |
1212 | ||
1213 | /* | |
1214 | * Try to release leaf bridge's resources that doesn't fit resource of | |
1215 | * child device under that bridge | |
1216 | */ | |
1217 | for (list = head.next; list;) { | |
1218 | struct pci_bus *bus = list->dev->bus; | |
1219 | unsigned long flags = list->flags; | |
1220 | ||
1221 | pci_bus_release_bridge_resources(bus, flags & type_mask, | |
1222 | whole_subtree); | |
1223 | list = list->next; | |
1224 | } | |
1225 | /* restore size and flags */ | |
1226 | for (list = head.next; list;) { | |
1227 | struct resource *res = list->res; | |
1228 | ||
1229 | res->start = list->start; | |
1230 | res->end = list->end; | |
1231 | res->flags = list->flags; | |
1232 | if (list->dev->subordinate) | |
1233 | res->flags = 0; | |
1234 | ||
1235 | list = list->next; | |
1236 | } | |
094732a5 | 1237 | free_list(resource_list_x, &head); |
32180e40 YL |
1238 | |
1239 | goto again; | |
3f579c34 YL |
1240 | |
1241 | enable_all: | |
1242 | retval = pci_reenable_device(bridge); | |
1243 | pci_set_master(bridge); | |
1244 | pci_enable_bridges(parent); | |
6841ec68 YL |
1245 | } |
1246 | EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources); |