[deliverable/linux.git] / drivers / pci / setup-bus.c

/*
 *	drivers/pci/setup-bus.c
 *
 * Extruded from code written by
 *      Dave Rusling (david.rusling@reo.mts.dec.com)
 *      David Mosberger (davidm@cs.arizona.edu)
 *	David Miller (davem@redhat.com)
 *
 * Support routines for initializing a PCI subsystem.
 */

/*
 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
 *	     PCI-PCI bridges cleanup, sorted resource allocation.
 * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
 *	     Converted to allocation in 3 passes, which gives
 *	     tighter packing. Prefetchable range support.
 */

#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/errno.h>
#include <linux/ioport.h>
#include <linux/cache.h>
#include <linux/slab.h>
#include "pci.h"

static void pbus_assign_resources_sorted(const struct pci_bus *bus)
{
	struct pci_dev *dev;
	struct resource *res;
	struct resource_list head, *list, *tmp;
	int idx;

	head.next = NULL;
	list_for_each_entry(dev, &bus->devices, bus_list) {
		u16 class = dev->class >> 8;

		/* Don't touch classless devices or host bridges or ioapics.  */
		if (class == PCI_CLASS_NOT_DEFINED ||
		    class == PCI_CLASS_BRIDGE_HOST)
			continue;

		/* Don't touch ioapic devices already enabled by firmware */
		if (class == PCI_CLASS_SYSTEM_PIC) {
			u16 command;
			pci_read_config_word(dev, PCI_COMMAND, &command);
			if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY))
				continue;
		}

		pdev_sort_resources(dev, &head);
	}

	for (list = head.next; list;) {
		res = list->res;
		idx = res - &list->dev->resource[0];
		if (pci_assign_resource(list->dev, idx)) {
			res->start = 0;
			res->end = 0;
			res->flags = 0;
		}
		tmp = list;
		list = list->next;
		kfree(tmp);
	}
}

void pci_setup_cardbus(struct pci_bus *bus)
{
	struct pci_dev *bridge = bus->self;
	struct pci_bus_region region;

	dev_info(&bridge->dev, "CardBus bridge, secondary bus %04x:%02x\n",
		 pci_domain_nr(bus), bus->number);

	pcibios_resource_to_bus(bridge, &region, bus->resource[0]);
	if (bus->resource[0]->flags & IORESOURCE_IO) {
		/*
		 * The IO resource is allocated a range twice as large as it
		 * would normally need.  This allows us to set both IO regs.
		 */
		dev_info(&bridge->dev, "  IO window: %#08lx-%#08lx\n",
		       (unsigned long)region.start,
		       (unsigned long)region.end);
		pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
					region.start);
		pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
					region.end);
	}

	pcibios_resource_to_bus(bridge, &region, bus->resource[1]);
	if (bus->resource[1]->flags & IORESOURCE_IO) {
		dev_info(&bridge->dev, "  IO window: %#08lx-%#08lx\n",
		       (unsigned long)region.start,
		       (unsigned long)region.end);
		pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
					region.start);
		pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
					region.end);
	}

	pcibios_resource_to_bus(bridge, &region, bus->resource[2]);
	if (bus->resource[2]->flags & IORESOURCE_MEM) {
		dev_info(&bridge->dev, "  PREFETCH window: %#08lx-%#08lx\n",
		       (unsigned long)region.start,
		       (unsigned long)region.end);
		pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
					region.start);
		pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
					region.end);
	}

	pcibios_resource_to_bus(bridge, &region, bus->resource[3]);
	if (bus->resource[3]->flags & IORESOURCE_MEM) {
		dev_info(&bridge->dev, "  MEM window: %#08lx-%#08lx\n",
		       (unsigned long)region.start,
		       (unsigned long)region.end);
		pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
					region.start);
		pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
					region.end);
	}
}
EXPORT_SYMBOL(pci_setup_cardbus);

/* Initialize bridges with base/limit values we have collected.
   PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998)
   requires that if there is no I/O ports or memory behind the
   bridge, corresponding range must be turned off by writing base
   value greater than limit to the bridge's base/limit registers.

   Note: care must be taken when updating I/O base/limit registers
   of bridges which support 32-bit I/O. This update requires two
   config space writes, so it's quite possible that an I/O window of
   the bridge will have some undesirable address (e.g. 0) after the
   first write. Ditto 64-bit prefetchable MMIO.  */
static void pci_setup_bridge(struct pci_bus *bus)
{
	struct pci_dev *bridge = bus->self;
	struct pci_bus_region region;
	u32 l, bu, lu, io_upper16;
	int pref_mem64;

	if (pci_is_enabled(bridge))
		return;

	dev_info(&bridge->dev, "PCI bridge, secondary bus %04x:%02x\n",
		 pci_domain_nr(bus), bus->number);

	/* Set up the top and bottom of the PCI I/O segment for this bus. */
	pcibios_resource_to_bus(bridge, &region, bus->resource[0]);
	if (bus->resource[0]->flags & IORESOURCE_IO) {
		pci_read_config_dword(bridge, PCI_IO_BASE, &l);
		l &= 0xffff0000;
		l |= (region.start >> 8) & 0x00f0;
		l |= region.end & 0xf000;
		/* Set up upper 16 bits of I/O base/limit. */
		io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
		dev_info(&bridge->dev, "  IO window: %#04lx-%#04lx\n",
		    (unsigned long)region.start,
		    (unsigned long)region.end);
	}
	else {
		/* Clear upper 16 bits of I/O base/limit. */
		io_upper16 = 0;
		l = 0x00f0;
		dev_info(&bridge->dev, "  IO window: disabled\n");
	}
	/* Temporarily disable the I/O range before updating PCI_IO_BASE. */
	pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
	/* Update lower 16 bits of I/O base/limit. */
	pci_write_config_dword(bridge, PCI_IO_BASE, l);
	/* Update upper 16 bits of I/O base/limit. */
	pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);

	/* Set up the top and bottom of the PCI Memory segment
	   for this bus. */
	pcibios_resource_to_bus(bridge, &region, bus->resource[1]);
	if (bus->resource[1]->flags & IORESOURCE_MEM) {
		l = (region.start >> 16) & 0xfff0;
		l |= region.end & 0xfff00000;
		dev_info(&bridge->dev, "  MEM window: %#08lx-%#08lx\n",
		    (unsigned long)region.start,
		    (unsigned long)region.end);
	}
	else {
		l = 0x0000fff0;
		dev_info(&bridge->dev, "  MEM window: disabled\n");
	}
	pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);

	/* Clear out the upper 32 bits of PREF limit.
	   If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily
	   disables PREF range, which is ok. */
	pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);

	/* Set up PREF base/limit. */
	pref_mem64 = 0;
	bu = lu = 0;
	pcibios_resource_to_bus(bridge, &region, bus->resource[2]);
	if (bus->resource[2]->flags & IORESOURCE_PREFETCH) {
		int width = 8;
		l = (region.start >> 16) & 0xfff0;
		l |= region.end & 0xfff00000;
		if (bus->resource[2]->flags & IORESOURCE_MEM_64) {
			pref_mem64 = 1;
			bu = upper_32_bits(region.start);
			lu = upper_32_bits(region.end);
			width = 16;
		}
		dev_info(&bridge->dev, "  PREFETCH window: %#0*llx-%#0*llx\n",
				width, (unsigned long long)region.start,
				width, (unsigned long long)region.end);
	}
	else {
		l = 0x0000fff0;
		dev_info(&bridge->dev, "  PREFETCH window: disabled\n");
	}
	pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);

	if (pref_mem64) {
		/* Set the upper 32 bits of PREF base & limit. */
		pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);
		pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);
	}

	pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
}

/* Check whether the bridge supports optional I/O and
   prefetchable memory ranges. If not, the respective
   base/limit registers must be read-only and read as 0. */
static void pci_bridge_check_ranges(struct pci_bus *bus)
{
	u16 io;
	u32 pmem;
	struct pci_dev *bridge = bus->self;
	struct resource *b_res;

	b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
	b_res[1].flags |= IORESOURCE_MEM;

	pci_read_config_word(bridge, PCI_IO_BASE, &io);
	if (!io) {
		pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0);
		pci_read_config_word(bridge, PCI_IO_BASE, &io);
 		pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
 	}
 	if (io)
		b_res[0].flags |= IORESOURCE_IO;
	/*  DECchip 21050 pass 2 errata: the bridge may miss an address
	    disconnect boundary by one PCI data phase.
	    Workaround: do not use prefetching on this device. */
	if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
		return;
	pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
	if (!pmem) {
		pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
					       0xfff0fff0);
		pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
		pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
	}
	if (pmem) {
		b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
		if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64)
			b_res[2].flags |= IORESOURCE_MEM_64;
	}

	/* double check if bridge does support 64 bit pref */
	if (b_res[2].flags & IORESOURCE_MEM_64) {
		u32 mem_base_hi, tmp;
		pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32,
					 &mem_base_hi);
		pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
					       0xffffffff);
		pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);
		if (!tmp)
			b_res[2].flags &= ~IORESOURCE_MEM_64;
		pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
				       mem_base_hi);
	}
}

/* Helper function for sizing routines: find first available
   bus resource of a given type. Note: we intentionally skip
   the bus resources which have already been assigned (that is,
   have non-NULL parent resource). */
static struct resource *find_free_bus_resource(struct pci_bus *bus, unsigned long type)
{
	int i;
	struct resource *r;
	unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
				  IORESOURCE_PREFETCH;

	for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
		r = bus->resource[i];
		if (r == &ioport_resource || r == &iomem_resource)
			continue;
		if (r && (r->flags & type_mask) == type && !r->parent)
			return r;
	}
	return NULL;
}

/* Sizing the IO windows of the PCI-PCI bridge is trivial,
   since these windows have 4K granularity and the IO ranges
   of non-bridge PCI devices are limited to 256 bytes.
   We must be careful with the ISA aliasing though. */
static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size)
{
	struct pci_dev *dev;
	struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO);
	unsigned long size = 0, size1 = 0;

	if (!b_res)
 		return;

	list_for_each_entry(dev, &bus->devices, bus_list) {
		int i;

		for (i = 0; i < PCI_NUM_RESOURCES; i++) {
			struct resource *r = &dev->resource[i];
			unsigned long r_size;

			if (r->parent || !(r->flags & IORESOURCE_IO))
				continue;
			r_size = resource_size(r);

			if (r_size < 0x400)
				/* Might be re-aligned for ISA */
				size += r_size;
			else
				size1 += r_size;
		}
	}
	if (size < min_size)
		size = min_size;
/* To be fixed in 2.5: we should have sort of HAVE_ISA
   flag in the struct pci_bus. */
#if defined(CONFIG_ISA) || defined(CONFIG_EISA)
	size = (size & 0xff) + ((size & ~0xffUL) << 2);
#endif
	size = ALIGN(size + size1, 4096);
	if (!size) {
		b_res->flags = 0;
		return;
	}
	/* Alignment of the IO window is always 4K */
	b_res->start = 4096;
	b_res->end = b_res->start + size - 1;
	b_res->flags |= IORESOURCE_STARTALIGN;
}

/* Calculate the size of the bus and minimal alignment which
   guarantees that all child resources fit in this size. */
static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
			 unsigned long type, resource_size_t min_size)
{
	struct pci_dev *dev;
	resource_size_t min_align, align, size;
	resource_size_t aligns[12];	/* Alignments from 1Mb to 2Gb */
	int order, max_order;
	struct resource *b_res = find_free_bus_resource(bus, type);
	unsigned int mem64_mask = 0;

	if (!b_res)
		return 0;

	memset(aligns, 0, sizeof(aligns));
	max_order = 0;
	size = 0;

	mem64_mask = b_res->flags & IORESOURCE_MEM_64;
	b_res->flags &= ~IORESOURCE_MEM_64;

	list_for_each_entry(dev, &bus->devices, bus_list) {
		int i;

		for (i = 0; i < PCI_NUM_RESOURCES; i++) {
			struct resource *r = &dev->resource[i];
			resource_size_t r_size;

			if (r->parent || (r->flags & mask) != type)
				continue;
			r_size = resource_size(r);
			/* For bridges size != alignment */
			align = pci_resource_alignment(dev, r);
			order = __ffs(align) - 20;
			if (order > 11) {
				dev_warn(&dev->dev, "BAR %d: bad alignment %llx: "
					 "%pRt\n", i, (unsigned long long)align, r);
				r->flags = 0;
				continue;
			}
			size += r_size;
			if (order < 0)
				order = 0;
			/* Exclude ranges with size > align from
			   calculation of the alignment. */
			if (r_size == align)
				aligns[order] += align;
			if (order > max_order)
				max_order = order;
			mem64_mask &= r->flags & IORESOURCE_MEM_64;
		}
	}
	if (size < min_size)
		size = min_size;

	align = 0;
	min_align = 0;
	for (order = 0; order <= max_order; order++) {
		resource_size_t align1 = 1;

		align1 <<= (order + 20);

		if (!align)
			min_align = align1;
		else if (ALIGN(align + min_align, min_align) < align1)
			min_align = align1 >> 1;
		align += aligns[order];
	}
	size = ALIGN(size, min_align);
	if (!size) {
		b_res->flags = 0;
		return 1;
	}
	b_res->start = min_align;
	b_res->end = size + min_align - 1;
	b_res->flags |= IORESOURCE_STARTALIGN;
	b_res->flags |= mem64_mask;
	return 1;
}

static void pci_bus_size_cardbus(struct pci_bus *bus)
{
	struct pci_dev *bridge = bus->self;
	struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
	u16 ctrl;

	/*
	 * Reserve some resources for CardBus.  We reserve
	 * a fixed amount of bus space for CardBus bridges.
	 */
	b_res[0].start = 0;
	b_res[0].end = pci_cardbus_io_size - 1;
	b_res[0].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN;

	b_res[1].start = 0;
	b_res[1].end = pci_cardbus_io_size - 1;
	b_res[1].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN;

	/*
	 * Check whether prefetchable memory is supported
	 * by this bridge.
	 */
	pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
	if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
		ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
		pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
		pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
	}

	/*
	 * If we have prefetchable memory support, allocate
	 * two regions.  Otherwise, allocate one region of
	 * twice the size.
	 */
	if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
		b_res[2].start = 0;
		b_res[2].end = pci_cardbus_mem_size - 1;
		b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_SIZEALIGN;

		b_res[3].start = 0;
		b_res[3].end = pci_cardbus_mem_size - 1;
		b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN;
	} else {
		b_res[3].start = 0;
		b_res[3].end = pci_cardbus_mem_size * 2 - 1;
		b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN;
	}
}

void __ref pci_bus_size_bridges(struct pci_bus *bus)
{
	struct pci_dev *dev;
	unsigned long mask, prefmask;
	resource_size_t min_mem_size = 0, min_io_size = 0;

	list_for_each_entry(dev, &bus->devices, bus_list) {
		struct pci_bus *b = dev->subordinate;
		if (!b)
			continue;

		switch (dev->class >> 8) {
		case PCI_CLASS_BRIDGE_CARDBUS:
			pci_bus_size_cardbus(b);
			break;

		case PCI_CLASS_BRIDGE_PCI:
		default:
			pci_bus_size_bridges(b);
			break;
		}
	}

	/* The root bus? */
	if (!bus->self)
		return;

	switch (bus->self->class >> 8) {
	case PCI_CLASS_BRIDGE_CARDBUS:
		/* don't size cardbuses yet. */
		break;

	case PCI_CLASS_BRIDGE_PCI:
		pci_bridge_check_ranges(bus);
		if (bus->self->is_hotplug_bridge) {
			min_io_size  = pci_hotplug_io_size;
			min_mem_size = pci_hotplug_mem_size;
		}
	default:
		pbus_size_io(bus, min_io_size);
		/* If the bridge supports prefetchable range, size it
		   separately. If it doesn't, or its prefetchable window
		   has already been allocated by arch code, try
		   non-prefetchable range for both types of PCI memory
		   resources. */
		mask = IORESOURCE_MEM;
		prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH;
		if (pbus_size_mem(bus, prefmask, prefmask, min_mem_size))
			mask = prefmask; /* Success, size non-prefetch only. */
		else
			min_mem_size += min_mem_size;
		pbus_size_mem(bus, mask, IORESOURCE_MEM, min_mem_size);
		break;
	}
}
EXPORT_SYMBOL(pci_bus_size_bridges);

void __ref pci_bus_assign_resources(const struct pci_bus *bus)
{
	struct pci_bus *b;
	struct pci_dev *dev;

	pbus_assign_resources_sorted(bus);

	list_for_each_entry(dev, &bus->devices, bus_list) {
		b = dev->subordinate;
		if (!b)
			continue;

		pci_bus_assign_resources(b);

		switch (dev->class >> 8) {
		case PCI_CLASS_BRIDGE_PCI:
			pci_setup_bridge(b);
			break;

		case PCI_CLASS_BRIDGE_CARDBUS:
			pci_setup_cardbus(b);
			break;

		default:
			dev_info(&dev->dev, "not setting up bridge for bus "
				 "%04x:%02x\n", pci_domain_nr(b), b->number);
			break;
		}
	}
}
EXPORT_SYMBOL(pci_bus_assign_resources);

static void pci_bus_dump_res(struct pci_bus *bus)
{
        int i;

        for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
                struct resource *res = bus->resource[i];
                if (!res || !res->end)
                        continue;

		dev_printk(KERN_DEBUG, &bus->dev, "resource %d %pRt\n", i, res);
        }
}

static void pci_bus_dump_resources(struct pci_bus *bus)
{
	struct pci_bus *b;
	struct pci_dev *dev;


	pci_bus_dump_res(bus);

	list_for_each_entry(dev, &bus->devices, bus_list) {
		b = dev->subordinate;
		if (!b)
			continue;

		pci_bus_dump_resources(b);
	}
}

void __init
pci_assign_unassigned_resources(void)
{
	struct pci_bus *bus;

	/* Depth first, calculate sizes and alignments of all
	   subordinate buses. */
	list_for_each_entry(bus, &pci_root_buses, node) {
		pci_bus_size_bridges(bus);
	}
	/* Depth last, allocate resources and update the hardware. */
	list_for_each_entry(bus, &pci_root_buses, node) {
		pci_bus_assign_resources(bus);
		pci_enable_bridges(bus);
	}

	/* dump the resource on buses */
	list_for_each_entry(bus, &pci_root_buses, node) {
		pci_bus_dump_resources(bus);
	}
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* drivers/pci/setup-bus.c
	3	*
	4	* Extruded from code written by
	5	* Dave Rusling (david.rusling@reo.mts.dec.com)
	6	* David Mosberger (davidm@cs.arizona.edu)
	7	* David Miller (davem@redhat.com)
	8	*
	9	* Support routines for initializing a PCI subsystem.
	10	*/
	11
	12	/*
	13	* Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
	14	* PCI-PCI bridges cleanup, sorted resource allocation.
	15	* Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
	16	* Converted to allocation in 3 passes, which gives
	17	* tighter packing. Prefetchable range support.
	18	*/
	19
	20	#include <linux/init.h>
	21	#include <linux/kernel.h>
	22	#include <linux/module.h>
	23	#include <linux/pci.h>
	24	#include <linux/errno.h>
	25	#include <linux/ioport.h>
	26	#include <linux/cache.h>
	27	#include <linux/slab.h>
6faf17f6	28	#include "pci.h"
1da177e4	29
ea741551	30	static void pbus_assign_resources_sorted(const struct pci_bus *bus)
1da177e4 LT	31	{
	32	struct pci_dev *dev;
	33	struct resource *res;
	34	struct resource_list head, list, tmp;
	35	int idx;
	36
1da177e4 LT	37	head.next = NULL;
	38	list_for_each_entry(dev, &bus->devices, bus_list) {
	39	u16 class = dev->class >> 8;
	40
9bded00b	41	/* Don't touch classless devices or host bridges or ioapics. */
1da177e4	42	if (class == PCI_CLASS_NOT_DEFINED \|\|
23186279	43	class == PCI_CLASS_BRIDGE_HOST)
1da177e4 LT	44	continue;
1da177e4 LT	45
9bded00b	46	/* Don't touch ioapic devices already enabled by firmware */
23186279	47	if (class == PCI_CLASS_SYSTEM_PIC) {
9bded00b KK	48	u16 command;
	49	pci_read_config_word(dev, PCI_COMMAND, &command);
	50	if (command & (PCI_COMMAND_IO \| PCI_COMMAND_MEMORY))
23186279 ST	51	continue;
	52	}
	53
1da177e4 LT	54	pdev_sort_resources(dev, &head);
	55	}
	56
	57	for (list = head.next; list;) {
	58	res = list->res;
	59	idx = res - &list->dev->resource[0];
542df5de RS	60	if (pci_assign_resource(list->dev, idx)) {
542df5de RS	61	res->start = 0;
960b8466	62	res->end = 0;
542df5de RS	63	res->flags = 0;
542df5de RS	64	}
1da177e4 LT	65	tmp = list;
	66	list = list->next;
	67	kfree(tmp);
	68	}
	69	}
	70
b3743fa4	71	void pci_setup_cardbus(struct pci_bus *bus)
1da177e4 LT	72	{
	73	struct pci_dev *bridge = bus->self;
	74	struct pci_bus_region region;
	75
80ccba11 BH	76	dev_info(&bridge->dev, "CardBus bridge, secondary bus %04x:%02x\n",
80ccba11 BH	77	pci_domain_nr(bus), bus->number);
1da177e4 LT	78
	79	pcibios_resource_to_bus(bridge, &region, bus->resource[0]);
	80	if (bus->resource[0]->flags & IORESOURCE_IO) {
	81	/*
	82	* The IO resource is allocated a range twice as large as it
	83	* would normally need. This allows us to set both IO regs.
	84	*/
80ccba11	85	dev_info(&bridge->dev, " IO window: %#08lx-%#08lx\n",
c40a22e0 BH	86	(unsigned long)region.start,
c40a22e0 BH	87	(unsigned long)region.end);
1da177e4 LT	88	pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
	89	region.start);
	90	pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
	91	region.end);
	92	}
	93
	94	pcibios_resource_to_bus(bridge, &region, bus->resource[1]);
	95	if (bus->resource[1]->flags & IORESOURCE_IO) {
80ccba11	96	dev_info(&bridge->dev, " IO window: %#08lx-%#08lx\n",
c40a22e0 BH	97	(unsigned long)region.start,
c40a22e0 BH	98	(unsigned long)region.end);
1da177e4 LT	99	pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
	100	region.start);
	101	pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
	102	region.end);
	103	}
	104
	105	pcibios_resource_to_bus(bridge, &region, bus->resource[2]);
	106	if (bus->resource[2]->flags & IORESOURCE_MEM) {
80ccba11	107	dev_info(&bridge->dev, " PREFETCH window: %#08lx-%#08lx\n",
c40a22e0 BH	108	(unsigned long)region.start,
c40a22e0 BH	109	(unsigned long)region.end);
1da177e4 LT	110	pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
	111	region.start);
	112	pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
	113	region.end);
	114	}
	115
	116	pcibios_resource_to_bus(bridge, &region, bus->resource[3]);
	117	if (bus->resource[3]->flags & IORESOURCE_MEM) {
80ccba11	118	dev_info(&bridge->dev, " MEM window: %#08lx-%#08lx\n",
c40a22e0 BH	119	(unsigned long)region.start,
c40a22e0 BH	120	(unsigned long)region.end);
1da177e4 LT	121	pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
	122	region.start);
	123	pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
	124	region.end);
	125	}
	126	}
b3743fa4	127	EXPORT_SYMBOL(pci_setup_cardbus);
1da177e4 LT	128
	129	/* Initialize bridges with base/limit values we have collected.
	130	PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998)
	131	requires that if there is no I/O ports or memory behind the
	132	bridge, corresponding range must be turned off by writing base
	133	value greater than limit to the bridge's base/limit registers.
	134
	135	Note: care must be taken when updating I/O base/limit registers
	136	of bridges which support 32-bit I/O. This update requires two
	137	config space writes, so it's quite possible that an I/O window of
	138	the bridge will have some undesirable address (e.g. 0) after the
	139	first write. Ditto 64-bit prefetchable MMIO. */
a391f197	140	static void pci_setup_bridge(struct pci_bus *bus)
1da177e4 LT	141	{
	142	struct pci_dev *bridge = bus->self;
	143	struct pci_bus_region region;
c40a22e0	144	u32 l, bu, lu, io_upper16;
1f82de10	145	int pref_mem64;
1da177e4	146
296ccb08	147	if (pci_is_enabled(bridge))
b73e97d9 AC	148	return;
b73e97d9 AC	149
80ccba11 BH	150	dev_info(&bridge->dev, "PCI bridge, secondary bus %04x:%02x\n",
80ccba11 BH	151	pci_domain_nr(bus), bus->number);
1da177e4 LT	152
	153	/* Set up the top and bottom of the PCI I/O segment for this bus. */
	154	pcibios_resource_to_bus(bridge, &region, bus->resource[0]);
	155	if (bus->resource[0]->flags & IORESOURCE_IO) {
	156	pci_read_config_dword(bridge, PCI_IO_BASE, &l);
	157	l &= 0xffff0000;
	158	l \|= (region.start >> 8) & 0x00f0;
	159	l \|= region.end & 0xf000;
	160	/* Set up upper 16 bits of I/O base/limit. */
	161	io_upper16 = (region.end & 0xffff0000) \| (region.start >> 16);
80ccba11	162	dev_info(&bridge->dev, " IO window: %#04lx-%#04lx\n",
c40a22e0 BH	163	(unsigned long)region.start,
c40a22e0 BH	164	(unsigned long)region.end);
1da177e4 LT	165	}
	166	else {
	167	/* Clear upper 16 bits of I/O base/limit. */
	168	io_upper16 = 0;
	169	l = 0x00f0;
80ccba11	170	dev_info(&bridge->dev, " IO window: disabled\n");
1da177e4 LT	171	}
	172	/* Temporarily disable the I/O range before updating PCI_IO_BASE. */
	173	pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
	174	/* Update lower 16 bits of I/O base/limit. */
	175	pci_write_config_dword(bridge, PCI_IO_BASE, l);
	176	/* Update upper 16 bits of I/O base/limit. */
	177	pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);
	178
	179	/* Set up the top and bottom of the PCI Memory segment
	180	for this bus. */
	181	pcibios_resource_to_bus(bridge, &region, bus->resource[1]);
	182	if (bus->resource[1]->flags & IORESOURCE_MEM) {
	183	l = (region.start >> 16) & 0xfff0;
	184	l \|= region.end & 0xfff00000;
80ccba11	185	dev_info(&bridge->dev, " MEM window: %#08lx-%#08lx\n",
c40a22e0 BH	186	(unsigned long)region.start,
c40a22e0 BH	187	(unsigned long)region.end);
1da177e4 LT	188	}
	189	else {
	190	l = 0x0000fff0;
80ccba11	191	dev_info(&bridge->dev, " MEM window: disabled\n");
1da177e4 LT	192	}
	193	pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
	194
	195	/* Clear out the upper 32 bits of PREF limit.
	196	If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily
	197	disables PREF range, which is ok. */
	198	pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
	199
	200	/* Set up PREF base/limit. */
1f82de10	201	pref_mem64 = 0;
c40a22e0	202	bu = lu = 0;
1da177e4 LT	203	pcibios_resource_to_bus(bridge, &region, bus->resource[2]);
1da177e4 LT	204	if (bus->resource[2]->flags & IORESOURCE_PREFETCH) {
1f82de10	205	int width = 8;
1da177e4 LT	206	l = (region.start >> 16) & 0xfff0;
1da177e4 LT	207	l \|= region.end & 0xfff00000;
1f82de10 YL	208	if (bus->resource[2]->flags & IORESOURCE_MEM_64) {
	209	pref_mem64 = 1;
	210	bu = upper_32_bits(region.start);
	211	lu = upper_32_bits(region.end);
	212	width = 16;
	213	}
	214	dev_info(&bridge->dev, " PREFETCH window: %#0llx-%#0llx\n",
	215	width, (unsigned long long)region.start,
	216	width, (unsigned long long)region.end);
1da177e4 LT	217	}
	218	else {
	219	l = 0x0000fff0;
80ccba11	220	dev_info(&bridge->dev, " PREFETCH window: disabled\n");
1da177e4 LT	221	}
	222	pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
	223
1f82de10 YL	224	if (pref_mem64) {
	225	/* Set the upper 32 bits of PREF base & limit. */
	226	pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);
	227	pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);
	228	}
1da177e4 LT	229
	230	pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
	231	}
	232
	233	/* Check whether the bridge supports optional I/O and
	234	prefetchable memory ranges. If not, the respective
	235	base/limit registers must be read-only and read as 0. */
96bde06a	236	static void pci_bridge_check_ranges(struct pci_bus *bus)
1da177e4 LT	237	{
	238	u16 io;
	239	u32 pmem;
	240	struct pci_dev *bridge = bus->self;
	241	struct resource *b_res;
	242
	243	b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
	244	b_res[1].flags \|= IORESOURCE_MEM;
	245
	246	pci_read_config_word(bridge, PCI_IO_BASE, &io);
	247	if (!io) {
	248	pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0);
	249	pci_read_config_word(bridge, PCI_IO_BASE, &io);
	250	pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
	251	}
	252	if (io)
	253	b_res[0].flags \|= IORESOURCE_IO;
	254	/* DECchip 21050 pass 2 errata: the bridge may miss an address
	255	disconnect boundary by one PCI data phase.
	256	Workaround: do not use prefetching on this device. */
	257	if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
	258	return;
	259	pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
	260	if (!pmem) {
	261	pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
	262	0xfff0fff0);
	263	pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
	264	pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
	265	}
1f82de10	266	if (pmem) {
1da177e4	267	b_res[2].flags \|= IORESOURCE_MEM \| IORESOURCE_PREFETCH;
1f82de10 YL	268	if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64)
	269	b_res[2].flags \|= IORESOURCE_MEM_64;
	270	}
	271
	272	/* double check if bridge does support 64 bit pref */
	273	if (b_res[2].flags & IORESOURCE_MEM_64) {
	274	u32 mem_base_hi, tmp;
	275	pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32,
	276	&mem_base_hi);
	277	pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
	278	0xffffffff);
	279	pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);
	280	if (!tmp)
	281	b_res[2].flags &= ~IORESOURCE_MEM_64;
	282	pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
	283	mem_base_hi);
	284	}
1da177e4 LT	285	}
	286
	287	/* Helper function for sizing routines: find first available
	288	bus resource of a given type. Note: we intentionally skip
	289	the bus resources which have already been assigned (that is,
	290	have non-NULL parent resource). */
96bde06a	291	static struct resource find_free_bus_resource(struct pci_bus bus, unsigned long type)
1da177e4 LT	292	{
	293	int i;
	294	struct resource *r;
	295	unsigned long type_mask = IORESOURCE_IO \| IORESOURCE_MEM \|
	296	IORESOURCE_PREFETCH;
	297
	298	for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
	299	r = bus->resource[i];
299de034 IK	300	if (r == &ioport_resource \|\| r == &iomem_resource)
299de034 IK	301	continue;
55a10984 JB	302	if (r && (r->flags & type_mask) == type && !r->parent)
55a10984 JB	303	return r;
1da177e4 LT	304	}
	305	return NULL;
	306	}
	307
	308	/* Sizing the IO windows of the PCI-PCI bridge is trivial,
	309	since these windows have 4K granularity and the IO ranges
	310	of non-bridge PCI devices are limited to 256 bytes.
	311	We must be careful with the ISA aliasing though. */
28760489	312	static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size)
1da177e4 LT	313	{
	314	struct pci_dev *dev;
	315	struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO);
	316	unsigned long size = 0, size1 = 0;
	317
	318	if (!b_res)
	319	return;
	320
	321	list_for_each_entry(dev, &bus->devices, bus_list) {
	322	int i;
	323
	324	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
	325	struct resource *r = &dev->resource[i];
	326	unsigned long r_size;
	327
	328	if (r->parent \|\| !(r->flags & IORESOURCE_IO))
	329	continue;
022edd86	330	r_size = resource_size(r);
1da177e4 LT	331
	332	if (r_size < 0x400)
	333	/* Might be re-aligned for ISA */
	334	size += r_size;
	335	else
	336	size1 += r_size;
	337	}
	338	}
28760489 EB	339	if (size < min_size)
28760489 EB	340	size = min_size;
1da177e4 LT	341	/* To be fixed in 2.5: we should have sort of HAVE_ISA
	342	flag in the struct pci_bus. */
	343	#if defined(CONFIG_ISA) \|\| defined(CONFIG_EISA)
	344	size = (size & 0xff) + ((size & ~0xffUL) << 2);
	345	#endif
6f6f8c2f	346	size = ALIGN(size + size1, 4096);
1da177e4 LT	347	if (!size) {
	348	b_res->flags = 0;
	349	return;
	350	}
	351	/* Alignment of the IO window is always 4K */
	352	b_res->start = 4096;
	353	b_res->end = b_res->start + size - 1;
88452565	354	b_res->flags \|= IORESOURCE_STARTALIGN;
1da177e4 LT	355	}
	356
	357	/* Calculate the size of the bus and minimal alignment which
	358	guarantees that all child resources fit in this size. */
28760489 EB	359	static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
28760489 EB	360	unsigned long type, resource_size_t min_size)
1da177e4 LT	361	{
1da177e4 LT	362	struct pci_dev *dev;
c40a22e0 BH	363	resource_size_t min_align, align, size;
c40a22e0 BH	364	resource_size_t aligns[12]; /* Alignments from 1Mb to 2Gb */
1da177e4 LT	365	int order, max_order;
1da177e4 LT	366	struct resource *b_res = find_free_bus_resource(bus, type);
1f82de10	367	unsigned int mem64_mask = 0;
1da177e4 LT	368
	369	if (!b_res)
	370	return 0;
	371
	372	memset(aligns, 0, sizeof(aligns));
	373	max_order = 0;
	374	size = 0;
	375
1f82de10 YL	376	mem64_mask = b_res->flags & IORESOURCE_MEM_64;
	377	b_res->flags &= ~IORESOURCE_MEM_64;
	378
1da177e4 LT	379	list_for_each_entry(dev, &bus->devices, bus_list) {
1da177e4 LT	380	int i;
1f82de10	381
1da177e4 LT	382	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1da177e4 LT	383	struct resource *r = &dev->resource[i];
c40a22e0	384	resource_size_t r_size;
1da177e4 LT	385
	386	if (r->parent \|\| (r->flags & mask) != type)
	387	continue;
022edd86	388	r_size = resource_size(r);
1da177e4	389	/* For bridges size != alignment */
6faf17f6	390	align = pci_resource_alignment(dev, r);
1da177e4 LT	391	order = __ffs(align) - 20;
1da177e4 LT	392	if (order > 11) {
a369c791 BH	393	dev_warn(&dev->dev, "BAR %d: bad alignment %llx: "
a369c791 BH	394	"%pRt\n", i, (unsigned long long)align, r);
1da177e4 LT	395	r->flags = 0;
	396	continue;
	397	}
	398	size += r_size;
	399	if (order < 0)
	400	order = 0;
	401	/* Exclude ranges with size > align from
	402	calculation of the alignment. */
	403	if (r_size == align)
	404	aligns[order] += align;
	405	if (order > max_order)
	406	max_order = order;
1f82de10	407	mem64_mask &= r->flags & IORESOURCE_MEM_64;
1da177e4 LT	408	}
1da177e4 LT	409	}
28760489 EB	410	if (size < min_size)
28760489 EB	411	size = min_size;
1da177e4 LT	412
	413	align = 0;
	414	min_align = 0;
	415	for (order = 0; order <= max_order; order++) {
8308c54d JF	416	resource_size_t align1 = 1;
	417
	418	align1 <<= (order + 20);
	419
1da177e4 LT	420	if (!align)
1da177e4 LT	421	min_align = align1;
6f6f8c2f	422	else if (ALIGN(align + min_align, min_align) < align1)
1da177e4 LT	423	min_align = align1 >> 1;
	424	align += aligns[order];
	425	}
6f6f8c2f	426	size = ALIGN(size, min_align);
1da177e4 LT	427	if (!size) {
	428	b_res->flags = 0;
	429	return 1;
	430	}
	431	b_res->start = min_align;
	432	b_res->end = size + min_align - 1;
88452565	433	b_res->flags \|= IORESOURCE_STARTALIGN;
1f82de10	434	b_res->flags \|= mem64_mask;
1da177e4 LT	435	return 1;
	436	}
	437
5468ae61	438	static void pci_bus_size_cardbus(struct pci_bus *bus)
1da177e4 LT	439	{
	440	struct pci_dev *bridge = bus->self;
	441	struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
	442	u16 ctrl;
	443
	444	/*
	445	* Reserve some resources for CardBus. We reserve
	446	* a fixed amount of bus space for CardBus bridges.
	447	*/
934b7024 LT	448	b_res[0].start = 0;
	449	b_res[0].end = pci_cardbus_io_size - 1;
	450	b_res[0].flags \|= IORESOURCE_IO \| IORESOURCE_SIZEALIGN;
1da177e4	451
934b7024 LT	452	b_res[1].start = 0;
	453	b_res[1].end = pci_cardbus_io_size - 1;
	454	b_res[1].flags \|= IORESOURCE_IO \| IORESOURCE_SIZEALIGN;
1da177e4 LT	455
	456	/*
	457	* Check whether prefetchable memory is supported
	458	* by this bridge.
	459	*/
	460	pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
	461	if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
	462	ctrl \|= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
	463	pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
	464	pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
	465	}
	466
	467	/*
	468	* If we have prefetchable memory support, allocate
	469	* two regions. Otherwise, allocate one region of
	470	* twice the size.
	471	*/
	472	if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
934b7024 LT	473	b_res[2].start = 0;
	474	b_res[2].end = pci_cardbus_mem_size - 1;
	475	b_res[2].flags \|= IORESOURCE_MEM \| IORESOURCE_PREFETCH \| IORESOURCE_SIZEALIGN;
1da177e4	476
934b7024 LT	477	b_res[3].start = 0;
	478	b_res[3].end = pci_cardbus_mem_size - 1;
	479	b_res[3].flags \|= IORESOURCE_MEM \| IORESOURCE_SIZEALIGN;
1da177e4	480	} else {
934b7024 LT	481	b_res[3].start = 0;
	482	b_res[3].end = pci_cardbus_mem_size * 2 - 1;
	483	b_res[3].flags \|= IORESOURCE_MEM \| IORESOURCE_SIZEALIGN;
1da177e4 LT	484	}
	485	}
	486
451124a7	487	void __ref pci_bus_size_bridges(struct pci_bus *bus)
1da177e4 LT	488	{
	489	struct pci_dev *dev;
	490	unsigned long mask, prefmask;
28760489	491	resource_size_t min_mem_size = 0, min_io_size = 0;
1da177e4 LT	492
	493	list_for_each_entry(dev, &bus->devices, bus_list) {
	494	struct pci_bus *b = dev->subordinate;
	495	if (!b)
	496	continue;
	497
	498	switch (dev->class >> 8) {
	499	case PCI_CLASS_BRIDGE_CARDBUS:
	500	pci_bus_size_cardbus(b);
	501	break;
	502
	503	case PCI_CLASS_BRIDGE_PCI:
	504	default:
	505	pci_bus_size_bridges(b);
	506	break;
	507	}
	508	}
	509
	510	/* The root bus? */
	511	if (!bus->self)
	512	return;
	513
	514	switch (bus->self->class >> 8) {
	515	case PCI_CLASS_BRIDGE_CARDBUS:
	516	/* don't size cardbuses yet. */
	517	break;
	518
	519	case PCI_CLASS_BRIDGE_PCI:
	520	pci_bridge_check_ranges(bus);
28760489 EB	521	if (bus->self->is_hotplug_bridge) {
	522	min_io_size = pci_hotplug_io_size;
	523	min_mem_size = pci_hotplug_mem_size;
	524	}
1da177e4	525	default:
28760489	526	pbus_size_io(bus, min_io_size);
1da177e4 LT	527	/* If the bridge supports prefetchable range, size it
	528	separately. If it doesn't, or its prefetchable window
	529	has already been allocated by arch code, try
	530	non-prefetchable range for both types of PCI memory
	531	resources. */
	532	mask = IORESOURCE_MEM;
	533	prefmask = IORESOURCE_MEM \| IORESOURCE_PREFETCH;
28760489	534	if (pbus_size_mem(bus, prefmask, prefmask, min_mem_size))
1da177e4	535	mask = prefmask; /* Success, size non-prefetch only. */
28760489 EB	536	else
	537	min_mem_size += min_mem_size;
	538	pbus_size_mem(bus, mask, IORESOURCE_MEM, min_mem_size);
1da177e4 LT	539	break;
	540	}
	541	}
	542	EXPORT_SYMBOL(pci_bus_size_bridges);
	543
ea741551	544	void __ref pci_bus_assign_resources(const struct pci_bus *bus)
1da177e4 LT	545	{
	546	struct pci_bus *b;
	547	struct pci_dev *dev;
	548
	549	pbus_assign_resources_sorted(bus);
	550
1da177e4 LT	551	list_for_each_entry(dev, &bus->devices, bus_list) {
	552	b = dev->subordinate;
	553	if (!b)
	554	continue;
	555
	556	pci_bus_assign_resources(b);
	557
	558	switch (dev->class >> 8) {
	559	case PCI_CLASS_BRIDGE_PCI:
	560	pci_setup_bridge(b);
	561	break;
	562
	563	case PCI_CLASS_BRIDGE_CARDBUS:
	564	pci_setup_cardbus(b);
	565	break;
	566
	567	default:
80ccba11 BH	568	dev_info(&dev->dev, "not setting up bridge for bus "
80ccba11 BH	569	"%04x:%02x\n", pci_domain_nr(b), b->number);
1da177e4 LT	570	break;
	571	}
	572	}
	573	}
	574	EXPORT_SYMBOL(pci_bus_assign_resources);
	575
76fbc263 YL	576	static void pci_bus_dump_res(struct pci_bus *bus)
	577	{
	578	int i;
	579
	580	for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
	581	struct resource *res = bus->resource[i];
681bf597	582	if (!res \|\| !res->end)
76fbc263 YL	583	continue;
76fbc263 YL	584
a369c791	585	dev_printk(KERN_DEBUG, &bus->dev, "resource %d %pRt\n", i, res);
76fbc263 YL	586	}
	587	}
	588
	589	static void pci_bus_dump_resources(struct pci_bus *bus)
	590	{
	591	struct pci_bus *b;
	592	struct pci_dev *dev;
	593
	594
	595	pci_bus_dump_res(bus);
	596
	597	list_for_each_entry(dev, &bus->devices, bus_list) {
	598	b = dev->subordinate;
	599	if (!b)
	600	continue;
	601
	602	pci_bus_dump_resources(b);
	603	}
	604	}
	605
1da177e4 LT	606	void __init
	607	pci_assign_unassigned_resources(void)
	608	{
	609	struct pci_bus *bus;
	610
	611	/* Depth first, calculate sizes and alignments of all
	612	subordinate buses. */
	613	list_for_each_entry(bus, &pci_root_buses, node) {
	614	pci_bus_size_bridges(bus);
	615	}
	616	/* Depth last, allocate resources and update the hardware. */
	617	list_for_each_entry(bus, &pci_root_buses, node) {
	618	pci_bus_assign_resources(bus);
	619	pci_enable_bridges(bus);
	620	}
76fbc263 YL	621
	622	/* dump the resource on buses */
	623	list_for_each_entry(bus, &pci_root_buses, node) {
	624	pci_bus_dump_resources(bus);
	625	}
1da177e4	626	}