Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * drivers/pci/setup-res.c | |
3 | * | |
4 | * Extruded from code written by | |
5 | * Dave Rusling (david.rusling@reo.mts.dec.com) | |
6 | * David Mosberger (davidm@cs.arizona.edu) | |
7 | * David Miller (davem@redhat.com) | |
8 | * | |
9 | * Support routines for initializing a PCI subsystem. | |
10 | */ | |
11 | ||
12 | /* fixed for multiple pci buses, 1999 Andrea Arcangeli <andrea@suse.de> */ | |
13 | ||
14 | /* | |
15 | * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru> | |
16 | * Resource sorting | |
17 | */ | |
18 | ||
19 | #include <linux/init.h> | |
20 | #include <linux/kernel.h> | |
21 | #include <linux/pci.h> | |
22 | #include <linux/errno.h> | |
23 | #include <linux/ioport.h> | |
24 | #include <linux/cache.h> | |
25 | #include <linux/slab.h> | |
26 | #include "pci.h" | |
27 | ||
28 | ||
14add80b | 29 | void pci_update_resource(struct pci_dev *dev, int resno) |
1da177e4 LT |
30 | { |
31 | struct pci_bus_region region; | |
32 | u32 new, check, mask; | |
33 | int reg; | |
613e7ed6 | 34 | enum pci_bar_type type; |
14add80b | 35 | struct resource *res = dev->resource + resno; |
1da177e4 | 36 | |
fb0f2b40 RB |
37 | /* |
38 | * Ignore resources for unimplemented BARs and unused resource slots | |
39 | * for 64 bit BARs. | |
40 | */ | |
cf7bee5a IK |
41 | if (!res->flags) |
42 | return; | |
43 | ||
fb0f2b40 RB |
44 | /* |
45 | * Ignore non-moveable resources. This might be legacy resources for | |
46 | * which no functional BAR register exists or another important | |
80ccba11 | 47 | * system resource we shouldn't move around. |
fb0f2b40 RB |
48 | */ |
49 | if (res->flags & IORESOURCE_PCI_FIXED) | |
50 | return; | |
51 | ||
1da177e4 LT |
52 | pcibios_resource_to_bus(dev, ®ion, res); |
53 | ||
096e6f67 BH |
54 | dev_dbg(&dev->dev, "BAR %d: got res %pR bus [%#llx-%#llx] " |
55 | "flags %#lx\n", resno, res, | |
6015fbef BH |
56 | (unsigned long long)region.start, |
57 | (unsigned long long)region.end, | |
80ccba11 | 58 | (unsigned long)res->flags); |
1da177e4 LT |
59 | |
60 | new = region.start | (res->flags & PCI_REGION_FLAG_MASK); | |
61 | if (res->flags & IORESOURCE_IO) | |
62 | mask = (u32)PCI_BASE_ADDRESS_IO_MASK; | |
63 | else | |
64 | mask = (u32)PCI_BASE_ADDRESS_MEM_MASK; | |
65 | ||
613e7ed6 YZ |
66 | reg = pci_resource_bar(dev, resno, &type); |
67 | if (!reg) | |
68 | return; | |
69 | if (type != pci_bar_unknown) { | |
755528c8 LT |
70 | if (!(res->flags & IORESOURCE_ROM_ENABLE)) |
71 | return; | |
72 | new |= PCI_ROM_ADDRESS_ENABLE; | |
1da177e4 LT |
73 | } |
74 | ||
75 | pci_write_config_dword(dev, reg, new); | |
76 | pci_read_config_dword(dev, reg, &check); | |
77 | ||
78 | if ((new ^ check) & mask) { | |
80ccba11 BH |
79 | dev_err(&dev->dev, "BAR %d: error updating (%#08x != %#08x)\n", |
80 | resno, new, check); | |
1da177e4 LT |
81 | } |
82 | ||
83 | if ((new & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) == | |
84 | (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64)) { | |
cf7bee5a | 85 | new = region.start >> 16 >> 16; |
1da177e4 LT |
86 | pci_write_config_dword(dev, reg + 4, new); |
87 | pci_read_config_dword(dev, reg + 4, &check); | |
88 | if (check != new) { | |
80ccba11 BH |
89 | dev_err(&dev->dev, "BAR %d: error updating " |
90 | "(high %#08x != %#08x)\n", resno, new, check); | |
1da177e4 LT |
91 | } |
92 | } | |
93 | res->flags &= ~IORESOURCE_UNSET; | |
80ccba11 BH |
94 | dev_dbg(&dev->dev, "BAR %d: moved to bus [%#llx-%#llx] flags %#lx\n", |
95 | resno, (unsigned long long)region.start, | |
96 | (unsigned long long)region.end, res->flags); | |
1da177e4 LT |
97 | } |
98 | ||
96bde06a | 99 | int pci_claim_resource(struct pci_dev *dev, int resource) |
1da177e4 LT |
100 | { |
101 | struct resource *res = &dev->resource[resource]; | |
cebd78a8 | 102 | struct resource *root; |
1da177e4 LT |
103 | int err; |
104 | ||
cebd78a8 | 105 | root = pci_find_parent_resource(dev, res); |
1da177e4 LT |
106 | |
107 | err = -EINVAL; | |
108 | if (root != NULL) | |
79896cf4 | 109 | err = request_resource(root, res); |
1da177e4 LT |
110 | |
111 | if (err) { | |
79896cf4 | 112 | const char *dtype = resource < PCI_BRIDGE_RESOURCES ? "device" : "bridge"; |
096e6f67 | 113 | dev_err(&dev->dev, "BAR %d: %s of %s %pR\n", |
80ccba11 BH |
114 | resource, |
115 | root ? "address space collision on" : | |
116 | "no parent found for", | |
096e6f67 | 117 | dtype, res); |
1da177e4 LT |
118 | } |
119 | ||
120 | return err; | |
121 | } | |
eaa959df | 122 | EXPORT_SYMBOL(pci_claim_resource); |
1da177e4 | 123 | |
32a9a682 YS |
124 | #ifdef CONFIG_PCI_QUIRKS |
125 | void pci_disable_bridge_window(struct pci_dev *dev) | |
126 | { | |
127 | dev_dbg(&dev->dev, "Disabling bridge window.\n"); | |
128 | ||
129 | /* MMIO Base/Limit */ | |
130 | pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0); | |
131 | ||
132 | /* Prefetchable MMIO Base/Limit */ | |
133 | pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0); | |
134 | pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0); | |
135 | pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff); | |
136 | } | |
137 | #endif /* CONFIG_PCI_QUIRKS */ | |
138 | ||
d09ee968 YL |
139 | static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev, |
140 | int resno) | |
1da177e4 | 141 | { |
1da177e4 | 142 | struct resource *res = dev->resource + resno; |
e31dd6e4 | 143 | resource_size_t size, min, align; |
1da177e4 LT |
144 | int ret; |
145 | ||
022edd86 | 146 | size = resource_size(res); |
1da177e4 | 147 | min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM; |
6faf17f6 | 148 | align = pci_resource_alignment(dev, res); |
1da177e4 LT |
149 | |
150 | /* First, try exact prefetching match.. */ | |
151 | ret = pci_bus_alloc_resource(bus, res, size, align, min, | |
152 | IORESOURCE_PREFETCH, | |
153 | pcibios_align_resource, dev); | |
154 | ||
155 | if (ret < 0 && (res->flags & IORESOURCE_PREFETCH)) { | |
156 | /* | |
157 | * That failed. | |
158 | * | |
159 | * But a prefetching area can handle a non-prefetching | |
160 | * window (it will just not perform as well). | |
161 | */ | |
162 | ret = pci_bus_alloc_resource(bus, res, size, align, min, 0, | |
163 | pcibios_align_resource, dev); | |
164 | } | |
165 | ||
d09ee968 | 166 | if (!ret) { |
88452565 IK |
167 | res->flags &= ~IORESOURCE_STARTALIGN; |
168 | if (resno < PCI_BRIDGE_RESOURCES) | |
14add80b | 169 | pci_update_resource(dev, resno); |
1da177e4 LT |
170 | } |
171 | ||
172 | return ret; | |
173 | } | |
174 | ||
d09ee968 YL |
175 | int pci_assign_resource(struct pci_dev *dev, int resno) |
176 | { | |
177 | struct resource *res = dev->resource + resno; | |
178 | resource_size_t align; | |
179 | struct pci_bus *bus; | |
180 | int ret; | |
181 | ||
6faf17f6 | 182 | align = pci_resource_alignment(dev, res); |
d09ee968 YL |
183 | if (!align) { |
184 | dev_info(&dev->dev, "BAR %d: can't allocate resource (bogus " | |
185 | "alignment) %pR flags %#lx\n", | |
186 | resno, res, res->flags); | |
187 | return -EINVAL; | |
188 | } | |
189 | ||
190 | bus = dev->bus; | |
191 | while ((ret = __pci_assign_resource(bus, dev, resno))) { | |
192 | if (bus->parent && bus->self->transparent) | |
193 | bus = bus->parent; | |
194 | else | |
195 | bus = NULL; | |
196 | if (bus) | |
197 | continue; | |
198 | break; | |
199 | } | |
200 | ||
201 | if (ret) | |
202 | dev_info(&dev->dev, "BAR %d: can't allocate %s resource %pR\n", | |
203 | resno, res->flags & IORESOURCE_IO ? "I/O" : "mem", res); | |
204 | ||
205 | return ret; | |
206 | } | |
207 | ||
2baad5f9 | 208 | #if 0 |
75acfeca KG |
209 | int pci_assign_resource_fixed(struct pci_dev *dev, int resno) |
210 | { | |
211 | struct pci_bus *bus = dev->bus; | |
212 | struct resource *res = dev->resource + resno; | |
213 | unsigned int type_mask; | |
214 | int i, ret = -EBUSY; | |
215 | ||
216 | type_mask = IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH; | |
217 | ||
218 | for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) { | |
219 | struct resource *r = bus->resource[i]; | |
220 | if (!r) | |
221 | continue; | |
222 | ||
223 | /* type_mask must match */ | |
224 | if ((res->flags ^ r->flags) & type_mask) | |
225 | continue; | |
226 | ||
227 | ret = request_resource(r, res); | |
228 | ||
229 | if (ret == 0) | |
230 | break; | |
231 | } | |
232 | ||
233 | if (ret) { | |
096e6f67 BH |
234 | dev_err(&dev->dev, "BAR %d: can't allocate %s resource %pR\n", |
235 | resno, res->flags & IORESOURCE_IO ? "I/O" : "mem", res); | |
75acfeca | 236 | } else if (resno < PCI_BRIDGE_RESOURCES) { |
14add80b | 237 | pci_update_resource(dev, resno); |
75acfeca KG |
238 | } |
239 | ||
240 | return ret; | |
241 | } | |
242 | EXPORT_SYMBOL_GPL(pci_assign_resource_fixed); | |
243 | #endif | |
244 | ||
1da177e4 | 245 | /* Sort resources by alignment */ |
96bde06a | 246 | void pdev_sort_resources(struct pci_dev *dev, struct resource_list *head) |
1da177e4 LT |
247 | { |
248 | int i; | |
249 | ||
250 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
251 | struct resource *r; | |
252 | struct resource_list *list, *tmp; | |
e31dd6e4 | 253 | resource_size_t r_align; |
1da177e4 LT |
254 | |
255 | r = &dev->resource[i]; | |
fb0f2b40 RB |
256 | |
257 | if (r->flags & IORESOURCE_PCI_FIXED) | |
258 | continue; | |
259 | ||
1da177e4 LT |
260 | if (!(r->flags) || r->parent) |
261 | continue; | |
88452565 | 262 | |
6faf17f6 | 263 | r_align = pci_resource_alignment(dev, r); |
1da177e4 | 264 | if (!r_align) { |
80ccba11 | 265 | dev_warn(&dev->dev, "BAR %d: bogus alignment " |
096e6f67 BH |
266 | "%pR flags %#lx\n", |
267 | i, r, r->flags); | |
1da177e4 LT |
268 | continue; |
269 | } | |
1da177e4 | 270 | for (list = head; ; list = list->next) { |
e31dd6e4 | 271 | resource_size_t align = 0; |
1da177e4 | 272 | struct resource_list *ln = list->next; |
88452565 IK |
273 | |
274 | if (ln) | |
6faf17f6 | 275 | align = pci_resource_alignment(ln->dev, ln->res); |
88452565 | 276 | |
1da177e4 LT |
277 | if (r_align > align) { |
278 | tmp = kmalloc(sizeof(*tmp), GFP_KERNEL); | |
279 | if (!tmp) | |
280 | panic("pdev_sort_resources(): " | |
281 | "kmalloc() failed!\n"); | |
282 | tmp->next = ln; | |
283 | tmp->res = r; | |
284 | tmp->dev = dev; | |
285 | list->next = tmp; | |
286 | break; | |
287 | } | |
288 | } | |
289 | } | |
290 | } | |
842de40d BH |
291 | |
292 | int pci_enable_resources(struct pci_dev *dev, int mask) | |
293 | { | |
294 | u16 cmd, old_cmd; | |
295 | int i; | |
296 | struct resource *r; | |
297 | ||
298 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
299 | old_cmd = cmd; | |
300 | ||
301 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
302 | if (!(mask & (1 << i))) | |
303 | continue; | |
304 | ||
305 | r = &dev->resource[i]; | |
306 | ||
307 | if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM))) | |
308 | continue; | |
309 | if ((i == PCI_ROM_RESOURCE) && | |
310 | (!(r->flags & IORESOURCE_ROM_ENABLE))) | |
311 | continue; | |
312 | ||
313 | if (!r->parent) { | |
314 | dev_err(&dev->dev, "device not available because of " | |
096e6f67 | 315 | "BAR %d %pR collisions\n", i, r); |
842de40d BH |
316 | return -EINVAL; |
317 | } | |
318 | ||
319 | if (r->flags & IORESOURCE_IO) | |
320 | cmd |= PCI_COMMAND_IO; | |
321 | if (r->flags & IORESOURCE_MEM) | |
322 | cmd |= PCI_COMMAND_MEMORY; | |
323 | } | |
324 | ||
325 | if (cmd != old_cmd) { | |
326 | dev_info(&dev->dev, "enabling device (%04x -> %04x)\n", | |
327 | old_cmd, cmd); | |
328 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
329 | } | |
330 | return 0; | |
331 | } |