Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * drivers/pci/setup-res.c | |
3 | * | |
4 | * Extruded from code written by | |
5 | * Dave Rusling (david.rusling@reo.mts.dec.com) | |
6 | * David Mosberger (davidm@cs.arizona.edu) | |
7 | * David Miller (davem@redhat.com) | |
8 | * | |
9 | * Support routines for initializing a PCI subsystem. | |
10 | */ | |
11 | ||
12 | /* fixed for multiple pci buses, 1999 Andrea Arcangeli <andrea@suse.de> */ | |
13 | ||
14 | /* | |
15 | * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru> | |
16 | * Resource sorting | |
17 | */ | |
18 | ||
19 | #include <linux/init.h> | |
20 | #include <linux/kernel.h> | |
363c75db | 21 | #include <linux/export.h> |
1da177e4 LT |
22 | #include <linux/pci.h> |
23 | #include <linux/errno.h> | |
24 | #include <linux/ioport.h> | |
25 | #include <linux/cache.h> | |
26 | #include <linux/slab.h> | |
27 | #include "pci.h" | |
28 | ||
29 | ||
14add80b | 30 | void pci_update_resource(struct pci_dev *dev, int resno) |
1da177e4 LT |
31 | { |
32 | struct pci_bus_region region; | |
33 | u32 new, check, mask; | |
34 | int reg; | |
613e7ed6 | 35 | enum pci_bar_type type; |
14add80b | 36 | struct resource *res = dev->resource + resno; |
1da177e4 | 37 | |
fb0f2b40 RB |
38 | /* |
39 | * Ignore resources for unimplemented BARs and unused resource slots | |
40 | * for 64 bit BARs. | |
41 | */ | |
cf7bee5a IK |
42 | if (!res->flags) |
43 | return; | |
44 | ||
fb0f2b40 RB |
45 | /* |
46 | * Ignore non-moveable resources. This might be legacy resources for | |
47 | * which no functional BAR register exists or another important | |
80ccba11 | 48 | * system resource we shouldn't move around. |
fb0f2b40 RB |
49 | */ |
50 | if (res->flags & IORESOURCE_PCI_FIXED) | |
51 | return; | |
52 | ||
1da177e4 LT |
53 | pcibios_resource_to_bus(dev, ®ion, res); |
54 | ||
1da177e4 LT |
55 | new = region.start | (res->flags & PCI_REGION_FLAG_MASK); |
56 | if (res->flags & IORESOURCE_IO) | |
57 | mask = (u32)PCI_BASE_ADDRESS_IO_MASK; | |
58 | else | |
59 | mask = (u32)PCI_BASE_ADDRESS_MEM_MASK; | |
60 | ||
613e7ed6 YZ |
61 | reg = pci_resource_bar(dev, resno, &type); |
62 | if (!reg) | |
63 | return; | |
64 | if (type != pci_bar_unknown) { | |
755528c8 LT |
65 | if (!(res->flags & IORESOURCE_ROM_ENABLE)) |
66 | return; | |
67 | new |= PCI_ROM_ADDRESS_ENABLE; | |
1da177e4 LT |
68 | } |
69 | ||
70 | pci_write_config_dword(dev, reg, new); | |
71 | pci_read_config_dword(dev, reg, &check); | |
72 | ||
73 | if ((new ^ check) & mask) { | |
80ccba11 BH |
74 | dev_err(&dev->dev, "BAR %d: error updating (%#08x != %#08x)\n", |
75 | resno, new, check); | |
1da177e4 LT |
76 | } |
77 | ||
28c6821a | 78 | if (res->flags & IORESOURCE_MEM_64) { |
cf7bee5a | 79 | new = region.start >> 16 >> 16; |
1da177e4 LT |
80 | pci_write_config_dword(dev, reg + 4, new); |
81 | pci_read_config_dword(dev, reg + 4, &check); | |
82 | if (check != new) { | |
80ccba11 BH |
83 | dev_err(&dev->dev, "BAR %d: error updating " |
84 | "(high %#08x != %#08x)\n", resno, new, check); | |
1da177e4 LT |
85 | } |
86 | } | |
87 | res->flags &= ~IORESOURCE_UNSET; | |
85b8582d VP |
88 | dev_dbg(&dev->dev, "BAR %d: set to %pR (PCI address [%#llx-%#llx])\n", |
89 | resno, res, (unsigned long long)region.start, | |
90 | (unsigned long long)region.end); | |
1da177e4 LT |
91 | } |
92 | ||
96bde06a | 93 | int pci_claim_resource(struct pci_dev *dev, int resource) |
1da177e4 LT |
94 | { |
95 | struct resource *res = &dev->resource[resource]; | |
966f3a75 | 96 | struct resource *root, *conflict; |
1da177e4 | 97 | |
cebd78a8 | 98 | root = pci_find_parent_resource(dev, res); |
865df576 | 99 | if (!root) { |
f6d440da BH |
100 | dev_info(&dev->dev, "no compatible bridge window for %pR\n", |
101 | res); | |
865df576 | 102 | return -EINVAL; |
1da177e4 LT |
103 | } |
104 | ||
966f3a75 BH |
105 | conflict = request_resource_conflict(root, res); |
106 | if (conflict) { | |
f6d440da BH |
107 | dev_info(&dev->dev, |
108 | "address space collision: %pR conflicts with %s %pR\n", | |
109 | res, conflict->name, conflict); | |
966f3a75 BH |
110 | return -EBUSY; |
111 | } | |
865df576 | 112 | |
966f3a75 | 113 | return 0; |
1da177e4 | 114 | } |
eaa959df | 115 | EXPORT_SYMBOL(pci_claim_resource); |
1da177e4 | 116 | |
32a9a682 YS |
117 | #ifdef CONFIG_PCI_QUIRKS |
118 | void pci_disable_bridge_window(struct pci_dev *dev) | |
119 | { | |
865df576 | 120 | dev_info(&dev->dev, "disabling bridge mem windows\n"); |
32a9a682 YS |
121 | |
122 | /* MMIO Base/Limit */ | |
123 | pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0); | |
124 | ||
125 | /* Prefetchable MMIO Base/Limit */ | |
126 | pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0); | |
127 | pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0); | |
128 | pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff); | |
129 | } | |
130 | #endif /* CONFIG_PCI_QUIRKS */ | |
131 | ||
2bbc6942 RP |
132 | |
133 | ||
d09ee968 | 134 | static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev, |
2bbc6942 | 135 | int resno, resource_size_t size, resource_size_t align) |
1da177e4 | 136 | { |
1da177e4 | 137 | struct resource *res = dev->resource + resno; |
2bbc6942 | 138 | resource_size_t min; |
1da177e4 LT |
139 | int ret; |
140 | ||
1da177e4 | 141 | min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM; |
1da177e4 LT |
142 | |
143 | /* First, try exact prefetching match.. */ | |
144 | ret = pci_bus_alloc_resource(bus, res, size, align, min, | |
145 | IORESOURCE_PREFETCH, | |
146 | pcibios_align_resource, dev); | |
147 | ||
148 | if (ret < 0 && (res->flags & IORESOURCE_PREFETCH)) { | |
149 | /* | |
150 | * That failed. | |
151 | * | |
152 | * But a prefetching area can handle a non-prefetching | |
153 | * window (it will just not perform as well). | |
154 | */ | |
155 | ret = pci_bus_alloc_resource(bus, res, size, align, min, 0, | |
156 | pcibios_align_resource, dev); | |
157 | } | |
2bbc6942 RP |
158 | return ret; |
159 | } | |
1da177e4 | 160 | |
2bbc6942 RP |
161 | static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev, |
162 | int resno, resource_size_t size) | |
163 | { | |
164 | struct resource *root, *conflict; | |
165 | resource_size_t start, end; | |
166 | int ret = 0; | |
58c84eda | 167 | |
2bbc6942 RP |
168 | start = res->start; |
169 | end = res->end; | |
170 | res->start = dev->fw_addr[resno]; | |
171 | res->end = res->start + size - 1; | |
351fc6d1 MS |
172 | |
173 | root = pci_find_parent_resource(dev, res); | |
174 | if (!root) { | |
175 | if (res->flags & IORESOURCE_IO) | |
176 | root = &ioport_resource; | |
177 | else | |
178 | root = &iomem_resource; | |
179 | } | |
180 | ||
2bbc6942 RP |
181 | dev_info(&dev->dev, "BAR %d: trying firmware assignment %pR\n", |
182 | resno, res); | |
183 | conflict = request_resource_conflict(root, res); | |
184 | if (conflict) { | |
185 | dev_info(&dev->dev, | |
186 | "BAR %d: %pR conflicts with %s %pR\n", resno, | |
187 | res, conflict->name, conflict); | |
188 | res->start = start; | |
189 | res->end = end; | |
190 | ret = 1; | |
191 | } | |
192 | return ret; | |
193 | } | |
194 | ||
195 | static int _pci_assign_resource(struct pci_dev *dev, int resno, int size, resource_size_t min_align) | |
196 | { | |
197 | struct resource *res = dev->resource + resno; | |
198 | struct pci_bus *bus; | |
199 | int ret; | |
200 | char *type; | |
58c84eda | 201 | |
2bbc6942 RP |
202 | bus = dev->bus; |
203 | while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) { | |
204 | if (!bus->parent || !bus->self->transparent) | |
205 | break; | |
206 | bus = bus->parent; | |
207 | } | |
208 | ||
209 | if (ret) { | |
210 | if (res->flags & IORESOURCE_MEM) | |
211 | if (res->flags & IORESOURCE_PREFETCH) | |
212 | type = "mem pref"; | |
213 | else | |
214 | type = "mem"; | |
215 | else if (res->flags & IORESOURCE_IO) | |
216 | type = "io"; | |
58c84eda | 217 | else |
2bbc6942 RP |
218 | type = "unknown"; |
219 | dev_info(&dev->dev, | |
220 | "BAR %d: can't assign %s (size %#llx)\n", | |
221 | resno, type, (unsigned long long) resource_size(res)); | |
58c84eda BH |
222 | } |
223 | ||
2bbc6942 RP |
224 | return ret; |
225 | } | |
226 | ||
227 | int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize, | |
228 | resource_size_t min_align) | |
229 | { | |
230 | struct resource *res = dev->resource + resno; | |
231 | resource_size_t new_size; | |
232 | int ret; | |
233 | ||
234 | if (!res->parent) { | |
235 | dev_info(&dev->dev, "BAR %d: can't reassign an unassigned resouce %pR " | |
236 | "\n", resno, res); | |
237 | return -EINVAL; | |
238 | } | |
239 | ||
240 | new_size = resource_size(res) + addsize + min_align; | |
241 | ret = _pci_assign_resource(dev, resno, new_size, min_align); | |
d09ee968 | 242 | if (!ret) { |
88452565 | 243 | res->flags &= ~IORESOURCE_STARTALIGN; |
865df576 | 244 | dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res); |
88452565 | 245 | if (resno < PCI_BRIDGE_RESOURCES) |
14add80b | 246 | pci_update_resource(dev, resno); |
1da177e4 | 247 | } |
1da177e4 LT |
248 | return ret; |
249 | } | |
250 | ||
d09ee968 YL |
251 | int pci_assign_resource(struct pci_dev *dev, int resno) |
252 | { | |
253 | struct resource *res = dev->resource + resno; | |
2bbc6942 | 254 | resource_size_t align, size; |
d09ee968 YL |
255 | struct pci_bus *bus; |
256 | int ret; | |
257 | ||
6faf17f6 | 258 | align = pci_resource_alignment(dev, res); |
d09ee968 | 259 | if (!align) { |
865df576 | 260 | dev_info(&dev->dev, "BAR %d: can't assign %pR " |
a369c791 | 261 | "(bogus alignment)\n", resno, res); |
d09ee968 YL |
262 | return -EINVAL; |
263 | } | |
264 | ||
265 | bus = dev->bus; | |
2bbc6942 RP |
266 | size = resource_size(res); |
267 | ret = _pci_assign_resource(dev, resno, size, align); | |
d09ee968 | 268 | |
2bbc6942 RP |
269 | /* |
270 | * If we failed to assign anything, let's try the address | |
271 | * where firmware left it. That at least has a chance of | |
272 | * working, which is better than just leaving it disabled. | |
273 | */ | |
274 | if (ret < 0 && dev->fw_addr[resno]) | |
275 | ret = pci_revert_fw_address(res, dev, resno, size); | |
d09ee968 | 276 | |
2bbc6942 RP |
277 | if (!ret) { |
278 | res->flags &= ~IORESOURCE_STARTALIGN; | |
279 | dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res); | |
280 | if (resno < PCI_BRIDGE_RESOURCES) | |
281 | pci_update_resource(dev, resno); | |
282 | } | |
d09ee968 YL |
283 | return ret; |
284 | } | |
285 | ||
2bbc6942 | 286 | |
1da177e4 | 287 | /* Sort resources by alignment */ |
96bde06a | 288 | void pdev_sort_resources(struct pci_dev *dev, struct resource_list *head) |
1da177e4 LT |
289 | { |
290 | int i; | |
291 | ||
292 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
293 | struct resource *r; | |
294 | struct resource_list *list, *tmp; | |
e31dd6e4 | 295 | resource_size_t r_align; |
1da177e4 LT |
296 | |
297 | r = &dev->resource[i]; | |
fb0f2b40 RB |
298 | |
299 | if (r->flags & IORESOURCE_PCI_FIXED) | |
300 | continue; | |
301 | ||
1da177e4 LT |
302 | if (!(r->flags) || r->parent) |
303 | continue; | |
88452565 | 304 | |
6faf17f6 | 305 | r_align = pci_resource_alignment(dev, r); |
1da177e4 | 306 | if (!r_align) { |
c7dabef8 | 307 | dev_warn(&dev->dev, "BAR %d: %pR has bogus alignment\n", |
a369c791 | 308 | i, r); |
1da177e4 LT |
309 | continue; |
310 | } | |
1da177e4 | 311 | for (list = head; ; list = list->next) { |
e31dd6e4 | 312 | resource_size_t align = 0; |
1da177e4 | 313 | struct resource_list *ln = list->next; |
88452565 IK |
314 | |
315 | if (ln) | |
6faf17f6 | 316 | align = pci_resource_alignment(ln->dev, ln->res); |
88452565 | 317 | |
1da177e4 LT |
318 | if (r_align > align) { |
319 | tmp = kmalloc(sizeof(*tmp), GFP_KERNEL); | |
320 | if (!tmp) | |
321 | panic("pdev_sort_resources(): " | |
322 | "kmalloc() failed!\n"); | |
323 | tmp->next = ln; | |
324 | tmp->res = r; | |
325 | tmp->dev = dev; | |
326 | list->next = tmp; | |
327 | break; | |
328 | } | |
329 | } | |
330 | } | |
331 | } | |
842de40d BH |
332 | |
333 | int pci_enable_resources(struct pci_dev *dev, int mask) | |
334 | { | |
335 | u16 cmd, old_cmd; | |
336 | int i; | |
337 | struct resource *r; | |
338 | ||
339 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
340 | old_cmd = cmd; | |
341 | ||
342 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
343 | if (!(mask & (1 << i))) | |
344 | continue; | |
345 | ||
346 | r = &dev->resource[i]; | |
347 | ||
348 | if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM))) | |
349 | continue; | |
350 | if ((i == PCI_ROM_RESOURCE) && | |
351 | (!(r->flags & IORESOURCE_ROM_ENABLE))) | |
352 | continue; | |
353 | ||
354 | if (!r->parent) { | |
865df576 BH |
355 | dev_err(&dev->dev, "device not available " |
356 | "(can't reserve %pR)\n", r); | |
842de40d BH |
357 | return -EINVAL; |
358 | } | |
359 | ||
360 | if (r->flags & IORESOURCE_IO) | |
361 | cmd |= PCI_COMMAND_IO; | |
362 | if (r->flags & IORESOURCE_MEM) | |
363 | cmd |= PCI_COMMAND_MEMORY; | |
364 | } | |
365 | ||
366 | if (cmd != old_cmd) { | |
367 | dev_info(&dev->dev, "enabling device (%04x -> %04x)\n", | |
368 | old_cmd, cmd); | |
369 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
370 | } | |
371 | return 0; | |
372 | } |