Commit | Line | Data |
---|---|---|
de957c89 MT |
1 | /* |
2 | * m8xx_pcmcia.c - Linux PCMCIA socket driver for the mpc8xx series. | |
3 | * | |
cbba0de2 | 4 | * (C) 1999-2000 Magnus Damm <damm@opensource.se> |
de957c89 MT |
5 | * (C) 2001-2002 Montavista Software, Inc. |
6 | * <mlocke@mvista.com> | |
7 | * | |
8 | * Support for two slots by Cyclades Corporation | |
9 | * <oliver.kurth@cyclades.de> | |
10 | * Further fixes, v2.6 kernel port | |
11 | * <marcelo.tosatti@cyclades.com> | |
1371d3be | 12 | * |
80128ff7 | 13 | * Some fixes, additions (C) 2005-2007 Montavista Software, Inc. |
1371d3be | 14 | * <vbordug@ru.mvista.com> |
de957c89 MT |
15 | * |
16 | * "The ExCA standard specifies that socket controllers should provide | |
17 | * two IO and five memory windows per socket, which can be independently | |
18 | * configured and positioned in the host address space and mapped to | |
19 | * arbitrary segments of card address space. " - David A Hinds. 1999 | |
20 | * | |
21 | * This controller does _not_ meet the ExCA standard. | |
22 | * | |
23 | * m8xx pcmcia controller brief info: | |
24 | * + 8 windows (attrib, mem, i/o) | |
25 | * + up to two slots (SLOT_A and SLOT_B) | |
26 | * + inputpins, outputpins, event and mask registers. | |
27 | * - no offset register. sigh. | |
28 | * | |
29 | * Because of the lacking offset register we must map the whole card. | |
30 | * We assign each memory window PCMCIA_MEM_WIN_SIZE address space. | |
31 | * Make sure there is (PCMCIA_MEM_WIN_SIZE * PCMCIA_MEM_WIN_NO | |
32 | * * PCMCIA_SOCKETS_NO) bytes at PCMCIA_MEM_WIN_BASE. | |
33 | * The i/o windows are dynamically allocated at PCMCIA_IO_WIN_BASE. | |
34 | * They are maximum 64KByte each... | |
35 | */ | |
36 | ||
37 | #include <linux/module.h> | |
38 | #include <linux/init.h> | |
39 | #include <linux/types.h> | |
40 | #include <linux/fcntl.h> | |
41 | #include <linux/string.h> | |
42 | ||
de957c89 MT |
43 | #include <linux/kernel.h> |
44 | #include <linux/errno.h> | |
de957c89 MT |
45 | #include <linux/timer.h> |
46 | #include <linux/ioport.h> | |
47 | #include <linux/delay.h> | |
48 | #include <linux/interrupt.h> | |
80128ff7 | 49 | #include <linux/fsl_devices.h> |
1977f032 | 50 | #include <linux/bitops.h> |
ad19dbdb SR |
51 | #include <linux/of_device.h> |
52 | #include <linux/of_platform.h> | |
de957c89 | 53 | |
80128ff7 | 54 | #include <asm/io.h> |
80128ff7 VB |
55 | #include <asm/system.h> |
56 | #include <asm/time.h> | |
de957c89 MT |
57 | #include <asm/mpc8xx.h> |
58 | #include <asm/8xx_immap.h> | |
59 | #include <asm/irq.h> | |
80128ff7 | 60 | #include <asm/fs_pd.h> |
de957c89 | 61 | |
de957c89 MT |
62 | #include <pcmcia/ss.h> |
63 | ||
de957c89 MT |
64 | #define pcmcia_info(args...) printk(KERN_INFO "m8xx_pcmcia: "args) |
65 | #define pcmcia_error(args...) printk(KERN_ERR "m8xx_pcmcia: "args) | |
66 | ||
67 | static const char *version = "Version 0.06, Aug 2005"; | |
68 | MODULE_LICENSE("Dual MPL/GPL"); | |
69 | ||
70 | #if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) | |
71 | ||
72 | /* The RPX series use SLOT_B */ | |
73 | #if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE) | |
74 | #define CONFIG_PCMCIA_SLOT_B | |
75 | #define CONFIG_BD_IS_MHZ | |
76 | #endif | |
77 | ||
78 | /* The ADS board use SLOT_A */ | |
79 | #ifdef CONFIG_ADS | |
80 | #define CONFIG_PCMCIA_SLOT_A | |
81 | #define CONFIG_BD_IS_MHZ | |
82 | #endif | |
83 | ||
84 | /* The FADS series are a mess */ | |
85 | #ifdef CONFIG_FADS | |
86 | #if defined(CONFIG_MPC860T) || defined(CONFIG_MPC860) || defined(CONFIG_MPC821) | |
87 | #define CONFIG_PCMCIA_SLOT_A | |
88 | #else | |
89 | #define CONFIG_PCMCIA_SLOT_B | |
90 | #endif | |
91 | #endif | |
92 | ||
1371d3be VB |
93 | #if defined(CONFIG_MPC885ADS) |
94 | #define CONFIG_PCMCIA_SLOT_A | |
95 | #define PCMCIA_GLITCHY_CD | |
96 | #endif | |
97 | ||
de957c89 MT |
98 | /* Cyclades ACS uses both slots */ |
99 | #ifdef CONFIG_PRxK | |
100 | #define CONFIG_PCMCIA_SLOT_A | |
101 | #define CONFIG_PCMCIA_SLOT_B | |
102 | #endif | |
103 | ||
99121c0d | 104 | #endif /* !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) */ |
de957c89 MT |
105 | |
106 | #if defined(CONFIG_PCMCIA_SLOT_A) && defined(CONFIG_PCMCIA_SLOT_B) | |
107 | ||
108 | #define PCMCIA_SOCKETS_NO 2 | |
109 | /* We have only 8 windows, dualsocket support will be limited. */ | |
110 | #define PCMCIA_MEM_WIN_NO 2 | |
111 | #define PCMCIA_IO_WIN_NO 2 | |
112 | #define PCMCIA_SLOT_MSG "SLOT_A and SLOT_B" | |
113 | ||
114 | #elif defined(CONFIG_PCMCIA_SLOT_A) || defined(CONFIG_PCMCIA_SLOT_B) | |
115 | ||
116 | #define PCMCIA_SOCKETS_NO 1 | |
117 | /* full support for one slot */ | |
118 | #define PCMCIA_MEM_WIN_NO 5 | |
119 | #define PCMCIA_IO_WIN_NO 2 | |
120 | ||
121 | /* define _slot_ to be able to optimize macros */ | |
122 | ||
123 | #ifdef CONFIG_PCMCIA_SLOT_A | |
124 | #define _slot_ 0 | |
125 | #define PCMCIA_SLOT_MSG "SLOT_A" | |
126 | #else | |
127 | #define _slot_ 1 | |
128 | #define PCMCIA_SLOT_MSG "SLOT_B" | |
129 | #endif | |
130 | ||
131 | #else | |
132 | #error m8xx_pcmcia: Bad configuration! | |
133 | #endif | |
134 | ||
135 | /* ------------------------------------------------------------------------- */ | |
136 | ||
99121c0d VB |
137 | #define PCMCIA_MEM_WIN_BASE 0xe0000000 /* base address for memory window 0 */ |
138 | #define PCMCIA_MEM_WIN_SIZE 0x04000000 /* each memory window is 64 MByte */ | |
139 | #define PCMCIA_IO_WIN_BASE _IO_BASE /* base address for io window 0 */ | |
de957c89 MT |
140 | /* ------------------------------------------------------------------------- */ |
141 | ||
80128ff7 | 142 | static int pcmcia_schlvl; |
de957c89 | 143 | |
34af946a | 144 | static DEFINE_SPINLOCK(events_lock); |
de957c89 | 145 | |
de957c89 MT |
146 | #define PCMCIA_SOCKET_KEY_5V 1 |
147 | #define PCMCIA_SOCKET_KEY_LV 2 | |
148 | ||
149 | /* look up table for pgcrx registers */ | |
80128ff7 | 150 | static u32 *m8xx_pgcrx[2]; |
de957c89 MT |
151 | |
152 | /* | |
153 | * This structure is used to address each window in the PCMCIA controller. | |
154 | * | |
155 | * Keep in mind that we assume that pcmcia_win[n+1] is mapped directly | |
156 | * after pcmcia_win[n]... | |
157 | */ | |
158 | ||
159 | struct pcmcia_win { | |
99121c0d VB |
160 | u32 br; |
161 | u32 or; | |
de957c89 MT |
162 | }; |
163 | ||
164 | /* | |
165 | * For some reason the hardware guys decided to make both slots share | |
166 | * some registers. | |
167 | * | |
168 | * Could someone invent object oriented hardware ? | |
169 | * | |
170 | * The macros are used to get the right bit from the registers. | |
171 | * SLOT_A : slot = 0 | |
172 | * SLOT_B : slot = 1 | |
173 | */ | |
174 | ||
175 | #define M8XX_PCMCIA_VS1(slot) (0x80000000 >> (slot << 4)) | |
176 | #define M8XX_PCMCIA_VS2(slot) (0x40000000 >> (slot << 4)) | |
177 | #define M8XX_PCMCIA_VS_MASK(slot) (0xc0000000 >> (slot << 4)) | |
178 | #define M8XX_PCMCIA_VS_SHIFT(slot) (30 - (slot << 4)) | |
179 | ||
180 | #define M8XX_PCMCIA_WP(slot) (0x20000000 >> (slot << 4)) | |
181 | #define M8XX_PCMCIA_CD2(slot) (0x10000000 >> (slot << 4)) | |
182 | #define M8XX_PCMCIA_CD1(slot) (0x08000000 >> (slot << 4)) | |
183 | #define M8XX_PCMCIA_BVD2(slot) (0x04000000 >> (slot << 4)) | |
184 | #define M8XX_PCMCIA_BVD1(slot) (0x02000000 >> (slot << 4)) | |
185 | #define M8XX_PCMCIA_RDY(slot) (0x01000000 >> (slot << 4)) | |
186 | #define M8XX_PCMCIA_RDY_L(slot) (0x00800000 >> (slot << 4)) | |
187 | #define M8XX_PCMCIA_RDY_H(slot) (0x00400000 >> (slot << 4)) | |
188 | #define M8XX_PCMCIA_RDY_R(slot) (0x00200000 >> (slot << 4)) | |
189 | #define M8XX_PCMCIA_RDY_F(slot) (0x00100000 >> (slot << 4)) | |
190 | #define M8XX_PCMCIA_MASK(slot) (0xFFFF0000 >> (slot << 4)) | |
191 | ||
192 | #define M8XX_PCMCIA_POR_VALID 0x00000001 | |
193 | #define M8XX_PCMCIA_POR_WRPROT 0x00000002 | |
194 | #define M8XX_PCMCIA_POR_ATTRMEM 0x00000010 | |
195 | #define M8XX_PCMCIA_POR_IO 0x00000018 | |
196 | #define M8XX_PCMCIA_POR_16BIT 0x00000040 | |
197 | ||
198 | #define M8XX_PGCRX(slot) m8xx_pgcrx[slot] | |
199 | ||
200 | #define M8XX_PGCRX_CXOE 0x00000080 | |
201 | #define M8XX_PGCRX_CXRESET 0x00000040 | |
202 | ||
203 | /* we keep one lookup table per socket to check flags */ | |
204 | ||
99121c0d | 205 | #define PCMCIA_EVENTS_MAX 5 /* 4 max at a time + termination */ |
de957c89 MT |
206 | |
207 | struct event_table { | |
208 | u32 regbit; | |
209 | u32 eventbit; | |
210 | }; | |
211 | ||
80128ff7 VB |
212 | static const char driver_name[] = "m8xx-pcmcia"; |
213 | ||
de957c89 | 214 | struct socket_info { |
99121c0d VB |
215 | void (*handler) (void *info, u32 events); |
216 | void *info; | |
de957c89 MT |
217 | |
218 | u32 slot; | |
80128ff7 VB |
219 | pcmconf8xx_t *pcmcia; |
220 | u32 bus_freq; | |
221 | int hwirq; | |
de957c89 MT |
222 | |
223 | socket_state_t state; | |
224 | struct pccard_mem_map mem_win[PCMCIA_MEM_WIN_NO]; | |
99121c0d | 225 | struct pccard_io_map io_win[PCMCIA_IO_WIN_NO]; |
de957c89 MT |
226 | struct event_table events[PCMCIA_EVENTS_MAX]; |
227 | struct pcmcia_socket socket; | |
228 | }; | |
229 | ||
230 | static struct socket_info socket[PCMCIA_SOCKETS_NO]; | |
231 | ||
232 | /* | |
233 | * Search this table to see if the windowsize is | |
234 | * supported... | |
235 | */ | |
236 | ||
237 | #define M8XX_SIZES_NO 32 | |
238 | ||
99121c0d | 239 | static const u32 m8xx_size_to_gray[M8XX_SIZES_NO] = { |
de957c89 MT |
240 | 0x00000001, 0x00000002, 0x00000008, 0x00000004, |
241 | 0x00000080, 0x00000040, 0x00000010, 0x00000020, | |
242 | 0x00008000, 0x00004000, 0x00001000, 0x00002000, | |
243 | 0x00000100, 0x00000200, 0x00000800, 0x00000400, | |
244 | ||
245 | 0x0fffffff, 0xffffffff, 0xffffffff, 0xffffffff, | |
246 | 0x01000000, 0x02000000, 0xffffffff, 0x04000000, | |
247 | 0x00010000, 0x00020000, 0x00080000, 0x00040000, | |
248 | 0x00800000, 0x00400000, 0x00100000, 0x00200000 | |
249 | }; | |
250 | ||
251 | /* ------------------------------------------------------------------------- */ | |
252 | ||
7d12e780 | 253 | static irqreturn_t m8xx_interrupt(int irq, void *dev); |
de957c89 | 254 | |
99121c0d | 255 | #define PCMCIA_BMT_LIMIT (15*4) /* Bus Monitor Timeout value */ |
de957c89 MT |
256 | |
257 | /* ------------------------------------------------------------------------- */ | |
258 | /* board specific stuff: */ | |
259 | /* voltage_set(), hardware_enable() and hardware_disable() */ | |
260 | /* ------------------------------------------------------------------------- */ | |
261 | /* RPX Boards from Embedded Planet */ | |
262 | ||
263 | #if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE) | |
264 | ||
265 | /* The RPX boards seems to have it's bus monitor timeout set to 6*8 clocks. | |
266 | * SYPCR is write once only, therefore must the slowest memory be faster | |
267 | * than the bus monitor or we will get a machine check due to the bus timeout. | |
268 | */ | |
269 | ||
270 | #define PCMCIA_BOARD_MSG "RPX CLASSIC or RPX LITE" | |
271 | ||
272 | #undef PCMCIA_BMT_LIMIT | |
273 | #define PCMCIA_BMT_LIMIT (6*8) | |
274 | ||
275 | static int voltage_set(int slot, int vcc, int vpp) | |
276 | { | |
277 | u32 reg = 0; | |
278 | ||
99121c0d VB |
279 | switch (vcc) { |
280 | case 0: | |
281 | break; | |
de957c89 MT |
282 | case 33: |
283 | reg |= BCSR1_PCVCTL4; | |
284 | break; | |
285 | case 50: | |
286 | reg |= BCSR1_PCVCTL5; | |
287 | break; | |
288 | default: | |
289 | return 1; | |
290 | } | |
291 | ||
99121c0d VB |
292 | switch (vpp) { |
293 | case 0: | |
294 | break; | |
de957c89 MT |
295 | case 33: |
296 | case 50: | |
99121c0d | 297 | if (vcc == vpp) |
de957c89 MT |
298 | reg |= BCSR1_PCVCTL6; |
299 | else | |
300 | return 1; | |
301 | break; | |
302 | case 120: | |
303 | reg |= BCSR1_PCVCTL7; | |
304 | default: | |
305 | return 1; | |
306 | } | |
307 | ||
99121c0d | 308 | if (!((vcc == 50) || (vcc == 0))) |
de957c89 MT |
309 | return 1; |
310 | ||
311 | /* first, turn off all power */ | |
312 | ||
99121c0d VB |
313 | out_be32(((u32 *) RPX_CSR_ADDR), |
314 | in_be32(((u32 *) RPX_CSR_ADDR)) & ~(BCSR1_PCVCTL4 | | |
315 | BCSR1_PCVCTL5 | | |
316 | BCSR1_PCVCTL6 | | |
317 | BCSR1_PCVCTL7)); | |
de957c89 MT |
318 | |
319 | /* enable new powersettings */ | |
320 | ||
99121c0d | 321 | out_be32(((u32 *) RPX_CSR_ADDR), in_be32(((u32 *) RPX_CSR_ADDR)) | reg); |
de957c89 MT |
322 | |
323 | return 0; | |
324 | } | |
325 | ||
326 | #define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V | |
99121c0d VB |
327 | #define hardware_enable(_slot_) /* No hardware to enable */ |
328 | #define hardware_disable(_slot_) /* No hardware to disable */ | |
de957c89 | 329 | |
99121c0d | 330 | #endif /* CONFIG_RPXCLASSIC */ |
de957c89 MT |
331 | |
332 | /* FADS Boards from Motorola */ | |
333 | ||
334 | #if defined(CONFIG_FADS) | |
335 | ||
336 | #define PCMCIA_BOARD_MSG "FADS" | |
337 | ||
338 | static int voltage_set(int slot, int vcc, int vpp) | |
339 | { | |
340 | u32 reg = 0; | |
341 | ||
99121c0d VB |
342 | switch (vcc) { |
343 | case 0: | |
344 | break; | |
345 | case 33: | |
346 | reg |= BCSR1_PCCVCC0; | |
347 | break; | |
348 | case 50: | |
349 | reg |= BCSR1_PCCVCC1; | |
350 | break; | |
351 | default: | |
352 | return 1; | |
de957c89 MT |
353 | } |
354 | ||
99121c0d VB |
355 | switch (vpp) { |
356 | case 0: | |
357 | break; | |
358 | case 33: | |
359 | case 50: | |
360 | if (vcc == vpp) | |
361 | reg |= BCSR1_PCCVPP1; | |
362 | else | |
de957c89 | 363 | return 1; |
99121c0d VB |
364 | break; |
365 | case 120: | |
366 | if ((vcc == 33) || (vcc == 50)) | |
367 | reg |= BCSR1_PCCVPP0; | |
368 | else | |
369 | return 1; | |
370 | default: | |
371 | return 1; | |
de957c89 MT |
372 | } |
373 | ||
374 | /* first, turn off all power */ | |
99121c0d VB |
375 | out_be32((u32 *) BCSR1, |
376 | in_be32((u32 *) BCSR1) & ~(BCSR1_PCCVCC_MASK | | |
377 | BCSR1_PCCVPP_MASK)); | |
1371d3be VB |
378 | |
379 | /* enable new powersettings */ | |
99121c0d | 380 | out_be32((u32 *) BCSR1, in_be32((u32 *) BCSR1) | reg); |
1371d3be VB |
381 | |
382 | return 0; | |
383 | } | |
384 | ||
385 | #define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V | |
386 | ||
387 | static void hardware_enable(int slot) | |
388 | { | |
99121c0d | 389 | out_be32((u32 *) BCSR1, in_be32((u32 *) BCSR1) & ~BCSR1_PCCEN); |
1371d3be VB |
390 | } |
391 | ||
392 | static void hardware_disable(int slot) | |
393 | { | |
99121c0d | 394 | out_be32((u32 *) BCSR1, in_be32((u32 *) BCSR1) | BCSR1_PCCEN); |
1371d3be VB |
395 | } |
396 | ||
397 | #endif | |
398 | ||
399 | /* MPC885ADS Boards */ | |
400 | ||
401 | #if defined(CONFIG_MPC885ADS) | |
402 | ||
403 | #define PCMCIA_BOARD_MSG "MPC885ADS" | |
80128ff7 | 404 | #define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V |
1371d3be | 405 | |
80128ff7 | 406 | static inline void hardware_enable(int slot) |
1371d3be | 407 | { |
99121c0d | 408 | m8xx_pcmcia_ops.hw_ctrl(slot, 1); |
de957c89 MT |
409 | } |
410 | ||
80128ff7 | 411 | static inline void hardware_disable(int slot) |
de957c89 | 412 | { |
80128ff7 | 413 | m8xx_pcmcia_ops.hw_ctrl(slot, 0); |
de957c89 MT |
414 | } |
415 | ||
80128ff7 | 416 | static inline int voltage_set(int slot, int vcc, int vpp) |
de957c89 | 417 | { |
80128ff7 | 418 | return m8xx_pcmcia_ops.voltage_set(slot, vcc, vpp); |
de957c89 MT |
419 | } |
420 | ||
421 | #endif | |
422 | ||
423 | /* ------------------------------------------------------------------------- */ | |
424 | /* Motorola MBX860 */ | |
425 | ||
426 | #if defined(CONFIG_MBX) | |
427 | ||
428 | #define PCMCIA_BOARD_MSG "MBX" | |
429 | ||
430 | static int voltage_set(int slot, int vcc, int vpp) | |
431 | { | |
432 | u8 reg = 0; | |
433 | ||
99121c0d VB |
434 | switch (vcc) { |
435 | case 0: | |
436 | break; | |
437 | case 33: | |
438 | reg |= CSR2_VCC_33; | |
439 | break; | |
440 | case 50: | |
441 | reg |= CSR2_VCC_50; | |
442 | break; | |
443 | default: | |
444 | return 1; | |
de957c89 MT |
445 | } |
446 | ||
99121c0d VB |
447 | switch (vpp) { |
448 | case 0: | |
449 | break; | |
450 | case 33: | |
451 | case 50: | |
452 | if (vcc == vpp) | |
453 | reg |= CSR2_VPP_VCC; | |
454 | else | |
455 | return 1; | |
456 | break; | |
457 | case 120: | |
458 | if ((vcc == 33) || (vcc == 50)) | |
459 | reg |= CSR2_VPP_12; | |
460 | else | |
de957c89 | 461 | return 1; |
99121c0d VB |
462 | default: |
463 | return 1; | |
de957c89 MT |
464 | } |
465 | ||
466 | /* first, turn off all power */ | |
99121c0d VB |
467 | out_8((u8 *) MBX_CSR2_ADDR, |
468 | in_8((u8 *) MBX_CSR2_ADDR) & ~(CSR2_VCC_MASK | CSR2_VPP_MASK)); | |
de957c89 MT |
469 | |
470 | /* enable new powersettings */ | |
99121c0d | 471 | out_8((u8 *) MBX_CSR2_ADDR, in_8((u8 *) MBX_CSR2_ADDR) | reg); |
de957c89 MT |
472 | |
473 | return 0; | |
474 | } | |
475 | ||
476 | #define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V | |
99121c0d VB |
477 | #define hardware_enable(_slot_) /* No hardware to enable */ |
478 | #define hardware_disable(_slot_) /* No hardware to disable */ | |
de957c89 | 479 | |
99121c0d | 480 | #endif /* CONFIG_MBX */ |
de957c89 MT |
481 | |
482 | #if defined(CONFIG_PRxK) | |
483 | #include <asm/cpld.h> | |
484 | extern volatile fpga_pc_regs *fpga_pc; | |
485 | ||
486 | #define PCMCIA_BOARD_MSG "MPC855T" | |
487 | ||
488 | static int voltage_set(int slot, int vcc, int vpp) | |
489 | { | |
490 | u8 reg = 0; | |
491 | u8 regread; | |
492 | cpld_regs *ccpld = get_cpld(); | |
493 | ||
99121c0d VB |
494 | switch (vcc) { |
495 | case 0: | |
496 | break; | |
497 | case 33: | |
498 | reg |= PCMCIA_VCC_33; | |
499 | break; | |
500 | case 50: | |
501 | reg |= PCMCIA_VCC_50; | |
502 | break; | |
503 | default: | |
504 | return 1; | |
de957c89 MT |
505 | } |
506 | ||
99121c0d VB |
507 | switch (vpp) { |
508 | case 0: | |
509 | break; | |
510 | case 33: | |
511 | case 50: | |
512 | if (vcc == vpp) | |
513 | reg |= PCMCIA_VPP_VCC; | |
514 | else | |
de957c89 | 515 | return 1; |
99121c0d VB |
516 | break; |
517 | case 120: | |
518 | if ((vcc == 33) || (vcc == 50)) | |
519 | reg |= PCMCIA_VPP_12; | |
520 | else | |
521 | return 1; | |
522 | default: | |
523 | return 1; | |
de957c89 MT |
524 | } |
525 | ||
526 | reg = reg >> (slot << 2); | |
527 | regread = in_8(&ccpld->fpga_pc_ctl); | |
99121c0d VB |
528 | if (reg != |
529 | (regread & ((PCMCIA_VCC_MASK | PCMCIA_VPP_MASK) >> (slot << 2)))) { | |
de957c89 | 530 | /* enable new powersettings */ |
99121c0d VB |
531 | regread = |
532 | regread & ~((PCMCIA_VCC_MASK | PCMCIA_VPP_MASK) >> | |
533 | (slot << 2)); | |
de957c89 MT |
534 | out_8(&ccpld->fpga_pc_ctl, reg | regread); |
535 | msleep(100); | |
536 | } | |
537 | ||
538 | return 0; | |
539 | } | |
540 | ||
541 | #define socket_get(_slot_) PCMCIA_SOCKET_KEY_LV | |
99121c0d VB |
542 | #define hardware_enable(_slot_) /* No hardware to enable */ |
543 | #define hardware_disable(_slot_) /* No hardware to disable */ | |
de957c89 | 544 | |
99121c0d | 545 | #endif /* CONFIG_PRxK */ |
de957c89 | 546 | |
de957c89 | 547 | static u32 pending_events[PCMCIA_SOCKETS_NO]; |
34af946a | 548 | static DEFINE_SPINLOCK(pending_event_lock); |
de957c89 | 549 | |
7d12e780 | 550 | static irqreturn_t m8xx_interrupt(int irq, void *dev) |
de957c89 MT |
551 | { |
552 | struct socket_info *s; | |
553 | struct event_table *e; | |
554 | unsigned int i, events, pscr, pipr, per; | |
99121c0d | 555 | pcmconf8xx_t *pcmcia = socket[0].pcmcia; |
de957c89 | 556 | |
c9f50ddd | 557 | pr_debug("m8xx_pcmcia: Interrupt!\n"); |
de957c89 MT |
558 | /* get interrupt sources */ |
559 | ||
80128ff7 VB |
560 | pscr = in_be32(&pcmcia->pcmc_pscr); |
561 | pipr = in_be32(&pcmcia->pcmc_pipr); | |
562 | per = in_be32(&pcmcia->pcmc_per); | |
de957c89 | 563 | |
99121c0d | 564 | for (i = 0; i < PCMCIA_SOCKETS_NO; i++) { |
de957c89 MT |
565 | s = &socket[i]; |
566 | e = &s->events[0]; | |
567 | events = 0; | |
568 | ||
99121c0d VB |
569 | while (e->regbit) { |
570 | if (pscr & e->regbit) | |
de957c89 MT |
571 | events |= e->eventbit; |
572 | ||
99121c0d | 573 | e++; |
de957c89 MT |
574 | } |
575 | ||
576 | /* | |
577 | * report only if both card detect signals are the same | |
578 | * not too nice done, | |
579 | * we depend on that CD2 is the bit to the left of CD1... | |
580 | */ | |
99121c0d VB |
581 | if (events & SS_DETECT) |
582 | if (((pipr & M8XX_PCMCIA_CD2(i)) >> 1) ^ | |
583 | (pipr & M8XX_PCMCIA_CD1(i))) { | |
de957c89 MT |
584 | events &= ~SS_DETECT; |
585 | } | |
de957c89 MT |
586 | #ifdef PCMCIA_GLITCHY_CD |
587 | /* | |
588 | * I've experienced CD problems with my ADS board. | |
589 | * We make an extra check to see if there was a | |
590 | * real change of Card detection. | |
591 | */ | |
592 | ||
99121c0d VB |
593 | if ((events & SS_DETECT) && |
594 | ((pipr & | |
595 | (M8XX_PCMCIA_CD2(i) | M8XX_PCMCIA_CD1(i))) == 0) && | |
596 | (s->state.Vcc | s->state.Vpp)) { | |
de957c89 MT |
597 | events &= ~SS_DETECT; |
598 | /*printk( "CD glitch workaround - CD = 0x%08x!\n", | |
99121c0d VB |
599 | (pipr & (M8XX_PCMCIA_CD2(i) |
600 | | M8XX_PCMCIA_CD1(i)))); */ | |
de957c89 MT |
601 | } |
602 | #endif | |
603 | ||
604 | /* call the handler */ | |
605 | ||
c9f50ddd | 606 | pr_debug("m8xx_pcmcia: slot %u: events = 0x%02x, pscr = 0x%08x, " |
99121c0d | 607 | "pipr = 0x%08x\n", i, events, pscr, pipr); |
de957c89 | 608 | |
99121c0d | 609 | if (events) { |
de957c89 MT |
610 | spin_lock(&pending_event_lock); |
611 | pending_events[i] |= events; | |
612 | spin_unlock(&pending_event_lock); | |
613 | /* | |
614 | * Turn off RDY_L bits in the PER mask on | |
615 | * CD interrupt receival. | |
616 | * | |
617 | * They can generate bad interrupts on the | |
618 | * ACS4,8,16,32. - marcelo | |
619 | */ | |
620 | per &= ~M8XX_PCMCIA_RDY_L(0); | |
621 | per &= ~M8XX_PCMCIA_RDY_L(1); | |
622 | ||
80128ff7 | 623 | out_be32(&pcmcia->pcmc_per, per); |
de957c89 MT |
624 | |
625 | if (events) | |
626 | pcmcia_parse_events(&socket[i].socket, events); | |
627 | } | |
628 | } | |
629 | ||
630 | /* clear the interrupt sources */ | |
80128ff7 | 631 | out_be32(&pcmcia->pcmc_pscr, pscr); |
de957c89 | 632 | |
c9f50ddd | 633 | pr_debug("m8xx_pcmcia: Interrupt done.\n"); |
de957c89 MT |
634 | |
635 | return IRQ_HANDLED; | |
636 | } | |
637 | ||
638 | static u32 m8xx_get_graycode(u32 size) | |
639 | { | |
640 | u32 k; | |
641 | ||
99121c0d VB |
642 | for (k = 0; k < M8XX_SIZES_NO; k++) |
643 | if (m8xx_size_to_gray[k] == size) | |
de957c89 MT |
644 | break; |
645 | ||
99121c0d | 646 | if ((k == M8XX_SIZES_NO) || (m8xx_size_to_gray[k] == -1)) |
de957c89 MT |
647 | k = -1; |
648 | ||
649 | return k; | |
650 | } | |
651 | ||
80128ff7 | 652 | static u32 m8xx_get_speed(u32 ns, u32 is_io, u32 bus_freq) |
de957c89 MT |
653 | { |
654 | u32 reg, clocks, psst, psl, psht; | |
655 | ||
99121c0d | 656 | if (!ns) { |
de957c89 MT |
657 | |
658 | /* | |
659 | * We get called with IO maps setup to 0ns | |
660 | * if not specified by the user. | |
661 | * They should be 255ns. | |
662 | */ | |
663 | ||
99121c0d | 664 | if (is_io) |
de957c89 MT |
665 | ns = 255; |
666 | else | |
99121c0d | 667 | ns = 100; /* fast memory if 0 */ |
de957c89 MT |
668 | } |
669 | ||
670 | /* | |
671 | * In PSST, PSL, PSHT fields we tell the controller | |
672 | * timing parameters in CLKOUT clock cycles. | |
673 | * CLKOUT is the same as GCLK2_50. | |
674 | */ | |
675 | ||
676 | /* how we want to adjust the timing - in percent */ | |
677 | ||
99121c0d | 678 | #define ADJ 180 /* 80 % longer accesstime - to be sure */ |
de957c89 | 679 | |
80128ff7 | 680 | clocks = ((bus_freq / 1000) * ns) / 1000; |
99121c0d VB |
681 | clocks = (clocks * ADJ) / (100 * 1000); |
682 | if (clocks >= PCMCIA_BMT_LIMIT) { | |
683 | printk("Max access time limit reached\n"); | |
684 | clocks = PCMCIA_BMT_LIMIT - 1; | |
de957c89 MT |
685 | } |
686 | ||
99121c0d VB |
687 | psst = clocks / 7; /* setup time */ |
688 | psht = clocks / 7; /* hold time */ | |
689 | psl = (clocks * 5) / 7; /* strobe length */ | |
de957c89 MT |
690 | |
691 | psst += clocks - (psst + psht + psl); | |
692 | ||
99121c0d VB |
693 | reg = psst << 12; |
694 | reg |= psl << 7; | |
de957c89 MT |
695 | reg |= psht << 16; |
696 | ||
697 | return reg; | |
698 | } | |
699 | ||
700 | static int m8xx_get_status(struct pcmcia_socket *sock, unsigned int *value) | |
701 | { | |
702 | int lsock = container_of(sock, struct socket_info, socket)->slot; | |
703 | struct socket_info *s = &socket[lsock]; | |
704 | unsigned int pipr, reg; | |
80128ff7 | 705 | pcmconf8xx_t *pcmcia = s->pcmcia; |
de957c89 | 706 | |
80128ff7 | 707 | pipr = in_be32(&pcmcia->pcmc_pipr); |
de957c89 | 708 | |
99121c0d VB |
709 | *value = ((pipr & (M8XX_PCMCIA_CD1(lsock) |
710 | | M8XX_PCMCIA_CD2(lsock))) == 0) ? SS_DETECT : 0; | |
de957c89 MT |
711 | *value |= (pipr & M8XX_PCMCIA_WP(lsock)) ? SS_WRPROT : 0; |
712 | ||
713 | if (s->state.flags & SS_IOCARD) | |
714 | *value |= (pipr & M8XX_PCMCIA_BVD1(lsock)) ? SS_STSCHG : 0; | |
715 | else { | |
716 | *value |= (pipr & M8XX_PCMCIA_RDY(lsock)) ? SS_READY : 0; | |
717 | *value |= (pipr & M8XX_PCMCIA_BVD1(lsock)) ? SS_BATDEAD : 0; | |
718 | *value |= (pipr & M8XX_PCMCIA_BVD2(lsock)) ? SS_BATWARN : 0; | |
719 | } | |
720 | ||
721 | if (s->state.Vcc | s->state.Vpp) | |
722 | *value |= SS_POWERON; | |
723 | ||
724 | /* | |
725 | * Voltage detection: | |
726 | * This driver only supports 16-Bit pc-cards. | |
727 | * Cardbus is not handled here. | |
728 | * | |
729 | * To determine what voltage to use we must read the VS1 and VS2 pin. | |
730 | * Depending on what socket type is present, | |
731 | * different combinations mean different things. | |
732 | * | |
733 | * Card Key Socket Key VS1 VS2 Card Vcc for CIS parse | |
734 | * | |
735 | * 5V 5V, LV* NC NC 5V only 5V (if available) | |
736 | * | |
737 | * 5V 5V, LV* GND NC 5 or 3.3V as low as possible | |
738 | * | |
739 | * 5V 5V, LV* GND GND 5, 3.3, x.xV as low as possible | |
740 | * | |
741 | * LV* 5V - - shall not fit into socket | |
742 | * | |
743 | * LV* LV* GND NC 3.3V only 3.3V | |
744 | * | |
745 | * LV* LV* NC GND x.xV x.xV (if avail.) | |
746 | * | |
747 | * LV* LV* GND GND 3.3 or x.xV as low as possible | |
748 | * | |
749 | * *LV means Low Voltage | |
750 | * | |
751 | * | |
752 | * That gives us the following table: | |
753 | * | |
754 | * Socket VS1 VS2 Voltage | |
755 | * | |
756 | * 5V NC NC 5V | |
757 | * 5V NC GND none (should not be possible) | |
758 | * 5V GND NC >= 3.3V | |
759 | * 5V GND GND >= x.xV | |
760 | * | |
761 | * LV NC NC 5V (if available) | |
762 | * LV NC GND x.xV (if available) | |
763 | * LV GND NC 3.3V | |
764 | * LV GND GND >= x.xV | |
765 | * | |
766 | * So, how do I determine if I have a 5V or a LV | |
767 | * socket on my board? Look at the socket! | |
768 | * | |
769 | * | |
770 | * Socket with 5V key: | |
771 | * ++--------------------------------------------+ | |
772 | * || | | |
773 | * || || | |
774 | * || || | |
775 | * | | | |
776 | * +---------------------------------------------+ | |
777 | * | |
778 | * Socket with LV key: | |
779 | * ++--------------------------------------------+ | |
780 | * || | | |
781 | * | || | |
782 | * | || | |
783 | * | | | |
784 | * +---------------------------------------------+ | |
785 | * | |
786 | * | |
787 | * With other words - LV only cards does not fit | |
788 | * into the 5V socket! | |
789 | */ | |
790 | ||
791 | /* read out VS1 and VS2 */ | |
792 | ||
793 | reg = (pipr & M8XX_PCMCIA_VS_MASK(lsock)) | |
99121c0d | 794 | >> M8XX_PCMCIA_VS_SHIFT(lsock); |
de957c89 | 795 | |
99121c0d VB |
796 | if (socket_get(lsock) == PCMCIA_SOCKET_KEY_LV) { |
797 | switch (reg) { | |
de957c89 MT |
798 | case 1: |
799 | *value |= SS_3VCARD; | |
99121c0d | 800 | break; /* GND, NC - 3.3V only */ |
de957c89 MT |
801 | case 2: |
802 | *value |= SS_XVCARD; | |
99121c0d | 803 | break; /* NC. GND - x.xV only */ |
de957c89 MT |
804 | }; |
805 | } | |
806 | ||
c9f50ddd | 807 | pr_debug("m8xx_pcmcia: GetStatus(%d) = %#2.2x\n", lsock, *value); |
de957c89 MT |
808 | return 0; |
809 | } | |
810 | ||
99121c0d | 811 | static int m8xx_set_socket(struct pcmcia_socket *sock, socket_state_t * state) |
de957c89 MT |
812 | { |
813 | int lsock = container_of(sock, struct socket_info, socket)->slot; | |
814 | struct socket_info *s = &socket[lsock]; | |
815 | struct event_table *e; | |
816 | unsigned int reg; | |
817 | unsigned long flags; | |
80128ff7 | 818 | pcmconf8xx_t *pcmcia = socket[0].pcmcia; |
de957c89 | 819 | |
c9f50ddd | 820 | pr_debug("m8xx_pcmcia: SetSocket(%d, flags %#3.3x, Vcc %d, Vpp %d, " |
99121c0d VB |
821 | "io_irq %d, csc_mask %#2.2x)\n", lsock, state->flags, |
822 | state->Vcc, state->Vpp, state->io_irq, state->csc_mask); | |
de957c89 MT |
823 | |
824 | /* First, set voltage - bail out if invalid */ | |
99121c0d | 825 | if (voltage_set(lsock, state->Vcc, state->Vpp)) |
de957c89 MT |
826 | return -EINVAL; |
827 | ||
828 | /* Take care of reset... */ | |
99121c0d VB |
829 | if (state->flags & SS_RESET) |
830 | out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) | M8XX_PGCRX_CXRESET); /* active high */ | |
de957c89 | 831 | else |
99121c0d VB |
832 | out_be32(M8XX_PGCRX(lsock), |
833 | in_be32(M8XX_PGCRX(lsock)) & ~M8XX_PGCRX_CXRESET); | |
de957c89 MT |
834 | |
835 | /* ... and output enable. */ | |
836 | ||
837 | /* The CxOE signal is connected to a 74541 on the ADS. | |
838 | I guess most other boards used the ADS as a reference. | |
839 | I tried to control the CxOE signal with SS_OUTPUT_ENA, | |
840 | but the reset signal seems connected via the 541. | |
841 | If the CxOE is left high are some signals tristated and | |
f26fc4e0 | 842 | no pullups are present -> the cards act weird. |
de957c89 MT |
843 | So right now the buffers are enabled if the power is on. */ |
844 | ||
99121c0d VB |
845 | if (state->Vcc || state->Vpp) |
846 | out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) & ~M8XX_PGCRX_CXOE); /* active low */ | |
de957c89 | 847 | else |
99121c0d VB |
848 | out_be32(M8XX_PGCRX(lsock), |
849 | in_be32(M8XX_PGCRX(lsock)) | M8XX_PGCRX_CXOE); | |
de957c89 MT |
850 | |
851 | /* | |
852 | * We'd better turn off interrupts before | |
853 | * we mess with the events-table.. | |
854 | */ | |
855 | ||
856 | spin_lock_irqsave(&events_lock, flags); | |
857 | ||
858 | /* | |
859 | * Play around with the interrupt mask to be able to | |
860 | * give the events the generic pcmcia driver wants us to. | |
861 | */ | |
862 | ||
863 | e = &s->events[0]; | |
864 | reg = 0; | |
865 | ||
99121c0d | 866 | if (state->csc_mask & SS_DETECT) { |
de957c89 MT |
867 | e->eventbit = SS_DETECT; |
868 | reg |= e->regbit = (M8XX_PCMCIA_CD2(lsock) | |
869 | | M8XX_PCMCIA_CD1(lsock)); | |
870 | e++; | |
871 | } | |
99121c0d | 872 | if (state->flags & SS_IOCARD) { |
de957c89 MT |
873 | /* |
874 | * I/O card | |
875 | */ | |
99121c0d | 876 | if (state->csc_mask & SS_STSCHG) { |
de957c89 MT |
877 | e->eventbit = SS_STSCHG; |
878 | reg |= e->regbit = M8XX_PCMCIA_BVD1(lsock); | |
879 | e++; | |
880 | } | |
881 | /* | |
882 | * If io_irq is non-zero we should enable irq. | |
883 | */ | |
99121c0d | 884 | if (state->io_irq) { |
80128ff7 | 885 | out_be32(M8XX_PGCRX(lsock), |
99121c0d VB |
886 | in_be32(M8XX_PGCRX(lsock)) | |
887 | mk_int_int_mask(s->hwirq) << 24); | |
de957c89 MT |
888 | /* |
889 | * Strange thing here: | |
890 | * The manual does not tell us which interrupt | |
891 | * the sources generate. | |
892 | * Anyhow, I found out that RDY_L generates IREQLVL. | |
893 | * | |
894 | * We use level triggerd interrupts, and they don't | |
895 | * have to be cleared in PSCR in the interrupt handler. | |
896 | */ | |
897 | reg |= M8XX_PCMCIA_RDY_L(lsock); | |
99121c0d VB |
898 | } else |
899 | out_be32(M8XX_PGCRX(lsock), | |
900 | in_be32(M8XX_PGCRX(lsock)) & 0x00ffffff); | |
901 | } else { | |
de957c89 MT |
902 | /* |
903 | * Memory card | |
904 | */ | |
99121c0d | 905 | if (state->csc_mask & SS_BATDEAD) { |
de957c89 MT |
906 | e->eventbit = SS_BATDEAD; |
907 | reg |= e->regbit = M8XX_PCMCIA_BVD1(lsock); | |
908 | e++; | |
909 | } | |
99121c0d | 910 | if (state->csc_mask & SS_BATWARN) { |
de957c89 MT |
911 | e->eventbit = SS_BATWARN; |
912 | reg |= e->regbit = M8XX_PCMCIA_BVD2(lsock); | |
913 | e++; | |
914 | } | |
915 | /* What should I trigger on - low/high,raise,fall? */ | |
99121c0d | 916 | if (state->csc_mask & SS_READY) { |
de957c89 | 917 | e->eventbit = SS_READY; |
99121c0d | 918 | reg |= e->regbit = 0; //?? |
de957c89 MT |
919 | e++; |
920 | } | |
921 | } | |
922 | ||
99121c0d | 923 | e->regbit = 0; /* terminate list */ |
de957c89 MT |
924 | |
925 | /* | |
926 | * Clear the status changed . | |
927 | * Port A and Port B share the same port. | |
928 | * Writing ones will clear the bits. | |
929 | */ | |
930 | ||
80128ff7 | 931 | out_be32(&pcmcia->pcmc_pscr, reg); |
de957c89 MT |
932 | |
933 | /* | |
934 | * Write the mask. | |
935 | * Port A and Port B share the same port. | |
936 | * Need for read-modify-write. | |
937 | * Ones will enable the interrupt. | |
938 | */ | |
939 | ||
99121c0d VB |
940 | reg |= |
941 | in_be32(&pcmcia-> | |
942 | pcmc_per) & (M8XX_PCMCIA_MASK(0) | M8XX_PCMCIA_MASK(1)); | |
80128ff7 | 943 | out_be32(&pcmcia->pcmc_per, reg); |
de957c89 MT |
944 | |
945 | spin_unlock_irqrestore(&events_lock, flags); | |
946 | ||
947 | /* copy the struct and modify the copy */ | |
948 | ||
949 | s->state = *state; | |
950 | ||
951 | return 0; | |
952 | } | |
953 | ||
954 | static int m8xx_set_io_map(struct pcmcia_socket *sock, struct pccard_io_map *io) | |
955 | { | |
956 | int lsock = container_of(sock, struct socket_info, socket)->slot; | |
957 | ||
958 | struct socket_info *s = &socket[lsock]; | |
959 | struct pcmcia_win *w; | |
960 | unsigned int reg, winnr; | |
80128ff7 VB |
961 | pcmconf8xx_t *pcmcia = s->pcmcia; |
962 | ||
de957c89 MT |
963 | #define M8XX_SIZE (io->stop - io->start + 1) |
964 | #define M8XX_BASE (PCMCIA_IO_WIN_BASE + io->start) | |
965 | ||
c9f50ddd | 966 | pr_debug("m8xx_pcmcia: SetIOMap(%d, %d, %#2.2x, %d ns, " |
5f784336 WS |
967 | "%#4.4llx-%#4.4llx)\n", lsock, io->map, io->flags, |
968 | io->speed, (unsigned long long)io->start, | |
969 | (unsigned long long)io->stop); | |
de957c89 MT |
970 | |
971 | if ((io->map >= PCMCIA_IO_WIN_NO) || (io->start > 0xffff) | |
972 | || (io->stop > 0xffff) || (io->stop < io->start)) | |
973 | return -EINVAL; | |
974 | ||
99121c0d | 975 | if ((reg = m8xx_get_graycode(M8XX_SIZE)) == -1) |
de957c89 MT |
976 | return -EINVAL; |
977 | ||
99121c0d | 978 | if (io->flags & MAP_ACTIVE) { |
de957c89 | 979 | |
c9f50ddd | 980 | pr_debug("m8xx_pcmcia: io->flags & MAP_ACTIVE\n"); |
de957c89 MT |
981 | |
982 | winnr = (PCMCIA_MEM_WIN_NO * PCMCIA_SOCKETS_NO) | |
99121c0d | 983 | + (lsock * PCMCIA_IO_WIN_NO) + io->map; |
de957c89 MT |
984 | |
985 | /* setup registers */ | |
986 | ||
99121c0d | 987 | w = (void *)&pcmcia->pcmc_pbr0; |
de957c89 MT |
988 | w += winnr; |
989 | ||
99121c0d | 990 | out_be32(&w->or, 0); /* turn off window first */ |
de957c89 MT |
991 | out_be32(&w->br, M8XX_BASE); |
992 | ||
993 | reg <<= 27; | |
99121c0d | 994 | reg |= M8XX_PCMCIA_POR_IO | (lsock << 2); |
de957c89 | 995 | |
80128ff7 | 996 | reg |= m8xx_get_speed(io->speed, 1, s->bus_freq); |
de957c89 | 997 | |
99121c0d | 998 | if (io->flags & MAP_WRPROT) |
de957c89 MT |
999 | reg |= M8XX_PCMCIA_POR_WRPROT; |
1000 | ||
99121c0d VB |
1001 | /*if(io->flags & (MAP_16BIT | MAP_AUTOSZ)) */ |
1002 | if (io->flags & MAP_16BIT) | |
de957c89 MT |
1003 | reg |= M8XX_PCMCIA_POR_16BIT; |
1004 | ||
99121c0d | 1005 | if (io->flags & MAP_ACTIVE) |
de957c89 MT |
1006 | reg |= M8XX_PCMCIA_POR_VALID; |
1007 | ||
1008 | out_be32(&w->or, reg); | |
1009 | ||
c9f50ddd DB |
1010 | pr_debug("m8xx_pcmcia: Socket %u: Mapped io window %u at " |
1011 | "%#8.8x, OR = %#8.8x.\n", lsock, io->map, w->br, w->or); | |
de957c89 MT |
1012 | } else { |
1013 | /* shutdown IO window */ | |
1014 | winnr = (PCMCIA_MEM_WIN_NO * PCMCIA_SOCKETS_NO) | |
99121c0d | 1015 | + (lsock * PCMCIA_IO_WIN_NO) + io->map; |
de957c89 MT |
1016 | |
1017 | /* setup registers */ | |
1018 | ||
99121c0d | 1019 | w = (void *)&pcmcia->pcmc_pbr0; |
de957c89 MT |
1020 | w += winnr; |
1021 | ||
99121c0d VB |
1022 | out_be32(&w->or, 0); /* turn off window */ |
1023 | out_be32(&w->br, 0); /* turn off base address */ | |
de957c89 | 1024 | |
c9f50ddd DB |
1025 | pr_debug("m8xx_pcmcia: Socket %u: Unmapped io window %u at " |
1026 | "%#8.8x, OR = %#8.8x.\n", lsock, io->map, w->br, w->or); | |
de957c89 MT |
1027 | } |
1028 | ||
1029 | /* copy the struct and modify the copy */ | |
1030 | s->io_win[io->map] = *io; | |
99121c0d | 1031 | s->io_win[io->map].flags &= (MAP_WRPROT | MAP_16BIT | MAP_ACTIVE); |
c9f50ddd | 1032 | pr_debug("m8xx_pcmcia: SetIOMap exit\n"); |
de957c89 MT |
1033 | |
1034 | return 0; | |
1035 | } | |
1036 | ||
99121c0d VB |
1037 | static int m8xx_set_mem_map(struct pcmcia_socket *sock, |
1038 | struct pccard_mem_map *mem) | |
de957c89 MT |
1039 | { |
1040 | int lsock = container_of(sock, struct socket_info, socket)->slot; | |
1041 | struct socket_info *s = &socket[lsock]; | |
1042 | struct pcmcia_win *w; | |
1043 | struct pccard_mem_map *old; | |
1044 | unsigned int reg, winnr; | |
80128ff7 | 1045 | pcmconf8xx_t *pcmcia = s->pcmcia; |
de957c89 | 1046 | |
c9f50ddd | 1047 | pr_debug("m8xx_pcmcia: SetMemMap(%d, %d, %#2.2x, %d ns, " |
5f784336 WS |
1048 | "%#5.5llx, %#5.5x)\n", lsock, mem->map, mem->flags, |
1049 | mem->speed, (unsigned long long)mem->static_start, | |
1050 | mem->card_start); | |
de957c89 MT |
1051 | |
1052 | if ((mem->map >= PCMCIA_MEM_WIN_NO) | |
99121c0d | 1053 | // || ((mem->s) >= PCMCIA_MEM_WIN_SIZE) |
de957c89 | 1054 | || (mem->card_start >= 0x04000000) |
99121c0d VB |
1055 | || (mem->static_start & 0xfff) /* 4KByte resolution */ |
1056 | ||(mem->card_start & 0xfff)) | |
de957c89 MT |
1057 | return -EINVAL; |
1058 | ||
99121c0d VB |
1059 | if ((reg = m8xx_get_graycode(PCMCIA_MEM_WIN_SIZE)) == -1) { |
1060 | printk("Cannot set size to 0x%08x.\n", PCMCIA_MEM_WIN_SIZE); | |
de957c89 MT |
1061 | return -EINVAL; |
1062 | } | |
1063 | reg <<= 27; | |
1064 | ||
1065 | winnr = (lsock * PCMCIA_MEM_WIN_NO) + mem->map; | |
1066 | ||
1067 | /* Setup the window in the pcmcia controller */ | |
1068 | ||
99121c0d | 1069 | w = (void *)&pcmcia->pcmc_pbr0; |
de957c89 MT |
1070 | w += winnr; |
1071 | ||
1072 | reg |= lsock << 2; | |
1073 | ||
80128ff7 | 1074 | reg |= m8xx_get_speed(mem->speed, 0, s->bus_freq); |
de957c89 | 1075 | |
99121c0d VB |
1076 | if (mem->flags & MAP_ATTRIB) |
1077 | reg |= M8XX_PCMCIA_POR_ATTRMEM; | |
de957c89 | 1078 | |
99121c0d | 1079 | if (mem->flags & MAP_WRPROT) |
de957c89 MT |
1080 | reg |= M8XX_PCMCIA_POR_WRPROT; |
1081 | ||
99121c0d | 1082 | if (mem->flags & MAP_16BIT) |
de957c89 MT |
1083 | reg |= M8XX_PCMCIA_POR_16BIT; |
1084 | ||
99121c0d | 1085 | if (mem->flags & MAP_ACTIVE) |
de957c89 MT |
1086 | reg |= M8XX_PCMCIA_POR_VALID; |
1087 | ||
1088 | out_be32(&w->or, reg); | |
1089 | ||
c9f50ddd | 1090 | pr_debug("m8xx_pcmcia: Socket %u: Mapped memory window %u at %#8.8x, " |
99121c0d | 1091 | "OR = %#8.8x.\n", lsock, mem->map, w->br, w->or); |
de957c89 | 1092 | |
99121c0d | 1093 | if (mem->flags & MAP_ACTIVE) { |
de957c89 MT |
1094 | /* get the new base address */ |
1095 | mem->static_start = PCMCIA_MEM_WIN_BASE + | |
99121c0d VB |
1096 | (PCMCIA_MEM_WIN_SIZE * winnr) |
1097 | + mem->card_start; | |
de957c89 MT |
1098 | } |
1099 | ||
c9f50ddd | 1100 | pr_debug("m8xx_pcmcia: SetMemMap(%d, %d, %#2.2x, %d ns, " |
5f784336 WS |
1101 | "%#5.5llx, %#5.5x)\n", lsock, mem->map, mem->flags, |
1102 | mem->speed, (unsigned long long)mem->static_start, | |
1103 | mem->card_start); | |
de957c89 MT |
1104 | |
1105 | /* copy the struct and modify the copy */ | |
1106 | ||
1107 | old = &s->mem_win[mem->map]; | |
1108 | ||
1109 | *old = *mem; | |
99121c0d | 1110 | old->flags &= (MAP_ATTRIB | MAP_WRPROT | MAP_16BIT | MAP_ACTIVE); |
de957c89 MT |
1111 | |
1112 | return 0; | |
1113 | } | |
1114 | ||
1115 | static int m8xx_sock_init(struct pcmcia_socket *sock) | |
1116 | { | |
1117 | int i; | |
1118 | pccard_io_map io = { 0, 0, 0, 0, 1 }; | |
1119 | pccard_mem_map mem = { 0, 0, 0, 0, 0, 0 }; | |
1120 | ||
c9f50ddd | 1121 | pr_debug("m8xx_pcmcia: sock_init(%d)\n", s); |
de957c89 MT |
1122 | |
1123 | m8xx_set_socket(sock, &dead_socket); | |
1124 | for (i = 0; i < PCMCIA_IO_WIN_NO; i++) { | |
1125 | io.map = i; | |
1126 | m8xx_set_io_map(sock, &io); | |
1127 | } | |
1128 | for (i = 0; i < PCMCIA_MEM_WIN_NO; i++) { | |
1129 | mem.map = i; | |
1130 | m8xx_set_mem_map(sock, &mem); | |
1131 | } | |
1132 | ||
1133 | return 0; | |
1134 | ||
1135 | } | |
1136 | ||
80128ff7 | 1137 | static int m8xx_sock_suspend(struct pcmcia_socket *sock) |
de957c89 MT |
1138 | { |
1139 | return m8xx_set_socket(sock, &dead_socket); | |
1140 | } | |
1141 | ||
1142 | static struct pccard_operations m8xx_services = { | |
99121c0d | 1143 | .init = m8xx_sock_init, |
80128ff7 | 1144 | .suspend = m8xx_sock_suspend, |
de957c89 | 1145 | .get_status = m8xx_get_status, |
de957c89 MT |
1146 | .set_socket = m8xx_set_socket, |
1147 | .set_io_map = m8xx_set_io_map, | |
1148 | .set_mem_map = m8xx_set_mem_map, | |
1149 | }; | |
1150 | ||
2dc11581 | 1151 | static int __init m8xx_probe(struct platform_device *ofdev, |
99121c0d | 1152 | const struct of_device_id *match) |
de957c89 MT |
1153 | { |
1154 | struct pcmcia_win *w; | |
80128ff7 VB |
1155 | unsigned int i, m, hwirq; |
1156 | pcmconf8xx_t *pcmcia; | |
1157 | int status; | |
2005ce35 | 1158 | struct device_node *np = ofdev->dev.of_node; |
de957c89 MT |
1159 | |
1160 | pcmcia_info("%s\n", version); | |
1161 | ||
80128ff7 | 1162 | pcmcia = of_iomap(np, 0); |
99121c0d | 1163 | if (pcmcia == NULL) |
80128ff7 VB |
1164 | return -EINVAL; |
1165 | ||
1166 | pcmcia_schlvl = irq_of_parse_and_map(np, 0); | |
99121c0d | 1167 | hwirq = irq_map[pcmcia_schlvl].hwirq; |
5a1c3e1a JL |
1168 | if (pcmcia_schlvl < 0) { |
1169 | iounmap(pcmcia); | |
80128ff7 | 1170 | return -EINVAL; |
5a1c3e1a | 1171 | } |
80128ff7 VB |
1172 | |
1173 | m8xx_pgcrx[0] = &pcmcia->pcmc_pgcra; | |
1174 | m8xx_pgcrx[1] = &pcmcia->pcmc_pgcrb; | |
1175 | ||
de957c89 | 1176 | pcmcia_info(PCMCIA_BOARD_MSG " using " PCMCIA_SLOT_MSG |
80128ff7 | 1177 | " with IRQ %u (%d). \n", pcmcia_schlvl, hwirq); |
de957c89 MT |
1178 | |
1179 | /* Configure Status change interrupt */ | |
1180 | ||
99121c0d VB |
1181 | if (request_irq(pcmcia_schlvl, m8xx_interrupt, IRQF_SHARED, |
1182 | driver_name, socket)) { | |
de957c89 MT |
1183 | pcmcia_error("Cannot allocate IRQ %u for SCHLVL!\n", |
1184 | pcmcia_schlvl); | |
5a1c3e1a | 1185 | iounmap(pcmcia); |
de957c89 MT |
1186 | return -1; |
1187 | } | |
1188 | ||
99121c0d | 1189 | w = (void *)&pcmcia->pcmc_pbr0; |
de957c89 | 1190 | |
99121c0d | 1191 | out_be32(&pcmcia->pcmc_pscr, M8XX_PCMCIA_MASK(0) | M8XX_PCMCIA_MASK(1)); |
80128ff7 | 1192 | clrbits32(&pcmcia->pcmc_per, M8XX_PCMCIA_MASK(0) | M8XX_PCMCIA_MASK(1)); |
de957c89 | 1193 | |
80128ff7 | 1194 | /* connect interrupt and disable CxOE */ |
de957c89 | 1195 | |
99121c0d VB |
1196 | out_be32(M8XX_PGCRX(0), |
1197 | M8XX_PGCRX_CXOE | (mk_int_int_mask(hwirq) << 16)); | |
1198 | out_be32(M8XX_PGCRX(1), | |
1199 | M8XX_PGCRX_CXOE | (mk_int_int_mask(hwirq) << 16)); | |
de957c89 | 1200 | |
80128ff7 | 1201 | /* intialize the fixed memory windows */ |
de957c89 | 1202 | |
99121c0d | 1203 | for (i = 0; i < PCMCIA_SOCKETS_NO; i++) { |
80128ff7 | 1204 | for (m = 0; m < PCMCIA_MEM_WIN_NO; m++) { |
de957c89 | 1205 | out_be32(&w->br, PCMCIA_MEM_WIN_BASE + |
99121c0d VB |
1206 | (PCMCIA_MEM_WIN_SIZE |
1207 | * (m + i * PCMCIA_MEM_WIN_NO))); | |
de957c89 | 1208 | |
99121c0d | 1209 | out_be32(&w->or, 0); /* set to not valid */ |
de957c89 MT |
1210 | |
1211 | w++; | |
1212 | } | |
1213 | } | |
1214 | ||
80128ff7 | 1215 | /* turn off voltage */ |
de957c89 MT |
1216 | voltage_set(0, 0, 0); |
1217 | voltage_set(1, 0, 0); | |
1218 | ||
80128ff7 | 1219 | /* Enable external hardware */ |
de957c89 MT |
1220 | hardware_enable(0); |
1221 | hardware_enable(1); | |
1222 | ||
99121c0d | 1223 | for (i = 0; i < PCMCIA_SOCKETS_NO; i++) { |
de957c89 MT |
1224 | socket[i].slot = i; |
1225 | socket[i].socket.owner = THIS_MODULE; | |
99121c0d VB |
1226 | socket[i].socket.features = |
1227 | SS_CAP_PCCARD | SS_CAP_MEM_ALIGN | SS_CAP_STATIC_MAP; | |
de957c89 MT |
1228 | socket[i].socket.irq_mask = 0x000; |
1229 | socket[i].socket.map_size = 0x1000; | |
1230 | socket[i].socket.io_offset = 0; | |
80128ff7 | 1231 | socket[i].socket.pci_irq = pcmcia_schlvl; |
de957c89 | 1232 | socket[i].socket.ops = &m8xx_services; |
4e8804ff | 1233 | socket[i].socket.resource_ops = &pccard_iodyn_ops; |
de957c89 | 1234 | socket[i].socket.cb_dev = NULL; |
80128ff7 VB |
1235 | socket[i].socket.dev.parent = &ofdev->dev; |
1236 | socket[i].pcmcia = pcmcia; | |
1237 | socket[i].bus_freq = ppc_proc_freq; | |
1238 | socket[i].hwirq = hwirq; | |
1239 | ||
de957c89 MT |
1240 | } |
1241 | ||
80128ff7 VB |
1242 | for (i = 0; i < PCMCIA_SOCKETS_NO; i++) { |
1243 | status = pcmcia_register_socket(&socket[i].socket); | |
1244 | if (status < 0) | |
1245 | pcmcia_error("Socket register failed\n"); | |
1246 | } | |
de957c89 MT |
1247 | |
1248 | return 0; | |
1249 | } | |
1250 | ||
2dc11581 | 1251 | static int m8xx_remove(struct platform_device *ofdev) |
de957c89 | 1252 | { |
80128ff7 VB |
1253 | u32 m, i; |
1254 | struct pcmcia_win *w; | |
1255 | pcmconf8xx_t *pcmcia = socket[0].pcmcia; | |
1256 | ||
1257 | for (i = 0; i < PCMCIA_SOCKETS_NO; i++) { | |
99121c0d | 1258 | w = (void *)&pcmcia->pcmc_pbr0; |
80128ff7 VB |
1259 | |
1260 | out_be32(&pcmcia->pcmc_pscr, M8XX_PCMCIA_MASK(i)); | |
1261 | out_be32(&pcmcia->pcmc_per, | |
99121c0d | 1262 | in_be32(&pcmcia->pcmc_per) & ~M8XX_PCMCIA_MASK(i)); |
de957c89 | 1263 | |
80128ff7 VB |
1264 | /* turn off interrupt and disable CxOE */ |
1265 | out_be32(M8XX_PGCRX(i), M8XX_PGCRX_CXOE); | |
1266 | ||
1267 | /* turn off memory windows */ | |
1268 | for (m = 0; m < PCMCIA_MEM_WIN_NO; m++) { | |
99121c0d | 1269 | out_be32(&w->or, 0); /* set to not valid */ |
80128ff7 VB |
1270 | w++; |
1271 | } | |
1272 | ||
1273 | /* turn off voltage */ | |
1274 | voltage_set(i, 0, 0); | |
1275 | ||
1276 | /* disable external hardware */ | |
1277 | hardware_disable(i); | |
1278 | } | |
de957c89 MT |
1279 | for (i = 0; i < PCMCIA_SOCKETS_NO; i++) |
1280 | pcmcia_unregister_socket(&socket[i].socket); | |
5a1c3e1a | 1281 | iounmap(pcmcia); |
de957c89 | 1282 | |
80128ff7 | 1283 | free_irq(pcmcia_schlvl, NULL); |
de957c89 | 1284 | |
80128ff7 VB |
1285 | return 0; |
1286 | } | |
1287 | ||
63c9a8b3 | 1288 | static const struct of_device_id m8xx_pcmcia_match[] = { |
80128ff7 | 1289 | { |
99121c0d VB |
1290 | .type = "pcmcia", |
1291 | .compatible = "fsl,pq-pcmcia", | |
1292 | }, | |
80128ff7 VB |
1293 | {}, |
1294 | }; | |
1295 | ||
1296 | MODULE_DEVICE_TABLE(of, m8xx_pcmcia_match); | |
1297 | ||
1298 | static struct of_platform_driver m8xx_pcmcia_driver = { | |
4018294b GL |
1299 | .driver = { |
1300 | .name = driver_name, | |
1301 | .owner = THIS_MODULE, | |
2005ce35 | 1302 | .of_match_table = m8xx_pcmcia_match, |
4018294b | 1303 | }, |
99121c0d VB |
1304 | .probe = m8xx_probe, |
1305 | .remove = m8xx_remove, | |
80128ff7 VB |
1306 | }; |
1307 | ||
1308 | static int __init m8xx_init(void) | |
1309 | { | |
1310 | return of_register_platform_driver(&m8xx_pcmcia_driver); | |
1311 | } | |
1312 | ||
1313 | static void __exit m8xx_exit(void) | |
1314 | { | |
1315 | of_unregister_platform_driver(&m8xx_pcmcia_driver); | |
de957c89 MT |
1316 | } |
1317 | ||
1318 | module_init(m8xx_init); | |
1319 | module_exit(m8xx_exit); |