Commit | Line | Data |
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59025887 VG |
1 | /* |
2 | * Samsung EXYNOS5 SoC series USB DRD PHY driver | |
3 | * | |
4 | * Phy provider for USB 3.0 DRD controller on Exynos5 SoC series | |
5 | * | |
6 | * Copyright (C) 2014 Samsung Electronics Co., Ltd. | |
7 | * Author: Vivek Gautam <gautam.vivek@samsung.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #include <linux/clk.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/io.h> | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/of.h> | |
20 | #include <linux/of_address.h> | |
21 | #include <linux/phy/phy.h> | |
22 | #include <linux/platform_device.h> | |
23 | #include <linux/mutex.h> | |
24 | #include <linux/mfd/syscon.h> | |
25 | #include <linux/mfd/syscon/exynos5-pmu.h> | |
26 | #include <linux/regmap.h> | |
27 | ||
28 | /* Exynos USB PHY registers */ | |
29 | #define EXYNOS5_FSEL_9MHZ6 0x0 | |
30 | #define EXYNOS5_FSEL_10MHZ 0x1 | |
31 | #define EXYNOS5_FSEL_12MHZ 0x2 | |
32 | #define EXYNOS5_FSEL_19MHZ2 0x3 | |
33 | #define EXYNOS5_FSEL_20MHZ 0x4 | |
34 | #define EXYNOS5_FSEL_24MHZ 0x5 | |
35 | #define EXYNOS5_FSEL_50MHZ 0x7 | |
36 | ||
37 | /* EXYNOS5: USB 3.0 DRD PHY registers */ | |
38 | #define EXYNOS5_DRD_LINKSYSTEM 0x04 | |
39 | ||
40 | #define LINKSYSTEM_FLADJ_MASK (0x3f << 1) | |
41 | #define LINKSYSTEM_FLADJ(_x) ((_x) << 1) | |
42 | #define LINKSYSTEM_XHCI_VERSION_CONTROL BIT(27) | |
43 | ||
44 | #define EXYNOS5_DRD_PHYUTMI 0x08 | |
45 | ||
46 | #define PHYUTMI_OTGDISABLE BIT(6) | |
47 | #define PHYUTMI_FORCESUSPEND BIT(1) | |
48 | #define PHYUTMI_FORCESLEEP BIT(0) | |
49 | ||
50 | #define EXYNOS5_DRD_PHYPIPE 0x0c | |
51 | ||
52 | #define EXYNOS5_DRD_PHYCLKRST 0x10 | |
53 | ||
54 | #define PHYCLKRST_EN_UTMISUSPEND BIT(31) | |
55 | ||
56 | #define PHYCLKRST_SSC_REFCLKSEL_MASK (0xff << 23) | |
57 | #define PHYCLKRST_SSC_REFCLKSEL(_x) ((_x) << 23) | |
58 | ||
59 | #define PHYCLKRST_SSC_RANGE_MASK (0x03 << 21) | |
60 | #define PHYCLKRST_SSC_RANGE(_x) ((_x) << 21) | |
61 | ||
62 | #define PHYCLKRST_SSC_EN BIT(20) | |
63 | #define PHYCLKRST_REF_SSP_EN BIT(19) | |
64 | #define PHYCLKRST_REF_CLKDIV2 BIT(18) | |
65 | ||
66 | #define PHYCLKRST_MPLL_MULTIPLIER_MASK (0x7f << 11) | |
67 | #define PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF (0x19 << 11) | |
68 | #define PHYCLKRST_MPLL_MULTIPLIER_50M_REF (0x32 << 11) | |
69 | #define PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF (0x68 << 11) | |
70 | #define PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF (0x7d << 11) | |
71 | #define PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF (0x02 << 11) | |
72 | ||
73 | #define PHYCLKRST_FSEL_UTMI_MASK (0x7 << 5) | |
74 | #define PHYCLKRST_FSEL_PIPE_MASK (0x7 << 8) | |
75 | #define PHYCLKRST_FSEL(_x) ((_x) << 5) | |
76 | #define PHYCLKRST_FSEL_PAD_100MHZ (0x27 << 5) | |
77 | #define PHYCLKRST_FSEL_PAD_24MHZ (0x2a << 5) | |
78 | #define PHYCLKRST_FSEL_PAD_20MHZ (0x31 << 5) | |
79 | #define PHYCLKRST_FSEL_PAD_19_2MHZ (0x38 << 5) | |
80 | ||
81 | #define PHYCLKRST_RETENABLEN BIT(4) | |
82 | ||
83 | #define PHYCLKRST_REFCLKSEL_MASK (0x03 << 2) | |
84 | #define PHYCLKRST_REFCLKSEL_PAD_REFCLK (0x2 << 2) | |
85 | #define PHYCLKRST_REFCLKSEL_EXT_REFCLK (0x3 << 2) | |
86 | ||
87 | #define PHYCLKRST_PORTRESET BIT(1) | |
88 | #define PHYCLKRST_COMMONONN BIT(0) | |
89 | ||
90 | #define EXYNOS5_DRD_PHYREG0 0x14 | |
91 | #define EXYNOS5_DRD_PHYREG1 0x18 | |
92 | ||
93 | #define EXYNOS5_DRD_PHYPARAM0 0x1c | |
94 | ||
95 | #define PHYPARAM0_REF_USE_PAD BIT(31) | |
96 | #define PHYPARAM0_REF_LOSLEVEL_MASK (0x1f << 26) | |
97 | #define PHYPARAM0_REF_LOSLEVEL (0x9 << 26) | |
98 | ||
99 | #define EXYNOS5_DRD_PHYPARAM1 0x20 | |
100 | ||
101 | #define PHYPARAM1_PCS_TXDEEMPH_MASK (0x1f << 0) | |
102 | #define PHYPARAM1_PCS_TXDEEMPH (0x1c) | |
103 | ||
104 | #define EXYNOS5_DRD_PHYTERM 0x24 | |
105 | ||
106 | #define EXYNOS5_DRD_PHYTEST 0x28 | |
107 | ||
108 | #define PHYTEST_POWERDOWN_SSP BIT(3) | |
109 | #define PHYTEST_POWERDOWN_HSP BIT(2) | |
110 | ||
111 | #define EXYNOS5_DRD_PHYADP 0x2c | |
112 | ||
113 | #define EXYNOS5_DRD_PHYUTMICLKSEL 0x30 | |
114 | ||
115 | #define PHYUTMICLKSEL_UTMI_CLKSEL BIT(2) | |
116 | ||
117 | #define EXYNOS5_DRD_PHYRESUME 0x34 | |
118 | #define EXYNOS5_DRD_LINKPORT 0x44 | |
119 | ||
120 | #define KHZ 1000 | |
121 | #define MHZ (KHZ * KHZ) | |
122 | ||
123 | enum exynos5_usbdrd_phy_id { | |
124 | EXYNOS5_DRDPHY_UTMI, | |
125 | EXYNOS5_DRDPHY_PIPE3, | |
126 | EXYNOS5_DRDPHYS_NUM, | |
127 | }; | |
128 | ||
129 | struct phy_usb_instance; | |
130 | struct exynos5_usbdrd_phy; | |
131 | ||
132 | struct exynos5_usbdrd_phy_config { | |
133 | u32 id; | |
134 | void (*phy_isol)(struct phy_usb_instance *inst, u32 on); | |
135 | void (*phy_init)(struct exynos5_usbdrd_phy *phy_drd); | |
136 | unsigned int (*set_refclk)(struct phy_usb_instance *inst); | |
137 | }; | |
138 | ||
139 | struct exynos5_usbdrd_phy_drvdata { | |
140 | const struct exynos5_usbdrd_phy_config *phy_cfg; | |
141 | u32 pmu_offset_usbdrd0_phy; | |
142 | u32 pmu_offset_usbdrd1_phy; | |
143 | }; | |
144 | ||
145 | /** | |
146 | * struct exynos5_usbdrd_phy - driver data for USB 3.0 PHY | |
147 | * @dev: pointer to device instance of this platform device | |
148 | * @reg_phy: usb phy controller register memory base | |
149 | * @clk: phy clock for register access | |
150 | * @drv_data: pointer to SoC level driver data structure | |
151 | * @phys[]: array for 'EXYNOS5_DRDPHYS_NUM' number of PHY | |
152 | * instances each with its 'phy' and 'phy_cfg'. | |
153 | * @extrefclk: frequency select settings when using 'separate | |
154 | * reference clocks' for SS and HS operations | |
155 | * @ref_clk: reference clock to PHY block from which PHY's | |
156 | * operational clocks are derived | |
157 | * @ref_rate: rate of above reference clock | |
158 | */ | |
159 | struct exynos5_usbdrd_phy { | |
160 | struct device *dev; | |
161 | void __iomem *reg_phy; | |
162 | struct clk *clk; | |
163 | const struct exynos5_usbdrd_phy_drvdata *drv_data; | |
164 | struct phy_usb_instance { | |
165 | struct phy *phy; | |
166 | u32 index; | |
167 | struct regmap *reg_pmu; | |
168 | u32 pmu_offset; | |
169 | const struct exynos5_usbdrd_phy_config *phy_cfg; | |
170 | } phys[EXYNOS5_DRDPHYS_NUM]; | |
171 | u32 extrefclk; | |
172 | struct clk *ref_clk; | |
173 | }; | |
174 | ||
175 | static inline | |
176 | struct exynos5_usbdrd_phy *to_usbdrd_phy(struct phy_usb_instance *inst) | |
177 | { | |
178 | return container_of((inst), struct exynos5_usbdrd_phy, | |
179 | phys[(inst)->index]); | |
180 | } | |
181 | ||
182 | /* | |
183 | * exynos5_rate_to_clk() converts the supplied clock rate to the value that | |
184 | * can be written to the phy register. | |
185 | */ | |
186 | static unsigned int exynos5_rate_to_clk(unsigned long rate, u32 *reg) | |
187 | { | |
188 | /* EXYNOS5_FSEL_MASK */ | |
189 | ||
190 | switch (rate) { | |
191 | case 9600 * KHZ: | |
192 | *reg = EXYNOS5_FSEL_9MHZ6; | |
193 | break; | |
194 | case 10 * MHZ: | |
195 | *reg = EXYNOS5_FSEL_10MHZ; | |
196 | break; | |
197 | case 12 * MHZ: | |
198 | *reg = EXYNOS5_FSEL_12MHZ; | |
199 | break; | |
200 | case 19200 * KHZ: | |
201 | *reg = EXYNOS5_FSEL_19MHZ2; | |
202 | break; | |
203 | case 20 * MHZ: | |
204 | *reg = EXYNOS5_FSEL_20MHZ; | |
205 | break; | |
206 | case 24 * MHZ: | |
207 | *reg = EXYNOS5_FSEL_24MHZ; | |
208 | break; | |
209 | case 50 * MHZ: | |
210 | *reg = EXYNOS5_FSEL_50MHZ; | |
211 | break; | |
212 | default: | |
213 | return -EINVAL; | |
214 | } | |
215 | ||
216 | return 0; | |
217 | } | |
218 | ||
219 | static void exynos5_usbdrd_phy_isol(struct phy_usb_instance *inst, | |
220 | unsigned int on) | |
221 | { | |
222 | unsigned int val; | |
223 | ||
224 | if (!inst->reg_pmu) | |
225 | return; | |
226 | ||
227 | val = on ? 0 : EXYNOS5_PHY_ENABLE; | |
228 | ||
229 | regmap_update_bits(inst->reg_pmu, inst->pmu_offset, | |
230 | EXYNOS5_PHY_ENABLE, val); | |
231 | } | |
232 | ||
233 | /* | |
234 | * Sets the pipe3 phy's clk as EXTREFCLK (XXTI) which is internal clock | |
235 | * from clock core. Further sets multiplier values and spread spectrum | |
236 | * clock settings for SuperSpeed operations. | |
237 | */ | |
238 | static unsigned int | |
239 | exynos5_usbdrd_pipe3_set_refclk(struct phy_usb_instance *inst) | |
240 | { | |
241 | static u32 reg; | |
242 | struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst); | |
243 | ||
244 | /* restore any previous reference clock settings */ | |
245 | reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST); | |
246 | ||
247 | /* Use EXTREFCLK as ref clock */ | |
248 | reg &= ~PHYCLKRST_REFCLKSEL_MASK; | |
249 | reg |= PHYCLKRST_REFCLKSEL_EXT_REFCLK; | |
250 | ||
251 | /* FSEL settings corresponding to reference clock */ | |
252 | reg &= ~PHYCLKRST_FSEL_PIPE_MASK | | |
253 | PHYCLKRST_MPLL_MULTIPLIER_MASK | | |
254 | PHYCLKRST_SSC_REFCLKSEL_MASK; | |
255 | switch (phy_drd->extrefclk) { | |
256 | case EXYNOS5_FSEL_50MHZ: | |
257 | reg |= (PHYCLKRST_MPLL_MULTIPLIER_50M_REF | | |
258 | PHYCLKRST_SSC_REFCLKSEL(0x00)); | |
259 | break; | |
260 | case EXYNOS5_FSEL_24MHZ: | |
261 | reg |= (PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF | | |
262 | PHYCLKRST_SSC_REFCLKSEL(0x88)); | |
263 | break; | |
264 | case EXYNOS5_FSEL_20MHZ: | |
265 | reg |= (PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF | | |
266 | PHYCLKRST_SSC_REFCLKSEL(0x00)); | |
267 | break; | |
268 | case EXYNOS5_FSEL_19MHZ2: | |
269 | reg |= (PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF | | |
270 | PHYCLKRST_SSC_REFCLKSEL(0x88)); | |
271 | break; | |
272 | default: | |
273 | dev_dbg(phy_drd->dev, "unsupported ref clk\n"); | |
274 | break; | |
275 | } | |
276 | ||
277 | return reg; | |
278 | } | |
279 | ||
280 | /* | |
281 | * Sets the utmi phy's clk as EXTREFCLK (XXTI) which is internal clock | |
282 | * from clock core. Further sets the FSEL values for HighSpeed operations. | |
283 | */ | |
284 | static unsigned int | |
285 | exynos5_usbdrd_utmi_set_refclk(struct phy_usb_instance *inst) | |
286 | { | |
287 | static u32 reg; | |
288 | struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst); | |
289 | ||
290 | /* restore any previous reference clock settings */ | |
291 | reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST); | |
292 | ||
293 | reg &= ~PHYCLKRST_REFCLKSEL_MASK; | |
294 | reg |= PHYCLKRST_REFCLKSEL_EXT_REFCLK; | |
295 | ||
296 | reg &= ~PHYCLKRST_FSEL_UTMI_MASK | | |
297 | PHYCLKRST_MPLL_MULTIPLIER_MASK | | |
298 | PHYCLKRST_SSC_REFCLKSEL_MASK; | |
299 | reg |= PHYCLKRST_FSEL(phy_drd->extrefclk); | |
300 | ||
301 | return reg; | |
302 | } | |
303 | ||
304 | static void exynos5_usbdrd_pipe3_init(struct exynos5_usbdrd_phy *phy_drd) | |
305 | { | |
306 | u32 reg; | |
307 | ||
308 | reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1); | |
309 | /* Set Tx De-Emphasis level */ | |
310 | reg &= ~PHYPARAM1_PCS_TXDEEMPH_MASK; | |
311 | reg |= PHYPARAM1_PCS_TXDEEMPH; | |
312 | writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1); | |
313 | ||
314 | reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST); | |
315 | reg &= ~PHYTEST_POWERDOWN_SSP; | |
316 | writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST); | |
317 | } | |
318 | ||
319 | static void exynos5_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd) | |
320 | { | |
321 | u32 reg; | |
322 | ||
323 | reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0); | |
324 | /* Set Loss-of-Signal Detector sensitivity */ | |
325 | reg &= ~PHYPARAM0_REF_LOSLEVEL_MASK; | |
326 | reg |= PHYPARAM0_REF_LOSLEVEL; | |
327 | writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0); | |
328 | ||
329 | reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1); | |
330 | /* Set Tx De-Emphasis level */ | |
331 | reg &= ~PHYPARAM1_PCS_TXDEEMPH_MASK; | |
332 | reg |= PHYPARAM1_PCS_TXDEEMPH; | |
333 | writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1); | |
334 | ||
335 | /* UTMI Power Control */ | |
336 | writel(PHYUTMI_OTGDISABLE, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMI); | |
337 | ||
338 | reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST); | |
339 | reg &= ~PHYTEST_POWERDOWN_HSP; | |
340 | writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST); | |
341 | } | |
342 | ||
343 | static int exynos5_usbdrd_phy_init(struct phy *phy) | |
344 | { | |
345 | int ret; | |
346 | u32 reg; | |
347 | struct phy_usb_instance *inst = phy_get_drvdata(phy); | |
348 | struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst); | |
349 | ||
350 | ret = clk_prepare_enable(phy_drd->clk); | |
351 | if (ret) | |
352 | return ret; | |
353 | ||
354 | /* Reset USB 3.0 PHY */ | |
355 | writel(0x0, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0); | |
356 | writel(0x0, phy_drd->reg_phy + EXYNOS5_DRD_PHYRESUME); | |
357 | ||
358 | /* | |
359 | * Setting the Frame length Adj value[6:1] to default 0x20 | |
360 | * See xHCI 1.0 spec, 5.2.4 | |
361 | */ | |
362 | reg = LINKSYSTEM_XHCI_VERSION_CONTROL | | |
363 | LINKSYSTEM_FLADJ(0x20); | |
364 | writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_LINKSYSTEM); | |
365 | ||
366 | reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0); | |
367 | /* Select PHY CLK source */ | |
368 | reg &= ~PHYPARAM0_REF_USE_PAD; | |
369 | writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0); | |
370 | ||
371 | /* This bit must be set for both HS and SS operations */ | |
372 | reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMICLKSEL); | |
373 | reg |= PHYUTMICLKSEL_UTMI_CLKSEL; | |
374 | writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMICLKSEL); | |
375 | ||
376 | /* UTMI or PIPE3 specific init */ | |
377 | inst->phy_cfg->phy_init(phy_drd); | |
378 | ||
379 | /* reference clock settings */ | |
380 | reg = inst->phy_cfg->set_refclk(inst); | |
381 | ||
382 | /* Digital power supply in normal operating mode */ | |
383 | reg |= PHYCLKRST_RETENABLEN | | |
384 | /* Enable ref clock for SS function */ | |
385 | PHYCLKRST_REF_SSP_EN | | |
386 | /* Enable spread spectrum */ | |
387 | PHYCLKRST_SSC_EN | | |
388 | /* Power down HS Bias and PLL blocks in suspend mode */ | |
389 | PHYCLKRST_COMMONONN | | |
390 | /* Reset the port */ | |
391 | PHYCLKRST_PORTRESET; | |
392 | ||
393 | writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST); | |
394 | ||
395 | udelay(10); | |
396 | ||
397 | reg &= ~PHYCLKRST_PORTRESET; | |
398 | writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST); | |
399 | ||
400 | clk_disable_unprepare(phy_drd->clk); | |
401 | ||
402 | return 0; | |
403 | } | |
404 | ||
405 | static int exynos5_usbdrd_phy_exit(struct phy *phy) | |
406 | { | |
407 | int ret; | |
408 | u32 reg; | |
409 | struct phy_usb_instance *inst = phy_get_drvdata(phy); | |
410 | struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst); | |
411 | ||
412 | ret = clk_prepare_enable(phy_drd->clk); | |
413 | if (ret) | |
414 | return ret; | |
415 | ||
416 | reg = PHYUTMI_OTGDISABLE | | |
417 | PHYUTMI_FORCESUSPEND | | |
418 | PHYUTMI_FORCESLEEP; | |
419 | writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMI); | |
420 | ||
421 | /* Resetting the PHYCLKRST enable bits to reduce leakage current */ | |
422 | reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST); | |
423 | reg &= ~(PHYCLKRST_REF_SSP_EN | | |
424 | PHYCLKRST_SSC_EN | | |
425 | PHYCLKRST_COMMONONN); | |
426 | writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST); | |
427 | ||
428 | /* Control PHYTEST to remove leakage current */ | |
429 | reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST); | |
430 | reg |= PHYTEST_POWERDOWN_SSP | | |
431 | PHYTEST_POWERDOWN_HSP; | |
432 | writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST); | |
433 | ||
434 | clk_disable_unprepare(phy_drd->clk); | |
435 | ||
436 | return 0; | |
437 | } | |
438 | ||
439 | static int exynos5_usbdrd_phy_power_on(struct phy *phy) | |
440 | { | |
441 | struct phy_usb_instance *inst = phy_get_drvdata(phy); | |
442 | struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst); | |
443 | ||
444 | dev_dbg(phy_drd->dev, "Request to power_on usbdrd_phy phy\n"); | |
445 | ||
446 | clk_prepare_enable(phy_drd->ref_clk); | |
447 | ||
448 | /* Power-on PHY*/ | |
449 | inst->phy_cfg->phy_isol(inst, 0); | |
450 | ||
451 | return 0; | |
452 | } | |
453 | ||
454 | static int exynos5_usbdrd_phy_power_off(struct phy *phy) | |
455 | { | |
456 | struct phy_usb_instance *inst = phy_get_drvdata(phy); | |
457 | struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst); | |
458 | ||
459 | dev_dbg(phy_drd->dev, "Request to power_off usbdrd_phy phy\n"); | |
460 | ||
461 | /* Power-off the PHY */ | |
462 | inst->phy_cfg->phy_isol(inst, 1); | |
463 | ||
464 | clk_disable_unprepare(phy_drd->ref_clk); | |
465 | ||
466 | return 0; | |
467 | } | |
468 | ||
469 | static struct phy *exynos5_usbdrd_phy_xlate(struct device *dev, | |
470 | struct of_phandle_args *args) | |
471 | { | |
472 | struct exynos5_usbdrd_phy *phy_drd = dev_get_drvdata(dev); | |
473 | ||
474 | if (WARN_ON(args->args[0] > EXYNOS5_DRDPHYS_NUM)) | |
475 | return ERR_PTR(-ENODEV); | |
476 | ||
477 | return phy_drd->phys[args->args[0]].phy; | |
478 | } | |
479 | ||
480 | static struct phy_ops exynos5_usbdrd_phy_ops = { | |
481 | .init = exynos5_usbdrd_phy_init, | |
482 | .exit = exynos5_usbdrd_phy_exit, | |
483 | .power_on = exynos5_usbdrd_phy_power_on, | |
484 | .power_off = exynos5_usbdrd_phy_power_off, | |
485 | .owner = THIS_MODULE, | |
486 | }; | |
487 | ||
488 | const struct exynos5_usbdrd_phy_config phy_cfg_exynos5[] = { | |
489 | { | |
490 | .id = EXYNOS5_DRDPHY_UTMI, | |
491 | .phy_isol = exynos5_usbdrd_phy_isol, | |
492 | .phy_init = exynos5_usbdrd_utmi_init, | |
493 | .set_refclk = exynos5_usbdrd_utmi_set_refclk, | |
494 | }, | |
495 | { | |
496 | .id = EXYNOS5_DRDPHY_PIPE3, | |
497 | .phy_isol = exynos5_usbdrd_phy_isol, | |
498 | .phy_init = exynos5_usbdrd_pipe3_init, | |
499 | .set_refclk = exynos5_usbdrd_pipe3_set_refclk, | |
500 | }, | |
501 | }; | |
502 | ||
503 | const struct exynos5_usbdrd_phy_drvdata exynos5420_usbdrd_phy = { | |
504 | .phy_cfg = phy_cfg_exynos5, | |
505 | .pmu_offset_usbdrd0_phy = EXYNOS5_USBDRD_PHY_CONTROL, | |
506 | .pmu_offset_usbdrd1_phy = EXYNOS5420_USBDRD1_PHY_CONTROL, | |
507 | }; | |
508 | ||
509 | const struct exynos5_usbdrd_phy_drvdata exynos5250_usbdrd_phy = { | |
510 | .phy_cfg = phy_cfg_exynos5, | |
511 | .pmu_offset_usbdrd0_phy = EXYNOS5_USBDRD_PHY_CONTROL, | |
512 | }; | |
513 | ||
514 | static const struct of_device_id exynos5_usbdrd_phy_of_match[] = { | |
515 | { | |
516 | .compatible = "samsung,exynos5250-usbdrd-phy", | |
517 | .data = &exynos5250_usbdrd_phy | |
518 | }, { | |
519 | .compatible = "samsung,exynos5420-usbdrd-phy", | |
520 | .data = &exynos5420_usbdrd_phy | |
521 | }, | |
522 | { }, | |
523 | }; | |
524 | ||
525 | static int exynos5_usbdrd_phy_probe(struct platform_device *pdev) | |
526 | { | |
527 | struct device *dev = &pdev->dev; | |
528 | struct device_node *node = dev->of_node; | |
529 | struct exynos5_usbdrd_phy *phy_drd; | |
530 | struct phy_provider *phy_provider; | |
531 | struct resource *res; | |
532 | const struct of_device_id *match; | |
533 | const struct exynos5_usbdrd_phy_drvdata *drv_data; | |
534 | struct regmap *reg_pmu; | |
535 | u32 pmu_offset; | |
536 | unsigned long ref_rate; | |
537 | int i, ret; | |
538 | int channel; | |
539 | ||
540 | phy_drd = devm_kzalloc(dev, sizeof(*phy_drd), GFP_KERNEL); | |
541 | if (!phy_drd) | |
542 | return -ENOMEM; | |
543 | ||
544 | dev_set_drvdata(dev, phy_drd); | |
545 | phy_drd->dev = dev; | |
546 | ||
547 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
548 | phy_drd->reg_phy = devm_ioremap_resource(dev, res); | |
549 | if (IS_ERR(phy_drd->reg_phy)) | |
550 | return PTR_ERR(phy_drd->reg_phy); | |
551 | ||
552 | match = of_match_node(exynos5_usbdrd_phy_of_match, pdev->dev.of_node); | |
553 | ||
554 | drv_data = match->data; | |
555 | phy_drd->drv_data = drv_data; | |
556 | ||
557 | phy_drd->clk = devm_clk_get(dev, "phy"); | |
558 | if (IS_ERR(phy_drd->clk)) { | |
559 | dev_err(dev, "Failed to get clock of phy controller\n"); | |
560 | return PTR_ERR(phy_drd->clk); | |
561 | } | |
562 | ||
563 | phy_drd->ref_clk = devm_clk_get(dev, "ref"); | |
564 | if (IS_ERR(phy_drd->ref_clk)) { | |
565 | dev_err(dev, "Failed to get reference clock of usbdrd phy\n"); | |
566 | return PTR_ERR(phy_drd->ref_clk); | |
567 | } | |
568 | ref_rate = clk_get_rate(phy_drd->ref_clk); | |
569 | ||
570 | ret = exynos5_rate_to_clk(ref_rate, &phy_drd->extrefclk); | |
571 | if (ret) { | |
572 | dev_err(phy_drd->dev, "Clock rate (%ld) not supported\n", | |
573 | ref_rate); | |
574 | return ret; | |
575 | } | |
576 | ||
577 | reg_pmu = syscon_regmap_lookup_by_phandle(dev->of_node, | |
578 | "samsung,pmu-syscon"); | |
579 | if (IS_ERR(reg_pmu)) { | |
580 | dev_err(dev, "Failed to lookup PMU regmap\n"); | |
581 | return PTR_ERR(reg_pmu); | |
582 | } | |
583 | ||
584 | /* | |
585 | * Exynos5420 SoC has multiple channels for USB 3.0 PHY, with | |
586 | * each having separate power control registers. | |
587 | * 'channel' facilitates to set such registers. | |
588 | */ | |
589 | channel = of_alias_get_id(node, "usbdrdphy"); | |
590 | if (channel < 0) | |
591 | dev_dbg(dev, "Not a multi-controller usbdrd phy\n"); | |
592 | ||
593 | switch (channel) { | |
594 | case 1: | |
595 | pmu_offset = phy_drd->drv_data->pmu_offset_usbdrd1_phy; | |
596 | break; | |
597 | case 0: | |
598 | default: | |
599 | pmu_offset = phy_drd->drv_data->pmu_offset_usbdrd0_phy; | |
600 | break; | |
601 | } | |
602 | ||
603 | dev_vdbg(dev, "Creating usbdrd_phy phy\n"); | |
604 | ||
605 | for (i = 0; i < EXYNOS5_DRDPHYS_NUM; i++) { | |
606 | struct phy *phy = devm_phy_create(dev, &exynos5_usbdrd_phy_ops, | |
607 | NULL); | |
608 | if (IS_ERR(phy)) { | |
609 | dev_err(dev, "Failed to create usbdrd_phy phy\n"); | |
610 | return PTR_ERR(phy); | |
611 | } | |
612 | ||
613 | phy_drd->phys[i].phy = phy; | |
614 | phy_drd->phys[i].index = i; | |
615 | phy_drd->phys[i].reg_pmu = reg_pmu; | |
616 | phy_drd->phys[i].pmu_offset = pmu_offset; | |
617 | phy_drd->phys[i].phy_cfg = &drv_data->phy_cfg[i]; | |
618 | phy_set_drvdata(phy, &phy_drd->phys[i]); | |
619 | } | |
620 | ||
621 | phy_provider = devm_of_phy_provider_register(dev, | |
622 | exynos5_usbdrd_phy_xlate); | |
623 | if (IS_ERR(phy_provider)) { | |
624 | dev_err(phy_drd->dev, "Failed to register phy provider\n"); | |
625 | return PTR_ERR(phy_provider); | |
626 | } | |
627 | ||
628 | return 0; | |
629 | } | |
630 | ||
631 | static struct platform_driver exynos5_usb3drd_phy = { | |
632 | .probe = exynos5_usbdrd_phy_probe, | |
633 | .driver = { | |
634 | .of_match_table = exynos5_usbdrd_phy_of_match, | |
635 | .name = "exynos5_usb3drd_phy", | |
636 | .owner = THIS_MODULE, | |
637 | } | |
638 | }; | |
639 | ||
640 | module_platform_driver(exynos5_usb3drd_phy); | |
641 | MODULE_DESCRIPTION("Samsung EXYNOS5 SoCs USB 3.0 DRD controller PHY driver"); | |
642 | MODULE_AUTHOR("Vivek Gautam <gautam.vivek@samsung.com>"); | |
643 | MODULE_LICENSE("GPL v2"); | |
644 | MODULE_ALIAS("platform:exynos5_usb3drd_phy"); |